WEDC EDI8L24128C12BI 128kx24 asynchronous sram, 5v Datasheet

EDI8L24128C
White Electronic Designs
128Kx24 Asynchronous SRAM, 5V
FEATURES
DESCRIPTION
 128Kx24 bit CMOS Static
The EDI8L24128CxxBC is a 5V, three megabit SRAM
constructed with three 128Kx8 die mounted on a multilayer laminate substrate. With 12 to 15ns access times, x24
width and a 5V operating voltage, the EDI8L2418C is ideal
for creating a single chip memory solution for the Motorola
DSP5600x or a two chip solution for the Analog Devices
SHARC™ DSP.
 Random Access Memory Array
 Fast Access Times: 12 and 15ns
 Master Output Enable and Write Control
 TTL Compatible Inputs and Outputs
 Fully Static, No Clocks
Surface Mount Package

 119 Lead BGA (JEDEC MO-163), No. 391
 Small Footprint, 14mm x 22mm
 Multiple Ground Pins for Maximum Noise
Immunity
The JEDEC Standard 119 lead BGA provides a 44% space
savings over using 128Kx8, 300mm wide SOJs and the
BGA package has a height of 100mm compared to 148mm
for the SOJ packages.
Single +5V (±10%) Supply Operation

DSP Memory Solution

The single or dual chip memory solutions offer improved
system performance by reducing the length of board traces
and the number of board connections compared to using
multiple monolithic devices. For example, the capacitance
load on the data lines for the BGA package is 58% less than
a monolithic SOJ solution.
 Motorola DSP5600x™
 Analog Devices SHARC™
FIG. 1 PIN CONFIGURATION
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
1
NC
NC
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
NC
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
NC
NC
2
A0
A5
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NC
A9
A13
3
A1
A6
NC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
NC
A10
A14
4
A2
E
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
W
G
5
A3
A7
NC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
NC
A11
A15
6
A4
A8
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NC
A12
A16
Pin DESCRIPTION
7
NC
NC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
NC
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
NC
NC
A0-16
E#
W#
G3
DQ0-23
VCC
GND
NC
A0-A16
G#
W#
E#
Address Inputs
Chip Enables
Master Write Enable
Master Output Enable
Common Data
Input/Output
Power (+5V±10%)
Ground
No Connection
128K x 24
Memory
Array
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2002
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI8L24128C
White Electronic Designs
Recommended Operating Conditions
Absolute Maximum Ratings*
Voltage on any pin relative to VSS
Operating Temperature TS (Ambient)
Commercial
Industrial
Storage Temperature
Power Dissipation
Output Current.
Junction Temperature, TJ
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
-0.5V to 7.0V
0°C to + 70°C
-40°C to +85°C
-55°C to +125°C
3 Watts
20 mA
175°C
G#
X
H
L
X
Mode
Standby
Output Deselect
Read
Write
Output
High Z
High Z
Data Out
Data In
Typ
5.0
0
—
—
Max
5.5
0
VCC+0.3
+0.8
Units
V
V
V
V
(f=1.0MHZ, VIN=VCC OR VSS)
Parameter
Address Lines
Data Lines
Write & Output Enable Line
Chip Enable Lines
Truth Table
W#
X
H
H
L
Min
4.5
0
2.2
-0.3
Capacitance
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
E#
H
L
L
L
Symbol
VCC
VSS
VIH
VIL
Power
ICC2, ICC3
ICC1
ICC1
ICC1
Symbol
CL
CD/Q
W#, G#
E#
Max
8
10
8
8
Unit
pf
pf
pf
pf
DC Electrical Characteristics
(Vcc = 5V, TA = 25°C)
Parameter
Operating Power Supply Current
Standby (TTL) Power Supply Current
Symbol
ICC1
ICC2
Full Standby Power CMOS
Supply Current
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ICC3
Conditions
W# = VIL, II/O = 0mA, Min Cycle
E#  VIH, VIN  VIL or VIN  VIH,
f = 0MHz
E#  VCC -0.2V
VIN  VCC -0.2V or VIN  0.2V
VIN = 0V to VCC
VI/O 0V to VCC
IOH = -4.0mA
IOL = 8.0mA
ILI
ILO
VOH
VOL
—
Min
200
—
—
2.4
—
Type
270
45
±10
—
—
—
Max
mA
mA
Units
10
mA
µA
±10
—
0.4
µA
V
V
AC Test Conditions
Fig. 1
Fig. 2
Vcc
RL= 50Ω
Z0= 50Ω
480Ω
DOUT
DOUT
VL=1.5V
255Ω
5pf
30pf
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Levels
Output Load
VSS to 3.0V
5ns
1.5V
Figure 1
Note: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2002
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI8L24128C
White Electronic Designs
AC Characteristics Read Cycle
Parameter
Symbol
JEDEC
tAVAV
tAVQV
tELQV
tELQX
tEHQZ
tAVQX
tGLQV
tGLQX
tGHQZ
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z1
Chip Disable to Output in High Z1
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z1
Output Disable to Output in High Z1
12ns
Alt.
tRC
tAA
tACS
tCLZ
tCHZ
tOH
tOE
tOLZ
tOHZ
Min
12
15ns
Max
Min
15
12
12
3
Units
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
3
6
3
7
3
6
0
7
0
6
7
1. This parameter is guaranteed by design but not tested.
AC Characteristics Write Cycle
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z1
Data to Write Time
Output Active from End of Write1
Symbol
JEDEC
tAVAV
tELWH
tELEH
tAVWL
tAVEL
tAVWH
tAVEH
tWLWH
tELEH
tWHAX
tEHAX
tWHDX
tEHDX
tWLQZ
tDVWH
tDVEH
tWHQX
12ns
Alt.
tWC
tCW
tCW
tAS
tAS
tAW
tAW
tWP
tWP
tWR
tWR
tDH
tDH
tWHZ
tDW
tDW
tWLZ
Min
12
9
9
0
0
9
9
10
10
0
0
0
0
0
6
6
3
15ns
Max
6
Min
15
9
9
0
0
10
10
11
11
0
0
0
0
0
7
7
3
Units
Max
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2002
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI8L24128C
White Electronic Designs
FIG. 2
TIMING WAVEFORM — READ CYCLE
tAVAV
A
tAVQV
E#
tAVAV
A
tELQV
ADDRESS 1
ADDRESS 2
tAVQV
tAVQX
tEHQZ
tELQX
G#
Q
tGLQV
tGHQZ
tGLQX
DATA 2
DATA 1
Q
Read Cycle 1 (W# High; G, E Low)
Read Cycle 2 (W# High)
FIG. 3
WRITE CYCLE — W# CONTROLLED
tAVAV
A
E#
tELWH
tWHAX
tAVWH
tWLWH
W#
tAVWL
tDVWH
D
tWHDX
DATA VALID
tWHQX
tWLQZ
HIGH Z
Q
FIG. 4
WRITE CYCLE — E# CONTROLLED
tAVAV
A
tAVEL
tELEH
E#
tAVEH
tEHAX
tWLEH
W#
tDVEH
D
Q
tEHDX
DATA VALID
HIGH Z
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2002
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI8L24128C
White Electronic Designs
PACKAGE 391:
119 LEAD BGA JEDEC MO-163
PIN 1
INDEX
0.866
BSC
0.551
BSC
0.110
MAX.
R.060 MAX.
(4x)
0.800
BSC
0.050
TYP
0.028
MAX.
0.300
BSC
ALL DIMENSIONS ARE IN INCHES
ORDERING INFORMATION
Commercial (0°C to +70°C)
Part Number
EDI8L24128C12BC
EDI8L24128C15BC
Speed
(ns)
12
15
Industrial (-40°C to +85°C)
Package
No.
391
391
Part Number
EDI8L24128C12BI
EDI8L24128C15BI
Speed
(ns)
12
15
Package
No.
391
391
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2002
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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