WEDC EDI8L24129V12BI 128kx24 sram 3.3 volt Datasheet

White Electronic Designs
EDI8L24129V
128Kx24 SRAM 3.3 Volt
FEATURES
DESCRIPTION
128Kx24 bit CMOS Static
Random Access Memory Array
The EDI8L24129VxxBC is a 3.3V, three megabit SRAM
constructed with three 128Kx8 die mounted on a multilayer laminate substrate. With 10 to 15ns access times,
x24 width and a 3.3V operating voltage, the EDI8L24129V
is ideal for creating a single chip memory solution for the
Motorola DSP5630x (Figure 3) or a two chip solution for
the Analog Devices SHARCTM DSP (Figure 4).
• Fast Access Times: 10, 12, and 15ns
• Master Output Enable and Write Control
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
The single or dual chip memory solutions offer improved
system performance by reducing the length of board traces
and the number of board connections compared to using
multiple monolithic devices. For example, the capacitance
load on the data lines for the BGA package is 58% less
than a monolithic SOJ solution.
Surface Mount Package
• 119 Lead BGA (JEDEC MO-163), No. 391
• Small Footprint, 14mm x 22mm
• Multiple Ground Pins for Maximum
Noise Immunity
Single +3.3V (±5%) Supply Operation
DSP Memory Solution
Motorola DSP5630xTM
Analog Devices SHARCTM
The JEDEC Standard 119 lead BGA provides a 44% space
savings over using 128Kx8, 300mil wide SOJs and the BGA
package has a maximum height of 100 mils compared to
148 mils for the SOJ packages. The BGA package also
allows the use of the same manufacturing and inspection
techniques as the Motorola DSP, which is also in a BGA
package.
PIN CONFIGURATION
PIN NAMES
1
NC
2
AO
3
A1
4
A2
5
A3
6
A4
7
NC
AØ-A16
A
E#
Chip Enable
B
NC
A5
A6
E#
A7
A8
NC
W#
Master Write Enable
C
I/012
NC
NC
NC
NC
NC
I/00
G#
Master Output Enable
D
I/013
VCC
GND
GND
GND
VCC
I/01
DQØ-DQ23
E
I/014
GND
VCC
GND
VCC
GND
I/02
F
I/015
VCC
GND
GND
GND
VCC
I/03
G
I/016
GND
VCC
GND
VCC
GND
I/04
H
I/017
VCC
GND
GND
GND
VCC
I/05
I
NC
GND
VCC
GND
VCC
GND
NC
J
I/018
VCC
GND
GND
GND
VCC
I/06
K
I/019
GND
VCC
GND
VCC
GND
I/07
L
I/020
VCC
GND
GND
GND
VCC
I/08
M
I/021
GND
VCC
GND
VCC
GND
I/09
N
I/022
VCC
GND
GND
GND
VCC
I/010
O
I/023
NC
NC
NC
NC
NC
I/011
P
NC
A9
A10
W#
A11
A12
NC
Q
NC
A13
A14
G#
A15
A16
NC
Address Inputs
Common Data Input/Output
VCC
Power (3.3V±5%)
GND
Ground
NC
No Connection
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March 2005
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White Electronic Designs
EDI8L24129V
BLOCK DIAGRAM
A0-A16
G#
W#
E#
17
128K x 24
Memory
Array
ABSOLUTE MAXIMUM RATINGS
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Industrial
Storage Temperature
Power Dissipation
Output Current.
Junction Temperature, TJ
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
RECOMMENDED OPERATING CONDITIONS
-0.5V to 4.6V
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
0°C to + 70°C
-40°C to +85°C
-55°C to +125°C
1.5 Watts
50 mA
175°C
Sym
VCC
VSS
VIH
VIL
Min
3.135
0
2.2
-0.3
Typ
3.3
0
–
–
Max
3.465
0
VCC+0.3
0.8
Units
V
V
V
V
Max
8
10
8
8
Unit
pF
pF
pF
pF
* Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
TRUTH TABLE
G#
X
H
L
X
E#
H
L
L
L
W#
X
H
H
L
Mode
Standby
Output Deselect
Read
Write
f=1.0MHZ, VIN=VCC or VSS
Output
High Z
High Z
DOUT
DIN
Power
ICC2,ICC3
ICC1
ICC1
ICC1
Parameter
Address Lines
Data Lines
Write & Output Enable Lines
Chip Enable Lines
Sym
CA
CD/Q
W#, G#
EØ#-E2#
These parameters are sampled, not 100% tested.
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March 2005
Rev. 5
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EDI8L24129V
DC ELECTRICAL CHARACTERISTICS
Parameter
Sym
Operating Power Supply Current
ICC1
Standby (TTL) Supply Current
ICC2
Full Standby CMOS
Supply Current
ICC3
Input Leakage Current
Output Leakage Current
Output High Volltage
Output Low Voltage
ILI
ILO
VOH
VOL
Conditions
Min
W#= VIL, II/O = 0mA,
Min Cycle
E# > VIH, VIN < VIL or
VIN > VIH, f=ØMHZ
E# > VCC-0.2V
VIN > VCC-0.2V or
VIN < 0.2V
VIN = 0V to VCC
V I/O = 0V to VCC
IOH = -4.0mA
IOL = 8.0mA
420
360
mA
90
75
mA
10
10
mA
±10
±10
±10
±10
0.4
0.4
µA
µA
V
V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Figure 1
RL= 50Ω
VL=1.5V
Z0= 50Ω
Units
12-15ns
2.4
AC TEST CIRCUIT
DOUT
Max
10ns
VSS to 3.0V
5ns
1.5V
Figure 1
(NOTE: For tEHQZ,tGHQZ and tWLQZ, Figure 2)
30pf
Figure 2
+3.3V
319W
DOUT
353Ω
5pf
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March 2005
Rev. 5
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EDI8L24129V
AC CHARACTERISTICS – READ CYCLE
Parameter
Symbol
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
JEDEC
tAVAV
tAVQV
tELQV
tELQX
tEHQZ
tAVQX
tGLQV
tGLQX
tGHQZ
10ns
Alt.
tRC
tAA
tACS
tCLZ
tCHZ
tOH
tOE
tOLZ
tOHZ
Min
10
12ns
Max
Min
12
10
10
15ns
Max
Min
15
12
12
3
3
5
3
3
5
7
3
6
0
0
5
Max
15
15
6
3
Units
7
0
6
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Parameter guaranteed, but not tested.
READ CYCLE – W# HIGH, G#, E# LOW
tAVAV
A
ADDRESS 1
ADDRESS 2
tAVQX
tAVQV
Q
DATA 1
DATA 2
READ CYCLE 2 – W# HIGH
tAVAV
A
tAVQV
E#
tEHQZ
tELQV
tELQX
G#
tGLQV
tGHQZ
tGLQX
Q
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March 2005
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EDI8L24129V
AC CHARACTERISTICS – WRITE CYCLE
Symbol
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
JEDEC
tAVAV
tELWH
tELEH
tAVWL
tAVEL
tAVWH
tAVEH
tWLWH
tWLEH
tWHAX
tEHAX
tWHDX
tEHDX
tWLQZ
tDVWH
tDVEH
tWHQX
10ns
Alt.
tWC
tCW
tCW
tAS
tAS
tAW
tAW
tWP
tWP
tWR
tWR
tDH
tDH
tWHZ
tDW
tDW
tWLZ
Min
10
8
8
0
0
8
8
8
8
0
0
0
0
0
6
6
3
12ns
Max
5
Min
12
9
9
0
0
9
9
10
10
0
0
0
0
0
6
6
3
15ns
Max
6
Min
15
9
9
0
0
10
10
11
11
0
0
0
0
0
7
7
3
Max
7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Parameter guaranteed, but not tested.
WRITE CYCLE – W# CONTROLLED
tAVAV
A
E#
tELWH
tAVWH
tWHAX
tWLWH
W#
tAVWL
tDVWH
D
tWHDX
DATA VALID
tWLQZ
tWHQX
HIGH Z
Q
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March 2005
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EDI8L24129V
WRITE CYCLE 2 – E# CONTROLLED
tAVAV
A
tAVEL
tELEH
E#
tEHAX
tAVEH
tWLEH
W#
tDVEH
D
Q
tEHDX
DATA VALID
HIGH Z
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March 2005
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EDI8L24129V
PACKAGE DESCRIPTION
Package No. 391
119 Lead BGA
JEDEC MO-163
PIN 1
INDEX
0.866
BSC
0.551
BSC
0.060 NOM./0.110 MAX.
0.800
BSC
0.050
TYP
0.028
MAX.
0.300
BSC
ORDERING INFORMATION
Commercial (0°C to +70°C)
Part Number
EDI8L24129V10BC
EDI8L24129V12BC
EDI8L24129V15BC
Speed
(ns)
10
12
15
Industrial (-40°C to +85°C)
Package
No.
391
391
391
Part Number
EDI8L24129V10BI
EDI8L24129V12BI
EDI8L24129V15BI
Speed
(ns)
10
12
15
Package
No.
391
391
391
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March 2005
Rev. 5
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EDI8L24129V
FIGURE 3 – INTERFACING THE MOTOROLA DSP5630X DSP FAMILY
WITH THE EDI8L24129V (128KX24)
EDI8L24129V
(128K x 24)
A16-0
E#
Address Bus
A23-0
DQ0-23
W#
G#
AA0
AA1
AA2
EDI8L24129V
AA3
Motorola
DSP5630x
(128K x 24)
WR#
A16-0
RD#
DQ0-23
E#
W#
G#
EDI8L24129V
(128K x 24)
Databus
D23-0
A16-0
E#
DQ0-23
W#
G#
NOTES:
1.
In this example three 128K x 24 external memory arrays are shown, one for X data, one for Y data and one for Program. Specific
applications may require one, two or all three arrays.
2.
Any combination of AA0-AA3 may be used as chip selects. However, each chip select may only be used to select one memory array.
FIGURE 4 – INTERFACING THE 21060L OR THE 21062L TO THE EDI8L24129V, 119 BGA
(CREATING A 128KX48 MEMORY ARRAY)
EDI8L24129V
Address Bus
A31-0
(128K x 24)
A16-0
DQ16-23
DQ8-15
DQ0-7
E#
W#
G#
MSX#
Analog
ADSP-2106xL
WR#
RD#
EDI8L24129V
(128K x 24)
A16-0
DQ16-23
DQ8-15
DQ0-7
E#
W#
G#
Databus
D47-0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 5
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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