IMP EI16C552 Dual fifo uart and parallel port Datasheet

Ei16C552
Dual FIFO UART and
Parallel Port
FEATURES
DESCRIPTION
•
IBM PC AT™ and PS/2™ compatible
•
Dual channel version of Ei16C550 with
Centronics printer interface
•
Independent control of transmit, receive, line
status and data set interrupts on each channel
•
Programmable serial interface characteristics for
each channel:
-5, 6, 7 or 8 bit characters
-Even, odd or no parity bit generation and
dectection
The Ei16C552 is an enhanced dual channel version
of the Ei16C550 Universal Asynchronous Receiver
Transmitter (UART). The device serves two serial
input/output interfaces simultaneously in microcomputer or microprocessor based systems. Each channel performs a serial-to-parallel conversion on data
characters received from peripheral devices or
modems, and a parallel-to-serial conversion on data
characters transmitted by the CPU. The complete
status of each channel of the dual UART can be
read at any time during functional operation by the
CPU. The information obtained includes the type and
condition of the transfer operations being performed,
and error conditions. In addition to its dual communications interface capabilities, the Ei16C552 provides the user with a fully bidirectional parallel data
port that fully supports the parallel Centronics type
printer. The parallel port, together with the two serial
ports, provide IBM PC AT™ and PS2 compatible
computers with a single device to serve the three
system ports.
-1, 1.5 or 2 stop bit generation
•
Programmable baud rate generator divides
CLK input by a divisor between 1 and (216 -1)
•
Tri-State® TTL drive capability for bidirectional
data bus and control bus on each channel
•
16 byte FIFO for receiver as well as for trans
mitter.
•
Advanced CMOS low power technology with
single 5 volt supply
Part Numbers May Be Marked With "IMP" or "Ei."
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
RXRDY0•
RSLD1•
GND
RI1•
DSR1•
CLK
CS1•
GND
LPTOE•
ACK•
PE
BUSY
SLCT
VCC
ERR•
SIN1
RXRDY1•
PIN CONFIGURATION
Ei16C552-CJ68
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
INT1
INT2
SLIN•
INIT•
AFD•
STB•
GND
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
INT0
BD0
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
CTS0•
RSLD0•
RI0•
DSR0•
CS0
A2
A1
A0
IOW•
IOR•
CS2•
RESET•
VCC
SIN0
TXRDY1•
INTSLC
SOUT1
DTR1•
RTS1•
CTS1•
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
TXRDY0•
VCC
RTS0•
DTR0•
SOUT0
5
For additional information, contact IMP, Inc. at 408.432.9100 or visit www.impweb.com
IMP, Inc. acquired Epic products on January 26, 2001. (see press release at http://www.impweb.com/PRESS/PR012601.htm)
Ei16C552
NOTES ON PIN DESCRIPTION:
1) Pin 4 and Pin 2 can be used by external crystal oscillator in future versions
2) Pin 23 and Pin 43 can be used as OUT20• and OUT21• respectively in future versions
ORDERING INFORMATION
Ei16C552-CJ68
68 Pin PLCC package
LIFE SUPPORT POLICY: Epic products are not to be used in life support devices without prior written
authorization.
Epic Semiconductor Inc. retains the right to make changes these specifications at any time, without notice.
Tri-state® is a Registered Trademark of National Semiconductor,Inc.
IBM PC AT™ and PS2 are Trademark s of International Business Machines.
BLOCK DIAGRAM
CTS0•
DSDR0•
RLSD0•
R10•
SIN0
CS0•
UART
#1
8
DB0-DB7
RTS0•
DTR0•
SOUT0
INT0
TXRDY0•
RXRDY0*
8
CTS1•
DSR1•
RLSD1•
RI1•
SIN1
CS1•
A0-A2
IOW•
IOR•
RESET•
RTS1•
DTR1•
SOUT1
INT1
TXRDY1•
RXRDY1•
UART
#2
3
SELECT
AND
CONTROL
•
BDO
8
LOGIC
CLK
8
ERR•
SLCT
BUSY
PE
ACK•
PARALLEL
PORT
PD0-PD7
INIT•
AFD•
STB•
SLIN•
INT2
LPTOE•
6
CS2•
For additional information, contact IMP, Inc. at 408.432.9100 or visit www.impweb.com
IMP, Inc. acquired Epic products on January 26, 2001. (see press release at http://www.impweb.com/PRESS/PR012601.htm)
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