Elantec EL2006CG High gain fast fet input op amp Datasheet

High Gain Fast FET Input Op Amp
Features
General Description
#
#
#
#
#
#
#
90 dB open loop gain
450 V/ms slew rate
40 MHz bandwidth
No thermal tail
3 mV max input offset voltage
Offset nulls with single pot
No compensation required for
gains above 50
# Peak output current to 200 mA
# Pin compatible with LH0032
# 80 dB common mode rejection
The EL2006/EL2006A are high slew rate, wide bandwidth, high
input impedance, high gain and fully differential input operational amplifiers. They exhibit excellent open loop gain characteristics making them suitable for a broad range of high speed
signal processing applications. These patented devices have
open loop gains in excess of 86 dB making the EL2006/
EL2006A ideal choices for current mode video bandwidth digital to analog converters of 10 bits or higher resolution. The
EL2006’s FET input structure, high slew rate, and high output
drive capability allow use in applications such as buffers for
flash converter inputs. In general, the EL2006/EL2006A allow
the user to take relatively high closed loop gains without compromising gain accuracy or bandwidth.
Ordering Information
The EL2006/EL2006A are pin compatible with the popular industry standard ELH0032/ELH0032A offering comparable
bandwidth and slew rate, while offering significant improvements in open loop gain, common mode rejection and power
supply rejection.
Temp. Range
Pkg.
OutlineÝ
EL2006CG
Part No.
b 25§ C to a 85§ C
TO-8
MDP0002
EL2006G
b 55§ C to a 125§ C
TO-8
MDP0002
EL2006G/883B
b 55§ C to a 125§ C
TO-8
MDP0002
EL2006ACG
b 25§ C to a 85§ C
TO-8
MDP0002
EL2006AG
b 55§ C to a 125§ C
TO-8
MDP0002
EL2006AG/883G
b 55§ C to a 125§ C
TO-8
MDP0002
Connection Diagrams
EL2006/EL2006A
EL2006/EL2006A
Elantec facilities comply with MIL-I-45208A and are
MIL-STD-1772 certified. Elantec’s Military devices comply
with MIL-STD-883 Class B Revision C and are manufactured
in our rigidly controlled, ultra-clean facilities in Milpitas, California. For additional information on Elantec’s Quality and Reliability Assurance Policy and procedures request brochure
QRA-1.
Simplified Schematic
2006 – 1
Top View
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
© 1989 Elantec, Inc.
November 1993 Rev F
2006 – 3
Manufactured under U.S. Patent No. 4,746,877
EL2006/EL2006A
High Gain Fast FET Input Op Amp
Absolute Maximum Ratings (TA e 25§ C)
IOUT
PD
TJ
TST
Operating Temperature Range
EL2006, EL2006A
EL2006C, EL2006AC
Operating Junction Temperature
Storage Temperature
Lead Temperature
(Soldering 10 seconds)
b 55§ C to a 125§ C
b 25§ C to a 85§ C
175§ C
b 65§ C to a 150§ C
300§ C
TD is 0.9in
TA
g 18V
Supply Voltage
g 15V
Input Voltage
Differential Input Voltage
30V
g 200 mA
Peak Output Current (Note 1)
Power Dissipation
TA e 25§ C 1.5W, derate 100§ C/W to a 125§ C
TC e 25§ C 2.2W, derate 70§ C/W to a 125§ C
VS
VIN
Important Note:
All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually
performed during production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test
equipment, specifically the LTX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefore TJ e TC e TA.
Test Level
I
II
III
IV
V
Test Procedure
100% production tested and QA sample tested per QA test plan QCX0002.
100% production tested at TA e 25§ C and QA sample tested at TA e 25§ C ,
TMAX and TMIN per QA test plan QCX0002.
QA sample tested per QA test plan QCX0002.
Parameter is guaranteed (but not tested) by Design and Characterization Data.
Parameter is typical value at TA e 25§ C for information purposes only.
DC Electrical Characteristics VS e g 15V, TMIN k TA k TMAX
Description
Test Conditions
Min
TJ e 25§ C
VOS
Offset Voltage
DVOS/DT
Offset Voltage Drift
IB
Bias Current
TJ e 25§ C
IOS
Offset Current
TJ e 25§ C
5
10
15
1
0.2
VCM
Common Mode Range
CMRR
Common Mode
Rejection Ratio
DVIN e g 10V
PSRR
Power Supply
Rejection Ratio
g 5V s VS s g 15V
AVOL
Large Signal
Voltage Gain
EL2006C
Test
Typ Max
Level
Min
I
I
V
100
I
10
I
25
I
2.5
I
g 10
Typ Max
5
I
10
III
mV
V
mV/§ C
500
I
pA
10
III
nA
50
I
pA
2.5
III
nA
II
V
15
1
0.2
I
g 10
Test Units
Level
mV
70
80
I
70
80
II
dB
70
88
I
70
88
II
dB
RL e 1 kX, VOUT e g 10V,
TJ e 25§ C
74
90
I
74
90
I
dB
RL e 1 kX, VOUT e g 10V
80
I
74
III
dB
g 12
I
g 12
II
V
g 100
I
g 100
I
mA
II
mA
VO
Output Voltage Swing RL e 1 kX
IOUT
Output Current
ICC
Supply Current
VOUT e g 10V,
TJ e 25§ C, (Note 1)
20
2
23
I
20
23
TD is 3.9in
EL2006
Parameter
EL2006/EL2006A
High Gain Fast FET Input Op Amp
DC Electrical Characteristics Ð Contd.
VS e g 15V, TMIN k TA k TMAX (Note: These tests are in addition to those listed above.)
Parameter
Description
Test Conditions
Min Typ Max
TJ e 25§ C
VOS
Offset Voltage
DVOS/DT
Offset Voltage Drift
AVOL
Large Signal
Voltage Gain
15
TJ e 25§ C, RL e 1 kX,
VOUT e g 10V
74
RL e 1 kX, VOUT e g 10V
74
EL2006AC
Test
Test
Min Typ Max
Level
Level
3
I
25
I
90
15
I
74
I
74
Units
3
I
mV
25
I
mV/§ C
II
dB
III
dB
90
TD is 1.4in
EL2006A
AC Electrical Characteristics VS e g 15V, RL e 1 kX, TJ e 25§ C (See AC Test Circuits)
tr
Description
Test Conditions
Rise Time
AV e 10V, VOUT e 1 VP-P
18
AV e 1V, VOUT e 1 VP-P
12
SR
Slew Rate (Note 2)
AV e 1V, VOUT e 20 VP-P
ts
Settling Time to 1.0%
ts
Settling Time to 0.1%
ts
Settling Time to 0.01%
GBW
350
15
V
18
I
12
V
ns
I
ns
450
I
V/ms
15
I
AV e b1V, VOUT e 10 VP-P
90
V
90
V
ns
AV e b1V, VOUT e 10 VP-P
160
V
160
V
ns
AV e b1V, VOUT e 10 VP-P
250
V
250
V
ns
500
V
500
V
MHz
7
I
7
I
MHz
VOUT e g 10V
5.5
350
Units
450
Gain Bandwidth Product AV t 20V
Pull Power
Bandwidth (Note 3)
EL2006C, EL2006AC
Test
Test
Min Typ Max
Min Typ Max
Level
Level
5.5
Unity Gain Bandwidth
CA e 8 pF, CB e 100 pF
40
V
40
V
MHz
eN
Noise Voltage
1 kHz to 1 MHz
20
V
20
V
nV/0Hz
tD
Small Signal Delay
AV e 1V
13
I
13
CIN
Input Capacitance
V
2
15
2
15
I
ns
V
pF
Note 1: TJ e 25§ C, duty cycle k 1%, pulse width k 10 ms.
Note 2: Slew rate is measured at the 25% and 75% points.
Note 3: The Full Power bandwidth is guaranteed by testing slew rate.
EL2006 Recommended Compensation
(See Figure 1)
AVOL
CA
CB
RS a
RSb
RF
a1
5–8 pF
100 pF
2k
Open Circuit
100
b 1 to a 5
5 pF
68 pF
0
k 1k
1k
g 10
5 pF
10 pF
k 1k
1k
l 10k
l g 20
3 pF
10 pF
k 1k
1k
l 20k
Note: Use a small capacitor of about 1 pF in parallel with RF to compensate for stray
input capacitance.
2006 – 4
Figure 1
3
TD is 2.9in
EL2006, EL2006A
Parameter
EL2006/EL2006A
High Gain Fast FET Input Op Amp
Typical Performance Curves
Bode Plot, Unity Gain
Compensation
Input Bias Currents as a
Function of Input
Voltage
Supply Current vs
Temperature
Inverting Gain of b 1
Settling Time
TO-8
Maximum Power
Dissipation
Normalized Input Bias
and Offset Current vs
Junction Temperature
2006 – 5
Applications Information
eliminates ‘‘thermal tail’’, which is the tendency
for the gain to diminish at very low frequencies
to DC due to thermal feedback. The EL2006 is
also easier to stabilize than earlier designs,
thanks to an Elantec proprietary internal compensation technique which eliminates the ‘‘second stage bump.’’ The EL2006 open loop gain
General
The EL2006 was designed to overcome the gain
and stability limitations of prior high speed FET
input operational amplifiers like the LH0032.
Open loop gain is typically 90 dB allowing gain
setting to 12-bit accuracy. This new design also
4
EL2006/EL2006A
High Gain Fast FET Input Op Amp
Applications Information Ð Contd.
Power Dissipation
characteristic is well behaved well beyond the
unity gain frequency so that spurious ringing or
oscillation in the 100 MHZ – 200 MHz region is
avoided. Finally, we have provided temperature
compensation so that gain and stability are relatively constant over temperature.
There is an additional effect on input bias current
as the input voltage is changed. The effect, common to all FETs, is an avalanche-like increase in
gate current as the FET gate-to-drain voltage is
increased above a critical value, depending on
FET geometry and doping levels. This effect will
be noted as the input voltage of the EL2006 is
taken below ground potential when the supplies
are g 15V. All of the effects described here may
be minimized by operating the device with
VS s g 15V.
These improvements are provided in a configuration which is plug compatible with LH0032 and
similar products so that designers can easily upgrade their system performance without extensive re-design. In most cases, the EL2006 can be
used to replace LH0032 with no change in external compensation.
These effects are indicated in the typical performance curves.
Video DAC Amplifiers
Input Capacitance
A typical application for the EL2006 is to provide gain for video signals. In the example
shown, the EL2006 provides a gain of 2 with settling time around 35 ns to 10 mV.
The input capacitance to the EL2006/EL2006A
is typically 2 pF and thus may form a significant
time constant with high value resistors. For optimum performance, the input capacitance to the
inverting input should be compensated by a
small capacitor across the feedback resistor. The
value is strongly dependent on layout and closed
loop gain, but will typically be in the neighborhood of several picofarads.
Power Supply Decoupling
The EL2006/EL2006A, like most high-speed circuits, is sensitive to layout and stray capacitance.
Power supplies should be bypassed as near to
pins 10 and 12 as possible with low inductance
capacitors such as 0.01 mF disc ceramics. Compensation components should also be located
close to the appropriate pins to minimize stray
reactances.
In the non-inverting configuration, it may be advantageous to bootstrap the case and/or a guard
conductor to the inverting input. This serves
both to divert leakage currents away from the
non-inverting input and to reduce the effective
input capacitance. A unity gain follower so treated will have an input capacitance under a 1 pF.
Input Current
Because the input devices are FETs, the input
bias current may be expected to double for each
11§ C junction temperature rise. This characteristic is plotted in the typical performance characteristics graphs. The device will self-heat due to
internal power dissipation after application of
power, thus raising the FET junction temperature 40§ C – 60§ C above the free-air ambient temperature when supplies are g 15V. The device
temperature will stabilize within 5 –10 minutes
after application of power, and the input bias currents measured at the time will be indicative of
normal operating currents. An additional rise will
occur as power is delivered to a load due to additional internal power dissipation.
2006 – 6
5
EL2006/EL2006A
High Gain Fast FET Input Op Amp
ture rise with a small heat sink such as the Thermalloy No. 2241 or equivalent. The case of the
device has no internal connection, so it may be
electrically connected to the sink if this is advantageous. Be aware, however, that this will affect
the stray capacitances to all pins and may thus
require adjustment of circuit compensation values.
Applications Information Ð Contd.
Heatsinking
While the EL2006/EL2006A are specified for operation without any explicit heatsink, internal
power dissipation does cause a significant temperature rise. Improved bias current performance
can thus be obtained by limiting this temperaVoltage Follower (AV e a 1)
Large Signal Pulse Response
Large Signal Pulse Response
Test Circuit
2006 – 12
VS e g 15V, VIN e a 10V to b10V and b10V to a 10V
2006 – 7
EL2006 Settling Time Test Circuit
2006 – 8
Inverting Unity Gain
Inverting Gain of 10
2006 – 9
2006 – 10
6
EL2006/EL2006A
High Gain Fast FET Input Op Amp
Burn-In Circuit
2006 – 11
Pin Numbers are for TO-8 package. LCC uses the same schematic.
7
EL2006/EL2006A
TAB WIDE
High Gain Fast FET Input Op Amp
EL2006 Macromodel
a input
l
l
l
l
l
l
l
l
b input
l
l
l
l
l
l
l
a Vsupply
l
l
l
l
l
l
b Vsupply
l
l
l
l
l
Comp 3
Comp 4
l
*
l
l Comp 2
*
l
l l Output
*
l
l l l
.subckt M2006
6
5
12
10
3
4
2
11
* Models
.model qfa njf (vto eb2.5V beta e 1.11eb3 cgd e 2pF cgs e 5pF m e 0.3744)
.model qp pnp (is e 5Eb14 bf e 150 vaf e 100 ikf e 100mA tf e .53nS vtf e 0 ise e 1 nA,
a cjc e 4pF cje e 5.7pF tr e 170nS rb e 3 br e 5 mje e .32 mjc e .43 xtb e 2.1 ne e 4
a isc e 1nA nc e 4 itf e .4 vtf e 4 xtf e 6)
.model qn npn (is e 5eb14 bf e 150 vaf e 800 ikf e 200mA tf e .54nS vtf e 0
a cjc e 4pF cje e 5pF rb e 3 br e 5 mje e .42 mjc e .23 tr e 200nS xtb e 2.1
a ise e 4nA ne e 4 isc e 4nA nc e 4 itf e .4 vtf e 4 xtf e 2)
.model qfb njf (vto eb2.8V beta e 4eb3 cgd e 7pF cgs e 8pF lambda e 4eb3)
.model zener d (bv e 2.49V ibv e 1mA)
* Resistors and Capacitors
r1 12 4 700
r2 12 3 700
r3 12 105 160
r4 103 100 10
r5 108 100 10
r6 12 101 22K
r7 113 11 10
r8 11 112 10
r9 102 10 407
cs2 10 116 100pF
* Transistors and Diodes
j1a 4 5 103 qfa
j1b 3 6 108 qfa
j2 111 10 116 qfb
q1 104 4 105 qp
q2 2 3 105 qp
q3 114 11 104 qp
q4 12 2 113 qn
q5 10 111 112 qp
q6 2 2 110 qn
q7 111 111 110 qp
q8 100 101 102 qn
d1 10 117 zener
q9 101 101 117 qn
q10 114 114 10 qn
q11 116 114 10 qn
.ends
8
TD is 6.4in
* Connections:
*
*
*
*
*
EL2006/EL2006A
High Gain Fast FET Input Op Amp
EL2006 Macromodel Ð Contd.
2006 – 3
9
10
BLANK
11
BLANK
EL2006/EL2006A
EL2006/EL2006A
High Gain Fast FET Input Op Amp
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes
in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any
circuits described herein and makes no representations that they are free from patent infringement.
November 1993 Rev F
WARNING Ð Life Support Policy
Elantec, Inc. products are not authorized for and should not be
used within Life Support Systems without the specific written
consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform
when properly used in accordance with instructions provided can
be reasonably expected to result in significant personal injury or
death. Users contemplating application of Elantec, Inc. products
in Life Support Systems are requested to contact Elantec, Inc.
factory headquarters to establish suitable terms & conditions for
these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages.
Elantec, Inc.
1996 Tarob Court
Milpitas, CA 95035
Telephone: (408) 945-1323
(800) 333-6314
Fax: (408) 945-9305
European Office: 44-71-482-4596
12
Printed in U.S.A.
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