Intersil EL5373IUZ 450mhz differential twisted-pair driver Datasheet

EL5173, EL5373
¬
Data Sheet
February 4, 2008
450MHz Differential Twisted-Pair Drivers
Features
The EL5173 and EL5373 are single and triple high bandwidth
amplifiers with a fixed gain of 2. They are primarily targeted for
applications such as driving twisted-pair lines in component
video applications. The inputs can be in either single-ended or
differential form but the outputs are always in differential form.
• Fully differential inputs and outputs
The output common mode level for each channel is set by
the associated REF pin, which have a -3dB bandwidth of
over 190MHz. Generally, these pins are grounded but can
be tied to any voltage reference.
• 1100V/µs slew rate (EL5373)
All outputs are short circuit protected to withstand temporary
overload condition.
• Low power - 12mA per channel
The EL5173 and EL5373 are specified for operation over the
full -40°C to +85°C temperature range.
FN7312.7
• Differential input range ±2.3V
• 450MHz 3dB bandwidth at fixed gain of 2
• 900V/µs slew rate (EL5173)
• Single 5V or dual ±5V supplies
• 40mA maximum output current
• Pb-free available (RoHS compliant)
Applications
• Twisted-pair drivers
Pinouts
• Differential line drivers
EL5373
(24 LD QSOP)
TOP VIEW
EL5173
(8 LD SOIC, MSOP)
TOP VIEW
• VGA over twisted-pairs
• ADSL/HDSL drivers
1 IN+
OUT 8
EN 1
2 EN
VS- 7
INP1 2
3 IN-
VS+ 6
INN1 3
22 NC
OUTB 5
REF1 4
21 VSP
NC 5
20 VSN
4 REF
+
-
INN2 7
+
-
REF2 8
REF3 12
1
• Transmission of analog signals in a noisy environment
18 OUT2
17 OUT2B
16 NC
NC 9
INN3 11
• Single ended to differential amplification
23 OUT1B
19 NC
INP2 6
INP3 10
24 OUT1
+
-
15 OUT3
14 OUT3B
13 NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5173, EL5373
Ordering Information
PART NUMBER
PART MARKING
PACKAGE
PKG. DWG. #
EL5173IS
5173IS
8 Ld SOIC
MDP0027
EL5173IS-T7
5173IS
8 Ld SOIC
MDP0027
EL5173IS-T13
5173IS
8 Ld SOIC
MDP0027
EL5173ISZ (Note)
5173ISZ
8 Ld SOIC (Pb-free)
MDP0027
EL5173ISZ-T7 (Note)
5173ISZ
8 Ld SOIC (Pb-free)
MDP0027
EL5173ISZ-T13 (Note)
5173ISZ
8 Ld SOIC (Pb-free)
MDP0027
EL5173IY
i
8 Ld MSOP
MDP0043
EL5173IY-T7
i
8 Ld MSOP
MDP0043
EL5173IY-T13
i
8 Ld MSOP
MDP0043
EL5173IYZ (Note)
BAAYA
8 Ld MSOP (Pb-free)
MDP0043
EL5173IYZ-T7 (Note)
BAAYA
8 Ld MSOP (Pb-free)
MDP0043
EL5173IYZ-T13 (Note)
BAAYA
8 Ld MSOP (Pb-free)
MDP0043
EL5373IU
EL5373IU
24 Ld QSOP
MDP0040
EL5373IU-T7
EL5373IU
24 Ld QSOP
MDP0040
EL5373IU-T13
EL5373IU
24 Ld QSOP
MDP0040
EL5373IUZ (Note)
EL5373IUZ
24 Ld QSOP (Pb-free)
MDP0040
EL5373IUZ-T7 (Note)
EL5373IUZ
24 Ld QSOP (Pb-free)
MDP0040
EL5373IUZ-T13 (Note)
EL5373IUZ
24 Ld QSOP (Pb-free)
MDP0040
* Please refer to TB347 for details on reel specifications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN7312.7
February 4, 2008
EL5173, EL5373
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6V
Supply Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs max.
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Recommended Operating Temperature . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 200Ω, CLD = 1pF, Unless Otherwise Specified
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
450
MHz
BW
±0.1dB Bandwidth
60
MHz
SR
Slew Rate - EL5173
VOUT = 2VP-P, 20% to 80%
750
900
V/µs
Slew Rate - EL5373
VOUT = 2VP-P, 20% to 80%
900
1100
V/µs
TSTL
Settling Time to 0.1%
VOUT = 2VP-P
10
ns
OS
Overshoot
VODP-P = 2V
10
%
TOVR
Output Overdrive Recovery Time
10
ns
VREFBW (-3dB)
VREF -3dB Bandwidth
AV =1, CLD = 2.7pF
190
MHz
VREFSR+
VREF Slew Rate - Rise
VOUT = 2VP-P, 20% to 80%
200
V/µs
VREFSR-
VREF Slew Rate - Fall
VOUT = 2VP-P, 20% to 80%
125
V/µs
VN
Input Voltage Noise
f = 10kHz
25
nV/√Hz
HD2
Second Harmonic Distortion
VOUT = 2VP-P, 5MHz
84
dBc
HD2
Second Harmonic Distortion
VOUT = 2VP-P, 20MHz
71
dBc
HD3
Third Harmonic Distortion
VOUT = 2VP-P, 5MHz
62
dBc
HD3
Third Harmonic Distortion
VOUT = 2VP-P, 20MHz
53
dBc
dG
Differential Gain at 3.58MHz
RLD = 300Ω, AV = 2
0.05
%
dθ
Differential Phase at 3.58MHz
RLD = 300Ω, AV = 2
0.08
°
eS
Channel Separation - for EL5373 only
at 1MHz
90
dB
INPUT CHARACTERISTICS
VOS
Input Referred Offset Voltage
IIN
Input Bias Current (VIN, VINB)
IREF
INput Bias Current at REF
Gain
Gain Accuracy
RIN
Differential Input Resistance
CIN
Differential Input Capacitance
DMIR
Differential Mode Input Range
CMIR+
Common Mode Positive Input Range at
VIN+, VIN-
3
±3
±30
mV
EL5173
-21
-11
-5
µA
EL5373
-21
-13
-5
µA
VREF = +3.2V
1
5
µA
VREF = -3.2V
-1
+1
µA
2.01
V
VIN = ±1V
1.97
1.99
150
kΩ
1
pF
±2
±2.3
V
3.1
3.4
V
FN7312.7
February 4, 2008
EL5173, EL5373
Electrical Specifications
VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 200Ω, CLD = 1pF, Unless Otherwise Specified (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
CMIR-
Common Mode Negative Input Range at
VIN+, VIN-
VREFIN+
Reference Input - Positive
VIN+ = VIN- = 0V
VREFIN-
Reference Input - Negative
VIN+ = VIN- = 0V
VREFOS
Output Offset Relative to VREF
CMRR
Input Common Mode Rejection Ratio
MIN
3.3
TYP
MAX
UNIT
-4.5
-4.2
V
3.7
V
-3.3
-3
V
-100
50
+100
mV
VIN = ±2.5V
60
80
dB
RLD = 200Ω
3.3
3.67
V
OUTPUT CHARACTERISTICS
VOUT
(EL5173)
VOUT
(EL5373)
IOUT(Max)
ROUT
Positive Output Voltage Swing
Negative Output Voltage Swing
Positive Output Voltage Swing
-3.3
RLD = 200Ω
3.7
Negative Output Voltage Swing
Maximum Output Current
-3
V
4
-3.7
V
-3.4
V
RL = 10Ω (EL5173)
±45
±55
mA
RL = 10Ω (EL5373)
±40
±50
mA
60
mΩ
Output Impedance
SUPPLY
VSUPPLY
Supply Operating Range
IS(ON)
Power Supply Current - Per Channel
IS(OFF)+ (EL5173) Positive Power Supply Current - Disabled
IS(OFF)- (EL5173)
VS+ to VS-
EN pin tied to 4.8V
Negative Power Supply Current - Disabled
IS(OFF)+ (EL5373) Positive Power Supply Current - Disabled
IS(OFF)- (EL5373)
Negative Power Supply Current - Disabled
PSRR
Power Supply Rejection Ratio
EN pin tied to 4.8V
VS from ±4.5V to ±5.5V
4.75
11
V
9
12
14
mA
60
80
100
µA
-150
-120
-90
µA
0.5
2
10
µA
-150
-120
-90
µA
60
73
dB
ENABLE
tEN
Enable Time
100
ns
tDS
Disable Time
1.2
µs
VIH
EN Pin Voltage for Power-Up
VIL
EN Pin Voltage for Shut-Down
IIH-EN
EN Pin Input Current High - Per Channel
At VEN = 5V
IIL-EN
EN Pin Input Current Low - Per Channel
At VEN = 0V
4
VS+ - 1.5
VS+ - 0.5
V
40
-5
V
-2.5
60
µA
µA
FN7312.7
February 4, 2008
EL5173, EL5373
Pin Descriptions
EL5173
EL5373
PIN NUMBER
PIN NAME
PIN NUMBER
PIN NAME
1
IN+
2, 6, 10
INP1, 2, 3
2
EN
1
EN
3
IN-
3, 7, 11
INN1, 2, 3
Inverting inputs, note that on EL5173, this pin is also the REF pin
4
REF
4, 8, 12
REF1, 2, 3
Reference inputs, sets common-mode output voltage
5
OUTB
14, 17, 23
OUT3B, 2B, 1B
6
VS+
21
VS+, VSP
Positive supply
7
VS-
20
VS-, VSN
Negative supply
8
OUT
15, 18, 24
OUT3, 2, 1
-
NC
5, 9, 13, 16,
19, 22
NC
5
PIN FUNCTION
Non-inverting inputs
ENABLE
Inverting outputs
Non-inverting outputs
No connect; grounded for best crosstalk performance
FN7312.7
February 4, 2008
Connection Diagrams
EL5173
CL1
RS1
50Ω
-5V
RRT2
1 IN+
INP
LOADP
OUT 8
50Ω
6
EN
2 EN
VS- 7
INN
3 IN-
VS+ 6
REF
4 REF
RS2
50Ω
RRT2
LOADN
OUTB 5
RS3
50Ω
+5V
CL2
50Ω
EL5373
RRT1
ENABLE
1 EN
LD1
OUT1 24
RRT1B
INP1
2 INP1
50Ω
LD1B
OUT1B 23
50Ω
INN1
3 INN1
NC 22
REF1
4 REF1
VSP 21
5 NC
VSN 20
INP2
6 INP2
NC 19
INN2
7 INN2
OUT2 18
RRT2
LD2
RRT2B
REF2
8 REF2
50Ω
LD2B
OUT2B 17
50Ω
9 NC
NC 16
RRT3
INP3
10 INP3
OUT3 15
RRT3B
11 INN3
INN3
OUT3B 14
50Ω
12 REF3
REF3
RSP1
50Ω
RSN1
50Ω
RSR1
50Ω
RSP2
50Ω
RSN2
50Ω
RSR2
50Ω
RSP3
50Ω
RSN3
50Ω
NC 13
RSR3
50Ω
FN7312.7
February 4, 2008
-5V
LD3
50Ω
LD3B
EL5173, EL5373
+5V
EL5173, EL5373
Typical Performance Curves
VS = ±5V, CLD = 1pF
VS = ±5V, RLD = 200Ω
10
10
9
9
8
8
RLD = 500Ω
7
VODP-P = 200mV
6
GAIN (dB)
GAIN (dB)
7
RLD = 1kΩ
5
4
3
6
5
RLD = 200Ω
4
3
VODP-P = 700mV
2
RLD = 100Ω
2
1
1
0
1M
10M
100M
0
100k
1G
1G
FIGURE 2. FREQUENCY RESPONSE vs RLD
VS = ±5V, RLD = 200Ω, VODP-P = 200mV
5
11
4
10
CLD = 16pF
8
3
GAIN (dB)
9
GAIN (dB)
100M
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE
CLD = 5pF
7
6
4
VREF = 200mVP-P
1
0
-2
CLD = 0pF
3
2
-1
CLD = 2.3pF
5
VREF = 1VP-P
-3
-4
2
1
1M
10M
1M
FREQUENCY (Hz)
10M
100M
-5
1M
1G
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 4. FREQUENCY RESPONSE vs VREF
FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE vs CLD
100Ω
VINCM
+
-
VODM
VOCM
100Ω
COMMON MODE REJECTION (dB)
0
-10
-20
PSRR (dB)
-30
PSRR-
-40
-50
-60
PSRR+
-70
-80
-90
100k
1M
10M
FREQUENCY (Hz)
FIGURE 5. PSRR vs FREQUENCY
7
100M
0
-10
-20
-30
-40
VOCM/VINCM
-50
-60
-70
VODM/VINCM
-80
-90
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 6. COMMON MODE REJECTION vs FREQUENCY
FN7312.7
February 4, 2008
EL5173, EL5373
Typical Performance Curves
(Continued)
100Ω
VIN
+
-
RT
VOCM
VODM
R
100Ω
1000
VOLTAGE NOISE (nV/√Hz)
0
BALANCE ERROR (dB)
-10
-20
-30
-40
VOCM/VODM
-50
-60
100k
1M
10M
100M
100
10
10
1G
100
1k
10k
100k
1M
10M
FREQENCY (Hz)
FREQUENCY (Hz)
FIGURE 8. INPUT VOLTAGE NOISE vs FREQUENCY
FIGURE 7. DIFFERENTIAL MODE OUTPUT BALANCE
ERROR vs FREQUENCY
460
-40
440
420
-50
CH3-->CH2
CH2-->CH1
-60
BW (MHz)
CHANNEL SEPARATION (dB)
VODMP-P = 200mV, RLD = 200Ω
-30
CH2-->CH3
-70
-80
CH1-->CH2
400
380
360
CH3-->CH1
-90
340
CH1-->CH3
-100
-110
100k
1M
10M
320
100M
1G
300
4
5
6
8
7
9
11
10
VS (V)
FREQUENCY (Hz)
FIGURE 9. CHANNEL SEPARATION vs FREQUENCY
FIGURE 10. SMALL SIGNAL BANDWIDTH vs SUPPLY
VOLTAGE
-40
11.9
VS = ±5V, RLD = 200Ω
-45
11.8
DISTORTION (dB)
11.7
IS (mA)
HD3 (f=20MHz)
-50
IS+
IS-
11.6
11.5
-55
HD3 (f=5MHz)
-60
-65
-70
HD2 (f=20MHz)
-75
HD2 (f=5MHz)
-80
11.4
11.3
4
-85
-90
5
6
8
7
9
10
11
VS (V)
FIGURE 11. SUPPLY CURRENT vs SUPPLY VOLTAGE
8
1
2
3
4
5
6
7
8
9
DIFFERENTIAL OUTPUT VOLTAGE (V)
FIGURE 12. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE
FN7312.7
February 4, 2008
EL5173, EL5373
Typical Performance Curves
-40
(Continued)
VS = ±5V, VODMP-P = 2V
-40
VS = ±5V, RLD = 200Ω, VODMP-P = 2V
-45
-50
HD3 (f = 20MHz)
DISTORTION (dB)
DISTORTION (dB)
-50
-60
HD3 (f
-70
)
HD2 (f = 20MHz)
-80
-90
-100
100
= 5M Hz
300
400
500
600
700
-60
HD2
-65
-70
-75
-80
HD2 (f = 5MHz)
200
HD3
-55
-85
800
900 1000
-90
0M
5M
10M
15M
20M
25M
30M
35M
40M
FREQUENCY (Hz)
RLD (Ω)
FIGURE 13. HARMONIC DISTORTION vs RLD
FIGURE 14. HARMONIC DISTORTION vs FREQUENCY
0.5V/DIV
100mV/DIV
20ns/DIV
20ns/DIV
FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE
EMPTY
BOARD
DISABLED
OUT1B
OUT1
FIGURE 17. OUTPUT IMPEDANCE (DISABLED)
9
FIGURE 18. OUTPUT IMPEDANCE (ENABLED)
FN7312.7
February 4, 2008
EL5173, EL5373
Typical Performance Curves
(Continued)
FIGURE 19. DISABLED RESPONSE
FIGURE 20. ENABLED RESPONSE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1.2
1.136W
1.0
909mW
0.8
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.4
QSOP24
θJA = +88°C/W
SO8
θJA = +110°C/W
870mW
0.6
MSOP8/10
θJA = +115°C/W
0.4
0.2
0
1.0
870mW
0.8
QSOP24
θJA = +115°C/W
625mW
0.6
SO8
θJA = +160°C/W
0.4 486mW
MSOP8
θJA = +206°C/W
0.2
0
0
25
75 85 100
50
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
10
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7312.7
February 4, 2008
EL5173, EL5373
Simplified Schematic
200Ω
VS+
R3
R1
R4
R2
R7
IN+
IN-
FBP
R8
FBN
VB1
OUT+
RCD
REF
RCD
OUT-
VB2
CC
R9
R10
CC
R5
R6
VS-
400Ω
Description of Operation and Application
Information
Product Description
The EL5173 and EL5373 are wide bandwidth, low power
and single/differential ended to differential output amplifiers.
They have a fixed gain of 2. The EL5173 is a single channel
differential amplifier. The EL5373 is a triple channel
differential amplifier. The EL5173 and EL5373 have a -3dB
bandwidth of 450MHz while driving a 200Ω differential load.
The EL5173 and EL5373 are available with a power down
feature to reduce the power while the amplifiers are
disabled.
Input, Output and Supply Voltage Range
The EL5173 and EL5373 have been designed to operate
with a single supply voltage of 5V to 10V or a split supplies
with its total voltage from 5V to 10V. The amplifiers have an
input common mode voltage range from -4.5V to 3.4V for
±5V supply. The differential mode input range (DMIR)
between the two inputs is from -2.3V to +2.3V. The input
voltage range at the REF pin is from -3.3V to 3.7V. If the
input common mode or differential mode signal is outside the
above-specified ranges, it will cause the output signal
distorted.
200Ω
Driving Capacitive Loads and Cables
The EL5173 and EL5373 can drive 16pF differential
capacitor in parallel with 200Ω differential load with less than
3.5dB of peaking. If less peaking is desired in applications, a
small series resistor (usually between 5Ω to 50Ω) can be
placed in series with each output to eliminate most peaking.
However, this will reduce the gain slightly.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier’s output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The output of the EL5173 and EL5373 can swing from -3.3V
to 3.6V at 200Ω differential load at ±5V supply. As the load
resistance becomes lower, the output swing is reduced.
The EL5173 and EL5373 can be disabled and placed their
outputs in a high impedance state. The turn off time is about
1.2µs and the turn on time is about 100ns. When disabled,
the amplifier’s supply current is reduced to 40µA for IS+ and
2.5µA for IS- typically, thereby effectively eliminating the
power consumption. The amplifier’s power down can be
controlled by standard CMOS signal levels at the ENABLE
pin. The applied logic signal is relative to VS+ pin. Letting the
EN pin float or applying a signal that is less than 1.5V below
VS+ will enable the amplifier. The amplifier will be disabled
when the signal at EN pin is above VS+ - 0.5V.
Differential and Common Mode Gain Settings
Output Drive Capability
As shown at the simplified schematic, since the feedback
resistors RF and the gain resistor are integrated with 200Ω
and 400Ω, the EL5173 and EL5373 have a fixed gain of 2.
The common mode gain is always one.
The EL5173 and EL5373 have internal short circuit
protection. Its typical short circuit current is ±55mA. If the
output is shorted indefinitely, the power dissipation could
easily increase such that the part will be destroyed.
11
FN7312.7
February 4, 2008
EL5173, EL5373
Maximum reliability is maintained if the output current never
exceeds ±60mA. This limit is set by the design of the internal
metal interconnect.
Where:
• VS = Total supply voltage
• ISMAX = Maximum quiescent supply current per channel
Power Dissipation
With the high output drive capability of the EL5173 and
EL5373 it is possible to exceed the +125°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T JMAX – T AMAX
PD MAX = --------------------------------------------Θ JA
(EQ. 1)
Where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
ΔV O⎞
⎛
PD = i × ⎜ V S × I SMAX + V S × ------------⎟
R LD ⎠
⎝
(EQ. 2)
• ΔVO = Maximum differential output voltage of the
application
• RLD = Differential load resistance
• ILOAD = Load current
• i = Number of channels
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier’s inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
Typical Applications
Twisted pair cable driver
0Ω
50
VFB
50Ω
EL5173/
EL5373
VIN
50
VINB
ZO = 100Ω
EL5175/
EL5375
VOUT
50Ω
VREF
FIGURE 23. TWISTED PAIR CABLE DRIVER
12
FN7312.7
February 4, 2008
EL5173, EL5373
Small Outline Package Family (SO)
A
D
h X 45¬
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4¬× ¬±
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
13
FN7312.7
February 4, 2008
EL5173, EL5373
Quarter Size Outline Plastic Packages Family (QSOP)
MDP0040
A
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
INCHES
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
E
PIN #1
I.D. MARK
E1
1
(N/2)
A
0.068
0.068
0.068
Max.
-
A1
0.006
0.006
0.006
±0.002
-
A2
0.056
0.056
0.056
±0.004
-
b
0.010
0.010
0.010
±0.002
-
c
0.008
0.008
0.008
±0.001
-
D
0.193
0.341
0.390
±0.004
1, 3
E
0.236
0.236
0.236
±0.008
-
E1
0.154
0.154
0.154
±0.004
2, 3
e
0.025
0.025
0.025
Basic
-
L
0.025
0.025
0.025
±0.009
-
L1
0.041
0.041
0.041
Basic
-
N
16
24
28
Reference
-
B
0.010
C A B
e
H
C
SEATING
PLANE
0.007
0.004 C
b
C A B
Rev. F 2/07
NOTES:
L1
A
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
c
SEE DETAIL "X"
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010
A2
GAUGE
PLANE
L
A1
4¬×¬±
DETAIL X
14
FN7312.7
February 4, 2008
EL5173, EL5373
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
MILLIMETERS
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
0.10 C
N LEADS
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
-
0.08 M C A B
b
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3¬× ¬±
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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15
FN7312.7
February 4, 2008
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