Eorex EM482M3244VTA-75FE 128mb (1mã 4bankã 32) synchronous dram Datasheet

eorex
EM484M3244VTA
128Mb (1M×4Bank×32) Synchronous DRAM
Features
Description
• Fully Synchronous to Positive Clock Edge
• Single 3.3V ±0.3V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms (15.625us)
The EM484M3244VTA is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
1Meg words x 4 banks by 32 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 128Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages:TSOPII 86P 400mil.
Ordering Information
Part No
Organization
Max. Freq
Package
Grade
Pb
EM484M3244VTA-75F
4M X 32
133MHz @CL3
86pin TSOP(ll)
Commercial
Free
EM484M3244VTA-7F
4M X 32
143MHz @CL3
86pin TSOP(ll)
Commercial
Free
EM484M3244VTA-6F
4M X 32
166MHz @CL3
86pin TSOP(ll)
Commercial
Free
* EOREX reserves the right to change products or specification without notice.
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EM484M3244VTA
Pin Assignment
86pin TSOP-II / (400mil × 875mil) / (0.5mm Pin pitch)
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EM484M3244VTA
Pin Description (Simplified)
Pin
Name
68
CLK
20
/CS
67
CKE
21,24~27,60~66
A0~A11
22, 23
BA0, BA1
19
/RAS
18
/CAS
17
/WE
16,28,59,71
DQM0~DQM3
2, 4, 5, 7, 8, 10,
11,13,31,33,34,36
,37,39,40,42,45,
47,48,50,51,53,
54,56,74,76,77,
79,80,82,83,85
1,15,29,43/
44,58,72,86
3,9,35,41,49,55,
75,81/6,12,32,38,
46,52,78,84
14,30,57,69,70,
73
DQ0~DQ31
VDD/VSS
VDDQ/VSSQ
NC
Function
(System Clock)
Master clock input (Active on the positive rising edge)
(Chip Select)
Selects chip when active
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
(Address)
Row address (A0 to A11) is determined by A0 to A11 level at
the bank active command cycle CLK rising edge.
CA (CA0 to CA7) is determined by A0 to A7 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the
pre-charge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA0/BA1 is pre-charged.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK
with /RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Data Input/Output Mask)
DQM controls I/O buffers.
(Data Input/Output)
DQ pins have the same function as I/O pins on a conventional
DRAM.
(Power Supply/Ground)
VDD and VSS are power supply pins for internal circuits.
(Power Supply/Ground)
VDDQ and VSSQ are power supply pins for the output buffers.
(No Connection)
This pin is recommended to be left No Connection on the
device.
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EM484M3244VTA
Absolute Maximum Rating
Symbol
Item
Rating
Units
VIN, VOUT
Input, Output Voltage
-0.3 ~ +4.6
V
VDD, VDDQ
Power Supply Voltage
-0.3 ~ +4.6
Commercial
0 ~ +70
Extended
-25 ~ +85
-55 ~ +150
V
°C
1
W
TOP
Operating Temperature Range
TSTG
Storage Temperature Range
PD
Power Dissipation
°C
IOS
Short Circuit Current
50
mA
Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could
cause permanent damage. The device is not meant to be operated under conditions outside the
limits described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Capacitance (VCC=3.3V, f=1MHz, TA=25°C)
Symbol
Parameter
Min.
CCLK
Clock Capacitance
Input Capacitance for CLK, CKE, Address,
/CS, /RAS, /CAS, /WE, DQML, DQMU
Input/Output Capacitance
CI
CO
Typ.
Max.
Units
2.5
4.0
pF
2.5
4.5
pF
4.0
6.5
pF
Recommended DC Operating Conditions (TA=0°C ~70°C)
Symbol
Parameter
Min.
Typ.
Max.
Units
VDD
Power Supply Voltage
3.0
3.3
3.6
V
VDDQ
Power Supply Voltage (for I/O Buffer)
3.0
3.3
3.6
V
Input Logic High Voltage
2.0
VDD+0.3
V
-0.3
0.8
V
VIH
VIL
Input Logic Low Voltage
Note: * All voltages referred to VSS.
* VIH (max.) = 5.6V for pulse width 3ns
* VIL (min.) = -2.0V for pulse width 3ns
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EM484M3244VTA
Recommended DC Operating Conditions
(VDD=3.3V±0.3V, TA=0°C ~70°C)
Symbol
Parameter
(Note 1)
ICC1
Operating Current
ICC2P
Precharge Standby Current in
Power Down Mode
ICC2PS
ICC2N
Precharge Standby Current in
Non-power Down Mode
ICC2NS
ICC3P
ICC3PS
ICC3N
Active Standby Current in
Power Down Mode
Active Standby Current in
Non-power Down Mode
ICC3NS
ICC4
Operating Current (Burst
(Note 2)
Mode)
ICC5
Refresh Current
ICC6
Self Refresh Current
(Note 3)
Test Conditions
Burst length=1,
tRC≥tRC(min.), IOL=0mA,
One bank active
CKE≤VIL(max.), tCK=15ns
CKE≤VIL(max.), tCK= ∞
CKE≥VIL(min.), tCK=15ns,
/CS≥VIH(min.)
Input signals are changed
one time during 30ns
CKE≥VIL(min.), tCK= ∞ ,
Input signals are stable
CKE≤VIL(max.), tCK=15ns
Max.
Units
100
mA
1
mA
1
mA
35
mA
10
mA
5
mA
CKE≤VIL(max.), tCK= ∞
CKE≥VIL(min.), tCK=15ns,
/CS≥VIH(min.)
Input signals are changed
one time during 30ns
CKE≥VIL(min.), tCK= ∞ ,
Input signals are stable
1
mA
60
mA
30
mA
tCCD≥2CLKs, IOL=0mA
160
mA
tRC≥tRC(min.)
120
mA
(Note 4)
mA
CKE≤0.2V
1
*All voltages referenced to VSS.
Note 1: ICC1 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK (min.)
Note 2: ICC4 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK (min.)
Note 3: Input signals are changed only one time during tCK (min.)
Note 4: Standard power version.
Recommended DC Operating Conditions (Continued)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
-0.5
+0.5
uA
Output Leakage Current
0≤VI≤VDDQ, VDDQ=VDD
All other pins not under test=0V
0≤VO≤VDDQ, DOUT is disabled
-0.5
+0.5
uA
VOH
High Level Output Voltage
IO=-4mA
2.4
VOL
Low Level Output Voltage
IO=+4mA
IIL
Input Leakage Current
IOL
V
0.4
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EM484M3244VTA
Block Diagram
Auto/Self
Refresh Counter
A0
A1
DQM
A2
A3
A4
Memory
Array
A5
A6
Write DQM
Control
A7
A8
Data In
A9
DOi
S/A & I/O Gating
A10
A11
Data Out
Col. Decoder
BA0
BA1
Col. Add. Buffer
Read DQM
Control
Mode Register Set
Col. Add. Counter
Burst Counter
Timing Register
CLK
CKE
/CS
/RAS
/CAS
Jul. 2006
/WE
DQM
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EM484M3244VTA
AC Operating Test Conditions
(VDD=3.3V±0.3V, TA=0°C ~70°C)
Item
Conditions
Output Reference Level
1.4V/1.4V
Output Load
See diagram as below
Input Signal Level
2.4V/0.4V
Transition Time of Input Signals
2ns
Input Reference Level
1.4V
AC Operating Test Characteristics
(VDD=3.3V±0.3V, TA=0°C ~70°C)
Symbol
-6
Parameter
CL=3
Min.
6
CL=2
10
-7
Max.
Min.
7
Max.
-7.5
Min. Max.
7.5
Units
tCK
Clock Cycle Time
tAC
Access Time form CLK
tCH
CLK High Level Width
2
2
2
ns
tCL
CLK Low Level Width
2
2
2
ns
tOH
Data-out Hold Time
2
2
2
tHZ
Data-out High Impedance
(Note 5)
Time
tLZ
Data-out Low Impedance Time
0
0
0
ns
tIH
Input Hold Time
1
1
1
ns
tIS
Input Setup Time
1.5
2
2
ns
10
10
CL=3
5.5
5.5
6
CL=2
5
6
6
CL=3
6
7
7
CL=2
ns
ns
CL=2
CL=3
ns
ns
* All voltages referenced to VSS.
Note 5: tHZ defines the time at which the output achieve the open circuit condition and is not referenced to
output voltage levels.
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EM484M3244VTA
AC Operating Test Characteristics (Continued)
(VDD=3.3V±0.3V, TA=0°C ~70°C)
Symbol
tRC
tRAS
tRP
tRCD
tRRD
Parameter
-6
Min.
ACTIVE to ACTIVE Command
(Note 6)
Period
ACTIVE to PRECHARGE
(Note 6)
Command Period
PRECHARGE to ACTIVE
(Note 6)
Command Period
ACTIVE to READ/WRITE Delay
(Note 6)
Time
ACTIVE(one) to ACTIVE(another)
(Note 6)
Command
-7
Max.
60
42
Min.
Max.
65
100k
45
-75
Min. Max.
67
100k
45
Units
ns
100k
ns
18
18
18
ns
18
18
18
ns
12
14
16
ns
tCCD
READ/WRITE Command to
READ/WRITE Command
1
1
1
CLK
tDPL
Date-in to PRECHARGE
Command
2
2
2
CLK
1
1
1
CLK
3
3
3
2
2
2
tBDL
tROH
tREF
Date-in to BURST Stop Command
Data-out to High
CL=3
Impedance from
CL=2
PRECHARGE Command
Refresh Time (4,096 cycle)
64
64
CLK
64
ms
* All voltages referenced to VSS.
Note 6: These parameters account for the number of clock cycles and depend on the operating frequency
of the clock, as follows:
The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole
number)
Recommended Power On and Initialization
The following power on and initialization sequence guarantees the device is preconditioned to each user’s
specific needs. (Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on
voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. (CLK signal started at same
time)
After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the
precharge command.
To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be
held high during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR)
are also required, and these may be done before or after programming the Mode Register.
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EM484M3244VTA
SE
LF
Ex
it
SE
LF
Simplified State Diagram
E
CK
E
CK
ACT
T
BS ad
e
wit
PR
E
h
Wr
i te
wit
h
R
ad
Re
E
PR
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EM484M3244VTA
Address Input for Mode Register Set
BA1
BA0
A11
A10
A9
A8
A7
A6
Operation Mode
A5
A4
A3
CAS Latency
A2
BT
A1
A0
Burst Length
Burst Length
Sequential
Interleave
A2
A1
A0
1
1
0
0
0
2
2
0
0
1
4
4
0
1
0
8
8
0
1
1
Reserved
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Full Page
Reserved
1
1
1
Burst Type
A3
Interleave
1
Sequential
0
CAS Latency
A6
A5
A4
Reserved
0
0
0
Reserved
0
0
1
2
0
1
0
3
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
BA1
BA0
A11
A10
A9
A8
A7
Operation Mode
0
0
0
0
0
0
0
Normal
0
0
0
0
1
0
0
Burst Read with Single-bit Write
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EM484M3244VTA
Burst Type (A3)
Burst Length
2
4
8
A2
A1
A0
Sequential Addressing
Interleave Addressing
X
X
0
01
01
X
X
0
10
10
X
0
0
0123
0123
X
0
1
1230
1032
X
1
0
2301
2301
X
1
1
3012
3210
0
0
0
01234567
01234567
0
0
1
12345670
10325476
0
1
0
23456701
23016745
0
1
1
34567012
32107654
1
0
0
45670123
45670123
1
0
1
56701234
54761032
1
1
0
67012345
67452301
1
1
1
70123456
76543210
Full Page*
n
n
n
Cn Cn+1 Cn+2……
* Page length is a function of I/O organization and column addressing ×32 (CA0 ~ CA7):
Full page = 256bits
-
1. Command Truth Table
Command
Symbol
CKE
n-1 n
H X
/CS
/RAS
/CAS
/WE
BA0,
BA1
A10
A11,
A9~A10
H
X
X
X
X
X
X
Ignore Command
DESL
No Operation
NOP
H
X
L
H
H
H
X
X
X
Burst Stop
BSTH
H
X
L
H
H
L
X
X
X
Read
READ
H
X
L
H
L
H
V
L
V
READA
H
X
L
H
L
H
V
H
V
Write
WRIT
H
X
L
H
L
L
V
L
V
Write with Auto Pre-charge
Read with Auto Pre-charge
WRITA
H
X
L
L
H
H
V
H
V
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Pre-charge Select Bank
PRE
H
X
L
L
H
L
V
L
X
Pre-charge All Banks
PALL
H
X
L
L
H
L
X
H
X
L
V
Mode Register Set
MRS
H X
L
L
L
L
L
H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
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EM484M3244VTA
2. DQM Truth Table
Command
CKE
Symbol
n-1
n
/CS
Data Write/Output Enable
ENB
H
X
H
Data Mask/Output Disable
MASK
H
X
L
Upper Byte Write Enable/Output Enable
BSTH
H
X
L
Read
READ
H
X
L
READA
H
X
L
Write
WRIT
H
X
L
Write with Auto Pre-charge
WRITA
H
X
L
Bank Activate
ACT
H
X
L
Pre-charge Select Bank
PRE
H
X
L
Pre-charge All Banks
PALL
H
X
Read with Auto Pre-charge
L
Mode Register Set
MRS
H
X
H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
L
3. CKE Truth Table
Item
Activating
Any
Clock
Suspend
Idle
Command
Symbol
Clock Suspend Mode Entry
Clock Suspend Mode
Clock Suspend Mode Exit
CKE
n-1 n
H
L
L
L
/CS
/RAS
/CAS
/WE
Addr.
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
CBR Refresh Command
REF
H
H
L
L
L
H
X
Idle
Self Refresh Entry
SELF
H
L
L
L
L
L
H
X
Self Refresh
Self Refresh Exit
H
L
H
H
H
X
L
H
H
X
X
X
X
Idle
Power Down Entry
H
L
X
X
X
X
X
X
X
X
X
Power Down
Power Down Exit
L
H
X
Remark H = High level, L = Low level, X = High or Low level (Don't care)
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EM484M3244VTA
4. Operative Command Table (Note 7)
Current
State
Idle
Row
Active
Read
/CS
/R
/C
/W
Addr.
Command
Action
H
X
X
X
X
DESL
Nop or power down
L
H
H
X
X
NOP or BST
Nop or power down
L
H
L
H
BA/CA/A10
READ/READA
ILLEGAL
L
L
L
H
L
L
L
H
H
L
H
L
BA/CA/A10
BA/RA
BA, A10
WRIT/WRITA
ACT
PRE/PALL
L
L
L
H
X
REF/SELF
ILLEGAL
Row activating
Nop
Refresh or self refresh
L
H
L
L
L
X
H
H
L
X
H
L
L
X
X
H
Op-Code
X
X
BA/CA/A10
MRS
DESL
NOP or BST
READ/READA
Mode register accessing
Nop
Nop
(Note 11)
Begin read: Determine AP
L
H
L
L
BA/CA/A10
WRIT/WRITA
Begin write: Determine AP
(Note 9)
(Note 8)
(Note 8)
(Note 9)
(Note 9)
(Note 10)
(Note 11)
L
L
H
H
BA/RA
ACT
L
L
H
L
BA, A10
PRE/PALL
Pre-charge
L
L
H
L
L
L
L
X
H
H
L
L
X
H
H
H
L
X
H
L
X
Op-Code
X
X
X
REF/SELF
MRS
DESL
NOP
BST
L
H
L
H
BA/CA/A10
READ/READA
ILLEGAL
ILLEGAL
Continue burst to end → Row active
Continue burst to end → Row active
Burst stop → Row active
Terminate burst, new read:
(Note 13)
Determine AP
L
L
L
L
BA/CA/A10
WRIT/WRITA
L
L
H
H
BA/RA
ACT
L
L
H
L
BA, A10
PRE/PALL
L
L
L
L
L
L
H
L
X
Op-Code
REF/SELF
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA/CA/A10
READ/READA
L
L
L
L
BA/CA/A10
WRIT/WRITA
L
L
H
H
BA/RA
ACT
L
L
H
L
BA, A10
PRE/PALL
Write
ILLEGAL
(Note 12)
(Note 10)
Terminate burst, start write:
(Note 13, 14)
Determine AP
ILLEGAL
(Note 9)
Terminate burst, pre-charging
(Note 10)
ILLEGAL
ILLEGAL
Continue burst to end → Write
recovering
Continue burst to end → Write
recovering
Burst stop → Row active
Terminate burst, start read:
(Note 13, 14)
Determine AP 7, 8
Terminate burst, new write:
(Note 13)
Determine AP 7
ILLEGAL
(Note 9)
Terminate burst, pre-charging
(Note 15)
ILLEGAL
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care)
L
L
L
L
L
L
H
L
X
Op-Code
REF/SELF
MRS
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EM484M3244VTA
4. Operative Command Table (Continued) (Note 7)
Current
State
Read with
AP
Write with
AP
Pre-charging
Row
Activating
/CS
/R
/C
/W
Addr.
Command
Action
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
L
H
H
H
L
L
H
X
BA/CA/A10
BST
READ/READA
Continue burst to end →
Pre-charging
Continue burst to end →
Pre-charging
ILLEGAL
(Note 9)
ILLEGAL
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA/RA
ACT
ILLEGAL
L
L
L
L
L
L
H
L
L
L
H
L
BA, A10
X
Op-Code
PRE/PALL
REF/SELF
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
L
H
H
H
L
L
H
X
BA/CA/A10
BST
READ/READA
ILLEGAL
ILLEGAL
ILLEGAL
Burst to end → Write recovering
with auto pre-charge
Continue burst to end → Write
recovering with auto pre-charge
ILLEGAL
(Note 9)
ILLEGAL
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA/RA
ACT
ILLEGAL
L
L
L
H
L
L
L
L
L
L
X
H
H
H
H
L
L
X
H
H
L
L
H
L
X
H
L
H
BA, A10
X
Op-Code
X
X
X
BA/CA/A10
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter idle after tRP
Nop → Enter idle after tRP
ILLEGAL
(Note 9)
ILLEGAL
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL
L
L
L
L
H
L
L
L
L
L
L
L
X
H
H
H
H
H
L
L
X
H
H
L
H
L
H
L
X
H
L
H
BA/RA
BA, A10
X
Op-Code
X
X
X
BA/CA/A10
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
ILLEGAL
Nop → Enter idle after tRP
ILLEGAL
ILLEGAL
Nop → Enter idle after tRCD
Nop → Enter idle after tRCD
ILLEGAL
(Note 9)
ILLEGAL
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA/RA
ACT
ILLEGAL
L
L
L
L
L
L
H
L
L
L
H
L
BA, A10
X
Op-Code
PRE/PALL
REF/SELF
MRS
(Note 9)
(Note 9)
(Note 9)
(Note 9)
(Note 9)
(Note 9)
(Note 9)
(Note 9)
(Note 9)
(Note 9, 16)
(Note 9)
ILLEGAL
ILLEGAL
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
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4. Operative Command Table (Continued) (Note 7)
Current
State
Write
Recovering
Write
Recovering
with AP
Refreshing
Mode
Register
Accessing
/CS
/R
/C
/W
Addr.
Command
Action
H
L
L
L
L
X
H
H
H
H
X
H
H
L
L
X
H
L
H
L
X
X
X
BA/CA/A10
BA/CA/A10
DESL
NOP
BST
READ/READA
WRIT/WRITA
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Start read, Determine AP
(Note 14)
New write, Determine AP
L
L
H
H
BA/RA
ACT
L
L
L
H
L
L
L
L
L
L
X
H
H
H
H
L
L
X
H
H
L
L
H
L
X
H
L
H
BA, A10
X
Op-Code
X
X
X
BA/CA/A10
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter pre-charge after tDPL
Nop → Enter pre-charge after tDPL
Nop → Enter pre-charge after tDPL
(Note 9, 14)
ILLEGAL
L
H
L
L
BA/CA/A10
WRIT/WRITA
ILLEGAL
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
X
H
H
L
L
X
H
H
H
H
H
L
L
X
H
L
H
L
X
H
H
L
H
L
H
L
X
X
X
X
X
X
H
L
X
BA/RA
BA, A10
X
Op-Code
X
X
X
X
X
X
X
X
X
L
L
X
X
X
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP/BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
NOP
BST
READ/WRIT
ACT/PRE/PALL/
REF/SELF/MRS
ILLEGAL
(Note 9)
(Note 9)
(Note 9)
(Note 9)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter idle after tRC
Nop → Enter idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Nop
ILLEGAL
ILLEGAL
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
Note 7: All entries assume that CKE was active (High level) during the preceding clock cycle.
Note 8: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode.
All input buffers except CKE will be disabled.
Note 9: Illegal to bank in specified states;
Function may be legal in the bank indicated by Bank Address (BA), depending on the state of
that bank.
Note 10: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode.
All input buffers except CKE will be disabled.
Note 11: Illegal if tRCD is not satisfied.
Note 12: Illegal if tRAS is not satisfied.
Note 13: Must satisfy burst interrupt condition.
Note 14: Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Note 15: Must mask preceding data which don't satisfy tDPL.
Note 16: Illegal if tRRD is not satisfied.
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5. Command Truth Table for CKE
Current State
Self Refresh
Self Refresh
Recovery
Power Down
Both Banks
Idle
CKE
n-1
n
Any State Other
than Listed above
/R
/C
/W
Addr.
H
X
X
X
X
X
X
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
L
L
H
L
L
L
X
H
L
L
L
H
L
L
L
X
H
H
L
X
X
H
H
L
X
H
H
L
X
H
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
L
L
L
X
X
H
L
L
L
L
H
L
L
L
X
X
X
H
L
L
L
X
H
L
L
X
X
X
X
H
L
L
X
X
H
L
X
X
X
X
X
H
L
X
X
X
H
X
X
L
L
L
L
Op-Code
H
Row Active
/CS
L
Action
INVALID, CLK(n-1) would exit self
refresh
Self refresh recovery
Self refresh recovery
ILLEGAL
ILLEGAL
Maintain self refresh
Idle after tRC
Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
INVALID, CLK(n-1) would exit
power down
Exit power down → Idle
Maintain power down mode
Refer to operations in Operative
Command Table
X
Op-Code
Refresh
Refer to operations in Operative
Command Table
X
L
X
X
X
X
X
X
H
X
X
X
X
X
X
L
X
X
X
X
X
X
H
H
X
X
X
X
H
L
X
X
X
X
X
(Note 17)
Self refresh
Refer to operations in Operative
Command Table
(Note 17)
Power down
Refer to operations in Operative
Command Table
(Note 17)
Power down
Refer to operations in Operative
Command Table
Begin clock suspend next cycle
(Note 18)
Exit clock suspend next cycle
Maintain clock suspend
Remark: H = High level, L = Low level, X = High or Low level (Don't care)
Notes 17: Self refresh can be entered only from the both banks idle state.
Power down can be entered only from both banks idle or row active state.
Notes 18: Must be legal command as defined in Operative Command Table
L
L
H
L
X
X
X
X
X
X
Jul. 2006
X
X
X
X
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EM484M3244VTA
Package Description
DIM
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
−
−
1.20
−
−
0.047
A1
0.05
−
0.15
0.002
−
0.006
A2
0.90
1.00
1.10
0.035
0.039
0.043
b
0.17
0.20
0.27
0.007
0.008
0.011
c
0.09
0.125
0.2
0.004
0.005
0.008
D
22.12
22.22
22.32
0.871
0.875
0.879
e
0.50 BASIC
0.020 BASIC
E
11.56
11.76
11.96
0.455
0.463
0.471
E1
10.03
10.16
10.29
0.395
0.400
0.405
L
0.40
0.50
0.60
0.016
0.020
0.024
R
0.12
−
0.25
0.005
−
0.010
R1
0.12
0.005
−
−
−
−
* Controlling dimension: millimeters
* Dimension D does not include mold protrusion. Mold protrusion shall not exceed 0.15mm
(0.006”) per side. Dimension E1 does not include interlead protrusion. Interlead protrusion
shall not exceed 0.25mm (0.01”) per side.
* Dimension b does not include dambar protrusions/intrusion. Allowable dambar protrusion shall
not cause the lead to be wider than the MAX b dimension by more than 0.13mm. Dambar
intrusion shall not cause the lead to be narrower than the MIN b dimension by more than
0.07mm.
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