EMLSI EM6160FU8AW-85S

EM640FP16 Series
Low Power, 256Kx16 SRAM
Document Title
256K x16 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
History
Draft Date
0.0
Initial Draft
October 24 , 2002
0.1
2’nd Draft
Changed Icc, Icc1 value
November 11 , 2002
0.2
3’rd Draft
Changed ISB1 test conditions,
December 23 , 2002
Remark
Preliminary
Changed VDR & IDR
measurement condition
0.3
4’th Draft
0.4
5’th Draft
Add Pb-free part number
EM640FP16:
February 13 , 2004
April 11 , 2006
Changed Icc2 value
Changed Package Dimension
Emerging Memory & Logic Solutions Inc.
IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160
Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM640FP16 Series
Low Power, 256Kx16 SRAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The EM640FP16 families are fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The families also supports low data retention voltage for battery
back-up operation with low data retention current.
Process Technology : 0.18µm Full CMOS
Organization : 256K x 16 bit
Power Supply Voltage : 1.65V ~ 2.2V
Low Data Retention Voltage : 1.0V(Min.)
Three state outputs
Package Type : 48-FPBGA 6.0x7.0
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc
Range
Industrial (-40 ~ 85oC)
EM640FP16
Speed
Standby
(ISB1, Typ.)
1 µA
70ns1)
1.65~2.2V
PKG
Type
Operating
(ICC1.Max)
48-FPBGA
(6.0x7.0)
2 mA
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
CS2
B
I/O9
UB
A3
A4
CS1
I/O1
Pre-charge Circuit
I/O10 I/O 11
A5
A6
I/O2
I/O3
D
VSS
I/O 12
A17
A7
I/O4
VCC
E
V CC
I/O 13
DNU
A16
I/O5
VSS
VCC
Row Select
C
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O15 I/O 14
A14
A15
I/O6
I/O7
G
I/O16 DNU
A12
A13
WE
I/O8
H
DNU
A9
A10
A11
DNU
A8
UB
LB
Name
Function
CS1
CS2
CS1,CS2
Chip select inputs
Vcc
Power Supply
OE
Output Enable input
Vss
Ground
WE
Write Enable input
UB
Upper Byte (I/O9~16)
Address Inputs
LB
Lower Byte (I/O1~8)
A 0~A17
I/O 1~I/O16 Data Inputs/outputs
DNU
I/O Circuit
Column Select
A11 A12 A13 A14 A15 A16 A17
WE
OE
Function
Data
Cont
Data
Cont
48-FPBGA : Top view (ball down)
Name
2048 x 2048
A10
I/O1 ~ I/O8
I/O9 ~ I/O16
F
VSS
Memory Array
Do Not Use
2
Control Logic
EM640FP16 Series
Low Power, 256Kx16 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Symbol
Voltage on Any Pin Relative to Vss
Minimum
Unit
VIN, VOUT
-0.5 to 2.5V
V
Voltage on Vcc supply relative to Vss
VCC
-0.3 to 2.5V
V
Power Dissipation
PD
1.0
W
Operating Temperature
TA
-40 to 85
oC
* Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
LB
UB
I/O1-8
I/O9-16
Mode
Power
H
X
X
X
X
X
High-Z
High-Z
Deselected
Stand by
X
L
X
X
X
X
High-Z
High-Z
Deselected
Stand by
X
X
X
X
H
H
High-Z
High-Z
Deselected
Stand by
L
H
H
H
L
X
High-Z
High-Z
Output Disabled
Active
L
H
H
H
X
L
High-Z
High-Z
Output Disabled
Active
L
H
L
H
L
H
Data Out
High-Z
Lower Byte Read
Active
L
H
L
H
H
L
High-Z
Data Out
Upper Byte Read
Active
L
H
L
H
L
L
Data Out
Data Out
Word Read
Active
L
H
X
L
L
H
Data In
High-Z
Lower Byte Write
Active
L
H
X
L
H
L
High-Z
Data In
Upper Byte Write
Active
L
H
X
L
L
L
Data In
Data In
Word Write
Active
Note: X means don’t care. (Must be low or high state)
3
EM640FP16 Series
Low Power, 256Kx16 SRAM
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
1.
2.
3.
4.
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
1.65
1.8
2.2
V
Ground
VSS
0
0
0
V
Input high voltage
VIH
1.4
-
VCC + 0.32)
V
Input low voltage
VIL
-0.33)
-
0.4
V
TA= -40 to 85oC, otherwise specified
Overshoot: VCC +1.0 V in case of pulse width < 20ns
Undershoot: -1.0 V in case of pulse width < 20ns
Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Ouput capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
ILI
VIN =VSS to VCC
-1
-
1
uA
Output leakage current
ILO
CS1=V IH, CS2=VIL or OE=V IH or WE=VIL or LB=UB=VIH
VIO=V SS to VCC
-1
-
1
uA
Operating power supply
ICC
IIO=0mA, CS1=VIL, CS2=WE=VIH , VIN=V IH or VIL
-
-
2
mA
ICC1
Cycle time=1µs, 100% duty, ILO=0mA,
CS1<0.2V, LB<0.2V or/and UB<0.2V, CS2>VCC-0.2V
VIN<0.2V or V IN>VCC -0.2V
-
-
2
mA
ICC2
Cycle time = Min, IIO=0mA, 100% duty,
CS1=VIL, CS2=V IH , LB=V IL or/and UB=VIL
VIN =V IL or VIH
-
-
15
mA
Output low voltage
VOL
IOL = 0.1mA
-
-
0.2
V
Output high voltage
VOH
IOH = -0.1mA
1.4
-
-
V
ISB1
CS1>V CC-0.2V, CS2>VCC-0.2V (CS 1 controlled)
or 0V<CS2<0.2V (CS2 controlled),
Other inputs = 0 ~ VCC
-
1
5
uA
Average operating current
Standby Current (CMOS)
(Typ. condition : VCC =1.8V @ 25oC)
(Max. condition : V CC=2.2V @ 85oC)
4
LL
LF
EM640FP16 Series
Low Power, 256Kx16 SRAM
VTM3)
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
R12)
Input Pulse Level : 0.2 to VCC-0.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 0.9V
Output Load (See right) : CL = 100pF+ 1 TTL
CL1) = 30pF + 1 TTL
1. Including scope and Jig capacitance
R2=3150 ohm
2. R 1=3070 ohm,
3. VTM =1.8V
R22)
CL1)
READ CYCLE (Vcc =1.65 to 2.2V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
70ns
Min
Max
Unit
Read Cycle Time
tRC
70
-
ns
Address Access Time
tAA
-
70
ns
Chip Select to output
tco1, tco2
-
70
ns
Output Enable to valid output
tOE
-
35
ns
UB, LB Acess time
tBA
70
ns
tLZ1, tLZ2
10
-
ns
UB, LB enable to low-Z output
tBLZ
10
-
ns
Output Enable to Low-Z output
tOLZ
5
-
ns
tHZ1, tHZ2
0
25
ns
UB, LB disable to high-Z output
tBHZ
0
25
ns
Output disable to high-Z output
tOHZ
0
25
ns
Output hold from address change
tOH
10
-
ns
Chip select to low-Z output
Chip disable to high-Z output
WRITE CYCLE (Vcc =1.65 to 2.2V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
70ns
Unit
Min
Max
tWC
70
-
ns
tCW1, tCW2
60
-
ns
Address Setup time
tAs
0
-
ns
Address valid to end of write
tAW
60
-
ns
UB, LB valid to end of write
tBW
60
-
ns
Write pulse width
tWP
55
-
ns
Write recovery time
tWR
0
-
ns
Write to ouput high-Z
tWHZ
0
25
ns
Data to write time overlap
tDW
30
Data hold from write time
tDH
0
-
ns
End write to output low-Z
tOW
5
-
ns
Write Cycle Time
Chip Select to end of write
5
ns
EM640FP16 Series
Low Power, 256Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC
Address
tAA
tOH
tCO
CS1
CS2
tHZ
tBA
UB,LB
tBHZ
tOE
OE
tOHZ
tOLZ
Data Out
High-Z
Data Valid
tBLZ
tWHZ
tLZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
EM640FP16 Series
Low Power, 256Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC
Address
tCW(2)
tWR(4)
CS1
CS2
tAW
tBW
UB,LB
tWP(1)
WE
tAS(3)
Data in
tDH
tDW
High-Z
High-Z
Data Valid
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
CS2
tAW
tBW
UB,LB
tWP(1)
WE
tDW
Data in
Data out
Data Valid
High-Z
High-Z
7
tDH
EM640FP16 Series
Low Power, 256Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
tWC
Address
tCW(2)
tWR(4)
CS1
CS2
tAW
tBW
UB,LB
tWP(1)
tAS(3)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double
byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is
measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1
or WE going high.
8
EM640FP16 Series
Low Power, 256Kx16 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
Symbol
VCC for Data Retention
V DR
Data Retention Current
IDR
Chip Deselect to Data Retention Time
tSDR
Test Condition
ISB1 Test Condition
(Chip Disabled) 1)
VCC=1.2V, ISB1 Test Condition
(Chip Disabled) 1)
Min
Typ
Max
Unit
1.0
-
2.2
V
-
0.5
2
uA
0
-
-
tRC
-
-
See data retention wave form
Operation Recovery Time
tRDR
ns
NOTES
1. See the ISB1 measurement condition of datasheet page 4.
DATA RETENTION WAVE FORM
tSDR
Data Retention Mode
tRDR
Vcc
1.65V
1.4V
VDR
CS1 > Vcc-0.2V
CS1
GND
Data Retention Mode
Vcc
1.65V
CS2
tRDR
tSDR
VDR
0.4V
CS 2 < 0.2V
GND
9
EM640FP16 Series
Low Power, 256Kx16 SRAM
Unit: millimeters
PACKAGE DIMENSION
48 Ball Fine Pitch BGA (0.75mm ball pitch)
Bottom View
Top View
A1 index Mark
B
B1
6
5
4
3
0.4
2
0.4
B
1
A
B
#A1
C
C1
C
C
D
C1/2
E
F
G
H
B/2
Detail A
D
E2
0.26
Side View
0.27Typ.
E
E1
A
Min
Typ
Max
A
-
0.75
-
B
5.95
6.00
6.05
B1
-
3.75
-
C
6.95
7.00
7.05
C1
-
5.25
-
D
0.30
0.35
0.40
E
-
0.85
0.90
E1
-
0.58
-
E2
-
0.27
-
Y
-
-
0.08
Y
0.58Typ.
C
NOTES.
1. Bump counts : 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75x0.75) (typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity : 0.08(Max)
10
EM640FP16 Series
Low Power, 256Kx16 SRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
11. Power
2. Device Type
10. Speed
3. Density
4. Option
9. Packages
5. Technology
8. Version
6. Operating Voltage
7. Orgainzation
8. Version
Blank ----------------- Mother die
A ----------------------- First version
B ----------------------- Second version
C ----------------------- Third version
D ----------------------- Fourth version
E ----------------------- Fifth version
1. Memory Component
2. Device Type
6 ------------------------ Low Power SRAM
7 ------------------------ Pseudo SRAM
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
9. Package
Blank ---------------------- Package
W --------------------- Wafer
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 --------------------- 100ns
12 --------------------- 120ns
4. Option
0 ----------------------- Dual CS
1 ----------------------- Single CS
5. Technology
Blank ------------------ CMOS
F ------------------------ Full CMOS
11. Power
LL ------------ Low Low Power
LF ------------ Low Low Power(Pb-Free & Green)
L ------------- Low Power
S ------------- Standard Power
6. Operating Voltage
Blank ------------------- 5V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
7. Orginzation
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
11