ETC2 EM680FT8GS-70S 512k x16 bit low power and low voltage full cmos static ram Datasheet

EM681FV16AU Series
Low Power, 512Kx16 SRAM
Document Title
512K x16 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History2.1
Revision No.
History
Draft Date
Remark
0.0
Initial Draft
Oct. 26, 2006
Preliminary
0.1
0.1 Revision
Production code change from
EM681FV16U-45LL to
EM681FV16U-45LF
Jan. 18, 2007
0.2
0.2 Revision
Production code change from
EM681FV16U-45LF to
EM681FV16AU-45LF
April. 10, 2007
0.3
0.3 Revision
Product code table update
June 15, 2007
0.4
0.4 Revision
Fix typo error
Nov. 12, 2007
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Zip Code : 690-719
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM681FV16AU Series
Low Power, 512Kx16 SRAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The EM681FV16AU is fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The families also supports low data retention voltage for battery
back-up operation with low data retention current.
Process Technology : 0.15µm Full CMOS
Organization : 512K x 16 bit
Power Supply Voltage : 2.7V ~ 3.6V
Low Data Retention Voltage : 1.5V (Min.)
Three state output and TTL Compatible
Package Type : 44-TSOP2
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc Range
Speed
Standby
(ISB1, Typ.)
Operating
(ICC1.Max)
PKG Type
EM681FV16AU-45LF
Industrial (-40 ~ 85oC)
2.7V~3.6V
45ns
2 µA
4mA
44-TSOP2
EM681FV16AU-55LF
Industrial (-40 ~ 85oC)
2.7V~3.6V
55ns
2 µA
4mA
44-TSOP2
EM681FV16AU-70LF
Industrial (-40 ~ 85oC)
2.7V~3.6V
70ns
2 µA
4mA
44-TSOP2
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Pre-charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
Row Select
VCC
I/O0 ~ I/O7
Data
Cont
Data
Cont
I/O8 ~ I/O15
VSS
Memory Array
2048 x 4096
I/O Circuit
Column Select
A11 A12 A13 A14 A15 A16 A17 A18
44-TSOP2 : Top view
Name
Function
Name
Function
CS
Chip select inputs
Vcc
Power Supply
OE
Output Enable input
Vss
Ground
WE
Write Enable input
UB
Upper Byte (I/O8~15)
Address Inputs
LB
Lower Byte (I/O0~7)
NC
No Connected
A0~A18
I/O0~I/O15 Data Inputs/outputs
WE
OE
UB
LB
CS
2
Control Logic
EM681FV16AU Series
Low Power, 512Kx16 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Symbol
Minimum
VIN, VOUT
-0.2 to 4.0V
V
Voltage on Vcc supply relative to Vss
VCC
-0.2 to 4.0V
V
Power Dissipation
PD
1.0
W
Operating Temperature
TA
-40 to 85
Voltage on Any Pin Relative to Vss
Unit
o
C
* Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
FUNCTIONAL DESCRIPTION
CS
OE
WE
LB
UB
I/O0-7
I/O8-15
Mode
Power
H
X
X
X
X
High-Z
High-Z
Deselected
Stand by
X
X
X
H
H
High-Z
High-Z
Deselected
Stand by
L
H
H
X
X
High-Z
High-Z
Output Disabled
Active
L
L
H
L
H
Data Out
High-Z
Lower Byte Read
Active
L
L
H
H
L
High-Z
Data Out
Upper Byte Read
Active
L
L
H
L
L
Data Out
Data Out
Word Read
Active
L
X
L
L
H
Data In
High-Z
Lower Byte Write
Active
L
X
L
H
L
High-Z
Data In
Upper Byte Write
Active
L
X
L
L
L
Data In
Data In
Word Write
Active
Note: X means don’t care. (Must be low or high state)
3
EM681FV16AU Series
Low Power, 512Kx16 SRAM
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
Symbol
Min
Supply voltage
VCC
2.7
3.3
3.6
V
Ground
VSS
0
0
0
V
Input high voltage
VIH
2.2
-
VCC + 0.22)
V
Input low voltage
VIL
-0.23)
-
0.6
V
1.
2.
3.
4.
Typ
Max
Unit
TA= -40 to 85oC, otherwise specified
Overshoot: VCC +2.0 V in case of pulse width < 20ns
Undershoot: -2.0 V in case of pulse width < 20ns
Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Ouput capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
ILI
VIN=VSS to VCC
-1
-
1
uA
Output leakage current
ILO
CS=VIH or OE=VIH or WE=VIL or LB=UB=VIH
VIO=VSS to VCC
-1
-
1
uA
Operating power supply
ICC
IIO=0mA, CS=VIL, WE=VIH, VIN=VIH or VIL
-
-
2
mA
ICC1
Cycle time=1µs, 100% duty, IIO=0mA,
CS<0.2V, LB<0.2V or/and UB<0.2V,
VIN<0.2V or VIN>VCC-0.2V
-
-
4
mA
ICC2
Cycle time = Min, IIO=0mA, 100% duty,
CS=VIL, LB=VIL or/and UB=VIL ,
VIN=VIL or VIH
-
-
45
35
25
mA
Output low voltage
VOL
IOL = 2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH = -1.0mA
2.2
-
-
V
Standby Current (TTL)
ISB
CS=VIH, Other inputs=VIH or VIL
-
-
0.5
mA
-
2
15
uA
Average operating current
45ns
55ns
70ns
CS>VCC-0.2V
Standby Current (CMOS)
ISB1
Other inputs=0 ~ VCC
LF
(Typ. condition : VCC=3.3V @ 25oC)
(Max. condition : VCC=3.6V @ 85oC)
4
EM681FV16AU Series
Low Power, 512Kx16 SRAM
AC OPERATING CONDITIONS
VTM3)
Test Conditions (Test Load and Test Input/Output Reference)
R12)
Input Pulse Level : 0.4 to 2.4V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL1) = 100pF + 1 TTL (70nsec)
CL1) = 30pF + 1 TTL (45ns/55ns)
1. Including scope and Jig capacitance
2. R1=3070 ohm,
R2=3150 ohm
3. VTM=2.8V
4. CL = 5pF + 1 TTL (measurement with tLZ, tHZ, tOLZ, tOHZ, tWHZ)
R22)
CL1)
READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
45ns
55ns
70ns
Min
Max
Min
Max
Min
Max
Unit
Read cycle time
tRC
45
-
55
-
70
-
ns
Address access time
tAA
-
45
-
55
-
70
ns
Chip select to output
tco
-
45
-
55
-
70
ns
Output enable to valid output
tOE
-
30
-
35
-
35
ns
UB, LB access time
tBA
70
ns
Chip select to low-Z output
tLZ
5
-
5
-
5
-
ns
UB, LB enable to low-Z output
tBLZ
5
-
5
-
5
-
ns
Output enable to low-Z output
tOLZ
5
-
5
-
5
-
ns
Chip disable to high-Z output
tHZ
0
20
0
20
0
25
ns
UB, LB disable to how-Z output
tBHZ
0
20
0
20
0
25
ns
Output disable to high-Z output
tOHZ
0
20
0
20
0
25
ns
tOH
10
-
10
-
10
-
ns
Output hold from address change
45
55
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
45ns
55ns
70ns
Unit
Min
Max
Min
Max
Min
Max
Write cycle time
tWC
45
-
55
-
70
-
ns
Chip select to end of write
tCW
45
-
45
-
60
-
ns
Address setup time
tAs
0
-
0
-
0
-
ns
Address valid to end of write
tAW
45
-
45
-
60
-
ns
UB, LB valid to end of write
tBW
45
-
45
-
60
-
ns
Write pulse width
tWP
45
-
45
-
55
-
ns
Write recovery time
tWR
0
-
0
-
0
-
ns
Write to ouput high-Z
tWHZ
0
20
0
20
0
25
ns
Data to write time overlap
tDW
25
Data hold from write time
tDH
0
-
0
End write to output low-Z
tOW
5
-
5
30
5
30
-
ns
0
-
ns
5
-
ns
EM681FV16AU Series
Low Power, 512Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS=OE=VIL,
UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC
Address
tAA
tOH
tCO
CS
tHZ
tBA
UB,LB
tBHZ
tOE
OE
tOHZ
tOLZ
Data Out
High-Z
Data Valid
tBLZ
tWHZ
tLZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
EM681FV16AU Series
Low Power, 512Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tBW
UB,LB
tWP(1)
WE
tAS(3)
Data in
tDH
tDW
High-Z
High-Z
Data Valid
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS CONTROLLED)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tBW
UB,LB
tWP(1)
WE
tDW
Data in
Data out
Data Valid
High-Z
High-Z
7
tDH
EM681FV16AU Series
Low Power, 512Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tBW
UB,LB
tAS(3)
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double
byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is
measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS
or WE going high.
8
EM681FV16AU Series
Low Power, 512Kx16 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
Symbol
VCC for Data Retention
VDR
Data Retention Current
IDR
Chip Deselect to Data Retention Time
tSDR
Test Condition
ISB1 Test Condition
(Chip Disabled) 1)
VCC=1.5V, ISB1 Test Condition
(Chip Disabled) 1)
Typ
Max
Unit
1.5
-
3.6
V
-
-
4
uA
0
-
-
tRC
-
-
See data retention wave form
tRDR
Operation Recovery Time
Min
ns
NOTES
1. See the ISB1 measurement condition of data sheet page 4.
DATA RETENTION WAVE FORM
tSDR
Data Retention Mode
Vcc
2.7V
2.2V
VDR
CS > Vcc-0.2V
CS
GND
9
tRDR
EM681FV16AU Series
Low Power, 512Kx16 SRAM
PACKAGE DIMENSION
44 - TSOP2 (0.8mm pin pitch)
10
EM681FV16AU Series
Low Power, 512Kx16 SRAM
SRAM PART CODING SYSTEM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
11. Power
2. Product Type
10. Speed
3. Density
4. Function
9. Package
8. Generation
5. Technology
7. Organization
6. Operating Voltage
7. Organization
8 ---------------------- x8 bit
16 ---------------------- x16 bit
1. Memory Component
EM --------------------- Memory
2. Product Type
6 ------------------------ SRAM
8. Generation
Blank ----------------- 1st generation
A ----------------------- 2nd generation
B ----------------------- 3rd generation
C ----------------------- 4th generation
D ----------------------- 5th generation
E ----------------------- 6th generation
F ----------------------- 7th generation
G ---------------------- 8th generation
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
4. Function
0 ----------------------- Dual CS
1 ----------------------- Single CS
2 ----------------------- Multiplexed
3 ------------- Single CS / LBB, UBB(tBA=tOE)
4 ------------- Single CS / LBB, UBB(tBA=tCO)
5 ------------- Dual CS / LBB, UBB(tBA=tOE)
6 ------------- Dual CS / LBB, UBB(tBA=tCO)
9. Package
Blank ---------------- KGD, 48&36FpBGA
S ---------------------- 32 sTSOP1
T ---------------------- 32 TSOP1
U ---------------------- 44 TSOP2
V ---------------------- 32 SOP
10. Speed
45 ---------------------55 ---------------------70 ---------------------85 ---------------------10 ---------------------12 ----------------------
5. Technology
F ------------------------- Full CMOS
6. Operating Voltage
T ------------------------- 5.0V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
45ns
55ns
70ns
85ns
100ns
120ns
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free & Green)
L ---------------------- Low Power
S ---------------------- Standard Power
11
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