Cirrus EP7312-EB-C High-performance, low-power system-on-chip with sdram and enhanced digital audio interface Datasheet

EP7311 Data Sheet
FEATURES
High-Performance,
Low-Power System on Chip with
SDRAM and Enhanced Digital
Audio Interface
■ ARM720T Processor
— ARM7TDMI CPU
— 8 KB of four-way set-associative cache
— MMU with 64-entry TLB
— Thumb code support enabled
■ Ultra low power
— 90 mW at 74 MHz typical
— 30 mW at 18 MHz typical
— 10 mW in the Idle State
— <1 mW in the Standby State
■ 48 KB of on-chip SRAM
■ MaverickKey™ IDs
OVERVIEW
The Maverick™ EP7311 is designed for ultra-low-power
applications such as PDAs, smart cellular phones, and
industrial hand held information appliances. The corelogic functionality of the device is built around an
ARM720T processor with 8 KB of four-way setassociative unified cache and a write buffer. Incorporated
into the ARM720T is an enhanced memory management
unit (MMU) which allows for support of sophisticated
operating systems like Linux®.
— 32-bit unique ID can be used for SDMI compliance
— 128-bit random ID
■ Dynamically programmable clock speeds of
18, 36, 49, and 74 MHz
(cont.)
(cont.)
BLOCK DIAGRAM
EPB Bus
Serial
Interface
Power
Management
(2) UARTs
w/ IrDA
Clocks &
Timers
ARM720T
ICE-JTAG
Interrupts,
PWM & GPIO
ARM7TDMI CPU Core
8 KB
Cache
Boot
ROM
Write
Buffer
Bus
Bridge
MMU
Keypad&
Touch
Screen I/F
Internal Data Bus
Memory Controller
MaverickKeyT M
SRAM I/F
SDRAM I/F
On-chip SRAM
48 KB
USER INTERFACE
SERIAL PORTS
Multimedia
Codec Port
LCD
Controller
MEMORY AND STORAGE
Copyright Cirrus Logic, Inc. 2003
http://www.cirrus.com
(All Rights Reserved)
Nov ’03
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
FEATURES (cont)
■ LCD controller
— Interfaces directly to a single-scan panel
monochrome STN LCD
— Interfaces to a single-scan panel color STN LCD
with minimal external glue logic
■ Full JTAG boundary scan and Embedded ICE
support
■ Integrated Peripheral Interfaces
— 32-bit SDRAM Interface up to 2 external banks
— 8/32/16-bit SRAM/FLASH/ROM Interface
— Multimedia Codec Port
— Two Synchronous Serial Interfaces (SSI1, SSI2)
— CODEC Sound Interface
— 8×8 Keypad Scanner
— 27 General Purpose Input/Output pins
— Dedicated LED flasher pin from the RTC
■ Internal Peripherals
— Two 16550 compatible UARTs
— IrDA Interface
— Two PWM Interfaces
— Real-time Clock
— Two general purpose 16-bit timers
— Interrupt Controller
— Boot ROM
■ Package
— 208-Pin LQFP
— 256-Ball PBGA
— 204-Ball TFBGA
■ The fully static EP7311 is optimized for low power
dissipation and is fabricated on a 0.25 micron CMOS
process
■ Development Kits
— EDB7312: Development Kit with color STN LCD
on board.
— EDB7312-LW: EDB7312 with Lynuxworks’
BlueCat Linux Tools and software for Windows
host (free 30 day BlueCat support from
Lynuxworks).
— EDB7312-LL: EDB7312 with Lynuxworks’ BlueCat
Linux Tools and software for Linux host (free 30
day BlueCat support from Lynuxworks).
Note:
* BlueCat available separately through Lynuxworks
only.
* Use the EDB7312 Development Kit for all the EP73xx
devices.
OVERVIEW (cont.)
The EP7311 is designed for low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation
range of 2.5 V–3.3 V. The device has three basic power
states: operating, idle and standby.
Simply by adding desired memory and peripherals to the
highly integrated EP7311 completes a low-power system
solution. All necessary interface logic is integrated onchip.
One of its notable features is MaverickKey unique IDs.
These are factory programmed IDs in response to the
growing concern over secure web content and commerce.
With Internet security playing an important role in the
delivery of digital media such as books or music,
traditional software methods are quickly becoming
unreliable. The MaverickKey unique IDs consist of two
registers, one 32-bit series register and one random 128bit register that may be used by an OEM for an
authentication mechanism.
2
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Processor Core - ARM720T
Digital Music Initiative) or any other authentication
mechanism.
The EP7311 incorporates an ARM 32-bit RISC
microcontroller that controls a wide range of on-chip
peripherals. The processor utilizes a three-stage pipeline
consisting of fetch, decode and execute stages. Key
features include:
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7311 through the use of laser
probing technology. These IDs can then be used to match
secure copyrighted content with the ID of the target
device the EP7311 is powering, and then deliver the
copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
• ARM (32-bit) and Thumb (16-bit compressed)
instruction sets
• Enhanced MMU for Microsoft Windows CE and other
operating systems
• 8 KB of 4-way set-associative cache.
• Translation Look Aside Buffers with 64 Translated
Entries
Power Management
The EP7311 is designed for ultra-low-power operation.
Its core operates at only 2.5 V, while its I/O has an
operation range of 2.5 V–3.3 V allowing the device to
achieve a performance level equivalent to 60 MIPS. The
device has three basic power states:
• Operating — This state is the full performance
state. All the clocks and peripheral logic are
enabled.
• Idle — This state is the same as the Operating
State, except the CPU clock is halted while
waiting for an event such as a key press.
• Standby — This state is equivalent to the
computer being switched off (no display), and
the main oscillator shut down. An event such as
a key press can wake-up the processor.
Pin Mnemonic
I/O
Pin Description
BATOK
I
Battery ok input
nEXTPWR
I
External power supply sense
input
nPWRFL
I
Power fail sense input
nBATCHG
I
Battery changed sense input
Memory Interfaces
There are two main external memory interfaces. The first
one is the ROM/SRAM/FLASH-style interface that has
programmable wait-state timings and includes burstmode capability, with six chip selects decoding six
256 MB sections of addressable space. For maximum
flexibility, each bank can be specified to be 8-, 16-, or 32bits wide. This allows the use of 8-bit-wide boot ROM
options to minimize overall system cost. The on-chip
boot ROM can be used in product manufacturing to
serially download system code into system FLASH
memory. To further minimize system memory
requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industryleading code density.
Pin Mnemonic
I/O
Pin Description
nCS[5:0]
O
Chip select out
A[27:0]
O
Address output
D[31:0]
I/O
Data I/O
nMOE/nSDCAS
(Note)
O
ROM expansion OP enable
nMWE/nSDWE
(Note)
O
ROM expansion write enable
HALFWORD
O
Halfword access select
output
WORD
O
Word access select output
O
Transfer direction
WRITE/nSDRAS
(Note)
Table A. Power Management Pin Assignments
Table B. Static Memory Interface Pin Assignments
MaverickKey™ Unique ID
Note:
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
DS506PP1
Pins are multiplexed. See Table S on page 8 for more
information.
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
3
EP7311
High-Performance, Low-Power System on Chip
The second is the programmable 16- or 32-bit-wide
SDRAM interface that allows direct connection of up to
two banks of SDRAM, totaling 512 Mb. To assure the
lowest possible power consumption, the EP7311
supports self-refresh SDRAMs, which are placed in a
low-power state by the device when it enters the lowpower Standby State.
Pin Mnemonic
I/O
Pin Description
SDCLK
O
SDRAM clock output
SDCKE
O
SDRAM clock enable output
nSDCS[1:0]
O
SDRAM chip select out
WRITE/nSDRAS
(Note 2)
O
SDRAM RAS signal output
nMOE/nSDCAS
(Note 2)
O
SDRAM CAS control signal
RX/TX signals to/from UART 1 to enable these signals
to drive an infrared communication interface directly.
Pin Mnemonic
I/O
Pin Description
TXD[1]
O
UART 1 transmit
RXD[1]
I
UART 1 receive
CTS
I
UART 1 clear to send
DCD
I
UART 1 data carrier detect
DSR
I
UART 1 data set ready
TXD[2]
O
UART 2 transmit
RXD[2]
I
UART 2 receive
LEDDRV
O
Infrared LED drive output
PHDIN
I
Photo diode input
nMWE/nSDWE
(Note 2)
O
SDRAM write enable control
signal
A[27:15]/DRA[0:12]
(Note 1)
O
SDRAM address
O
SDRAM internal bank select
Multimedia Codec Port (MCP)
I/O
SDRAM byte lane mask
SDQM[3:2]
O
SDRAM byte lane mask
D[31:0]
I/O
Data I/O
The Multimedia Codec Port provides access to an audio
codec, a telecom codec, a touchscreen interface, four
general purpose analog-to-digital converter inputs, and
ten programmable digital I/O lines.
A[14:13]/DRA[12:14]
PD[7:6]/SDQM[1:0]
(Note 2)
Table D. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Table C. SDRAM Interface Pin Assignments
Pin Mnemonic
Note:
1. Pins A[27:13] map to DRA[0:14] respectively.
(i.e. A[27}/DRA[0}, A[26}/DRA[1], etc.) This is to
balance the load for large memory systems.
2. Pins are multiplexed. See Table S on page 8 for
more information.
Digital Audio Capability
I/O
Pin Description
SIBCLK
O
Serial bit clock
SIBDOUT
O
Serial data out
SIBDIN
I
Serial data in
SIBSYNC
O
Sample clock
Table E. MCP Interface Pin Assignments
The EP7311 uses its powerful 32-bit RISC processing
engine to implement audio decompression algorithms in
software. The nature of the on-board RISC processor, and
the availability of efficient C-compilers and other
software development tools, ensures that a wide range of
audio decompression algorithms can easily be ported to
and run on the EP7311
Note:
See Table R on page 8 for information on pin
multiplexes.
Universal Asynchronous
Receiver/Transmitters (UARTs)
The EP7311 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-byte
FIFOs for receiving and transmitting data. The UARTs
support bit rates up to 115.2 kbps. An IrDA SIR protocol
encoder/decoder can be optionally switched into the
4
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
CODEC Interface
Synchronous Serial Interface
The EP7311 includes an interface to telephony-type
CODECs for easy integration into voice-over-IP and
other voice communications systems. The CODEC
interface is multiplexed to the same pins as the MCP and
SSI2.
• ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
• Selectable serial clock polarity
Pin Mnemonic
Pin Mnemonic
I/O
PCMCLK
O
Serial bit clock
PCMOUT
O
Serial data out
PCMIN
I
Serial data in
PCMSYNC
O
Frame sync
O
SSI1 ADC serial clock
ADCIN
I
SSI1 ADC serial input
ADCOUT
O
SSI1 ADC serial output
nADCCS
O
SSI1 ADC chip select
SMPCLK
O
SSI1 ADC sample clock
Table H. Serial Interface Pin Assignments
See Table R on page 8 for information on pin
multiplexes.
LCD Controller
SSI2 Interface
An additional SPI/Microwire1-compatible interface is
available for both master and slave mode
communications. The SSI2 unit shares the same pins as
the MCP and CODEC interfaces through a multiplexer.
•
•
•
•
Synchronous clock speeds of up to 512 kHz
Separate 16 entry TX and RX half-word wide FIFOs
Half empty/full interrupts for FIFOs
Separate RX and TX frame sync signals for
asymmetric traffic
Pin Mnemonic
I/O
Pin Description
SSICLK
I/O
Serial bit clock
SSITXDA
O
Serial data out
SSIRXDA
I
Serial data in
SSITXFR
I/O
Transmit frame sync
SSIRXFR
I/O
Receive frame sync
Table G. SSI2 Interface Pin Assignments
Note:
See Table R on page 8 for information on pin
multiplexes.
DS506PP1
Pin Description
ADCLK
Table F. CODEC Interface Pin Assignments
Note:
I/O
Pin Description
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The
display frame buffer start address is programmable,
allowing the LCD frame buffer to be in SDRAM, internal
SRAM or external SRAM.
• Interfaces directly to a single-scan panel monochrome
STN LCD
• Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
• Panel width size is programmable from 32 to 1024
pixels in 16-pixel increments
• Video frame buffer size programmable up to
128 KB
• Bits per pixel of 1, 2, or 4 bits
Pin Mnemonic
I/O
Pin Description
CL1
O
LCD line clock
CL2
O
LCD pixel clock out
DD[3:0]
O
LCD serial display data bus
FRM
O
LCD frame synchronization pulse
M
O
LCD AC bias drive
Table I. LCD Interface Pin Assignments
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
5
EP7311
High-Performance, Low-Power System on Chip
64-Keypad Interface
.
Pin Mnemonic
Matrix keyboards and keypads can be easily read by the
EP7311. A dedicated 8-bit column driver output
generates strobes for each keyboard column signal. The
pins of Port A, when configured as inputs, can be
selectively OR'ed together to provide a keyboard
interrupt that is capable of waking the system from a
STANDBY or IDLE state.
• Column outputs can be individually set high with the
remaining bits left at high-impedance
• Column outputs can be driven all-low, all-high, or allhigh-impedance
• Keyboard interrupt driven by OR'ing together all Port
A bits
• Keyboard interrupt can be used to wake up the
system
• 8×8 keyboard matrix usable with no external logic,
extra keys can be added with minimal glue logic
Pin Mnemonic
I/O
Pin Description
O
Keyboard scanner column drive
COL[7:0]
Table J. Keypad Interface Pin Assignments
Interrupt Controller
When unexpected events arise during the execution of a
program (i.e., interrupt or memory fault) an exception is
usually generated. When these exceptions occur at the
same time, a fixed priority system determines the order
in which they are handled. The EP7311 interrupt
controller has two interrupt types: interrupt request
(IRQ) and fast interrupt request (FIQ). The interrupt
controller has the ability to control interrupts from 22
different FIQ and IRQ sources.
• Supports 22 interrupts from a variety of sources (such
as UARTs, SSI1, and key matrix.)
• Routes interrupt sources to the ARM720T’s IRQ or
FIQ (Fast IRQ) inputs
• Five dedicated off-chip interrupt lines operate as level
sensitive interrupts
I/O
Pin Description
nEINT[2:1]
I
External interrupt
EINT[3]
I
External interrupt
nEXTFIQ
I
External Fast Interrupt input
I
Media change interrupt input
nMEDCHG/nBROM
(Note)
Table K. Interrupt Controller Pin Assignments
Note:
Pins are multiplexed. See Table S on page 8 for more
information.
Real-Time Clock
The EP7311 contains a 32-bit Real Time Clock (RTC) that
can be written to and read from in the same manner as
the timer counters. It also contains a 32-bit output match
register which can be programmed to generate an
interrupt.
• Driven by an external 32.768 kHz crystal oscillator
Pin Mnemonic
Pin Description
RTCIN
Real-Time Clock Oscillator Input
RTCOUT
Real-Time Clock Oscillator Output
VDDRTC
Real-Time Clock Oscillator Power
VSSRTC
Real-Time Clock Oscillator Ground
Table L. Real-Time Clock Pin Assignments
PLL and Clocking
• Processor and Peripheral Clocks operate from a single
3.6864 MHz crystal or external 13 MHz clock
• Programmable clock speeds allow the peripheral bus
to run at 18 MHz when the processor is set to 18 MHz
and at 36 MHz when the processor is set to 36, 49 or
74 MHz
Pin Mnemonic
Pin Description
MOSCIN
Main Oscillator Input
MOSCOUT
Main Oscillator Output
VDDOSC
Main Oscillator Power
VSSOSC
Main Oscillator Ground
Table M. PLL and Clocking Pin Assignments
6
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
DC-to-DC converter interface (PWM)
Hardware debug Interface
• Provides two 96 kHz clock outputs with
programmable duty ratio (from 1-in-16 to 15-in-16)
that can be used to drive a positive or negative DC to
DC converter
• Full JTAG boundary scan and Embedded ICE
support
Pin Mnemonic
Pin Mnemonic
DRIVE[1:0]
I/O
I/O
FB[1:0]
I
Pin Description
PWM drive output
PWM feedback input
Table N. DC-to-DC Converter Interface Pin Assignments
Pin Description
TCLK
I
JTAG clock
TDI
I
JTAG data input
TDO
O
JTAG data output
nTRST
I
JTAG async reset input
TMS
I
JTAG mode select
Timers
Table P. Hardware Debug Interface Pin Assignments
• Internal (RTC) timer
• Two internal 16-bit programmable hardware countdown timers
General Purpose Input/Output (GPIO)
• Three 8-bit and one 3-bit GPIO ports
• Supports scanning keyboard matrix
Pin Mnemonic
I/O
Pin Description
PA[7:0]
I/O
GPIO port A
PB[7:0]
I/O
GPIO port B
I/O
GPIO port D
I/O
GPIO port D
(Note)
I/O
GPIO port D
PE[1:0]/BOOTSEL[1:0] (Note)
I/O
GPIO port E
PE[2]/CLKSEL
I/O
GPIO port E
PD[0]/LEDFLSH
(Note)
PD[5:1]
PD[7:6]/SDQM[1:0]
(Note)
LED Flasher
A dedicated LED flasher module can be used to generate
a low frequency signal on Port D pin 0 for the purpose of
blinking an LED without CPU intervention. The LED
flasher feature is ideal as a visual annunciator in battery
powered applications, such as a voice mail indicator on a
portable phone or an appointment reminder on a PDA.
•
•
•
•
Software adjustable flash period and duty cycle
Operates from 32 kHz RTC clock
Will continue to flash in IDLE and STANDBY states
4 mA drive current
Pin Mnemonic
PD[0]/LEDFLSH
(Note)
I/O
O
Pin Description
LED flasher driver
Table Q. LED Flasher Pin Assignments
Table O. General Purpose Input/Output Pin Assignments
Note:
I/O
Pins are multiplexed. See Table S on page 8 for more
information.
Note:
Pins are multiplexed. See Table S on page 8 for more
information.
Internal Boot ROM
The internal 128 byte Boot ROM facilitates download of
saved code to the on-board SRAM/FLASH.
Packaging
The EP7311 is available in a 208-pin LQFP package, 256ball PBGA package or a 204-ball TFBGA package.
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
7
EP7311
High-Performance, Low-Power System on Chip
Pin Multiplexing
The following table shows the pin multiplexing of the
MCP, SSI2 and the CODEC. The selection between SSI2
and the CODEC is controlled by the state of the SERSEL
bit in SYSCON2. The choice between the SSI2, CODEC,
and the MCP is controlled by the MCPSEL bit in
SYSCON3 (see the EP73xx User’s Manual for more
information).
Pin
Mnemonic
I/O
MCP
SSI2
CODEC
SSICLK
I/O
SIBCLK
SSICLK
PCMCLK
SSITXDA
O
SIBDOUT
SSITXDA
PCMOUT
SSIRXDA
I
SIBDIN
SSIRXDA
PCMIN
SSITXFR
I/O
SIBSYNC
SSITXFR
PCMSYNC
SSIRXFR
I
p/u
SSIRXFR
p/u
BUZ
O
Table R. MCP/SSI2/CODEC Pin Multiplexing
The following table shows the pins that have been
multiplexed in the EP7311.
Signal
Block
Signal
Block
nMOE
Static Memory
nSDCAS
SDRAM
nMWE
Static Memory
nSDWE
SDRAM
WRITE
Static Memory
nSDRAS
SDRAM
A[27:15]
Static Memory
DRA[0:12]
SDRAM
A[14:13]
Static Memory
DRA[13:14]
SDRAM
PD[7:6]
GPIO
SDQM[1:0]
SDRAM
RUN
System
Configuration
CLKEN
System
Configuration
nMEDCHG
Interrupt
Controller
nBROM
Boot ROM
select
PD[0]
GPIO
LEDFLSH
LED Flasher
PE[1:0]
GPIO
BOOTSEL[1:0]
System
Configuration
PE[2]
GPIO
CLKSEL
System
Configuration
Table S. Pin Multiplexing
8
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
System Design
As shown in system block diagram, simply adding
desired memory and peripherals to the highly integrated
EP7311 completes a low-power system solution. All
necessary interface logic is integrated on-chip.
CRYSTAL
MOSCIN
DD[0-3]
CRYSTAL
RTCIN
nCS[4]
PB0
EXPCLK
CL1
CL2
FRM
M
LCD
COL[0-7]
PC CARD
CONTROLLER
PC CARD
SOCKET
KEYBOARD
D[0-31]
PA[0-7]
A[0-27]
PB[0-7]
nMOE
WRITE
PD[0-7]
SDRAS/
SDCAS
×16
SDRAM
×16
SDRAM
SDCS[0]
×16
SDRAM
×16
SDRAM
SDCS[1]
SDQM[0-3]
SDQM[0-3]
EP7311
PE[0-2]
nPOR
nPWRFL
BATOK
nEXTPWR
nBATCHG
RUN
WAKEUP
DRIVE[0-1]
FB[0-1]
nCS[0]
nCS[1]
×16
FLASH
×16
FLASH
SSICLK
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
×16
FLASH
×16
FLASH
LEDDRV
PHDIN
CS[n]
WORD
EXTERNAL MEMORYMAPPED EXPANSION
BUFFERS
nCS[2]
nCS[3]
ADDITIONAL I/O
BUFFERS
AND
LATCHES
LEDFLSH
RXD1/2
TXD1/2
DSR
CTS
DCD
ADCCLK
nADCCS
ADCOUT
ADCIN
SMPCLK
POWER
SUPPLY UNIT
AND
COMPARATORS
DC
INPUT
BATTERY
DC-TO-DC
CONVERTERS
CODEC/SSI2/
MCP
IR LED AND
PHOTODIODE
2× RS-232
TRANSCEIVERS
ADC
DIGITIZER
Figure 1. A Maximum EP7311 Based System
Note:
A system can only use one of the following peripheral
interfaces at any given time: SSI2,CODEC or MCP.
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
9
EP7311
High-Performance, Low-Power System on Chip
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
DC Core, PLL, and RTC Supply Voltage
2.9 V
DC I/O Supply Voltage (Pad Ring)
3.6 V
DC Pad Input Current
±10 mA/pin; ±100 mA cumulative
Storage Temperature, No Power
–40°C to +125°C
Recommended Operating Conditions
DC core, PLL, and RTC Supply Voltage
2.5 V ± 0.2 V
DC I/O Supply Voltage (Pad Ring)
2.3 V - 3.5 V
DC Input / Output Voltage
O–I/O supply voltage
Operating Temperature
Extended -20°C to +70°C; Commercial 0°C to +70°C;
Industrial -40°C to +85°C
DC Characteristics
All characteristics are specified at V DDCORE = 2.5 V, VDDIO = 3.3 V and VSS = 0 V over an operating temperature of 0°C
to +70°C for all frequencies of operation. The current consumption figures have test conditions specified per
parameter.”
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
VIH
CMOS input high voltage
0.65 × VDDIO
-
VDDIO + 0.3
V
VDDIO = 2.5 V
VIL
CMOS input low voltage
VSS − 0.3
-
0.25 × VDDIO
V
VDDIO = 2.5 V
VT+
Schmitt trigger positive going
threshold
-
-
2.1
V
VT-
Schmitt trigger negative going
threshold
0.8
-
-
V
Vhst
Schmitt trigger hysteresis
0.1
-
0.4
V
VIL to VIH
VDD – 0.2
2.5
2.5
-
-
V
V
V
IOH = 0.1 mA
IOH = 4 mA
IOH = 12 mA
Output drive 2a
-
-
0.3
0.5
0.5
V
V
V
IOL = –0.1 mA
IOL = –4 mA
IOL = –12 mA
Input leakage current
-
-
1.0
µA
VIN = VDD or GND
25
-
100
µA
VOUT = VDD or GND
8
-
10.0
pF
CMOS output high voltagea
VOH
Output drive 1a
Output drive 2a
CMOS output low voltagea
VOL
IIN
IOZ
CIN
10
Output drive 1a
Bidirectional 3-state leakage
currentb c
Input capacitance
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Symbol
Parameter
Min
Typ
Max
Unit
COUT
Output capacitance
8
-
10.0
pF
CI/O
Transceiver capacitance
8
-
10.0
pF
IDDSTANDBY
@ 25 C
IDDSTANDBY
@ 70 C
IDDSTANDBY
@ 85 C
IDD idle
at 74 MHz
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
-
77
41
-
-
-
570
111
µA
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
µA
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
µA
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Idle current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
VDD STANDBY Standby supply voltage
-
-
1693
163
Conditions
-
6
10
-
mA
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = V DD ± 0.1 V, VIL
= GND ± 0.1 V
2.0
-
-
V
Minimum standby voltage for
state retention, internal SRAM
cache, and RTC operation only
a.
Refer to the strength column in the pin assignment tables for all package types.
b.
Assumes buffer has no pull-up or pull-down resistors.
c.
The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.
Note:
DS506PP1
1) Total power consumption = IDDCORE x 2.5 V + IDDIO x 3.3 V
2) A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be
compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).
2) Pull-up current = 50 µA typical at VDD = 3.3 V.
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
11
EP7311
High-Performance, Low-Power System on Chip
Timings
Timing Diagram Conventions
This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any
variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless
specifically stated.
C lo c k
H ig h
H ig h /L o w
B u s
to
to
L o w
H ig h
C h a n g e
B u s
V a lid
U n d e fin e d /In v a lid
V a lid
B u s
to
T r is ta te
B u s / S ig n a l O m is s io n
Figure 2. Legend for Timing Diagrams
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are
specified at VDDIO = 3.1 - 3.5 V and V SS = 0 V over an operating temperature of -40°C to +85°C. Pin loadings is 50 pF.
The timing values are referenced to 1/2 V DD.
12
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
SDRAM Interface
Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the
values for the timings of each of the SDRAM modes.
Parameter
Symbol
Min
Typ
Max
Unit
SDCLK rising edge to SDCS assert delay time
tCSa
0
2
4
ns
SDCLK rising edge to SDCS deassert delay time
tCSd
−3
2
10
ns
SDCLK rising edge to SDRAS assert delay time
tRAa
1
3
7
ns
SDCLK rising edge to SDRAS deassert delay time
tRAd
−3
1
10
ns
SDCLK rising edge to SDRAS invalid delay time
tRAnv
2
4
7
ns
SDCLK rising edge to SDCAS assert delay time
tCAa
−2
2
5
ns
SDCLK rising edge to SDCAS deassert delay time
tCAd
−5
0
3
ns
SDCLK rising edge to ADDR transition time
tADv
−3
1
5
ns
SDCLK rising edge to ADDR invalid delay time
tADx
−2
2
5
ns
SDCLK rising edge to SDMWE assert delay time
tMWa
−2
1
5
ns
SDCLK rising edge to SDMWE deassert delay time
tMWd
−4
0
4
ns
DATA transition to SDCLK rising edge time
tDAs
-
-
2
ns
SDCLK rising edge to DATA transition hold time
tDAh
-
-
1
ns
SDCLK rising edge to DATA transition delay time
tDAd
0
-
15
ns
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
13
EP7311
High-Performance, Low-Power System on Chip
SDRAM Load Mode Register Cycle
SDCLK
tCSa
tCSd
tRAa
tRAd
tCAa
tCAd
SDCS
SDRAS
SDCAS
tADv
tADx
ADDR
DATA
SDQM
tMWa
tMWd
SDMWE
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement
Note:
14
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
SDRAM Burst Read Cycle
SDCLK
tCSa
SDCS
tCSa
tCSd
tCSd
tRAa
SDRAS
tRAnv
tRAd
tCAa
tCAd
SDCAS
tADv
ADDR
tADv
ADRAS
ADCAS
tDAs
DATA
D1
tDAh
tDAs
D2
tDAh
tDAs
D3
tDAh
tDAs
D4
tDAh
SDQM
[0:3]
SDMWE
Figure 4. SDRAM Burst Read Cycle Timing Measurement
Note:
DS506PP1
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal.
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
15
EP7311
High-Performance, Low-Power System on Chip
SDRAM Burst Write Cycle
SDCLK
tCSa
tCSa
tCSd
SDCS
tCSd
tRAa
tRAd
SDRAS
tCAa
tCAd
SDCAS
tADv
tADv
tDAd
tDAd
tDAd
D1
DATA
SDQM
ADCAS
ADRAS
ADDR
D2
tDAd
D3
D4
0
tMWa
tMWd
SDMWE
Figure 5. SDRAM Burst Write Cycle Timing Measurement
Note:
16
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
SDRAM Refresh Cycle
SDCLK
tCSa
tCSd
tRAa
tRAd
SDCS
SDRAS
tCAd
SDCAS
tCAa
SDATA
ADDR
SDQM
[3:0]
SDMWE
Figure 6. SDRAM Refresh Cycle Timing Measurement
Note:
DS506PP1
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
17
EP7311
High-Performance, Low-Power System on Chip
Static Memory
Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory. The following table
contains the values for the timings of each of the Static Memory modes.
Parameter
Symbol
Min
Typ
Max
Unit
EXPCLK rising edge to nCS assert delay time
tCSd
2
8
20
ns
EXPCLK falling edge to nCS deassert hold time
tCSh
2
7
20
ns
EXPCLK rising edge to A assert delay time
tAd
4
9
16
ns
EXPCLK falling edge to A deassert hold time
tAh
3
10
19
ns
EXPCLK rising edge to nMWE assert delay time
tMWd
3
6
10
ns
EXPCLK rising edge to nMWE deassert hold time
tMWh
3
6
10
ns
EXPCLK falling edge to nMOE assert delay time
tMOEd
3
7
10
ns
EXPCLK falling edge to nMOE deassert hold time
tMOEh
2
7
10
ns
EXPCLK falling edge to HALFWORD deassert delay time
tHWd
2
8
20
ns
EXPCLK falling edge to WORD assert delay time
tWDd
2
8
16
ns
EXPCLK rising edge to data valid delay time
tDv
8
13
21
ns
EXPCLK falling edge to data invalid delay time
tDnv
6
15
30
ns
Data setup to EXPCLK falling edge time
tDs
-
-
1
ns
EXPCLK falling edge to data hold time
tDh
-
-
3
ns
EXPCLK rising edge to WRITE assert delay time
tWRd
5
11
23
ns
EXPREADY setup to EXPCLK falling edge time
tEXs
-
-
0
ns
EXPCLK falling edge to EXPREADY hold time
tEXh
-
-
0
ns
18
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Static Memory Single Read Cycle
EXPCLK
tCSd
tCSh
nCS
tAd
A
nMWE
tMOEd
tMOEh
nMOE
tHWd
HALFWORD
tWDd
WORD
tDs
tDh
D
tEXs
tEXh
EXPRDY
tWRd
WRITE
Figure 7. Static Memory Single Read Cycle Timing Measurement
Note:
DS506PP1
1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Address, Halfword, Word, and Write hold state until next cycle.
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
19
EP7311
High-Performance, Low-Power System on Chip
Static Memory Single Write Cycle
EXPCLK
tCSd
tCSh
nCS
tAd
A
tMWd
tMWh
nMWE
nMOE
tHWd
HALFWORD
tWDd
WORD
tDv
D
tEXs
tEXh
EXPRDY
WRITE
Figure 8. Static Memory Single Write Cycle Timing Measurement
Note:
20
1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
3. Address, Data, Halfword, Word, and Write hold state until next cycle.
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
EXPCLK
tCSd
tCSh
nCS
tAd
tAh
tAh
tAh
A
nMWE
tMOEd
tMOEh
nMOE
tHWd
HALF
WORD
tWDd
WORD
tDs tDh
tDs
tDh
tDs tDh
tDs tDh
D
tEXs
tEXh
EXPRDY
tWRd
WRITE
Figure 9. Static Memory Burst Read Cycle Timing Measurement
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
4. Address, Halfword, Word, and Write hold state until next cycle.
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
21
EP7311
High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
EXPCLK
tCSd
tCSh
nCS
tAh
tAd
tAh
tAh
A
tMWd
tMWd
tMWd
tMWh
nMWE
tMWd
tMWh
tMWh
tMWh
nMOE
tHWd
HALF
WORD
WORD
tWDd
tDv
tDnv
tDv
tDnv
tDv
tDnv
tDv
D
tEXs
tEXh
EXPRDY
WRITE
Figure 10. Static Memory Burst Write Cycle Timing Measurement
Note:
22
1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
4. Address, Data, Halfword, Word, and Write hold state until next cycle.
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
SSI1 Interface
Parameter
Symbol
Min
Max
Unit
ADCCLK falling edge to nADCCSS deassert delay time
tCd
9
10
ms
ADCIN data setup to ADCCLK rising edge time
tINs
-
15
ns
ADCIN data hold from ADCCLK rising edge time
tINh
-
14
ns
ADCCLK falling edge to data valid delay time
tOvd
−7
13
ns
ADCCLK falling edge to data invalid delay time
tOd
−2
3
ns
ADC
CLK
tCd
nADC
CSS
tINs
tINh
ADCIN
tOvd
tOd
ADC
OUT
Figure 11. SSI1 Interface Timing Measurement
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
23
EP7311
High-Performance, Low-Power System on Chip
SSI2 Interface
Parameter
Symbol
Min
Max
Unit
SSICLK period (slave mode)
tclk_per
185
2050
ns
SSICLK high time
tclk_high
925
1025
ns
SSICLK low time
tclk_low
925
1025
ns
SSICLK rise/fall time
tclkrf
3
18
ns
SSICLK rising edge to RX and/or TX frame sync high time
tFRd
-
3
ns
SSICLK rising edge to RX and/or TX frame sync low time
tFRa
-
8
ns
tFR_per
960
990
ns
SSIRXDA setup to SSICLK falling edge time
tRXs
3
7
ns
SSIRXDA hold from SSICLK falling edge time
tRXh
3
7
ns
SSICLK rising edge to SSITXDA data valid delay time
tTXd
-
2
ns
SSITXDA valid time
tTXv
960
990
ns
SSIRXFR and/or SSITXFR period
tclk_per
tclk_high
tclk_low
SSI
CLK
tclkrf
tFRd
tFRa
tFR_per
SSIRXFR/
SSITXFR
tRXh
tRXs
SSI
RXDA
D7
D2
D1
D0
D7
D2
D1
D0
tTXd
SSI
TXDA
tTXv
Figure 12. SSI2 Interface Timing Measurement
24
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
LCD Interface
Parameter
Symbol
Min
Max
Unit
CL[2] falling to CL[1] rising delay time
tCL1d
− 10
25
ns
CL[1] falling to CL[2] rising delay time
tCL2d
80
3,475
ns
CL[1] falling to FRM transition time
tFRMd
300
10,425
ns
CL[1] falling to M transition time
tMd
− 10
20
ns
CL[2] rising to DD (display data) transition time
tDDd
− 10
20
ns
CL[2]
tCL2d
tCL1d
CL[1]
tFRMd
FRM
tMd
M
tDDd
DD [3:0]
Figure 13. LCD Controller Timing Measurement
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
25
EP7311
High-Performance, Low-Power System on Chip
JTAG Interface
Parameter
Symbol
Min
Max
Units
TCK clock period
tclk_per
2
-
ns
TCK clock high time
tclk_high
1
-
ns
TCK clock low time
tclk_low
1
-
ns
JTAG port setup time
tJPs
-
0
ns
JTAG port hold time
tJPh
-
3
ns
JTAG port clock to output
tJPco
-
10
ns
JTAG port high impedance to valid output
tJPzx
-
12
ns
JTAG port valid output to high impedance
tJPxz
-
19
ns
tclk_per
tclk_high
tclk_low
TCK
tJPs
tJPh
TMS
TDI
tJPzx
tJPco
tJPxz
TDO
Figure 14. JTAG Timing Measurement
26
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Packages
208-Pin LQFP Package Characteristics
208-Pin LQFP Package Specifications
29.60 (1.165)
30.40 (1.197)
27.80 (1.094)
28.20 (1.110)
0.17 (0.007)
0.27 (0.011)
27.80 (1.094)
28.20 (1.110)
EP7311
29.60 (1.165)
30.40 (1.197)
208-Pin LQFP
0.50
(0.0197)
BSC
Pin 1 Indicator
Pin 208
Pin 1
1.35 (0.053)
1.45 (0.057)
0.45 (0.018)
0.75 (0.030)
1.00 (0.039) BSC
0.09 (0.004)
0.20 (0.008)
0° MIN
7° MAX
0.05 (0.002)
0.15 (0.006)
1.40 (0.055)
1.60 (0.063)
Figure 15. 208-Pin LQFP Package Outline Drawing
Note:
DS506PP1
1)
2)
3)
4)
Dimensions are in millimeters (inches), and controlling dimension is millimeter.
Drawing above does not reflect exact package pin count.
Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.
For pin locations, please see Figure 16. For pin descriptions see the EP7311 User’s Manual.
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
27
EP7311
High-Performance, Low-Power System on Chip
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
nURESET
nMEDCHG/nBROM
nPOR
BATOK
nEXTPWR
nBATCHG
D[7]
VSSIO
A[7]
D[8]
A[8]
D[9]
A[9]
D[10]
A[10]
D[11]
VSSIO
VDDIO
A[11]
D[12]
A[12]
D[13]
A[13]\DRA[14]
D[14]
A[14]/DRA[13]
D[15]
A[15]/DRA[12]
D[16]
A[16]/DRA[11]
D[17]
A[17]/DRA[10]
nTRST
VSSIO
VDDIO
D[18]
A[18/DRA[9]
D[19]
A[19]/DRA[8]
D[20]
A[20]/DRA[7]
VSSIO
D[21]
A[21]/DRA[6]
D[22]
A[22]/DRA[5]
D[23]
A[23]/DRA[4]
D[24]
VSSIO
VDDIO
A[24]/DRA[3]
HALFWORD
208-Pin LQFP Pin Diagram
EP7311
208-Pin LQFP
(Top View)
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
D[25]
A[25]/DRA[2]
D[26]
A[26]/DRA[1]
D[27]
A[27]/DRA[0]
VSSIO
D[28]
D[29]
D[30]
D[31]
BUZ
COL[0]
COL[1]
TCLK
VDDIO
COL[2]
COL[3]
COL[4]
COL[5]
COL[6]
COL[7]
FB[0]
VSSIO
FB[1]
SMPCLK
ADCOUT
ADCCLK
DRIVE[0]
DRIVE[1]
VDDIO
VSSIO
VDDCORE
VSSCORE
nADCCS
ADCIN
SSIRXFR
SSIRXDA
SSITXDA
SSITXFR
VSSIO
SSICLK
PD[0]/LEDFLSH
PD[1]
PD[2]
PD[3]
TMS
VDDIO
PD[4]
PD[5]
PD[6]/SDQM[0]
PD[7]/SDQM[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
nCS[5]
VDDIO
VSSIO
EXPCLK
WORD
WRITE/nSDRAS
RUN/CLKEN
EXPRDY
TXD[2]
RXD[2]
TDI
VSSIO
PB[7]
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]
PB[0]
VDDIO
TDO
PA[7]
PA[6]
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
PA[0]
LEDDRV
TXD[1]
VSSIO
PHDIN
CTS
RXD[1]
DCD
DSR
nTEST[1]
nTEST[0]
EINT[3]
nEINT[2]
nEINT[1]
nEXTFIQ
PE[2]/CLKSEL
PE[1]BOOTSEL[1]
PE[0]BOOTSEL[0]
VSSRTC
RTCOUT
RTCIN
VDDRTC
N/C
VDDOSC
MOSCIN
MOSCOUT
VSSOSC
WAKEUP
nPWRFL
A[6]
D[6]
A[5]
D[5]
VDDIO
VSSIO
A[4]
D[4]
A[3]
D[3]
A[2]
VSSIO
D[2]
A[1]
D[1]
A[0]
D[0]
VSSCORE
VDDCORE
VSSIO
VDDIO
CL[2]
CL[1]
FRM
M
DD[3]
DD[2]
VSSIO
DD[1]
DD[0]
nSDCS[1]
nSDCS[0]
SDQM[3]
SDQM[2]
VDDIO
VSSIO
SDCKE
SDCLK
nMWE/nSDWE
nMOE/nSDCAS
VSSIO
nCS[0]
nCS[1]
nCS[2]
nCS[3]
nCS[4]
Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
Note:
28
1. N/C should not be grounded but left as no connects.
2. Pin differences between the EP7211 and the EP7311 are bolded.
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
208-Pin LQFP Numeric Pin Listing
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Table T. 208-Pin LQFP Numeric Pin Listing
Pin
No.
Signal
Type
38
DSR
I
39
nTEST[1]
I
With p/u*
40
nTEST[0]
I
With p/u*
41
EINT[3]
I
42
nEINT[2]
I
43
nEINT[1]
I
44
nEXTFIQ
I
45
PE[2]/CLKSEL
I/O
1
Input
46
PE[1]/
BOOTSEL[1]
I/O
1
Input
47
PE[0]/
BOOTSEL[0]
I/O
1
Input
48
VSSRTC
RTC Gnd
Input
49
RTCOUT
O
1
Input
50
RTCIN
I
I/O
1
Input
51
VDDRTC
RTC power
PB[4]
I/O
1
Input
52
N/C
17
PB[3]
I/O
1
Input
53
PD[7]/SDQM[1]
I/O
1
Low
18
PB[2]
I/O
1
Input
54
PD[6]/SDQM[0]
I/O
1
Low
19
PB[1]/PRDY2
I/O
1
Input
55
PD[5]
I/O
1
Low
20
PB[0]/PRDY1
I/O
1
Input
56
PD[4]
I/O
1
Low
21
VDDIO
Pad Pwr
57
VDDIO
Pad Pwr
22
TDO
O
1
Three state
58
TMS
I
with p/u*
23
PA[7]
I/O
1
Input
59
PD[3]
I/O
1
Low
24
PA[6]
I/O
1
Input
60
PD[2]
I/O
1
Low
25
PA[5]
I/O
1
Input
61
PD[1]
I/O
1
Low
26
PA[4]
I/O
1
Input
62
PD[0]/LEDFLSH
I/O
1
Low
27
PA[3]
I/O
1
Input
63
SSICLK
I/O
1
Input
28
PA[2]
I/O
1
Input
64
VSSIO
Pad Gnd
29
PA[1]
I/O
1
Input
65
SSITXFR
I/O
1
Low
30
PA[0]
I/O
1
Input
66
SSITXDA
O
1
Low
31
LEDDRV
O
1
Low
67
SSIRXDA
I
32
TXD[1]
O
1
High
68
SSIRXFR
I/O
33
VSSIO
Pad Gnd
1
High
69
ADCIN
I
34
PHDIN
I
70
nADCCS
O
35
CTS
I
71
VSSCORE
Core Gnd
36
RXD[1]
I
72
VDDCORE
Core Pwr
37
DCD
I
73
VSSIO
Pad Gnd
Pin
No.
Signal
Type
Strength
Reset
State
1
nCS[5]
O
1
Low
2
VDDIO
Pad Pwr
3
VSSIO
Pad Gnd
4
EXPCLK
I/O
1
5
WORD
Out
1
Low
6
WRITE/nSDRAS
Out
1
Low
7
RUN/CLKEN
O
1
Low
8
EXPRDY
I
1
9
TXD[2]
O
1
10
RXD[2]
I
11
TDI
I
12
VSSIO
Pad Gnd
13
PB[7]
I/O
1
14
PB[6]
I/O
15
PB[5]
16
DS506PP1
High
with p/u*
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
Strength
Reset
State
Input
1
High
29
EP7311
High-Performance, Low-Power System on Chip
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Signal
Type
74
VDDIO
Pad Pwr
75
DRIVE[1]
I/O
Strength
Reset
State
2
High /
Low
76
DRIVE[0]
I/O
2
High /
Low
77
ADCCLK
O
1
Low
78
ADCOUT
O
1
Low
79
SMPCLK
O
1
Low
80
FB[1]
I
81
VSSIO
Pad Gnd
82
FB[0]
I
83
COL[7]
O
1
High
84
COL[6]
O
1
High
85
COL[5]
O
1
High
86
COL[4]
O
1
High
87
COL[3]
O
1
High
88
COL[2]
O
1
High
89
VDDIO
Pad Pwr
90
TCLK
I
91
COL[1]
O
1
High
92
COL[0]
O
1
High
93
BUZ
O
1
Low
94
D[31]
I/O
1
Low
95
D[30]
I/O
1
Low
96
D[29]
I/O
1
Low
97
D[28]
I/O
1
Low
98
VSSIO
Pad Gnd
99
A[27]/DRA[0]
O
2
Low
100
D[27]
I/O
1
Low
101
A[26]/DRA[1]
O
2
Low
102
D[26]
I/O
1
Low
103
A[25]/DRA[2]
O
2
Low
104
D[25]
I/O
1
Low
105
HALFWORD
O
1
Low
106
A[24]/DRA[3]
O
1
Low
107
VDDIO
Pad Pwr
—
108
VSSIO
Pad Gnd
—
109
D[24]
I/O
1
Low
110
A[23]/DRA[4]
O
1
Low
30
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Signal
Type
Strength
Reset
State
111
D[23]
I/O
1
Low
112
A[22]/DRA[5]
O
1
Low
113
D[22]
I/O
1
Low
114
A[21]/DRA[6]
O
1
Low
115
D[21]
I/O
1
Low
116
VSSIO
Pad Gnd
117
A[20]/DRA[7]
O
1
Low
118
D[20]
I/O
1
Low
119
A[19]/DRA[8]
O
1
Low
120
D[19]
I/O
1
Low
121
A[18]/DRA[9]
O
1
Low
122
D[18]
I/O
1
Low
123
VDDIO
Pad Pwr
124
VSSIO
Pad Gnd
125
nTRST
I
126
A[17]/DRA[10]
O
1
Low
127
D[17]
I/O
1
Low
128
A[16]/DRA[11]
O
1
Low
129
D[16]
I/O
1
Low
130
A[15]/DRA[12]
O
1
Low
131
D[15]
I/O
1
Low
132
A[14]/DRA[13]
O
1
Low
133
D[14]
I/O
1
Low
134
A[13]/DRA[14]
O
1
Low
135
D[13]
I/O
1
Low
136
A[12]
O
1
Low
137
D[12]
I/O
1
Low
138
A[11]
O
1
Low
139
VDDIO
Pad Pwr
140
VSSIO
Pad Gnd
141
D[11]
I/O
1
Low
142
A[10]
O
1
Low
143
D[10]
I/O
1
Low
144
A[9]
O
1
Low
145
D[9]
I/O
1
Low
146
A[8]
O
1
Low
147
D[8]
I/O
1
Low
148
A[7]
O
1
Low
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Signal
Type
Pin
No.
Signal
Type
Strength
Reset
State
149
VSSIO
Pad Gnd
187
M
O
1
Low
150
D[7]
I/O
188
DD[3]
I/O
1
Low
151
nBATCHG
I
189
DD[2]
I/O
1
Low
152
nEXTPWR
I
190
VSSIO
Pad Gnd
153
BATOK
I
191
DD[1]
I/O
1
Low
154
nPOR
I
192
DD[0]
I/O
1
Low
155
nMEDCHG/
nBROM
I
193
nSDCS[1]
O
1
High
194
nSDCS[0]
O
1
High
156
nURESET
I
195
SDQM[3]
I/O
2
Low
157
VDDOSC
Osc Pwr
196
SDQM[2]
I/O
2
Low
158
MOSCIN
Osc
197
VDDIO
Pad Pwr
159
MOSCOUT
Osc
198
VSSIO
Pad Gnd
160
VSSOSC
Osc Gnd
199
SDCKE
I/O
2
Low
161
WAKEUP
I
200
SDCLK
I/O
2
Low
162
nPWRFL
I
201
nMWE/nSDWE
O
1
High
163
A[6]
O
1
Low
202
nMOE/nSDCAS
O
1
High
164
D[6]
I/O
1
Low
203
VSSIO
Pad Gnd
165
A[5]
Out
1
Low
204
nCS[0]
O
1
High
166
D[5]
I/O
1
Low
205
nCS[1]
O
1
High
167
VDDIO
Pad Pwr
206
nCS[2]
O
1
High
168
VSSIO
Pad Gnd
207
nCS[3]
O
1
High
169
A[4]
O
1
Low
208
nCS[4]
O
1
High
170
D[4]
I/O
1
Low
171
A[3]
O
2
Low
172
D[3]
I/O
1
Low
173
A[2]
O
2
Low
174
VSSIO
Pad Gnd
175
D[2]
I/O
1
Low
176
A[1]
O
2
Low
177
D[1]
I/O
1
Low
178
A[0]
O
2
Low
179
D[0]
I/O
1
Low
180
VSS CORE
Core Gnd
181
VDD CORE
Core Pwr
182
VSSIO
Pad Gnd
183
VDDIO
Pad Pwr
184
CL[2]
O
1
Low
185
CL[1]
O
1
Low
186
FRM
O
1
Low
DS506PP1
Strength
1
Reset
State
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Low
Schmitt
Schmitt
Schmitt
*With p/u’ means with internal pull-up on the pin.
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
31
EP7311
High-Performance, Low-Power System on Chip
204-Ball TFBGA Package Characteristics
204-Ball TFBGA Package Specifications
TOP VIEW
BOTTOM VIEW
Ø0.08 M C
Ø0.15 M C A B
A1 CORNER
A1 CORNER
Ø0.25~0.35(204X)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
C
D
E
F
G
H
J
K
L
M
12.35
13±0.05
0.65
A
B
N
P
R
T
N
P
R
T
U
V
W
Y
U
V
W
Y
A
0.65
12.35
0.20 C
13±0.05
0.15(4X) C
0.10 C
0.53±0.05
B
Ball Pitch :
SEATING PLANE
Ball Diameter :
0.20~0.30
C
1.20 MAX.
0.36
0.65
Substrate Thickness :
0.36
Mold Thickness :
0.3
0.53
Figure 17. 204-Ball TFBGA Package
32
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
204-Ball TFBGA Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A VDDIO EXPCLK nCS3
nCS1
nMWE/
SDQM2 nSDCS1
nSDWE
DD2
FRM
CL1
GNDCOR
E
D1
A2
D4
A5
nPWRFL MOSCOUT GNDIO
GNDIO
B WORD
nCS2
nMOE/
SDCKE nSDCS0
nSDCAS
DD1
M
CL2
D0
A1
D3
A4
D6
WAKEUP MOSCIN
GNDIO
GNDIO nURESET B
DD0
DD3
VDDCO
RE
A0
D2
A3
D5
A6
GNDOS
VDDOSC
C
GNDIO
BATOK
nPOR
C
GNDIO
nBATCHG
A7
D
nMEDCHG
nEXTPWR
/nBROM
D9
E
C
VDDIO
nCS5
RUN/
EXPRDY VDDIO
CLKEN
nCS4
nCS0
SDCLK SDQM3
GNDIO A
D
PB7
RXD2
VDDIO
E
PB4
TXD2
WRITE/
nSDRAS
F
PB3
PB6
TDI
D7
A8
D10
F
G
PB1/
PRDY2
PB2
PB5
D8
A9
D11
G
H
PA7
TDO
PB0/
PRDY1
A10
D12
A12
H
J
PA4
PA5
PA6
A11
D13
A13/
DRA14
J
K
PA1
PA2
VDDIO
D14
A14/
DRA13
D15
K
PA3
VDDIO
D16
A16/
DRA11
L
PA0
A15/
DRA12
A17/
DRA10
nTEST1 PHDIN
D17
D19
A18/
DRA9
N
P EINT3
nEINT2
D18
A20/
DRA7
D20
P
R nEXTFIQ
PE2/
nTEST0
CLKSEL
A19/
DRA8
D22
A21/
DRA6
R
D21
D23
A22/
DRA5
T
HALF
WORD
D24
A23/
DRA4
U
L
TXD1 LEDDRV
M RXD1
N
T
DSR
PE1/
BOOT
SEL1
CTS
PE0/
BOOT
SEL0
DCD
nEINT1
U GNDRTCRTCOUT RTCIN
V VDDRTC GNDIO GNDIO
PD7/
SDQM1
PD4
PD2
W GNDIO GNDIO GNDIO
PD6/SD
TMS
QM0
PD1
Y GNDIO GNDIO GNDIO
DS506PP1
PD5
PD3
SSICLK SSIRXDA nADCCS VDDIO ADCCLK COL7
nTRST M
COL4 TCLK
BUZ
D29
A26/
DRA1
VDDIO
VDDIO
A24/
DRA3
V
GNDCO
DRIVE1 ADCOUT
RE
FB0
COL5 COL2
COL0
D30
A27/
DRA0
D26
VDDIO
D25
W
PD0/
VDDCO
LED SSITXDA ADCIN
DRIVE0 SMPLCK
RE
FLSH
FB1
COL6 COL3
COL1
D31
D28
D27
A25/
DRA2
VDDIO
Y
SSITXFR SSIRXFR
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
33
EP7311
High-Performance, Low-Power System on Chip
204-Ball TFBGA Ball Listing
The list is ordered by ball location.
Table 21. 204-Ball TFBGA Ball Listing
Ball Location
Name
†
Strength
Reset
State
Type
Description
Pad power
Digital I/O power,
3.3 V
I
Expansion clock
input
A1
VDDIO
A2
EXPCLK
1
A3
nCS[3]
1
High
O
Chip select 3
A4
nCS[1]
1
High
O
Chip select 1
A5
nMWE/nSDWE
1
High
O
ROM, expansion
write enable/
SDRAM write enable
control signal
A6
SDQM[2]
2
Low
O
SDRAM byte lane
mask
A7
nSDCS[1]
1
High
O
SDRAM chip select
2
A8
DD[2]
1
Low
O
LCD serial display
data
A9
FRM
1
Low
O
LCD frame
synchronization
pulse
A10
CL[1]
1
Low
O
LCD line clock
A11
VSSCORE
A12
D[1]
1
Low
I/O
Data I/O
A13
A[2]
2
Low
O
System byte address
A14
D[4]
1
Low
I/O
Data I/O
A15
A[5]
1
Low
O
System byte address
A16
nPWRFL
I
Power fail sense
input
A17
MOSCOUT
O
Main oscillator out
A18
VSSIO
Pad ground
I/O ground
A19
VSSIO
Pad ground
I/O ground
A20
VSSIO
Pad ground
I/O ground
B1
WORD
B2
VDDIO
B3
nCS[5]
1
Low
O
Chip select 5
B4
nCS[2]
1
High
O
Chip select 2
B5
nMOE/nSDCAS
1
High
O
ROM, expansion OP
enable/SDRAM CAS
control signal
B6
SDCKE
2
Low
O
SDRAM clock
enable output
B7
nSDCS[0]
1
High
O
SDRAM chip select
0
34
Core ground
1
Low
Core ground
O
Word access select
output
Pad power
Digital I/O power, 3.3
V
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
Strength
Reset
State
Type
†
Description
B8
DD[1]
1
Low
O
LCD serial display
data
B9
M
1
Low
O
LCD AC bias drive
B10
CL[2]
1
Low
0
LCD pixel clock out
B11
D[0]
1
Low
I/O
Data I/O
B12
A[1]
2
Low
O
System byte address
B13
D[3]
2
Low
I/O
Data I/O
B14
A[4]
1
Low
O
System byte address
B15
D[6]
1
Low
I/O
Data I/O
B16
WAKEUP
B17
MOSCIN
B18
VSSIO
Pad ground
I/O ground
B19
VSSIO
Pad ground
I/O ground
B20
nURESET
C1
RUN/CLKEN
1
C2
EXPRDY
1
C3
VDDIO
C4
nCS[4]
1
High
O
Chip select 4
C5
nCS[0]
1
High
O
Chip select 0
C6
SDCLK
2
Low
O
SDRAM clock out
C7
SDQM[3]
2
Low
O
SDRAM byte lane
mask
C8
DD[0]
1
Low
O
LCD serial display
data
C9
DD[3]
1
Low
O
LCD serial display
data
C10
VDDCORE
Core power
Digital core power,
2.5 V
C11
A[0]
2
Low
O
System byte address
C12
D[2]
1
Low
I/O
Data I/O
C13
A[3]
2
Low
O
System byte address
C14
D[5]
1
Low
I/O
Data I/O
C15
A[6]
1
Low
O
System byte address
C16
VSSOSC
Oscillator ground
PLL ground
C17
VDDOSC
Oscillator power
Oscillator power in,
2.5V
C18
VSSIO
Pad ground
C19
BATOK
I
DS506PP1
Schmitt
Schmitt
Low
I
System wake up
input
I
Main oscillator input
I
User reset input
0
Run output / clock
enable output
I
Expansion port
ready input
Pad power
Digital I/O power,
3.3 V
I/O ground
Battery ok input
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
35
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
†
Strength
Reset
State
Type
Description
I
Power-on reset input
I
GPIO port B
UART 2 receive data
input
C20
nPOR
Schmitt
D1
PB[7]
1
D2
RXD[2]
I
D3
VDDIO
Pad power
Digital I/O power,
3.3V
D18
VSSIO
Pad ground
I/O ground
D19
nBATCHG
D20
A[7]
1
Low
E1
PB[4]
1
Input
E2
TXD[2]
1
E3
WRITE/nSDRAS
1
E18
Input
‡
I
Battery changed
sense input
O
System byte address
I
GPIO port B
High
O
UART 2 transmit
data output
Low
O
Transfer direction /
SDRAM RAS signal
output
nMEDCHG/nBROM
I
Media change
interrupt input /
internal ROM boot
enable
E19
nEXTPWR
I
External power
supply sense input
E20
D[9]
1
Low
F1
PB[3]
1
Input
F2
PB[6]
1
Input
F3
TDI
with p/u*
F18
D[7]
1
Low
I/O
Data I/O
F19
A[8]
1
Low
O
System byte address
F20
D[10]
1
Low
I/O
Data I/O
G1
PB[1]
1
Input
‡
I/O
G2
PB[2]
1
Input
‡
I/O
GPIO port B
G3
PB[5]
1
Input
‡
I/O
GPIO port B
G18
D[8]
1
Input
‡
I/O
Data I/O
G19
A[9]
1
Low
O
System byte address
G20
D[11]
1
Low
I/O
Data I/O
H1
PA[7]
1
Input
‡
I/O
GPIO port A
H[2]
TDO
1
Input
‡
O
JTAG data out
H[3]
PB[0]
1
Input
‡
I/O
GPIO port B
H[18]
A[10]
1
Low
O
System byte address
36
‡
I/O
Data I/O
‡
I/O
GPIO port B
‡
I/O
I
GPIO port B
JTAG data input
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
Strength
Reset
State
Type
†
Description
H19
D[12]
1
Low
I/O
Data I/O
H20
A[12]
1
Low
O
System byte address
J1
PA[4]
1
Input
‡
I/O
GPIO port A
J2
PA[5]
1
Input
‡
I/O
GPIO port A
J3
PA[6]
1
Input
‡
I/O
GPIO port A
J18
A[11]
1
Low
O
System byte address
J19
D[13]
1
Low
I/O
Data I/O
J20
A[13]/DRA[14]
1
Low
O
System byte address
/ SDRAM address
K1
PA[1]
1
Input
‡
I/O
GPIO port A
K2
PA[2]
1
Input
‡
I/O
GPIO port A
K3
VDDIO
K18
D[14]
1
Low
I/O
Data I/O
K19
A[14]/DRA[13]
1
Low
O
System byte address
/ SDRAM address
K20
D[15]
1
Low
I/O
Data I/O
L1
TXD[1]
1
High
O
UART 1 transmit
data out
L2
LEDDRV
1
Low
O
IR LED drive
L3
PA[3]
1
Input
I/O
GPIO port A
L18
VDDIO
L19
D[16]
1
Low
I/O
Data I/O
L20
A[16]/DRA[11]
1
Low
O
System byte address
/ SDRAM address
M1
RXD[1]
I
UART 1 receive data
input
M2
CTS
I
UART 1 clear to
send input
M3
PA[0]
1
Input
M18
A[15]/DRA[12]
1
Low
O
System byte address
/ SDRAM address
M19
A[17]/DRA[10]
1
Low
O
System byte address
/ SDRAM address
M20
nTRST
I
JTAG async reset
input
N1
DSR
I
UART 1 data set
ready input
N2
nTEST[1]
I
Test mode select
input
N3
PHDIN
I
Photodiode input
DS506PP1
Pad power
‡
Pad power
With p/u*
‡
I/O
Digital I/O power,
3.3V
Digital I/O power,
3.3V
GPIO port A
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
37
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
Strength
Reset
State
Type
†
Description
N18
D[17]
1
Low
I/O
Data I/O
N19
D[19]
1
Low
I/O
Data I/O
N20
A[18]/DRA[9]
1
Low
O
System byte address
/ SDRAM address
P1
EINT[3]
I
External interrupt
P2
nEINT[2]
I
External interrupt
input
P3
DCD
I
UART 1 data carrier
detect
P18
D[18]
1
Low
I/O
Data I/O
P19
A[20]/DRA[7]
1
Low
O
System byte address
/ SDRAM address
P20
D[20]
1
Low
I/O
Data I/O
R1
nEXTFIQ
R2
PE[2]/CLKSEL
R3
nTEST[0]
R18
A[19]/DRA[8]
1
R19
D[22]
R20
I
1
Input
‡
I/O
External fast
interrupt input
GPIO port E / clock
input mode select
I
Test mode select
input
Low
O
System byte address
/ SDRAM address
1
Low
I/O
Data I/O
A[21]/DRA[6]
1
Low
O
System byte address
/ SDRAM address
T1
PE[1]/BOOTSEL[1]
1
Input
‡
I/O
GPIO port E / boot
mode select
T2
PE[0]/BOOTSEL[0]
1
Input
‡
I/O
GPIO port E / boot
mode select
T3
nEINT[1]
I
External interrupt
input
T18
D[21]
1
Low
I/O
Data I/O
T19
D[23]
1
Low
I/O
Data I/O
T20
A[22]/DRA[5]
1
Low
O
System byte address
/ SDRAM address
U1
VSSRTC
RTC ground
Real time clock
ground
U2
RTCOUT
O
Real time clock
oscillator output
U3
RTCIN
I/O
Real time clock
oscillator input
U18
HALFWORD
1
Low
O
Halfword access
select output
U19
D[24]
1
Low
I/O
Data I/O
U20
A[23]/DRA[4]
1
Low
O
System byte address
/ SDRAM address
V1
VDDRTC
38
With p/u*
RTC power
Real time clock
power, 2.5V
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
†
Strength
Reset
State
Type
Description
V2
VSSIO
Pad ground
I/O ground
V3
VSSIO
Pad ground
I/O ground
V4
PD[7]/SDQM[1]
1
Low
I/O
GPIO port D /
SDRAM byte lane
mask
V5
PD[4]
1
Low
I/O
GPIO port D
V6
PD[2]
1
Low
I/O
GPIO port D
V7
SSICLK
1
Input
I/O
DAI/CODEC/SSI2
serial clock
V8
SSIRXDA
I/O
DAI/CODEC/SSI2
serial data input
V9
nADCCS
O
SSI1 ADC chip
select
V10
VDDIO
V11
ADCCLK
1
V12
COL[7]
V13
COL[4]
V14
TCLK
V15
BUZ
1
V16
D[29]
V17
A[26]/DRA[1]
V18
VDDIO
Pad power
Digital I/O power,
3.3 V
V19
VDDIO
Pad power
Digital I/O power,
3.3 V
V20
A[24]/DRA[3]
W1
VSSIO
Pad ground
I/O ground
W2
VSSIO
Pad ground
I/O ground
W3
VSSIO
Pad ground
I/O ground
W4
PD[6]/SDQM[0]
W5
TMS
with p/u*
W6
PD[1]
1
Low
I/O
GPIO port D
W7
SSITXFR
1
Low
I/O
DAI/CODEC/SSI2
frame sync
W8
SSIRXFR
1
Input
I/O
DAI/CODEC/SSI2
frame sync
W9
VSSCORE
W10
DRIVE[1]
DS506PP1
1
‡
High
Pad power
Digital I/O power,
3.3V
Low
O
SSI1 ADC serial
clock
1
High
O
Keyboard scanner
column drive
1
High
O
Keyboard scanner
column drive
I
JTAG clock
Low
O
Buzzer drive output
1
Low
I/O
Data I/O
2
Low
O
System byte address
/ SDRAM address
‘
1
Low
Low
‡
O
I/O
GPIO port D /
SDRAM byte lane
mask
I
JTAG mode select
Core Ground
2
High /
Low
System byte address
/ SDRAM address
I/O
Core Ground
PWM drive output
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
39
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
Strength
Reset
State
Type
1
Low
O
SSI1 ADC serial
data output
I
PWM feedback input
†
Description
W11
ADCOUT
W12
FB[0]
W13
COL[5]
1
High
O
Keyboard scanner
column drive
W14
COL[2]
1
High
O
Keyboard scanner
column drive
W15
COL[0]
1
High
O
Keyboard scanner
column drive
W16
D[30]
1
Low
I/O
Data I/O
W17
A[27]/DRA[0]
2
Low
O
System byte address
/ SDRAM address
W18
D[26]
1
Low
I/O
Data I/O
W19
VDDIO
W20
D[25]
Y1
VSSIO
Pad ground
I/O ground
Y2
VSSIO
Pad ground
I/O ground
Y3
VSSIO
Pad ground
I/O ground
Y4
PD[5]
1
Low
I/O
GPIO port D
Y5
PD[3]
1
Low
I/O
GPIO port D
Y6
PD[0]/LEDFLSH
1
Low
I/O
GPIO port D / LED
blinker output
Y7
SSITXDA
1
Low
O
DAI/CODEC/SSI2
serial data output
Y8
ADCIN
I
SSI1 ADC serial
input
Y9
VDDCORE
Y10
DRIVE[0]
2
Input
Y11
SMPCLK
1
Low
Y12
FB[1]
Y13
COL[6]
1
Y14
COL[3]
Y15
Pad power
1
Low
I/O
Digital I/O power,
3.3V
Data I/O
Core power
Digital core power,
2.5V
I/O
PWM drive output
O
SSI1 ADC sample
clock
I
PWM feedback input
High
O
Keyboard scanner
column drive
1
High
O
Keyboard scanner
column drive
COL[1]
1
High
O
Keyboard scanner
column drive
Y16
D[31]
1
Low
I/O
Data I/O
Y17
D[28]
1
Low
I/O
Data I/O
Y18
D[27]
1
Low
I/O
Data I/O
Y19
A[25]/DRA[2]
2
Low
O
System byte address
/ SDRAM address
40
‡
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Y20
Reset
State
†
Name
Strength
Type
VDDIO
Description
Digital I/O power,
3.3V
Pad power
*
“With p/u” means with internal pull-up of 100 KOhms on the pin.
†
‡
Strength 1 = 4 ma
Strength 2 = 12 ma
Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
256-Ball PBGA Package Characteristics
256-Ball PBGA Package Specifications
Figure 18. 256-Ball PBGA Package
Note:
1) For pin locations see Table V.
2) Dimensions are in millimeters (inches), and controlling dimension is millimeter
3) Before beginning any new EP7311 design, contact Cirrus Logic for the latest package information.
256-Ball PBGA Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VDDIO
nCS[4]
nCS[1]
SDCLK
SDQM[3]
DD[1]
M
VDDIO
D[0]
D[2]
A[3]
VDDIO
A[6]
B
nCS[5]
VDDIO
nCS[3]
nMOE/
nSDCAS
VDDIO
nSDCS[1]
DD[2]
CL[1]
VDDCORE
D[1]
A[2]
A[4]
A[5]
WAKEUP
VDDIO
nURESET B
C
VDDIO
EXPCLK
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
nPOR
nEXTPWR C
D
WRITE/
nSDRAS
EXPRDY
VSSIO
VDDIO
nCS[2]
nMWE/
nSDWE
nSDCS[0]
CL[2]
VSSRTC
D[4]
nPWRFL
MOSCIN
VDDIO
VSSIO
D[7]
D[8]
D
E
RXD[2]
PB[7]
TDI
WORD
VSSIO
nCS[0]
SDQM[2]
FRM
A[0]
D[5]
VSSOSC
VSSIO
nMEDCHG/
nBROM
VDDIO
D[9]
D[10]
E
F
PB[5]
PB[3]
VSSIO
TXD[2]
RUN/
CLKEN
VSSIO
SDCKE
DD[3]
A[1]
D[6]
VSSRTC
BATOK
nBATCHG
VSSIO
D[11]
VDDIO
F
G
PB[1]
VDDIO
TDO
PB[4]
PB[6]
VSSRTC
VSSRTC
DD[0]
D[3]
VSSRTC
A[7]
A[8]
A[9]
VSSIO
D[12]
D[13]
G
H
PA[7]
PA[5]
VSSIO
PA[4]
PA[6]
PB[0]
PB[2]
VSSRTC
VSSRTC
A[10]
A[11]
A[12]
A[13]/
DRA[14]
VSSIO
D[14]
D[15]
H
J
PA[3]
PA[1]
VSSIO
PA[2]
PA[0]
TXD[1]
CTS
VSSRTC
VSSRTC
A[17]/
DRA[10]
A[16]/
DRA[11]
A[15]/
DRA[12]
A[14]/
DRA[13]
nTRST
D[16]
D[17]
J
PHDIN
VSSIO
DCD
nTEST[1]
EINT[3]
VSSRTC
ADCIN
COL[4]
TCLK
D[20]
D[19]
D[18]
VSSIO
VDDIO
VDDIO
K
DSR
VDDIO
nEINT[1]
PE[2]/
CLKSEL
VSSRTC
COL[6]
D[31]
VSSRTC
A[22]/
DRA[5]
A[21]/
DRA[6]
VSSIO
A[18]/
DRA[9]
A[19]/
DRA[8]
L
nEINT[2]
VDDIO
PE[0]/
BOOTSEL[0]
TMS
VDDIO
SSITXFR
DRIVE[1]
FB[0]
COL[0]
D[27]
VSSIO
A[23]/
DRA[4]
VDDIO
A[20]/
DRA[7]
D[21]
M
VDDIO
PD[5]
PD[2]
SSIRXDA
ADCCLK
SMPCLK
COL[2]
D[29]
D[26]
HALFWORD
VSSIO
D[22]
D[23]
N
K LEDDRV
L
RXD[1]
M nTEST[0]
N nEXTFIQ
P VSSRTC
R
PE[1]/
VSSIO
BOOTSEL[1]
15
MOSCOUT VDDOSC
16
VSSIO
A
RTCOUT
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
D[24]
VDDIO
P
VDDIO
PD[4]
PD[1]
SSITXDA
nADCCS
VDDIO
ADCOUT
COL[7]
COL[3]
COL[1]
D[30]
A[27]/
DRA[0]
A[25]/
DRA[2]
VDDIO
A[24]\
DRA[3]
R
PD[7]/
SDQM[1]
PD[6]/
SDQM[0]
PD[3]
SSICLK
FB[1]
COL[5]
VDDIO
BUZ
D[28]
A[26]/
DRA[1]
D[25]
VSSIO
T
RTCIN
T VDDRTC
PD[0]/
VSSRTC
LEDFLSH
14
DS506PP1
SSIRXFR VDDCORE DRIVE[0]
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
41
EP7311
High-Performance, Low-Power System on Chip
0.85 (0.034)
±0.05 (.002)
17.00 (0.669)
±0.20 (.008)
Pin 1 Corner
D1
0.40 (0.016)
±0.05 (.002)
15.00 (0.590)
±0.20 (.008)
30° TYP
Pin 1 Indicator
17.00 (0.669)
±0.20 (.008)
E1
15.00 (0.590)
±0.20 (.008)
2 Layer
0.36 (0.014)
±0.09 (0.004)
TOP VIEW
SIDE VIEW
D
17.00 (0.669)
Pin 1 Corner
1.00 (0.040)
1.00 (0.040)
REF
E
16 15 14 13 12 11 10 9 8 7
6 5
1.00 (0.040)
REF
42
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1.00 (0.040)
0.50
R
3 Places
4 3 2
17.00 (0.669)
BOTTOM VIEW
JEDEC #: MO-151
Ball Diameter: 0.50 mm ± 0.10 mm
17 ¥ 17 ¥ 1.61 mm body
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
256-Ball PBGA Ball Listing
The list is ordered by ball location.
Table V. 256-Ball PBGA Ball Listing (Continued)
Table V. 256-Ball PBGA Ball Listing
Ball Location
Name
Type
A1
VDDIO
Pad power
nCS[4]
O
Chip select out
A3
nCS[1]
O
Chip select out
A4
SDCLK
O
SDRAM clock out
A5
SDQM[3]
O
SDRAM byte lane mask
A6
DD[1]
O
LCD serial display data
M
O
A8
VDDIO
Pad power
Name
Type
Description
C12
VDDIO
Pad power
Digital I/O power, 3.3V
C13
VSSIO
Pad ground
I/O ground
C14
VSSIO
Pad ground
I/O ground
C15
nPOR
I
Power-on reset input
C16
nEXTPWR
I
External power supply sense input
D1
WRITE/nSDRAS
O
Transfer direction / SDRAM RAS signal
output
Digital I/O power, 3.3V
A2
A7
Ball Location
Description
LCD AC bias drive
D2
EXPRDY
I
Digital I/O power, 3.3V
D3
VSSIO
Pad ground
I/O ground
Digital I/O power, 3.3V
Expansion port ready input
A9
D[0]
I/O
Data I/O
D4
VDDIO
Pad power
A10
D[2]
I/O
Data I/O
D5
nCS[2]
O
Chip select out
A11
A[3]
O
System byte address
D6
nMWE/nSDWE
O
ROM, expansion write enable/ SDRAM
write enable control signal
A12
VDDIO
Pad power
D7
nSDCS[0]
O
SDRAM chip select out
A13
A[6]
O
D8
CL[2]
O
LCD pixel clock out
A14
MOSCOUT
O
A15
VDDOSC
Oscillator
power
A16
VSSIO
Pad ground
B1
nCS[5]
O
B2
VDDIO
Pad power
B3
nCS[3]
O
B4
nMOE/nSDCAS
O
Digital I/O power, 3.3V
System byte address
Main oscillator out
D9
VSSRTC
D10
D[4]
I/O
I/O ground
D11
nPWRFL
I
Power fail sense input
Chip select out
D12
MOSCIN
I
Main oscillator input
I/O ground
D13
VDDIO
Pad power
Digital I/O power, 3.3V
Chip select out
D14
VSSIO
Pad ground
I/O ground
ROM, expansion OP enable/SDRAM
CAS control signal
D15
D[7]
I/O
Data I/O
D16
D[8]
I/O
Data I/O
E1
RXD[2]
I
UART 2 receive data input
E2
PB[7]
I
GPIO port B
E3
TDI
I
JTAG data input
E4
WORD
O
Word access select output
E5
VSSIO
Pad ground
E6
nCS[0]
O
E7
SDQM[2]
O
SDRAM byte lane mask
E8
FRM
O
LCD frame synchronization pulse
Oscillator power in, 2.5V
B5
VDDIO
Pad power
Digital I/O power, 3.3V
B6
nSDCS[1]
O
SDRAM chip select out
B7
B8
DD[2]
CL[1]
B9
VDDCORE
B10
D[1]
B11
B12
A[2]
A[4]
O
O
LCD line clock
Core power Digital core power, 2.5V
I/O
O
O
System byte address
A[5]
O
System byte address
I
System wake up input
B15
VDDIO
Pad power
B16
nURESET
I
C1
VDDIO
Pad power
Digital I/O power, 3.3V
C2
EXPCLK
I
Expansion clock input
C3
VSSIO
Pad ground
I/O ground
C4
VDDIO
Pad power
Digital I/O power, 3.3V
C5
VSSIO
Pad ground
I/O ground
User reset input
VSSIO
Pad ground
I/O ground
C7
VSSIO
Pad ground
I/O ground
C8
VDDIO
Pad power
Digital I/O power, 3.3V
C9
VSSIO
Pad ground
I/O ground
DS506PP1
VSSIO
Pad ground
E9
A[0]
O
System byte address
E10
D[5]
I/O
Data I/O
E11
VSSOSC
Oscillator
ground
PLL ground
E12
VSSIO
Pad ground
I/O ground
E13
nMEDCHG/nBROM
I
E14
VDDIO
Pad power
Digital I/O power, 3.3V
C6
C11
Chip select out
System byte address
WAKEUP
Pad ground
I/O ground
Data I/O
B14
VSSIO
Data I/O
LCD serial display data
B13
C10
Core ground Real time clock ground
Media change interrupt input / internal
ROM boot enable
Digital I/O power, 3.3V
E15
D[9]
I/O
Data I/O
E16
D[10]
I/O
Data I/O
F1
PB[5]
I
GPIO port B
F2
PB[3]
I
GPIO port B
F3
VSSIO
Pad ground
F4
TXD[2]
O
UART 2 transmit data output
F5
RUN/CLKEN
O
Run output / clock enable output
F6
VSSIO
Pad ground
I/O ground
I/O ground
I/O ground
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
I/O ground
43
EP7311
High-Performance, Low-Power System on Chip
Table V. 256-Ball PBGA Ball Listing (Continued)
Table V. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
F7
SDCKE
O
SDRAM clock enable output
J7
CTS
F8
DD[3]
O
LCD serial display data
J8
VSSRTC
RTC ground Real time clock ground
RTC ground Real time clock ground
44
Description
Ball Location
Name
Type
I
Description
UART 1 clear to send input
F9
A[1]
O
System byte address
J9
VSSRTC
F10
D[6]
I/O
Data I/O
J10
A[17]/DRA[10]
O
System byte address / SDRAM address
F11
VSSRTC
RTC ground Real time clock ground
J11
A[16]/DRA[11]
O
System byte address / SDRAM address
F12
BATOK
Battery ok input
J12
A[15]/DRA[12]
O
System byte address / SDRAM address
F13
nBATCHG
I
F14
VSSIO
Pad ground
I
F15
D[11]
I/O
F16
VDDIO
Pad power
Battery changed sense input
J13
A[14]/DRA[13]
O
System byte address / SDRAM address
I/O ground
J14
nTRST
I
JTAG async reset input
Data I/O
J15
D[16]
I/O
Data I/O
Digital I/O power, 3.3V
J16
D[17]
I/O
Data I/O
G1
PB[1]
I
G2
VDDIO
Pad power
GPIO port B
K1
LEDDRV
O
IR LED drivet
Digital I/O power, 3.3V
K2
PHDIN
I
Photodiode input
G3
TDO
O
G4
PB[4]
I
JTAG data out
K3
VSSIO
Pad ground
GPIO port B
K4
DCD
I
UART 1 data carrier detect
I
GPIO port B
I/O ground
G5
PB[6]
K5
nTEST[1]
I
Test mode select input
G6
VSSRTC
Core ground Real time clock ground
K6
EINT[3]
I
External interrupt
G7
VSSRTC
RTC ground Real time clock ground
K7
VSSRTC
G8
DD[0]
K8
ADCIN
I
RTC ground Real time clock ground
O
LCD serial display data
SSI1 ADC serial input
I/O
Data I/O
K9
COL[4]
O
Keyboard scanner column drive
RTC ground Real time clock ground
K10
TCLK
I
JTAG clock
G9
D[3]
G10
VSSRTC
G11
A[7]
O
System byte address
K11
D[20]
I/O
Data I/O
G12
A[8]
O
System byte address
K12
D[19]
I/O
Data I/O
G13
A[9]
O
G14
VSSIO
Pad ground
System byte address
K13
D[18]
I/O
I/O ground
K14
VSSIO
Pad ground
I/O ground
G15
D[12]
G16
D[13]
H1
PA[7]
I
H2
PA[5]
I
H3
VSSIO
Pad ground
H4
PA[4]
I
I/O
Data I/O
K15
VDDIO
Pad power
Digital I/O power, 3.3V
I/O
Data I/O
K16
VDDIO
Pad power
Digital I/O power, 3.3V
GPIO port A
L1
RXD[1]
I
GPIO port A
L2
DSR
I
I/O ground
L3
VDDIO
Pad power
Digital I/O power, 3.3V
GPIO port A
L4
nEINT[1]
I
External interrupt input
I
GPIO port E / clock input mode select
H5
PA[6]
I
GPIO port A
L5
PE[2]/CLKSEL
H6
PB[0]
I
GPIO port B
L6
VSSRTC
I
GPIO port B
L7
PD[0]/LEDFLSH
L8
VSSRTC
H7
PB[2]
H8
VSSRTC
RTC ground Real time clock ground
RTC ground Real time clock ground
Data I/O
UART 1 receive data input
UART 1 data set ready input
RTC ground Real time clock ground
I/O
GPIO port D / LED blinker output
Core ground Real time clock ground
H9
VSSRTC
L9
COL[6]
O
Keyboard scanner column drive
H10
A[10]
O
System byte address
L10
D[31]
I/O
Data I/O
H11
A[11]
O
System byte address
L11
VSSRTC
H12
A[12]
O
System byte address
L12
A[22]/DRA[5]
H13
A[13]/DRA[14]
O
H14
VSSIO
Pad ground
H15
D[14]
H16
D[15]
J1
PA[3]
J2
PA[1]
J3
VSSIO
Pad ground
J4
PA[2]
I
RTC ground Real time clock ground
O
System byte address / SDRAM address
System byte address / SDRAM address
L13
A[21]/DRA[6]
O
I/O ground
L14
VSSIO
Pad ground
I/O
Data I/O
L15
A[18]/DRA[9]
O
System byte address / SDRAM address
I/O
Data I/O
L16
A[19]/DRA[8]
O
System byte address / SDRAM address
I
GPIO port A
M1
nTEST[0]
I
Test mode select input
I
GPIO port A
M2
nEINT[2]
I
External interrupt input
I/O ground
M3
VDDIO
Pad power
Digital I/O power, 3.3V
GPIO port A
M4
PE[0]/BOOTSEL[0]
I
J5
PA[0]
I
GPIO port A
M5
TMS
I
J6
TXD[1]
O
UART 1 transmit data out
M6
VDDIO
Pad power
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
System byte address / SDRAM address
I/O ground
GPIO port E / Boot mode select
JTAG mode select
Digital I/O power, 3.3V
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table V. 256-Ball PBGA Ball Listing (Continued)
Type
Table V. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Description
Ball Location
M7
SSITXFR
I/O
MCP/CODEC/SSI2 frame sync
M8
DRIVE[1]
I/O
PWM drive output
Name
Type
Description
R7
VDDIO
Pad power
R8
ADCOUT
O
SSI1 ADC serial data output
Digital I/O power, 3.3V
M9
FB[0]
I
PWM feedback input
R9
COL[7]
O
Keyboard scanner column drive
M10
COL[0]
O
Keyboard scanner column drive
R10
COL[3]
O
Keyboard scanner column drive
M11
D[27]
I/O
Data I/O
R11
COL[1]
O
Keyboard scanner column drive
M12
VSSIO
Pad ground
I/O ground
R12
D[30]
I/O
Data I/O
M13
A[23]/DRA[4]
O
System byte address / SDRAM address
M14
VDDIO
Pad power
M15
A[20]/DRA[7]
M16
System byte address / SDRAM address
R13
A[27]/DRA[0]
O
Digital I/O power, 3.3V
R14
A[25]/DRA[2]
O
O
System byte address / SDRAM address
R15
VDDIO
Pad power
D[21]
I/O
Data I/O
R16
A[24]/DRA[3]
O
N1
nEXTFIQ
I
External fast interrupt input
T1
VDDRTC
RTC power
N2
PE[1]/BOOTSEL[1]
I
GPIO port E / boot mode select
T2
PD[7]/SDQM[1]
I/O
N3
VSSIO
Pad ground
I/O ground
T3
PD[6]/SDQM[0]
I/O
GPIO port D / SDRAM byte lane mask
N4
VDDIO
Pad power
Digital I/O power, 3.3V
T4
PD[3]
I/O
GPIO port D
N5
PD[5]
I/O
GPIO port D
T5
SSICLK
I/O
MCP/CODEC/SSI2 serial clock
N6
PD[2]
I/O
GPIO port D
T6
SSIRXFR
–
MCP/CODEC/SSI2 frame sync
N7
SSIRXDA
I/O
MCP/CODEC/SSI2 serial data input
T7
VDDCORE
N8
ADCCLK
O
SSI1 ADC serial clock
T8
DRIVE[0]
System byte address / SDRAM address
Digital I/O power, 3.3V
System byte address / SDRAM address
Real time clock power, 2.5V
GPIO port D / SDRAM byte lane mask
Core power Core power, 2.5V
I/O
PWM drive output
N9
SMPCLK
O
SSI1 ADC sample clock
T9
FB[1]
I
PWM feedback input
N10
COL[2]
O
Keyboard scanner column drive
T10
COL[5]
O
Keyboard scanner column drive
N11
D[29]
I/O
Data I/O
T11
VDDIO
Pad power
N12
D[26]
I/O
Data I/O
T12
BUZ
O
Buzzer drive output
N13
HALFWORD
O
Data I/O
N14
VSSIO
Pad ground
N15
D[22]
N16
D[23]
Halfword access select output
T13
D[28]
I/O
I/O ground
T14
A[26]/DRA[1]
O
System byte address / SDRAM address
I/O
Data I/O
T15
D[25]
I/O
Data I/O
I/O
Data I/O
T16
VSSIO
Pad ground
P1
VSSRTC
P2
RTCOUT
O
P3
VSSIO
Pad ground
I/O ground
P4
VSSIO
Pad ground
I/O ground
P5
VDDIO
Pad power
Digital I/O power, 3.3V
P6
VSSIO
Pad ground
I/O ground
P7
VSSIO
Pad ground
I/O ground
P8
VDDIO
Pad power
Digital I/O power, 3.3V
I/O ground
RTC ground Real time clock ground
Real time clock oscillator output
P9
VSSIO
Pad ground
I/O ground
P10
VDDIO
Pad power
Digital I/O power, 3.3V
P11
VSSIO
Pad ground
I/O ground
P12
VSSIO
Pad ground
I/O ground
P13
VDDIO
Pad power
Digital I/O power
P14
VSSIO
Pad ground
P15
D[24]
I/O
P16
VDDIO
Pad power
I/O ground
Data I/O
Digital I/O power, 3.3V
R1
RTCIN
I/O
R2
VDDIO
Pad power
R3
PD[4]
I/O
GPIO port D
R4
PD[1]
I/O
GPIO port D
R5
SSITXDA
O
MCP/CODEC/SSI2 serial data output
R6
nADCCS
O
SSI1 ADC chip select
DS506PP1
Digital I/O power, 3.3V
Real time clock oscillator input
Digital I/O power, 3.3V
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
45
EP7311
High-Performance, Low-Power System on Chip
JTAG Boundary Scan Signal Ordering
Table W. JTAG Boundary Scan Signal Ordering
46
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball
Signal
Type
Position
1
B3
B1
nCS[5]
O
1
4
A2
C2
EXPCLK
I/O
3
5
B1
E4
WORD
O
6
6
E3
D1
WRITE/nSDRAS
O
8
7
C1
F5
RUN/CLKEN
O
10
8
C2
D2
EXPRDY
I
13
9
E2
F4
TXD2
O
14
10
D2
E1
RXD2
I
16
13
F3
E2
PB[7]
I/O
17
14
D1
G5
PB[6]
I/O
20
15
F2
F1
PB[5]
I/O
23
16
G3
G4
PB[4]
I/O
26
17
E1
F2
PB[3]
I/O
29
18
F1
H7
PB[2]
I/O
32
19
G2
G1
PB[1]/PRDY2
I/O
35
20
G1
H6
PB[0]/PRDY1
I/O
38
23
H3
H1
PA[7]
I/O
41
24
H1
H5
PA[6]
I/O
44
25
J3
H2
PA[5]
I/O
47
26
J2
H4
PA[4]
I/O
50
27
J1
J1
PA[3]
I/O
53
28
L3
J4
PA[2]
I/O
56
29
K2
J2
PA[1]
I/O
59
30
K1
J5
PA[0]
I/O
62
31
M3
K1
LEDDRV
O
65
32
L2
J6
TXD1
O
67
34
L1
K2
PHDIN
I
69
35
N3
J7
CTS
I
70
36
M2
L1
RXD1
I
71
37
M1
K4
DCD
I
72
38
P3
L2
DSR
I
73
39
N1
K5
nTEST1
I
74
40
N2
M1
nTEST0
I
75
41
R3
K6
EINT3
I
76
42
P1
M2
nEINT2
I
77
43
P2
L4
nEINT1
I
78
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table W. JTAG Boundary Scan Signal Ordering (Continued)
DS506PP1
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball
Signal
Type
Position
44
T3
N1
nEXTFIQ
I
79
45
R1
L5
PE[2]/CLKSEL
I/O
80
46
R2
N2
PE[1]/BOOTSEL1
I/O
83
47
T1
M4
PE[0]/BOOTSEL0
I/O
86
53
T2
T2
PD[7]/SDQM[1]
I/O
89
54
V4
T3
PD[6/SDQM[0]]
I/O
92
55
W4
N5
PD[5]
I/O
95
56
Y4
R3
PD[4]
I/O
98
59
V5
T4
PD[3]
I/O
101
60
W5
N6
PD[2]
I/O
104
61
Y5
R4
PD[1]
I/O
107
62
V6
L7
PD[0]/LEDFLSH
O
110
68
W6
T6
SSIRXFR
I/O
122
69
Y6
K8
ADCIN
I
125
70
W8
R6
nADCCS
O
126
75
Y8
M8
DRIVE1
I/O
128
76
V9
T8
DRIVE0
I/O
131
77
W10
N8
ADCCLK
O
134
78
Y10
R8
ADCOUT
O
136
79
V11
N9
SMPCLK
O
138
80
W11
T9
FB1
I
140
82
Y11
M9
FB0
I
141
83
Y12
R9
COL7
O
142
84
W12
L9
COL6
O
144
85
V12
T10
COL5
O
146
86
Y13
K9
COL4
O
148
87
W13
R10
COL3
O
150
88
V13
N10
COL2
O
152
91
Y14
R11
COL1
O
154
92
W14
M10
COL0
O
156
93
A1
T12
BUZ
O
158
94
V14
L10
D[31]
I/O
160
95
Y15
R12
D[30]
I/O
163
96
W15
N11
D[29]
I/O
166
97
V15
T13
D[28]
I/O
169
99
Y16
R13
A[27]/DRA[0]
Out
172
100
W16
M11
D[27]
I/O
174
101
V16
T14
A[26]/DRA[1]
O
177
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
47
EP7311
High-Performance, Low-Power System on Chip
Table W. JTAG Boundary Scan Signal Ordering (Continued)
48
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball
Signal
Type
Position
102
Y17
N12
D[26]
I/O
179
103
W17
R14
A[25]/DRA[2]
O
182
104
Y18
T15
D[25]
I/O
184
105
V17
N13
HALFWORD
O
187
106
W18
R16
A[24]/DRA[3]
O
189
109
Y19
P15
D[24]
I/O
191
110
W20
M13
A[23]/DRA[4]
O
194
111
U18
N16
D[23]
I/O
196
112
V20
L12
A[22]/DRA[5]
O
199
113
U19
N15
D[22]
I/O
201
114
U20
L13
A[21]/DRA[6]
O
204
115
T19
M16
D[21]
I/O
206
117
T20
M15
A[20]/DRA[7]
O
209
118
R19
K11
D[20]
I/O
211
119
R20
L16
A[19]/DRA[8]
O
214
120
T18
K12
D[19]
I/O
216
121
P19
L15
A[18]/DRA[9]
O
219
122
P20
K13
D[18]
I/O
221
126
R18
J10
A[17]/DRA[10]
O
224
127
N19
J16
D[17]
I/O
226
128
N20
J11
A[16]/DRA[11]
O
229
129
P18
J15
D[16]
I/O
231
130
M19
J12
A[15]/DRA[12]
O
234
131
N18
H16
D[15]
I/O
236
132
L20
J13
A[14]/DRA[13]
O
239
133
L19
H15
D[14]
I/O
241
134
M18
H13
A[13]/DRA[14]
O
244
135
K20
G16
D[13]
I/O
246
136
K19
H12
A[12]
O
249
137
K18
G15
D[12]
I/O
251
138
J20
H11
A[11]
O
254
141
J19
F15
D[11]
I/O
256
142
H20
H10
A[10]
O
259
143
H19
E16
D[10]
I/O
261
144
J18
G13
A[9]
O
264
145
K3
E15
D[9]
I/O
266
146
Y3
G12
A[8]
O
269
147
G20
D16
D[8]
I/O
271
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table W. JTAG Boundary Scan Signal Ordering (Continued)
DS506PP1
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball
Signal
Type
Position
148
H18
G11
A[7]
O
274
150
F20
D15
D[7]
I/O
276
151
G19
F13
nBATCHG
I
279
152
E20
C16
nEXTPWR
I
280
153
F19
F12
BATOK
I
281
154
G18
C15
nPOR
I
282
155
D20
E13
nMEDCHG/nBROM
I
283
156
F18
B16
nURESET
I
284
161
D19
B14
WAKEUP
I
285
162
E19
D11
nPWRFL
I
286
163
C19
A13
A[6]
O
287
164
C20
F10
D[6]
I/O
289
165
E18
B13
A[5]
O
292
166
B20
E10
D[5]
I/O
294
169
B16
B12
A[4]
O
297
170
A16
D10
D[4]
I/O
299
171
C15
A11
A[3]
O
302
172
B15
G9
D[3]
I/O
304
173
A15
B11
A[2]
O
307
175
C14
A10
D[2]
I/O
309
176
B14
F9
A[1]
O
312
177
A14
B10
D[1]
I/O
314
178
C13
E9
A[0]
O
317
179
B13
A9
D[0]
I/O
319
184
A13
D8
CL2
O
322
185
C12
B8
CL1
O
324
186
B12
E8
FRM
O
326
187
A12
A7
M
O
328
188
C11
F8
DD[3]
I/O
330
189
B11
B7
DD[2]
I/O
333
191
B10
A6
DD[1]
I/O
336
192
A10
G8
DD[0]
I/O
339
193
A9
B6
nSDCS[1]
O
342
194
B9
D7
nSDCS[0]
O
344
195
C9
A5
SDQM[3]
I/O
346
196
A8
E7
SDQM[2]
I/O
349
199
B8
F7
SDCKE
I/O
352
200
C8
A4
SDCLK
I/O
355
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
49
EP7311
High-Performance, Low-Power System on Chip
Table W. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball
Signal
Type
Position
201
A7
D6
nMWE/nSDWE
O
358
202
B7
B4
nMOE/nSDCAS
O
360
204
C7
E6
nCS[0]
O
362
205
A6
A3
nCS[1]
O
364
206
B6
D5
nCS[2]
O
366
207
C6
B3
nCS[3]
O
368
208
A5
A2
nCS[4]
O
370
1) See EP7311 Users’ Manual for pin naming / functionality.
2) For each pad, the JTAG connection ordering is input,
output, then enable as applicable.
50
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
CONVENTIONS
Table X. Acronyms and Abbreviations (Continued)
Acronym/
Abbreviation
This section presents acronyms, abbreviations, units of
measurement, and conventions used in this data sheet.
Acronyms and Abbreviations
Table X lists abbreviations and acronyms used in this
data sheet.
Table X. Acronyms and Abbreviations
Acronym/
Abbreviation
Definition
TAP
test access port
TLB
translation lookaside buffer
UART
universal asynchronous receiver
Units of Measurement
Table Y. Unit of Measurement
Definition
Symbol
Unit of Measure
A/D
analog-to-digital
ADC
analog-to-digital converter
°C
degree Celsius
CODEC
coder / decoder
fs
sample frequency
D/A
digital-to-analog
Hz
hertz (cycle per second)
DMA
direct-memory access
kbps
kilobits per second
EPB
embedded peripheral bus
KB
kilobyte (1,024 bytes)
FCS
frame check sequence
kHz
kilohertz
FIFO
first in / first out
kΩ
kilohm
FIQ
fast interrupt request
Mbps
megabits (1,048,576 bits) per second
GPIO
general purpose I/O
MB
megabyte (1,048,576 bytes)
ICT
in circuit test
MBps
megabytes per second
IR
infrared
MHz
megahertz (1,000 kilohertz)
IRQ
standard interrupt request
µA
microampere
IrDA
Infrared Data Association
µF
microfarad
JTAG
Joint Test Action Group
µW
microwatt
LCD
liquid crystal display
µs
microsecond (1,000 nanoseconds)
LED
light-emitting diode
mA
milliampere
LQFP
low profile quad flat pack
mW
milliwatt
LSB
least significant bit
ms
millisecond (1,000 microseconds)
MIPS
millions of instructions per second
ns
nanosecond
MMU
memory management unit
V
volt
MSB
most significant bit
W
watt
PBGA
plastic ball grid array
PCB
printed circuit board
PDA
personal digital assistant
PLL
phase locked loop
p/u
pull-up resistor
RISC
reduced instruction set computer
RTC
Real-Time Clock
SIR
slow (9600–115.2 kbps) infrared
SRAM
static random access memory
SSI
synchronous serial interface
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
51
EP7311
High-Performance, Low-Power System on Chip
General Conventions
Pin Description Conventions
Hexadecimal numbers are presented with all letters in
uppercase and a lowercase “h” appended or with a 0x at
the beginning. For example, 0x14 and 03CAh are
hexadecimal numbers. Binary numbers are enclosed in
single quotation marks when in text (for example, ‘11’
designates a binary number). Numbers not indicated by
an “h”, 0x or quotation marks are decimal.
Abbreviations used for signal directions are listed in
Table Z.
Registers are referred to by acronym, with bits listed in
brackets separated by a colon (:) (for example,
CODR[7:0]), and are described in the EP7311 User’s
Manual. The use of “TBD” indicates values that are “to
be determined,” “n/a” designates “not available,” and
“n/c” indicates a pin that is a “no connect.”
52
Table Z. Pin Description Conventions
Abbreviation
Direction
I
Input
O
Output
I/O
Input or Output
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
ORDERING INFORMATION
The order number for the device is:
EP7311 — CV — C
Revision †
Package Type:
V = Low Profile Quad Flat Pack
B = Plastic Ball Grid Array (17 mm x 17 mm)
R = Reduced Ball Grid Array (13 mm x 13 mm)
Part Number
Product Line:
Embedded Processor
Note:
DS506PP1
Temperature Range:
C = Commercial
E = Extended Operating Version
I = Industrial Operating Version
Contact Cirrus Logic for up-to-date information on revisions. Go to the Cirrus Logic Internet site at
http://cirrus.com/corporate/contacts to find contact information for your local sales representative.
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
53
EP7311
High-Performance, Low-Power System on Chip
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
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54
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1