F81485 F81485 5V Low Power RS-485 Interface Transceiver Release Date: Jan, 2012 Version: V0.11P Jan, 2012 V0.11P F81485 F81485 Datasheet Revision History Version V0.10P Date 2011/12 Page - V0.12P 2012/01 - Revision History Preliminary Made Clarification and Correction Update Top Marking Specification Update Differential Input Threshold Spec. Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. Jan, 2012 V0.11P F81485 Table of Content 1 General Description ................................................................................................................................................. 4 2 Feature List.............................................................................................................................................................. 4 3 Pin Configuration ..................................................................................................................................................... 5 4 Pin Description ........................................................................................................................................................ 5 5 Electrical Characteristics Request .......................................................................................................................... 7 6 Ordering Information ............................................................................................................................................. 10 7 Top Marking Specification ..................................................................................................................................... 10 8 Package Spec. ...................................................................................................................................................... 11 9 Application Circuit .................................................................................................................................................. 12 Jan, 2012 V0.11P F81485 1 General Description The F81485 is a CMOS design, features with single 5 V power supply, and low power differential bus/line transceiver suitable for the multipoint data transmission EIA standard RS485 and RS422 applications. The extended common-mode range is −7 V to +12 V. Both the driver and the receiver can be enabled independently. The driver and receiver feature three-state outputs, with the driver outputs maintaining high impedance over the entire common-mode range. Excessive power dissipation caused by the bus contention or faults is prevented by a thermal shutdown circuit which forces the driver outputs into a high impedance state. The receiver contains a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating). Up to 32 transceivers can be connected simultaneously on a bus, but only one driver should be enabled at any time. The F81485 features extremely fast switching speeds. Minimal driver propagation delays permit transmission at data rates up to 5 Mbps while low skew minimizes EMI interference. All inputs and outputs contain protection against ESD; all driver outputs feature high source and sink current capability. An epitaxial layer is used to guard against latch-up. 2 Feature List z Single 5V Supply z Meets EIA RS-485 standard z High speed, low power BiCMOS z -7V to 12V Bus Common-Mode Range Permits z ±7V Ground Difference Between Devices on the Bus z ESD ±8KV Contact z Thermal Shutdown Protection z Driver Maintains High Impedance in Three-State or with the Power Off z 70mV Typical Input Hysteresis z Driver propagation delay: 10 ns typical z Receiver propagation delay: 15 ns typical z High-Z outputs with power off z Pin Compatible with the ADM485, SP485 z 8 Pin SOP Packaging 4 Jan, 2012 V0.11P F81485 3 Pin Configuration F81485 4 8 Vcc 2 7 B DE 3 6 A DI 4 5 GND RO 1 RE R D Pin Description INt O4 P - TTL level input pin. - Output pin with 4mA driver. - Power. 4.1. Power Pin Pin Pin Name Type 5 8 GND VCC P P Description GND. 4.75V< VCC < 5.25V power supply voltage input. 4.2. Transceiver Pin Pin Name Type 1 RO O4 2 RE# INt 3 DE INt Description Receiver Output. When enabled (RE# is low), then if A > B by 200 mV, RO is high. A < B by 200 mV, RO is low. Active Low Receiver Output Enable pin. A low level enables the receiver output, RO. A high level places it in a high impedance state. Active High Driver Output Enable. A high level enables the driver differential outputs, A and B. The chip will function as a line driver. A low level places it in a high impedance state. The chip will function as a line receiver. 5 Jan, 2012 V0.11P F81485 4 DI INt 6 7 A B I/O I/O Driver Input. When the driver is enabled (DE is high), a logic low on DI forces A low and B high, while a logic high on DI forces A high and B low. Non-inverting Receiver Input A/Driver Output A. Inverting Receiver Input B/Driver Output B. Transmitting Inputs RE# DE DI X X X X 1 1 0 1 1 0 X X Line Conditio n No Fault No Fault X Fault Outputs B A 0 1 Z Z 1 0 Z Z Receiving Inputs RE# 0 0 0 1 DE 0 0 0 0 A-B ≥0.2V ≤0.2V Inputs Open X 6 Ouptuts R 1 0 1 Z Jan, 2012 V0.11P F81485 5 Electrical Characteristics Request 5.1 Absolute Maximum Ratings PARAMETER RATING UNIT Vcc ±12 V Input Voltage Output Voltage Logic -0.3 to Vcc +0.5 V Drivers -0.3 to Vcc +0.5 V Receivers ±15 Logic -0.3 to Vcc +0.5 V Drivers ±15 V Receivers -0.3 to Vcc +0.5 °C Storage Tempreature -65 to +150 Lead Temperature (soldering, 10s) +300 °C Power Disspation 500 mW Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device Test condition: VCC = 5V PARAMETER Supply Voltage Supply Current Operating Temperature 5.2 SYMBOL MIN. TYP. 4.75 MAX UNIT CONDITIONS 5.25 V μA No Load 900 0 70 。C MAX UNIT Vcc V Driver Section Test condition: VCC = 5V PARAMETER SYMBOL MIN. TYP. CONDITIONS DC Characteristics GND Differential Output Voltage 2 1.5 Differential Output Voltage for Complimentary States Output Voltage Input High Voltage Input Low Voltage Input Current Driver Short Current Vcc V Vcc V 0.2 V 3 V V V μA 2.0 0.8 ±10 35 250 mA 35 250 mA 7 Unloaded, R= ∞ With load, R = 50Ω (RS422) With load, R = 27Ω (RS485) R = 27Ω or R = 50Ω R = 27Ω or R = 50Ω Applies to DE, DI, RE# Applies to DE, DI, RE# Applies to DE, DI, RE# VOUT = High, -7V ≤ Vo ≤ +12V VOUT = Low, -7V ≤ Vo ≤ +12V Jan, 2012 V0.11P F81485 PARAMETER SYMBOL MIN. TYP. MAX UNIT CONDITIONS AC Characteristics Maximum Data Rate 5 Driver Input to Output 20 30 60 ns 20 30 60 ns 5 10 ns tSKEW =⏐ tDPLH - tDPHL ⏐ 15 40 ns 10% to 90%, RDIFF = 54Ω, CL1 = CL2 = 100pF 40 70 ns CL1 = 100pF 40 70 ns CL1 = 100pF 40 70 ns CL1 = 15pF 40 70 ns CL1 = 15pF TYP. MAX UNIT CONDITIONS +0 mV mV -7V ≤ VCM ≤ +12V V Io = -4mA, VID = +200mV Io = +4mA, VID = 200mV 0.4V ≤ Vo ≤ 2.4V, RE# = -5V 3 Driver Enable to Output High Driver Enable to Output Low Driver Disable Time from Low Driver Disable Time from High 5.3 RE# = 5V, DE = 5V tPLH; RDIFF = 54Ω, CL1 = CL2 = 100pF tPHL; RDIFF = 54Ω, CL1 = CL2 = 100pF Driver Skew Driver Rise or Fall Time Mbps Receiver Section Test condition: VCC = 5V PARAMETER SYMBOL MIN. DC Characteristics Differential Input Threshold Input Hysteresis Output Voltage High -300 10 3.5 Output Voltage Low 0.4 V Output Current ±1 μA Input Resistance Input Current (A,B), VIN = 12V Input Current (A,B), VIN = 7V Short Circuit Current 12 7 15 VCM = 0V k -7V ≤ VCM ≤ +12V +1.0 mA DE = 0V, Vcc = 0V or 5.25V, VIN = 12V -0.8 mA DE = 0V, Vcc = 0V or 5.25V, VIN = -7V 95Ω mA 0V ≤ VCM ≤ Vcc 8 Jan, 2012 V0.11P F81485 PARAMETER SYMBOL MIN. TYP. MAX UNIT CONDITIONS AC Characteristics Maximum Data Rate Receiver Input to Output Receiver Skew Receiver Enable to Output Low Receiver Enable to Output High Receiver Disable Time from Low Receiver Disable Time from High 5 Mbps RE# = 0V, DE = 0V 60 90 200 ns 60 90 200 ns tPLH; RDIFF = 54Ω, CL1 = CL2 = 100pF tPHL; RDIFF = 54Ω, CL1 = CL2 = 100pF ns tSKEW =⏐ tDPLH - tDPHL ⏐ 13 20 50 ns CRL = 15pF 20 50 ns CRL = 15pF 20 50 ns CRL = 15pF 20 50 ns CRL = 15pF 9 Jan, 2012 V0.11P F81485 6 Ordering Information Part Number F81485S 7 Package Type 8-SOP Green Package Production Flow Commercial, 0°C to +70°C Top Marking Specification The version identification is shown as the bold red characters. Please refer to below for detail: F81485S XXXXXXX XXXXXX.X ● 1st Line: Fintek Logo 2nd Line: Device Name Æ F81485S, where S means 8-SOP package 2nd Line: Assembly Plant Code (X) + Assembled Year Code (X) + Week Code (XX) + Fintek Internal Code (XX) + IC Version (X) where A means version A, B means version B, … 3rd Line: Wafer Fab Code (XXXX…XX) ● : Pin 1 Identifier 10 Jan, 2012 V0.11P F81485 8 Package Spec. 8-SOP Package 11 Jan, 2012 V0.11P F81485 9 Application Circuit 5V HOSTTX/RX F81485 C RS-485 Interface 1.0uF 8 Vcc 2 7 B DE 3 6 A DI 4 5 GND RX_DATA RO 1 Receive_EN RE Drive_EN TX_DATA R D MODE SELECTION /RE DE MODE 0 0 RS485 Recieve 1 1 RS485 Drive 0 1 RS485 LoopBack 1 0 Dis_RS485 Title Size B Date: 12 Document Number F81485 Friday , Nov ember 18, 2011 Rev A Sheet 1 of 1 Jan, 2012 V0.11P