www.fairchildsemi.com FAN5009 Dual Bootstrapped 12V MOSFET Driver Features General Description • Drives N-channel High-Side and Low-Side MOSFETs in a synchronous buck configuration • 12V High-Side and 12V Low-Side Drive • Internal Adaptive “Shoot-Through” Protection • Integrated Bootstrap Diode for High-Side Drive • Fast rise and fall times • Switching Frequency Up to 500kHz • OD input for Output Disable – allows for synchronization with PWM controller • SOIC-8 Package • Available in low thermal resistance MLP package The FAN5009 is a dual, high frequency MOSFET driver, specifically designed to drive N-Channel power MOSFETs in a synchronous-rectified buck converter. These drivers, combined with a Fairchild Multi-Phase PWM controller and power MOSFETs, form a complete core voltage regulator solution for advanced microprocessors. Applications • Multi-phase VRM/VRD regulators for Microprocessor Power • High Current/High Frequency DC/DC Converters • High Power Modular Supplies The FAN5009 drives the upper and lower MOSFET gates of a synchronous buck regulator to 12VGS. The upper gate drive includes an integrated boot diode and requires only an external bootstrap capacitor (CBOOT). The output drivers in the FAN5009 have the capacity to efficiently switch power MOSFETs at frequencies up to 500kHz. The circuit’s adaptive shoot-through protection prevents the MOSFETs from conducting simultaneously. The FAN5009 is rated for operation from 0°C to +85°C and is available in low-cost SOIC-8 or MLP packages. Typical Application 12V FAN5009 4 1 C VCC VCC BOOT Q1 C BOOT PWM OD 2 3 8 OVERLAP PROTECTION CIRCUIT 7 HDRV L1 SW VOUT Q2 C OUT VCC 5 6 LDRV PGND Figure 1. Typical Application. REV. 1.0.5 7/22/04 FAN5009 PRODUCT SPECIFICATION Pin Configuration Paddle (Ground) BOOT 1 PWM 2 OD 3 VCC 4 FAN5009 8 HDRV BOOT 1 7 SW PWM 2 6 PGND OD 3 5 LDRV VCC 4 FAN5009M 8-pin SO-8 package FAN5009 8 HDRV 7 SW 6 PGND 5 LDRV FAN5009MP 8-pin MLP package (Paddle should be connected to ground or left floating) Pin Definitions Pin # Pin Name Pin Function Description 1 BOOT Bootstrap Supply Input. Provides voltage supply to high-side MOSFET driver. Connect to bootstrap capacitor. See Applications Section. 2 PWM 3 OD 4 VCC Power Input. +12V chip bias power. Bypass with a 1µF ceramic capacitor. 5 LDRV Low Side Gate Drive Output. Connect to the gate of low-side power MOSFET(s). 6 PGND Power ground. Connect directly to source of low-side MOSFET(s). 7 SW Switch Node Input. Connect as shown in Figure 1. SW provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection. 8 HDRV High Side Gate Drive Output – Connect to the gate of high-side power MOSFET(s). PWM Signal Input. This pin accepts a logic-level PWM signal from the controller. Output Disable. When low, this pin disables FET switching (HDRV and LDRV are held low). Functional Block Diagram 4 OD PWM 2 1 3 8 VCC BOOT HDRV + 2.2 1.2 7 SW 1.2 VCC 5 6 2 LDRV PGND REV. 1.0.5 7/22/04 PRODUCT SPECIFICATION FAN5009 Absolute Maximum Ratings Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually, not in combination. Unless otherwise specified, voltages are referenced to PGND. Parameter Min. Max. Units VCC to PGND –0.3 15 V PWM and OD pins –0.3 5.5 V –1 15 V –5(1) 25 V –0.3 15 V –0.3 30 V 33(1) V VSW–1 VBOOT+0.3 V –0.5 VCC+0.3 SW to PGND Continuous Transient ( t=100nsec, F≤500kHz) BOOT to SW BOOT to PGND Continuous Transient ( t=100nsec, F≤500kHz) HDRV LDRV Continuous (1) Transient ( t=200nsec) V V –2 Notes: 1. For transient derating beyond the levels indicated, refer to the graphs on page 7. Thermal Information Parameter Min. Max. Units 0 150 °C –65 150 °C Lead Soldering Temperature, 10 seconds 300 °C Vapor Phase, 60 seconds 215 °C Infrared, 15 seconds 220 °C Power Dissipation (PD) TA = 25°C 715 mW Junction Temperature (TJ) Storage Temperature Typ. Thermal Resistance, SO8 – Junction to Case θJC 40 °C/W Thermal Resistance, SO8 – Junction to Ambient θJA 140 °C/W 4 °C/W Thermal Resistance, MLP – Junction to Paddle θJC Recommended Operating Conditions Parameter Supply Voltage VCC Conditions Min. Typ. Max. VCC to PGND 10 12 Units 13.5 V Ambient Temperature (TA) 0 85 °C Junction Temperature (TJ) 0 125 °C REV. 1.0.5 7/22/04 3 FAN5009 PRODUCT SPECIFICATION Electrical Specifications VCC = 12V, and TA = 25°C using circuit in Figure 2 unless otherwise noted. The • denotes specifications which apply over the full operating temperature range. Parameter Symbol Conditions Min. Typ. Max. Units 12 13.5 V 3.5 8 mA 25 mA Input Supply VCC Voltage Range VCC VCC Current ICC • OD = 0V 6.4 • Bootstrap Diode Continuous Forward Current IF(AVG) • Reverse Breakdown Voltage VR • Reverse Recovery Time2 Forward Voltage2 15 tRR V 10 VF IF = 10mA 0.8 ns 0.95 V OD Input Input High Voltage VIH (OD) • Input Low Voltage VIL (OD) • Input Current IOD OD = 3.0V Propagation Delay2 tpdl(OD) See Figure 3 • 2.5 V –300 tpdh(OD) 0.8 V +300 nA 30 40 ns 30 45 ns PWM Input Input High Voltage VIH(PWM) • Input Low Voltage VIL(PWM) • Input Current IIL(PWM) • 3.5 V -1 0.8 V +1 µA High-Side Driver Output Resistance, Sourcing Current RHUP VBOOT–VSW = 12V 3.8 4.4 Ω Output Resistance, Sinking Current RHDN VBOOT–VSW = 12V 1.4 1.8 Ω Transition Times2,4 tR(HDRV) See Figure 2 40 55 ns 20 30 ns 50 65 ns 25 40 ns tF(HDRV) Propagation Delay2,3 tpdh(HDRV) See Figure 2, and 4 tpdl(HDRV) 12V FAN5009 10K 33K 1 BOOT 2 PWM HDRV 8 3000pf SW 7 3 OD PGND 6 4 VCC LDRV 5 3000pf 1µf Figure 2. Test Circuit 4 REV. 1.0.5 7/22/04 PRODUCT SPECIFICATION FAN5009 Electrical Specifications (continued) Parameter Symbol Conditions Min. Typ. Max. Units Low-Side Driver Output Resistance, Sourcing Current RLUP 3.4 4.0 Ω Output Resistance, Sinking Current RLDN 1.4 1.8 Ω Transition Times2,4 tR(LDRV) 40 50 ns 20 30 ns Propagation Delay2,3 tpdh(LDRV) 20 30 ns 25 40 ns See Figure 2 tF(LDRV) See Figures 2, 4 tpdl(LDRV) tpdh(ODRV) See Adaptive Gate Drive Circuit description 240 ns NOTES: 1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control 2. AC Specifications guaranteed by design/characterization (not production tested). 3. For propagation delays, “tpdh” refers to low-to-high signal transition and “tpdl” refers to high-to-low signal transition 4. Transition times are defined for 10% and 90% of DC values VIH(OD) OD VIL(OD) t pdl(OD) t pdh(OD) LDRV / HDRV Figure 3. Output Disable Timing VIH(PWM) PWM VIL(PWM) t pdl (LDRV) LDRV 1.2V t pdh(HDRV) t pdl (HDRV) HDRV-SW t pdh(LDRV) SW 2.2V Figure 4. Adaptive Gate Drive Timing REV. 1.0.5 7/22/04 5 FAN5009 PRODUCT SPECIFICATION Typical Characteristics Gate Drive Rise and Fall Times PWM PWM HDRV HDRV LDRV LDRV HDRV Rise/Fall Times vs. CLOAD 70 60 60 50 TRISE Time (nsec) Time (nsec) LDRV Rise/Fall Times vs. CLOAD 70 40 30 20 50 TRISE 40 30 TFALL 20 TFALL 10 10 0 1,000 2,000 3,000 4,000 0 1,000 5,000 2,000 3,000 CLOAD (pF) 1.5 1.4 1.4 Z (normalized) Z (normalized) LDRV Impedance vs. Temperature (normalized) 1.5 1.3 Source Sink 1.1 1.3 1.2 Source Sink 1.1 1.0 1.0 0.9 0.9 0.8 0.8 0 25 50 75 Temperature (°C) 6 5,000 CLOAD (pF) HDRV Impedance vs. Temperature (normalized) 1.2 4,000 100 125 0 25 50 75 100 125 Temperature (°C) REV. 1.0.5 7/22/04 PRODUCT SPECIFICATION FAN5009 Typical Characteristics (continued) Boot Diode VF vs. IF ICC vs. Frequency 1,600 20 1,400 16 VF (mV) ICC (mA) 1,200 12 1,000 8 800 4 25°C 85°C 125°C 600 400 0 0 100 200 300 400 1 500 10 -13 10 -12 9 -11 8 -10 7 Peak I F (A) VSW (V) 1000 Boot Diode Peak IF Negative SW Voltage Transient -9 -8 -7 -6 6 5 4 3 -5 2 -4 1 0 -3 0 100 200 300 400 500 50 75 100 Transient Duration (nsec) 125 150 175 200 ton at 500KHz (nsec) Negative LDRV Voltage Transient Boot Voltage Transient -6.0 36 -5.0 35 VBOOT–GND (V) VLDRV (V) 100 IF (mA) Frequency (KHz) -4.0 -3.0 ~1.2µJ per cycle -2.0 -1.0 34 33 32 31 0.0 30 0 100 200 300 Transient Duration (nsec) REV. 1.0.5 7/22/04 400 500 0 100 200 300 400 500 Transient Duration (nsec) 7 FAN5009 Circuit Description The FAN5009 is a dual MOSFET driver optimized for driving N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3nF load at speeds up to 500kHz. For a more detailed description of the FAN5009 and its features, refer to the Internal Block Diagram and Figure 1. Low-Side Driver The low-side driver (LDRV) is designed to drive a groundreferenced low RDS(on) N-channel MOSFETs. The bias for LDRV is internally connected between VCC and PGND. When the driver is enabled, the driver’s output is 180° out of phase with the PWM input. When the FAN5009 is disabled (OD = 0V), LDRV is held low. High-Side Driver The high-side driver (HDRV) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the internal diode and external bootstrap capacitor (CBOOT) . During start-up, SW is held at PGND, allowing CBOOT to charge to VCC through the internal diode. When the PWM input goes high, HDRV will begin to charge the high-side MOSFET’s gate (Q1). During this transition, charge is removed from CBOOT and delivered to Q1’s gate. As Q1 turns on, SW rises to VIN, forcing the BOOT pin to VIN +VC(BOOT), which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling HDRV to SW. CBOOT is then recharged to VCC when SW falls to PGND. HDRV output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low. Adaptive Gate Drive Circuit The FAN5009 embodies an advanced design that ensures minimum MOSFET dead-time while eliminating potential shoot-through (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive, adaptively, to ensure they do not conduct simultaneously. Refer to Figure 4 for the relevant timing waveforms. To prevent overlap during the low-to-high switching transition (Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage at the LDRV pin. When the PWM signal goes HIGH, Q2 will begin to turn OFF after some propagation delay (tpdl(LDRV)). 8 PRODUCT SPECIFICATION Once the LDRV pin is discharged below ~1.2V, Q1 begins to turn ON after adaptive delay tpdh(HDRV). To preclude overlap during the high-to-low transition (Q1 OFF to Q2 ON), the adaptive circuitry monitors the voltage at the SW pin. When the PWM signal goes LOW, Q1 will begin to turn OFF after some propagation delay (tpdl(HDRV)). Once the SW pin falls below ~2.2V, Q2 begins to turn ON after adaptive delay tpdh(LDRV). Additionally, VGS of Q1 is monitored. When VGS(Q1) is discharged below ~1.2V, a secondary adaptive delay is initiated, which results in Q2 being driven ON after tpdh(ODRV), regardless of SW state. This function is implemented to ensure CBOOT is recharged each switching cycle, particularly for cases where the power convertor is sinking current and SW voltage does not fall below the 2.2V adaptive threshold. Secondary delay tpdh(ODRV) is longer than tpdh(LDRV). Application Information Supply Capacitor Selection For the supply input (VCC) of the FAN5009, a local ceramic bypass capacitor is recommended to reduce the noise and to supply the peak current. Use at least a 1µF, X7R or X5R capacitor. Keep this capacitor close to the FAN5009 VCC and PGND pins. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBOOT) and the internal diode, as shown in Figure 1. Selection of these components should be done after the high-side MOSFET has been chosen. The required capacitance is determined using the following equation: QG C BOOT = ---------------------∆V BOOT (1) where QG is the total gate charge of the high-side MOSFET, and ∆VBOOT is the voltage droop allowed on the high-side MOSFET drive. For example, the QG of the FDD6696 is about 35nC @ 12VGS. For an allowed droop of ~300mV, the required bootstrap capacitance is 100nF. A good quality ceramic capacitor must be used. The average diode forward current, IF(AVG), can be estimated by: I F ( AVG ) = Q GATE × F SW (2) where FSW is the switching frequency of the controller. The peak surge current rating of the internal diode should be checked in-circuit, since this is dependent on the equivalent impedance of the entire bootstrap circuit, including the PCB traces. For applications requiring higher IF, an external diode may be used in parallel to the internal diode. REV. 1.0.5 7/22/04 PRODUCT SPECIFICATION FAN5009 Thermal Considerations Total device dissipation: (3) P D = P Q + P R + P HDRV + P LDRV where PQ represents quiescent power dissipation: P Q = V CC × [ 4mA + 0.036 ( F SW – 100 ) ] RG is the polysilicon gate resistance, internal to the FET. RE is the external gate drive resistor implemented in many designs. Note that the introduction of RE can reduce driver power dissipation, but excess RE may cause errors in the “adaptive gate drive” circuitry. For more information please refer to Fairchild app note AN-6003, “Shoot-through” in Synchronous Buck Converters. (4) PLDRV is dissipation of the lower FET driver. where FSW is switching frequency (in kHz). (11) P LDRV = P L ( R ) + P L ( F ) PR is power dissipated in the bootstrap rectifier: P R = V F × F SW × Q G1 (5) Where PH(R) and PH(F) are internal dissipations for the rising and falling edges, respectively: Where QG1 is total gate charge of the upper FET (Q1) for it’s applied VGS. VF for the applied IF(AVG) can be graphically determined using the datasheet curves, where: I F ( AVG ) = F SW × Q G1 (6) (13) (14) Layout Considerations Use the following general guidelines when designing printed circuit boards (see Figures 6 and 7): Where PH(R) and PH(F) are internal dissipations for the rising and falling edges, respectively: R HUP P H ( R ) = P Q1 × ---------------------------------------R HUP + R E + R G (8) R HDN P H ( F ) = P Q1 × ----------------------------------------R HDN + R E + R G (9) 1. Trace out the high-current paths and use short, wide (>25 mil) traces to make these connections. 2. Connect the PGND pin of the FAN5009 as close as possible to the source of the lower MOSFET. 3. The VCC bypass capacitor should be located as close as possible to VCC and PGND pins. 4. Use vias to other layers when possible to maximize thermal conduction away from the IC. where: (10) As described in eq. 8 and 9 above, the total power consumed in driving the gate is divided in proportion to the resistances in series with the MOSFET's internal gate node as shown below: BOOT R LDN P L ( F ) = P Q2 × ----------------------------------------R HDN + R E + R G 1 P Q2 = --- × Q G2 × V GS ( Q2 ) × F SW 2 (7) 1 P Q1 = --- × Q G1 × V GS ( Q1 ) × F SW 2 (12) where: PHDRV represents internal power dissipation of the upper FET driver. P HDRV = P H ( R ) + P H ( F ) R LUP P L ( R ) = P Q2 × ---------------------------------------R LUP + R E + R G CBOOT 1 8 2 7 3 6 4 5 Q1 R HUP HDRV R HDN RE RG G S SW Figure 5. Driver dissipation model REV. 1.0.5 7/22/04 CVCC Figure 6. External component placement recommendation for SO8 package (not to scale) 9 FAN5009 5. PRODUCT SPECIFICATION The paddle on the MLP package is internally referenced to ground. It can be left floating or connected to ground. For best thermal performance it should be connected to ground as shown in Figure 7. CBOOT 1 8 2 7 3 6 4 5 PADDLE CVCC VIAS GROUND Figure 7. Recommended layout for MLP package. Also accepts SO8 package (not to scale) 6. The recommended land pattern shown in the MLP mechanical dimensions will work with both MLP-8 and SO-8 packages. The circuit in Figure 1 illustrates a typical implementation of a single phase of a multi-phase buck converter for VCORE applications. For a complete VR10 design example, please refer to the FAN5019 or FAN5018 datasheets. 10 REV. 1.0.5 7/22/04 PRODUCT SPECIFICATION FAN5009 Mechanical Dimensions 0.150, 8 Lead SOIC Package Inches Symbol Min. A A1 B C D E e H h L N α ccc Millimeters Max. Min. Max. .053 .069 .004 .010 .013 .020 .0075 .010 .189 .197 .150 .158 .050 BSC 1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC .228 .010 .016 5.79 0.25 0.40 .244 .020 .050 8 6.20 0.50 1.27 8 0° 8° 0° 8° — .004 — 0.10 8 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals. 3 6 5 E 1 H 4 h x 45° D C A1 A SEATING PLANE e B REV. 1.0.5 7/22/04 –C– LEAD COPLANARITY α L ccc C 11 FAN5009 PRODUCT SPECIFICATION Mechanical Dimensions 5mm x 6mm, 8 Lead MLP Package 5.0 A 4.50 B 6.25 3.50 6.0 4.25 0.25 (1.00) C 2X 0.25 TOP VIEW C 0.65 TYP 1.27 TYP 2X LAND PATTERN RECOMMENDATION 0.10 C (0.25) 1.0 MAX 0.08 C SIDE VIEW 0.05 0.00 C SEATING PLANE 4.25 A 1.75 1 2 3 4 0.75 A 0.35 PIN #1 IDENT. (OPTIONAL) 3.25 A 1.25 8 7 6 1.27 5 NOTES: A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-229, DATED 11/2001. B) DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONING AND TOLERANCES PER ASME Y14.5–1994. 0.28–0.40 A 0.10 M C A B 3.81 A 0.05 M C BOTTOM VIEW 12 REV. 1.0.5 7/22/04 FAN5009 PRODUCT SPECIFICATION Ordering Information Part Number Temperature Range Package Packing FAN5009M 0°C to 85°C SOIC-8 Rails FAN5009MX 0°C to 85°C SOIC-8 Tape and Reel FAN5009MPX 0°C to 85°C MLP-8 Tape and Reel DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 7/22/04 0.0m 001 Stock#DS505009 2004 Fairchild Semiconductor Corporation