FAN5033 8-Bit Programmable, 2- to 3-Phase, Synchronous Buck Controller Features Description Selectable 2- or 3-phase operation at up to 1MHz per phase ±7.7mV worst-case differential sensing error over temperature Active current balancing between the output phases 0.5V to 1.6V output The FAN5033 device is a multi-phase buck switching regulator controller optimized to convert a 12V input supply to the processor core voltage required by high ® performance Intel processors. It has an internal 8-bit DAC that converts a digital voltage identification (VID) code, sent from the processor, to set the output voltage between 0.5V and 1.6V in 6.25mV steps. It outputs PWM signals to external MOSFET drivers that drive the switching power MOSFETs. The switching frequency of the design is programmable by a single resistor value. The number of phases can be programmed to support two- or three-phase applications. Power Good and Crowbar blanking supports on-the-fly VID code changes Fully compliant with the Intel® VR10 and VR11 specifications Selectable VR10 extended (7-bit) and VR11 (8-bit) VID tables Programmable soft-start ramp Programmable short-circuit protection and latch-off delay The FAN5033 also includes programmable no-load offset and droop functions to adjust the output voltage as a function of the load current, as required by the Intel specifications. The FAN5033 provides an accurate and reliable short-circuit protection function with an adjustable over-current set point. The FAN5033 is specified over the commercial temperature range of 0°C to +85°C and is available in a 32-lead MLP package. Applications Desktop PC/Server processor power supplies for existing and next-generation Intel processors VRM modules Ordering Information Part Number Temperature Range Pb-Free Package Type Packing Method Quantity FAN5033MPX 0°C to 85°C Yes MLP-32 Tape and Reel 3,000 per Reel ® Intel is a registered trademark of Intel Corporation. © 2007 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller January 2007 VCC RT RAM PADJ FAN5033 UVLO SHUTDOWN & BIAS OD OSCILL ATOR GND SET EN + CMP – Threshold + – CMP – CURREN T BALANCING CIRCUI T + EN DAC+OV P + CMP – CSREF – PWM1 RESE T PWM2 RESE T PWM3 + 2 / 3 - PHASE DRIVER LOGIC + DAC - UV P – DEL AY PWRGD RESE T CROWBAR CURREN T LIMIT SW1 SW2 SW3 NC CSCOM P ILIMI T CURREN T LIMIT CIRCUI T DEL AY + CSREF – CSSUM Z + – COM P – + PRECISION REFERENCE – FB FBRTN START-UP CONTRO L Boot Control + DAC BUFF VID DAC VIDSE L SS VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Figure 1: Block Diagram © 2007 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 2 of 39 FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Block Diagram Figure 2: Pin Assignment Pin Definitions Pin # Name Description 1 EN Power Supply Enable Input. Analog comparator input with hysteresis. If input voltage is higher than the internal threshold, the controller is enabled. If lower, the controller is disabled. 2 PWRGD Power Good Output. Open drain output that pulls to GND when the output voltage is outside the proper operating range. 3 FBRTN Feedback Return. VID DAC and Error Amplifier reference for remote sensing of output voltage. 4 FB 5 COMP 6 SS 7 DELAY Delay Timer Input. An external capacitor connected between this pin and GND sets the over-current latch-off delay time, BOOT voltage hold time, EN delay time, and PWRGD delay time. 8 ILIMIT Current Limit Set. An external resistor from this pin to GND sets the current limit threshold of the converter. 9 RT 10 RAMPADJ 11 CSREF Current Sense Amplifier Positive Input. The voltage on this pin is used as the reference for the current sense amplifier. The Power Good and Crowbar functions are also internally connected to this pin. 12 CSSUM Current Sense Amplifier Negative Input. 13 CSCOMP © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 Feedback Input. Error amplifier input for remote sensing of output voltage. A positive internal current source is connected to this pin to allow the output voltage to be offset lower than the DAC voltage. Error Amplifier Output. For loop compensation. Soft-Start Input. An external capacitor connected between this pin and GND sets the soft-start ramp-up time. Frequency Set Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Set Input. An external resistor connected between this pin and the converter input voltage sets the internal PWM ramp. Current Sense Amplifier Compensation Output. www.fairchildsemi.com 3 of 39 FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Pin Assignment Name Description 14 GND Ground. All internal biasing and logic output signals of the device are referenced to this ground. 15 OD Output Disable. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO threshold to disable the external MOSFET drivers. (Also referred to as OD# in the text of this document.) 16 NC No Connection. This pin is not connected internally. 17 to 19 SW3 to SW1 20 to 22 PWM3 to PWM1 23 VCC 24 to 31 VID7 to VID0 Voltage Identification Code Inputs. These digital inputs are connected to the internal DAC and used to program the output voltage. These pins have 1µA internal pull-down; so if they are left open, the input state is decoded as logic low. 32 VIDSEL VID Table Select Input. A logic low selects the extended VR10 DAC table and a logic high selects the VR11 DAC table. This pin has a 1µA internal pull-down; so if left open, the input state is decoded as logic low. - Exposed Paddle Internally connected to die ground. May be connected to ground or left floating. Connect to ground for lowest package thermal resistance. © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 Switching Node Current Balance Inputs. Sense the switching side of the inductor and used to measure the current level in each phase. The SW pins of unused phases should be left open. PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the FAN5109. Connecting the PWM3 output to VCC disables that phase, allowing the FAN5033 to operate as a two-phase controller. Supply Voltage for the Device. www.fairchildsemi.com 4 of 39 FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Pin # Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Unless otherwise specified, all other voltages are referenced to GND. Symbol VCC TJ TSTG Parameter Min. Typ. Max. Unit Supply Voltage -0.3 +15 V FBRTN -0.3 +0.3 V RAMPADJ, PWM3 -0.3 VCC + 0.3 V SW1 – SW3 -10 +25 V All Other Inputs and Outputs -0.3 +5.5 V 0 +125 °C -65 +150 °C °C Operating Junction Temperature Storage Temperature TL Lead Soldering Temperature (10 seconds) 300 TLI Lead Infrared Temperature (15 seconds) 260 °C 45 °C/W θJA Thermal Resistance Junction-to-Ambient (1) Note: 1. Junction-to-ambient thermal resistance, θJA, is a strong function of PCB material, board thickness, thickness and number of copper planes, number of via used, diameter of via used, available copper surface, and attached heat sink characteristics. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter VCC Supply Voltage, VCC to GND TA Ambient Temperature © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 Min. Typ. Max. Unit 9.6 12 14.4 V +85 °C 0 www.fairchildsemi.com 5 of 39 FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Absolute Maximum Rating VCC = 12V, FBRTN = GND, and TA = +25°C. The • denotes specifications that apply over the full operating temperature range. Symbol Parameter Conditions Min. Typ. Max. Unit Error Amplifier VCOMP Output Voltage Range • 0.5 4.0 V +7.7 mV VFB Accuracy Relative to nominal DAC output, referenced to FBRTN. Figure 3 VRM11 VID Range: 1.00625V to 1.60000V • -7.7 VFB(BOOT) Accuracy Relative to nominal DAC output, referenced to FBRTN. Figure 3 During Start-up • 1.092 1.100 1.108 V Load Line Droop Accuracy CSREF-CSCOMP= 80mV Figure 5 • -78 -80 -82 mV • -1 +1 LSB Differential Non-linearity ΔVFB Line Regulation VCC =10V to 14V 0.05 Input Bias Current • IFBRTN FBRTN Current • IO(ERR) Output Current IFB 13.5 15.0 16.5 µA 70 95 µA 500 µA Gain Bandwidth Product (2) COMP = FB 20 MHz Slew Rate COMP = FB(2) 25 V/µs VCSCOMP CSCOMP Voltage Range Relative to CSREF tBOOT BOOT Voltage Hold Time CDELAY = 10nF GBW(ERR) FB forced to VOUT -3% % • -250 +250 2 mV ms VID Inputs and VIDSEL VIH(VID) Input Low Voltage VIDx, VIDSEL • VIL(VID) Input High Voltage VIDx, VIDSEL • VIH(VID) Select VR10 Table VIDSEL Logic Low IIN(VID) Select VR11 Table VIDSEL Logic High 0.8 0.8 Input Current, VID Low 0.4 V 3.3 V 0.4 V 3.3 -1 V µA VID Transition Delay Time VID code change to FB change(2) • 200 ns No CPU Detection Turn-off Delay Time VID code change to OFF state to PWM going low(2) • 200 ns • 0.25 Oscillator fOSC fPHASE VRT VRAMPADJ IRAMPADJ Frequency Frequency Variation TA = 25C, RT= 200K, 3phase Output Voltage RT =100kΩ to GND RAMPADJ Output Voltage VRAMPADJ = VDAC + 2kΩ * (VCC – VDAC) / (RRAMPADJ + 2KΩ) RAMPADJ Input Current Range © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 4.50 MHz -20% 400 20% kHz • 1.9 2.0 2.1 V • -50 +50 mV 1 50 µA www.fairchildsemi.com 6 of 39 FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Electrical Characteristics VCC = 12V, FBRTN = GND, and TA = +25°C. The • denotes specifications that apply over the full operating temperature range. Symbol Parameter Conditions Min. Typ. Max. Unit Current Sense Amplifier VOS(CSA) IBIAS(CSSUM) Offset Voltage CSSUM – CSREF Figure 4 Input Bias Current (for CSSUM) IBIAS(CSREF) Input Current (for CSREF) Current drawn by CSREF Pin GBW(CSA) Gain Bandwidth Product CSSUM = CSCOMP VCSACM tOC(DELAY) -1.0 +1.0 mV • -50 +50 nA • -3 +3 µA (2) (2) Slew Rate CCSCOMP = 10pF Input Common-Mode Range CSSUM and CSREF Output Voltage Range ICSCOMP • MHz V/µs • 0 3.2 V • 0.05 3.2 V Output Current Current Limit Latch-off Delay Time 10 10 CDELAY = 10nF 1 mA 5 ms Current Balance Circuit VSW(x)CM Common Mode Range(2) • -600 +200 mV RSW(x) Input Resistance SW(x) = 0V • 35 50 65 kΩ ISW(x) Input Current SW(x) = 0V • 1.6 3.3 5.0 µA Input Current Matching SW(x) = 0V • -5 +5 % • 1.6 1.8 V ΔISW(x) Current Limit Comparator VILIMIT Output Voltage RILIMT = 143kΩ IILIMIT Output Current RILIMT = 143kΩ Maximum Output Current VCL Current Limit Threshold Voltage VCSREF − VCSCOMP, RILIMT = 143kΩ Current Limit Setting Ratio VCL / IILIMT 1.7 12 • 60 • 100 µA µA 120 140 10 mV mV/µA Delay Timer Normal Mode Output Current • 12 15 18 µA IDELAY(CL) Output Current in Current Limit • 3.0 3.75 4.5 µA VDELAY(TH) Threshold Voltage • 1.6 1.7 1.8 V • 12 15 18 µA IDELAY Soft-Start I(SS) Output Current During Start-up Enable Input VTH(EN) Threshold Voltage • 800 850 900 mV VHYS(EN) Threshold Hysteresis • 80 100 120 mV IIN(EN) Enable Input Current tDELAY(EN) Turn-on Delay © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 Start-up sequence, EN>950mV, CDELAY = 10nF 1 µA 2 ms www.fairchildsemi.com 7 of 39 FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Electrical Characteristics (Continued) VCC = 12V, FBRTN = GND, and TA = +25°C. The • denotes specifications that apply over the full operating temperature range. Symbol Parameter Conditions Min. Typ. Max. Unit 160 400 mV OD Output VOL(ODB) Output Voltage Low IPWM(SINK) = 400μA • VOH(ODB) Output Voltage High IPWM(SOURCE) = 400μA • 4 5 V Power Good Comparator VPWRGD(UV) Under-Voltage Threshold Relative to Nominal DAC Output • -300 -250 -200 mV VPWRGD(OV) Over-Voltage Threshold Relative to Nominal DAC Output • 100 150 200 mV VOL(PWRGD) Output Low Voltage IPWRGD(SINK) = -4mA • 200 300 mV Start-up sequence • 2 ms VID code Changing • 250 µs VID Code Static • 100 200 ns tPWRGD VCROWBAR tCROWBAR Power Good Delay Time CDELAY = 10nF Power Good Blanking Time Crowbar Trip Point Relative to Nominal DAC Output • 100 150 200 mV Crowbar Reset Point Relative to FBRTN • 250 300 350 mV VID code Change • 100 250 µs VID Code Static • 400 ns 160 Crowbar Delay Time Over-voltage to PWM going low Crowbar Blanking Time PWM Outputs VOL(VRTM) Output Voltage Low IPWM(SINK) = 400μA • VOH(VRTM) Output Voltage High IPWM(SOURCE) = 400μA • Phase Disable Voltage Applicable to PWM3 pins only. Connect this pin to VCC to disable the phase.(3) • VCC -.1 DC Supply Current EN = Logic HIGH • VUVLO UVLO Threshold VCC rising • VULVOLHYS UVLO Hysteresis • 4 400 5 mV V V Input Supply VCC 8 12 mA 6.5 6.9 7.3 V 0.7 0.9 1.1 V Notes: 1. All limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control. 2. AC specifications guaranteed by design and characterization; not production tested. 3. To operate FAN5033 with fewer than three phases, PWM3 should be connected to VCC to disable this phase. See the “Theory of Operation” section for details. © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 8 of 39 FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Electrical Characteristics (Continued) FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Test Diagrams 12 V 1.25 V 20k 100nF VCC VID0 VIDSEL VID1 EN VID2 CSCOMP VID3 CSSUM VID4 CSREF VID5 12 V 1k 250k 10nF 10nF VID7 COMP SW1 ILIMIT SW2 SS SW3 VCC 100nF 8 13 8 Bit Code CSCOMP 39k 12 CSSUM - 1k VID6 FB 23 CSA 11 + V CSREF + 1V - 14 GND DELAY GND FBRTN Figure 3: Closed-Loop Output Voltage Accuracy Figure 4: Current Sense Amplifier VOS Rt as a function of Oscillator Frequency 8 1000 FB Rt (kΩ) 10k 100 13 CSCOMP - 8 20 1 17 0 14 7 12 9 11 5 10 4 94 86 79 72 67 62 58 54 51 48 45 43 40 38 4 3 COMP 24 5 30 41 4 23 VCC 62 12 V V dV + 11 CSREF + V V - 14 GND 10 0 1000 2000 3000 4000 5000 Oscillator Frequency (kHz) Figure 5: Droop Voltage Accuracy © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 Figure 6: RT Required to Set Oscillator Frequency www.fairchildsemi.com 9 of 39 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 VID2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID5 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT (V) OFF OFF OFF OFF 1.09375 1.10000 1.10625 1.11250 1.11875 1.12500 1.13125 1.13750 1.14375 1.15000 1.15625 1.16250 1.16875 1.17500 1.18125 1.18750 1.19375 1.20000 1.20625 1.21250 1.21875 1.22500 1.23125 1.23750 1.24375 1.25000 1.25625 1.26250 1.26875 1.27500 1.28125 1.28750 1.29375 1.30000 1.30625 1.31250 1.31875 1.32500 1.33125 1.33750 1.34375 1.35000 1.35625 1.36250 1.36875 1.37500 1.38125 1.38750 1.39375 1.40000 1.40625 1.41250 1.41875 1.42500 1.43125 1.43750 1.44375 1.45000 1.45625 1.46250 www.fairchildsemi.com 10 of 39 FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Table 1: Output Voltage Programming Codes (extended VR10) ; 0 = logic LOW; 1 = logic HIGH. VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 VID2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID5 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT (V) 1.46875 1.47500 1.48125 1.48750 1.49375 1.50000 1.50625 1.51250 1.51875 1.52500 1.53125 1.53750 1.54375 1.55000 1.55625 1.56250 1.56875 1.57500 1.58125 1.58750 1.59375 1.60000 0.83125 0.83750 0.84375 0.85000 0.85625 0.86250 0.86875 0.87500 0.88125 0.88750 0.89375 0.90000 0.90625 0.91250 0.91875 0.92500 0.93125 0.93750 0.94375 0.95000 0.95625 0.96250 0.96875 0.97500 0.98125 0.98750 0.99375 1.00000 1.00625 1.01250 1.01875 1.02500 1.03125 1.03750 1.04375 1.05000 1.05625 1.06250 1.06875 1.07500 1.08125 1.08750 www.fairchildsemi.com 11 of 39 FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Table 1: Continued HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Voltage OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 Tolerance +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 - © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 HEX 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Voltage 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 Tolerance +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) HEX 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Voltage 0.81250 0.80625 0.8 0.79375 0.7875 0.78125 0.775 0.76875 0.7625 0.75625 0.75 0.74375 0.7375 0.73125 0.725 0.71875 0.7125 0.70625 0.7 0.69375 0.6875 0.68125 0.675 0.66875 0.6625 0.65625 0.65 0.64375 0.6375 0.63125 0.625 0.61875 0.6125 0.60625 0.6 0.59375 0.5875 0.58125 0.575 0.56875 0.5625 0.55625 0.55 0.54375 0.5375 0.53125 0.525 0.51875 0.5125 0.50625 0.5 0.49375 0.4875 0.48125 0.475 0.46875 0.4625 0.45625 0.45 0.44375 0.4375 0.43125 0.425 0.41875 Tolerance Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care HEX C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Voltage 0.4125 0.40625 0.40000 0.39375 0.38750 0.38125 0.37500 0.36875 0.36250 0.35625 0.35000 0.34375 0.33750 0.33125 0.32500 0.31875 0.31250 0.30625 0.30000 0.29375 0.28750 0.28125 0.27500 0.26875 0.26250 0.25625 0.25000 0.24375 0.23750 0.23125 0.22500 0.21875 0.21250 0.20625 0.20000 0.19375 0.18750 0.18125 0.17500 0.16875 0.16250 0.15625 0.15000 0.14375 0.13750 0.13125 0.12500 0.11875 0.11250 0.10625 0.10000 0.09375 0.08750 0.08125 0.07500 0.06875 0.06250 0.05625 0.05000 0.04375 0.03750 0.03125 OFF OFF Tolerance Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care www.fairchildsemi.com 12 of 39 FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Table 2: Output Voltage Programming Codes (8-bit) 0 = logic LOW; 1 = logic HIGH. (MSB: VID7, LSB: VID0; 11110001b = F1h) (Contact your Fairchild representative for the latest VR11 reference designs) R5 10 10 0 R8 0 R7 R2A Optional R4 Optional 0 R3 R6 0 R2 J1 Optional R1 R1A Optional AGND VT R11 0 FBRTN VR C20 4.7uF VIN VTTA R15 3K VCORE 30.1K 470pF 1.21K 33pF J2 R21 680 GND 1 P4 VCORE 1 P3 C24 18nF COMP 1 2 3 4 5 6 7 8 9 10 C23 0.1uF ENABLE DIP20 S1 R19 C21 C22 VR_READY 20 19 18 17 16 15 14 13 12 11 0 R20 R12 Optional R13 D7 GREEN Optional C19 D5 MMSD4148 SOD-123 Q1 BCW33 R10 2.2 Optional R20A NOTES : 1. Optional parts are not populated unless otherwise specified ; GND VR_VCCee VCORE VR_VCCdie VR_VCCse VR_VSSse VR_VSSdie VR_VSSee D1 MMSZ4678 R9 10K VIN VTT SS 1K R22 C25 0.1uF C26 18nF 1 1 1 1 +12V DELAY GND P2 +12V P1 ILIMIT 1 1 1 1 R38 110K 1nF C27 ENABLE VIDSEL VID0 VID1VID2VID3VID4VID5VID6VID7 R23 R24 R25 R27 R28 R30 R32 R34 R35 680 680 680 680 680 680 680 680 680 VCC 8 7 6 5 4 3 2 1 ILIMIT DELAY SS COMP FB FBRTN PWRGD EN 32 VIDSEL RT C29 R39 267K 9 30 31 VID0 RAMPADJ R40 332K 6.8nF 10 VID1 CSREF 11 29 28 U1 VID2 CSSUM CSCOMP 12 27 C33 3900pF SW3 SW2 SW1 PWM3 PWM2 PWM1 VCC VID7 C28 Optional VID3 CSCOMP 13 25 VID6 NC 26 VID4 GND 14 VID5 OD 15 13 of 39 16 © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com CSREF 0 R43 C35 3300pF OD Optional 0 0 R45 68.1K R53 R55 102K R57 102K PWM3 Optional PWM2 R59 Optional C37 1uF 10 R56 R52 R50 102K CSREFA 100K THERMISTOR 5% RT2 39.2K R46 OD 10 R49 17 R44 10 R48 18 R31 10 R47 PWM1 VCC 19 20 21 22 23 24 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VIDSEL VIN SW3 SW2 SW1 PWM3 PWM2 PWM1 FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Figure 7A: Typical FAN5033 Three-Phase Design, Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 14 of 39 PWM3 OD C1 4.7uF VIN PWM1 OD C2 4.7uF 2 3 6 4 U2 LDRV FAN5109 PWM SW HDRV BOOT U4 5 1 7 8 MMSD4148 SOD123 LDRV FAN5109 PWM D2 BOOT SW HDRV 5 1 7 8 MMSD4148 SOD123 OD PGND VCC D3 OD PGND VCC 2 3 6 4 9 R73 10K 0.1uF C3 R16 2.2 R17 2.2 SW3 R71 10K 0.1uF C4 SW1 R72 10K C5 1000pf R26 2.2 Q4B FDD8780 R29 2.2 Q5B FDD8780 Q7 FDD8796 Q6 FDD8796 Q4 FDD8780 Q3 FDD8796 SW1 Q2 FDD8796 SW3 R70 10K Q5 FDD8780 + + + C66 560uF + CSREFA + C68 560uF VCORE C11 0.1uF C67 560uF CSREFA VCORE C10 22uF/16V C9 22uF/16V C65 560uF TP_L3 C64 560uF R33 10 0.6uH/ 27A L3 + C7 22uF/16V C6 1000pf R36 10 0. 6uF/ 27A L1 TP_L1 C8 22uF/16V OD + C70 560uF 1 2 3 4 5 1 7 GND +12V LDRV FAN5109 PWM 8 7 6 5 BOOT OD SW 8 MMSD4148 SOD123 HDRV U3 PGND VCC COM +12V COM +12V COM +12V COM +12V MOLEX_8B J3 2 3 6 4 D4 + C71 Optional 0.1uF C14 R75 10K R74 10K L4 Jumpe r R54 2.2 SW2 C72 1200uF/16V + + + R63 2.2 C74 1200uF/16V Q10 FDD8796 Q9B FDD8780 C73 1200uF/ 16V Q8 FDD8796 SW2 Q9 FDD8780 C15 1000pf C16 22uF/16V L2 C75 560uF VIN + + TP_L2 R67 10 300nH/30A C17 22uF/16V C76 560uF + CSREFA VCORE C18 0.1uF C77 560uF Outside Socket Optional C87 C88 C89 C90 C91 C93 C94 C95 C96 C97 C98 C99 10uF/6.3V 10uF/6.3V 10uF/6. 3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6. 3V Bottom Side Socket Optiona l Inside Socket C38 C57 C56 C54 C53 C52 C51 C50 C49 C48 C47 C46 C81 C82 C83 C84 C85 C86 10uF/6.3V 10uF/6.3V 10uF/6. 3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6. 3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/ 6.3V 10uF/ 6.3V 10uF/6.3V C30 C31 C32 C34 C36 C39 C40 C41 C42 C43 C44 C45 C58 C59 C60 C61 C62 C63 10uF/6.3V 10uF/6.3V 10uF/6. 3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6. 3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/ 6.3V 10uF/ 6.3V 10uF/6.3V C13 4.7uF C69 PWM2 560uF C12 0.1uF VIN FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller VIN 9 9 Figure 7B: Typical FAN5033 Three-Phase Design, Drivers (Contact your Fairchild representative for the latest VR11 reference designs) www.fairchildsemi.com Note: The values shown in this section are for reference only. See the parametric tables for actual values. The FAN5033 is a fixed-frequency PWM controller with multi-phase logic outputs for use in two- and threephase synchronous buck CPU power supplies. It has an internal VID DAC designed to interface directly with Intel’s 8-bit VRD/VRM 11 and 7-bit VRD/VRM 10.xcompatible CPUs. Multi-phase operation is required for the high currents and low voltages of today’s Intel’s microprocessors that can require up to 150A of current. The integrated features of the FAN5033 ensure a stable, high-performance topology for: Balanced currents and thermals between phases High-speed response at the lowest possible switching frequency and output decoupling capacitors Shorting PWM3 to VCC configures the system for twophase operation. 12V Vin Vtt UVLO Threshold 0.85V DELAY Threshold DELAY 1.0V Vboot =1.1V SS Vcore = VID Tight load line regulation and accuracy Vcore = Vboot Vcc (Core) High-current output by allowing up to three-phase designs Reduced output ripple due to multi-phase operation Two- to three-phase operation allows optimizing designs for cost/performance and support a wide range of applications TD1 Easily settable and adjustable design parameters with simple component selection START-UP SEQUENCE The FAN5033 start-up sequence is shown in Figure 8. Once the EN and UVLO conditions are met, the DELAY pin goes through one cycle (TD1); after which, the internal oscillator starts. The first two clock cycles are used for phase detection. The soft-start ramp is enabled (TD2), raising the output voltage up to the boot voltage of 1.1V. The boot hold time (TD3) allows the processor VID pins settle to the programmed VID code. After TD3 timing is finished, the output soft-starts, either up or down, to the final VID voltage during TD4. TD5 is the time between the output reaching the VID voltage and the PWRGD being presented to the system. PHASE-DETECTION SEQUENCE During start-up, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the FAN5033 operates as a three-phase PWM controller. For two-phase operation, connect the PWM3 pin to VCC. The PWM logic, which is driven by the master oscillator, directs the phase sequencer and channel detectors. Channel detection occurs during the first two clock cycles after the chip is enabled. During the detection TD2 TD3 TD4 TD5 VRready 50uS VIDs Good PC board layout noise immunity © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 period, PWM3 is connected to a 100µA sinking current source and two internal voltage comparators check the pin voltage of PWM3 versus a threshold of 3V typical. If the pin is tied to VIN, the pin voltage is above 3V and that phase is disabled and put in a tri-state mode. Otherwise, the internal 100µA current source pulls PWM pin below the 3V threshold. After channel detection, the 100µA current source is removed. Invalid Valid Figure 8: Start-Up Sequence Timing After detection time is complete, the PWM outputs that were not sensed as “pulled high” function as normal PWM outputs. PWM outputs that were sensed as “pulled high” are put into a high-impedance state. The PWM signals are logic-level outputs intended for driving external gate drivers, such as the FAN5109. Since each phase is monitored independently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at the same time to allow overlapping phases. MASTER CLOCK FREQUENCY The clock frequency of the FAN5033 is set with an external resistor connected from the RT pin to ground. The frequency to resistor relationship is shown in Figure 6. To determine the frequency per phase, divide the clock by the number of enabled phases. OUTPUT CURRENT SENSING (See Figure 2) The FAN5033 provides a dedicated current sense amplifier (CSA) to monitor the output current for proper voltage positioning and for current limit detection. It differentially senses the voltage drop across the DCR of the inductors to give the total average current being delivered to the load. This method is inherently more accurate than peak current detection or sampling the voltage across the low-side MOSFETs. The CSA implementation can be configured several ways, depending on the objectives of the system. It can use output inductor DCR sensing without a thermistor, for www.fairchildsemi.com 15 of 39 FAN5033 — 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Theory of Operation To measure the differential voltage across the output inductors, the positive input of the CSA (CSREF pin) is connected, using equal value resistors, to the output capacitor side of the inductors. The negative input of the CSA (CSSUM pin) is connected, again using equal value resistors, to the MOSFET side of the inductors. The CSA’s output (CSCOMP) is a voltage equal to the voltage dropped across the inductors, times the gain of the CSA, and is inversely proportional to the output current. The gain of the CSA is set by connecting an external feedback resistor between the CSA’s CSCOMP and CSSUM pins. A capacitor, connected across the resistor, is used to create a low pass filter to remove high-frequency switching effects and to create a RC pole to cancel the zero created by the L/DCR of the inductor. The end result is that the voltage between the CSCOMP and CSREF pins is inversely proportional to the output current (CSCOMP goes negative relative to CSREF as current increases) and the CSA gain sets the ratio of the CSA output voltage change as a function of output current change. This voltage difference is used by the current limit comparator and is also used by the droop amplifier to create the output load line. The CSA is designed to have a low offset input voltage. The sensing gain is determined by external resistors so that it can be extremely accurate. LOAD LINE IMPEDANCE CONTROL The FAN5033 has an internal “Droop Amp” that effectively subtracts the voltage applied between the CSCOMP and CSREF pins from the FB pin voltage of the error amplifier, allowing the output voltage to be varied independent of the DAC setting. A positive voltage on CSCOMP (relative to CSREF) increases the output voltage and a negative voltage decreases it. Since the voltage between the CSA’s CSCOMP and CSREF pins is inversely proportional to the output, current causes the output voltage to decrease an amount directly proportional to the increase in output, current, creating a droop or “Load Line.” The ratio of output voltage decrease to output current increase is the effective Ro of the power supply and is set by the DC gain of the CSA. CURRENT CONTROL MODE AND THERMAL BALANCE The FAN5033 has individual SW inputs for each phase. They are used to measure the voltage drop across the bottom FETs to determine the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system. This gives good current balance accuracy that takes into account, not only the current, but also the thermal balance between the bottom FETs in each phase. External resistors RSW1 through RSW3 can be placed in series with individual SW inputs to create an intentional current imbalance if desired, such as in cases where one phase has better cooling and can support higher © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 currents. It is best to have the ability to add these resistors in the initial design to ensure that placeholders are provided in the layout. To increase the current in a phase, increase RSW for that phase. Even adding a resistor of a few hundred ohms can make a noticeable increase in current, so use small steps. The amplitude of the internal ramp is set by a resistor connected between the input voltage and the RAMPADJ pin. This method also implements the Voltage Feed Forward function. OUTPUT VOLTAGE DIFFERENTIAL SENSING The FAN5033 uses differential sensing in conjunction with a high accuracy DAC and a low offset error amplifier to maintain a worst-case specification of ±7.7mV differential sensing accuracy over its specified operating range. A high gain-bandwidth error amplifier is used for the voltage control loop. The voltage on the FB pin is compared to the DAC voltage to control the output voltage. The FB voltage is also effectively offset by the CSA output voltage for accurately positioning the output voltage as a function of current. The output of the error amplifier is the COMP pin, which is compared to the internal PWM ramps to create the PWM pulse widths. The negative input (FB) is tied to the output sense location with a resistor (RB) and is used for sensing and controlling the output voltage at this point. Additionally a current source is connected internally to the FB pin, which causes a fixed DC current to flow through RB. This current creates a fixed voltage drop (offset voltage) across RB. The offset voltage adds to the sensed output voltage, which causes the error amp to regulate the actual output voltage lower than the programmed VID voltage by this amount. The main loop compensation is incorporated into the feedback by an external network connected between FB and COMP. DELAY TIMER The delay times for the start-up timing sequence are set with a capacitor from the DELAY pin to ground, as described in the Start-Up Sequence section. In UVLO or when EN is logic low, the DELAY pin is held at ground. Once the UVLO and EN are asserted, a 15µA current flows out of the DELAY pin to charge CDLY. A comparator, with a threshold of 1.7V, monitors the DELAY pin voltage. The delay time is therefore set by the 15µA charging the delay capacitor from 0V to 1.7V. This DELAY pin is used for multiple delay timings (TD1, TD3, and TD5) during start-up. DELAY is also used for timing the current limit latch off as explained in the CURRENT LIMIT section. SOFT-START The soft-start times for the output voltage are set with a capacitor from the SS pin to ground. After TD1 and the phase-detection cycle have been completed, the SS time (TD2 in Figure 8) starts. The SS pin is disconnected from GND and the capacitor is charged up to the 1.1V boot voltage by the SS amplifier, which has a limited output current of 15µA. The voltage at the FB pin follows the ramping voltage on the SS pin, limiting www.fairchildsemi.com 16 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller lowest cost, or output inductor DCR sensing with a thermistor, for improved accuracy with tracking of inductor temperature. Once the SS voltage is within 100mV of the boot voltage, the boot voltage delay time (TD3) is started. The end of the boot voltage delay time signals the beginning of the second soft-start time (TD4). The SS voltage changes from the boot voltage to the programmed VID DAC voltage (either higher or lower) using the SS amplifier with the limited output current of 15µA. The voltage of the FB pin follows the ramping voltage of the SS pin, limiting the inrush current during the transition from the boot voltage to the final DAC voltage. The second soft-start time depends on the boot voltage, the programmed VID DAC voltage, and CSS. If either EN is taken low or VCC drops below UVLO, DELAY and SS are reset to ground to be ready for another soft-start cycle. Figure 9 shows typical start-up waveforms for the FAN5033. starts the latch-off timer. Because the controller continues to operate during the latch-off delay time, if the OC is removed before the 1.7V threshold is reached, the controller returns to normal operation and the DELAY capacitor is reset to GND. The latch-off function can be reset by cycling the supply voltage to the FAN5033 or by toggling the EN pin low for a short time. To disable the short-circuit latch-off function, an external resistor can be placed in parallel with CDLY to prevent the DELAY capacitor from charging up to the 1.7V threshold. The addition of this resistor causes a slight increase in the delay times. During start-up, when the output voltage is below 200mV, a secondary current limit is active. This secondary current limit clamps the internal COMP voltage at the PWM comparators to 1.5V. Typical overcurrent latch-off waveforms are shown in Figure 10. Vcore Vcore VOD# VDELAY VVRREADY VPHASE1 VEN VDELAY Figure 10: Over-Current Latch-off Waveforms Figure 9: Start-up Waveforms CURRENT LIMIT, SHORT-CIRCUIT. AND LATCH-OFF PROTECTION The FAN5033 compares a programmable current limit set point to the voltage from the output of the current sense amplifier. The current limit level is set with the resistor from the ILIMIT pin to ground. During operation, the voltage on ILIMIT is 1.7V. The current through the external resistor is internally scaled to give a current limit threshold of 10mV/µA. If the voltage between CSREF and CSCOMP rises above the current limit threshold, the internal current limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. After TD5 has completed, an over-current (OC) event starts a latch-off delay timer. The delay timer uses the DELAY pin timing capacitor. During current limit, the DELAY pin current is reduced to 3.75 µA. When the voltage on the delay pin reaches 1.7V, the controller shuts down and latches off. The current limit latch-off delay time is therefore set by the current of 3.75µA charging the delay capacitor 1.7V. This delay is four times longer than the delay time during the start-up sequence. If there is a current limit during start-up, the FAN5033 goes through TD1 to TD5 in current limit and © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 DYNAMIC VID The FAN5033 has the ability to dynamically change the VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the FAN5033 detects the change and ignores the DAC inputs for a minimum of 200ns. This time prevents a false code due to logic skew while the eight VID inputs are changing. Additionally, the first VID change initiates the PWRGD and CROWBAR blanking functions for a minimum of 100µs to prevent a false PWRGD or CROWBAR event. Each VID change resets the internal timer. POWER GOOD MONITORING The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified based on the VID voltage setting. PWRGD goes low if the output voltage is www.fairchildsemi.com 17 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller the inrush current during start-up. The soft-start time depends on the value of the boot voltage and CSS. OUTPUT CROWBAR As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 300mV. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output over-voltage is due to a short in the highside MOSFET, this action current-limits the input supply, protecting the microprocessor. OUTPUT ENABLE AND UVLO For the FAN5033 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold and the EN pin must be higher than its 0.85V threshold. This initiates a system start-up sequence. If either UVLO or EN is less than their respective thresholds, the FAN5033 is disabled, which holds the © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 In the application circuit, the OD# pin should be connected to the OD# inputs of the FAN5009 or FAN5109 drivers. Pulling OD# low disables the drivers such that both DRVH and DRVL are driven low. This turns off the bottom MOSFETs to prevent them from discharging the output capacitors through the output inductors. If the bottom MOSFETs were left on, the output capacitors could ring with the output inductors and produce a negative output voltage to the processor. NTC Resistance versus Temperature Normalized to 25C 1.0 0.8 Resistance (25C = 1) The PWRGD circuitry also incorporates an initial turn-on delay time (TD5) based on the DELAY timer. Prior to the SS voltage reaching the programmed VID DAC voltage of -100mV, the PWRGD pin is held low. Once the SS pin is within 100mV of the programmed DAC voltage, the capacitor on the DELAY pin begins to charge up. A comparator monitors the DELAY voltage and enables PWRGD when the voltage reaches 1.7V. The PWRGD delay time is therefore set by a current of 15µA charging a capacitor from 0V to 1.7V. PWM outputs low, discharges the DELAY and SS capacitors, and forces PWRGD and OD# signals low. 0.6 0.4 0.2 0.0 25 50 75 Temperature (C) 100 125 Figure 11: Typical NTC Resistance vs. Temperature www.fairchildsemi.com 18 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller outside of the specified range, if the VID DAC inputs are in no CPU mode, or whenever the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of ~200µs to prevent false signals during the time the output is changing. FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller Application Section © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 19 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 20 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 21 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 22 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 23 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 24 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 25 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 26 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 27 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 28 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 29 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 30 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 31 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 32 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 33 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 34 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 35 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 36 of 39 The following guidelines are recommended for optimal performance of a switching regulator in a PC system. General Recommendations For good results, a PCB with at least four layers is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53mΩ at room temperature. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the FAN5033) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the FAN5033 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing in it. The components around the FAN5033 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB and CSSUM pins. The output capacitors should be connected as close as possible to the load (or connector); for example, a microprocessor core, that receives the power. If the load is distributed, the capacitors should also be distributed and be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop, described in the following section. Power Circuitry Recommendations The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (i.e., EMI) and conduction losses in the board. Failure to take proper precautions results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high-energy ringing, and it accommodates the high-current demand with minimal voltage loss. Whenever a power dissipating component, such as a power MOSFET, is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heatsink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers, extending fully under all the power components. Signal Circuitry Recommendations The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. The FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller. © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 37 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller LAYOUT AND COMPONENT PLACEMENT FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller Mechanical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 12. 32-Lead Molded Leadless Package © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 38 of 39 ACEx™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CROSSVOLT™ DOME™ EcoSPARK™ 2 E CMOS™ EnSigna™ ® FACT FACT Quiet Series™ ® FAST FASTr™ FPS™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ 2 I C™ i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ ® OPTOLOGIC OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerEdge™ PowerSaver™ ® PowerTrench ® QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ ScalarPump™ μSerDes™ ® SILENT SWITCHER SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TCM™ TinyBoost™ TinyBuck™ ® TinyLogic TINYOPTO™ TinyPower™ TinyPWM™ TruTranslation™ ® UHC UniFET™ VCX™ Wire™ Across the board. Around the world.™ Programmable Active Droop™ ® The Power Franchise DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Definition Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I22 © 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 39 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.