Fairchild FAN5093MTC Two phase interleaved synchronous buck converter for vrm 9.x application Datasheet

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FAN5093
Two Phase Interleaved Synchronous Buck Converter
for VRM 9.x Applications
Features
Description
• Programmable output from 1.10V to 1.85V in 25mV steps
using an integrated 5-bit DAC
• Two interleaved synchronous phases for maximum
performance
• 100nsec transient response time
• Built-in current sharing between phases
• Remote sense
• Programmable Active Droop (Voltage Positioning)
• Programmable switching frequency from 100KHz to
1MHz per phase
• Adaptive delay gate switching
• Integrated high-current gate drivers
• Integrated Power Good, OV, UV, Enable/Soft Start
functions
• Drives N-channel MOSFETs
• Operation optimized for 12V operation
• High efficiency mode (E*) at light load
• Overcurrent protection using MOSFET sensing
• 24 pin TSSOP package
The FAN5093 is a synchronous two-phase DC-DC controller
IC which provides a highly accurate, programmable output
voltage for VRM 9.x processors. Two interleaved synchronous buck regulator phases with built-in current sharing
operate 180° out of phase to provide the fast transient
response needed to satisfy high current applications while
minimizing external components.
The FAN5093 features Programmable Active Droop for
transient response with minimum output capacitance. It has
integrated high-current gate drivers, with adaptive delay gate
switching, eliminating the need for external drive devices.
The FAN5093 uses a 5-bit D/A converter to program the
output voltage from 1.10V to 1.85V in 25mV steps with an
accuracy of 1%. The FAN5093 uses a high level of integration to deliver load currents in excess of 50A from a 12V
source with minimal external circuitry.
The FAN5093 also offers integrated functions including
Power Good, Output Enable/Soft Start, under-voltage lockout, over-voltage protection, and adjustable current limiting
with independent current sense on each phase. It is available
in a 24 pin TSSOP package.
Applications
•
•
•
•
Power supply for Pentium IV
Power supply for Athlon
VRM for Pentium IV processor
Programmable step-down power supply
Block Diagram
+12V
BYPASS
6
23
BOOT A
18
+12V
13
OSC
UVL O
5V Reg
RT
+
-
+
14
Digital
Control
15
+12V
17
16
+
Current
Limit
VO
BOOT B
+
GNDA
12
+12V
11
Digital
Control
+
1 2 3 4 5
8
Power
Good
5-Bit
DAC
VID0 VID2 VID4
VID1 VID3
10
+12V
24
19
PWRGD
9
21
7
DROOP/E* AGND
22
ENABLE/SS
20
ILIM
Pentium is a registered trademark of Intel Corporation. Athlon is a registered trademark of AMD. Programmable Active Droop is a trademark of Fairchild Semiconductor.
REV. 1.1.0 3/27/03
FAN5093
PRODUCT SPECIFICATION
Pin Assignments
VID0
VID1
VID2
VID3
VID4
BYPASS
AGND
LDRVB
PGNDB
SWB
HDRVB
BOOTB
1
2
3
4
5
6
7
8
9
10
11
12
FAN5093
24
23
22
21
20
19
18
17
16
15
14
13
VFB
RT
ENABLE/SS
DROOP/E*
ILIM
PWRGD
VCC
LDRVA
PGNDA
SWA
HDRVA
BOOTA
Pin Definitions
Pin Number
Pin Name
Pin Function Description
VID0-4
Voltage Identification Code Inputs. Open collector/TTL compatible inputs will
program the output voltage over the ranges specified in Table 1. Internally PulledUp.
6
BYPASS
5V Rail. Bypass this pin with a 0.1µF ceramic capacitor to AGND.
7
AGND
Analog Ground. Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
8
LDRVB
Low Side FET Driver for B. Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should optimally be <0.5".
9
PGNDB
Power Ground B. Return pin for high currents flowing in low-side MOSFET.
Connect directly to low-side MOSFET source.
10
SWB
High side driver source and low side driver drain switching node B. Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
11
HDRVB
High Side FET Driver B. Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should optimally be <0.5".
12
BOOTB
Bootstrap B. Input supply for high-side MOSFET.
13
BOOTA
Bootstrap A. Input supply for high-side MOSFET.
14
HDRVA
High Side FET Driver A. Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should optimally be <0.5".
15
SWA
High side driver source and low side driver drain switching node A. Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
16
PGNDA
Power Ground A. Return pin for high currents flowing in low-side MOSFET.
Connect directly to low-side MOSFET source.
17
LDRVA
Low Side FET Driver for A. Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should optimally be <0.5".
18
VCC
VCC. Internal IC supply. Connect to system 12V supply, and decouple with a 10Ω
resistor and 1µF ceramic capacitor.
19
PWRGD
Power Good Flag. An open collector output that will be logic LOW if the output
voltage is less than 350mV less than the nominal output voltage setpoint. Power
Good is prevented from going low until the output voltage is out of spec for
500µsec.
1-5
2
REV. 1.1.0 3/27/03
PRODUCT SPECIFICATION
Pin Number
FAN5093
Pin Name
Pin Function Description
20
ILIM
Current Limit. A resistor from this pin to ground sets the over current trip level.
21
DROOP/E*
Droop Control/Energy Star Mode Control. A resistor from this pin to ground
sets the amount of droop by controlling the gain of the current sense amplifier.
When this pin is pulled high to BYPASS, the phase A drivers are turned off for
Energy-star operation.
22
ENABLE/SS
Output Enable/Softstart. A logic LOW on this pin will disable the output. An
10µA internal current source allows for open collector control. This pin also
doubles as soft start.
23
RT
Frequency Set. A resistor from this pin to ground sets the switching frequency.
24
VFB
Voltage Feedback. Connect to the desired regulation point at the output of the
converter.
Absolute Maximum Ratings (Absolute Maximum Ratings are the values beyond which the device
may be damaged or have it’s useful life impaired. Functional operation under these conditions is not implied.)
Parameter
Min.
Max.
Unit
Supply Voltage VCC
15
V
Supply Voltages BOOT to PGND
24
V
BOOT to SW
24
V
Voltage Identification Code Inputs, VID0-VID4
6
V
VFB, ENABLE/SS, PWRGD, DROOP/E*
6
V
SWA, SWB to AGND (<1µs)
-3
15
V
PGNDA, PGNDB to AGND
-0.5
0.5
V
3
A
Gate Drive Current, peak pulse
Junction Temperature, TJ
-55
150
°C
Storage Temperature
-65
150
°C
Thermal Ratings
Parameter
Max.
Unit
Lead Soldering Temperature, 10 seconds
Min.
Typ.
300
°C
Power Dissipation, PD
650
mW
Thermal Resistance Junction-to-Case, ΘJC
16
°C/W
Thremal Resistance Junction-to-Ambient, ΘJA
84
°C/W
Recommended Operating Conditions (See Figure 2)
Parameter
Output Driver Supply, BOOTA, B
Ambient Operating Temperature
Supply Voltage VCC
REV. 1.1.0 3/27/03
Conditions
Min.
Max.
Units
16
22
V
0
70
°C
10.8
13.2
V
3
FAN5093
PRODUCT SPECIFICATION
Electrical Specifications
(VCC = 12V, VID = [01111] = 1.475V, and TA = +25°C using circuit in Figure 2, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Input Supply
UVLO Hysteresis
12V UVLO
12V Supply Current
Internal Voltage Regulator
BYPASS Voltage
BYPASS Capacitor
VREF and DAC
Output Voltage
Initial Voltage Setpoint1
Output Temperature Drift
Line Regulation
Droop2
Programmable Droop Range
Response Time
Current Mismatch
VID Inputs
Input LOW current, VID pins
VID VIH
VID VIL
Oscillator
Oscillator Frequency
Oscillator Range
Maximum Duty Cycle
Minimum LDRV on-time
Gate Drive
Gate Drive On-Resistance
Output Driver Rise & Fall Time
Enable/Soft Start
Soft Start Current
Enable Threshold
Power Good
PWRGD Threshold
PWRGD Output Voltage
PWRGD Delay
OVP and OTP
Output Overvoltage Detect
Over Temperature Shutdown
Over Temperature Hysteresis
Conditions
Rising Edge
PWM Output Open
•
Min.
Typ.
8.5
4.75
100
See Table 1
ILOAD = 0A, VID = [01111]
TA = 0 to 70°C
VCC = 11.4V to 12.6V
ILOAD = 69A, RDROOP = 13.3kΩ
•
1.100
1.460
•
Max.
Units
0.5
9.5
20
10.3
V
V
mA
5
5.25
V
nF
1.850
1.490
5
V
V
mV
µV
mV
mΩ
nsec
%
0.8
µA
V
V
1.475
5
130
56
0
∆Vout = 10mV
RDS,on (A) = RDS,on (B),
ILOAD = 69A, Droop = 1mΩ
VVID = 0.4V
RT = 54.9kΩ
RT = 137.5kΩ to 13.75 kΩ
RT = 137.5kΩ
RT = 13.75kΩ
-60
2.0
•
440
200
Sink & Source
See Figure 1, CL = 3000pF
ON
OFF
Logic LOW, VVID – VPWRGD
Isink = 4mA
High → Low
1.25
100
500
560
2000
90
330
kHz
kHz
%
nsec
1.0
20
Ω
nsec
10
µA
V
1.0
0.4
•
85
88
92
0.4
%VOUT
V
µsec
2.3
150
V
°C
°C
500
•
2.1
130
2.2
140
40
Notes:
1. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than
0.5mΩ trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal
performance.
2. Using the VFB pin for remote sensing of the converter’s output at the load, the converter will be in compliance with VRM 9.x
specification.
4
REV. 1.1.0 3/27/03
PRODUCT SPECIFICATION
FAN5093
Gate Drive Test Circuit
tR
tF
90%
90%
VOUT
10%
HDRV
2.5V
2V
10%
3000pF
tDT
tDT
2V
2V
LDRV
Figure 1. Output Drive Timing Diagram
Table 1. Output Voltage Programming Codes
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VOUT to CPU
OFF
1.100V
1.125V
1.150V
1.175V
1.200V
1.225V
1.250V
1.275V
1.300V
1.325V
1.350V
1.375V
1.400V
1.425V
1.450V
1.475V
1.500V
1.525V
1.550V
1.575V
1.600V
1.625V
1.650V
1.675V
1.700V
1.725V
1.750V
1.775V
1.800V
1.825V
1.850V
Note:
1. 0 = VID pin is tied to GND.
1 = VID pin is pulled up to 5V.
REV. 1.1.0 3/27/03
5
FAN5093
PRODUCT SPECIFICATION
Typical Operating Characteristics
(VCC = 12V, VOUT = 1.475V, and TA = +25°C using circuit in Figure 2, unless otherwise noted.)
ADAPTIVE GATE DELAY
CH1: HDRVB
CH2: LDRVB
40A Load
EFFICIENCY VS. OUTPUT CURRENT
90
EFFICIENCY (%)
E* Mode
85
2 Phase Mode
80
75
70
0
10
20
30
40
50
60
70
80
LOAD CURRENT (A)
HIGH-SIDE GATE DRIVES, NORMAL OPERATION
CH1: HDRVB
CH2: HDRVA
40A Load
HIGH-SIDE GATE DRIVES, RISE / FALL TIME
CH1: HDRVB
40A Load
6
HIGH-SIDE GATE DRIVES, E*-MODE
CH1: HDRVB
CH2: HDRVA
10A Load
LOW-SIDE GATE DRIVES, RISE / FALL TIME
CH1: LDRVB
40A Load
REV. 1.1.0 3/27/03
PRODUCT SPECIFICATION
FAN5093
Typical Operating Characteristics (Continued)
DYNAMIC VID CHANGE
CH1: VOUT (1.475V-1.575V)
CH2: VID2
40A Load
OUTPUT RIPPLE, 70A LOAD
CURRENT SHARING, 30A LOAD
CURRENT SHARING, 70A LOAD
CH1: IL1 (5A/div)
CH2: IL2 (5A/div)
CH1: IL1 (5A/div)
CH2: IL2 (5A/div)
CURRENT LIMIT
DROOP VS. RDROOP
CH1: Iin
CH2: Vout
3.00
2.50
Droop (mV/A) (mΩ)
RT = 49.9K
2.00
1.50
1.00
RT = 61.9K
0.50
0.00
0
5
10
15
20
25
30
35
40
Rdroop (KΩ)
REV. 1.1.0 3/27/03
7
FAN5093
PRODUCT SPECIFICATION
Typical Operating Characteristics (Continued)
START-UP, 40A LOAD
POWER-DOWN, 40A LOAD
CH1: Vout
CH2: Vin
CH1: Vout
CH2: Vin
LOAD TRANSIENT, 0-40A
LOAD TRANSIENT, 12-52A
CH1: Iout (20A/div)
CH2: Vout
CH1: Iout (20A/div)
CH2: Vout
CLOSED LOOP RESPONSE, 40A LOAD
VOUT TEMPERATURE VARIATION
40
150
GAIN (dB)
Phase Margin
30
120
20
90
Gain
10
60
0
30
-10
100
1000
10000
FREQUENCY (HZ)
8
0
100000
1.501
1.500
1.499
VOUT (V)
180
PHASE MARGIN (DEG.)
50
1.498
1.497
1.496
1.495
1.494
0
25
70
100
TEMPERATURE (°C)
REV. 1.1.0 3/27/03
PRODUCT SPECIFICATION
FAN5093
Application Circuit
Vi n
L3
+12V
D3
D1
D2
C2
C1
+5V
+ Cin
C5
R10
R11
18
C6
5
4
3
2
1
23
22
21
20
R13
R14
6
C10
R12
L1
VCore
SWB
11
R3
Q3
Q4
R4
10
PWRGD
VID4
VID3
VID2
VID1
VID0
LDRVB
PGND B
BOOTA
RT
HDRVA
ENABLE/SS
SWA
8
Vi n
9
C3
13
R5
C4
Q5
R6
14
Q6
L2
15
DROOP/E*
R7
Q7
+ Cout
IL IM
BYPASS
C9
LDRVA
PGNDA
7
Q2
12
VCC
HDRVB
VID4
VID3
VID2
VID1
VID0
Q1
R2
BOOTB
C7
19
R1
C8
U1
FAN5093
AGND
VFB
R8
17
Q8
16
24
R9
Figure 2. Application Circuit for 70A VRM 9.x Desktop Application
Table 2. FAN5093 Application Bill of Materials for Figure 2
Reference
QTY
Description
Manufacturer / Number
U1
1
IC, PWM, FAN5093
Fairchild FAN5093
Q1-8
8
NFET, 30V, 50A, 9mΩ
Fairchild FDD6696
D1, 2, 3
3
DIOS, 40V, 500mA
Fairchild MBR0540
L1, 2
2
IND, 850nH, 30A, 0.9mΩ
Inter-Technical SCTA5022A-R85M
opt
IND, 750nH, 20A, 3.5mΩ
Inter-Technical SC4015-R75M
L3
R1-4, 9
5
4.7Ω, 5%
R5-8
4
2.2Ω, 5%
R10
1
10Ω, 5%
R11
1
10K, 5%
R12
1
75.0K, 1%
R13
1
13.3K, 1%
R14
1
56.2K, 1%
C1-6
6
1.0µf, 25V, 10%, X7R
C7-10
4
0.1µf, 16V, 10%, X7R
Cin
4
1500µf, 16V, 20%,12mΩ, Aluminum Electrolytic
Rubycon 16MBZ1500M
Cout
8
2200µf, 6.3V, 20%, 12mΩ, Aluminum Electrolytic
Rubycon 6.3MBZ2200M
REV. 1.1.0 3/27/03
9
FAN5093
Application Information
PRODUCT SPECIFICATION
output pins for each phase. These outputs control the external
power MOSFETs.
Operation
The FAN5093 Controller
The FAN5093 is a programmable synchronous two-phase
DC-DC controller IC. When designed with the appropriate
external components, the FAN5093 can be configured to
deliver more than 50A of output current, for VRM 9.x
applications. The FAN5093 functions as a fixed frequency
PWM step down regulator, with a high efficiency mode (E*)
at light load.
Main Control Loop
Refer to the FAN5093 Block Diagram on page 1. The
FAN5093 consists of two interleaved synchronous buck converters, implemented with summing-mode control. Each
phase has its own current feedback, and there is a common
voltage feedback.
The two buck converters controlled by the FAN5093 are
interleaved, that is, they run 180° out of phase. This minimizes the RMS input ripple current, minimizing the number
of input capacitors required. It also doubles the effective
switching frequency, improving transient response.
The FAN5093 implements “summing mode control”, which
is different from both classical voltage-mode and currentmode control. It provides superior performance to either by
allowing a large converter bandwidth over a wide range of
output loads and external components. No external compensation is required.
The control loop of the regulator contains two main sections:
the analog control block and the digital control block. The
analog section consists of signal conditioning amplifiers
feeding into a comparator which provides the input to the
digital control block. The signal conditioning section accepts
inputs from a current sensor and a voltage sensor, with the
voltage sensor being common to both phases, and the current
sensor separate for each. The voltage sensor amplifies the
difference between the VFB signal and the reference voltage
from the DAC and presents the output to each of the two
comparators. The current control path for each phase takes
the difference between its PGND and SW pins when the lowside MOSFET is on, reproducing the voltage across the
MOSFET and thus the input current; it presents the resulting
signal to the same input of its summing amplifier, adding its
signal to the voltage amplifier’s with a certain gain. These
two signals are thus summed together. This sum is then presented to a comparator looking at the oscillator ramp, which
provides the main PWM control signal to the digital control
block. The oscillator ramps are 180° out of phase with each
other, so that the two phases are on alternately.
The digital control block takes the analog comparator input
to provide the appropriate pulses to the HDRV and LDRV
10
Response Time
The FAN5093 utilizes leading-edge, not trailing-edge
control. Conventional trailing-edge control turns on the
high-side MOSFET at a clock signal, and then turns it off
when the error amplifier output voltage is equal to the ramp
voltage. As a result, the response time of a trailing-edge
converter can be as long as the off-time of the high-side
driver, nearly an entire switching period. The FAN5093’s
leading-edge control turns the high-side MOSFET on when
the error amplifier output voltage is equal to the ramp voltage, and turns it off at the clock signal. As a result, when a
transient occurs, the FAN5093 responds immediately by
turning on the high-side MOSFET. Response time is set by
the internal propagation delays, typically 100nsec. In worst
case, the response time is set by the minimum on-time of the
low-side MOSFET, 330nsec.
Oscillator
The FAN5093 oscillator section runs at a frequency determined by a resistor from the RT pin to ground according to
the formula
27.5E9
R T ( Ω ) = ------------------f ( Hz )
The oscillator generates two internal sawtooth ramps, each at
one-half the oscillator frequency, and running 180° out of
phase with each other. These ramps cause the turn-on time of
the two phases to be phased apart. The oscillator frequency
of the FAN5093 can be programmed from 200KHz to 2MHz
with each phase running at 100KHz to 1MHz, respectively.
Selection of a frequency will depend on various system
performance criteria, with higher frequency resulting in
smaller components but typically lower efficiency.
Remote Voltage Sense
The FAN5093 has true remote voltage sense capability, eliminating errors due to trace resistance. To utilize remote sense,
the VFB and AGND pins should be connected as a Kelvin
trace pair to the point of regulation, such as the processor
pins. The converter will maintain the voltage in regulation at
that point. Care is required in layout of these grounds; see the
layout guidelines in this datasheet.
High Current Output Drivers
The FAN5093 contains four high current output drivers that
utilize MOSFETs in a push-pull configuration. The drivers
for the high-side MOSFETs use the BOOT pin for input
power and the SW pin for return. The drivers for the low-side
MOSFETs use the VCC pin for input power and the PGND
pin for return. Typically, the BOOT pin will use a charge
pump as shown in Figure 2. Note that the BOOT and VCC
pins are separated from the chip’s internal power and ground,
BYPASS and AGND, for switching noise immunity.
REV. 1.1.0 3/27/03
PRODUCT SPECIFICATION
Adaptive Delay Gate Drive
The FAN5093 embodies an advanced design that ensures
minimum MOSFET transition times while eliminating
shoot-through current. It senses the state of the MOSFETs
and adjusts the gate drive adaptively to ensure that they are
never on simultaneously. When the high-side MOSFET turns
off, the voltage on its source begins to fall. When the voltage
there reaches approximately 2.5V, the low-side MOSFETs
gate drive is applied. When the low-side MOSFET turns off,
the voltage at the LDRV pin is sensed. When it drops below
approximately 2V, the high-side MOSFET’s gate drive is
applied.
Maximum Duty Cycle
In order to ensure that the current-sensing and chargepumping work, the FAN5093 guarantees that the low-side
MOSFET will be on a certain portion of each period. For low
frequencies, this occurs as a maximum duty cycle of approximately 90%. Thus at 250KHz, with a period of 4µsec, the
low-side will be on at least 4µsec • 10% = 400nsec. At higher
frequencies, this time might fall so low as to be ineffective.
The FAN5093 guarantees a minimum low-side on-time of
approximately 330nsec, regardless of duty cycle.
Current Sensing
FAN5093
Short Circuit Current Characteristics
(ILIM Pin)
The FAN5093 short circuit current characteristic includes a
function that protects the DC-DC converter from damage in
the event of a short circuit. The short circuit limit is set with
the RS resistor, as given by the formula
R S ( Ω ) = I SC • R DS, on • R T • 3.33
with ISC the desired output current limit, RT the oscillator
resistor and RDS,on one phase’s low-side MOSFET’s on
resistance. Remember to make the RS large enough to
include the effects of initial tolerance and temperature variation on the MOSFETs’ RDS,on.
Important Note! The oscillator frequency must be selected
before selecting the current limit resistor, because the value
of RT is used in the calculation of RS.
When an overcurrent is detected, the high-side MOSFETs
are turned off, and the low-side MOSFETs are turned on,
and they remain in this state until the measured current
through the low-side MOSFET has returned to zero amps.
After reaching zero, the FAN5093 re-soft-starts, ensuring
that it can also safely turn on into a short.
The FAN5093 has two independent current sensors, one for
each phase. Current sensing is accomplished by measuring
the source-to-drain voltage of the low-side MOSFET during
its on-time. Each phase has its own power ground pin, to permit the phases to be placed in different locations without
affecting measurement accuracy. For best results, it is important to connect the PGND and SW pins for each phase as a
Kelvin trace pair directly to the source and drain, respectively, of the appropriate low-side MOSFET. Care is required
in the layout of these grounds; see the layout guidelines in
this datasheet.
A limitation on the current sense circuit is that ISC • RDS,on
must be less that 375mV. To ensure correct operation, use
ISC • RDS,on ≤ 300mV; between 300mV and 375mV, there
will be some non-linearity in the short-circuit current not
accounted for in the equation.
Current Sharing
The converter exhibits a normal load regulation characteristic until the voltage across the MOSFETs exceeds the internal short circuit threshold of 50KΩ/(3.9mΩ • 41.2KΩ • 6.66)
= 47A. [Note that this current limit level can be as high as
50KΩ/(3.5mΩ • 41.2KΩ • 6.66) = 52A, if the MOSFETs
have typical RDS,on rather than maximum, and are at 25°C.]
At this point, the internal comparator trips and signals the
controller to leave on the low-side MOSFETs and keep off
the high-side MOSFETs. The inductor current decreases,
and power is not applied again until the inductor current
reaches 0A and the converter attempts to re-softstart.
The two independent current sensors of the FAN5093 operate
with their independent current control loops to guarantee that
the two phases each deliver half of the total output current.
The only mismatch between the two phases occurs if there is
a mismatch between the RDS,on of the low-side MOSFETs.
Light Load Efficiency
At light load, the FAN5093 uses a number of techniques to
improve efficiency. Because a synchronous buck converter is
two quadrant, able to both source and sink current, during
light load the inductor current will flow away from the output and towards the input during a portion of the switching
cycle. This reverse current flow is detected by the FAN5093
as a positive voltage appearing on the low-side MOSFET
during its on-time. When reverse current flow is detected,
the low-side MOSFET is turned off for the rest of the cycle,
and the current instead flows through the body diode of the
high-side MOSFET, returning the power to the source. This
technique substantially enhances light load efficiency.
REV. 1.1.0 3/27/03
As an example, consider the typical characteristic of the
DC-DC converter circuit with two FDP6670AL low-side
MOSFETs (RDS = 6.5mΩ maximum at 25°C • 1.2 at 75°C
= 7.8mΩ each, or 3.9mΩ total) in each phase, RT = 42.1KΩ
(600KHz oscillator) and a 50KΩ RS.
E*-mode
In addition, further enhancement in efficiency can be
obtained by putting the FAN5093 into E*-mode. When the
Droop pin is pulled to the 5V BYPASS voltage, the “A”
phase of the FAN5093 is completly turned off, reducing in
half the amount of gate charge power being consumed.
E*-mode can be implemented with the circuit shown in
Figure 3.
11
FAN5093
PRODUCT SPECIFICATION
FAN5098, Pin 6
(Bypass)
10K
2N3906
FAN5098, Pin 21
(Droop, E*)
1K
10K
2N3904
HI=E*MODE
RDROOP
10K
Figure 3. Implementing E*-mode Control
Note: The charge pump for the HIDRVs should be based on
the “B” phase of the FAN5093, since the “A” phase is off in
E*-mode.
Output Enable/Soft Start (ENABLE/SS)
The FAN5093 will accept an open collector/TTL signal for
controlling the output voltage. The low state disables the
output voltage. When disabled, the PWRGD output is in the
low state.
Even if an enable is not required in the circuit, this pin
should have attached a capacitor (typically 100nF) to softstart the switching. A softstart capacitor may be approximately chosen by the formula:
C SS ( 1.7 + 0.9074 • VOUT )
t D = -------------- • ---------------------------------------------------------2.5
10µA
where: tD is the delay time before the output starts to ramp
C SS V OUT • 0.9
t R = -------------- • ---------------------------V IN
10µA
Internal Voltage Reference
The reference included in the FAN5093 is a precision bandgap voltage reference. Its internal resistors are precisely
trimmed to provide a near zero temperature coefficient (TC).
Based on the reference is the output from an integrated 5-bit
DAC. The DAC monitors the 5 voltage identification pins,
VID0-4, and scales the reference voltage from 1.100V to
1.850V in 25mV steps.
BYPASS Reference
The internal logic of the FAN5093 runs on 5V. To permit the
IC to run with 12V only, it produces 5V internally with a
linear regulator, whose output is present on the BYPASS pin.
This pin should be bypassed with a 100nF capacitor for noise
suppression. The BYPASS pin should not have any external
load attached to it.
Dynamic Voltage Adjustment
The FAN5093 can have its output voltage dynamically
adjusted to accommodate low power modes. The designer
must ensure that the transitions on the VID lines all occur
simultaneously (within less than 500nsec) to avoid false codes
generating undesired output voltages. The Power Good flag
tracks the VID codes, but has a 500µsec delay transitioning
from high to low; this is long enough to ensure that there will
not be any glitches during dynamic voltage adjustment.
Power Good (PWRGD)
The FAN5093 Power Good function is designed in accordance with the Pentium IV DC-DC converter specifications
and provides a continuous voltage monitor on the VFB pin.
The circuit compares the VFB signal to the VREF voltage
and outputs an active-low interrupt signal to the CPU should
the power supply voltage deviate more than -12% of its nominal setpoint. The Power Good flag provides no control functions to the FAN5093.
tR is the ramp time of the output
CSS = softstart cap
VOUT = nominal output voltage
However, C must be ≥ 100nF.
Programmable Active Droop™
The FAN5093 features Programmable Active Droop™: as
the output current increases, the output voltage drops proportionately an amount that can be programmed with an external resistor. This feature is offered in order to allow
maximum headroom for transient response of the converter.
The current is sensed losslessly by measuring the voltage
across the low-side MOSFET during its on time. Consult the
section on current sensing for details. The droop is adjusted
by the droop resistor changing the gain of the current loop.
Note that this method makes the droop dependent on the
temperature and initial tolerance of the MOSFET, and the
droop must be calculated taking account of these tolerances.
Given a maximum output current, the amount of droop can
be programmed with a resistor to ground on the droop pin,
according to the formula
V Droop • R T
R Droop ( Ω ) = ------------------------------------I max • R DS, on
with VDroop the desired droop voltage, RT the oscillator
resistor, Imax the output current at which the droop is desired,
and RDS, on the on-state resistance of one phase’s low-side
MOSFET.
Important Note! The oscillator frequency must be selected
before selecting the droop resistor, because the value of RT is
used in the calculation of RDroop.
Over-Voltage Protection
The FAN5093 constantly monitors the output voltage for
protection against over-voltage conditions. If the voltage at
12
REV. 1.1.0 3/27/03
PRODUCT SPECIFICATION
the VFB pin exceeds 2.2V, an over-voltage condition is
assumed and the FAN5093 latches on the external low-side
MOSFET and latches off the high-side MOSFET. The
DC-DC converter returns to normal operation only after VCC
has been recycled.
Over Temperature Protection
If the FAN5093 die temperature exceeds approximately
150°C, the IC shuts itself off. It remains off until the temperature has dropped approximately 25°C, at which time it
resumes normal operation.
Component Selection
MOSFET Selection
This application requires N-channel Enhancement Mode Field
Effect Transistors. Desired characteristics are as follows:
•
•
•
•
•
Low Drain-Source On-Resistance,
RDS,ON < 10mΩ (lower is better);
Power package with low Thermal Resistance;
Drain-Source voltage rating > 15V;
Low gate charge, especially for higher frequency
operation.
For the low-side MOSFET, the on-resistance (RDS,ON) is the
primary parameter for selection. Because of the small duty
cycle of the high-side, the on-resistance determines the
power dissipation in the low-side MOSFET and therefore
significantly affects the efficiency of the DC-DC converter.
For high current applications, it may be necessary to use two
MOSFETs in parallel for the low-side for each phase.
For the high-side MOSFET, the gate charge is as important
as the on-resistance, especially with a 12V input and with
higher switching frequencies. This is because the speed of
the transition greatly affects the power dissipation. It may be
a good trade-off to select a MOSFET with a somewhat
higher RDS,on, if by so doing a much smaller gate charge is
available. For high current applications, it may be necessary
to use two MOSFETs in parallel for the high-side for each
phase.
At the FAN5093’s highest operating frequencies, it may be
necessary to limit the total gate charge of both the high-side
and low-side MOSFETs together, to avert excess power dissipation in the IC.
For details and a spreadsheet on MOSFET selection, refer to
Applications Bulletin AB-8.
Gate Resistors
Use of a gate resistor on every MOSFET is mandatory. The
gate resistor prevents high-frequency oscillations caused by
the trace inductance ringing with the MOSFET gate
capacitance. The gate resistors should be located physically
as close to the MOSFET gate as possible.
REV. 1.1.0 3/27/03
FAN5093
The gate resistor also limits the power dissipation inside the
IC, which could otherwise be a limiting factor on the switching frequency. It may thus carry significant power, especially
at higher frequencies. As an example: The FDB7045L has a
maximum gate charge of 70nC at 5V, and an input capacitance of 5.4nF. The total energy used in powering the gate
during one cycle is the energy needed to get it up to 5V, plus
the energy to get it up to 12V:
2
1
1
E = QV + --- C • ∆V 2 = 70nC • 5V + --- 5.4nF • ( 12V – 5V )
2
2
= 482nJ
This power is dissipated every cycle, and is divided between
the internal resistance of the FAN5093 gate driver and the
gate resistor. Thus,
E • f • R gate
P Rgate = ------------------------------------------------ = 482nJ • 300KHz •
( R gate + R internal )
4.7Ω
--------------------------------- = 131mW
4.7Ω + 0.5Ω
and each gate resistor thus requires a 1/4W resistor to ensure
worst case power dissipation.
Inductor Selection
Choosing the value of the inductor is a tradeoff between
allowable ripple voltage and required transient response.
A smaller inductor produces greater ripple while producing
better transient response. In any case, the minimum inductance is determined by the allowable ripple. The first order
equation (close approximation) for minimum inductance for
a two-phase converter is:
V in – 2 • V out V out ESR
L min = ----------------------------------- • ----------- • ----------------V in V ripple
f
where:
Vin = Input Power Supply
Vout = Output Voltage
f = DC/DC converter switching frequency
ESR = Equivalent series resistance of all output capacitors in
parallel
Vripple = Maximum peak to peak output ripple voltage
budget.
Schottky Diode Selection
The application circuit of Figure 2 shows a Schottky diode,
D1 (D2 respectively), one in each phase. They are used as
free-wheeling diodes to ensure that the body-diodes in the
low-side MOSFETs do not conduct when the upper
MOSFET is turning off and the lower MOSFETs are turning
on. It is undesirable for this diode to conduct because its high
forward voltage drop and long reverse recovery time
degrades efficiency, and so the Schottky provides a shunt
path for the current. Since this time duration is extremely
short, being minimized by the adaptive gate delay, the
selection criterion for the diode is that the forward voltage of
13
FAN5093
PRODUCT SPECIFICATION
the Schottky at the output current should be less than the forward voltage of the MOSFET’s body diode. Power capability
is not a criterion for this device, as its dissipation is very
small.
L3
Vin
+12V
1000µF, 16V
Electrolytic
Output Filter Capacitors
The output bulk capacitors of a converter help determine its
output ripple voltage and its transient response. It has
already been seen in the section on selecting an inductor that
the ESR helps set the minimum inductance. For most converters, the number of capacitors required is determined by
the transient response and the output ripple voltage, and
these are determined by the ESR and not the capacitance
value. That is, in order to achieve the necessary ESR to meet
the transient and ripple requirements, the capacitance value
required is already very large.
The most commonly used choice for output bulk capacitors
is aluminum electrolytics, because of their low cost and low
ESR. The only type of aluminum capacitor used should be
those that have an ESR rated at 100kHz. Consult Application
Bulletin AB-14 for detailed information on output capacitor
selection.
For higher frequency applications, particularly those running
the FAN5093 oscillator at >1MHz, Oscon or ceramic capacitors may be considered. They have much smaller ESR than
comparable electrolytics, but also much smaller capacitance.
The output capacitance should also include a number of
small value ceramic capacitors placed as close as possible to
the processor; 0.1µF and 0.01µF are recommended values.
Input Filter
The DC-DC converter design may include an input inductor
between the system main supply and the converter input as
shown in Figure 2. This inductor serves to isolate the main
supply from the noise in the switching portion of the DC-DC
converter, and to limit the inrush current into the input capacitors during power up. A value of 1.3µH is recommended.
It is necessary to have some low ESR capacitors at the input
to the converter. These capacitors deliver current when the
high side MOSFET switches on. Because of the interleaving,
the number of such capacitors required is greatly reduced
from that required for a single-phase buck converter. Figure
2 shows 3 x 1500µF, but the exact number required will vary
with the output voltage and current, according to the formula
I out
I rms = --------- 2DC – 4DC 2
2
for the two phase FAN5093, where DC is the duty cycle,
DC = Vout / Vin. Capacitor ripple current rating is a function
of temperature, and so the manufacturer should be contacted
to find out the ripple current rating at the expected operational temperature. For details on the design of an input filter,
refer to Applications Bulletin AB-16.
14
Figure 4. Input Filter
Design Considerations and Component
Selection
Additional information on design and component selection
may be found in Fairchild’s Application Note 59.
PCB Layout Guidelines
• Placement of the MOSFETs relative to the FAN5093 is
critical. Place the MOSFETs such that the trace length of
the HIDRV and LODRV pins of the FAN5093 to the FET
gates is minimized. A long lead length on these pins will
cause high amounts of ringing due to the inductance of the
trace and the gate capacitance of the FET. This noise
radiates throughout the board, and, because it is switching
at such a high voltage and frequency, it is very difficult to
suppress.
• In general, all of the noisy switching lines should be kept
away from the quiet analog section of the FAN5093. That
is, traces that connect to pins 8-17 (LODRV, HIDRV,
PGND and BOOT) should be kept far away from the
traces that connect to pins 1 through 7, and pins 18-24.
• Place the 0.1µF decoupling capacitors as close to the
FAN5093 pins as possible. Extra lead length on these
reduces their ability to suppress noise.
• Each power and ground pin should have its own via to the
appropriate plane. This helps provide isolation between
pins.
• Place the MOSFETs, inductor, and Schottky of a given
phase as close together as possible for the same reasons as
in the first bullet above. Place the input bulk capacitors as
close to the drains of the high side MOSFETs as possible.
In addition, placement of a 0.1µF decoupling cap right on
the drain of each high side MOSFET helps to suppress
some of the high frequency switching noise on the input
of the DC-DC converter.
• Place the output bulk capacitors as close to the CPU as
possible to optimize their ability to supply instantaneous
current to the load in the event of a current transient.
Additional space between the output capacitors and the
CPU will allow the parasitic resistance of the board traces
to degrade the DC-DC converter’s performance under
severe load transient conditions, causing higher voltage
deviation. For more detailed information regarding
capacitor placement, refer to Application Bulletin AB-5.
• A PC Board Layout Checklist is available from Fairchild
Applications. Ask for Application Bulletin AB-11.
REV. 1.1.0 3/27/03
PRODUCT SPECIFICATION
FAN5093
PC Motherboard Sample Layout and Gerber File
Additional Information
A reference design for motherboard implementation of the
FAN5093 along with the PCAD layout Gerber file and silk
screen can be obtained through your local Fairchild representative.
For additional information contact your local Fairchild
representative.
FAN5093 Evaluation Board
Fairchild provides an evaluation board to verify the system
level performance of the FAN5093. It serves as a guide to
performance expectations when using the supplied external
components and PCB layout. Please contact your local
Fairchild representative for an evaluation board.
REV. 1.1.0 3/27/03
15
FAN5093
PRODUCT SPECIFICATION
Mechanical Dimensions – 24 Lead TSSOP
Inches
Symbol
Millimeters
Min.
Max.
Min.
Max.
A
A1
B
C
D
—
.002
.007
.004
.303
.047
.006
—
0.05
0.19
0.09
7.70
1.20
0.15
E
e
H
.169
.177
.026 BSC
.252 BSC
.018
.030
4.30
4.50
0.65 BSC
6.40 BSC
0.45
0.75
24
24
L
N
α
ccc
.012
.008
.316
0.30
0.20
7.90
0°
8°
0°
8°
—
.004
—
0.10
Notes:
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .006 inch (0.15mm).
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5. Symbol "N" is the maximum number of terminals.
2
2
3
5
D
E
H
C
A1
A
B
e
SEATING
PLANE
–C–
α
L
LEAD COPLANARITY
ccc C
16
REV. 1.1.0 3/27/03
FAN5093
PRODUCT SPECIFICATION
Ordering Information
Product Number
Description
Package
FAN5093MTC
VRM 9.x DC-DC Controller
24 pin TSSOP
FAN5093MTCX
VRM 9.x DC-DC Controller
24 pin TSSOP in Tape and Reel
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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3/27/03 0.0m 005
Stock#DS30005093
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