Fairchild FDB8870 N-channel powertrench mosfet 30v, 160a, 3.9mw Datasheet

FDB8870
N-Channel PowerTrench® MOSFET
30V, 160A, 3.9m Ω
General Description
Features
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
r DS(ON) and fast switching speed.
• r DS(ON) = 3.9mΩ, V GS = 10 V, ID = 35A
• r DS(ON) = 4.4mΩ, V GS = 4.5V, I D = 35A
• High performance trench technology for extremely low
r DS(ON)
• Low gate charge
Applications
• High power and current handling capability
• DC/DC converters
D
GATE
G
SOURCE
TO-263AB
DRAIN
(FLANGE)
S
FDB SERIES
MOSFET Maximum Ratings T C = 25°C unless otherwise noted
Symbol
V DSS
Drain to Source Voltage
Parameter
Ratings
30
Units
V
V GS
Gate to Source Voltage
±20
V
Continuous (T C = 25 o C, V GS = 10V) (Note 1)
160
A
Continuous (T C = 25 o C, V GS = 4.5V) (Note 1)
150
A
Continuous (T amb = 25 o C, VGS = 10 V, with Rθ JA = 43 o C/W)
23
A
Drain Current
ID
Pulsed
E AS
PD
TJ, T STG
Single Pulse Avalanche Energy (Note 2)
Figure 4
A
300
mJ
Power dissipation
160
W
Derate above 25 o C
1.07
W/ o C
-55 to 175
oC
0.94
o C/W
Operating and Storage Temperature
Thermal Characteristics
Rθ JC
Thermal Resistance Junction to Case TO-263
Rθ JA
Thermal Resistance Junction to Ambient TO-263 ( Note 3)
62
o C/W
Rθ JA
Thermal Resistance Junction to Ambient TO-263, 1in 2 copper pad area
43
o C/W
Package Marking and Ordering Information
Device Marking
FDB8870
©2004 Fairchild Semiconductor Corporation
Device
FDB8870
Package
TO-263AB
Reel Size
330mm
Tape Width
24mm
Quantity
800 units
FDB8870 Rev. A1
FDB8870
September 2004
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
30
-
-
-
V
-
1
-
-
250
-
-
±100
nA
-
2.5
V
Off Characteristics
B VDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, V GS = 0V
V DS = 24V
V GS = 0V
T C = 150 o C
V GS = ±20V
µA
On Characteristics
V GS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
V GS = VDS , I D = 250µA
1.2
ID = 35A, V GS = 10V
-
0.0032 0.0039
ID = 35A, V GS = 4.5V
-
0.0038 0.0044
ID = 35A, V GS = 10V,
T J = 175 o C
-
0.0051 0.0065
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
-
5200
-
pF
-
970
-
CRSS
Reverse Transfer Capacitance
pF
-
570
-
RG
Gate Resistance
pF
V GS = 0.5V, f = 1MHz
-
2.1
-
Qg(TOT)
Ω
Total Gate Charge at 10V
V GS = 0V to 10V
-
106
132
nC
Qg(5)
Total Gate Charge at 5V
V GS = 0V to 5V
Qg(TH)
Threshold Gate Charge
V GS = 0V to 1V
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
Switching Characteristics
V DS = 15V, V GS = 0V,
f = 1MHz
V DD = 15V
ID = 35A
Ig = 1.0mA
-
56
69
nC
-
5.0
6.5
nC
-
15
-
nC
-
10
-
nC
-
23
-
nC
(V GS = 10V)
tO N
Turn-On Time
-
-
162
ns
td(ON)
Turn-On Delay Time
-
10
-
ns
tr
Rise Time
-
98
-
ns
td(OFF)
Turn-Off Delay Time
-
75
-
ns
tf
Fall Time
-
47
-
ns
tOFF
Turn-Off Time
-
-
183
ns
ISD = 35A
-
-
1.25
V
ISD = 15A
-
-
1.0
V
V DD = 15V, I D = 35A
V GS = 10V, R GS = 3.3Ω
Drain-Source Diode Characteristics
V SD
Source to Drain Diode Voltage
trr
Reverse Recovery Time
ISD = 35A, dI SD /dt = 100A/µs
-
-
37
ns
QRR
Reverse Recovered Charge
ISD = 35A, dI SD /dt = 100A/µs
-
-
21
nC
Notes:
1: Package current limitation is 80A.
2: Starting TJ = 25°C, L = 0.15mH, I A S = 64A, VD D = 27V, VGS = 10V.
3: Pulse width = 100s.
©2004 Fairchild Semiconductor Corporation
FDB8870 Rev. A1
FDB8870
Electrical Characteristics TC = 25°C unless otherwise noted
FDB8870
Typical Characteristics TC = 25°C unless otherwise noted
175
1.0
150
I D, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
CURRENT LIMITED
BY PACKAGE
125
100
75
50
0.2
25
0
0
25
50
75
100
150
125
0
175
25
50
75
TC , CASE TEMPERATURE (oC)
100
125
150
175
TC , CASE TEMPERATURE (o C)
Figure 1. Normalized Power Dissipation vs Case
Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
Zθ JC , NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1 /t 2
PEAK TJ = P DM x Z θJC x RθJC + TC
SINGLE PULSE
0.01
10 -5
10-4
10 -3
10 -2
10-1
10 0
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
TC = 25 o C
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
ID M, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
CURRENT AS FOLLOWS:
VGS = 4.5V
175 - TC
I = I25
150
100
50
10 -5
10 -4
10 -3
10-2
10-1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2004 Fairchild Semiconductor Corporation
FDB8870 Rev. A1
FDB8870
Typical Characteristics TC = 25°C unless otherwise noted
1000
500
If R = 0
tA V = (L)(IA S)/(1.3*RATED BVDSS - V D D)
If R ≠ 0
t A V = (L/R)ln[(IA S*R)/(1.3*RATED BVDSS - VD D ) +1]
IAS , AVALANCHE CURRENT (A)
ID , DRAIN CURRENT (A)
10µs
100
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
1
10ms
SINGLE PULSE
TJ = MAX RATED
TC = 25 o C
DC
100
STARTING TJ = 25 o C
10
STARTING TJ = 150o C
0.1
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
0.1
1
10
t A V, TIME IN AVALANCHE (ms)
Figure 6. Unclamped Inductive Switching
Capability
160
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
VGS = 5V
VGS = 4V
120
TJ = 175 o C
80
TJ = 25 o C
40
120
V GS = 10V
V GS = 3V
80
40
TC = 25o C
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
TJ = -55oC
0
0
1.5
2.0
2.5
3.0
V GS , GATE TO SOURCE VOLTAGE (V)
0
3.5
0.25
0.5
0.75
1.0
V D S, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
1.6
10
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = 35A
rDS (ON) , DRAIN TO SOURCE
ON RESISTANCE (mΩ)
100
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
I D, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
160
1
0.01
60
8
6
4
ID = 1A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.4
1.2
1.0
0.8
VGS = 10V, ID = 35A
2
2
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
©2004 Fairchild Semiconductor Corporation
0.6
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (o C)
200
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
FDB8870 Rev. A1
FDB8870
Typical Characteristics TC = 25°C unless otherwise noted
1.2
1.4
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = V D S, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
1.2
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
160
1.1
1.0
0.9
-80
200
-40
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
80
120
160
200
10
CRSS = CGD
VGS , GATE TO SOURCE VOLTAGE (V)
CISS = CGS + C GD
C, CAPACITANCE (pF)
40
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10000
COSS ≅ CDS + CGD
1000
VD D = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
I D = 35A
I D = 5A
2
VGS = 0V, f = 1MHz
400
0.1
0
TJ , JUNCTION TEMPERATURE (o C)
TJ, JUNCTION TEMPERATURE ( o C)
0
1
10
V D S, DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Source
Voltage
©2004 Fairchild Semiconductor Corporation
30
0
20
40
60
Qg , GATE CHARGE (nC)
80
100
Figure 14. Gate Charge Waveforms for Constant
Gate Current
FDB8870 Rev. A1
FDB8870
Test Circuits and Waveforms
VDS
BVDSS
tP
L
VD S
VARY t P TO OBTAIN
IAS
+
RG
REQUIRED PEAK I AS
VD D
VDD
-
VGS
DUT
tP
IAS
0V
0.01Ω
0
tA V
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VD S
VDD
Q g(TOT)
VDS
L
VGS
VGS = 10V
VGS
Qg(5)
+
Qgs2
VD D
VGS = 5V
DUT
VGS = 1V
I g(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VD S
t ON
t OFF
t d(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
V GS
50%
50%
PULSE WIDTH
V GS
0
Figure 19. Switching Time Test Circuit
©2004 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveforms
FDB8870 Rev. A1
FDB8870
Thermal Resistance vs. Mounting Pad Area
(T
–T )
JM
A
P D M = ----------------------------R θJA
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
80
Rθ J A = 26.51+ 19.84/(0.262+Area) EQ.2
Rθ JA = 26.51+ 128/(1.69+Area) EQ.3
60
Rθ JA (o C/W)
The maximum rated junction temperature, TJ M, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P DM, in an
application.
Therefore the application’s ambient
temperature, T A (o C), and thermal resistance R θJA ( o C/W)
must be reviewed to ensure that T JM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
40
20
0.1
1
10
(0.645)
(6.45)
AREA, TOP COPPER AREA in2 (cm2 )
(64.5)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the Rθ JA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
R θJA =
19.84
26.51 + ------------------------------------( 0.262 + Area )
(EQ. 2)
Area in Inches Squared
R θJA =
128
26.51 + ---------------------------------( 1.69 + Area)
(EQ. 3)
Area in Centimeters Squared
©2004 Fairchild Semiconductor Corporation
FDB8870 Rev. A1
.SUBCKT FDB8870 2 1 3 ; rev December 2003
Ca 12 8 4.5e-9
Cb 15 14 4.5e-9
Cin 6 8 4.7e-9
LDRAIN
DPLCAP
5
DRAIN
2
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
+
RSLC2
5
51
Ebreak 11 7 17 18 33.45
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
ESLC
EVTHRES
+ 19 8
+
LGATE
GATE
1
It 8 17 1
11
50
+
17
EBREAK 18
-
RDRAIN
6
8
ESG
DBREAK
EVTEMP
RGATE + 18 9
20 22
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
Lgate 1 9 3.6e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 3.3e-9
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RLSOURCE
RLgate 1 9 36
RLdrain 2 5 10
RLsource 3 7 33
S1A
12
S2A
13
8
CA
15
14
13
S1B
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
17
18
S2B
RVTEMP
13
CB
+
+
6
8
EGS
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1.95e-3
Rgate 9 20 2.1
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 9e-4
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
RBREAK
VBAT
5
8
EDS
-
19
IT
14
-
+
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}
.MODEL DbodyMOD D (IS=7.5E-12 IKF=17 N=1.01 RS=2.1e-3 TRS1=2e-3 TRS2=2e-7
+ CJO=1.9e-9 M=0.57 TT=9e-11 XTI=2.6)
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.75e-9 IS=1e-30 N=10 M=0.4)
.MODEL MmedMOD NMOS (VTO=2.1 KP=30 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.1 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=2.51 KP=650 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=1.67 KP=0.1 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=21 RS=0.1 T_ABS=25)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-9e-7)
.MODEL RdrainMOD RES (TC1=2.4e-3 TC2=5.5e-6)
.MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=8e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-2.3e-3 TC2=-9e-6)
.MODEL RvtempMOD RES (TC1=-3e-3 TC2=2e-7)
.MODEL
.MODEL
.MODEL
.MODEL
.ENDS
S1AMOD
S1BMOD
S2AMOD
S2BMOD
VSWITCH
VSWITCH
VSWITCH
VSWITCH
(RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2)
(RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4)
(RON=1e-5 ROFF=0.1 VON=-1 VOFF=-0.5)
(RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-1)
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2004 Fairchild Semiconductor Corporation
FDB8870 Rev. A1
FDB8870
PSPICE Electrical Model
FDB8870
SABER Electrical Model
rev December 2003
template FDB8870 n2,n1,n3 =m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod = (isl=7.5e-12,ikf=17,nl=1.01,rs=2.1e-3,trs1=2e-3,trs2=2e-7,cjo=1.9e-9,m=0.57,tt=9e-11,xti=2.6)
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.75e-9,isl=10e-30,nl=10,m=0.4)
m..model mmedmod = (type=_n,vto=2.1,kp=30,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.51,kp=650,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.67,kp=0.1,is=1e-30, tox=1,rs=0.1)
LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-2)
DPLCAP 5
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4)
10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=-0.5)
RLDRAIN
RSLC1
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-1)
51
c.ca n12 n8 = 4.5e-9
RSLC2
c.cb n15 n14 = 4.5e-9
ISCL
c.cin n6 n8 = 4.7e-9
spe.ebreak n11 n7 n17 n18 = 33.45 GATE
spe.eds n14 n8 n5 n8 = 1
1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
DRAIN
2
8
LSOURCE
SOURCE
3
7
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
12
l.lgate n1 n9 = 3.6e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 3.3e-9
13
8
14
13
S1B
CA
res.rlgate n1 n9 = 36
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 33
S2A
RBREAK
15
17
18
S2B
13
+
6
8
EGS
RVTEMP
CB
+
-
19
IT
14
VBAT
5
8
EDS
-
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-9e-7
res.rdrain n50 n16 = 1.95e-3, tc1=2.4e-3,tc2=5.5e-6
res.rgate n9 n20 = 2.1
res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 9e-4, tc1=8e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-2.3e-3,tc2=-9e-6
res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))
}
}
©2004 Fairchild Semiconductor Corporation
FDB8870 Rev. A1
th
FDB8870
PSPICE Thermal Model
JUNCTION
REV 23 December 2003
FDB8870T
CTHERM1 TH 6 1e-3
CTHERM2 6 5 2e-3
CTHERM3 5 4 3e-3
CTHERM4 4 3 9e-3
CTHERM5 3 2 1e-2
CTHERM6 2 TL 2e-2
RTHERM1
CTHERM1
6
RTHERM1 TH 6 3e-2
RTHERM2 6 5 8e-2
RTHERM3 5 4 1.1e-1
RTHERM4 4 3 1.6e-1
RTHERM5 3 2 1.72e-1
RTHERM6 2 TL 2e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDB8870T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1e-3
ctherm.ctherm2 6 5 =2e-3
ctherm.ctherm3 5 4 =3e-3
ctherm.ctherm4 4 3 =9e-3
ctherm.ctherm5 3 2 =1e-2
ctherm.ctherm6 2 tl =2e-2
rtherm.rtherm1 th 6 =3e-2
rtherm.rtherm2 6 5 =8e-2
rtherm.rtherm3 5 4 =1.1e-1
rtherm.rtherm4 4 3 =1.6e-1
rtherm.rtherm5 3 2 =1.72e-1
rtherm.rtherm6 2 tl =2e-1
}
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2004 Fairchild Semiconductor Corporation
CASE
FDB8870 Rev. A1
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Rev. I12