Fairchild FDG6301N Dual n-channel, digital fet Datasheet

FDG6301N_F085
Dual N-Channel, Digital FET
General Description
Features
25 V, 0.22 A continuous, 0.65 A peak.
RDS(ON) = 4 Ω @ VGS= 4.5 V,
RDS(ON) = 5 Ω @ VGS= 2.7 V.
These dual N-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. This device has been
designed especially for low voltage applications as a
replacement for bipolar digital transistors and small
signal MOSFETs.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (VGS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
Compact industry standard SC70-6 surface mount
package.
Qualified to AEC Q101
RoHS Compliant
SuperSOTTM-6
SOT-23
SC70-6
D1
G2
SC70-6
SO-8
SuperSOTTM-8
SOT-223
S2
1 or 4 *
.01
S1
G1
D2
6 or 3
2 or 5
5 or 2
3 or 6
4 or 1 *
*The pinouts are symmetrical; pin 1 and 4 are interchangeable.
Units inside the carrier can be of either orientation and will not affect the functionality of the device.
Absolute Maximum Ratings
TA = 25°C unless otherwise noted
Symbol
Parameter
VDSS
Drain-Source Voltage
FDG6301N_F085
VGSS
Gate-Source Voltage
ID
Drain/Output Current
PD
Maximum Power Dissipation
TJ,TSTG
Operating and Storage Temperature Range
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model(100 pF / 1500 Ω)
- Continuous
- Pulsed
Units
25
V
8
V
0.22
A
0.65
(Note 1)
0.3
W
-55 to 150
°C
6.0
kV
415
°C/W
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
©2009 Fairchild Semiconductor Corporation
FDG6301N_F085 Rev. A
1
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FDG6301N_F085 Dual N-Channel, Digital FET
March 2009
Symbol
Parameter
Conditions
Min
25
Typ
Max
Units
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
ID = 250 µA, Referenced to 25 o C
IDSS
Zero Gate Voltage Drain Current
VDS = 20 V, VGS = 0 V
V
TJ = 55°C
IGSS
Gate - Body Leakage Current
mV / oC
25
VGS = 8 V, VDS = 0 V
1
µA
10
µA
100
nA
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
∆VGS(th)/∆TJ
Gate Threshold Voltage Temp.Coefficient
ID = 250 µA, Referenced to 25 o C
0.65
-2.1
RDS(ON)
Static Drain-Source On-Resistance
VGS = 4.5 V, ID = 0.22 A
2.6
4
5.3
7
3.7
5
TJ =125°C
VGS = 2.7 V, ID = 0.19 A
0.85
1.5
V
mV / oC
0.22
Ω
ID(ON)
On-State Drain Current
VGS = 4.5 V, VDS = 5 V
A
gFS
Forward Transconductance
VDS = 5 V, ID= 0.22 A
0.2
S
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
9.5
pF
6
pF
1.3
pF
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
tD(on)
Turn - On Delay Time
tr
Turn - On Rise Time
tD(off)
Turn - Off Delay Time
tf
Turn - Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 5 V, ID = 0.5 A,
VGS = 4.5 V, RGEN = 50 Ω
VDS = 5 V, ID = 0.22 A,
VGS = 4.5 V
5
10
ns
4.5
10
ns
4
8
ns
3.2
7
ns
0.29
0.4
nC
0.12
nC
0.03
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Source Current
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 0.25 A
(Note 2)
0.8
0.25
A
1.2
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed
by design while RθCA is determined by the user's board design. RθJA = 415OC/W on minimum pad mounting on FR-4 board in still air.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDG6301N_F085 Rev. A
2
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FDG6301N_F085 Dual N-Channel, Digital FET
Electrical Characteristics (TA = 25 OC unless otherwise noted )
0.4
5
3.5V
3.0V
2.7V
0.3
2.5V
0.2
2.0V
0.1
0
R DS(ON), NORMALIZED
VGS =4.5V
0
1
2
3
4
DRAIN-SOURCE ON-RESISTANCE
I D, DRAIN-SOURCE CURRENT (A)
0.5
4.5
VGS = 2.5V
2.7V
4
3.0V
3.5
3.5V
4.0V
3
2
5
0
0.1
Figure 1. On-Region Characteristics.
0.4
20
I D = 0.22A
RDS(ON), ON-RESISTANCE(OHM)
RDS(ON) , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
0.3
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage .
1.8
V GS = 4.5V
ID = 0.10A
16
1.4
12
1.2
1
0.8
0.6
-50
-25
0
25
50
75
100
125
8
TA =125°C
4
25°C
0
150
T , JUNCTION TEMPERATURE (°C)
1
2
J
0.4
TJ = -55°C
V DS = 5V
25°C
125°C
0.15
0.1
0.05
0
0.5
1.5
2
2.5
3
VGS = 0V
TJ = 125°C
0.01
25°C
-55°C
0.001
0
0.2
0.4
0.6
0.8
1
1.2
VSD , BODY DIODE FORWARD VOLTAGE (V)
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
Figure 5. Transfer Characteristics.
FDG6301N_F085 Rev. A
5
0.1
0.0001
1
4
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
I S , REVERSE DRAIN CURRENT (A)
0.2
3
VGS ,GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation
with Temperature.
I D , DRAIN CURRENT (A)
0.2
5.0V
I D , DRAIN CURRENT (A)
VDS , DRAIN-SOURCE VOLTAGE (V)
1.6
4.5V
2.5
3
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FDG6301N_F085 Dual N-Channel, Digital FET
Typical Electrical Characteristics
6
VDS = 5V
V GS , GATE-SOURCE VOLTAGE (V)
I D = 0.22A
10V
CAPACITANCE (pF)
5
30
4
3
2
0
0.1
0.2
0.3
0.4
0.5
Coss
5
2
0.1
0.6
Ciss
8
3
1
0
15
Crss
f = 1 MHz
VGS = 0 V
0.3
3
10
25
Figure 8. Capacitance Characteristics.
Figure 7. Gate Charge Characteristics.
1
50
0.3
RD
S(
O
L
N)
IM
10m
s
IT
1s
0.1
10
s
V GS = 4.5V
SINGLE PULSE
RθJA = 415 °C/W
T A = 25°C
0.03
0.01
0.4
0.8
SINGLE PULSE
R θJA=415°C/W
TA= 25°C
40
10
0m
s
POWER (W)
I D , DRAIN CURRENT (A)
1
V DS , DRAIN TO SOURCE VOLTAGE (V)
Q g , GATE CHARGE (nC)
DC
30
20
10
2
5
10
25
0
0.0001
40
0.001
0.01
0.1
1
10
200
SINGLE PULSE TIME (SEC)
VDS , DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
1
0.5
D = 0.5
0.2
0.2
0.1
R θJA (t) = r(t) * R θJA
R θJA =415 °C/W
0.1
0.05
0.02
0.01
P(pk)
0.05
t1
0.02
0.01
Duty Cycle, D = t 1/ t 2
0.005
0.002
0.0001
t2
TJ - TA = P * R θJA (t)
Single Pulse
0.001
0.01
0.1
1
10
100
200
t 1, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in note 1.
Transient thermal response will change depending on the circuit board design.
FDG6301N_F085 Rev. A
4
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FDG6301N_F085 Dual N-Channel, Digital FET
Typical Electrical Characteristics ( continued)
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Rev. I39
FDG6301N_F085 Rev. A
5
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FDG6301N_F085 Dual N-Channel, Digital FET
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