UniFET FDP7N50/FDPF7N50 TM 500V N-Channel MOSFET Features Description • 7A, 500V, RDS(on) = 0.9Ω @VGS = 10 V These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. • Low gate charge ( typical 12.8 nC) • Low Crss ( typical 9 pF) This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficient switched mode power supplies and active power factor correction. • Fast switching • 100% avalanche tested • Improved dv/dt capability D G G DS TO-220 FDP Series TO-220F GD S FDPF Series S Absolute Maximum Ratings Symbol Parameter VDSS Drain-Source Voltage ID Drain Current - Continuous (TC = 25°C) - Continuous (TC = 100°C) IDM Drain Current - Pulsed VGSS Gate-Source voltage EAS IAR FDP7N50 FDPF7N50 500 V 7 4.2 (Note 1) Unit 28 7* 4.2 * A A 28 * A ±30 V Single Pulsed Avalanche Energy (Note 2) 270 mJ Avalanche Current (Note 1) 7 A EAR Repetitive Avalanche Energy (Note 1) 8.9 mJ dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns PD Power Dissipation (TC = 25°C) - Derate above 25°C 89 0.71 TJ, TSTG Operating and Storage Temperature Range TL Maximum Lead Temperature for Soldering Purpose, 1/8” from Case for 5 Seconds 31.3 0.25 W W/°C -55 to +150 °C 300 °C * Drain current limited by maximum junction temperature. Thermal Characteristics Symbol Parameter FDP7N50 FDPF7N50 Unit Thermal Resistance, Junction-to-Case 1.4 4.0 °C/W RθCS Thermal Resistance, Case-to-Sink Typ. 0.5 -- °C/W RθJA Thermal Resistance, Junction-to-Ambient 62.5 62.5 °C/W RθJC ©2007 Fairchild Semiconductor Corporation FDP7N50/FDPF7N50 REV. B 1 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET April 2007 Device Marking Device Package Reel Size Tape Width Quantity FDP7N50 FDP7N50 TO-220 -- -- 50 FDPF7N50 FDPF7N50 TO-220F -- -- 50 Electrical Characteristics Symbol TC = 25°C unless otherwise noted Parameter Conditions Min. Typ. Max Units 500 -- -- V Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0V, ID = 250μA ΔBVDSS / ΔTJ Breakdown Voltage Temperature Coefficient ID = 250μA, Referenced to 25°C -- 0.5 -- V/°C IDSS Zero Gate Voltage Drain Current VDS = 500V, VGS = 0V VDS = 400V, TC = 125°C --- --- 1 10 μA μA IGSSF Gate-Body Leakage Current, Forward VGS = 30V, VDS = 0V -- -- 100 nA IGSSR Gate-Body Leakage Current, Reverse VGS = -30V, VDS = 0V -- -- -100 nA 3.0 -- 5.0 V -- 0.76 0.9 Ω -- 2.5 -- S -- 720 940 pF -- 95 190 pF -- 9 13.5 pF -- 6 20 ns -- 55 120 ns -- 25 60 ns On Characteristics VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250μA RDS(on) Static Drain-Source On-Resistance VGS = 10V, ID = 3.5A gFS Forward Transconductance VDS = 40V, ID = 3.5A (Note 4) Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = 25V, VGS = 0V, f = 1.0MHz Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 250V, ID = 7A RG = 25Ω (Note 4, 5) VDS = 400V, ID = 7A VGS = 10V (Note 4, 5) -- 35 80 ns -- 12.8 16.6 nC -- 3.7 -- nC -- 5.8 -- nC Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current -- -- 7 A ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 28 A VSD Drain-Source Diode Forward Voltage VGS = 0V, IS = 7A -- -- 1.4 V trr Reverse Recovery Time -- 275 -- ns Qrr Reverse Recovery Charge VGS = 0V, IS = 7A dIF/dt =100A/μs -- 0.04 -- μC (Note 4) NOTES: 1. Repetitive Rating: Pulse width limited by maximum junction temperature 2. IAS = 7A, VDD = 50V, L=10mH, RG = 25Ω, Starting TJ = 25°C 3. ISD ≤ 7A, di/dt ≤ 200A/μs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test: Pulse width ≤ 300μs, Duty Cycle ≤ 2% 5. Essentially Independent of Operating Temperature Typical Characteristics FDP7N50/FDPF7N50 REV. B 2 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Package Marking and Ordering Information Figure 1. On-Region Characteristics 20 Figure 2. Transfer Characteristics VGS Top : 10.0 V 8.0 V 7.5 V 7.0 V 6.5 V 6.0 V 5.5 V Bottom : 5.0 V 1 10 ID , Drain Current [A] ID, Drain Current [A] 15 10 * Notes : 1. 250μs Pulse Test 5 o 150 C 0 10 o 25 C o -55 C -1 10 o * Note: 1. VDS = 40V 2. TC = 25 C 2. 250μs Pulse Test 0 0 10 20 30 40 -2 50 10 2 VDS, Drain-Source Voltage [V] 6 10 Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature IDR , Reverse Drain Current [A] 2.5 2.0 VGS = 10V 1.5 1.0 VGS = 20V 0.5 1 10 0 10 o 150 C o 25 C * Notes : 1. VGS = 0V 2. 250μs Pulse Test o * Note : TJ = 25 C 0.0 -1 0 5 10 15 10 20 0.2 0.4 0.6 0.8 Figure 5. Capacitance Characteristics VGS, Gate-Source Voltage [V] Ciss Coss Crss * Notes : 1. VGS = 0 V 2. f = 1 MHz 10 10 VDS = 400V 8 6 4 2 * Note : ID = 7 A 0 5 10 15 QG, Total Gate Charge [nC] VDS, Drain-Source Voltage [V] FDP7N50/FDPF7N50 REV. B 1.8 VDS = 250V 10 0 1 10 1.6 VDS = 100V Crss = Cgd 0 1.4 12 Ciss = Cgs + Cgd (Cds = shorted) 100 1.2 Figure 6. Gate Charge Characteristics Coss = Cds + Cgd 1000 1.0 VSD , Source-Drain Voltage [V] ID, Drain Current [A] Capacitance [pF] 8 VGS , Gate-Source Voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage RDS(ON) [Ω],Drain-Source On-Resistance 4 3 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Typical Performance Characteristics Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 3.0 RDS(ON), (Normalized) 1.1 1.0 *Notes : 1. VGS = 0 V 0.9 2. ID = 250 μA Drain-Source On-Resistance BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.2 2.5 2.0 1.5 1.0 ∗Notes : 1. VGS = 10 V 0.5 2. ID = 3.5 A 0.8 -100 -50 0 50 100 150 0.0 -100 200 o TJ, Junction Temperature [ C] -50 0 50 100 150 Figure 9-1. Maximum Safe Operating Area - FDP7N50 Figure 9-2. Maximum Safe Operating Area - FDPF7N50 10 us 1 ms 10 ms 100 ms 0 Operation in This Area is Limited by R DS(on) DC -1 10 100 us 1 10 ID, Drain Current [A] ID, Drain Current [A] 10 us 100 us 1 10 10 * Notes : o 1. TC = 25 C 1 ms 10 ms 0 Operation in This Area is Limited by R DS(on) 10 100 ms DC -1 10 * Notes : o 1. TC = 25 C o 2. TJ = 150 C o 2. TJ = 150 C 3. Single Pulse 3. Single Pulse -2 10 200 o TJ, Junction Temperature [ C] -2 0 1 10 10 2 10 10 0 10 VDS, Drain-Source Voltage [V] 1 10 2 10 VDS, Drain-Source Voltage [V] Figure 10. Maximum Drain Current Vs. Case Temperature 8 ID, Drain Current [A] 6 4 2 0 25 50 75 100 125 150 o TC, Case Temperature [ C] FDP7N50/FDPF7N50 REV. B 4 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Typical Performance Characteristics (Continued) FDP7N50/FDPF7N50 500V N-Channel MOSFET Figure 11-1. Transient Thermal Response Curve - FDP7N50 10 0 ZθJC(t), Thermal Response D = 0 .5 0 .2 0 .1 10 -1 PDM 0 .0 5 t1 0 .0 2 0 .0 1 * N o te s : t2 o 1 . Z θ JC (t) = 1 .4 C /W M a x. 2 . D u ty F a c to r, D = t 1 /t 2 s in g le p u ls e 10 3 . T J M - T C = P D M * Z θ JC (t) -2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ] Figure 11-2. Transient Thermal Response Curve - FDPF7N50 ZθJC(t), Thermal Response D = 0 .5 10 0 0 .2 0 .1 0 .0 5 10 PDM 0 .0 2 -1 t1 0 .0 1 * N o te s : t2 o 1 . Z θ JC (t) = 4 .0 C /W M a x. 2 . D u ty F a c to r, D = t 1 /t 2 3 . T J M - T C = P D M * Z θ J C (t) s in g le p u ls e 10 -2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ] FDP7N50/FDPF7N50 REV. B 5 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Gate Charge Test Circuit & Waveform Resistive Switching Test Circuit & Waveforms Unclamped Inductive Switching Test Circuit & Waveforms FDP7N50/FDPF7N50 REV. B 6 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Peak Diode Recovery dv/dt Test Circuit & Waveforms FDP7N50/FDPF7N50 REV. B 7 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Mechanical Dimensions TO-220 Dimensions in Millimeters FDP7N50/FDPF7N50 REV. B 8 www.fairchildsemi.com (Continued) TO-220F 3.30 ±0.10 10.16 ±0.20 2.54 ±0.20 ø3.18 ±0.10 (7.00) (1.00x45°) 15.87 ±0.20 15.80 ±0.20 6.68 ±0.20 (0.70) 0.80 ±0.10 ) 0° (3 9.75 ±0.30 MAX1.47 #1 +0.10 0.50 –0.05 2.54TYP [2.54 ±0.20] 2.76 ±0.20 2.54TYP [2.54 ±0.20] 9.40 ±0.20 4.70 ±0.20 0.35 ±0.10 Dimensions in Millimeters FDP7N50/FDPF7N50 REV. B 9 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Mechanical Dimensions TRADEMARKS The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Definition Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I31 © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com