FDS6982 Dual N-Channel, Notebook Power Supply MOSFET General Description Features This part is designed to replace two single SO-8 MOSFETs in synchronous DC:DC power supplies that provide the various peripheral voltage rails required in notebook computers and other battery powered electronic devices. FDS6982 contains two unique 30V, N-channel, logic level, PowerTrenchTM MOSFETs designed to maximize power conversion efficiency. • The high-side switch (Q1) is designed with specific emphasis on reducing switching losses while the low-side switch (Q2) is optimized for low conduction (less than 20mΩ at VGS = 4.5V). Applications • Battery powered synchronous DC:DC converters. • Embedded DC:DC conversion. Q2: 8.6A, 30V. RDS(on) = 0.015 Ω @ VGS = 10V RDS(on) = 0.020 Ω @ VGS = 4.5V • Q1: 6.3A, 30V. RDS(on) = 0.028 Ω @ VGS = 10V RDS(on) = 0.035 Ω @ VGS = 4.5V • Fast switching speed. • Low gate charge (Q1 typical = 8.5nC). • High performance trench technology for extremely low RDS(ON). D2 D2 5 D1 D1 4 Q1 6 SO-8 G1 G2 S2 2 7 Q2 8 1 S1 Absolute Maximum Ratings Symbol 3 T A = 25°C unless otherwise noted Parameter Q2 Q1 Units V DSS Drain-Source Voltage 30 30 V V GSS Gate-Source Voltage ID Drain Current ±20 8.6 ±20 6.3 A PD Power Dissipation for Dual Operation - Continuous (Note 1a) - Pulsed Power Dissipation for Single Operation 30 TJ, Tstg 20 2 (Note 1a) 1.6 (Note 1b) 1 (Note 1c) Operating and Storage Junction Temperature Range V W 0.9 -55 to +150 °C °C/W °C/W Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 RθJC Thermal Resistance, Junction-to-Case (Note 1) 40 Package Marking and Ordering Information Device Marking Device Reel Size Tape Width Quantity FDS6982 FDS6982 13” 12mm 2500 units 1999 Fairchild Semiconductor Corporation FDS6982, Rev. C FDS6982 June 1999 Symbol Parameter TA = 25°C unless otherwise noted Test Conditions Type Min Typ Max Units Off Characteristics BVDSS VGS = 0 V, ID = 250 µA IGSSF Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage, Forward IGSSR Gate-Body Leakage, Reverse VGS = -20 V, VDS = 0 V ∆BVDSS ∆TJ IDSS On Characteristics VDS = 24 V, VGS = 0 V Q2 Q1 Q2 Q1 All VGS = 20 V, VDS = 0 V ID = 250 µA, Referenced to 25°C 30 30 V mV/°C 27 26 1 µA All 100 nA All -100 nA 3 3 V (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA ∆VGS(th) ∆TJ RDS(on) Gate Threshold Voltage Temperature Coefficient Static Drain-Source On-Resistance ID = 250 µA, Referenced to 25°C ID(on) On-State Drain Current gFS Forward Transconductance VGS = 10 V, ID = 8.6 A VGS = 10 V, ID = 8.6 A, TJ = 125°C VGS = 4.5 V, ID = 7.5 A VGS = 10 V, ID = 6.3 A VGS = 10 V, ID = 6.3 A, TJ = 125°C VGS = 4.5 V, ID = 5.6 A VGS = 10 V, VDS = 5 V VDS = 5 V, ID = 8.6 A VDS = 5 V, ID = 6.3 A Q2 Q1 Q2 Q1 Q2 1 1 Q1 Q2 Q1 Q2 Q1 2.2 1.6 -5 -4 0.012 0.018 0.016 0.021 0.038 0.028 30 20 mV/°C 0.015 0.024 0.020 0.028 0.047 0.035 Ω A 50 40 S 2085 760 420 160 160 70 pF Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = 10 V, VGS = 0 V, f = 1.0 MHz Q2 Q1 Q2 Q1 Q2 Q1 pF pF FDS6982, Rev. C FDS6982 Electrical Characteristics Symbol Parameter Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd (continued) TA = 25°C unless otherwise noted Test Conditions Type Min Typ Max Units (Note 2) Gate-Drain Charge VDD = 15 V, ID = 1 A, VGS = 10V, RGEN = 6 Ω Q2 VDS = 15 V, ID = 8.6 A, VGS = 5 V Q1 VDS = 15 V, ID = 6.3 A,VGS = 5 V Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 15 10 11 14 36 21 18 7 18.5 8.5 7.3 2.4 6.2 3.1 27 18 20 25 58 34 29 14 26 12 ns ns ns ns nC nC nC Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward VGS = 0 V, IS = 1.3 A Voltage VGS = 0 V, IS = 1.3 A (Note 2) (Note 2) Q2 Q1 Q2 Q1 0.72 0.74 1.3 1.3 1.2 1.2 A V Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθJA is determined by the user's board design. a) 78° C/W when mounted on a 0.5 in2 pad of 2 oz. copper. b) 125° C/W when mounted on a 0.02 in2 pad of 2 oz. copper. c) 135° C/W when mounted on a 0.003 in2 pad of 2 oz. copper. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0% FDS6982, Rev. C FDS6982 Electrical Characteristics FDS6982 Typical Characteristics: Q2 2 50 VGS = 10V 5.0V 4.5V 40 1.8 VGS = 4.0V 1.6 4.0V 30 4.5V 1.4 5.0V 20 1.2 6.0V 7.0V 3.5V 10 10V 1 3.0V 0 0 1 2 0.8 3 0 4 10 20 Figure 1. On-Region Characteristics. 1.6 30 40 50 ID, DRAIN CURRENT (A) VDS, DRAIN-SOURCE VOLTAGE (V) Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.04 ID = 8.6A VGS = 10V ID = 4.5A 1.4 0.03 o 1.2 TA = 125 C 0.02 1 o TA = 25 C 0.01 0.8 0.6 0 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) o TJ, JUNCTION TEMPERATURE ( C) Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 50 o TA = -55 C VDS = 5V VGS = 0V o 25 C 10 o 125 C 40 o TA = 125 C 1 30 o 25 C 0.1 o -55 C 20 0.01 10 0.001 0.0001 0 1 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 6 0 0.4 0.8 1.2 1.6 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS6982, Rev. C FDS6982 Typical Characteristics: Q2 (continued) 10 3000 ID = 8.6A VDS = 5V 10V f = 1MHz VGS = 0 V 2500 8 15V CISS 2000 6 1500 4 1000 2 500 COSS CRSS 0 0 0 5 10 15 20 25 30 35 0 5 Qg, GATE CHARGE (nC) 10 15 20 25 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate-Charge Characteristics. Figure 8. Capacitance Characteristics. 30 100 SINGLE PULSE RDS(ON) LIMIT o 100µs 1ms 10 o TA = 25 C 10ms 100ms 1s 10s 1 RθJA = 135 C/W 25 20 15 DC 10 VGS = 10V SINGLE PULSE 0.1 o RθJA = 135 C/W 5 o TA = 25 C 0.01 0 0.1 1 10 VDS, DRAIN-SOURCE VOLTAGE (V) Figure 9. Maximum Safe Operating Area. 100 0.01 0.1 1 10 100 1000 SINGLE PULSE TIME (SEC) Figure 10. Single Pulse Maximum Power Dissipation. FDS6982, Rev. C FDS6982 Typical Characteristics: Q1 40 2 VGS = 10V 6.0V 4.5V 4.0V 30 1.8 1.6 VGS = 3.5V 1.4 4.0V 3.5V 20 4.5V 10 5.0V 1.2 3.0V 6.0V 10V 1 2.5V 0 0.8 0 1 2 3 4 0 10 VDS, DRAIN-SOURCE VOLTAGE (V) 20 30 40 ID, DRAIN CURRENT (A) Figure 11. On-Region Characteristics. Figure 12. On-Resistance Variation with Drain Current and Gate Voltage. 0.08 1.6 ID = 6.3A VGS = 10V ID = 3.5A 1.4 0.06 1.2 o TA = 125 C 0.04 1 o TA = 25 C 0.02 0.8 0.6 0 -50 -25 0 25 50 75 100 125 150 2 4 o TJ, JUNCTION TEMPERATURE ( C) 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 13. On-Resistance Variation with Temperature. Figure 14. On-Resistance Variation with Gate-to-Source Voltage. 100 40 o TA = -55 C VDS = 5V VGS = 0V o 25 C o 10 125 C 30 o TA = 125 C 1 o 25 C 0.1 20 o -55 C 0.01 10 0.001 0.0001 0 1 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) Figure 15. Transfer Characteristics. 6 0 0.4 0.8 1.2 1.6 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 16. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS6982, Rev. C FDS6982 Typical Characteristics: Q1 (continued) 10 1200 ID = 6.3A VDS = 5V 10V f = 1MHz VGS = 0 V 1000 8 15V 800 CISS 6 600 4 400 2 200 COSS CRSS 0 0 0 4 8 12 16 0 5 Qg, GATE CHARGE (nC) 10 15 20 25 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 17. Gate-Charge Characteristics. Figure 18. Capacitance Characteristics. 30 100 SINGLE PULSE o 100µs 1ms RDS(ON) LIMIT 10 o TA = 25 C 10ms 100ms 1s 10s 1 RθJA = 135 C/W 25 20 15 DC 10 VGS = 10V SINGLE PULSE 0.1 o 5 RθJA = 135 C/W o TA = 25 C 0.01 0 0.1 1 10 VDS, DRAIN-SOURCE VOLTAGE (V) Figure 19. Maximum Safe Operating Area. 100 0.01 0.1 1 10 100 1000 SINGLE PULSE TIME (SEC) Figure 20. Single Pulse Maximum Power Dissipation. FDS6982, Rev. C FDS6982 Typical Characteristics: Q1 & Q2 (continued) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 D = 0.5 0.2 0.2 0.1 0.05 0.02 0.01 R θJA (t) = r(t) * R θJA R θJA = 135°C/W 0.1 0.05 P(pk) 0.02 0.01 t1 Single Pulse 0.005 Duty Cycle, D = t1 /t2 0.002 0.001 0.0001 t2 TJ - TA = P * R θJA (t) 0.001 0.01 0.1 t 1, TIME (sec) 1 10 100 300 Figure 21. Transient Thermal Response Curve. FDS6982, Rev. C SO-8 Tape and Reel Data and Package Dimensions SOIC(8lds) Packaging Configuration: Figure 1.0 N ELECTROSTATIC SENSITIVE DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS TNR DATE PT NUMBER PEEL STRENGTH MIN ______________ gms MAX _____________ gms ESD Label Antistatic Cover Tape Conductive Embossed Carrier Tape F63TNR Label Pin 1 F852 831N F852 831N F852 831N F852 831N Customized Label SOIC-8 Unit Orientation SOIC (8lds) Packaging Information Packaging Option Packaging type Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Standard (no flow code) TNR L86Z S62Z D84Z Rail/Tube Bag TNR 2,500 95 200 500 13” Dia - - 7” Dia 184x187x47 343x64x343 530x130x83 76x102x127 Max qty per Box 5,000 30,000 1,000 2,500 Weight per unit (gm) 0.0774 0.0774 0.0774 0.0774 Weight per Reel (kg) 0.6060 - - 0.1182 Note/Comments Bulk 343mm x 342mm x 64mm Standard Intermediate box ESD Label F63TNR Label sample F63TNLabel LOT: CBVK741B019 F63TNLabel QTY: 2500 FSID: FDS9953A SPEC: ESD Label D/C1: D9842 D/C2: QTY1: QTY2: SPEC REV: CPN: QARV: (F63TNR)2 SOIC(8lds) Tape Leader and Trailer Configuration: Figure 2.0 Carrier Tape Cover Tape Trailer Tape 160mm minimum Components Leader Tape 390mm minimum November 1998, Rev. A SO-8 Tape and Reel Data and Package Dimensions, continued SOIC(8lds) Embossed Carrier Tape Configuration: Figure 3.0 P0 D0 T E1 F K0 Wc W E2 B0 Tc A0 D1 P1 User Direction of Feed Dimensions are in millimeter Pkg type SOIC(8lds) (12mm) A0 6.50 +/-0.10 B0 5.30 +/-0.10 W 12.0 +/-0.3 D0 D1 1.55 +/-0.05 E1 1.60 +/-0.10 E2 1.75 +/-0.10 F 10.25 min P1 5.50 +/-0.05 P0 8.0 +/-0.1 4.0 +/-0.1 K0 2.1 +/-0.10 Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C). T Wc 0.450 +/0.150 9.2 +/-0.3 0.06 +/-0.02 0.5mm maximum 20 deg maximum Typical component cavity center line B0 Tc 0.5mm maximum 20 deg maximum component rotation Typical component center line Sketch A (Side or Front Sectional View) A0 Component Rotation Sketch C (Top View) Component lateral movement Sketch B (Top View) SOIC(8lds) Reel Configuration: Figure 4.0 Component Rotation W1 Measured at Hub Dim A Max Dim A max See detail AA Dim N 7” Diameter Option B Min Dim C See detail AA W3 13” Diameter Option Dim D min W2 max Measured at Hub DETAIL AA Dimensions are in inches and millimeters Tape Size Reel Option Dim A Dim B 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 5.906 150 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 – 0.606 11.9 – 15.4 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 7.00 178 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 – 0.606 11.9 – 15.4 12mm 7” Dia 7.00 177.8 12mm 13” Dia 13.00 330 1998 Fairchild Semiconductor Corporation Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL) November 1998, Rev. A SO-8 Tape and Reel Data and Package Dimensions, continued SOIC-8 (FS PKG Code S1) 1:1 Scale 1:1 on letter size paper Dimensions shown below are in: inches [millimeters] Part Weight per unit (gram): 0.0774 9 September 1998, Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.