Fairchild FDS7064N 30v n-channel powertrench mosfet Datasheet

FDS7064N
30V N-Channel PowerTrench MOSFET
General Description
Features
This N-Channel MOSFET has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers. It has been optimized for
“low side” synchronous rectifier operation, providing an
extremely low RDS(ON) in a small package.
• 16 A, 30 V
RDS(ON) = 7.5 mΩ @ VGS = 4.5 V
• High performance trench technology for extremely
low RDS(ON)
• High power and current handling capability
Applications
• Fast switching
• Synchronous rectifier
• FLMP SO-8 package: Enhanced thermal
• DC/DC converter
performance in industry-standard package size
5
Absolute Maximum Ratings
Symbol
Bottom-side
Drain Contact
4
6
3
7
2
8
1
TA=25oC unless otherwise noted
Ratings
Units
VDSS
Drain-Source Voltage
Parameter
30
V
VGSS
Gate-Source Voltage
± 12
V
ID
Drain Current
16
A
– Continuous
(Note 1a)
– Pulsed
60
PD
Power Dissipation for Single Operation
TJ, TSTG
Operating and Storage Junction Temperature Range
(Note 1a)
3.0
W
–55 to +150
°C
Thermal Characteristics
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
(Note 1a)
40
°C/W
0.5
°C/W
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
FDS7064N
FDS7064N
13’’
12mm
2500 units
2004 Fairchild Semiconductor Corporation
FDS7064N Rev C2 (W)
FDS7064N
January 2004
Symbol
TA = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max Units
Off Characteristics
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
VGS = 0 V, ID = 250 µA
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
1
µA
IGSSF
Gate–Body Leakage, Forward
VGS = 12 V, VDS = 0 V
100
nA
IGSSR
Gate–Body Leakage, Reverse
VGS = –12 V , VDS = 0 V
–100
nA
2
V
BVDSS
∆BVDSS
∆TJ
IDSS
On Characteristics
VGS(th)
∆VGS(th)
∆TJ
RDS(on)
gFS
30
ID = 250 µA, Referenced to 25°C
V
23
mV/°C
(Note 2)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
Forward Transconductance
VDS = VGS, ID = 250 µA
ID = 250 µA, Referenced to 25°C
0.8
1.2
–4.3
mV/°C
VGS = 4.5 V, ID = 16 A
VGS = 4.5 V, ID = 16 A,TJ = 125°C
VDS = 5 V, ID = 16 A
6.2
9.0
112
7.5
11.0
VDS = 15 V, V GS = 0 V,
f = 1.0 MHz
3355
pF
522
pF
209
pF
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Switching Characteristics
td(on)
Turn–On Delay Time
tr
Turn–On Rise Time
(Note 2)
VDD = 15 V, ID = 1 A,
VGS = 4.5 V, RGEN = 6 Ω
17
30
ns
13
23
ns
td(off)
Turn–Off Delay Time
54
86
ns
tf
Turn–Off Fall Time
26
42
ns
30
48
Qg
Total Gate Charge
Qgs
Gate–Source Charge
Qgd
Gate–Drain Charge
VDS = 15 V, ID = 16 A,
VGS = 4.5 V
nC
6.3
nC
7.7
nC
Drain–Source Diode Characteristics and Maximum Ratings
IS
VSD
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
VGS = 0 V, IS = 2.5 A
Voltage
0.7
(Note 2)
2.5
A
1.2
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a)
40°C/W when
mounted on a 1in2 pad
of 2 oz copper
b)
85°C/W when mounted on
a minimum pad of 2 oz
copper
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDS7064N Rev C2 (W)
FDS7064N
Electrical Characteristics
FDS7064N
Typical Characteristics
3
VGS = 10V
3.5V
4.5V
50
ID, DRAIN CURRENT (A)
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
60
3.0V
2.5V
40
30
2.0V
20
10
VGS = 2.0V
2.5
2
2.5V
1.5
3.0V
0
0.5
1
0
1.5
10
10V
20
30
40
50
ID, DRAIN CURRENT (A)
VDS, DRAIN-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.018
1.8
ID = 16 A
VGS = 10V
1.6
RDS(ON), ON-RESISTANCE (OHM)
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
4.5V
0.5
0
1.4
1.2
1
0.8
0.6
-50
-25
0
25
50
75
100
125
150
ID = 8 A
0.014
TA = 125oC
0.01
0.006
TA = 25oC
0.002
175
1
2.5
TJ, JUNCTION TEMPERATURE (oC)
4
5.5
7
8.5
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation
withTemperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
100
60
IS, REVERSE DRAIN CURRENT (A)
VDS = 5V
50
ID, DRAIN CURRENT (A)
3.5V
1
40
30
TA = 125oC
20
25oC
10
-55oC
VGS = 0V
10
TA = 125oC
1
25oC
0.1
-55oC
0.01
0.001
0.0001
0
1
1.25
1.5
1.75
2
2.25
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
2.5
0
0.2
0.4
0.6
0.8
1
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDS7064N Rev C2 (W)
FDS7064N
Typical Characteristics
4500
VDS = 10V
ID = 16 A
4000
15V
4
3
2
3000
2500
2000
1500
1000
1
COSS
500
CRSS
0
0
0
5
10
15
20
25
30
0
35
Figure 7. Gate Charge Characteristics.
10
15
20
25
30
Figure 8. Capacitance Characteristics.
100
50
RDS(ON) LIMIT
P(pk), PEAK TRANSIENT POWER (W)
100µs
1ms
10
10ms
100ms
1s
DC
1
0.1
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VGS = 10V
SINGLE PULSE
RθJA = 88oC/W
TA = 25oC
0.01
0.01
0.1
1
10
30
20
10
0
0.01
100
SINGLE PULSE
RθJA = 88°C/W
TA = 25°C
40
0.1
VDS, DRAIN-SOURCE VOLTAGE (V)
1
10
100
t1, TIME (sec)
Figure 9. Maximum Safe Operating Area.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
ID, DRAIN CURRENT (A)
f = 1MHz
VGS = 0 V
CISS
3500
20V
CAPACITANCE (pF)
VGS, GATE-SOURCE VOLTAGE (V)
5
Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
R θJA(t) = r(t) + R θJA
R θJA = 85 °C/W
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
t1
t2
T J - T A = P * R θJA (t)
Duty Cycle, D = t1 / t2
0.01
SINGLE PULSE
0.001
0.001
0.01
0.1
1
10
100
1000
t1, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDS7064N Rev C2 (W)
FDS7064N
Dimensional Outline and Pad Layout
FDS7064N Rev C2 (W)
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not intended to be an exhaustive list of all such trademarks.
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OPTOPLANAR™
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Power247™
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CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
2. A critical component is any component of a life
1. Life support devices or systems are devices or
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I8
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