Fairchild FIN1022MTC 2 x 2 lvds high speed crosspoint switch Datasheet

Revised December 2001
FIN1022
2 X 2 LVDS High Speed Crosspoint Switch
General Description
Features
This non-blocking 2x2 crosspoint switch has a fully differential input to output data path for low noise generation and
low pulse width distortion. The device can be used as a
high speed crosspoint switch, 2:1 multiplexer, 1:2 demultiplexer or 1:2 signal splitter. The inputs can directly interface
with LVDS and LVPECL levels.
■ Low jitter, 800 Mbps full differential data path
■ Worst case jitter of 190ps
with PRBS = 223 − 1 data pattern at 800 Mbps
■ Rail-to-rail common mode range is 0.5V to 3.25V
■ Worst case power dissipation is less than 126 mW
■ Open-circuit fail safe protection
■ Fast switch time of 1.1 ns typical
■ 35 ps typical pin channel to channel skew
■ 3.3V power supply operation
■ Non-blocking switch
■ LVDS receiver inputs accept LVPECL signals directly
■ 7.5 kV HBM ESD protection
■ 16-lead SOIC package and TSSOP package
■ Inter-operates with TIA/EIA 644-1995 specification
■ See the Fairchild Interface Solutions web page for cross
reference information:
www.fairchildsemi.com/products/interface/lvds.html
Ordering Code:
Order Number
Package Number
FIN1022M
FIN1022MTC
M16A
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation
DS500653
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FIN1022 2 X 2 LVDS High Speed Crosspoint Switch
September 2001
FIN1022
Connection Diagram
Pin Descriptions
Pin Name
Description
RIN0+, RIN1+
LVDS non-inverting data inputs
RIN0−, RIN1−
LVDS inverting data inputs
DOUT0+, DOUT1+ LVDS non-inverting data outputs
DOUT0−, DOUT1− LVDS inverting data outputs
EN0
LVTTL input for enabling DOUT0+/DOUT0−
EN1
LVTTL input for enabling DOUT1+/DOUT1−
SEL0
LVTTL input for selecting RIN0+/RIN0− or
RIN1+/RIN1− for output DOUT0+/DOUT0−
SEL1
LVTTL input for selecting RIN0+/RIN0− or
RIN1+/RIN1− for output DOUT1+/DOUT1−
VCC
Power Supply
GND
Ground
Function Table
Inputs
Outputs
Mode
SEL0
SEL1
EN0
EN1
DOUT0+
DOUT0−
DOUT1+
DOUT1−
L/O
L/O
H
H
RIN0+
RIN0−
RIN0+
RIN0−
1:2 Splitter
L/O
H
H
H
RIN0+
RIN0−
RIN1+
RIN1−
Repeater
H
L/O
H
H
RIN1+
RIN1−
RIN0+
RIN0−
Switch
H
H
H
H
RIN1+
RIN1−
RIN1+
RIN1−
1:2 Splitter
X
L/O
L/O
H
Z
Z
RIN0+
RIN0−
DOUT0 Disabled
X
H
L/O
H
Z
Z
RIN1+
RIN1−
DOUT0 Disabled
L/O
X
H
L/O
RIN0+
RIN0−
Z
Z
DOUT1 Disabled
H
X
H
L/O
RIN1+
RIN1−
Z
Z
DOUT1 Disabled
X
X
L/O
L/O
Z
Z
Z
Z
O = OPEN
L / O = LOW or OPEN
H = HIGH Logic Level
L = LOW Logic Level
Function Diagrams
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2
DOUT0 and DOUT1 Disabled
X = Don’t Care
Z = High Impedance
Supply Voltage (VCC)
−0.3V to +4.6V
Recommended Operating
Conditions
DC Input Voltage (VIN)
−0.3V to +4.6V
−0.3V to +4.6V
Supply Voltage (VCC)
DC Output Voltage (VOUT)
Driver Short Circuit Current (IOSD)
Storage Temperature Range (TSTG)
Continuous
0 to VCC
−40°C to +85°C
Operating Temperature (TA)
−65°C to +150°C
Electrostatic Discharge
150°C
Max Junction Temperature (TJ)
3.0V to 3.6V
Input Voltage (VIN)
(HBM 1.5 kΩ, 100 pF)
Lead Temperature (TL)
>7500V
Electrostatic Discharge
260°C
(Soldering, 10 seconds)
(MM 0Ω, 100 pF)
>300V
Note 1: The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified (Note 2)
Symbol
Parameter
Test Conditions
Min
Typ
Max
(Note 3)
Units
LVDS Differential Driver Characteristics
VOD
Output Differential Voltage
RL = 75 Ω, See Figure 3
RL = 75 Ω, See Figure 3
TA = 25°C and VCC = 3.3V
∆VOD
VOD Magnitude Change from
Differential LOW-to-HIGH
VOS
Offset Voltage
∆VOS
Offset Magnitude Change from
Differential LOW-to-HIGH
270
365
475
285
365
440
RL = 75 Ω, See Figure 3
See Figure 3
35
1.0
1.2
mV
mV
1.45
V
See Figure 3
35
mV
µA
IOZD
Disabled Output Leakage Current
VOUT = 3.6V or GND, Driver Disabled
±10
IOFF
Power-Off Current
VCC = 0V, VIN or VOUT = 3.6V or 0V
±20
IOS
Short Circuit Output Current
VOUT = 0V, Driver Enabled
−10
VOUTx+ = 0V, VOUTx− = 0V, Driver Enabled
−10
µA
mA
LVDS Differential Receiver Characteristics
VTH
Differential Input Threshold HIGH
VIC = 0.05V or 1.2V or 3.25V
VTL
Differential Input Threshold LOW
VCC = 3.3V
VIC
Input Common Mode Voltage
IIND
Input Current (Differential Inputs)
100
−100
0.05
3.25
VIN = GND
±20
VIN = V CC
±20
mV
V
µA
LVTTL Control Characteristics
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Current
2
V
VIN = 3.6V or GND
0.8
V
±20
µA
±10
µA
Device Characteristics
VIK
Input Clamp Voltage
IPU/PD
Output Power-Up/Power-Down
High Z Leakage Current
IIK = −18 mA
−1.5
V
VCC = 0V to 1.5V
CIN
Input Capacitance
4.5
COUT
Output Capacitance
4.5
ICC
Power Supply Current
pF
pF
No Load, All Drivers Enabled
35
mA
RL = 75 Ω, All Drivers Enabled
35
mA
RL = 75 Ω, All Drivers Enabled
35
mA
Note 2: This part will only function with datasheet specification when a resistive load is applied to the driver outputs.
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.
3
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FIN1022
Absolute Maximum Ratings(Note 1)
FIN1022
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
tPLHD
tPHLD
Parameter
Test Conditions
Differential Output Propagation Delay
Min
Typ
Max
(Note 4)
0.7
LOW-to-HIGH
RL = 75 Ω, CL = 5 pF,
Differential Output Propagation Delay
VCC = 3.3V, TA = 25°C
0.7
HIGH-to-LOW
See Figure 4 and Figure 5
1.0
1.0
1.6
1.2
1.3
1.2
1.3
1.6
Units
ns
ns
tTLHD
Differential Output Rise Time (20% to 80%)
290
580
ps
tTHLD
Differential Output Fall Time (80% to 20%)
290
580
ps
tPLH
Selection Propagation Delay
LOW-to-HIGH (SELn to OUTn)
tPHL
tZHD
0.6
RL = 75 Ω, CL = 5 pF,
0.9
Selection Propagation Delay
VCC = 3.3V, TA = 25°C
0.6
HIGH-to-LOW (SELn to OUTn)
See Figure 6 and Figure 7
0.9
1.5
1.1
1.2
1.1
1.2
1.5
Differential Output Enable Time
from Z-to-HIGH
tZLD
tHZD
Differential Output Enable Time
from Z-to-LOW
RL = 75Ω, CL = 5 pF
Differential Output Disable Time
See Figure 8 and Figure 9
from HIGH-to-Z
tLZD
Differential Output Disable Time
from LOW-to-Z
tSET
Input (INn+/INn−) Setup Time to SELn
See Figure 10
0.5
0.3
tHOLD
Input (INn+/INn−) Hold Time to SELn
See Figure 10
0.5
0.3
tJIT
Output Peak-to-Peak Jitter
223 −1 PRBS Sequence at 800 Mbps
50% Duty Cycle at 800 Mbps
RL = 75 Ω, CL = 5 pF, See Figure 4
20
ns
ns
3.5
ns
3.5
ns
3.5
ns
3.5
ns
ns
ns
190
ps
35
ps
fTOG
Maximum Toggle Frequency
tSKEW
Within Device Channel-to-Channel Skew
35
80
ps
Pulse Skew |tPLHD -tPHLD|
0
225
ps
Part-to-Part Skew (Note 5)
100
500
ps
800
900
Mbps
Note 4: All typical values are at TA = 25°C and with VCC = 3.3V.
Note 5: Part-to-part skew is the maximum delay time difference on like edges (LOW-to-HIGH or HIGH-to-LOW) for the same VCC and temperature conditions.
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4
1. When the true and complement LVDS outputs (having
a 75Ω connected between outputs) are connected to
3.75 kΩ resistors and the common point of those 3.75
kΩ resistors are connected to a voltage source that
sweeps from 0 to 2.4V, the DC VOD and ∆VOD are still
maintained (see Figure 1).
3. Pull-down resistors are required on Enable (EN0 and
EN1) and select (SEL0 and SEL1) inputs.
4. Fail safe protection on the outputs that draw less than
20 µA of current (worst case) on the LVDS inputs. In
this condition, if the input is in fail safe selected to
OUT0+/OUT0− (say) and the outputs are Enabled then
OUT0+ = HIGH and OUT0− = LOW. This prevents noise
from being amplified when the connection is broken.
2. When the true and complement LVDS outputs (having
a 5 pF capacitor attached between outputs) are connected with 37.5Ω resistors each to common point,
then the common point does not vary by more than 150
mV under all process, temperature and voltage conditions when the outputs switch either from LOW-toHIGH or from HIGH-to-LOW (see Figure 2).
5. In the disabled state the outputs can go beyond VCC
but there should be no appreciable leakage (see IOZD
and IOFF specifications)
FIGURE 1. Common Mode Supply Test Circuit
FIGURE 2. Dynamic VOS Test Circuit and Waveforms
5
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FIN1022
Required Specifications
FIN1022
Required Specifications
(Continued)
Note A: All input pulses have frequency = 50 MHz, tR or tF = 500 ps
Note B: CL includes all probe and jig capacitances
FIGURE 3. LVDS Driver DC Test Circuit
FIGURE 4. LVDS Input to LVDS Driver Propagation
Delay and Transition Time Circuit
FIGURE 5. LVDS Input to LVDS Output AC Waveforms
FIGURE 6. LVTTL Input to LVDS Driver Propagation
Delay and Transition Time Test Circuit
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FIN1022
Required Specifications
(Continued)
Note A: All input pulses have frequency = 10MHz, tR or tF < = 1 ns.
Note B: CL includes all probe and jig capacitances.
FIGURE 7. LVTTL Input to LVDS Output AC Waveforms
FIGURE 8. Differential Driver Enable
and Disable Test Circuits
FIGURE 9. Enable and Disable AC Waveforms
7
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FIN1022
Required Specifications
(Continued)
FIGURE 10. Set-up and Hold Time Specification
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FIN1022
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
9
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FIN1022 2 X 2 LVDS High Speed Crosspoint Switch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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