Fairchild FIN1531 5v lvds 4-bit high speed differential driver Datasheet

Revised August 2001
FIN1531
5V LVDS 4-Bit High Speed Differential Driver
General Description
This quad driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates 5V TTL/CMOS signal levels to
LVDS levels with a typical differential output swing of 350
mV which provides low EMI at ultra low power dissipation
even at high frequencies. This device is ideal for high
speed transfer of clock and data.
The FIN1531 can be paired with its companion receiver,
the FIN1532, or with any other Fairchild LVDS receiver.
Features
■ Greater than 400Mbs data rate
■ 5V power supply operation
■ 400ps max differential pulse skew
■ 2.0ns maximum propagation delay
■ Low power dissipation
■ Power-Off protection
■ Meets or exceeds the TIA/EIA-644 LVDS standard
■ Pin compatible with equivalent RS-422 and
PECL devices
■ 16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number
Package Number
FIN1531M
M16A
FIN1531MTC
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Function Table
Connection Diagram
Input
Outputs
EN
EN
DIN
DOUT+
H
X
H
H
L
H
X
L
L
H
H
X
OPEN
L
H
X
L
H
H
L
X
L
L
L
H
X
L
OPEN
L
H
L
H
X
Z
Z
H = HIGH Logic Level
X = Don’t Care
DOUT−
L = LOW Logic Level
Z = High Impedance
Pin Descriptions
Pin Name
DIN1, DIN2, DIN3, DIN4
Description
5V TTL/CMOS Data Input
DOUT1+, DOUT2+, DOUT3+, DOUT4+ Non-inverting LVDS Output
DOUT1−, DOUT2−, DOUT3−, DOUT4− Inverting LVDS Output
© 2001 Fairchild Semiconductor Corporation
EN
Driver Enable Pin
EN
Inverting Driver Enable Pin
VCC
Power Supply
GND
Ground
DS500505
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FIN1531 5V LVDS 4-Bit High Speed Differential Driver
August 2001
FIN1531
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
−0.5V to +6V
Recommended Operating
Conditions
DC Input Voltage (VIN)
−0.5V to +6V
−0.5V to +6V
Supply Voltage (VCC)
DC Output Voltage (VOUT)
Driver Short Circuit Current (IOSD)
Storage Temperature Range (TSTG)
4.5V to 5.5V
Input Voltage (VIN)
Continuous
0 to VCC
−40°C to +85°C
Operating Temperature (TA)
−65°C to +150°C
150°C
Max Junction Temperature (TJ)
Lead Temperature (TL)
(Soldering, 10 seconds)
260°C
ESD (Human Body Model)
≥ 8000V
Note 1: The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
≥ 400V
ESD (Machine Model)
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
VOD
Output Differential Voltage
∆VOD
VOD Magnitude Change from
RL = 100Ω, driver enabled,
Differential LOW-to-HIGH
See Figure 1
VOS
Offset Voltage
∆VOS
Offset Magnitude Change from
Min
Typ
Max
(Note 2)
Units
250
350
450
mV
25
mV
1.125
1.25
1.375
V
25
mV
µA
Differential LOW-to-HIGH
IOFF
Power Off Output Current
VCC = 0V, VOUT = 5.5V
50
IOS
Short Circuit Output Current
VOUT = 0V, Driver Enabled
−6
VIH
Input HIGH Voltage
2.0
VCC
V
VIL
Input LOW Voltage
GND
0.8
V
IIN
Input Current
VIN = 0V or VCC
±20
µA
II(OFF)
Power-OFF Input Current
VCC = 0V, VIN = 5.5V
50
µA
IOZ
Disabled Output Leakage Current
EN = 0.8V, EN = 2.0V,
±20
µA
VOD = 0V, Driver Enabled
±6
VOUT = 0V or 7V
VIK
Input Clamp Voltage
IIK = −18 mA
ICC
Power Supply Current
No Load, VIN = 0V or VCC, Driver Enabled
3.3
RL = 100Ω, Driver Disabled
3.4
6
RL = 100Ω, VIN = 0V or VCC, Driver Enabled
18
26
CIN
Input Capacitance
COUT
Output Capacitance
−1.5
Note 2: All typical values are at TA = 25°C and with VCC = 5.0V.
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2
−0.8
mA
V
6
mA
7
pF
4.5
pF
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
tPLHD
Parameter
Test Conditions
Differential Propagation Delay
LOW-to-HIGH
tPHLD
Differential Propagation Delay
HIGH-to-LOW
RL = 100 Ω, CL = 10 pF,
Min
Typ
Max
(Note 3)
Units
0.5
1.4
2.0
ns
0.5
1.4
2.0
ns
tTLHD
Differential Output Rise Time (20% to 80%) See Figure 2 and Figure 3 (Note 7)
0.6
0.8
1.2
ns
tTHLD
Differential Output Fall Time (80% to 20%)
0.6
0.8
1.2
ns
0.4
ns
0.3
ns
tSK(P)
Pulse Skew |tPLH - tPHL|
tSK(LH),
Channel-to-Channel Skew
tSK(HL)
(Note 4)
tSK(PP)
Part-to-Part Skew (Note 5)
fMAX
Maximum Frequency(Note 6)
tZHD
LVTTL Output Enable Time from Z to HIGH RL = 100Ω, CL = 10 pF,
5.0
ns
tZLD
LVTTL Output Enable Time from Z to LOW See Figure 4 and Figure 5 (Note 7)
5.0
ns
tHZD
LVTTL Output Disable Time from HIGH to Z
5.0
ns
tLZD
LVTTL Output Disable Time from LOW to Z
5.0
ns
1.0
200
250
ns
ns
Note 3: All typical values are at TA = 25°C and with VCC = 5V.
Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction.
Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: fMAX Criteria: Input tR = tF < 1 ns, 0V to 3V, 50% Duty Cycle; Output VOD > 250 mV, 45% to 55% Duty Cycle; all output channels switching in phase.
Note 7: Test Circuits in Figure 2 and Figure 4 are simplified representations of test fixture and DUT loading.
3
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FIN1531
AC Electrical Characteristics
FIN1531
Note A: Input pulses have frequency = 10 MHz, tR or tF = 1 ns
Note B: C L includes all probe and jig capacitances
FIGURE 1. Differential Driver DC Test Circuit
FIGURE 2. Differential Driver Propagation Delay and
Transition Time Test Circuit
Note A: Input pulses have the following characteristics:
Frequency = 10 MHz, tR or tF = 1 ns
Note B: C L includes probes and jig capacitance
FIGURE 3. AC Waveforms
FIGURE 4. Differential Driver Enable and
Disable Test Circuit
FIGURE 5. Enable and Disable AC Waveforms
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FIN1531
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
5
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FIN1531 5V LVDS 4-Bit High Speed Differential Driver
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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6
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