Fairchild FL103M Primary-side-regulation pwm controller for led illumination Datasheet

FL103
Primary-Side-Regulation PWM Controller for
LED Illumination
Features
Description




Low Standby Power: < 30mW
This third-generation Primary-Side-Regulation (PSR)
and highly integrated PWM controller provides features
to enhance the performance of LED illumination.


Green-Mode: Linearly-Decreasing PWM Frequency









Peak-Current-Mode Control in CV Mode
High-Voltage Startup
Few External Component Counts
Constant-Voltage (CV) and Constant-Current (CC)
Control without Secondary-Feedback Circuitry
Fixed PWM Frequency at 50kHz and 33kHz with
Frequency Hopping to Solve EMI Problems
Cycle-by-Cycle Current Limiting
VDD Over-Voltage Protection (OVP)
The proprietary topology, TRUECURRENT™, enables
precise CC regulation and simplified circuit for LED
illumination applications. The result is lower-cost and
smaller LED lighting compared to a conventional design
or a linear transformer.
To minimize standby power consumption, the
proprietary green-mode function provides off-time
modulation to linearly decrease PWM frequency under
light-load conditions. Green mode assists the power
supply in meeting the power conservation requirements.
By using the FL103,
implemented with few
minimized cost.
VDD Under-Voltage Lockout (UVLO)
Adjustable Brownout Detector
LED illumination can be
external components and
Gate Output Maximum Voltage Clamped at 15V
Thermal Shutdown (TSD) Protection
Available in the 8-Lead SOIC Package
Application Voltage Range: 80VAC ~ 308VAC
Applications


Figure 1.
LED Illumination
8-Lead SOIC
Battery chargers for cellular phones, cordless
phones, PDA, digital cameras, power tools
Ordering Information
Part Number
Operating
Temperature Range
Top Mark
Package
Packing
Method
FL103M
-40°C to +125°C
FL103
8-Lead, Small-Outline Package (SOIC-8)
Tape & Reel
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
www.fairchildsemi.com
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
May 2012
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
Application Diagram
Figure 2.
Typical Application
Block Diagram
HV
8
VDD
Auto
Recovery
TSD
+
28V
S
Soft
Driver
2 GATE
Q
R
VDD
+
-
3
Max. Duty
VRESET
16V
/
7.5V
+
-
OSC
0.8V
1 CS
LEB
Peak
Detector
...
EAI
Pattern
Generator
+
X
TS
2.5V
TDIS
Slope
Compensation
VRESET
EAV
Protection:
OVP (Over-Voltage Protection)
UVLO (Under-Voltage Lockout)
TSD (Thermal Shutdown Protection)
+
-
2.5V
Sampling
& Holder
5 VS
6
GND
Figure 3.
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
Internal Block Diagram
www.fairchildsemi.com
2
F: Fairchild Logo
Z: Plant Code
X: 1-Digit Year Code
Y: 1-Digit Week Code
TT: 2-Digit Die Run Code
T: Package Type (M=SOP)
P: Y=Green Package
M: Manufacture Flow Code
ZXYTT
FL103
TPM
Figure 4.
Top Mark
Pin Configuration
Figure 5.
Pin Configuration
Pin Definitions
Pin #
Name
Description
1
CS
Current Sense. This pin connects a current-sense resistor to detect the MOSFET current
for peak-current-mode control in CV Mode and provides the output-current regulation in
CC Mode.
2
GATE
PWM Signal Output. This pin uses the internal totem-pole output driver to drive the power
MOSFET. It is internally clamped below 15V.
3
VDD
Power Supply. IC operating current and MOSFET driving current are supplied using this
pin. This pin is connected to an external VDD capacitor of typically 10µF. The threshold
voltages for startup and turn-off are 16V and 7.5V, respectively. The operating current is
lower than 5mA.
4
NC
No Connect. This pin is connected to GND or no connection. Does not connect any
voltage source.
5
VS
Voltage Sense. This pin detects the output voltage information and discharge time based
on voltage of auxiliary winding.
6
GND
7
NC
No Connect
8
HV
High Voltage. This pin connects to DC link capacitor for high-voltage startup. This pin is
connected to an external startup resistor of typically 100kΩ.
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
Marking Information
Ground
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VHV
Parameter
Min.
HV Pin Input Voltage
(1)
Max.
Unit
500
V
VVDD
DC Supply Voltage
30
V
VVS
VS Pin Input Voltage
-0.3
7.0
V
VCS
CS Pin Input Voltage
-0.3
7.0
V
PD
Power Dissipation (TA<50°C)
660
mW
+150
°C/W
39
°C/W
θJA
Thermal Resistance, (Junction-to-Air)
θJC
Thermal Resistance, (Junction-to-Case)
TJ
Junction Temperature
-40
+150
°C
Storage Temperature Range
-55
+150
°C
+260
°C
TSTG
TL
Lead Temperature (Wave Soldering or IR, 10 Seconds)
(2)
ESD
Electrostatic Discharge Capability
Human Body Model (Except HV Pin),
JEDEC-JESD22_A114
4.50
Charged Device Model (Except HV Pin),
JEDEC-ESD22_C101
1.25
kV
Note:
1. All voltage values, except differential voltages, are given with respect to GND pin.
2. All Pins: HBM =1500V, CDM =750V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
VDD
Continuous Operating Voltage
TA
Operation Ambient Temperature
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
Min.
-40
Typ.
Max.
Unit
25
V
+125
°C
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
Absolute Maximum Ratings
www.fairchildsemi.com
4
Unless otherwise specified, VDD=15V and TA=25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDD Section
VDD-ON
Turn-On Threshold Voltage
15
16
17
V
VDD-OFF
Turn-Off Threshold Voltage
7.0
7.5
8.0
V
3.2
5.0
mA
IDD-OP
Operating Current
IDD-GREEN
Green Mode Operating Supply Current
0.95
1.20
mA
VDD-OVP
VDD Over-Voltage Protection Level
27
28
29
V
tD-VDDOVP
VDD OVP Debounce Time
90
200
350
µs
50
V
2.0
5.0
mA
0.5
3.0
µA
47
50
53
±1.5
±2.0
±2.5
High Voltage (HV) Section
VHV-MIN
Minimum Startup Voltage on HV Pin
IHV
Supply Current Drawn from Pin HV
VDL=100V
Leakage Current after Startup
HV=500V,
VDD=VDD-OFF +1V
IHV-LC
1.5
Oscillator Section
fOSC
VF-JUM-53
VF-JUM-35
Normal
Frequency
Center Frequency
Frequency Hopping Range
> VO * 0.5
33
Center Frequency
Protection
< VO * 0.5
(3)
Frequency Frequency Hopping Range
Frequency Jumping Point
fOSC-N-MIN
Minimum Frequency at No-Load
fOSC-CM-MIN
Minimum Frequency at CCM
kHz
±1.3
50kHz  33kHz, VS
1.05
1.25
1.55
V
33kHz  50kHz, VS
1.28
1.50
1.75
V
300
450
600
Hz
7
12
17
kHz
1
2
%
15
%
2.525
V
fDV
Frequency Variation vs. VDD Deviation
VDD=10~25V
fDT
Frequency Variation vs. Temperature
Deviation
TA=-40°C to +105°C
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
Electrical Characteristics
Voltage Sense (VS) Section
VR
Reference Voltage for Error AMPs
VN
Green-Mode Starting Voltage on EAV
fOSC=2kHz
2.5
V
VG
Green-Mode Ending Voltage on EAV(3)
fOSC=1kHz
0.5
V
Adaptive Bias Voltage Dominated by
VCOMV
RVS=20kΩ
1.4
V
VBIAS-COMV
Itc
IVS-BO
2.475
IC Bias Current
7.3
(3)
Brownout Detection Current
2.500
10.0
12.7
175
(3)
IVS-MIN
Minimum VS Current
IVS-MAX
Maximum VS Current(3)
tDIS_MIN
Normal Operation
Minimum
Discharging Time Protection Area
(3)
µA
µA
90VAC, Heavy Load
227
µA
264VAC, No Load
721
µA
fOSC=50kHz
0.65
fOSC=33kHz
2.0
2.6
4.0
µs
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
www.fairchildsemi.com
5
Unless otherwise specified, VDD=15V and TA=25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
90
200
ns
800
975
1150
ns
0.75
0.80
0.85
V
Current Sense (CS) Section
tPD
tMIN-N
Propagation Delay to GATE Output
Minimum On Time at No-Load
VTH
Threshold Voltage for Current Limit
VTL
Threshold Voltage on VS Pin Smaller
than 0.5V
VCOMR=1V
0.25
V
GATE Section
DCYMAX
Maximum Duty Cycle
60
75
85
%
1.5
V
VOL
Output Voltage Low
VDD=20V,
Gate Sinks 10mA
VOH
Output Voltage High
VDD=8V,
Gate Sources 1mA
tr
Rising Time
CL=1nF
200
250
ns
tf
Falling Time
CL=1nF
60
100
ns
Output Clamp Voltage
VDD=25V
15
18
V
VCLAMP
5
V
Thermal Shutdown (TSD) Section
TSD
TSDHYS
Thermal Shutdown Temperature(3)
Thermal Shutdown Hysteresis
+140
(3)
-
Note:
3. These parameters, although guaranteed, are not 100% tested in production.
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
°C
+15
°C
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
Electrical Characteristics (Continued)
www.fairchildsemi.com
6
8.0
16.6
7.8
16.2
VDD-OFF [V]
VDD-ON [V]
17.0
15.8
15.4
7.6
7.4
7.2
15.0
7.0
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
Temperature [℃]
Figure 6.
20
35
50
65
80
95
110
125
110
125
Temperature [℃]
VDD-ON vs. Temperature
Figure 7.
5
56
4
54
VDD-OFF vs. Temperature
fOSC[kHz]
IDD-OP [mA]
52
3
2
1
50
48
46
0
44
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
Temperature [℃]
IDD-OP vs. Temperature
Figure 9.
2.525
1.20
2.515
1.12
2.505
1.04
IDD-GREEN[mA]
VR[V]
Figure 8.
20
35
50
65
80
95
Temperature [℃]
2.495
2.485
fOSC vs. Temperature
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
Typical Performance Characteristics
0.96
0.88
2.475
0.80
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
Figure 10.
VR vs. Temperature
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
5
20
35
50
65
80
95
110
125
Temperature [℃]
Temperature [℃]
Figure 11.
IDD-GREEN vs. Temperature
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7
16
420
15
fOSC-CM-MIN[kHz]
fOSC-N-MIN[Hz]
450
390
360
330
14
13
12
11
300
10
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
Temperature [℃]
Figure 12.
35
50
65
80
95
110
125
Temperature [℃]
fOSC-N-MIN vs. Temperature
Figure 13.
3.5
fOSC-CM-MIN vs. Temperature
1150
1100
2.8
TMIN-N[ns]
IHV[mA]
1050
2.1
1.4
1000
950
900
0.7
850
0.0
800
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
Temperature [℃]
IHV vs. Temperature
12.0
18.0
11.2
17.2
10.4
16.4
VCLAMP[V]
Itc[uA]
Figure 14.
20
35
50
65
80
95
110
125
Temperature [℃]
9.6
8.8
Figure 15.
tMIN-N vs. Temperature
-25
20
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
Typical Performance Characteristics (Continued)
15.6
14.8
8.0
14.0
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-10
5
Temperature [℃]
Figure 16.
50
65
80
95
110
125
Temperature [℃]
Itc vs. Temperature
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
35
Figure 17.
VCLAMP vs. Temperature
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8
1.45
1.70
1.62
VF-JUM-HYS[V]
VF-JUM[V]
1.37
1.29
1.21
1.13
1.54
1.46
1.38
1.05
-40
-25
-10
5
20
35
50
65
80
95
110
1.30
125
-40
-25
-10
Temperature [℃]
Figure 18.
20
35
50
65
80
95
Temperature [℃]
VF-JUM vs. Temperature
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
5
Figure 19.
VF-JUM-HYS vs. Temperature
110
125
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
Typical Performance Characteristics (Continued)
www.fairchildsemi.com
9
Figure 20.
Basic Circuit of a PSR Flyback Converter for LED Illumination
The operation principles of DCM flyback converter are
as follows:
Figure 20 shows the basic circuit diagram of a primaryside regulated flyback converter with typical waveforms
shown in Figure 21. Generally, Discontinuous
Conduction Mode (DCM) operation is preferred for
primary-side regulation since it allows better output
regulation.
I
PK
×
N
N
Stage I
During the MOSFET on time (tON), input voltage (VDC) is
applied across the primary-side inductor (Lm). Then
MOSFET current (IDS) increases linearly from zero to the
peak value (IPK). During this time, the energy is drawn
from the input and stored in the inductor.
Stage II
When the MOSFET (Q1) is turned off, the energy stored
in the inductor forces the rectifier diode (DF) to be turned
on. While the diode is conducting, the output voltage
(VO), together with diode forward-voltage drop (VF), is
applied across the secondary-side inductor and the
diode current (IF) decreases linearly from the peak value
(IPK × NP/NS) to zero. At the end of inductor current
discharge time (tDIS), all the energy stored in the
inductor has been delivered to the output.
P
S
Stage III
When the diode current reaches zero, the transformer
auxiliary winding voltage (VA) begins to oscillate by the
resonance between the primary-side inductor (Lm) and
the effective capacitor loaded across MOSFET (Q1).
N
VF × A
NS
VO ×
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
Functional Description
NA
NS
Constant Voltage Regulation
Figure 21.
During the inductor current discharge time (tDIS), the
sum of output voltage (VO) and diode forward-voltage
drop (VF) is reflected to the auxiliary winding side as
(VO+VF) × NA/NS. Since the diode forward-voltage drop
(VF) decreases as current decreases, the auxiliary
winding voltage (VA) reflects the output voltage (VO) at
the end of diode conduction time (tDIS), where the diode
current (IF) diminishes to zero. By sampling the winding
Waveforms of DCM Flyback Converter
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
www.fairchildsemi.com
10
Frequency Hopping
EMI reduction is accomplished by frequency hopping,
which spreads the energy over a wider frequency range
than the bandwidth measured by the EMI test
equipment. FL103 has an internal frequency hopping
circuit that changes the switching frequency between
47kHz and 53kHz.
Constant Current Regulation
High-Voltage Startup
The output current (IO) can be estimated using the peak
drain current (IPK) and inductor current discharge time
(tDIS) since output current (IO) is same as the average of
the diode current (IF_AVG) in steady state. The output
current estimator (IO Estimator) determines the peak
value of the drain current with a peak detection circuit
and calculates the output current (IO) using the inductor
discharge time (tDIS) and switching period (tS). This
output information is compared with an internal precise
reference to generate error voltage (VCOMI), which
determines the duty cycle of the MOSFET (Q1) in
Constant Current Mode. With Fairchild’s innovative
technique TRUECURRENT™, constant current output
can be precisely controlled.
Figure 23 shows the startup block. The HV pin is
connected to the line input or DC link capacitor (CDC).
During startup, the internal startup circuit is enabled.
Meanwhile, line input supplies the current (IStart) to
charge the VDD capacitor (CVDD). When the VDD voltage
reaches VDD-ON (16V) and VDC is enough high to avoid
brownout, the internal startup circuit is disabled,
blocking IStart from flowing into the HV pin. Once the IC
turns on, CVDD is the only energy source to supply the IC
consumption current before the PWM starts to switch.
Thus, CVDD must be large enough to prevent VDD-OFF
(7.5V) before the power can be delivered from the
auxiliary winding. To avoid the surge from input source,
the RStart is connected between CDC and HV, with a
recommended value of 100kΩ.
Voltage and Current Error Amplifier
Of the two error voltages, VCOMV and VCOMI, the small
one determines the duty cycle. Therefore, during
Constant Voltage Regulation Mode, VCOMV determines
the duty cycle while VCOMI is saturated to HIGH. During
Constant Current Regulation Mode, VCOMI determines
the duty cycle while VCOMV is saturated to HIGH.
Operating Current
The operating current is typically 3.2mA. The small
operating current results in higher efficiency and
reduces the VDD capacitor (CVDD) requirement. Once
FL103 enters Green Mode, the operating current is
reduced to 0.95mA, assisting the power supply in
meeting power conservation requirements.
Figure 23.
Startup Block
Protections
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
voltage at the end of the diode conduction time (tDIS),
the output voltage (VO) information can be obtained. The
internal error amplifier for output voltage regulation
(EAV) compares the sampled voltage with an internal
precise reference to generate error voltage (VCOMV),
which determines the duty cycle of the MOSFET (Q1) in
Constant Voltage Mode.
The FL103 has several self-protection functions; overvoltage protection, thermal shutdown protection,
brownout protection, and pulse-by-pulse current limit.
Green Mode Operation
The FL103 uses voltage regulation error amplifier output
(VCOMV) as an indicator of the output load and modulates
the PWM frequency, as shown in Figure 22. The
switching frequency decreases as load decreases. In
heavy load conditions, the switching frequency is fixed
at 50kHz. Once VCOMV decreases below 2.5V, the PWM
frequency linearly decreases from 50kHz. When FL103
enters into green load, the PWM frequency is reduced
to a minimum frequency of 370Hz., gaining power
saving power to help meet international power
conservation requirements.
VDD Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
16V and 7.5V, respectively. During startup, the VDD
capacitor (CVDD) must be charged to 16V. The VDD
capacitor (CVDD) continues to supply VDD until power can
be delivered from the auxiliary winding of the main
transformer. VDD is not allowed to drop below 7.5V
during this startup process. This UVLO hysteresis
window ensures that VDD capacitor (CVDD) properly
supplies VDD during startup.
VDD Over-Voltage Protection (OVP)
The OVP prevents damage from over-voltage
conditions. If the VDD voltage exceeds 28V at open-loop
feedback condition, the OVP is triggered and the PWM
switching is disabled. The OVP has a debounce time
(typically 200µs) to prevent false triggering due to
switching noises.
Figure 22.
Thermal Shutdown Protection (TSD)
The built-in temperature-sensing circuit shuts down
PWM output if the junction temperature exceeds 140°C.
There is a hysteresis of 15°C.
Switching Frequency as Output Load
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
www.fairchildsemi.com
11
Noise from the current sense or the control signal can
cause significant pulse-width jitter, particularly in
Continuous-Conduction
Mode.
While
slope
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoiding long PCB
traces and component leads, locating compensation
and filter components near the FL103, and increasing
the power MOSFET gate resistance are advised.
Leading-Edge Blanking (LEB)
Each time the power MOSFET (Q1) switches on, a turnon spike occurs at the sense resistor (RSense). To avoid
premature termination of the switching pulse, a leadingedge blanking time is built in. Conventional RC filtering
can be omitted. During this blanking period, the currentlimit comparator is disabled and cannot switch off the
gate driver.
Operation Area
Figure 24 shows operation area. FL103 has two
switching frequency (fS) in Constant Current Mode. One
is 50kHz. In this case, FL103 can be operated with best
condition for LED illumination. The output voltage range
N
is between normal output voltage (VO ) and 50% of
N
normal output voltage (VO ). The other is 33kHz. When
the output voltage is dropped, by increased load and
decreasing the number of LEDs, the output voltage (VO)
N
drops under 50% of normal voltage (VO ). At that time,
VDD drops to near UVLO protection and triggers
N
protection. To avoid 33kHz, VO should be designed
with enough margin.
Gate Output
The FL103 output stage is a fast totem-pole gate driver.
Cross conduction has been avoided to minimize heat
dissipation, increase efficiency, and enhance reliability.
The output driver is clamped by an internal 15V Zener
diode to protect power MOSFET transistors against
undesired over-voltage gate signals.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for Current Mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
peak-current mode control. The FL103 has a
synchronized, positive-slope ramp built-in at each
switching cycle.
Figure 24.
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
Noise Immunity
Pulse-by-Pulse Current Limit
When the current sensing voltage (VCS) across the
current-sense resistor (RSense) of MOSFET (Q1)
exceeds the internal threshold of 0.8V, the MOSFET
(Q1) is turned off for the remainder of switching cycle. In
normal operation, the pulse-by-pulse current limit is not
triggered because the peak current is limited by the
control loop.
Operation Area
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12
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
Physical Dimensions
5.00
4.80
A
0.65
3.81
5
8
B
6.20
5.80
PIN ONE
INDICATOR
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
0.25
0.10
SEE DETAIL A
1.75 MAX
R0.10
0.10
0.51
0.33
0.50 x 45°
0.25
C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
8°
0°
0.90
0.406
0.25
0.19
C
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 25.
8-Lead, Small Outline Package (SOIC-8)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
www.fairchildsemi.com
13
FL103 — Primary-Side-Regulation PWM Controller for LED Illumination
© 2012 Fairchild Semiconductor Corporation
FL103 • Rev. 1.0.1
www.fairchildsemi.com
14
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