FPD3000 2W POWER PHEMT • FEATURES ♦ 32.5 dBm Linear Output Power at 12 GHz ♦ 6.5 dB Power Gain at 12 GHz ♦ 8 dB Maximum Stable Gain at 12 GHz ♦ 42 dBm Output IP3 ♦ 30% Power-Added Efficiency DRAIN BOND PAD (4X) SOURCE BOND PAD (2x) GATE BOND PAD (4X) • DESCRIPTION AND APPLICATIONS DIE SIZE (µm): 830 x 470 DIE THICKNESS: 75 µm BONDING PADS (µm): >75 x 60 The FPD3000 is an AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (PHEMT), featuring a 0.25 µm by 3000 µm Schottky barrier gate, defined by high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance. The epitaxial structure and processing have been optimized for reliable high-power applications. The FPD3000 also features Si3N4 passivation and is available in a P100 flanged ceramic package and in the low cost plastic SOT89 plastic package. Typical applications include commercial and other narrowband and broadband high-performance amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output amplifiers, and medium-haul digital radio transmitters. • ELECTRICAL SPECIFICATIONS AT 22°C Parameter Symbol Test Conditions Min Typ Max Units RF SPECIFICATIONS MEASURED AT f = 12 GHz USING CW SIGNAL Power at 1dB Gain Compression P1dB VDS = 8 V; IDS = 50% IDSS 31.5 32.5 dBm Maximum Stable Gain (S21/S12) SSG VDS = 8 V; IDS = 50% IDSS 7.0 8.0 dB Power Gain at P1dB G1dB VDS = 8 V; IDS = 50% IDSS 6.0 6.5 dB Power-Added Efficiency PAE VDS = 8 V; IDS = 50% IDSS; POUT = P1dB 30 % Output Third-Order Intercept Point IP3 VDS = 8V; IDS = 50% IDSS Matched for optimal power 42 dBm Tuned for best IP3 44 (from 15 to 5 dB below P1dB) Saturated Drain-Source Current IDSS VDS = 1.3 V; VGS = 0 V Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 1.5 A Transconductance GM VDS = 1.3 V; VGS = 0 V 800 mS Gate-Source Leakage Current IGSO VGS = -5 V 10 µA Pinch-Off Voltage |VP| VDS = 1.3 V; IDS = 3 mA 1.0 V Gate-Source Breakdown Voltage |VBDGS| IGS = 3 mA 12.0 14.0 V Gate-Drain Breakdown Voltage |VBDGD| IGD = 3 mA 14.5 16.0 V Thermal Resistivity (see Notes) θJC VDS > 6V 20 °C/W Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis 750 930 1100 mA Revised: 11/17/04 Email: [email protected] FPD3000 2W POWER PHEMT • ABSOLUTE MAXIMUM RATINGS1 Parameter Symbol Test Conditions Drain-Source Voltage VDS Gate-Source Voltage Max Units -3V < VGS < +0V 8 V VGS 0V < VDS < +8V -3 V Drain-Source Current IDS For VDS > 2V IDSS mA Gate Current IG Forward or reverse current 25 mA PIN Under any acceptable bias state 600 mW Channel Operating Temperature TCH Under any acceptable bias state 175 ºC Storage Temperature TSTG Non-Operating Storage 150 ºC Total Power Dissipation PTOT See De-Rating Note below 7.3 W Comp. Under any bias conditions 5 dB 2 or more Max. Limits 80 % RF Input Power 2 Gain Compression 3 Simultaneous Combination of Limits 1 3 TAmbient = 22°C unless otherwise noted Min -40 2 Max. RF Input Limit must be further limited if input VSWR > 2.5:1 Users should avoid exceeding 80% of 2 or more Limits simultaneously Notes: • Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device. • Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib. • Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power • Absolute Maximum Power Dissipation to be de-rated as follows above 22°C: PTOT= 7.3W – (0.05W/°C) x THS where THS = heatsink or ambient temperature above 22°C Example: For a 85°C heatsink temperature: PTOT = 7.3W – (0.05 x (85 – 22)) = 4.2W • HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. • ASSEMBLY INSTRUCTIONS The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280-290°C; maximum time at temperature is one minute. The recommended wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm) gold wire. Stage temperature should be 250-260°C. • APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. All information and specifications are subject to change without notice. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised: 11/17/04 Email: [email protected]