Fairchild FQP4N80 800v n-channel mosfet Datasheet

FQP4N80
September 2000
QFET
TM
FQP4N80
800V N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supply.
•
•
•
•
•
•
3.9A, 800V, RDS(on) = 3.6Ω @VGS = 10 V
Low gate charge ( typical 19 nC)
Low Crss ( typical 8.6 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
D
!
"
G!
G DS
ID
!
FQP Series
S
TC = 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
- Continuous (TC = 100°C)
IDM
Drain Current
"
"
TO-220
Absolute Maximum Ratings
Symbol
VDSS
3 5
- Pulsed
(Note 1)
FQP4N80
800
Units
V
3.9
A
2.47
A
15.6
A
VGSS
Gate-Source Voltage
± 30
V
EAS
Single Pulsed Avalanche Energy
(Note 2)
460
mJ
IAR
Avalanche Current
(Note 1)
3.9
A
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
(Note 1)
13
4.0
130
1.04
-55 to +150
mJ
V/ns
W
W/°C
°C
300
°C
dv/dt
PD
TJ, TSTG
TL
(Note 3)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
Typ
--
RθCS
Thermal Resistance, Case-to-Sink
0.5
--
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
--
62.5
°C/W
©2000 Fairchild Semiconductor International
Max
0.96
Units
°C/W
Rev. A, September 2000
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
800
--
--
V
--
0.95
--
V/°C
VDS = 800 V, VGS = 0 V
--
--
10
µA
VDS = 640 V, TC = 125°C
--
--
100
µA
Gate-Body Leakage Current, Forward
VGS = 30 V, VDS = 0 V
--
--
100
nA
Gate-Body Leakage Current, Reverse
VGS = -30 V, VDS = 0 V
--
--
-100
nA
3.0
--
5.0
V
--
2.8
3.6
Ω
--
3.8
--
S
--
680
880
pF
--
75
100
pF
--
8.6
12
pF
--
16
40
ns
--
45
100
ns
--
35
80
ns
--
35
80
ns
--
19
25
nC
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = 250 µA, Referenced to 25°C
IDSS
IGSSF
IGSSR
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static Drain-Source
On-Resistance
VGS = 10 V, ID = 1.95 A
gFS
Forward Transconductance
VDS = 50 V, ID = 1.95 A
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 400 V, ID = 3.9 A,
RG = 25 Ω
(Note 4, 5)
VDS = 640 V, ID = 3.9 A,
VGS = 10 V
(Note 4, 5)
--
4.2
--
nC
--
9.1
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
3.9
A
ISM
--
--
15.6
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = 3.9 A
Drain-Source Diode Forward Voltage
--
--
1.4
V
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 3.9 A,
dIF / dt = 100 A/µs
(Note 4)
--
575
--
ns
--
3.65
--
µC
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 57mH, IAS = 3.9A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 3.9A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A, September 2000
FQP4N80
Electrical Characteristics
VGS
15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
Bottom : 5.5 V
1
Top :
0
10
1
10
ID, Drain Current [A]
ID, Drain Current [A]
10
-1
10
o
150 C
0
10
o
25 C
o
-55 C
※ Notes :
1. 250μs Pulse Test
2. TC = 25℃
※ Notes :
1. VDS = 50V
2. 250μs Pulse Test
-2
-1
10
-1
0
10
10
1
10
2
10
4
6
8
10
VGS, Gate-Source Voltage [V]
VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
7
1
10
VGS = 10V
5
IDR , Reverse Drain Current [A]
RDS(ON) [Ω ],
Drain-Source On-Resistance
6
VGS = 20V
4
3
※ Note : TJ = 25℃
0
10
25℃
150℃
※ Notes :
1. VGS = 0V
2. 250μs Pulse Test
-1
2
0
2
4
6
8
10
10
0.2
0.4
0.6
0.8
1.0
1.2
ID, Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
1200
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
Ciss
800
600
Coss
※ Notes :
1. VGS = 0 V
2. f = 1 MHz
400
Crss
200
VDS = 160V
10
VGS, Gate-Source Voltage [V]
1000
Capacitance [pF]
FQP4N80
Typical Characteristics
VDS = 400V
VDS = 640V
8
6
4
2
※ Note : ID = 3.9A
0
-1
10
0
0
10
1
10
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2000 Fairchild Semiconductor International
0
4
8
12
16
20
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A, September 2000
FQP4N80
Typical Characteristics
(Continued)
3.0
1.2
RDS(ON) , (Normalized)
Drain-Source On-Resistance
BV DSS , (Normalized)
Drain-Source Breakdown Voltage
2.5
1.1
1.0
※ Notes :
1. VGS = 0 V
2. ID = 250 μA
0.9
0.8
-100
-50
0
50
100
150
2.0
1.5
1.0
※ Notes :
1. VGS = 10 V
2. ID = 1.95 A
0.5
0.0
-100
200
-50
o
0
50
100
150
200
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
4
Operation in This Area
is Limited by R DS(on)
1
100μs
3
1 ms
ID, Drain Current [A]
ID, Drain Current [A]
10
10 ms
DC
0
10
-1
10
※ Notes :
2
1
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
-2
10
0
10
1
2
10
0
25
3
10
10
50
100
125
150
Figure 10. Maximum Drain Current
vs. Case Temperature
0
D = 0 .5
※ N o te s :
1 . Z θ J C ( t) = 0 .9 6 ℃ / W M a x .
2 . D u ty F a c to r , D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C ( t)
0 .2
10
0 .1
-1
0 .0 5
PDM
0 .0 2
θ JC
( t) , T h e r m a l R e s p o n s e
Figure 9. Maximum Safe Operating Area
10
75
TC, Case Temperature [℃]
VDS, Drain-Source Voltage [V]
0 .0 1
t1
t2
Z
s i n g le p u ls e
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A, September 2000
FQP4N80
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50KΩ
Qg
200nF
12V
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
VDS
90%
VDD
VGS
RG
VGS
DUT
10V
10%
td(on)
tr
td(off)
t on
tf
t off
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
BVDSS
IAS
ID
RG
VDD
DUT
10V
tp
©2000 Fairchild Semiconductor International
ID (t)
VDS (t)
VDD
tp
Time
Rev. A, September 2000
FQP4N80
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
Same Type
as DUT
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
I SD
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
VSD
VDD
Body Diode
Forward Voltage Drop
©2000 Fairchild Semiconductor International
Rev. A, September 2000
TO-220
4.50 ±0.20
2.80 ±0.10
(3.00)
+0.10
1.30 –0.05
18.95MAX.
(3.70)
ø3.60 ±0.10
15.90 ±0.20
1.30 ±0.10
(8.70)
(1.46)
9.20 ±0.20
(1.70)
9.90 ±0.20
1.27 ±0.10
1.52 ±0.10
0.80 ±0.10
2.54TYP
[2.54 ±0.20]
10.08 ±0.30
(1.00)
)
(45°
13.08 ±0.20
FQP4N80
Package Dimensions
+0.10
0.50 –0.05
2.40 ±0.20
2.54TYP
[2.54 ±0.20]
10.00 ±0.20
©2000 Fairchild Semiconductor International
Rev. A, September 2000
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Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
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First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
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This datasheet contains final specifications. Fairchild
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The datasheet is printed for reference information only.
©2000 Fairchild Semiconductor International
Rev. F1
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