Fairchild FQPF12P20YDTU 200v p-channel mosfet Datasheet

FQPF12P20
May 2000
QFET
TM
FQPF12P20
200V P-Channel MOSFET
General Description
Features
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters.
•
•
•
•
•
•
-7.3A, -200V, RDS(on) = 0.47Ω @VGS = -10 V
Low gate charge ( typical 31 nC)
Low Crss ( typical 30 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
S
!
●
●
G!
▶ ▲
●
GD S
Absolute Maximum Ratings
Symbol
VDSS
ID
TO-220F
!
FQPF Series
D
TC = 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
- Continuous (TC = 100°C)
IDM
Drain Current
VGSS
Gate-Source Voltage
EAS
Single Pulsed Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
dv/dt
PD
TJ, TSTG
TL
- Pulsed
FQPF12P20
-200
Units
V
-7.3
A
-4.6
A
-29.2
A
± 30
V
(Note 2)
810
mJ
(Note 1)
-7.3
A
(Note 1)
5.0
-5.5
50
0.4
-55 to +150
mJ
V/ns
W
W/°C
°C
300
°C
(Note 1)
(Note 3)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
RθJA
Thermal Resistance, Junction-to-Ambient
©2000 Fairchild Semiconductor International
Typ
--
Max
2.5
Units
°C/W
--
62.5
°C/W
Rev. B, May 2000
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
-200
--
--
V
--
-
--
V/°C
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = -250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = -250 µA, Referenced to 25°C
IDSS
IGSSF
IGSSR
VDS = -200 V, VGS = 0 V
--
--
-1
µA
VDS = -160 V, TC = 125°C
--
--
-10
µA
Gate-Body Leakage Current, Forward
VGS = -30 V, VDS = 0 V
--
--
-100
nA
Gate-Body Leakage Current, Reverse
VGS = 30 V, VDS = 0 V
--
--
100
nA
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
-3.0
--
-5.0
V
RDS(on)
Static Drain-Source
On-Resistance
VGS = -10 V, ID = -3.65 A
--
0.36
0.47
Ω
gFS
Forward Transconductance
VDS = -40 V, ID = -3.65 A
--
5.6
--
S
--
920
1200
pF
--
190
250
pF
--
30
40
pF
ns
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = -25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = -100 V, ID = -11.5 A,
RG = 25 Ω
(Note 4, 5)
VDS = -160 V, ID = -11.5 A,
VGS = -10 V
(Note 4, 5)
--
20
50
--
195
400
ns
--
40
90
ns
--
60
130
ns
--
31
40
nC
--
8.1
--
nC
--
16
--
nC
A
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
-7.3
ISM
--
--
-29.2
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = -7.3 A
Drain-Source Diode Forward Voltage
--
--
-5.0
V
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = -11.5 A,
dIF / dt = 100 A/µs
(Note 4)
--
180
--
ns
--
1.44
--
µC
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 22.8mH, IAS = -7.3A, VDD = -50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ -11.5A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. B, May 2000
FQPF12P20
Elerical Characteristics
VGS
-15.0 V
-10.0 V
-8.0 V
-7.0 V
-6.5 V
-6.0 V
Bottom : -5.5 V
Top :
-I D, Drain Current [A]
1
10
-I D , Drain Current [A]
1
10
0
10
※ Notes :
1. 250μs Pulse Test
2. TC = 25℃
150℃
0
10
25℃
※ Notes :
1. VDS = -40V
2. 250μs Pulse Test
-55℃
-1
-1
10
-1
0
10
10
1
10
2
10
4
6
8
10
-VGS , Gate-Source Voltage [V]
-VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
2.0
10
1.5
-I DR , Reverse Drain Current [A]
RDS(on) [ Ω ],
Drain-Source On-Resistance
1
VGS = - 10V
VGS = - 20V
1.0
0.5
※ Note : TJ = 25℃
0
10
150℃
※ Notes :
1. VGS = 0V
2. 250μs Pulse Test
25℃
-1
0.0
0
10
20
30
10
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-ID , Drain Current [A]
-VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
2400
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
1600
※ Notes :
1. VGS = 0 V
2. f = 1 MHz
Ciss
Coss
1200
800
Crss
400
0
-1
10
VDS = -40V
10
-V GS , Gate-Source Voltage [V]
2000
Capacitance [pF]
FQPF12P20
Typical Characteristics
VDS = -100V
VDS = -160V
8
6
4
2
※ Note : ID = -11.5 A
0
0
10
1
10
-VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2000 Fairchild Semiconductor International
0
5
10
15
20
25
30
35
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. B, May 2000
(Continued)
2.5
1.2
2.0
1.1
RDS(ON) , (Normalized)
Drain-Source On-Resistance
-BV DSS , (Normalized)
Drain-Source Breakdown Voltage
FQPF12P20
Typical Characteristics
1.0
※ Notes :
1. VGS = 0 V
2. ID = -250 μA
0.9
0.8
-100
-50
0
50
100
150
1.5
1.0
※ Notes :
1. VGS = -10 V
2. ID = -5.75 A
0.5
0.0
-100
200
-50
0
o
50
100
150
200
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
8
Operation in This Area
is Limited by R DS(on)
2
6
1 ms 100 µs
1
10
-I D, Drain Current [A]
-I D, Drain Current [A]
10
10 ms
100 ms
DC
0
10
※ Notes :
-1
10
4
2
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
-2
10
0
1
10
0
25
2
10
10
50
100
125
150
Figure 10. Maximum Drain Current
vs. Case Temperature
D = 0 .5
0
0 .2
※ N o te s :
1 . Z θ J C ( t ) = 2 . 5 ℃ /W M a x .
2 . D u ty F a c t o r , D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C( t )
0 .1
0 .0 5
10
-1
0 .0 2
θ JC
( t) , T h e r m a l R e s p o n s e
Figure 9. Maximum Safe Operating Area
10
75
TC, Case Temperature [℃]
-VDS, Drain-Source Voltage [V]
PDM
0 .0 1
t1
Z
t2
s in g le p u ls e
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. B, May 2000
FQPF12P20
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50KΩ
Qg
200nF
12V
-10V
300nF
VDS
VGS
Qgs
Qgd
DUT
-3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
t on
VDD
VGS
RG
td(on)
VGS
t off
tr
td(off)
tf
10%
DUT
-10V
VDS
90%
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
tp
ID
RG
VDD
DUT
-10V
tp
©2000 Fairchild Semiconductor International
VDD
Time
VDS (t)
ID (t)
IAS
BVDSS
Rev. B, May 2000
FQPF12P20
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
VDS
DUT
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
I SD
( DUT )
Compliment of DUT
(N-Channel)
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
Body Diode Reverse Current
IRM
di/dt
IFM , Body Diode Forward Current
VDS
( DUT )
VSD
Body Diode
Forward Voltage Drop
VDD
Body Diode Recovery dv/dt
©2000 Fairchild Semiconductor International
Rev. B, May 2000
3.30 ±0.10
TO-220F
10.16 ±0.20
2.54 ±0.20
ø3.18 ±0.10
(7.00)
(1.00x45°)
15.87 ±0.20
15.80 ±0.20
6.68 ±0.20
(0.70)
MAX1.47
0.80 ±0.10
)
0°
(3
9.75 ±0.30
0.35 ±0.10
#1
+0.10
0.50 –0.05
2.54TYP
[2.54 ±0.20]
2.54TYP
[2.54 ±0.20]
9.40 ±0.20
©2000 Fairchild Semiconductor International
2.76 ±0.20
4.70 ±0.20
FQPF12P20
Package Dimensions
Rev. B, May 2000
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Advance Information
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In Design
This datasheet contains the design specifications for
product development. Specifications may change in
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First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
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changes at any time without notice in order to improve
design.
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Rev. G
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