Fairchild FQPF3P20 Qfet p-channel Datasheet

QFET P-CHANNEL
FQPF3P20
FEATURES
BVDSS = −200V
•
Advanced New Design
•
Avalanche Rugged Technology
•
Rugged Gate Oxide Technology
•
Very Low Intrinsic Capacitances
•
Excellent Switching Characteristics
•
Unrivalled Gate Charge: 6.0nC (Typ.)
•
Extended Safe Operating Area
•
Lower RDS(ON): 2.06Ω (Typ.)
RDS(ON) = 2.7Ω
ID = −2.2A
TO-220F
1
2
3
1. Gate 2. Drain 3. Source
ABSOLUTE MAXIMUM RATINGS
Symbol
VDSS
ID
Characteristics
Value
Units
Drain-to-Source Voltage
−200
V
Continuous Drain Current (TC = 25°C)
−2.2
Continuous Drain Current (TC = 100°C)
−1.39
A
−8.8
A
±30
V
②
150
mJ
Avalanche Current
①
−2.2
A
EAR
Repetitive Avalanche Energy
①
3.2
mJ
dv/dt
Peak Diode Recovery dv/dt
③
−5.5
V/ns
32
0.26
W
W/°C
IDM
Drain Current-Pulsed
VGS
Gate-to-Source Voltage
EAS
Single Pulsed Avalanche Energy
IAR
PD
TJ, TSTG
TL
①
Total Power Dissipation (TC = 25°C)
Linear Derating Factor
Operating Junction and Storage
Temperature Range
−55 to +150
°C
Maximum Lead Temp. for Soldering
Purposes, 1/8” from case for 5-seconds
300
THERMAL RESISTANCE
Symbol
Characteristics
Typ.
Max.
RθJC
Junction-to-Case
−
3.9
RθJA
Junction-to-Ambient
−
62.5
Units
°C/W
REV. B
1
 1999 Fairchild Semiconductor Corporation
FQPF3P20
QFET P-CHANNEL
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise specified)
Symbol
Characteristics
Min.
Typ.
Max.
Units
Test Conditions
BVDSS
Drain-Source Breakdown Voltage
−200
−
−
V
∆BV/∆TJ
Breakdown Voltage Temp. Coeff.
−
−0.18
−
V/°C
−3.0
−
−5.0
V
Gate-Source Leakage, Forward
−
−
−100
Gate-Source Leakage, Reverse
−
−
100
−
−
−1
−
−
−10
Static Drain-Source
On-State Resistance
−
2.06
2.7
Ω
VGS=−10V, ID=−1.1A
④
gfs
Forward Transconductance
−
1.15
−
S
VDS=−40V, ID=−1.1A
④
Ciss
Input Capacitance
−
190
250
Coss
Output Capacitance
−
45
60
pF
Crss
Reverse Transfer Capacitance
−
7.5
10
VGS=0V, VDS=−25V
f=1MHz
See Fig 5
td(on)
Turn-On Delay Time
−
8.5
25
Rise Time
−
35
80
Turn-Off Delay Time
−
12
35
ns
VDD=−100V, ID=−2.8A
RG=50Ω
See Fig 13
④⑤
Fall Time
−
25
60
Qg
Total Gate Charge
−
6.0
8.0
Qgs
Gate-Source Charge
−
1.7
−
nC
Qgd
Gate-Drain (Miller) Charge
−
2.9
−
VDS=−160V, VGS=−10V
ID=−2.8A
See Fig 6 & Fig 12 ④ ⑤
VGS(th)
IGSS
IDSS
RDS(on)
tr
td(off)
tf
Gate Threshold Voltage
Drain-to-Source Leakage Current
nA
VGS=0V, ID=−250µA
ID=−250µA,
See Fig 7
VDS=−5V, ID=−250µA
VGS=−30V
VGS= 30V
µA
VDS=−200V
VDS=−160V, TC=125°C
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
Symbol
IS
Characteristics
Continuous Source Current
Min.
Typ.
Max.
−
−
−2.2
Test Conditions
A
Integral reverse pn-diode
in the MOSFET
ISM
Pulsed-Source Current
①
−
−
−8.8
VSD
Diode Forward Voltage
④
−
−
−5.0
V
TJ=25°C, IS=−2.2A, VGS=0V
trr
Reverse Recovery Time
−
100
−
ns
Qrr
Reverse Recovery Charge
−
0.34
−
µC
TJ=25°C, IF=−2.8A, VDD=−160V
diF/dt=100A/µs
④
Notes:
① Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature
② L=46.5mH, IAS=−2.2A, VDD=−50V, RG=25Ω, Starting TJ =25°C
③ ISD ≤ −2.8A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ =25°C
④ Pulse Test: Pulse Width ≤ 300µs, Duty Cycle ≤ 2%
⑤ Essentially Independent of Operating Temperature
2
Units
QFET P-CHANNEL
FQPF3P20
10
10
Fig 2. Transfer Characteristics
0
-I D , Drain Current [A]
-I D, Drain Current [A]
Fig 1. Output Characteristics
VGS
Top :
-15.0 V
-10.0 V
-8.0 V
-7.0 V
-6.5 V
-6.0 V
Bottom : -5.5 V
-1
0
10
150¡É
25¡É
-55¡É
¡Ø Note :
1. 250¥ìs Pulse Test
2. TC = 25¡É
¡Ø Note
1. VDS = -40V
2. 250¥ìs Pulse Test
-1
10
-1
0
10
1
10
2
10
4
6
8
10
-VGS , Gate-Source Voltage [V]
-VDS, Drain-Source Voltage [V]
Fig 3. On-Resistance vs. Drain Current
Fig 4. Source-Drain Diode Forward Voltage
-I DR , Reverse Drain Current [A]
RDS(on) , [ Ω ]
Drain-Source On-Resistance
10
8
VGS = - 10V
6
VGS = - 20V
4
2
0
10
150¡É
25¡É
¡Ø Note :
1. VGS = 0V
2. 250¥ìs Pulse Test
¡Ø Note : TJ = 25¡É
-1
0
0
2
4
6
8
10
0.4
0.8
-ID , Drain Current [A]
1.2
1.6
2.0
2.4
2.8
-VSD , Source-Drain Voltage [V]
Fig 5. Capacitance vs. Drain-Source Voltage
Fig 6. Gate Charge vs. Gate-Source Voltage
12
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
Capacitances [pF]
300
Ciss
Coss
200
¡Ø Note ;
1. VGS = 0 V
2. f = 1 MHz
Crss
100
VDS = -40V
10
-V GS , Gate-Source Voltage [V]
400
VDS = -100V
VDS = -160V
8
6
4
2
¡Ø Note : ID = -2.8 A
0
-1
10
0
0
10
1
10
-VDS, Drain-Source Voltage [V]
0
1
2
3
4
5
6
7
QG, Total Gate Charge [nC]
3
FQPF3P20
QFET P-CHANNEL
Fig 7. Breakdown Voltage vs. Temperature
Fig 8. On-Resistance vs. Temperature
2.5
1.1
1.0
¡Ø Note :
1. VGS = 0 V
2. ID = -250 ¥ìA
0.9
0.8
-100
-50
0
50
100
150
2.0
R DS(ON) , (Normalized)
Drain-Source On-Resistance
-BV DSS , (Normalized)
Drain-Source Breakdown Voltage
1.2
1.5
1.0
¡Ø Note :
1. VGS = -10 V
2. ID = -1.4 A
0.5
0.0
-100
200
-50
0
o
50
100
150
200
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Fig 9. Max. Safe Operating Area
Fig 10. Max. Drain Current vs. Case Temperature
2.5
Operation in This Area
is Limited by R DS(on)
10
2.0
1
-I D, Drain Current [A]
-I D, Drain Current [A]
1 ms
10 ms
100 ms
10
10
DC
0
-1
¡Ø Notes :
1.5
1.0
0.5
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
10
-2
0
10
10
1
10
0.0
25
2
50
75
100
[°C]
TC, Case Temperature [¡É]
-VDS, Drain-Source Voltage [V]
D = 0 .5
10
0
0 .2
¡ Ø N o te s :
1 . Z ¥ èJ C ( t ) = 3 . 9 ¡ É / W M a x .
2 . D u t y F a c t o r , D = t 1 /t 2
3 . T J M - T C = P D M * Z ¥ èJ C ( t )
0 .1
0 .0 5
10
-1
PDM
0 .0 2
0 .0 1
¥èJC
(t ) , T h e r m a l R e s p o n s e
Fig 11. Thermal Response
t1
Z
t2
s in g le p u ls e
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
4
10
0
10
1
125
150
QFET P-CHANNEL
FQPF3P20
Fig 12. Gate Charge Test Circuit & Waveform
50K
12V
VGS
Same Type
as DUT
Qg
200nF
-10V
300nF
VDS
VGS
Qgs
Qgd
DUT
-3mA
Charge
Fig 13. Resistive Switching Test Circuit & Waveforms
RL
VDS
t on
td(on)
VDD
RG
( 0.5 rated VDS )
Vin
t off
tr
td(off)
tf
10%
DUT
-10V
VDS
90%
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- LL IAS2 -------------------2
BVDSS -- VDD
L
VDS
VDD
tp
ID
VDD
RG
Time
VDS (t)
ID (t)
-10V
DUT
IAS
BVDSS
5
FQPF3P20
QFET P-CHANNEL
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
IS
L
Driver
RG
VGS
VGS
( Driver )
Compliment of DUT
(N-Channel)
VDD
• dv/dt controlled by RG
• IS controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
IS
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
Vf
Body Diode
Forward Voltage Drop
6
VDD
QFET P-CHANNEL
FQPF3P20
TO-220F Package Dimensions
3.30 ±0.10
TO-220F (FS PKG CODE AQ)
10.16 ±0.20
2.54 ±0.20
ø3.18 ±0.10
(7.00)
(1.00x45°)
15.87 ±0.20
15.80 ±0.20
6.68 ±0.20
(0.70)
0.80 ±0.10
)
0°
(3
0.35 ±0.10
#1
+0.10
0.50 –0.05
2.54TYP
[2.54 ±0.20]
2.76 ±0.20
2.54TYP
[2.54 ±0.20]
9.40 ±0.20
4.70 ±0.20
9.75 ±0.30
MAX1.47
Dimensions in Millimeters
September 1999, Rev B
7
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Definition of Terms
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Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner
without notice.
Preliminary
First Production
This datasheet contains preliminary data, and supplementary
data will be published at a later data.
Fairchild Semiconductor reserves the right to make changes
at any time without notice in order to improve design.
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without notice in order to improve design.
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The datasheet contains specifications on a product that has
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The datasheet is printed for reference information only.