FAIRCHILD FSA2259UMX

FSA2259 Low-Voltage, Dual-SPDT
(0.8Ω) Analog Switch with 16kV ESD
Features
Description
ƒ
ƒ
ƒ
ƒ
The FSA2259 is a high-performance, dual, Single Pole
Double Throw (SPDT) analog switch that features low
RON of 0.8Ω (typical) at 3.0V VCC. The FSA2259 operates
over a wide VCC range of 1.65V to 4.3V and is designed
for break-before-make operation. The select input is TTLlevel compatible.
ƒ
ƒ
ƒ
ƒ
0.8Ω Typical On Resistance (RON) for +3.0V Supply
0.40Ω Maximum RON Flatness for +3.0V Supply
-3db Bandwidth: > 50MHz
Low ICCT Current Over an Expanded Control Input
Range
Packaged in 10-Lead UMLP (1.4 x 1.8mm)
Power-Off Protection on Common Ports
Broad VCC Operating Range: 1.65 to 4.3V
ESD HBM JEDEC: JESD22-A114
- I/O to GND: 8.5kV
- Power to GND: 16.0kV
IMPORTANT NOTE:
For
additional
information,
[email protected].
Applications
ƒ
ƒ
The FSA2259 features very low quiescent current even
when the control voltage is lower than the VCC supply.
This feature suits mobile handset applications by
allowing direct interface with baseband processor
general-purpose I/Os with minimal battery consumption.
please
contact
Cell Phone, PDA, Digital Camera, and Notebook
LCD Monitor, TV, and Set-Top Box
Ordering Information
Part Number
Top
Mark
Operating Temperature
Range
FSA2259UMX
JT
-40 to +85°C
Eco Status
Package
10-Lead, Quad, Ultrathin Molded
Leadless Package (UMLP), 1.4 x 1.8mm
Green
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Analog Symbol
1B0
1B1
1A
S1
2B0
2B1
Figure 1.
© 2008 Fairchild Semiconductor Corporation
FSA2259 • Rev. 1.0.2
2A
S2
FSA2259
www.fairchildsemi.com
FSA2259 — Low-Voltage, Dual-SPDT (0.8Ω) Analog Switch with 16kV ESD
July 2009
1B1 Vcc
1A
3
S1
4
1B0
5
Figure 2.
1
2
6
7
GND 2B0
10 2B1
9
2A
8
S2
10-Pin UMLP (Top Through View)
Pin Description
Pin#
Name
Description
1
VCC
Supply Voltage
2
1B1
Data Ports
3
1A
Data Ports
4
S1
Switch Select Pins
5
1B0
Data Ports
6
GND
7
2B0
Data Ports
8
S2
Switch Select Pins
Ground
9
2A
Data Ports
10
2B1
Data Ports
Truth Table
Control Input, Sn
Function
LOW Logic Level
nB0 Connected to nA
HIGH Logic Level
nB1 Connected to nA
© 2008 Fairchild Semiconductor Corporation
FSA2258 • Rev. 1.0.2
www.fairchildsemi.com
2
FSA2259 — Low-Voltage, Dual-SPDT (0.8Ω) Analog Switch with 16kV ESD
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Supply Voltage
(1)
Min.
Max.
Units
-0.5
5.5
V
1B0, 1B1, 2B0, 2B1,
1A, 2A Pins
-0.5
VCC + 0.3
V
S1, S2
-0.5
5.5
V
VSW
Switch I/O Voltage
VIN
Control Input Voltage
IIK
Input Clamp Diode Current
-50
mA
ISW
Switch I/O Current (Continuous)
350
mA
Peak Switch Current (Pulsed at 1ms Duration, <10% Duty Cycle)
500
mA
+150
°C
ISWPEAK
TSTG
(1)
Storage Temperature Range
-65
TJ
Maximum Junction Temperature
+150
°C
TL
Lead Temperature (Soldering, 10 seconds)
+260
°C
ESD
Human Body Model, JEDEC:
JESD22-A114
I/O to GND
8.5
Power to GND
16.0
All Other Pins
8.0
Charged Device Model, JEDEC: JESD22-C101
kV
2.0
kV
Note:
1. Input and output negative ratings may be exceeded if input and output diode current ratings are observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Units
1.65
4.30
V
VCC
Supply Voltage
VIN
Control Input Voltage
0
VCC
V
VSW
Switch I/O Voltage
0
4.3
V
-40
+85
°C
TA
Operating Temperature
© 2008 Fairchild Semiconductor Corporation
FSA2258 • Rev. 1.0.2
www.fairchildsemi.com
3
FSA2259 — Low-Voltage, Dual-SPDT (0.8Ω) Analog Switch with 16kV ESD
Absolute Maximum Ratings
All typical values are at 25ºC unless otherwise specified.
Symbol
Parameter
Conditions
Min.
VIH
VIL
Control Input Voltage High
Control Input Voltage Low
TA=-40 to
+85ºC
TA=+25ºC
VCC (V)
Typ.
Max.
Min.
3.60 to 4.30
1.7
2.70 to 3.60
1.5
2.30 to 2.70
1.4
1.65 to 1.95
0.9
V
3.60 to 4.30
0.7
2.70 to 3.60
0.5
2.30 to 2.70
0.4
1.65 to 1.95
0.4
IIN
Control Input Leakage
(S1,S2)
VIN=0 to VCC
1.65 to 4.30
INO(0FF),
INC(OFF)
Off Leakage Current of
Port nB0 and nB1
nA=0.3V, VCC–0.3V
nB0 or nB1=VCC-0.3V,
0.3V, or Floating
Figure 4
1.95 to 4.30
-10
IA(ON)
On Leakage Current of
Port nA
nA=0.3V, VCC–0.3V
nB0 or nB1=VCC-0.3V,
0.3V, or Floating
Figure 5
1.95 to 4.30
-20
IOFF
Power-Off Leakage
Current (Common Port
Only 1A, 2A)
Common Port (1A,
2A), VIN=0V to 4.3V,
VCC=0V nB0,
nB1=Floating
0V
ION=100mA, nB0 or
nB1=0.7V, 3.6V
Figure 3
4.30
0.50
1.00
ION=100mA, nB0 or
nB1=0.7V, 2.3V
Figure 3
3.00
0.80
1.20
RON
∆RON
Switch On Resistance(2,5)
On Resistance Matching
Between Channels(3,5)
RFLAT(ON)
On Resistance Flatness
0.5
µA
10
-50
50
nA
20
-100
100
nA
±1
µA
Ω
ION=100mA, nB0 or
nB1=0V, 0.7V, 1.6V,
2.3V
Figure 3
2.30
1.10
ION=100mA, nB0 or
nB1=0V, 0.7V, 1.65V
Figure 3
1.65
1.50
4.30
0.08
0.25
3.00
0.20
0.25
2.30
0.40
1.65
0.50
ION=100mA, nB0 or
nB1=0.7V
IOUT=100mA, nB0 or
nB1=0V to VCC
3.00
ICCT
Quiescent Supply Current
VIN=0 or VCC, IOUT=0
4.30
0.4
2.30
Increase in ICC per Input
Input at 2.6V
4.30
Input at 1.8V
Ω
0.4
0.9
1.65
ICC
V
-0.5
4.30
(4,5)
Unit
Max.
Ω
1.2
-100
100
-500
500
3
7
7
15
nA
µA
Notes:
2. On resistance is determined by the voltage drop between A and B pins at the indicated current through the switch.
3. ∆RON=RON max – RON min measured at identical VCC, temperature, and voltage.
4. Flatness is defined as the difference between the maximum and minimum value of on resistance (RON) over the
specified range of conditions.
5. Guaranteed by characterization, not production tested for VCC=1.65 – 3.0V
© 2008 Fairchild Semiconductor Corporation
FSA2258 • Rev. 1.0.2
www.fairchildsemi.com
4
FSA2259 — Low-Voltage, Dual-SPDT (0.8Ω) Analog Switch with 16kV ESD
DC Electrical Characteristics
All typical value are for VCC=3.3V at 25ºC unless otherwise specified.
Symbol Parameter
Conditions
TA=-40 to
+85°C
TA=+25ºC
VCC (V)
Min. Typ. Max. Min.
tON
tOFF
tBBM
nB0 or
nB1=1.5V,
RL=50Ω,
CL=35pF
Turn-On
Time
nB0 or
nB1=1.5V,
RL=50Ω,
CL=35pF
Turn-Off
Time
nB0 or
BreaknB1=1.5V,
Before-Make
RL=50Ω,
(6)
Time
CL=35pF
3.60 to 4.30
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
3.60 to 4.30
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
3.60 to 4.30
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
Unit
Max.
55
60
65
60
65
70
ns
70
30
35
40
5
5
5
40
15
15
15
16
Figure
Figure 6
Figure 7
35
40
45
ns
2
2
2
2
ns
Figure 8
Charge
Injection(6)
CL=1.0nF,
VS=0V, RS=0Ω
1.65 to 4.30
25
pC
Figure 12
OIRR
Off Isolation(6)
f=100kHz,
1.65 to 4.30
RL=50Ω, CL=0pF
-70
dB
Figure 10
Xtalk
Crosstalk(6)
f=100kHz,
1.65 to 4.30
RL=50Ω, CL=0pF
-70
dB
Figure 11
BW
-3db
Bandwidth(6)
RL=50Ω, CL=0pF 1.65 to 4.30
>50
MHz
Figure 9
THD+N
Total
Harmonic
Distortion +
Noise(6)
f=20Hz to 20kHz,
1.65 to 4.30
RL=32Ω,
VIN=2Vpp
.06
%
Figure 15
Q
Notes:
6. Guaranteed by characterization, not production tested
Capacitance
All capacitance specifications are guaranteed by characterization and are not production tested.
Symbol
Parameter
Conditions VCC (V)
TA=+25ºC
Min.
Typ.
Unit
Figure
Max.
CIN
Control Pin Input Capacitance
f=1MHz
0
1.5
pF
Figure 13
COFF
B Port Off Capacitance
f=1MHz
3.3
30
pF
Figure 13
CON
A Port On Capacitance
f=1MHz
3.3
120
pF
Figure 14
© 2008 Fairchild Semiconductor Corporation
FSA2258 • Rev. 1.0.2
www.fairchildsemi.com
5
FSA2259 — Low-Voltage, Dual-SPDT (0.8Ω) Analog Switch with 16kV ESD
AC Electrical Characteristics
VON
I A(OFF)
NC
nBn
A
nA
V IN
V IN
GND
I ON
Select
V Sel =
R ON = VON / ION
Figure 3.
Select
VSel =
GND
0 or Vcc
**Each switch port is tested separately.
On Resistance
Figure 4.
nA
V IN
A
GND
V IN
Select
VSel =
Off Leakage (Ports Tested Separately)
nBn
I A(ON)
NC
GND
0 orVcc
0 or Vcc
RS
CL
RL
V OUT
GND
GND
V Sel
GND
Figure 5.
On Leakage
Figure 6.
tRISE = 2.5ns
Test Circuit Load
tFALL = 2.5ns
VCC
Input - VSel
10%
GND
VOH
Output - VOUT
VOL
Figure 7.
© 2008 Fairchild Semiconductor Corporation
FSA2258 • Rev. 1.0.2
90%
90%
VCC /2
VCC /2
90%
tON
10%
90%
tOFF
Turn-On / Turn-Off Waveforms
www.fairchildsemi.com
6
FSA2259 — Low-Voltage, Dual-SPDT (0.8Ω) Analog Switch with 16kV ESD
Test Diagrams
t RISE = 2.5ns
nB n
nA
V cc
V IN
GN D
VOUT
CL
V IN
R
L
10%
0V
GN D
GN D
90%
V cc /2
Input - VSel
V OUT
RS
0.9*V out
0.9*V out
V Sel
G ND
tBBM
RL and CL are functions of the application
environment (50, 75, or 100 ).
CL includes test fixture and stray capacitance.
Figure 8.
Break-Before-Make Interval Timing
Network Analyzer
RS
GND
V IN
VS
GND
VSel
GND
VOUT
GND
RT
RL and CL are functions of the application
environment (50, 75, or 100 ).
L
CL includes
test fixture and stray capacitance.
Figure 9.
GND
Bandwidth
Network Analyzer
RS
VSel
VS
GND
RT
GND
GND
VOUT
GND
GND
RS and RT are functions of the application
environment (50, 75, or 100 ).
RT
GND
Off-Isolation
= 20 Log (VOUT / VIN )
Figure 10.
© 2008 Fairchild Semiconductor Corporation
FSA2258 • Rev. 1.0.2
Channel Off Isolation
www.fairchildsemi.com
7
FSA2259 — Low-Voltage, Dual-SPDT (0.8Ω) Analog Switch with 16kV ESD
Test Diagrams (Continued)
Network Analyzer
RS
VIN
GND
VS
GND
VSel
GND
GND
RT
V OUT
RT
GND
GND
RS and RT are functions of the application
CROSSTALK = 20 Log (VOUT / VIN )
environment (50, 75, or 100 ).
Figure 11.
Adjacent Channel Crosstalk
Generator
VCC
B
RS
VS
VIN
Input – VSEL
mA
CL
GND
nSn
Off
On
Off
0V
VOUT
ΔVOUT
GND
VOUT
VSEL
CL includes test fixture and stray capacitance
GND
Figure 12.
Charge Injection Test
Capacitance
Meter
nBn
nSn
Capacitance
Meter
VSel =
f = 1MHz
Figure 13.
Q = ΔVOUT / CL
0 or Vcc
nBn
nSn
V Sel =
f = 1MHz
0 orV cc
nBn
nBn
Channel Off Capacitance
Figure 14.
Channel On Capacitance
Audio Analyzer
RS
GND
V IN
VS
GND
V CNTRL
GND
VSel =
GND
0 or Vcc
RS and RT are functions of the application
environment (see AC Tables for specific values).
Figure 15.
© 2008 Fairchild Semiconductor Corporation
FSA2258 • Rev. 1.0.2
V OUT
RT
GND
Total Harmonic Distortion
www.fairchildsemi.com
8
FSA2259 — Low-Voltage, Dual-SPDT (0.8Ω) Analog Switch with 16kV ESD
Test Diagrams (Continued)
0.15 C
A
1.40
2X
1.700
B
9X
0.563
0.663
1
1.80
PIN #1 QUADRANT
2.100
0.400
0.15 C
2X
10X
0.225
TOP VIEW
RECOMMENDED LAND PATTERN
0.55 MAX.
1.450
0.10 C
0.550
0.152
9X
0.450
SEATING
PLANE
0.08 C
0.050
C
0.400
SIDE VIEW
1.850
10X
0.225
3
9X
0.35
0.45
0.45
0.55
OPTIONAL MINIMIAL TOE LAND PATTERN
0.40
6
1
10
0.500
0.15
10X
0.25
0.100
0.10 C A B
0.05 C
0.100
0.100
BOTTOM VIEW
DETAIL A
PIN #1 TERMINAL
SCALE: 2X
A. DIMENSIONS ARE IN MILLIMETERS.
B. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
C. DRAWING FILENAME: UMLP10Arev2
Figure 16.
10-Lead Quad Ultrathin Molded Leadless Package (UMLP)
Note: click here for tape and reel specifications, available at:
http://www.fairchildsemi.com/products/analog/pdf/UMLP10_TNR.pdf
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
FSA2258 • Rev. 1.0.2
www.fairchildsemi.com
9
FSA2259 — Low-Voltage, Dual-SPDT (0.8Ω) Analog Switch with 16kV ESD
Physical Dimensions
FSA2259 — Low-Voltage, Dual-SPDT (0.8Ω) Analog Switch with 16kV ESD
© 2008 Fairchild Semiconductor Corporation
FSA2258 • Rev. 1.0.2
www.fairchildsemi.com
10