Fairchild FSB50450UD Smart power module (spmâ®) Datasheet

Motion-SPM
FSB50450UD
TM
Smart Power Module (SPM®)
Features
General Description
• 500V RDS(on)=2.4W(max) 3-phase FRFET inverter including
high voltage integrated circuit (HVIC)
FSB50450UD is a tiny smart power module (SPM®) based on
FRFET technology as a compact inverter solution for small
power motor drive applications such as fan motors and water
suppliers. It is composed of 6 fast-recovery MOSFET (FRFET),
and 3 half-bridge HVICs for FRFET gate driving.
FSB50250UTD provides low electromagnetic interference (EMI)
characteristics with optimized switching speed. Moreover, since
it employs FRFET as a power switch, it has much better
ruggedness and larger safe operation area (SOA) than that of
an IGBT-based power module or one-chip solution. The
package is optimized for the thermal performance and
compactness for the use in the built-in motor application and
any other application where the assembly space is concerned.
FSB50450UD is the most solution for the compact inverter
providing the energy efficiency, compactness, and low
electromagnetic interference.
• 3 divided negative dc-link terminals for inverter current sensing applications
• HVIC for gate driving and undervoltage protection
• 3/5V CMOS/TTL compatible, active-high interface
• Optimized for low electromagnetic interference
• Isolation voltage rating of 1500Vrms for 1min.
• Embedded bootstrap diode in the package
Absolute Maximum Ratings
Symbol
Parameter
Conditions
Rating
Units
500
V
VPN
DC Link Input Voltage,
Drain-source Voltage of each FRFET
ID25
Each FRFET Drain Current, Continuous
TC = 25°C
1.5
A
ID80
Each FRFET Drain Current, Continuous
TC = 80°C
1.1
A
IDP
Each FRFET Drain Current, Peak
TC = 25°C, PW < 100ms
3.8
A
PD
Maximum Power Dissipation
TC = 25°C, Each FRFET
14
W
V CC
Control Supply Voltage
Applied between V CC and COM
20
V
VBS
High-side Bias Voltage
Applied between V B(U)-U, VB(V)-V, VB(W)-W
V IN
Input Signal Voltage
Applied between IN and COM
TJ
20
V
-0.3 ~ VCC+0.3
V
Operating Junction Temperature
-40 ~ 150
°C
TSTG
Storage Temperature
-40 ~ 125
°C
R qJC
Junction to Case Thermal Resistance
Each FRFET under inverter operating condition (Note 1)
8.9
°C/W
VISO
Isolation Voltage
60Hz, Sinusoidal, 1 minute, Connection
pins to heatsink
1500
Vrms
©2010 Fairchild Semiconductor Corporation
FSB50450UD Rev. A
1
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FSB50450UD Smart Power Module (SPM®)
April 2010
FSB50450UD Smart Power Module (SPM®)
Pin Descriptions
Pin Number
Pin Name
1
COM
Pin Description
IC Common Supply Ground
2
VB(U)
3
V CC(U)
Bias Voltage for U Phase High Side FRFET Driving
4
IN(UH)
Signal Input for U Phase High-side
5
IN(UL)
Signal Input for U Phase Low-side
Bias Voltage for U Phase IC and Low Side FRFET Driving
6
VS(U)
Bias Voltage Ground for U Phase High Side FRFET Driving
7
V B(V)
Bias Voltage for V Phase High Side FRFET Driving
8
VCC(V)
Bias Voltage for V Phase IC and Low Side FRFET Driving
9
IN (VH)
Signal Input for V Phase High-side
10
IN (VL)
Signal Input for V Phase Low-side
11
V S(V)
Bias Voltage Ground for V Phase High Side FRFET Driving
12
VB(W)
Bias Voltage for W Phase High Side FRFET Driving
13
V CC(W)
Bias Voltage for W Phase IC and Low Side FRFET Driving
14
IN(WH)
Signal Input for W Phase High-side
15
IN(WL)
Signal Input for W Phase Low-side
16
VS(W)
Bias Voltage Ground for W Phase High Side FRFET Driving
17
P
Positive DC–Link Input
18
U
Output for U Phase
19
NU
Negative DC–Link Input for U Phase
20
NV
21
V
Negative DC–Link Input for V Phase
22
NW
Negative DC–Link Input for W Phase
23
W
Output for W Phase
Output for V Phase
(1) COM
(2) VB(U)
(17) P
(3) VCC(U)
VCC
VB
(4) IN (UH)
HIN
HO
(5) IN (UL)
LIN
VS
COM
LO
(18) U
(6) VS(U)
(19) N U
(7) VB(V)
(8) VCC(V)
VCC
VB
(9) IN (VH)
HIN
HO
LIN
VS
COM
LO
(10) IN(VL)
(20) N V
(21) V
(11) VS(V)
(12) VB(W)
(13) VCC(W)
VCC
VB
(14) IN(WH)
HIN
HO
LIN
VS
COM
LO
(15) IN(WL)
(22) N W
(23) W
(16) VS(W)
Note:
Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside SPM®. External connections should be made as indicated in Figure 2 and 5.
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
FSB50450UD Rev. A
2
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Inverter Part (Each FRFET Unless Otherwise Specified)
Symbol
Min
Typ
500
-
-
V
Breakdown Voltage TemID = 250mA, Referenced to 25°C
perature Coefficient
-
0.53
-
V
IDSS
Zero Gate Voltage
Drain Current
V IN= 0V, VDS = 500V
-
-
250
mA
RDS(on)
Static Drain-Source
On-Resistance
V CC = VBS = 15V, V IN = 5V, ID = 1A
-
1.9
2.4
W
VSD
Drain-Source Diode
Forward Voltage
V CC = VBS = 15V, V IN = 0V, ID = -1A
-
-
1.2
V
V PN = 300V, VCC = VBS = 15V, ID = 1A
V IN = 0V « 5V
Inductive load L=3mH
High- and low-side FRFET switching
-
1250
-
ns
BV DSS
DBVDSS/
DTJ
Parameter
Drain-Source Breakdown
V IN= 0V, ID = 250mA (Note 2)
Voltage
tON
tOFF
trr
Conditions
Switching Times
EON
(Note 3)
EOFF
RBSOA
Max Units
-
500
-
ns
-
200
-
ns
-
80
-
mJ
-
10
-
mJ
V = 400V, VCC = VBS = 15V, ID = IDP, V DS=BVDSS,
Reverse-bias Safe Oper- PN
TJ = 150°C
ating Area
High- and low-side FRFET switching (Note 4)
Full Square
Control Part (Each HVIC Unless Otherwise Specified)
Symbol
IQCC
Parameter
Quiescent VCC Current
Conditions
Min Typ Max Units
V CC=15V, V IN=0V
Applied between VCC and COM
-
-
160
mA
Applied between VB(U)-U,
V B(V)-V, VB(W)-W
-
-
100
mA
IQBS
Quiescent VBS Current
V BS=15V, V IN=0V
UVCCD
Low-side Undervoltage
Protection (Figure 7)
V CC Undervoltage Protection Detection Level
7.4
8.0
9.4
V
UVCCR
V CC Undervoltage Protection Reset Level
8.0
8.9
9.8
V
High-side Undervoltage
Protection (Figure 8)
V BS Undervoltage Protection Detection Level
7.4
8.0
9.4
V
V BS Undervoltage Protection Reset Level
8.0
8.9
9.8
V
V IH
ON Threshold Voltage
Logic High Level
2.9
-
-
V
V IL
OFF Threshold Voltage
Logic Low Level
-
-
0.8
V
-
10
20
mA
-
-
2
mA
UVBSD
UVBSR
IIH
IIL
Input Bias Current
V IN = 5V
V IN = 0V
Applied between IN and COM
Applied between IN and COM
Bootstrap Diode Part
Symbol
VRRM
Parameter
Conditions
Maixmum Repetitive Reverse Voltage
IF
Forward Current
TC = 25°C
IFP
Forward Current (Peak)
TC = 25°C, Under 1ms Pulse Width
TJ
Operating Junction Temperature
Rating
Units
500
V
0.5
A
2
A
-40 ~ 150
°C
Note:
1. For the measurement point of case temperature T C, please refer to Figure 4 in page 5.
2. BVDSS is the absolute maximum voltage rating between drain and source terminal of each FRFET inside SPM®. VPN should be sufficiently less than this value considering the
effect of the stray inductance so that VDS should not exceed BVDSS in any case.
3. tON and tOFF include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the
field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 5 for the switching time definition with the switching test circuit of Figure 6.
4. The peak current and voltage of each FRFET during the switching operation should be included in the safe operating area (SOA). Please see Figure 6 for the RBSOA test circuit that is same as the switching test circuit.
FSB50450UD Rev. A
3
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FSB50450UD Smart Power Module (SPM®)
Electrical Characteristics (TJ = 25°C, VCC=VBS=15V Unless Otherwise Specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VF
Forward Voltage
IF = 0.1A, TC = 25°C
-
2.0
-
V
trr
Reverse Recovery Time
IF = 0.1A, TC = 25°C
-
80
-
ns
Built in Bootstrap Diode VF-IF Characteristic
1.0
0.9
0.8
0.7
IF [A]
0.6
0.5
0.4
0.3
0.2
0.1
0.0
TC=25℃
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VF [V]
Note:
Built in bootstrap diode includes around 15 Ω resistance characteristic.
Figure 2. Built in Bootstrap Diode Characteristics
Package Marking & Ordering Information
Device Marking
Device
Package
Reel Size
Packing Type
Quantity
FSB50450UD
FSB50450UD
SPM23-HD
_
_
15
FSB50450UD Rev. A
4
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FSB50450UD Smart Power Module (SPM®)
Bootstrap Diode Part
Symbol
Parameter
Value
Conditions
Units
Min.
Typ.
Max.
-
300
400
V
V PN
Supply Voltage
Applied between P and N
VCC
Control Supply Voltage
Applied between V CC and COM
13.5
15
16.5
V
VBS
High-side Bias Voltage
Applied between V B and output(U, V, W)
13.5
15
16.5
V
3.0
-
V CC
V
0
-
0.6
V
1.0
-
-
ms
-
15
-
kHz
VIN(ON)
Input ON Threshold Voltage
VIN(OFF)
Input OFF Threshold Voltage
Applied between IN and COM
tdead
Blanking Time for Preventing
VCC =VBS=13.5 ~ 16.5V, TJ £ 150°C
Arm-short
fPWM
PWM Switching Frequency
TJ £ 150°C
These values depend on PWM
control algorithm
R2
15-V Line
R1
P
D1
R5
Micom
C5
VCC
VB
HIN
HO
LIN
VS
COM
LO
Inverter
Output
C3
N
C2
10mF
VDC
R3
One-Leg Diagram of SPM
C1
HIN
LIN
Output
Note
0
0
Z
Both FRFET Off
0
1
0
Low-side FRFET On
1
0
VDC
High-side FRFET On
1
1
Forbidden
Shoot-through
Open
Open
Z
Same as (0, 0)
* Example of bootstrap paramters:
C1 = C2 = 1mF ceramic capacitor,
R1 = 56W, R2 = 20W
Note:
(1) It is recommended the bootstrap diode D1 to have soft and fast recovery characteristics with 500-V rating
(2) Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above.
(3) RC coupling(R5 and C5) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM®is compatible with
standard CMOS or LSTTL outptus.
(4) Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. Bypass capacitors such as C1, C2
and C3 should have good high-frequency characteristics to absorb high-frequency ripple current.
Figure 3. Recommended CPU Interface and Bootstrap Circuit with Parameters
14.50
3.80
Case Temperature (Tc)
Detecting Point
MOSFET
Note:
Attach the thermocouple on top of the heatsink-side of SPM® (between SPM® and heatsink if applied) to get the correct temperature measurement.
Figure 4. Case Temperature Measurement
FSB50450UD Rev. A
5
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FSB50450UD Smart Power Module (SPM®)
Recommended Operating Conditions
FSB50450UD Smart Power Module (SPM®)
VIN
VIN
Irr
120% of ID
100% of ID
VDS
ID
10% of ID
ID
VDS
tON
trr
tOFF
(b) Turn-off
(a) Turn-on
Figure 5. Switching Time Definition
REH
VCC
ID
RBS
CBS
VCC
VB
HIN
HO
LIN
VS
COM
LO
L
VDC
+
VDS
-
One-leg Diagram of SPM
Figure 6. Switching and RBSOA(Single-pulse) Test Circuit (Low-side)
Input Signal
UV Protection
Status
Low-side Supply, VCC
RESET
DETECTION
RESET
UVCCR
UVCCD
MOSFET Current
Figure 7. Undervoltage Protection (Low-side)
Input Signal
UV Protection
Status
High-side Supply, VBS
RESET
DETECTION
RESET
UVBSR
UVBSD
MOSFET Current
Figure 8. Undervoltage Protection (High-side)
FSB50450UD Rev. A
6
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(1) COM
R1
(3) VCC(U)
R5
(4) IN (UH)
(5) IN (UL)
C5
C2
C1
R1
(6) VS(U)
VCC
VB
HIN
HO
LIN
VS
COM
LO
(18) U
C3
(9) IN (VH)
(10) IN(VL)
C2
C1
R1
(11) VS(V)
VDC
(19) NU
(7) VB(V)
(8) VCC(V)
Micom
(17) P
(2) VB(U)
VCC
VB
HIN
HO
LIN
VS
COM
LO
VCC
VB
HIN
HO
LIN
VS
COM
LO
(20) NV
M
(21) V
(12) VB(W)
(13) VCC(W)
(14) IN(WH)
(15) IN(WL)
C2
C1
(16) VS(W)
(22) NW
(23) W
For 3-phase current sensing and protection
15-V
Supply
C4
R4
R3
Figure 9. Example of Application Circuit
FSB50450UD Rev. A
7
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FSB50450UD Smart Power Module (SPM®)
R2
FSB50450UD Smart Power Module (SPM®)
Detailed Package Outline Drawings
16-Max 1.00
16-0.50±0.05
13-(0.30)
#1
#16
(1.165)
15*1.778=26.67±0.30
(1.80)
13.34
13.34
(1.00)
#16
14.55±0.30
7.00
12.00±0.20
)
40
0.
(R
7.00
6°
2°
#1
12.23
13.13
#23
0.50±0.05
#17
3.10±0.20
29.00±0.20
2.55~3.35
6.05±0.20
2x3.90=7.80±0.30
1.95±0.30
#17
#19
(0.30)
#23
(0.30)
0.60±0.05
0.50±0.05
#17,18,21,22,23 LEAD
#19, 20 LEAD
Max 1.00
Max 1.00
FSB50450UD Rev. A
(1.30)
4x3.90=15.60±0.30
(1.80)
(2.275)
8
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FSB50450UD Smart Power Module (SPM®)
Rev. I15
9
FSB50450UD Rev. A
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