Fairchild FST3126 4-bit bus switch Datasheet

Revised January 2005
FST3126
4-Bit Bus Switch
General Description
Features
The Fairchild Switch FST3126 provides four high-speed
CMOS TTL-compatible bus switches. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating
additional ground bounce noise.
■ 4Ω switch connection between two ports.
The device is organized as four 1-bit switches with separate OE inputs. When OE is HIGH, the switch is ON and
Port A is connected to Port B. When OE is LOW, the switch
is OPEN and a high-impedance state exists between the
two ports.
■ Control inputs compatible with TTL level.
■ Minimal propagation delay through the switch.
■ Low lCC.
■ Zero bounce in flow-through mode.
Ordering Code:
Order Number
Package Number
FST3126M
M14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
FST3126QSC
MQA16
16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
FST3126MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagrams
Pin Assignment for SOIC and TSSOP
Pin Assignment for QSOP
Pin Descriptions
Pin Name
Description
OE1, OE2, OE3, OE4
Bus Switch Enables
1A, 2A, 3A, 4A
Bus A
Inputs
Inputs/Outputs
1B, 2B, 3B, 4B
Bus B
OE
A,B
NC
Not Connected
L
Z
H
A=B
© 2005 Fairchild Semiconductor Corporation
DS500044
Truth Table
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FST3126 4-Bit Bus Switch
August 1997
FST3126
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC )
−0.5V to +7.0V
DC Switch Voltage (VS)
−0.5V to +7.0V
Power Supply Operating (VCC)
DC Input Voltage (VIN) (Note 2)
−0.5V to +7.0V
Input Voltage (VIN)
0V to 5.5V
0V to 5.5V
DC Input Diode Current (lIK) VIN<0V
−50mA
Output Voltage (VOUT)
DC Output (IOUT ) Sink Current
128mA
Input Rise and Fall Time (tr, tf)
+/− 100mA
DC VCC/GND Current (ICC/IGND)
Storage Temperature Range (TSTG)
4.0V to 5.5V
Switch Control Input
−65°C to +150 °C
0nS/V to 5nS/V
Switch I/O
0nS/V to DC
−40 °C to +85 °C
Free Air Operating Temperature (TA)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3: Unused control inputs must be held high or low. They may not float.
DC Electrical Characteristics
Symbol
Parameter
VCC
(V)
TA = −40 °C to +85 °C
Typ
(Note 4)
Min
Max
−1.2
Units
Conditions
IIN = −18mA
VIK
Clamp Diode Voltage
VIH
HIGH Level Input Voltage
4.0–5.5
VIL
LOW Level Input Voltage
4.0–5.5
0.8
V
II
Input Leakage Current
5.5
±1.0
µA
0≤ VIN ≤5.5V
IOZ
OFF-STATE Leakage Current
5.5
±1.0
µA
0 ≤A, B ≤VCC
RON
Switch On Resistance
4.5
4
7
Ω
VIN = 0V, IIN = 64mA
(Note 5)
4.5
4
7
Ω
VIN = 0V, IIN = 30mA
4.5
2.0
V
V
4.5
8
15
Ω
VIN = 2.4V, IIN = 15mA
4.0
11
20
Ω
VIN = 2.4V, IIN = 15mA
ICC
Quiescent Supply Current
5.5
3
µA
VIN = VCC or GND,
∆ICC
Increase in ICC per Input
5.5
2.5
mA
One input at 3.4V.
IOUT = 0
Other inputs at VCC or GND
Note 4: Typical values are at VCC = 5.0V and T A = +25°C
Note 5: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
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TA = −40 °C to +85 °C,
CL = 50pF, RU = RD = 500Ω
Symbol
Parameter
VCC = 4.5 − 5.5V
Min
tPHL,tPLH
Prop Delay Bus to Bus (Note 6)
tPZH, tPZL
Output Enable Time
VCC = 4.0V
Max
1.0
Min
Units
Conditions
Max
0.25
0.25
ns
VI = OPEN
4.5
5.0
ns
VI = 7V for tPZL
Figures 1, 2
VI = OPEN for tPZH
tPHZ, tPLZ
Output Disable Time
1.5
Figure No.
5.7
6.2
ns
VI = 7V for tPLZ
VI = OPEN for tPHZ
Figures 1, 2
Figures 1, 2
Note 6: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
Symbol
(Note 7)
Parameter
Typ
Max
Units
Conditions
CIN
Control Pin Input Capacitance
3
pF
VCC = 5.0V
CI/O
Input/Output Capacitance
5
pF
VCC = 5.0V, OE = 0V
Note 7: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50 Ω source terminated in 50 Ω
Note: C L includes load and stray capacitance
Note: Input PRR = 1.0MHz, tW = 500ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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FST3126
AC Electrical Characteristics
FST3126
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Package Number MQA16
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FST3126 4-Bit Bus Switch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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