CML FX009A Low-noise digitally controlled amplifier array Datasheet

CML Semiconductor Products
PRODUCT INFORMATION
Digitally Controlled
FX009A Low-Noise
Amplifier Array
Publication D/009A/3 July 1994
Features/Applications
8 Digitally Controlled Low-Noise
Amplifiers
15 Gain/Attenuation Steps
7 Trimmers, with a ± 3dB Range in
0.43dB Steps
1 'Volume' Trimmer, with a ± 14dB
Range in 2.0dB Steps
SERIAL CLOCK INPUT
Audio and Data Gain Control
Applications
Cellular, PMR, PABX Applications
LOAD/LATCH
LOAD/LATCH
16
1
V BIAS
Output Mute/Powersave Function
8 - BIT
SERIAL DATA INPUT
AND
LINE DECODERS
SERIAL DATA INPUT
V DD
8-Bit Serial Data Control
1
2
3
4
5
6
7
V BIAS
3
V BIAS
V BIAS
4
7
*
V BIAS
Ch4
6
Ch6
V BIAS
*
Ch3
Ch5
*
*
Ch2
V SS
5
*
*OUTPUT MUTE - POWERSAVE
Ch1
2
8
16-LINE STEP CONTROLS TO AMPLIFIERS 1 to 8
Ch7
VBIAS
*
*
FX009A
8
Ch8
V BIAS
V BIAS
4
3
2
1
5
6
7
8 - VOLUME
CONTROLLED AUDIO OUTPUT LINES
Fig.1 Functional Block Diagram
Brief Description
The FX009A Digitally Adjustable Amplifier Array is
intended to replace trimmer potentiometers and volume
controls in Cellular, PMR, Telephony and
Communications applications where d.c., voice or data
signals need adjustment.
The FX009A is a low-noise single-chip LSI consisting
eight digitally controlled amplifier stages, each with 15
distinct gain/attenuation steps. Control of each
individual amplifier is by an 8-bit serial data stream.
Seven of the amplifier stages offer a +/-3dB range in
steps of 0.43dB, whilst the remaining amplifier offers a
+/-14dB range in steps of 2dB, and is intended for
volume control applications. Each amplifier includes a
16th 'Mute' state which sets the output to bias (VDD/2)
and powersaves the entire section. Minimum current
drain may be achieved by muting all eight sections.
This product replaces the need for manual trimming of
audible signals by using the host microprocessor to
digitally control the set-up of all audio levels.
Applications include:
(i) Control, adjustment and set-up of communications
equipment by an Intelligent ATE without manual
intervention – eg. Deviation, Microphone and L/S
Level, Rx Audio Level etc.
(ii) Automatic Dynamic Compensation of drift caused
by variations in temperature, linearity, etc.
(iii)Fully automated servicing and re-alignment.
The FX009A is a low-power, single 5-volt CMOS
device available in both 24-pin DIL and SMD package
versions.
1
Pin Number
Function
FX009A
J
FX009A
LG/LS
1
1
Serial Clock : This external clock pulse input is used to “clock in” the Control Data.
See Figure 4, Data Load Timing. This input has an internal 1MΩ pullup resistor.
2
2
Load/Latch : Governs the loading and execution of the control data. During serial
data loading this input should be kept at a logical '0' to ensure that data rippling past
the latches has no effect. When all 8 bits have been loaded, this input should be
strobed '0' ⇒ '1' ⇒ '0' to latch the new data in. Data is executed on the falling edge
of the strobe. If the Load/Latch input is used this pin should be left open circuit. This
input has an internal 1MΩ pullup resistor.
3
3
Load/Latch : The inverted Load/Latch input. This function governs the loading and
execution of the control data. During serial data loading this input should be kept at a
logical '1' to ensure that data rippling past the latches has no effect. When all 8 bits
have been loaded, this input should be strobed '1' - '0' - '1' to latch the new data in.
Data is executed on the rising edge of the strobe. If the Load/Latch input is used this
pin should be left open circuit. This input has an internal 1MΩ pulldown resistor.
4
4
Ch1 Input :
5
5
Ch2 Input :
6
6
Ch3 Input :
Analogue Inputs :
These individual amplifier inputs are self-biasing, a.c. input
analogue signals must be capacitively coupled to these pins,
as shown in Figure 2.
In the powersave modes the inputs are biased at VDD/2.
7
7
Ch4 Input :
Note that amplifiers Ch1 to Ch8 are 'inverting amplifiers.'
8
8
VBIAS : The output of the on-chip bias circuitry, held at VDD/2. This pin should be
decoupled to VSS as shown in Figure 2.
9
9
Ch5 Input :
10
10
Ch6 Input :
11
11
Ch7 Input :
12
12
Ch8 Input :
13
13
VSS : Negative supply rail (GND).
14
14
Ch8 Output :
Analogue Outputs :
15
15
Ch7 Output :
16
16
Ch6 Output :
17
17
Ch5 Output :
The individual "Gain Controlled" amplifier outputs.
Ch1 to Ch7 range from -3dB to +3dB in 0.43dB steps, Ch8
could be utilized as a volume control, ranging from -14dB to
+14dB in 2.0dB steps.
In the powersave mode the selected output is biased at VDD/2.
18
18
No internal connection. Do not use.
19
19
Ch4 Output :
Analogue Outputs
20
20
Ch3 Output :
Note that amplifiers Ch1 to Ch8 are 'inverting amplifiers.'
21
21
Ch2 Output :
22
22
Ch1 Output :
23
23
VDD : Positive supply rail. A single +5-volt power supply is required.
24
24
Control Data Input : Operation of the 8 amplifier channels (Ch1 – Ch8) is controlled
by the 8 bits of data entered serially at this pin . The data is entered (bit 7 to bit 0) on
the rising edge of the external Serial Clock. The data format is described in Tables 1,
2 and Figure 4. This input has an internal 1MΩ pullup resistor.
Analogue Inputs :
2
Application Notes
V DD
C 10
V SS
SERIAL CLOCK INPUT
1
LOAD/LATCH
LOAD/LATCH
C1
CHANNEL 1 INPUT
CHANNEL 2 INPUT
C2
CHANNEL 4 INPUT
CHANNEL 6 INPUT
CHANNEL 8 INPUT
22
4
21
7
C5
V BIAS
C6
C7
CHANNEL 7 INPUT
23
3
6
C4
CHANNEL 5 INPUT
2
5
C3
CHANNEL 3 INPUT
C8
SERIAL CONTROL DATA INPUT
24
FX009A
20
J - LG - LS
18
CHANNEL 1 OUTPUT
CHANNEL 2 OUTPUT
CHANNEL 3 OUTPUT
CHANNEL 4 OUTPUT
19
8
17
9
16
10
15
11
14
12
V DD
X
CHANNEL 5 OUTPUT
CHANNEL 6 OUTPUT
CHANNEL 7 OUTPUT
CHANNEL 8 OUTPUT
V SS
13
C9
V SS
Notes
(1) Channel Amplifiers 1 to 8 are inverting amplifiers.
Component
Unit Value
C1 to C8
C9
C10
Tolerances: C = ± 20%
(2) Analogue input capacitors C1 to C8 are only required for a.c.
input signals, d.c. input signals do not require these
components.
0.1µ
1.0µ
1.0µ
Fig.2 External Component Connections
Application Recommendations
To avoid excess noise and instability in the final installation it is recommended that the following points be noted.
(a) A noisy or badly regulated power supply can
cause instability and/or variance of selected gains.
(b) Care should be taken on the design and layout of
the printed circuit board.
(c) All external components (Figure 2) should be
kept close to the FX009A package.
(d) Inputs and outputs should be screened wherever
possible.
(e) Tracks should be kept short.
(f) Analogue tracks should not run parallel to digital
tracks.
(g) A "Ground Plane" connected to VSS will assist in
eliminating external pick-up on the channel input and
output pins.
(h) Do not run high-level output tracks close to lowlevel input tracks.
(i) Input signal amplitudes should be applied with due
regard to Figure 3.
SINAD (dB)
60
50
Input Frequency = 1.0kHz
Input Level 0dB ref: = 775mVrms
Ch1 to Ch8 Gain Set to 0dB
40
1000.0
10.0
30
-40
25.0
75.0
-30
-20
110.0
250.0
775.0
-17
-10
0
1730.0
mVrms
7
INPUT LEVEL
Fig.3 SINAD vs Input Level – Typical Values
3
dB
The gain of each amplifier block (Channel 1 to Channel 8)
in the FX009A is set by a separate 8-bit data word ( bit 7
to bit 0 ). This 8-bit word, consisting of 4 Address bits (bit
7 to bit 4) and 4 Gain Control bits (bit 3 to bit 0), is loaded
to the Control Data Input in serial format using the external
data clock.
Data is loaded to the FX009A on the rising edge of the
Serial Clock. Loaded data is executed on the falling
(rising) edge of the Load/Latch (Load/Latch) pulse. Table
1 shows the format of each 4-bit Address word, Table 2
shows the format of each Gain Control word with Figure 4
describing the data loading operation and timing.
Table 1 Address Word Format
Table 2 Gain Control Word Format
Bit 7
MSB
Bit 6
Bit 5
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Bit 4
LSB
Channel
Selected
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
Data Loading
The 8-bit data word is loaded bit 7 first and bit 0 last.
Bit 7 must be a logic “1” to address the chip.
If bit 7 in the word is a logic “0” that 8-bit word will not be
executed. Figure 4 (below) shows the timing information
required to load and operate this device.
Bit 3
MSB
Bit2
Bit 1
Bit 0
LSB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Stage 1 to 7
(0.43dB)
Powersave
-3.0
-2.571
-2.143
-1.714
-1.286
-0.857
-0.428
0
0.428
0.857
1.286
1.714
2.143
2.571
3.0
Stage 8
(2.0dB)
Powersave
-14.0 dB
-12.0 dB
-10.0 dB
-8.0 dB
-6.0 dB
-4.0 dB
-2.0 dB
0
dB
2.0
dB
4.0
dB
6.0
dB
8.0
dB
10.0 dB
12.0 dB
14.0 dB
SERIAL DATA CLOCK
t PWL
SERIAL DATA IN
t DS
t PWH
Next
Clock
Pulse
8th
Clock
Pulse
tDH
(ONE 8-BIT WORD)
Logic ’1’
Loaded
First
BIT 7
Loaded Last
BIT 6
BIT 1
BIT 0
t LLD
LOAD/LATCH
t LLW
LOAD/LATCH
Timing
tLLD
tPWH
tDS
Serial Clock "High" Pulse Width
tPWL
Data Set-up Time
tDH
Serial Clock "Low" Pulse Width
Data Hold Time
Load/Latch Delay
tLLW
Load/Latch Pulse Width
tLLO
Load/Latch Over Time
Fig.4 Serial Control Data Loading Diagram
4
t LLO
Specification
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is
not implied.
Supply voltage
-0.3 to 7.0V
Input voltage at any pin (ref VSS = 0V)
-0.3 to (VDD + 0.3V)
Sink/source current (supply pins)
+/- 30mA
(other pins)
+/- 20mA
Total device dissipation @ TAMB 25°C
800mW Max.
Derating
10mW/°C
Operating temperature range: FX009A J
-30°C to +85°C (cerdip)
FX009A LG/LS
-30°C to +70°C (plastic)
Storage temperature range:
FX009A J
-55°C to +125°C (cerdip)
FX009A LG/LS
-40°C to +85°C (plastic)
Operating Limits
All device characteristics are measured under the following conditions unless otherwise specified:
VDD = 5.0V, TAMB = 25°C. Audio Level 0dB ref: = 775mVrms. Amplifier Gain Set = 0dB.
Characteristics
See Note
Min.
Static Values
Supply Voltage (VDD)
4.5
Supply Current –
– All Stages Quiescent
–
– All Stages Operating
–
Dynamic Values
Control Functions
Input Logic '1'
3.5
Input Logic '0'
–
Digital Input Impedances
0.5
Amplifier Stages (General)
Bandwidth (-3dB)
15.0
Output Impedance
–
Total Harmonic Distortion
1
–
Output Noise Level (per stage)
2
–
Onset of Clipping
3
–
Gain Variation
4
–
Interstage Isolation
–
“Trimmer” Stages (Ch1 – Ch7)
Gain
-3.0
Gain per Step (15 in No.)
–
Step Error
5
–
Input Impedance
100.0
“Volume” Stage (Ch8)
Gain
-14.0
Gain per Step (15 in No.)
–
Step Error
5
–
Input Impedance
50.0
Timing (Figure 4)
Serial Clock "High" Pulse Width (tPWH)
250
Serial Clock "Low" Pulse Width (tPWL)
250
Data Set-up Time
(tDS)
150
Data Hold Time
(tDH)
50
Load/Latch Over Time
(tLLO)
–
Load/Latch Delay
(tLLD)
200
Load/Latch Pulse Width
(tLLW)
150
Serial Data Clock Frequency
–
Notes
1. Gain Set 0dB, Input Level 1kHz -3.0dB (549mVrms).
2. a.c short-circuit input, measured in a 30kHz bandwidth.
3. See Figure 3.
4. Over temperature and supply voltage range.
5. With reference to a 1.0kHz signal.
5
Typ.
Max.
Unit
5.0
5.5
V
0.16
3.75
–
–
mA
mA
–
–
1.0
–
1.5
–
V
V
MΩ
–
0.8
0.35
65.0
1.73
–
60.0
–
3.0
0.5
–
0.1
–
kHz
kΩ
%
µVrms
Vrms
dB
dB
0.43
–
–
+3.0
–
±0.2
–
dB
dB
dB
kΩ
2.0
–
–
+14.0
–
±0.4
–
dB
dB
dB
kΩ
–
–
–
–
–
–
–
–
–
–
–
–
50.0
–
–
2.0
ns
ns
ns
ns
ns
ns
ns
MHz
Package Outlines
Handling Precautions
The FX009A is available in the package styles outlined
below. Mechanical package diagrams and
specifications are detailed in Section 10 of this
document.
Pin 1 identification marking is shown on the relevant
diagrams and pins on all package styles number anticlockwise when viewed from the top.
The FX009A is a CMOS LSI circuit which includes
input protection. However precautions should be
taken to prevent static discharges which may cause
damage.
FX009AJ 24-pin cerdip DIL
FX009ALG 24-pin quad plastic encapsulated
bent and cropped
(L1)
(J4)
NOT TO SCALE
NOT TO SCALE
Max. Body Length
Max. Body Width
32.00mm
13.36mm
Max. Body Length
Max. Body Width
10.25mm
10.25mm
FX009ALS 24-lead plastic leaded chip
carrier
(L2)
NOT TO SCALE
Ordering Information
FX009AJ
24-pin cerdip DIL
(J4)
FX009ALG 24-pin quad plastic
encapsulated bent and cropped
(L1)
FX009ALS 24-lead plastic leaded chip
carrier
(L2)
Max. Body Length
Max. Body Width
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied
and CML reserves the right at any time without notice to change the said circuitry.
6
10.40mm
10.40mm
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor
companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc
(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst
maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)
Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits.
These companies are all 100% owned operating companies of the CML Microsystems Plc
Group and these changes are purely changes of name and do not change any underlying legal
entities and hence will have no effect on any agreements or contacts currently in force.
CML Microcircuits Product Prefix Codes
Until the latter part of 1996, the differentiator between products manufactured and sold from
MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX
respectively. These products use the same silicon etc. and today still carry the same prefixes.
In the latter part of 1996, both companies adopted the common prefix: CMX.
This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits
(UK)Ltd
CML Microcircuits
(USA) Inc.
CML Microcircuits
(Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon,
Essex, CM9 6WG, England
Tel: +44 (0)1621 875500
Fax: +44 (0)1621 875600
[email protected]
www.cmlmicro.com
4800 Bethania Station Road,
Winston-Salem, NC 27105, USA
Tel: +1 336 744 5050,
0800 638 5577
Fax: +1 336 744 5054
[email protected]
www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/
06 Mactech Industrial Building,
Singapore 349307
Tel: +65 7450426
Fax: +65 7452917
[email protected]
www.cmlmicro.com
D/CML (D)/1 February 2002
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