Fox FXO-PC735RFC-2125 Fibre channel Datasheet

for FIBRE
LVPECL 7 x 5mm
CHANNEL
3.3V
50ppm
Model: FXO-PC735RFC-212.5
XO
Freq: 212.5MHz
Features
Low Jitter
Low Cost
Tri-State Enable / Disable Feature
Industry Standard Package
Gold over Nickel Termination Finish
V DD
Enable / Disable
FOX
X PRESSO
OUTPUT
ASICs
GND
Electrical Characteristics
Parameters
Frequency
Symbol
Condition
FO
212.5 MHz
Frequency Stability 1
Temperature Range
Supply Voltage
TO
TSTG
VDD
Input Current
IDD
Output Load
Differential
Start-Up Time
Standard operating
Storage
Standard
Standard Load
Standard
TS
50 ppm
-40°C to +85°C
-55°C to +125°C
3.3V ± 5%
120 mA
50 ohms into VDD -2.0VDC
10 mS
Output Enable / Disable Time
Moisture Sensitivity Level
Termination Finish
Maximum Value
(unless otherwise noted)
100 nS
MSL
1
Au
Note 1 – Stability is inclusive of 25°C tolerance, operating temperature range, input voltage change, load change, aging, shock and vibration.
Output Wave Characteristics
Parameters
Symbol
Output LOW Voltage
Output HIGH Voltage
Output Symmetry
VOL
VOH
Output Enable (PIN # 1) Voltage
VIH
Output Disable (PIN # 1) Voltage
Cycle Rise Time
Cycle Fall Time
VIL
TR
TF
Condition
Standard Load
Standard Load
@ 50% Vp-p Level
Maximum Value
(unless otherwise noted)
1.35V ~ 1.65V
2.055V ~ 2.405V
45% ~ 55%
≥70% VDD
20% ~ 80% Vp-p
80% ~ 20% Vp-p
DWG- 100751 | Rev. 07/13/2010
DWG- | Rev. 07/13/2010
Page 1 of 2
© 2010 FOX ELECTRONICS | ISO9001:2000 Certified | FOXONLINE
≤30% VDD
400 pS
400 pS
for FIBRE
LVPECL 7 x 5mm
CHANNEL
3.3V
50ppm
Model: FXO-PC735RFC-212.5
XO
Freq: 212.5MHz
Dimensional Drawing & Pad Layout
Phase Jitter & Time Interval Error (TIE) (Typical Measurements)
Frequency
Phase Jitter
TIE
(12kHz to 20MHz)
(Sigma of Jitter Distribution)
Units
212.5 MHz
1.05
3.6
pS RMS
Phase Jitter is integrated from HP3048 Phase Noise Measurement System; measured directly into 50 ohm input; VDD = 3.3V.
TIE was measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software; VDD = 3.3V.
Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)
Random & Deterministic Jitter Composition (Typical Measurements)
Frequency
Random (Rj)
Deterministic (Dj)
(pS RMS)
(pS P-P)
1.22
8.6
212.5 MHz
Total Jitter (Tj)
(14 x Rj) + Dj
26.1 pS
Rj and Dj, measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software.
Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)
Pin Functional Description
Pin #
1
2
3
4
5
6
NOTES:
Name
E/D
NC
Type
1
GND
Output
Output 2
VDD 3
1
2
3
Logic
2
Function
Enable / Disable Control of Output (0 = Disabled)
No Connection – Leave Open
Ground
Output
Output
Power
Electrical Ground for VDD
LVPECL Oscillator Output
Complementary LVPECL Output
Power Supply Source Voltage
Includes pull-up resistor to VDD to provide output when the pin (1) is No Connect. (Also see note 2)
An optional pin # 2 Enable / disable is available.
Installation should include a 0.01µF bypass capacitor placed between VDD
(Pin 6) and GND (Pin 3) to minimize power supply line noise.
DWG- | Rev. 07/13/2010
Page 2 of 2
© 2010 FOX ELECTRONICS | ISO9001:2000 Certified | FOXONLINE
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