ETC1 GLT4160L04E-60TC 4m x 4 cmos dynamic ram with extended data output Datasheet

G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Features :
Description :
∗
∗
∗
∗
The GLT4160L04 is a high-performance
CMOS dynamic random access memory
containing 16,777,216 bits organized in a x4
configuration. The GLT4160L04 offers page
cycle access with Extended Data Output.
The GLT4160L04 has 11 row- and 11
column-addresses, and accepts 2048-cycle
refresh in 32 ms.
The GLT4160L04 provides EDO PAGE
MODE operation which allows for fast data
access within a row-address defined
boundary, up to 2048 x 4 bits with cycle
times as short as 18ns.
∗
∗
∗
∗
∗
4,194,304 words by 4 bits organization.
Fast access time and cycle time
Low power dissipation.
Read-Modify-Write, RAS -Only Refresh,
CAS -Before- RAS Refresh, Hidden Refresh.
2,048 refresh cycles per 32ms.
Available in 300 mil 26(24) SOJ and TSOPII.
3.3V±0.3V Vcc Power Supply voltage.
All inputs and Outputs are LVTTL compatible.
Extended Data-Out (EDO) Page access
cycle.
∗ Self-refresh Capability. (S-Version).
HIGH PERFORMANCE
40
50
60
70
Max. RAS Access Time, (tRAC)
40 ns
50 ns
60 ns
70 ns
Max. Column Address Access Time, (tAA)
20 ns
25 ns
30 ns
35 ns
Min. Extended Data Out Page Mode Cycle Time, (tPC)
18 ns
20 ns
25 ns
30 ns
Min. Read/Write Cycle Time, (tRC)
70 ns
84 ns
104 ns 124 ns
Max. CAS Access Time (tCAC)
12 ns
13 ns
15 ns
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20 ns
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GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Pin Configuration :
GLT4160L04
300mil 26(24) TSOPII
GLT4160L04
300mil 26(24) SOJ
Vcc
DQ0
DQ1
WE
RAS
NC
1
2
3
4
5
6
26
25
24
23
22
21
VSS
DQ3
DQ2
CAS
OE
A9
Vcc
DQ0
DQ1
WE
RAS
NC
1
2
3
4
5
6
26
25
24
23
22
21
VSS
DQ3
DQ2
CAS
OE
A9
A10
A0
A1
A2
A3
VCC
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
A10
A0
A1
A2
A3
VCC
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
Pin Descriptions:
Name
A0 - A10
Function
RAS
Address Inputs
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
DQ0 - DQ3
VCC
VSS
NC
Data Inputs / Outputs
+3.3V Power Supply
Ground
No Connection
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GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Absolute Maximum Ratings*
Capacitance*
TA=25°C, VCC=3.3V±0.3V, VSS=0V
Operating Temperature, TA (ambient)
Symbol
Parameter
.............................................….0°C to
+70°C
CIN1 Address Input
For Extended Temperature……………..-20°C to 85°C
CIN2 RAS, CAS, WE, OE
Storage Temperature(plastic)............-55°C to +150°C
Voltage Relative to VSS........................-0.5V to + 4.6V
COUT Data Input/Output
Short Circuit Output Current...............................20mA
Power Dissipation...............................................1.0W
*Note: Operation above Absolute Maximum Ratings can
aversely affect device reliability.
Max. Unit
5
pF
7
pF
7
pF
*Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l
l
All voltages are referenced to GND.
After power up, wait more than 200µs and then, execute eight CAS -before- RAS or RAS -only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
WE
CAS
4
DATA-IN
BUFFER
DATA-OUT
BUFFER
NO.2 CLOCK
GENERATOR
DQ 0
DQ 1
4
DQ 2
DQ 3
4
OE
COLUMN
DECODER
11
2048
REFRESH
CONTROLLER
REFRESH
COUNTER
11
RAS
ROW
ADDRESS
BUFFERS(11)
NO.1 CLOCK
GENERATOR
4
SENSE AMPLIFIERS
I/O GATING
2048
11
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
11
COLUMNADDRESS
BUFFER(11)
2048
2048 x 1024 x 4
MEMORY
ARRAY
VDD
VSS
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GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Truth Table:
Function
ADDRESS
tR
tC
DATA-IN/OUT
DQ1-DQ4
RAS
CAS
WE
OE
Standby
H
H→X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
READ WRITE
L
L
H→L
L→H
ROW
COL
Data-Out,Data-In
EDO-PAGE-MODE
1st Cycle
L
H→L
H
L
ROW
COL
Data-Out
READ
2nd cycle
L
H→L
H
L
n/a
COL
Data-Out
EDO-PAGE-MODE
1st Cycle
L
H→L
L
X
ROW
COL
Data-In
EARLY-WRITE
2nd cycle
L
H→L
L
X
n/a
COL
Data-In
EDO-PAGE-MODE
1st Cycle
L
H→L
H→L
L→H
ROW
COL
Data-Out,Data-In
READ-WRITE
2nd cycle
L
H→L
H→L
L→H
n/a
COL
Data-Out,Data-In
L
H
X
X
ROW
n/a
High-Z
L→H→L
L
H
L
ROW
COL
Data-Out
WRITE L→H→L
L
L
X
ROW
COL
Data-In
RAS -ONLY REFRESH
HIDDEN REFRESH
READ
CBR REFRESH
H→L
L
H
X
X
X
High-Z
SELF REFRESH
H→L
L
H
X
X
X
High-Z
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GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, -20°C to 85°C VCC=3.3V±0.3V, VSS=0V, unless otherwise specified.
Sym.
ILI
ILO
ICC1
ICC2
ICC3
ICC4
ICC5
Parameter
Input Leakage Current
(any input pin)
Output Leakage Current
(for High-Z State)
Operating Current,
Random READ/WRITE
Standby Current (TTL)
Refresh Current,
0V ≤ VIN ≤ VCC+0.3V
(All other pins not under
test=0V)
0V ≤ Vout ≤ VCC
Output is disabled (Hiz)
tRC = tRC (min.)
RAS cycling, CAS at VIH
Operating Current,
EDO Page Mode
RAS at VIL, CAS address
Standby Current, (CMOS)
Min.
-5
Self refresh Current
-5
tRAC = 40ns
tRAC = 50ns
tRAC = 60ns
tRAC = 70ns
cycling:tPC=tPC(min.)
RAS , CAS address cycling:
tRC=tRC (min.)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Unit Notes
+5
+5
130
120
80
70
tRAC = 40ns
tRAC = 50ns
tRAC = 60ns
tRAC = 70ns
tRAC = 40ns
tRAC = 50ns
tRAC = 60ns
tRAC = 70ns
tRAC = 40ns
tRAC = 50ns
tRAC = 60ns
tRAC = 70ns
130
120
80
70
130
120
80
70
130
120
80
70
µA
1,2
mA
mA
2
mA
1,2
mA
mA
1
300
µA
1,5
300
µA
+0.8
VCC+0.3
0.4
V
V
V
V
RAS ≥VCC-0.2V,
RAS = CAS =0.2V,
WE = OE = A0~A10=VCC-0.2V or
0.2V
DQ0~DQ3=VCC-0.2V,0.2V or
Open
VIL
VIH
VOL
VOH
Max.
µA
CAS ≥VCC-0.2V,
All other inputs VSS
ICC7
Typ
1
tRC = tRC (min.)
Refresh Current,
Access
Time
RAS , CAS at VIH
other inputs ≥VSS
RAS -Only
CAS Before RAS
ICC6
Test Conditions
-0.3
2.0
IOL = 2mA
IOH = -2mA
2.4
3
4
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open.
2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle
in random Read/Write and EDO Fast Page Mode.
3. Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to –1V for a period not to exceed 15ns. All AC
parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.
4. Specified VIH(max.) is steady state operation . During transitions VIH(max.) may overshoot to VCC+1V for a period not to exceed 15ns. All AC
parameters are measured with VIL(min.) ≥ VSS and VIH(max.) ≤ VCC .
5. S-Version.
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GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
AC Characteristics
TA =0°C to 70°C , -20°C to 85°C VCC = 3.3 V ± 0.3V, VIH/VIL = 3/0 V, VOH/VOL = 2/0.8V
An initial pause of 200 µs and 8 CAS -before- RAS or RAS -only refresh cycles are required after power-up.
40
Parameter
Read or Write Cycle Time
50
60
70
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
tRC
70
84
104
124
ns
tRWC
91
116
140
170
ns
RAS Precharge Time
tRP
25
30
40
50
ns
RAS Pulse Width
tRAS
40
Access Time from RAS
tRAC
40
50
tCAC
12
tAA
20
Read Modify Write Cycle Time
Access Time from CAS
Access Time from Column Address
10K
50
10k
10k
ns
60
70
ns
13
15
20
ns 1,5,10
25
30
35
ns
10k
tCLZ
0
CAS to Output High-Z
tCEZ
3
RAS Hold Time
tRSH
12
13
15
20
ns
CAS Hold Time
tCSH
34
38
45
50
ns
CAS Pulse Width
tCAS
7
10k
8
10k
10
10k
15
10k
ns
RAS to CAS Delay Time
tRCD
18
28
20
37
20
45
20
50
ns
RAS to Column Address Delay Time
tRAD
13
20
15
25
15
30
15
35
ns
tCRP
5
5
5
5
ns
tASR
0
0
0
0
ns
Row Address Hold Time
tRAH
8
10
10
10
ns
Column Address Set-Up Time
tASC
0
0
0
0
ns
Column Address Hold Time
tCAH
6
8
10
15
ns
Column Address to RAS Lead Time
tRAL
20
25
30
35
ns
8
3
3
70
CAS to Output Low-Z
CAS to RAS Precharge Time
Row Address Set-Up Time
3
60
13
3
3
15
3
1,2,3
1,5,6
ns
20
ns
7
Column Address Hold Time Referenced to RAS
Read Command Set-Up Time
tAR
34
40
45
50
ns
tRCS
0
0
0
0
ns
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
0
ns
4
Read Command Hold Time Referenced to RAS
Write Command Set-Up Time
tRRH
0
0
0
0
ns
4
tWCS
0
0
0
0
ns
8,9
Write Command Hold Time
tWCH
6
10
10
15
ns
Write Command Pulse Width
tWP
6
10
10
15
ns
Write Command to RAS Lead Time
tRWL
12
13
15
30
ns
Write Command to CAS Lead Time
tCWL
8
8
10
15
ns
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GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
AC Characteristics
40
Parameter
50
60
70
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Data Set-Up Time
tDS
0
0
0
0
ns
Data Hold Time
tDH
7
8
10
15
ns
Data Hold Time Referenced to RAS
tDHR
36
40
45
50
ns
RAS to WE Delay Time
tRWD
54
67
79
94
ns
CAS to WE Delay Time
tCWD
24
30
34
44
ns
Column Address to WE Delay Time
tAWD
32
42
49
59
ns
CAS Precharge to WE Delay
tCPWD
47
47
54
64
ns
RAS to CAS Precharge Time
tRPC
0
5
5
5
ns
tCPT
20
20
20
25
ns
CAS precharge time ( CAS Before RAS counter
test cycle)
Access Time from CAS Precharge
EDO Page Mode Cycle Time
22
tCPA
28
35
40
ns
tPC
18
20
25
30
ns
tPRWC
50
47
56
71
ns
CAS Precharge Time (EDO Page Mode)
tCP
6
8
10
10
ns
RAS Pulse Width (EDO Page Mode Only)
tRASP
40
70
100k ns
tRHCP
30
40
ns
EDO Page Mode Read-Modify-Write Cycle Time
RAS Hold Time from CAS precharge
100k
50
100k
30
12
60
100k
35
13
15
0
20
ns
Access Time from OE
tOEA
OE to Data Delay Time
tOED
8
13
15
20
ns
OE to Output Low-Z
tOLZ
3
3
0
0
ns
OE to Output High-Z
tOEZ
3
WE to Data Delay
tWED
15
15
15
20
ns
OE Command Hold Time
tOEH
7
13
15
20
ns
Data Output Hold after CAS low
tDOH
3
5
5
5
ns
RAS to Output High-Z
tREZ
3
8
3
13
3
15
3
20
ns
WE to Output High-Z
tWEZ
3
10
3
13
3
15
3
20
ns
OE to CAS Hold Time
tOCH
5
5
5
5
ns
CAS Hold Time to OE
tCHO
5
5
5
5
ns
OE Precharge Time
tOEP
5
5
5
5
ns
WE Puts width (EDO mixed read write cycle)
tWPE
5
5
5
5
ns
CAS Set-Up Time for CAS -before- RAS Cycle
tCSR
5
5
5
5
ns
8
3
13
3
15
3
20
ns
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GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
40
Parameter
CAS Hold Time for CAS -before- RAS Cycle
WE to RAS precharge time ( CAS Before RAS
refresh )
WE to RAS hold time ( CAS Before RAS
refresh )
Transition Time
50
60
70
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
tCHR
8
10
10
15
ns
tWRP
10
10
10
10
ns
tWRH
10
10
10
10
ns
tT
2
50
2
50
2
50
2
50
ns
Refresh Period (2,048 cycles)
tREF
32
32
32
32
ms
Refresh Period (S-Version)
tREF
128
128
128
128
ms
RAS Pulse Width ( CAS Before RAS Self refresh
)
tRASS
100
100
100
100
µs
tRPS
70
90
110
130
ns
tCHS
-50
-50
-50
-50
ns
RAS precharge Time ( CAS Before RAS Self
refresh )
CAS Hold Time ( CAS Before RAS Self refresh )
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GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
TEST MODE CYCLE
40
Parameter
Random read or write cycle time
50
60
70
Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit
Notes
tRC
89
89
109
129
ns
Read-modify-write cycle time
tRWC
121
121
145
175
ns
Access time from RAS
tRAC
55
55
65
75
ns
1,2,3,7
tCAC
18
18
20
25
ns
1,3,7
tAA
30
30
35
40
ns
1,2,7
Access time from CAS
Access time from column address
RAS pulse width
tRAS
55
10k
55
10k
65
10k
75
10k
ns
CAS pulse width
tCAS
13
10k
13
10k
15
10k
20
10k
ns
RAS hold time
tRSH
18
18
20
25
ns
CAS hold time
tCSH
43
43
50
55
ns
Column address to RAS lead time
tRAL
30
30
35
40
ns
CAS to WE delay time
tCWD
35
35
39
49
ns
8
tRWD
72
72
84
99
ns
8
tAWD
47
47
54
64
ns
8
CAS Precharge to WE delay time
EDO Page Mode cycle time
tCPWD
52
52
59
69
ns
8
tPC
25
25
30
35
ns
EDO page mode read-modify-write cycle time
tPRWC
53
53
61
76
ns
RAS Pulse width (EDO page cycle)
tRASP
55
Access time form CAS precharge
tCPA
33
33
OE access time
tOEA
18
18
OE to data delay
tOED
18
18
20
25
ns
tOEH
18
18
20
25
ns
tWTS
10
10
10
10
ns
tWTH
10
10
10
10
ns
RAS to WE delay time
Column address to WE delay time
OE command hold time
Write command set-up time (Test mode in)
Write command hold time (Test mode in)
100k
55
100k
65
100k
75
100k
ns
40
45
ns
20
25
ns
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GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Notes:
1. Measure with a load equivalent to one TTL input and 100 pF.
2. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tAA
dominant.
3. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRCD (max.), access time will be
controlled by tCAC.
4. Either tRRH or tRCH must be satisfied for a Read Cycle.
5. Access time is determined by the longest of tAA, tCAC and tCPA.
6. Assumes that tRAD ≥ tRAD (max.).
7. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.)
is specified as a reference point only. If tRAD is greater than the specified tRAD (max.)
limit, the access time is controlled by tCAA and tCAC.
8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
9. tWCS (min.) must be satisfied in an Early Write Cycle.
10. tDS and tDH are referenced to the latter occurrence of CAS or WE .
11. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 2 ns.
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GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Read CYCLE
tRC
tRAS
tRP
VIH-
RAS
VIL-
tCSH
tCRP
tRCD
tCRP
tRSH
VIH-
CAS
tCAS
VIL-
tRAD
tASR
Address
VIHVIL-
tRAL
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tAR
tRCH
tRRH
tRCS
VIH-
WE
VIL-
tCEZ
tAA
tOEZ
VIH-
OE
tOEA
VIL-
tCAC
tCLZ
tRAC
DQ
VOHDATA-OUT
VOLDon't Care
Early Write Cycle
NOTE : DOUT = OPEN
tRC
RAS
tRP
tRAS
VIHVIL-
tCSH
tCRP
CAS
tRCD
tRSH
VIH-
tCRP
tCAS
VIL-
VIH-
Address
VIL-
tASR
tRAH
tRAD
tASC
ROW
ADDRESS
tRAL
tCAH
COLUMN
ADDRESS
tCWL
tRWL
tAR
VIH-
WE
tWCS
tWCR
tWCH
tWP
VIL-
VIH-
OE
VIL-
tDHR
tDS
tDH
VIH-
DQ
VIL-
DATA - IN
Don't Care
G-Link Technology
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 11 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
OE Controlled Write Cycle NOTE : DOUT = OPEN
tRC
RAS
tRP
tRAS
VIHVIL-
tCSH
tCRP
CAS
tRCD
tCRP
tRSH
VIH-
tCAS
VIL-
VIH-
Address
VIL-
tRAL
tCAH
tRAD
tASC
tASR
tRAH
ROW
ADDRESS
COLUMN
ADDRESS
tCWL
tRWL
tRCS
VIH-
WE
tWP
VIL-
VIH-
OE
tOEH
tOED
VIL-
tDS
tDH
VIH-
DQ
DATA - IN
VIL-
Don't Care
Read - Modify - Write Cycle
tRC
RAS
VIHVIL-
tCRP
CAS
tRP
tRAS
tRCD
tCRP
tRSH
VIH-
tCAS
VILtCSH
tASR
tRAD
tCAH
tASC
Address
VIHVIL-
tRAH
ROW
ADDR.
COLUMN
ADDRESS
tAWD
tRWL
tCWL
tCWD
WE
OE
VIHtWP
VIL-
VIH-
tOEA
VILtCLZ
tAA
DQ
VI/OHVI/OL-
tRAC
tCAC
tOED
tOEZ
VALID
DATA-OUT
tDS
tDH
VALID
DATA-IN
Don't Care
G-Link Technology
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 12 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
EDO Page Mode Read Cycle NOTE : DOUT = OPEN
tRASP
tRP
VIH-
tRHCP
RAS
VIL-
tCSH
tCRP
tRCD
tPC
tCAS
VIHVIL-
VIL-
tCAS
tCAS
tCAH
tASC
tCAH
tRAD
tCSR
VIH-
tPC
tCP
tCAS
CAS
Address
tPC
tCP
tCP
tRAH
tASC
COLUMN
ADDRESS
ROW
ADDR.
tCAH
tCAH tASC
tASC
COLUMN
ADDRESS
COL.
ADDR.
COL.
ADDR.
tRRH
tRCS
tRCH
VIH-
WE
tCAC
tAA
tAA
VIL-
tCPA
tCPA
tCHO
tOEP
tOCH
tCAC
tOEA
VIH-
tCPA
tCAC
tAA
tOEA
OE
VIL-
tCAC
tRAC
tOLZ
VOH-
DQ
tCLZ
VOL-
tOEP
tOEZ
tDOH
tOEZ
VALID
DATA-OUT
tOEZ
VALID
DATA-OUT
VALID
VALID
DATA-OUT DATA-OUT
VALID
DATA-OUT
Don't Care
EDO Page Mode Early Write Cycle NOTE : DOUT = OPEN
tRASP
tRP
tRHCP
VIH-
RAS
VIL-
tPC
tCRP
tRCD
tCAS
tCP
tPC
tCAS
tCP
tRSH
tCAS
VIH-
CAS
VIL-
tRAD
tASR
Address
VIHVIL-
tRAH
tASC
ROW
ADDR.
COLUMN
ADDRESS
tWCS
VIH-
WE
tCSH
tCAH
tASC
tCAH
COLUMN
ADDRESS
tWCH
tWCS
tWP
tWP
tWCH
tCAH
tASC
COLUMN
ADDRESS
tWCS
tWCH
tWP
VIL-
VIH-
OE
VIL-
tDS
VIH-
DQ
VIL-
tDH
VALID
DATA-IN
tDS
VALID
DATA-IN
tDS
tDS
tDS
VALID
DATA-IN
Don't Care
G-Link Technology
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 13 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
EDO Page Mode Read - Modify - Write Cycle NOTE : DOUT = OPEN
tRASP
RAS
VIH-
tRP
tCSH
VIL-
tRCD
tCAS
tRSH
tCAS
tCP
tCRP
VIH-
CAS
VIL-
tASR
VIH-
Address
VIL-
tRAD
tRAH
tASC
ROW
ADDR.
tPRWC
tRAL
tCAH
tCAH
tASC
COL.
ADDR.
COL.
ADDR.
tRWL
tCWL
tCWL
tRCS
VIH-
WE
tCWD
tWP
tCWD
VIL-
tWP
tAWD
tAWD
tCPWD
tOEH
tRWD
OE
VIH-
tOEA
tOEA
tDH
VIL-
tCAC
tAA
tCAC
tAA
tOED
tOEZtDS
tRAC
tDH
tOED
tOEZ
tDS
VI/OH-
DQ
VI/OL-
tCLZ
tCLZ
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
Don't Care
EDO PAGE READ AND WRITE MIXED CYCLE
tRP
tRASP
VIHVIL-
RAS
VIHVIL-
CAS
tASR
ADDRESS
VIHVIL-
WE
VIHVIL-
OE
VIHVIL-
tHPC
tRAH
tASC
tCAS
ROW
ADDR
tRCS
VI/OH-
tCP
tHPC
tCP
tCAS
tCAS
tCAH
tASC
COL.
ADDR
tASC
tCAH
COLUMN
ADDRESS
tRCH
tRCS
tCAH
COLUMN
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tRCH
tRCH
tWCS tWCH
tWPE
DQ0~DQ3 VI/OL-
tHPC
tCP
tCLZ
tCPA
tOEA
tCAC tWEZ
tAA
tRAC
VALID
DATA-OUT
tWED
tWEZ
VALID
DATA-OUT
tDH
tDS
VALID
DATA-IN
tAA
tREZ
VALID
DATA-OUT
Don't Care
G-Link Technology
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 14 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
CAS - Before - RAS Refresh Cycle
tRC
tRC
tRP
tRAS
tRAS
tRP
VIH-
RAS
VIL-
tCSR
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
VIH-
CAS
VIL-
tWRH
tWRP
tWRP
tWRH
VIH-
WE
VIL-
Remark Address, OE : Don’t care DQ : Hi - Z
RAS -Only Refresh Cycle
tRC
tRC
tRP
tRAS
tRAS
tRP
VIH-
RAS
VIL-
tCRP
tRPC
tCRP
VIH-
CAS
VIL-
tRAH
tASR
VIH-
Address
ROW
ADDRESS
VIL-
Remark
tASR
tRAH
ROW
ADDRESS
WE, OE : Don’t care DQ : Hi - Z
Hidden Refresh Cycle ( Read )
tRC
tRC
tRP
tRAS
RAS
tRAS
tRP
VIHVIL-
tCRP
tRCD
tRSH
tCHR
VIH-
UCAS,LCAS
VIL-
tRAD
tASR
Address
VIHVIL-
tRAL
tCAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tRCS
tRRH
tWRP
tWRH
VIH-
WE
tAA
VIL-
tOEA
VIH-
OE
VIL-
tCAC
tRAC
tCLZ
tWEZ
tOEZ
tCEZ
tREZ
VIH-
DQ
OPEN
DATA-OUT
VIL-
Don't Care
G-Link Technology
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 15 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Hidden Refresh Cycle ( Write ) NOTE : DOUT = OPEN
tRC
tRP
tRAS
RAS
tRAS
tRP
VIHVIL-
tRCD
tCRP
tRSH
tCHR
VIH-
CAS
VIL-
tRAD
tASC
Address
VIHVIL-
tCAH
ROW
ADDRESS
tRSH
tASC
tCAH
COLUMN
ADDRESS
tWCS
VIH-
WE
tWCH
tWRP
tWRH
tWP
VIL-
VIH-
OE
VIL-
tDS
DQ
tDH
VIHDATA-IN
VIL-
Don't Care
G-Link Technology
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 16 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
CAS-Before RAS Refresh Counter Test Cycle
tRP
tRAS
VIHRAS VIL-
tCSR
tRSH
tCAS
tCPT
tCHR
VIHCAS VIL-
tRAL
tASC
Address VIH-
COLUMN
ADDRESS
VIL-
Read Cycle
tCAH
tWRP
tWRH
tAA
tCAC
tRCS
tRRH
tRCH
VIH-
WE VIL-
tOEA
VIH-
OE VIL-
tOEZ
tCLZ
VOH-
DQ VOL-
Write Cycle
tCEZ
VALID DATA-OUT
tWRP
tWRH
tRWL
tCWL
tWCH
tWCS
VIHWE VIL-
tWP
VIH-
OE VIL-
tDS
VIHDQ VIL-
OPEN
VALID DATA-IN
Read-Modify-Write
VIH-
WE VIL-
tDH
tRCS
tAWD
tCWD
tCWL
tRWL
tWP
tWRP
tWRH
tCAC
tAA
tOEA
VIH-
OE VIL-
tOED
tCLZ
tOEZ
tDH
tDS
VI/OH-
DQ VI/OL-
VALID
DATA-OUT
VALID
DATA-IN
Don't Care
G-Link Technology
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 17 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
TEST MODE IN CYCLE
tRC
tRP
RAS
VIHVIL-
tRP
tRAS
tRPC
tRPC
tCP tCSR
CAS
VIHVIL-
WE
VIHVIL-
tWTS
tCHR
tWTH
tCEZ
OPEN
VI/OHDQ V I/OL-
Don't Care
Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the x
16-bit organization during test mode. Don’t care about the input levels of the CAS input A0, A1 .
(1) Setting the mode
Executing the test mode cycle (WE , CAS before RAS refresh cycle ) sets the test mode.
(2) Write / read operation
When either a “0” or a “1” is written to the input pin in test mode, this data is written to 16 bits of memory
cell.
Next, when the data is read from the output pin at the same address, the cell be checked.
Output = “1” Normal write (all memory cells)
Output = “0” Abnormal write
(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS
refresh cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS
refresh’s internal counter.
(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh
cycle.
G-Link Technology
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 18 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
CAS-BEFORE-RAS SELF REFRESH CYCLE
tRP
RAS
VIHVIL-
tRPC
tCP
CAS
tRPS
tRASS
VIHVIL-
tRPC
tCHS
tCSR
tCEZ
DQ
VI/OHVI/OL-
WE
VIHVIL-
OPEN
tWRP
tWRH
Don't Care
NOTE : OE , Address = Don’t Care
G-Link Technology
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 19 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Ordering Information
Part Number
SPEED
POWER
FEATURE
TEMPERATURE
PACKAGE
GLT4160L04-40J3
GLT4160L04-50J3
GLT4160L04-60J3
GLT4160L04-70J3
GLT4160L04E-40J3
GLT4160L04E-50J3
GLT4160L04E-60J3
GLT4160L04E-70J3
GLT4160L04S-40J3
GLT4160L04S-50J3
GLT4160L04S-60J3
GLT4160L04S-70J3
GLT4160L04SE-40J3
GLT4160L04SE-50J3
GLT4160L04SE-60J3
GLT4160L04SE-70J3
GLT4160L04-40TC
GLT4160L04-50TC
GLT4160L04-60TC
GLT4160L04-70TC
GLT4160L04E-40TC
GLT4160L04E-50TC
GLT4160L04E-60TC
GLT4160L04E-70TC
GLT4160L04S-40TC
GLT4160L04S-50TC
GLT4160L04S-60TC
GLT4160L04S-70TC
GLT4160L04SE-40TC
GLT4160L04SE-50TC
GLT4160L04SE-60TC
GLT4160L04SE-70TC
40ns
50ns
60ns
70ns
40ns
50ns
60ns
70ns
40ns
50ns
60ns
70ns
40ns
50ns
60ns
70ns
40ns
50ns
60ns
70ns
40ns
50ns
60ns
70ns
40ns
50ns
60ns
70ns
40ns
50ns
60ns
70ns
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Self Refresh
Self Refresh
Self Refresh
Self Refresh
Self Refresh
Self Refresh
Self Refresh
Self Refresh
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Self Refresh
Self Refresh
Self Refresh
Self Refresh
Self Refresh
Self Refresh
Self Refresh
Self Refresh
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
EDO
Commercial
Commercial
Commercial
Commercial
Extended
Extended
Extended
Extended
Commercial
Commercial
Commercial
Commercial
Extended
Extended
Extended
Extended
Commercial
Commercial
Commercial
Commercial
Extended
Extended
Extended
Extended
Commercial
Commercial
Commercial
Commercial
Extended
Extended
Extended
Extended
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
SOJ 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
TSOPII 300mil 26(24)L
G-Link Technology
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 20 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Parts Numbers (Top Mark) Definition :
GLT 4 160 L 04 S E
4 : DRAM
5 : Synchronous
DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
9 : SGRAM
-SRAM
CONFIG.
064 : 8K
256 : 256K
512 : 512K
100 : 1M
04 : x04
08 : x08
16 : x16
32 : x32
-DRAM
10 : 1M(C/EDO)
11 : 1M(C/FPM)
12 : 1M(H/EDO)
13 : 1M(H/FPM)
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
160 : 16M(EDO)
161 : 16M(FPM)
640 : 64M(EDO)
641 : 64M(FPM)
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
VOLTAGE
Blank : 5V
L : 3.3V
M : 2.5V
N : 2.1V
-SDRAM
40 : 4M
160 : 16M
320 : 32M,4Bank
321 : 32M,2Bank
640 : 64M
- 40 J3
POWER
Blank : Standard
S : Self Refresh Low Power
L : Low Power
LL : Low Low Power
SL : Super Low Power
25 : 25ns
28 : 28ns
30 : 30ns
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
70 : 70ns
80 : 80ns
100 : 100ns
SDRAM :
5 : 5ns/200 MHZ
5.5 : 5.5ns/182 MHZ
6 : 7ns/166 MHZ
7 : 8ns/125 MHZ
10 : 10ns/100 MHZ
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
ST : sTSOP(Type I)
TC : TSOPll (40/44)
TD : TSOPII (44/50)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
FG : 48Pin BGA 9x12
FH : 48Pin BGA 8x10
FI : 48Pin BGA 6x8
Temperature Range
E : Extended Temperature
I : Industrial Temperature
Blank : Commercial Temperature
G-Link Technology
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 21 -
G -LINK
GLT4160L04
4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
May 2001 (Rev.3.1)
Package Information
300mil 24/26 Lead Thin Small Outline Package SOJ
300mil 24/26 Lead Thin Small Outline Package (TSOP) TYPE II
G-Link Technology
G-Link Technology Corporation,Taiwan
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
6F, No. 24-2, Industry E. RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 22 -
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