Gennum GS1575A Gs1575a / gs9075a hd-linx-r ii multi-rate sdi automatic reclocker Datasheet

GS1575A / GS9075A HD-LINX® II
Multi-Rate SDI Automatic Reclocker
GS1575A / GS9075A Data Sheet
Features
GS1575A
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SMPTE 292M, 259M and 344M compliant
Supports data rates of 143, 177, 270, 360, 540, 1483.5,
1485 Mb/s
Supports DVB-ASI at 270Mb/s
Pb-free and RoHS Compliant
Auto and Manual Modes for rate selection
Standards indication in Auto Mode
4:1 input multiplexer
Loss of Signal (LOS) Output
Lock Detect Output
On-chip Input and Output Termination
Differential 50Ω inputs and outputs
Mute, Bypass and Autobypass functions
SD/HD indication output to control GS1528A Dual
Slew-Rate Cable Driver
Single 3.3V power supply
Operating temperature range: 0°C to 70°C
GS9075A
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SMPTE 259M and 344M compliant
Supports data rates of 143, 177, 270, 360, and 540Mb/s
Supports DVB-ASI at 270Mb/s
Pb-free and RoHS Compliant
Auto and Manual Modes for rate selection
Standards indication in Auto Mode
4:1 input multiplexer
Loss of Signal (LOS) Output
Lock Detect Output
On-chip Input and Output Termination
Differential 50Ω inputs and outputs
Mute, Bypass and Autobypass functions
Single 3.3V power supply
Operating temperature range: 0°C to 70°C
Applications
GS1575A
•
SMPTE 292M, SMPTE 259M and SMPTE 344M Serial
Digital Interfaces
GS9075A
•
SMPTE 259M and SMPTE 344M Serial Digital Interfaces.
Description
The GS1575A/9075A is a Multi-Rate Serial Digital
Reclocker designed to automatically recover the
embedded clock from a digital video signal and re-time
the incoming video data.
The GS1575A Serial Digital Reclocker will recover the
embedded clock signal and re-time the data from a
SMPTE 292M, SMPTE 259M or SMPTE 344M
compliant digital video signal.
The GS9075A Serial Digital Reclocker will recover the
embedded clock signal and re-time the data from a
SMPTE 259M or SMPTE 344M compliant digital video
signal.
The GS1575A/9075A removes the high frequency jitter
components from the bit-serial stream. Input
termination is on-chip for seamless matching to 50Ω
transmission lines. An LVPECL compliant output
interfaces seamlessly to the GS1578A/GS9078A Cable
Driver.
The GS1575A/9075A can operate in either auto or
manual rate selection mode. In Auto mode the device
will automatically detect and lock onto incoming SMPTE
SDI data signals at any supported rate. For single rate
data systems, the GS1575A/9075A can be configured
to operate in Manual mode. In both modes, the device
requires only one external crystal to set the VCO
frequency when not locked and provides adjustment
free operation.
In systems which require passing of non-SMPTE data
rates, the GS1575A/9075A can be configured to either
automatically or manually enter a bypass mode in order
to pass the signal without reclocking.
The ASI/177 input pin allows for manual selection of
support of either 177Mb/s or DVB-ASI inputs.
The GS1575A/9075A is Pb-free, and the encapsulation
compound does not contain halogenated flame
retardant.
This component and all homogeneous sub-components
are RoHS compliant.
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www.gennum.com
GS1575A / GS9075A Data Sheet
XTAL+ XTAL-
XTAL XTAL
OUT+ OUT-
XTAL
OSC
LF+ LF-
KBB
BUFFER
RE-TIMER
M
U
X
DATA BUFFER
DDO/DDO
DDO_MUTE
SCO_ENABLE
DDI 0
DDI 1
DDI 2
PHASE
FREQUENCY
DETECTOR
D
A
T
A
CHARGE
PUMP
M
U
X
CLOCK BUFFER
VCO
SCO/SCO
PHASE
DETECTOR
M
U
X
DIVIDE BY
2,4,6,8,12,16
DIVIDE BY
152, 160, 208
DDI 3
BYPASS
LOGIC
CONTROL LOGIC
DDI_SEL[1:0]
SS[2:0]
ASI/177
AUTO/MAN
LD
SD/HD
LOS
AUTOBYPASS
BYPASS
GS1575A Functional Block Diagram
XTAL+ XTAL-
XTAL XTAL
OUT+ OUT-
XTAL
OSC
LF+ LF-
KBB
BUFFER
RE-TIMER
M
U
X
DATA BUFFER
DDO/DDO
DDO_MUTE
SCO_ENABLE
DDI 0
DDI 1
DDI 2
DDI 3
PHASE
FREQUENCY
DETECTOR
D
A
T
A
CHARGE
PUMP
M
U
X
CLOCK BUFFER
VCO
SCO/SCO
PHASE
DETECTOR
M
U
X
DIVIDE BY
2,4,6,8,12
DIVIDE BY
152, 160
BYPASS
LOGIC
CONTROL LOGIC
DDI_SEL[1:0]
SS[2:0]
ASI/177
AUTO/MAN
SD/HD
LD
LOS
AUTOBYPASS
BYPASS
GS9075A Functional Block Diagram
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GS1575A / GS9075A Data Sheet
Contents
Features ........................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
1. Pin Out ......................................................................................................................4
1.1 GS1575A Pin Assignment ..............................................................................4
1.2 GS9075A Pin Assignment ..............................................................................5
1.3 Pin Descriptions ..............................................................................................6
2. Electrical Characteristics ...........................................................................................9
2.1 Absolute Maximum Ratings ............................................................................9
2.2 DC Electrical Characteristics ..........................................................................9
2.3 AC Electrical Characteristics .........................................................................10
2.4 Solder Reflow Profiles ...................................................................................13
3. Input / Output Circuits .............................................................................................14
4. Detailed Description ................................................................................................17
4.1 Slew Rate Phase Lock Loop (S-PLL) ...........................................................17
4.2 VCO ..............................................................................................................18
4.3 Charge Pump ................................................................................................18
4.4 Frequency Acquisition Loop — The Phase-Frequency Detector ..................19
4.5 Phase Acquisition Loop — The Phase Detector ...........................................19
4.6 4:1 Input Mux ................................................................................................20
4.7 Automatic and Manual Data Rate Selection .................................................20
4.8 Bypass Mode ................................................................................................21
4.9 DVB-ASI Operation .......................................................................................21
4.10 Lock and LOS .............................................................................................22
4.11 Output Drivers and Serial Clock Outputs ....................................................22
4.12 Output Mute ................................................................................................23
5. Typical Application Circuits .....................................................................................24
6. Package & Ordering Information .............................................................................26
6.1 Package Dimensions ....................................................................................26
6.2 Recommended PCB Footprint ......................................................................27
6.3 Packaging Data .............................................................................................28
6.4 Ordering Information .....................................................................................28
7. Revision History ......................................................................................................29
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GS1575A / GS9075A Data Sheet
1. Pin Out
GND
XTAL_OUTXTAL_OUT+
XTAL+
XTAL-
NC
NC
NC
NC
NC
NC
VEE_CP
VCC_CP
LF+
GND
LF-
1.1 GS1575A Pin Assignment
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
DDI0
DDI0_VTT
1
2
47
VCC_DDO
DDI0
3
46
DDO
GND
4
45
NC
DDI1
5
44
DDI1_VTT
6
43
DDO
GND_DRV
DDI1
7
42
VEE_SCO
GND
8
41
DDI2
9
VCC_SCO
SCO
–
–
GS1575A
64-pin QFN
(Top View)
40
VEE_DDO
NC
DDI2_VTT
–
DDI2
10
39
11
38
GND
12
37
GND
DDI3
13
36
DDO_MUTE
DDI3_VTT
14
35
SCO_ENABLE
SCO
KBB
SD/HD
GND
VEE_DIG
LOCKED
LOS
VCC_DIG
ASI/177
SS2
SS1
SS0
VEE_VCO
VCC_VCO
AUTO/MAN
DDI_SEL0
GND
34
15
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AUTOBYPASS
DDI3
DDI_SEL1
BYPASS
–
–
Ground Pad
(bottom of package)
Figure 1-1: 64-Pin QFN
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GS1575A / GS9075A Data Sheet
GND
XTAL_OUTXTAL_OUT+
XTAL+
XTAL-
NC
NC
NC
NC
NC
NC
VEE_CP
VCC_CP
LF+
GND
LF-
1.2 GS9075A Pin Assignment
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
DDI0
DDI0_VTT
1
2
47
VCC_DDO
DDI0
3
46
DDO
GND
4
45
NC
DDI1
5
44
DDI1_VTT
6
43
DDO
GND_DRV
DDI1
7
42
VEE_SCO
GND
8
41
DDI2
9
VCC_SCO
SCO
–
–
GS9075A
64-pin QFN
(Top View)
40
VEE_DDO
NC
DDI2_VTT
–
DDI2
10
39
11
38
GND
12
37
GND
DDI3
13
36
DDO_MUTE
DDI3_VTT
14
35
SCO_ENABLE
SCO
KBB
SD
GND
VEE_DIG
LOCKED
LOS
VCC_DIG
ASI/177
SS2
SS1
SS0
VEE_VCO
VCC_VCO
AUTO/MAN
DDI_SEL0
GND
34
15
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AUTOBYPASS
DDI3
DDI_SEL1
BYPASS
–
–
Ground Pad
(bottom of package)
Figure 1-2: 64-Pin QFN
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GS1575A / GS9075A Data Sheet
1.3 Pin Descriptions
Table 1-1: Pin Descriptions
Pin Number
Name
Type
Description
1, 3
DDI0, DDI0
Input
Serial digital differential input 0.
2
DDI0_VTT
Passive
Center tap of two 50Ω on-chip termination resistors between DDI0 and DDI0.
GND
Passive
Recommended connect to GND.
5, 7
DDI1,DDI1
Input
Serial digital differential input 1.
6
DDI1_VTT
Passive
Center tap of two 50Ω on-chip termination resistors between DDI1 and DDI1.
9, 11
DDI2, DDI2
Input
Serial digital differential input 2.
10
DDI2_VTT
Passive
Center tap of two 50Ω on-chip termination resistors between DDI2 and DDI2.
13, 15
DDI3, DDI3
Input
Serial digital differential input 3.
14
DDI3_VTT
Passive
Center tap of two 50Ω on-chip termination resistors between DDI3 and DDI3.
DDI_SEL[1:0]
Logic Input
Serial digital input select.
4, 8, 12,16, 32,
37, 43, 49, 64
17, 18
19
BYPASS
Logic Input
DDI_SEL1
DDI_SEL0
INPUT SELECTED
0
0
DDI0
0
1
DDI1
1
0
DDI2
1
1
DDI3
Bypass the reclocker stage.
When BYPASS is HIGH, it overwrites the AUTOBYPASS setting.
20
AUTOBYPASS
Logic Input
Automatically bypasses the reclocker stage when the PLL is not locked
This pin is ignored when BYPASS is HIGH.
21
AUTO/MAN
Logic Input
Auto/Manual select.
When set HIGH, the standard is automatically detected from the input data rate.
When set LOW, the user must program the input standard using the SS[2:0]
pins.
22
VCC_VCO
Power
Most positive power supply connection for the internal VCO section.
Connect to 3.3V.
23
VEE_VCO
Power
Most negative power supply connection for the internal VCO section.
Connect to GND.
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GS1575A / GS9075A Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin Number
Name
Type
Description
24, 25, 26
SS[2:0]
Bi-directional
When AUTO/MAN is HIGH, SS[0:2] are outputs, displaying the data rate to
which the PLL has locked.
When AUTO/MAN is LOW, SS[0:2] are inputs, forcing the PLL to lock only to a
selected data rate
.
27
ASI/177
Logic Input
SS2
SS1
SS0
DATA RATE
SELECTED/FORCED
(Mb/s)
0
0
0
143
0
0
1
177
0
1
0
270
0
1
1
360
1
0
0
540
1
0
1
1483.5/1485
When set HIGH, the device disables the 177Mb/s data rate in the data rate
detection circuit. This prevents a false lock to 177Mb/s when using DVB-ASI.
When set LOW, 177Mb/s lock is possible, however, if a 270Mb/s ASI signal is
applied, the device could false lock to the 177MHz signal.
28
LOCKED
Output
Lock Detect.
This pin is set HIGH by the device when the PLL is locked.
29
LOS
Output
Loss of Signal.
Set HIGH when there are no transitions on the active DDI[3:0] input. See Lock
and LOS on page 22.
30
VCC_DIG
Power
Most positive power supply connection for the internal glue logic.
Connect to 3.3V.
31
VEE_DIG
Power
Most negative power supply connection for the internal glue logic.
Connect to GND.
33
SD/HD
Output
(GS1575A only)
This signal will be set LOW by the device when the reclocker has locked to
1.485Gbps or 1.485/1.001Gbps, or when a non-SMPTE standard is applied (i.e.
the device is not locked).
It will be set HIGH when the reclocker has locked to 143Mbps, 177Mbps,
270Mbps, 360Mbps, or 540Mbps.
33
SD
Output
This signal will go HIGH when the reclocker has locked to the input SD signal. It
will be LOW otherwise.
Analog Input
Controls the loop bandwidth of the PLL.
(GS9075A only)
34
KBB
Leave this pin floating for serial reclocking applications.
35
SCO_ENABLE
Power
Serial clock output enable.
Connect to VCC to enable the serial clock output. Connect to GND to disable the
serial clock output.
NOTE: This is not a TTL signal input.
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GS1575A / GS9075A Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin Number
36
38, 40
Name
Type
Description
DDO_MUTE
Logic Input
Mutes the DDO/DDO outputs. This option is not available in bypass mode.
SCO, SCO
Output
Serial clock output.
When SCO_ENABLE is set HIGH, a serial digital differential clock will be
presented to the application layer at the selected data rate.
39, 45, 54 - 59
41
NC
No Connect
Not connected internally.
VCC_SCO
Power
Most positive power supply connection for the SCO/SCO output driver.
Connect to 3.3V.
42
VEE_SCO
Power
Most negative power supply connection for the SCO/SCO output driver.
Connect to GND.
43
GND_DRV
Passive
Recommended connect to GND.
44, 46
DDO, DDO
Output
Differential Serial Digital Outputs.
47
VCC_DDO
Power
Most positive power supply connection for the DDO/DDO output driver.
Connect to 3.3V.
48
VEE_DDO
Power
Most negative power supply connection for the DDO/DDO output driver.
Connect to GND.
50, 51
XTAL_OUT+,
XTAL_OUT-
Output
Differential outputs of the reference oscillator used for monitoring or test
purposes.
52, 53
XTAL+, XTAL-
Input
Reference crystal input. Connect to the GO1535 as shown in the Typical
Application Circuits on page 24.
VEE_CP
Power
Most negative power supply connection for the internal charge pump.
60
Connect to GND.
61
VCC_CP
Power
Most positive power supply connection for the internal charge pump.
Connect to 3.3V.
62, 63
–
LF+, LF-
Passive
Loop filter capacitor connection. Connect as shown in the Typical Application
Circuits on page 24.
Center Pad
–
Ground pad on bottom of package.
Solder to main ground plane following recommendations under Recommended
PCB Footprint on page 27.
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GS1575A / GS9075A Data Sheet
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter
Value
Supply Voltage
+3.6 VDC
Input Voltage
Vcc + 0.5V
Operating Temperature Range
0°C to 70°C
Storage Temperature Range
-50°C < Ts < 125°C
Input ESD Voltage
1kV
Solder Reflow Temperature
260°C
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
VCC = 3.3V,
TA = 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply Voltage
VCC
Operating Range
3.135
3.3
3.465
V
Supply Current
ICC
SCO enabled,
TA=25°C
–
215
260
mA
ICC
SCO disabled,
TA=25°C
–
195
230
mA
–
SCO enabled,
TA=25°C
–
710
–
mW
–
SCO disabled,
TA=25°C
–
645
–
mW
Logic Inputs
VIH
High
2.0
–
–
V
DDI_SEL[1:0], BYPASS,
AUTOBYPASS, AUTO/MAN, ASI/177,
DDO_MUTE
VIL
Low
–
–
0.8
V
Logic Outputs
VOH
250uA Load
2.8
–
–
V
VOL
250uA Load
–
–
0.5
V
VIH
High
2.0
–
–
V
VIL
Low
–
–
0.8
V
Power Consumption
SD/HD, LOCKED, LOS
Bi-Directional Pins (Manual Mode)
SS[2:0], AUTO/MAN = 0
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GS1575A / GS9075A Data Sheet
Table 2-1: DC Electrical Characteristics (Continued)
VCC = 3.3V,
TA = 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Bi-Directional Pins (Auto Mode)
VOH
High, 250uA Load
2.8
–
–
V
VOL
Low, 250uA Load
–
–
0.5
V
VOH
High
–
VCC
–
V
VOL
Low
–
VCC - 0.285
–
V
SCO_ENABLE
–
1.5mA of current
delivered
VCC - 0.165
–
VCC + 0.165
V
Serial Input Voltage
–
Common Mode
1.65 +
(VSID/2)
–
VCC (VSID/2)
V
Serial Output Voltage
–
Common Mode
–
VCC - (VOD/2)
–
V
SS[2:0], AUTO/MAN = 1
XTAL_OUT+, XTAL_OUT-
SDO/SDO, SCO/SCO
2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
VCC = 3.3V,
TA = 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Serial Input Data Rate
–
GS1575A
143
–
1485
Mb/s
–
GS9075A
143
–
540
Mb/s
–
Worst case modulation (e.g.
square wave modulation)
0.8
–
–
UI
Serial Input Jitter Tolerance
143, 270, 360, 1485 Mb/s
PLL Lock Time - Asynchronous
t ALOCK
–
–
–
10
ms
PLL Lock Time - Synchronous
t SLOCK
CLF=47nF, SD/HD=0
–
–
10
us
t SLOCK
CLF=47nF, SD/HD=1
–
–
39
us
Serial Output Rise/Fall Time
SDO/SDO and SCO/SCO
(20% - 80%)
trSDO,trSCO
50Ω load (on chip)
–
114
–
ps
tfSDO,tfSCO
50Ω load (on chip)
–
106
–
ps
Serial Digital Input Signal Swing
VSID
Differential with internal 100Ω
input termination
100
–
800
mVp-p
1400
1600
2200
mVp-p
See Figure 2-1
Serial Digital Output Signal
Swing
VOD
100Ω load differential
See Figure 2-2
SDO/SDO and SCO/SCO
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GS1575A / GS9075A Data Sheet
Table 2-2: AC Electrical Characteristics (Continued)
VCC = 3.3V,
TA = 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Serial Output Jitter
tOJ
SDO/SDO and SCO/SCO
KBB = Float
PRN, 223-1
Measurement is output jitter
that includes input jitter from
BERT.
Loop Bandwidth
Min
Typ
Max
Units
143 Mb/s
–
0.02
–
UI
tOJ
177 Mb/s
–
0.02
–
UI
tOJ
270 Mb/s
–
0.02
0.09
UI
tOJ
360 Mb/s
–
0.03
–
UI
tOJ
540 Mb/s
–
0.03
0.09
UI
tOJ
1485 Mb/s (GS1575A only)
–
0.06
0.13
UI
tOJ
Bypass
–
0.06
0.13
UI
BWLOOP
1.485 Gb/s, KBB = FLOAT
(GS1575A only)
–
1.75
–
MHz
BWLOOP
1.485 Gb/s, KBB = GND,
<0.1dB Peaking
–
3.2
–
MHz
(GS1575A only)
BWLOOP
270 Mb/s, KBB = FLOAT
–
520
–
KHz
BWLOOP
270 Mb/s, KBB = GND
–
1000
–
KHz
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GS1575A / GS9075A Data Sheet
VCC
VCC _ VSID
2
VSID
2
Single-Ended Swing (DDIx)
VSID
2
Single-Ended Swing (DDIx)
VSID
Differential Swing (DDIx-DDIx)
VDD
VCC _ VSID
2
+
VSID
2
0
_ VSID
2
Figure 2-1: Serial Digital Input Signal Swing
VCC
VCC
_ VOD
2
VCC
_ VOD
2
VOD
2
Single-Ended Swing (DDO, SCO)
VOD
2
Single-Ended Swing (DDO, SCO)
VOD
Differential Swing (DDO-DDO)
(SCO-SCO)
VDD
+
VOD
2
0
_ VOD
2
Figure 2-2: Serial Digital Output Signal Swing
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GS1575A / GS9075A Data Sheet
2.4 Solder Reflow Profiles
The device is manufactured with Matte-Sn terminations and is compatible with both
standard eutectic and Pb-free solder reflow profiles. MSL qualification was
performed using the maximum Pb-free reflow profile shown in Figure 2-3. The
recommended standard Pb reflow profile is shown in Figure 2-4.
Temperature
60-150 sec.
20-40 sec.
260˚C
250˚C
3˚C/sec max
217˚C
6˚C/sec max
200˚C
150˚C
25˚C
Time
60-180 sec. max
8 min. max
Figure 2-3: Maximum Pb-free Solder Reflow Profile (Preferred)
60-150 sec.
Temperature
10-20 sec.
230˚C
220˚C
3˚C/sec max
183˚C
6˚C/sec max
150˚C
100˚C
25˚C
Time
120 sec. max
6 min. max
Figure 2-4: Standard Pb Solder Reflow Profile (Pb-free package)
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GS1575A / GS9075A Data Sheet
3. Input / Output Circuits
VREF
Figure 3-1: TTL Inputs
LF+
LF-
Figure 3-2: Loop Filter
250R
250R
10p
5K
5K
XTAL+
XTAL-
Figure 3-3: Crystal Input
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GS1575A / GS9075A Data Sheet
1K
1K
XTAL OUT-
XTAL OUT+
Figure 3-4: Crystal Output Buffer
50
50
SDO/SCO
SDO/SCO
Figure 3-5: Serial Data Outputs, Serial Clock Outputs
V
REF
KBB
500R
Figure 3-6: KBB
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GS1575A / GS9075A Data Sheet
Figure 3-7: Indicator Outputs: SD/HD, LOCKED, LOS
vREF
SS[2:0]
Figure 3-8: Standard Select/Indication Bi-directional Pins
DDI[3:0]
50
1k
1k
DDI_VTT
50
DDI[3:0]
Figure 3-9: Serial Data Inputs
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GS1575A / GS9075A Data Sheet
4. Detailed Description
The GS1575A/9075A is a Multi-Rate Serial Digital Reclocker designed to
automatically recover the embedded clock from a digital video signal and re-time
the incoming video data.
The GS1575A will recover the embedded clock signal and re-time the data from a
SMPTE 292M, SMPTE 259M or SMPTE 344M compliant digital video signal.
The GS9075A will recover the embedded clock signal and re-time the data from a
SMPTE 259M or SMPTE 344M compliant digital video signal.
Using the functional block diagram (page 2) as a guide, Slew Rate Phase Lock
Loop (S-PLL) on page 17 to Output Mute on page 23 describes each aspect of the
GS1575A/9075A in detail.
4.1 Slew Rate Phase Lock Loop (S-PLL)
The term “slew” refers to the output phase of the PLL in response to a step change
at the input. Linear PLLs have an output phase response characterized by an
exponential response whereas an S-PLL’s output is a ramp response (see
Figure 4-1). Because of this non-linear response characteristic, traditional small
signal analysis is not possible with an S-PLL.
PHASE (UI)
0.2
INPUT
0.1
OUTPUT
0.0
SLEW PLL RESPONSE
PHASE (UI)
0.2
INPUT
0.1
OUTPUT
0.0
LINEAR (CONVENTIONAL) PLL RESPONSE
Figure 4-1: PLL Characteristics
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GS1575A / GS9075A Data Sheet
The S-PLL offers several advantages over the linear PLL. The Loop Bandwidth of
an S-PLL is independent of the transition density of the input data. Pseudo-random
data has a transition density of 0.5 verses a pathological signal which has a
transition density of 0.05. The loop bandwidth of a linear PLL will change
proportionally with this change in transition density. With an S-PLL, the loop
bandwidth is defined by the jitter at the data input. This translates to infinite loop
bandwidth with a zero jitter input signal. This allows the loop to correct for small
variations in the input jitter quickly, resulting in very low output jitter. The loop
bandwidth of the GS1575A/9075A’s PLL is defined at 0.2UI of input jitter.
The PLL consists of two acquisition loops. First is the Frequency Acquisition (FA)
loop. This loop is active when the device is not locked and is used to achieve lock
to the supported data rates. Second is the phase acquisition (PA) loop. Once
locked, the PA loop tracks the incoming data and makes phased corrections to
produce a re-clocked output.
4.2 VCO
The internal VCO of the GS1575A/9075A is a ring oscillator. It is trimmed at the
time of manufacture to capture all data rates over temperature and operation
voltage ranges.
Integrated into the VCO is a series of programmable dividers used to achieve all
serial data rates, as well as additional dividers for the frequency acquisition loop.
4.3 Charge Pump
A common charge pump is used for the PLL of the GS1575A/9075A.
During frequency acquisition, the charge pump has two states, “pump-up” and
“pump-down,” which is produced by a leading or lagging phase difference between
the input and the VCO frequency.
During phase acquisition, there are two levels of “pump-up” and two levels of
“pump down” produced for leading and lagging phase difference between the input
and VCO frequency. This is to allow for greater precision of VCO control.
The charge pump produces these signals by holding the integrated frequency
information on the external loop-filter capacitor, CLF. The instantaneous frequency
information is the result of the current flowing through an internal resistor
connected to the loop-filter capacitor.
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GS1575A / GS9075A Data Sheet
4.4 Frequency Acquisition Loop — The Phase-Frequency Detector
An external crystal of 14.140 MHz is used as a reference to keep the VCO centered
at the last known data rate. This allows the device to achieve a fast synchronous
lock, especially in cases where a known data rate is interrupted. The crystal
reference is also used to clock internal timers and counters. To keep the optimal
performance of the reclocker over all operating conditions, the crystal frequency
must be 14.140 MHz, +/-50ppm. The GO1535 meets this specification and is
available from GENNUM.
The VCO is divided by a selected ratio which is dependant on the input data rate.
The resultant is then compared to the crystal frequency. If the divided VCO
frequency and the crystal frequency are within 1% of each other, the PLL is
considered to be locked to the input data rate.
4.5 Phase Acquisition Loop — The Phase Detector
The phase detector is a digital quadrature phase detector. It indicates whether the
input data is leading or lagging with respect to a clock that is in phase with the VCO
(I-clk) and a quadrature clock (Q-clk). When the phase acquisition loop (PA loop)
is locked, the input data transition is aligned to the falling edge of I-clk and the
output data is re-timed on the rising edge of I-clk. During high input jitter conditions
(>0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra
phase correction signals will be generated which instructs the charge pump to
create larger frequency corrections for the VCO.
i-PHASE ALIGNMENT
EDGE
DATA RE-TIMING
EDGE
I-clk
q-clk
q-PHASE ALIGNMENT
EDGE
INPUT DATA
WITH JITTER
0.25UI
0.8UI
RE-TIMED
OUTPUT DATA
Figure 4-2: Phase Detector Characteristics
When the PA loop is active, the crystal frequency and the incoming data rate are
compared. If the resultant is more that 2%, the PLL is considered to be unlocked
and the system jumps to the FA loop.
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GS1575A / GS9075A Data Sheet
4.6 4:1 Input Mux
The 4:1 input mux allows the connection of four independent streams of video/data.
There are four differential inputs (DDI[3:0] and DDI[3:0]). The active channel can
be selected via the DDI_SEL[1:0] pins. Table 4-1 shows the input selected for a
given state at DDI_SEL[1:0].
Table 4-1: Bit Pattern for Input Select
DDI_SEL[1:0]
Selected Input
00
DDI0
01
DDI1
10
DDI2
11
DDI3
The DDI inputs are designed to be DC interfaced with the output of the
GS1524A/9064A Cable Equalizer. There are on chip 50Ω termination resistors
which come to a common point at the DDI_VT pins. Connect a 10nF capacitor to
this pin and connect the other end of the capacitor to ground. This terminates the
transmission line at the inputs for optimum performance.
If only one input pair is used, connect the unused positive inputs to +3.3V and leave
the unused negative inputs floating. This helps to eliminate crosstalk from potential
noise that would couple to the unused input pair.
4.7 Automatic and Manual Data Rate Selection
The GS1575A/9075A can be configured to manually lock to a specific data rate or
automatically search for and lock to the incoming data rate. The AUTO/MAN pin
selects automatic data rate detection mode (Auto mode) when HIGH and manual
data rate selection mode (Manual mode) when LOW.
In Auto mode, the SS[2:0] bi-directional pins become outputs and the bit pattern
indicates the data rate that the PLL is locked to (or previously locked to). The
"search algorithm" cycles through the data rates and starts over if that data rate is
not found (see Figure 4-3).
POWER-UP
143 Mb\s
177 Mb\s
270Mb\s
360 Mb\s
1.485Mb\s
(GS1575A only)
540 Mb\s
Figure 4-3: Data Rate Search Pattern
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GS1575A / GS9075A Data Sheet
In Manual mode, the SS[2:0] pins become inputs and the data rate can be
programmed by the application layer. In this mode, the search algorithm is disabled
and the PLL will only lock to the data rate selected.
Table 4-2 shows the SS[2:0] pin settings for either the data rate selected (in
Manual mode) or the data rate that the PLL has locked to (in Auto mode).
Table 4-2: Data Rate Indication/Selection Bit Pattern
SS[2:0]
Data Rate (Mb/s)
000
143
001
177
010
270
011
360
100
540
101*
1485/1483.5
* This setting only applies to the GS1575A. For the GS9075A, when AUTO/MAN is LOW, the pin
settings SS[0:2] = 101 will be ignored by the device.
4.8 Bypass Mode
In Bypass mode, the GS1575A/9075A passes the data at the inputs directly to the
outputs. There are two pins that control the bypass function: BYPASS and
AUTOBYPASS.
When BYPASS is set HIGH by the application layer, the GS1575A/9075A will be
in Bypass mode.
When AUTOBYPASS is set HIGH by the application layer, the GS1575A/9075A
will be configured to enter Bypass mode only when the PLL has not locked to a data
rate. When BYPASS is set HIGH, AUTOBYPASS will be ignored.
When the PLL is not locked, and both BYPASS and AUTOBYPASS are set LOW,
the serial digital output DDO/DDO will produce invalid data.
4.9 DVB-ASI Operation
The GS1575A/9075A will also re-clock DVB-ASI at 270 Mb/s. When reclocking
DVB-ASI data set the ASI/177 pin HIGH to prevent a false lock to 177Mb/s. If
ASI/177 is not set HIGH, a false lock may occur since there is a harmonic present
in idle patterns (K28.5) which is very close the 177 Mb/s data rate (EIC 1179). Note
that setting the ASI/177 pin HIGH will disable the 177 Mb/s search when the device
is in Auto mode, consequently the GS1575A/9075A will not lock to that data rate.
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GS1575A / GS9075A Data Sheet
4.10 Lock and LOS
The LOCKED signal is an active high output which indicates when the PLL is
locked.
The internal lock logic of the GS1575A/9075A includes a system which monitors
the Frequency Acquisition Loop and the Phase Acquisition Loop as well as a
monitor to detect harmonic lock.
The LOS (Loss of Signal) output is an active HIGH output which indicates the
absence of data transitions at the DDIx input. In order for this output to be asserted,
transitions must not be present for a period of typically 5.14 us. After this output has
been asserted, LOS will deassert typically 5.14 us after the appearance of a
transition at the DDIx input. This timing relationship is shown in Figure 4-4:
5.14 us
5.14 us
DATA
LOS
Figure 4-4: LOS signal timing
NOTE: LOS is sensitive to transitions appearing at the input, and does not
distinguish between transitions caused by input data, and transitions due to noise.
4.11 Output Drivers and Serial Clock Outputs
The device’s serial digital data outputs (DDO/DDO) have a nominal voltage of
800mv single ended or 1600mV differential when terminated into a 50Ω load.
The GS1575A/9075A may also be configured to output a serial clock at the data
output rate. The internal serial clock output block is powered via the SCO_ENABLE
pin. When SCO_ENABLE is connected to VCC, a differential serial clock output will
be present on SCO/SCO. Otherwise, when SCO_ENABLE is connected to GND,
the clock output block will be powered down and the device will have reduced
power consumption.
NOTE: The SCO_ENABLE signal should have a 1.5mA drive strength to maintain
a supply voltage of 3.3 +/- 0.165V.
Clock and data alignment is shown in Figure 4-5.
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GS1575A / GS9075A Data Sheet
DATA
SCLK
For HD-SDI: tCD = 32ps (typ.), 36ps (max.)
For SD-SDI: tCD = 30ps (typ.), 38ps (max.)
tCD
Figure 4-5: Clock and Data Alignment
4.12 Output Mute
The DDO_MUTE pin is provided to allow muting of the re-timed output.
When the PLL is locked and the device is reclocking, setting DDO_MUTE = LOW
will force the serial digital outputs DDO/DDO to mute. However, if the
GS1575A/9075A is in Bypass mode, (AUTOBYPASS = HIGH and/or BYPASS =
HIGH), DDO_MUTE will have no effect on the output.
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GS1575A / GS9075A Data Sheet
5. Typical Application Circuits
GO1535
(14.140MHz)
47n
3.3V
100
10n
3
4
49
GND
53
XT AL -
55
54
NC
NC
56
NC
57
NC
58
NC
NC
VEE_ C P
60
59
62
61
VC C _ C P
DDO
6
DDI1_VT
GND
NC
DDI2
SCO
GN D
GND
DDI3
DDO_MUTE
SCO_ENABLE
DDI3_VT
46
45
Zo = 50
DATA OUTPUT
44
43
42
1 0n
3.3V
39
Zo = 50 CLOCK OUTPUT
38
37
36
SD O _ MU T E
35
34
DDI3
KBB
3.3V
DDI_SEL0
DDI_SEL1
SD /H D
GND
VEE_DIG
33
32
VCC_DIG
31
30
LOCKED
LOS
29
28
ASI/177
SS2
10n
27
SS1
26
SS0
25
17
SD/HD
24
GN D
DDI_SEL0
16
3.3V
40
DDI2_VT
VEE_VC0
15
1 0n
47
SCO
23
10n
GS1575A
DDI2
VCC_VCO
14
48
41
AUTO/MAN
13
VCC_SCO
22
12
GN D
21
11
VEE_SCO
AUTOBYPASS
10n
DDI1
20
9
10
Zo = 50
63
NC
DDI1
8
D A TA I N PU T 3
LF-
GN D
10n
Zo = 50
DDO
5
7
D ATA I N PU T 2
DDI0
BYPASS
Zo = 50
VCC_DDO
DDI_SEL1
D A TA I N PU T 1
VEE_DDO
DDI0_VT
19
Zo = 50
DDI0
18
D A TA I N PU T 0
2
XT AL + 5 2
51
XT AL _ O U T 50
XT AL _ O U T +
1
LF+
GND 64
10n
10n
3.3V
LOS
ASI_177
LOCKED
Note: All resistors in ohms and all capacitors in Farads.
Figure 5-1: GS1575A Typical Application Circuit
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GS1575A / GS9075A Data Sheet
G O 1535
(14.140MHz )
47n
3.3V
100
49
G ND
53
X TAL-
X TAL+ 52
51
X TAL_O UT50
X TAL_O UT+
55
54
NC
NC
56
NC
57
NC
58
NC
NC
V E E _CP
60
59
62
61
V CC_CP
63
LF-
DDI3
SCO _ ENABLE
DDI3_V T
46
45
Zo = 5 0
DA TA OUTPUT
44
43
42
10n
3.3V
39
Zo = 5 0 C LOCK OUTPUT
38
37
36
SDO_MUTE
35
34
DDI3
KBB
10n
3.3V
DDI_S E L0
DDI_S E L1
SD
G ND
VEE_ DIG
33
32
VCC_ DIG
31
30
LO S
SD
LO CKED
GND
DDI_ SEL0
16
G ND
DDO _ MUTE
29
15
GND
28
10n
NC
SCO
DDI2
ASI/177
Zo = 50
3.3V
40
DDI2_V T
17
DATA INPUT 3
14
10n
47
SCO
SS2
13
GS 9075A
DDI2
27
12
48
41
SS1
11
VCC_ SCO
26
10n
GND
SS0
Zo = 50
VEE_ SCO
25
DATA INPUT 2
DDI1
24
9
10
G ND
VEE_ VC0
8
DDI1_V T
23
7
VCC_ VCO
10n
DDO
AUTO /MAN
6
Z o = 50
NC
DDI1
22
DATA INPUT 1
GND
21
5
DDO
DDI0
AUTO BYPASS
4
20
3
VCC_ DDO
BYPASS
10n
VEE_ DDO
DDI0_V T
DDI_ SEL1
Zo = 50
DDI0
19
DATA INPUT 0
2
18
1
LF+
G ND 64
10n
10n
3.3V
LO S
A S I_177
LO CKED
Note: All resistors in ohms and all capacitors in Farads.
Figure 5-2: GS9075A Typical Application Circuit
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GS1575A / GS9075A Data Sheet
6. Package & Ordering Information
B
4.50
0.95+/-0.05
A
9.00
0.40+/-0.05
6.1 Package Dimensions
7.10+/-0.15
3.55
45
˚
9.00
PIN 1 AREA
7.10+/-0.15
4.50
0.35
4.50
3.55
CENTRE TAB
2X
2X
0.20 REF
0.15 C
0.15 C
0.10 C
+0.03
0.25-0.02
0.50
C
64X
C A B
0.10
C
0.05
64X
0.90 +/- 0.10
+0.03
0.02-0.02
0.08 C
SEATING PLANE
ALL DIMENSIONS IN MM
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GS1575A / GS9075A Data Sheet
6.2 Recommended PCB Footprint
0.25
0.50
0.55
CENTER PAD
8.70
7.10
7.10
8.70
NOTE: All dimensions
are in millimeters.
The center pad of the PCB footprint should be connected to the ground plane by a
minimum of 36 vias.
NOTE: Suggested dimensions only. Final dimensions should conform to customer
design rules and process optimizations.
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GS1575A / GS9075A Data Sheet
6.3 Packaging Data
Parameter
Value
Package Type
9mm x 9mm 64-pin QFN
Moisture Sensitivity Level
3
Junction to Case Thermal Resistance, θj-c
9.1°C/W
Junction to Air Thermal Resistance, θj-a (at zero airflow)
21.5°C/W
Psi, Ψ
0.2°C/W
Pb-free and RoHS Compliant
Yes
6.4 Ordering Information
Part Number
Package
Temperature Range
GS1575A
GS1575ACNE3
Pb-free 64-pin QFN
0°C to 70°C
GS9075A
GS9075ACNE3
Pb-free 64-pin QFN
0°C to 70°C
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GS1575A / GS9075A Data Sheet
7. Revision History
Version
ECR
PCN
Date
Changes and/or Modifications
A
136456
–
April 2005
New Document.
0
137416
–
December 2005
Converted to Data Sheet. Added block
diagram, pinout, DC and AC electrical,
and circuit information for serial clock
output support. Added information on
GS9075A. Added LOS support
information. Corrected minor typing
errors. Corrected maximum Serial
Digital Output swing to 2200 mV.
Corrected packaging diagram.
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes to the product at any time without notice to improve reliability,
function or design, in order to provide the best product possible.
GENNUM CORPORATION
Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan
Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the
circuits or devices described herein. The sale of the circuit or device described herein does not imply any
patent license, and Gennum makes no representation that the circuit or device is free from patent infringement.
GENNUM and the G logo are registered trademarks of Gennum Corporation.
© Copyright 2005 Gennum Corporation. All rights reserved. Printed in Canada.
www.gennum.com
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