GSI GS816236B-150 1m x 18, 512k x 36, 256k x 72 18mb sync burst sram Datasheet

GS816218(B/D)/GS816236(B/D)/GS816272(C)
250 MHz–133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
1M x 18, 512K x 36, 256K x 72
18Mb Sync Burst SRAMs
119-, 165-, & 209-Bump BGA
Commercial Temp
Industrial Temp
Features
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
De
sig
n
.
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-, 165-, and 209-bump BGA package
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SCD and DCD Pipelined Reads
The GS816218(B/D)/GS816236(B/D)/GS816272(C) is a SCD
(Single Cycle Deselect) and DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. DCD SRAMs pipeline disable
commands to the same degree as read commands. SCD SRAMs
pipeline deselect commands one stage less than read commands.
SCD RAMs begin turning off their outputs immediately after the
deselect command has been captured in the input registers. DCD
RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge of
clock. The user may configure this SRAM for either mode of
operation using the SCD mode input.
Functional Description
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
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Applications
The GS816218(B/D)/GS816236(B/D)/GS816272(C) is an
18,874,368-bit high performance synchronous SRAM with a 2-bit
burst address counter. Although of a type originally developed for
Level 2 Cache applications supporting high performance CPUs,
the device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip set
support.
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FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
in
th
is
Core and Interface Voltages
The GS816218(B/D)/GS816236(B/D)/GS816272(C) operates on
a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V
compatible. Separate output power (VDDQ) pins are used to
decouple output noise from the internal circuits and are 3.3 V and
2.5 V compatible.
x3
6
pa
rt
s
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
-250
-225
-200
-166
-150
-133
Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.4
6.0
3.8
6.7
4.0
7.5
ns
ns
3.3 V
Curr (x18)
Curr (x36)
Curr (x72)
280
330
n/a
255
300
n/a
230
270
350
200
230
300
185
215
270
165
190
245
mA
mA
mA
Flow Through
2-1-1-1
tKQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
Curr (x18)
Curr (x36)
Curr (x72)
175
200
n/a
165
190
n/a
160
180
225
150
170
115
145
165
210
135
150
185
mA
mA
mA
x1
8a
nd
Th
e
Parameter Synopsis
Rev: 2.17 11/2004
1/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816272 Pad Out—209 Bump BGA—Top View (Package C)
2
3
4
5
6
7
8
9
10
11
A
DQG
DQG
A
E2
ADSP
ADSC
ADV
E3
A
DQB
DQB
B
DQG
DQG
BC
BG
NC
BW
A
BB
BF
C
DQG
DQG
BH
BD
NC
E1
NC
BE
BA
D
DQG
DQG
VSS
NC
NC
G
GW
NC
VSS
E
DQPG
DQPC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
F
DQC
DQC
VSS
VSS
VSS
ZQ
VSS
G
DQC
DQC
VDDQ
VDDQ
VDD
MCH
VDD
H
DQC
DQC
VSS
VSS
VSS
MCL
VSS
J
DQC
DQC
VDDQ
VDDQ
VDD
MCL
K
NC
NC
CK
NC
VSS
L
DQH
DQH
VDDQ
VDDQ
M
DQH
DQH
VSS
N
DQH
DQH
P
DQH
R
DQB
DQB
DQB
DQB
VDDQ
DQP
DQPB
VSS
VSS
DQF
DQF
VDDQ
ed
VDDQ
DQF
DQF
VSS
VSS
DQF
DQF
VDD
VDDQ
VDDQ
DQF
DQF
MCL
VSS
NC
NC
NC
NC
VDD
FT
VDD
VDDQ
VDDQ
DQA
DQA
VSS
VSS
MCL
VSS
VSS
VSS
DQA
DQA
VDDQ
VDDQ
VDD
SCD
VDD
VDDQ
VDDQ
DQA
DQA
DQH
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQA
DQA
DQPD
DQPH
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPA
DQPE
T
DQD
DQD
VSS
NC
NC
LBO
NC
NC
VSS
DQE
DQE
U
DQD
DQD
NC
A1
A
A1
A
A
NC
DQE
DQE
V
DQD
DQD
A
A
A
A1
A
A
A
DQE
DQE
W
DQD
DQD
TDI
A
A0
A
TDO
TCK
DQE
DQE
th
rt
s
in
TMS
fo
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en
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11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Th
e
x1
8a
nd
x3
6
pa
Rev 10
ew
DQB
is
DQB
sp
ec
if
De
sig
n
.
1
Rev: 2.17 11/2004
2/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816272 BGA Pin Description
Type
Description
A 0, A 1
I
Address field LSBs and Address Counter Preset Inputs.
An
I
Address Inputs
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
I/O
Data Input and Output pins
BA, BB, BC,BD, BE, BF, BG,BH
I
Byte Write Enable for DQA, DQB, DQC, DQD, DQE,
DQF, DQG, DQH I/Os; active low
NC
—
No Connect
CK
I
Clock Input Signal; active high
GW
I
Global Write Enable—Writes all bytes; active low
E1, E3
I
Chip Enable; active low
E2
I
G
I
ADV
I
ADSP, ADSC
I
ZZ
I
FT
I
LBO
I
SCD
I
MCH
I
en
d
m
Re
co
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eN
ot
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
Must Connect High
is
sp
ec
if
ica
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n
Address Strobe (Processor, Cache Controller); active low
Must Connect Low
I
Byte Enable; active low
ZQ
I
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
I
Scan Test Mode Select
I
Scan Test Data In
O
Scan Test Data Out
TCK
I
Scan Test Clock
VDD
I
Core power supply
VSS
I
I/O and Core Ground
VDDQ
I
Output driver power supply
pa
in
BW
rt
s
th
MCL
ed
fo
rN
ew
De
sig
n
.
Symbol
TDI
Th
e
x1
8a
nd
TDO
x3
6
TMS
Rev: 2.17 11/2004
3/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BB
NC
E3
BW
ADSC
ADV
A
A
B
NC
A
E2
NC
BA
CK
GW
G
ADSP
A
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
D
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
E
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
F
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
G
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
H
FT
MCL
NC
VDD
VSS
VSS
Re
co
m
J
DQB
NC
VDDQ
VDD
VSS
K
DQB
NC
VDDQ
VDD
VSS
L
DQB
NC
VDDQ
VDD
VSS
M
DQB
NC
VDDQ
VDD
N
DQB
SCD
VDDQ
VSS
P
NC
NC
A
R
LBO
NC
A
C
NC
DQA
D
NC
DQA
E
VDDQ
NC
DQA
F
VDD
VDDQ
NC
DQA
G
VSS
VDD
NC
ZQ
ZZ
H
VSS
VSS
VDD
VDDQ
DQA
NC
J
VSS
VSS
VDD
VDDQ
DQA
NC
K
VSS
VSS
VDD
VDDQ
DQA
NC
L
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
M
NC
A
NC
VSS
VDDQ
NC
NC
N
A
TDI
A1
TDO
A
A
A
A
P
A
TMS
A0
TCK
A
A
A
A
R
n
fo
rN
ed
en
d
m
ew
DQA
ar
eN
ot
B
sp
ec
if
is
th
in
rt
s
NC
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Th
e
x1
8a
nd
x3
6
pa
A
De
sig
n
.
1
ica
ti o
165-Bump BGA—x18 Commom I/O—Top View (Package D)
Rev: 2.17 11/2004
4/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BC
BB
E3
BW
ADSC
ADV
A
NC
B
NC
A
E2
BD
BA
CK
GW
G
ADSP
A
C
DQC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
D
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
E
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
F
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
G
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
H
FT
MCL
NC
VDD
VSS
VSS
Re
co
m
J
DQD
DQD
VDDQ
VDD
VSS
K
DQD
DQD
VDDQ
VDD
VSS
L
DQD
DQD
VDDQ
VDD
VSS
M
DQD
DQD
VDDQ
VDD
N
DQD
SCD
VDDQ
VSS
P
NC
NC
A
R
LBO
NC
A
C
DQB
DQB
D
DQB
DQB
E
VDDQ
DQB
DQB
F
VDD
VDDQ
DQB
DQB
G
VSS
VDD
NC
ZQ
ZZ
H
VSS
VSS
VDD
VDDQ
DQA
DQA
J
VSS
VSS
VDD
VDDQ
DQA
DQA
K
VSS
VSS
VDD
VDDQ
DQA
DQA
L
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
M
NC
A
NC
VSS
VDDQ
NC
DQA
N
A
TDI
A1
TDO
A
A
A
A
P
A
TMS
A0
TCK
A
A
A
A
R
n
fo
rN
ed
en
d
m
ew
DQB
ar
eN
ot
B
sp
ec
if
is
th
in
rt
s
NC
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Th
e
x1
8a
nd
x3
6
pa
A
De
sig
n
.
1
ica
ti o
165-Bump BGA—x36 Common I/O—Top View (Package D)
Rev: 2.17 11/2004
5/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
B
NC
A
A
ADSC
A
A
C
NC
A
A
VDD
A
A
D
DQC
DQPC
VSS
ZQ
VSS
DQB
DQB
E
DQC
DQC
VSS
E1
VSS
DQB
DQB
F
VDDQ
DQC
VSS
G
VSS
DQB
VDDQ
G
DQC
DQC
BC
ADV
BB
DQB
DQB
H
DQC
DQC
VSS
GW
VSS
DQB
DQB
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQD
L
DQD
M
VDDQ
fo
rN
NC
ew
VDDQ
De
sig
n
.
1
en
d
GS816236 Pad Out—119-Bump BGA—Top View (Package B)
VSS
CK
VSS
DQA
DQA
DQD
BD
SCD
BA
DQA
DQA
DQD
VSS
BW
VSS
DQA
VDDQ
DQD
DQD
VSS
A1
VSS
DQA
DQA
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC
A
LBO
VDD
FT
A
PE
T
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
th
is
DQD
sp
ec
if
ica
ti o
n
ar
eN
ot
Re
co
m
m
ed
NC
Th
e
x1
8a
nd
x3
6
pa
P
rt
s
in
N
Rev: 2.17 11/2004
6/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
2
3
4
5
A
VDDQ
A
A
ADSP
A
B
NC
A
A
ADSC
A
A
NC
C
NC
A
A
VDD
A
A
D
DQB
NC
VSS
ZQ
VSS
DQPA
fo
rN
6
7
E
NC
DQB
VSS
E1
VSS
F
VDDQ
NC
VSS
G
G
NC
DQB
BB
ADV
H
DQB
NC
VSS
J
VDDQ
VDD
NC
K
NC
L
DQB
M
VDDQ
ew
VDDQ
ed
NC
NC
DQA
VSS
DQA
VDDQ
NC
NC
DQA
GW
VSS
DQA
NC
VDD
NC
VDD
VDDQ
Re
co
m
m
NC
ica
ti o
n
ar
eN
ot
De
sig
n
.
1
en
d
GS816218 Pad Out—119-Bump BGA—Top View (Package B)
VSS
CK
VSS
NC
DQA
NC
NC
SCD
BA
DQA
NC
DQB
VSS
BW
VSS
NC
VDDQ
DQB
NC
VSS
A1
VSS
DQA
NC
NC
DQPB
VSS
A0
VSS
NC
DQA
LBO
VDD
FT
A
PE
th
is
sp
ec
if
DQB
pa
P
rt
s
in
N
NC
T
NC
A
A
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Th
e
x1
8a
nd
x3
6
R
BPR1999.05.18
Rev: 2.17 11/2004
7/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816218/36 BGA Pin Description
Type
Description
A 0, A 1
I
Address field LSBs and Address Counter Preset Inputs
An
I
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA , BB , BC , BD
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC
—
No Connect
CK
I
Clock Input Signal; active high
BW
I
Byte Write—Writes all enabled bytes; active low
GW
I
Global Write Enable—Writes all bytes; active low
E1
I
Chip Enable; active low
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active low
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep mode control; active high
FT
I
LBO
I
ZQ
I
SCD
I
TMS
I
TDI
I
TDO
O
TCK
I
PE
I
VDD
I
VSS
I
De
sig
n
ew
fo
rN
ed
en
d
m
Re
co
m
ar
eN
ot
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
ica
ti o
n
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
sp
ec
if
Single Cycle Deselect/Dual Cyle Deselect Mode Control
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
th
is
Scan Test Clock
in
Parity Bit Enable; active low
rt
s
Core power supply
I/O and Core Ground
pa
VDDQ
.
Symbol
Output driver power supply
Th
e
x1
8a
nd
x3
6
I
Rev: 2.17 11/2004
8/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816218/36 (PE = 0) Block Diagram
Register
Q
A0
D0
A1
Q0
A1
.
A0
D1
Q1
Counter
Load
A
ew
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
36
en
d
ica
ti o
Q
n
D
Register
Q
BD
Q
Register
D
4
Register
BC
4
D
Q
ar
eN
ot
D
36
m
Register
D
Q
BB
Register
Re
co
m
Register
D
Q
D
D
ed
Q
Register
GW
BW
BA
Register
Q
sp
ec
if
D
36
36
36
Register
E1
Q
4
Parity
Encode
Register
D
Q
4
Parity
Compare
x3
6
x1
8a
nd
Power Down
32
36
pa
rt
s
in
th
is
D
FT
G
ZZ
De
sig
n
D
fo
rN
A0–An
36
SCD
DQx1–DQx9
NC
NC
Control
Th
e
Note: Only x36 version shown for simplicity.
Rev: 2.17 11/2004
9/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816218/36 (PE = 1) x32 Mode Block Diagram
Register
Q
Q0
A1
D1
Q1
Counter
Load
De
sig
n
D0
A1
.
A0
A0
A
LBO
ADV
fo
rN
Memory
Array
CK
ADSC
ADSP
Q
Register
Q
en
d
m
Q
BC
n
ica
ti o
Q
D
BD
Register
Q
sp
ec
if
D
32
36
Register
D
is
Register
D
4
rt
s
Register
D
Register
D
Q
Power Down
32
Q
Parity
Encode
4
Parity
Compare
pa
x1
8a
nd
ZZ
36
32
x3
6
FT
G
Q
Q
in
th
E1
Register
Register
32
4
Q
ar
eN
ot
Register
D
4
D
Q
BB
D
36
Parity
Encode
Re
co
m
Register
D
D
36
Register
D
Q
GW
BW
BA
ew
D
ed
A0–An
32
SCD
DQx1–DQx8
NC
NC
Control
Th
e
Note: Only x36 version shown for simplicity.
Rev: 2.17 11/2004
10/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
Single/Dual Cycle Deselect Control
SCD
FLXDrive Output Impedance Control
ZQ
9th Bit Enable
PE
State
Function
L
Linear Burst
H
Interleaved Burst
L
Flow Through
H or NC
Pipeline
L or NC
Active
De
sig
n
Pin Name
ew
Mode Name
Standby, IDD = ISB
fo
rN
H
L
Dual Cycle Deselect
H or NC
Single Cycle Deselect
en
d
Re
co
m
H or NC
Low Drive (High Impedance)
m
L
High Drive (Low Impedance)
ed
L
H or NC
.
Mode Pin Functions
Activate DQPx I/Os (x18/x36 mode)
Deactivate DQPx I/Os (x16/x32 mode)
ar
eN
ot
Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
ica
ti o
n
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
01
10
2nd address
01
10
11
3rd address
10
11
00
4th address
11
00
01
11
1st address
00
01
10
11
00
2nd address
01
00
11
10
01
3rd address
10
11
00
01
10
4th address
11
10
01
00
sp
ec
if
00
th
is
1st address
A[1:0] A[1:0] A[1:0] A[1:0]
Note:
The burst counter wraps to initial state on the 5th clock.
x3
6
pa
rt
s
in
Note:
The burst counter wraps to initial state on the 5th clock.
Th
e
x1
8a
nd
BPR 1999.05.18
Rev: 2.17 11/2004
11/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
Write byte b
H
L
H
L
H
H
Write byte c
H
L
H
H
L
H
Write byte d
H
L
H
H
H
Write all bytes
H
L
L
L
L
De
sig
n
Function
.
Byte Write Truth Table
2, 3
fo
rN
ew
2, 3
2, 3, 4
2, 3, 4
L
2, 3, 4
ed
L
Th
e
x1
8a
nd
x3
6
pa
rt
s
in
th
is
sp
ec
if
ica
ti o
n
ar
eN
ot
Re
co
m
m
en
d
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x36 version.
Rev: 2.17 11/2004
12/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Synchronous Truth Table
Operation
Address Used
State
Diagram
Key5
Deselect Cycle, Power Down
None
X
H
X
L
X
Read Cycle, Begin Burst
External
R
L
L
X
X
Read Cycle, Begin Burst
External
R
L
H
L
Write Cycle, Begin Burst
External
W
L
H
L
Read Cycle, Continue Burst
Next
CR
X
H
Read Cycle, Continue Burst
Next
CR
H
X
Write Cycle, Continue Burst
Next
CW
X
H
Write Cycle, Continue Burst
Next
CW
H
X
Read Cycle, Suspend Burst
Current
X
Read Cycle, Suspend Burst
Current
Write Cycle, Suspend Burst
Current
Write Cycle, Suspend Burst
Current
ADSP
ADSC
ADV
W3
DQ4
X
Q
X
F
Q
X
T
D
H
L
F
Q
H
L
F
Q
H
L
T
D
H
L
T
D
H
H
H
F
Q
H
X
H
H
F
Q
X
H
H
H
T
D
H
X
H
H
T
D
en
d
m
Re
co
m
ar
eN
ot
ew
High-Z
ed
X
fo
rN
De
sig
n
.
E1
Th
e
x1
8a
nd
x3
6
pa
rt
s
in
th
is
sp
ec
if
ica
ti o
n
Notes:
1. X = Don’t Care, H = High, L = Low
2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding
3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 2.17 11/2004
13/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Simplified State Diagram
De
sig
n
.
X
Deselect
ew
R
CW
ed
First Read
X
CR
Simple Burst Synchronous Operation
ar
eN
ot
CR
en
d
R
First Write
m
X
R
Re
co
m
Simple Synchronous Operation
W
fo
rN
W
ica
ti o
n
W
R
R
sp
ec
if
Burst Write
Burst Read
X
CR
CW
CR
rt
s
in
th
is
X
Th
e
x1
8a
nd
x3
6
pa
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and
assumes ADSP is tied high and ADV is tied low.
Rev: 2.17 11/2004
14/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Simplified State Diagram with G
De
sig
n
.
X
Deselect
ew
R
W
CR
CW
ed
First Read
X
CR
X
ica
ti o
W
n
ar
eN
ot
Re
co
m
CW
W
en
d
R
First Write
m
X
R
fo
rN
W
sp
ec
if
Burst Write
R
W
Burst Read
X
CW
CW
CR
rt
s
in
th
is
CR
R
Th
e
x1
8a
nd
x3
6
pa
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 2.17 11/2004
15/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Absolute Maximum Ratings
(All voltages reference to VSS)
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
–0.5 to 4.6
VI/O
Voltage on I/O Pins
–0.5 to VDDQ +0.5 (≤ 4.6 V max.)
V
VIN
Voltage on Other Input Pins
–0.5 to VDD +0.5 (≤ 4.6 V max.)
V
IIN
Input Current on Any Pin
+/–20
mA
IOUT
Output Current on Any I/O Pin
+/–20
mA
PD
Package Power Dissipation
1.5
W
TSTG
Storage Temperature
TBIAS
Temperature Under Bias
ed
fo
rN
ew
De
sig
n
.
Symbol
V
–55 to 125
o
–55 to 125
o
en
d
C
m
C
ar
eN
ot
Re
co
m
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Symbol
Min.
Typ.
Max.
Unit
3.3 V Supply Voltage
VDD3
3.0
3.3
3.6
V
VDD2
2.3
2.5
2.7
V
VDDQ3
3.0
3.3
3.6
V
VDDQ2
2.3
2.5
2.7
V
Notes
ica
ti o
n
Parameter
sp
ec
if
2.5 V Supply Voltage
3.3 V VDDQ I/O Supply Voltage
is
2.5 V VDDQ I/O Supply Voltage
Th
e
x1
8a
nd
x3
6
pa
rt
s
in
th
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 2.17 11/2004
16/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
VDDQ3 Range Logic Levels
Symbol
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
2.0
—
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
–0.3
—
0.8
VDDQ I/O Input High Voltage
VIHQ
2.0
—
VDDQ + 0.3
VDDQ I/O Input Low Voltage
VILQ
–0.3
—
0.8
V
1
V
1,3
V
1,3
fo
rN
ew
De
sig
n
.
Parameter
Re
co
m
m
en
d
ed
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Symbol
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
0.6*VDD
—
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
–0.3
—
0.3*VDD
V
1
VDDQ I/O Input High Voltage
VIHQ
0.6*VDD
—
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
–0.3
—
0.3*VDD
V
1,3
n
ar
eN
ot
Parameter
ica
ti o
VDDQ2 Range Logic Levels
VILQ
in
th
is
sp
ec
if
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
rt
s
Recommended Operating Temperatures
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)
TA
0
25
70
°C
2
Ambient Temperature (Industrial Range Versions)
TA
–40
25
85
°C
2
x1
8a
nd
x3
6
pa
Parameter
Th
e
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 2.17 11/2004
17/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
50% tKC
50%
50%
VDD
De
sig
n
VSS
.
VDD + 2.0 V
50% tKC
ew
VSS – 2.0 V
fo
rN
VIL
Capacitance
Input Capacitance
CIN
VIN = 0 V
Input/Output Capacitance
CI/O
VOUT = 0 V
Typ.
Max.
Unit
4
5
pF
6
7
pF
en
d
Test conditions
m
Symbol
Re
co
m
Parameter
ed
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
AC Test Conditions
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
sp
ec
if
ica
ti o
n
Parameter
ar
eN
ot
Note:
These parameters are sample tested.
VDDQ/2
Output reference level
Fig. 1
is
Output load
Th
e
x1
8a
nd
x3
6
pa
rt
s
in
th
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Rev: 2.17 11/2004
Output Load 1
DQ
50Ω
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
18/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
ZZ Input Current
IIN1
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
FT, SCD, ZQ Input Current
IIN2
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
Output Leakage Current
IOL
Output Disable, VOUT = 0 to VDD
Output High Voltage
VOH2
Output High Voltage
Output Low Voltage
.
Parameter
De
sig
n
DC Electrical Characteristics
1 uA
100 uA
–100 uA
–1 uA
1 uA
1 uA
–1 uA
1 uA
IOH = –8 mA, VDDQ = 2.375 V
1.7 V
—
VOH3
IOH = –8 mA, VDDQ = 3.135 V
2.4 V
—
VOL
IOL = 8 mA
—
0.4 V
Th
e
x1
8a
nd
x3
6
pa
rt
s
in
th
is
sp
ec
if
ica
ti o
n
ar
eN
ot
Re
co
m
m
en
d
ed
fo
rN
ew
–1 uA
–1 uA
Rev: 2.17 11/2004
19/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
Rev: 2.17 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
20/41
x3
6
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
ZZ ≥ VDD – 0.2 V
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
x1
8a
nd
Test Conditions
—
—
(x18)
(x36)
(x72)
(x18)
rt
s
(x36)
pa
(x72)
is
IDD
60
85
IDD
Pipeline
Flow
Through
20
ISB
Pipeline
ISB
20
IDDQ
Flow
Through
165
10
Flow
Through
IDD
IDDQ
260
15
IDD
Pipeline
180
20
IDD
IDDQ
Flow
Through
290
30
n/a
n/a
65
90
30
30
175
10
270
15
190
20
300
30
n/a
n
n/a
175
10
270
20
190
20
300
40
n/a
n/a
n/a
155
10
235
20
170
20
265
35
n/a
n/a
0
to
70°C
n/a
165
10
245
20
180
20
275
35
n/a
n/a
–40
to
85°C
-225
60
80
20
20
155
10
235
15
170
20
265
30
n/a
65
85
30
30
165
10
245
15
180
20
50
75
20
20
150
10
215
15
165
15
240
25
195
30
290
45
150
10
215
15
165
15
240
30
195
30
290
60
0
to
70°C
55
80
30
30
160
10
50
64
20
20
140
10
185
10
ed
155
15
205
20
185
30
250
40
140
10
185
15
155
15
205
25
185
30
250
50
55
70
30
30
150
10
fo
rN
195
10
165
15
215
20
195
30
260
40
150
10
195
15
165
15
215
25
195
30
260
50
–40
to
85°C
-166
0
to
70°C
en
d
225
15
m
175
15
250
25
205
30
300
45
160
10
225
15
175
15
250
30
205
30
300
60
–40
to
85°C
-200
Re
co
m
275
30
n/a
ar
eN
ot
–40
to
85°C
ica
ti o
165
10
260
20
IDD
IDDQ
IDDQ
IDD
IDD
IDDQ
IDD
IDDQ
sp
ec
if
IDD
IDDQ
180
20
290
40
n/a
n/a
0
to
70°C
Pipeline
Flow
Through
Pipeline
Flow
Through
Pipeline
th
IDD
IDDQ
Flow
Through
in
IDD
IDDQ
IDD
IDDQ
Flow
Through
Pipeline
IDD
IDDQ
Symbol
Pipeline
Mode
-250
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
Deselect
Current
Standby
Current
2.5 V
Operating
Current
3.3 V
Operating
Current
Th
e
Parameter
Operating Currents
50
60
20
55
65
30
.
45
50
20
20
125
10
155
10
140
10
170
15
165
20
205
30
125
10
155
10
140
10
170
20
165
20
205
40
50
55
30
30
135
10
165
10
150
10
180
15
175
20
215
30
135
10
165
10
150
10
180
20
175
20
215
40
–40
to
85°C
-133
0
to
70°C
De
sig
n
30
ew
20
145
10
180
10
160
15
200
20
190
30
235
35
145
10
180
15
160
15
200
25
190
30
235
45
–40
to
85°C
135
10
170
10
150
15
190
20
180
30
225
35
135
10
170
15
150
15
190
25
180
30
225
45
0
to
70°C
-150
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Unit
GS816218(B/D)/GS816236(B/D)/GS816272(C)
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
AC Electrical Characteristics
-166
-150
Min
Max
Min
Max
Min
Max
Min
tKC
4.0
—
4.4
—
5.0
—
6.0
—
6.7
Clock to Output Valid
tKQ
—
2.5
—
2.7
—
3.0
—
3.4
—
Clock to Output Invalid
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
Clock to Output in Low-Z
tLZ1
1.5
—
1.5
—
1.5
—
1.5
Setup time
tS
1.2
—
1.3
—
1.4
—
1.5
Hold time
tH
0.2
—
0.3
—
0.4
—
0.5
Clock Cycle Time
tKC
5.5
—
6.0
—
6.5
—
Clock to Output Valid
tKQ
—
5.5
—
6.0
—
Clock to Output Invalid
tKQX
3.0
—
3.0
—
Clock to Output in Low-Z
tLZ1
3.0
—
3.0
—
Setup time
tS
1.5
—
Hold time
tH
0.5
—
Clock HIGH Time
tKH
1.3
—
Clock LOW Time
tKL
1.5
—
Clock to Output in
High-Z
tHZ1
1.5
2.5
G to Output Valid
tOE
—
G to output in Low-Z
tOLZ1
G to output in High-Z
pa
ZZ hold time
x3
6
ZZ recovery
Min
Max
—
7.5
—
ns
3.8
—
4.0
ns
1.5
—
1.5
—
ns
1.5
—
1.5
—
ns
—
1.5
—
1.5
—
ns
—
0.5
—
0.5
—
ns
7.0
—
7.5
—
8.5
—
ns
6.5
—
7.0
—
7.5
—
8.5
ns
3.0
—
3.0
—
3.0
—
3.0
—
ns
3.0
—
3.0
—
3.0
—
3.0
—
ns
en
d
Re
co
m
ar
eN
ot
ed
—
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
1.3
—
1.3
—
1.3
—
1.5
—
1.7
—
ns
1.5
—
1.5
—
1.5
—
1.7
—
2
—
ns
1.5
2.7
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
2.5
—
2.7
—
3.2
—
3.5
—
3.8
—
4.0
ns
0
—
0
—
0
—
0
—
0
—
0
—
ns
—
2.5
—
2.7
—
3.0
—
3.0
—
3.0
—
3.0
ns
tZZS2
5
—
5
—
5
—
5
—
5
—
5
—
ns
tZZH2
1
—
1
—
1
—
1
—
1
—
1
—
ns
tZZR
20
—
20
—
20
—
20
—
20
—
20
—
ns
is
sp
ec
if
ica
ti o
n
1.5
tOHZ1
rt
s
ZZ setup time
Unit
Max
.
Max
ew
Min
-133
De
sig
n
-200
fo
rN
-225
m
Clock Cycle Time
-250
th
Flow
Through
Symbol
in
Pipeline
Parameter
Th
e
x1
8a
nd
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 2.17 11/2004
21/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Pipeline Mode Timing (SCD)
Cont
Cont
Deselect Write B
Single Read
Read C
Read C+1 Read C+2 Read C+3 Cont
Single Write
tKL
tKH
tKC
Burst Read
CK
ew
ADSP
tS
tH
fo
rN
ADSC initiated read
ADSC
tS
tH
tH
B
C
tS
GW
tS
tH
ar
eN
ot
BW
Re
co
m
A
m
tS
en
d
ed
ADV
A0–An
Deselect
.
Read A
De
sig
n
Begin
tH
tS
Ba–Bd
E1
tH
E2 and E3 only sampled with ADSP and ADSC
E2
is
tS
th
tH
in
E3
tOE
tS
tOHZ
Q(A)
tKQ
tH
D(B)
tKQX
tLZ
tHZ
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Th
e
x1
8a
nd
x3
6
pa
rt
s
G
DQa–DQd
E1 masks ADSP
sp
ec
if
tS
Deselected with E1
ica
ti o
tH
n
tS
Rev: 2.17 11/2004
22/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Flow Through Mode Timing (SCD)
Begin
Read A
Cont
Cont
Write B
Read C
Read C+1 Read C+2 Read C+3 Read C
Cont
Deselect
tKL
.
tKC
De
sig
n
tKH
CK
ADSP
Fixed High
tS
tH
ADSC
initiated read
ew
tS
tH
fo
rN
ADSC
tS
tH
ed
ADV
B
C
m
A
Re
co
m
A0–An
en
d
tS
tH
tS
tH
tS
tH
BW
n
tS
tH
ica
ti o
Ba–Bd
tS
tH
Deselected with E1
sp
ec
if
E1
tS
tH
E2 and E3 only sampled with ADSC
th
is
E2
in
tS
tH
rt
s
E3
x3
6
pa
G
tH
tS
tOE
tOHZ
Q(A)
D(B)
tKQ
tLZ
tHZ
tKQX
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
Th
e
x1
8a
nd
DQa–DQd
ar
eN
ot
GW
Rev: 2.17 11/2004
23/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Pipeline Mode Timing (DCD)
Cont
Deselect Deselect Write B
Read C
Read C+1 Read C+2 Read C+3 Cont
tKL
tKH
tKC
CK
tS
ew
ADSP
ADSC initiated read
fo
rN
tH
ADSC
tS
tH
ed
ADV
en
d
tS
tH
B
C
tS
GW
tS
tH
ar
eN
ot
BW
m
A
Re
co
m
Ao–An
Deselect Deselect
.
Read A
De
sig
n
Begin
tH
tS
Ba–Bd
tS
ica
ti o
E1
tS
E2 and E3 only sampled with ADSC
tH
sp
ec
if
E2
tS
tH
is
E3
in
th
G
tOE
rt
s
Hi-Z
tS
tOHZ
Q(A)
tKQ
tH
D(B)
tHZ
tLZ
tKQX
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Th
e
x1
8a
nd
x3
6
pa
DQa–DQd
Deselected with E1
n
tH
Rev: 2.17 11/2004
24/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Read A
Cont
Deselect Write B
Read C
Read C+1 Read C+2 Read C+3 Read C
tKL
tKH
tKC
ADSP
ew
CK
Fixed High
tS
tH
ADSC
initiated read
fo
rN
tS
tH
tS
B
C
Re
co
m
A
m
tS
tH
tS
tH
tS
tH
BW
n
tH
tS
ar
eN
ot
GW
ica
ti o
Ba–Bd
tS
tH
tS
tH
E2 and E3 only sampled with ADSP and ADSC
is
E2
E1 masks ADSP
in
th
tS
tH
E3
Deselected with E1
E1 masks ADSP
sp
ec
if
E1
rt
s
G
pa
tH
tS
tOHZ
Q(A)
tKQX
tHZ
tLZ
D(B)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
Th
e
x1
8a
nd
x3
6
tOE
tKQ
DQa–DQd
tH
en
d
ADV
Ao–An
ed
ADSC
tH
tS
Deselect
De
sig
n
Begin
.
Flow Through Mode Timing (DCD)
Rev: 2.17 11/2004
25/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Sleep Mode
.
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
fo
rN
ew
De
sig
n
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
ed
Sleep Mode Timing Diagram
en
d
tKH
tKC
tKL
Re
co
m
m
CK
Setup
Hold
ar
eN
ot
ADSP
ADSC
tZZS
sp
ec
if
ica
ti o
n
ZZ
tZZR
tZZH
Application Tips
Th
e
x1
8a
nd
x3
6
pa
rt
s
in
th
is
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 2.17 11/2004
26/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
JTAG Port Operation
De
sig
n
.
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
fo
rN
ew
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
en
d
m
Re
co
m
Test Data Out
ar
eN
ot
TDO
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
n
Test Data In
ica
ti o
TDI
ed
Pin
sp
ec
if
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
is
JTAG Port Registers
pa
rt
s
in
th
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
x1
8a
nd
x3
6
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Th
e
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
Rev: 2.17 11/2004
27/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
·
·
·
·
·
·
·
·
Boundary Scan Register
ed
·
en
d
·
fo
rN
ew
De
sig
n
.
JTAG TAP Block Diagram
108
0
Re
co
m
Bypass Register
2 1 0
ar
eN
ot
Instruction Register
TDI
0
m
1
·
TDO
ID Code Register
·
· · ·
2 1 0
ica
ti o
n
31 30 29
sp
ec
if
Control Signals
TMS
Test Access Port (TAP) Controller
is
TCK
Th
e
x1
8a
nd
x3
6
pa
rt
s
in
th
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 2.17 11/2004
28/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GSI Technology
JEDEC Vendor
ID Code
.
I/O
Configuration
Not Used
De
sig
n
Die
Revision
Code
Presence Register
ID Register Contents
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x72
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0 0 1 1 0 1 1 0 0 1
1
x36
X
X
X
X
0
0
0
X
1
0
0
1
0
0
0
0
1
0
0
0
0
0 0 1 1 0 1 1 0 0 1
1
x32
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0 0 1 1 0 1 1 0 0 1
1
x18
X
X
X
X
0
0
0
X
1
0
0
1
0
0
0
0
1
0
1
0
0
0 0 1 1 0 1 1 0 0 1
1
x16
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0 0 1 1 0 1 1 0 0 1
1
fo
rN
ed
en
d
m
Tap Controller Instruction Set
ew
Bit #
ar
eN
ot
Re
co
m
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
Th
e
x1
8a
nd
x3
6
pa
rt
s
in
th
is
sp
ec
if
ica
ti o
n
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 2.17 11/2004
29/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
JTAG Tap Controller State Diagram
0
1
Run Test Idle
Select DR
1
0
0
1
1
Capture DR
Capture IR
0
1
Shift IR
0
1
1
Exit2 DR
Update DR
0
m
1
Exit2 IR
1
0
0
Update IR
1
0
ica
ti o
n
1
0
Pause IR
0
ar
eN
ot
1
0
Re
co
m
1
en
d
0
0
Exit1 IR
ed
Exit1 DR
Pause DR
fo
rN
1
ew
0
Shift DR
1
Select IR
.
0
Test Logic Reset
De
sig
n
1
sp
ec
if
Instruction Descriptions
th
is
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
Th
e
x1
8a
nd
x3
6
pa
rt
s
in
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Rev: 2.17 11/2004
30/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
ew
De
sig
n
.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.
ed
fo
rN
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
Re
co
m
m
en
d
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Instruction
Code
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
in
ar
eN
ot
JTAG TAP Instruction Set Summary
Description
Notes
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
n
1
pa
rt
s
th
is
sp
ec
if
ica
ti o
1, 2
1
Th
e
x1
8a
nd
x3
6
BYPASS
111
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 2.17 11/2004
31/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
JTAG Port Recommended Operating Conditions and DC Characteristics
Symbol
Min.
Max.
3.3 V Test Port Input High Voltage
VIHJ3
2.0
VDD3 +0.3
V
1
3.3 V Test Port Input Low Voltage
VILJ3
–0.3
0.8
V
1
2.5 V Test Port Input High Voltage
VIHJ2
0.6 * VDD2
VDD2 +0.3
V
1
2.5 V Test Port Input Low Voltage
VILJ2
–0.3
0.3 * VDD2
V
1
TMS, TCK and TDI Input Leakage Current
IINHJ
–300
1
uA
2
TMS, TCK and TDI Input Leakage Current
IINLJ
–1
100
uA
3
TDO Output Leakage Current
IOLJ
–1
1
uA
4
Test Port Output High Voltage
VOHJ
1.7
—
V
5, 6
Test Port Output Low Voltage
VOLJ
—
0.4
V
5, 7
Test Port Output CMOS High
VOHJC
VDDQ – 100 mV
—
V
5, 8
Test Port Output CMOS Low
VOLJC
—
100 mV
V
5, 9
De
sig
n
ew
fo
rN
ed
en
d
m
Re
co
m
Unit Notes
.
Parameter
sp
ec
if
ica
ti o
n
ar
eN
ot
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOHJC = +100 uA
is
JTAG Port AC Test Conditions
th
Parameter
in
Input high level
pa
Input slew rate
rt
s
Input low level
Conditions
VDD – 0.2 V
DQ
0.2 V
50Ω
1 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
x3
6
JTAG Port AC Test Load
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
Th
e
x1
8a
nd
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 2.17 11/2004
32/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
.
TCK
De
sig
n
tTH
tTS
TDI
tTH
ew
tTS
fo
rN
TMS
tTKQ
TDO
ed
tTH
en
d
tTS
Symbol
Min
TCK Cycle Time
tTKC
50
—
ns
TCK Low to TDO Valid
tTKQ
—
20
ns
TCK High Pulse Width
tTKH
20
—
ns
TCK Low Pulse Width
tTKL
20
—
ns
TDI & TMS Set Up Time
tTS
10
—
ns
TDI & TMS Hold Time
tTH
10
—
ns
ica
ti o
sp
ec
if
is
Unit
pa
rt
s
in
Max
n
Parameter
th
JTAG Port AC Electrical Characteristics
ar
eN
ot
Re
co
m
m
Parallel SRAM input
Th
e
x1
8a
nd
x3
6
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: [email protected].
Rev: 2.17 11/2004
33/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
A
De
sig
n
Side View
D
aaa
.
C A1
fo
rN
ew
D1
E
E1
Bottom View
ar
eN
ot
Re
co
m
m
en
d
ed
e
∅b
Min
Typ
Max
A
—
—
1.70
A1
0.40
0.50
∅b
0.50
0.60
c
0.31
0.36
D
21.9
22.0
Symbol
Min
Typ
Max
Units
mm
D1
—
18.0 (BSC)
—
mm
0.60
mm
E
13.9
14.0
14.1
mm
0.70
mm
E1
—
10.0 (BSC)
—
mm
0.38
mm
e
—
1.00 (BSC)
—
mm
22.1
mm
aaa
—
0.15
—
mm
is
th
in
Th
e
x1
8a
nd
x3
6
pa
rt
s
Rev 1.0
Units
sp
ec
if
Symbol
ica
ti o
n
e
Rev: 2.17 11/2004
34/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Package Dimensions—165-Bump FPBGA (Package D; Variation 1)
BOTTOM
Ø0.10M C
Ø0.25M C A B
Ø0.40~0.50
1 2 3 4 5 6 7 8 9 10
11 10 9 8 7 6 5 4 3 2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
ed
1.0
1.0
10.
ica
ti o
13±0.0
0.20(4
0.25~0.4
1.20
SEATING
Th
e
x1
8a
nd
x3
6
pa
rt
s
in
th
is
C
B
sp
ec
if
0.15 C
n
0.45±0.05
0.25 C
A
ar
eN
ot
Re
co
m
m
en
d
1.0
14.
15±0.0
1.0
fo
rN
ew
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
(0.26
A1
.
TOP
De
sig
n
A1
Rev: 2.17 11/2004
35/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
TOP VIEW
2
3
4
5
6
7
.
1
BOTTOM VIEW
A1
Ø0.10S C
Ø0.30S C AS B S
Ø0.60~0.90 (119x)
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
ed
ar
eN
ot
Re
co
m
m
en
d
20.32
22±0.10
1.27
fo
rN
ew
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
De
sig
n
A1
ica
ti o
sp
ec
if
0.15 C
n
1.27
A
0.20(4x)
14±0.10
is
SEATING PLANE
7.62
0.50~0.70
1.86.±0.13
C
Th
e
x1
8a
nd
x3
6
pa
rt
s
in
th
0.56±0.05
0.70±0.05
0.15 C
B
Rev: 2.17 11/2004
36/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Part Number1
Type
Package
Speed2
(MHz/ns)
1M x 18
GS816218B-250
Pipeline/Flow Through
119 BGA (var. 2)
250/5.5
1M x 18
GS816218B-225
Pipeline/Flow Through
119 BGA (var. 2)
225/6
1M x 18
GS816218B-200
Pipeline/Flow Through
119 BGA (var. 2)
200/6.5
C
1M x 18
GS816218B-166
Pipeline/Flow Through
119 BGA (var. 2)
166/7
C
1M x 18
GS816218B-150
Pipeline/Flow Through
119 BGA (var. 2)
150/7.5
C
1M x 18
GS816218B-133
Pipeline/Flow Through
119 BGA (var. 2)
133/8.5
C
512K x 36
GS816236B-250
Pipeline/Flow Through
119 BGA (var. 2)
250/5.5
C
512K x 36
GS816236B-225
Pipeline/Flow Through
119 BGA (var. 2)
225/6
C
512K x 36
GS816236B-200
Pipeline/Flow Through
119 BGA (var. 2)
200/6.5
C
512K x 36
GS816236B-166
Pipeline/Flow Through
119 BGA (var. 2)
166/7
C
512K x 36
GS816236B-150
Pipeline/Flow Through
119 BGA (var. 2)
150/7.5
C
512K x 36
GS816236B-133
Pipeline/Flow Through
119 BGA (var. 2)
133/8.5
C
1M x 18
GS816218D-250
Pipeline/Flow Through
165 BGA (var. 1)
250/5.5
C
1M x 18
GS816218D-225
Pipeline/Flow Through
165 BGA (var. 1)
225/6
C
1M x 18
GS816218D-200
Pipeline/Flow Through
165 BGA (var. 1)
200/6.5
C
1M x 18
GS816218D-166
Pipeline/Flow Through
165 BGA (var. 1)
166/7
C
1M x 18
GS816218D-150
Pipeline/Flow Through
165 BGA (var. 1)
150/7.5
C
1M x 18
GS816218D-133
Pipeline/Flow Through
165 BGA (var. 1)
133/8.5
C
512K x 36
GS816236D-250
Pipeline/Flow Through
165 BGA (var. 1)
250/5.5
C
512K x 36
GS816236D-225
Pipeline/Flow Through
165 BGA (var. 1)
225/6
C
512K x 36
GS816236D-200
Pipeline/Flow Through
165 BGA (var. 1)
200/6.5
C
512K x 36
GS816236D-166
Pipeline/Flow Through
165 BGA (var. 1)
166/7
C
512K x 36
GS816236D-150
Pipeline/Flow Through
165 BGA (var. 1)
150/7.5
C
512K x 36
GS816236D-133
Pipeline/Flow Through
165 BGA (var. 1)
133/8.5
C
Status
De
sig
n
ew
ed
en
d
m
Re
co
m
ar
eN
ot
n
ica
ti o
sp
ec
if
is
th
in
rt
s
pa
x3
6
x1
8a
nd
TA3
.
Org
fo
rN
Ordering Information for GSI Synchronous Burst RAMs
C
C
Th
e
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816236-200IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 2.17 11/2004
37/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
256K x 72
GS816272C-200
Pipeline/Flow Through
209 BGA
200/6.5
C
256K x 72
GS816272C-166
Pipeline/Flow Through
209 BGA
166/7
256K x 72
GS816272C-150
Pipeline/Flow Through
209 BGA
150/7.5
256K x 72
GS816272C-133
Pipeline/Flow Through
209 BGA
133/8.5
1M x 18
GS816218B-250I
Pipeline/Flow Through
119 BGA (var. 2)
250/5.5
I
1M x 18
GS816218B-225I
Pipeline/Flow Through
119 BGA (var. 2)
225/6
I
1M x 18
GS816218B-200I
Pipeline/Flow Through
119 BGA (var. 2)
200/6.5
I
1M x 18
GS816218B-166I
Pipeline/Flow Through
119 BGA (var. 2)
166/7
I
1M x 18
GS816218B-150I
Pipeline/Flow Through
119 BGA (var. 2)
150/7.5
I
1M x 18
GS816218B-133I
Pipeline/Flow Through
119 BGA (var. 2)
133/8.5
I
512K x 36
GS816236B-250I
Pipeline/Flow Through
119 BGA (var. 2)
250/5.5
I
512K x 36
GS816236B-225I
Pipeline/Flow Through
119 BGA (var. 2)
225/6
I
512K x 36
GS816236B-200I
Pipeline/Flow Through
119 BGA (var. 2)
200/6.5
I
512K x 36
GS816236B-166I
Pipeline/Flow Through
119 BGA (var. 2)
166/7
I
512K x 36
GS816236B-150I
Pipeline/Flow Through
119 BGA (var. 2)
150/7.5
I
512K x 36
GS816236B-133I
Pipeline/Flow Through
119 BGA (var. 2)
133/8.5
I
1M x 18
GS816218D-250I
Pipeline/Flow Through
165 BGA (var. 1)
250/5.5
I
1M x 18
GS816218D-225I
Pipeline/Flow Through
165 BGA (var. 1)
225/6
I
1M x 18
GS816218D-200I
Pipeline/Flow Through
165 BGA (var. 1)
200/6.5
I
1M x 18
GS816218D-166I
Pipeline/Flow Through
165 BGA (var. 1)
166/7
I
1M x 18
GS816218D-150I
Pipeline/Flow Through
165 BGA (var. 1)
150/7.5
I
1M x 18
GS816218D-133I
Pipeline/Flow Through
165 BGA (var. 1)
133/8.5
I
Status
ew
fo
rN
ed
en
d
m
Re
co
m
ar
eN
ot
n
ica
ti o
is
th
in
rt
s
De
sig
n
.
Org
sp
ec
if
Ordering Information for GSI Synchronous Burst RAMs
C
C
C
Th
e
x1
8a
nd
x3
6
pa
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816236-200IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 2.17 11/2004
38/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Ordering Information for GSI Synchronous Burst RAMs
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
512K x 36
GS816236D-250I
Pipeline/Flow Through
165 BGA (var. 1)
250/5.5
I
512K x 36
GS816236D-225I
Pipeline/Flow Through
165 BGA (var. 1)
225/6
512K x 36
GS816236D-200I
Pipeline/Flow Through
165 BGA (var. 1)
200/6.5
512K x 36
GS816236D-166I
Pipeline/Flow Through
165 BGA (var. 1)
166/7
512K x 36
GS816236D-150I
Pipeline/Flow Through
165 BGA (var. 1)
150/7.5
I
512K x 36
GS816236D-133I
Pipeline/Flow Through
165 BGA (var. 1)
133/8.5
I
256K x 72
GS816272C-200I
Pipeline/Flow Through
209 BGA
200/6.5
I
256K x 72
GS816272C-166I
Pipeline/Flow Through
209 BGA
166/7
I
256K x 72
GS816272C-150I
Pipeline/Flow Through
209 BGA
150/7.5
I
256K x 72
GS816272C-133I
Pipeline/Flow Through
209 BGA
133/8.5
I
Status
Re
co
m
m
en
d
ed
fo
rN
ew
De
sig
n
.
Org
I
I
I
ica
ti o
n
ar
eN
ot
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816236-200IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
sp
ec
if
18Mb Sync SRAM Datasheet Revision History
Types of Changes
Format or Content
Page;Revisions;Reason
pa
in
rt
s
GS816218B-150IB 1.00 9/
1999A;GS816218B-150IB
2.00 1/1999B
th
is
DS/DateRev. Code: Old;
New
• Changed BGA package drawing for 209 pin package.
Th
e
x1
8a
nd
x3
6
GS816218B 2.01 1/
2000C;GS816218 B 2.02 1/
2000D
Content
• Converted from 0.25u 3.3V process to 0.18u 2.5V process.
Master File Rev B
• Added x72 Pinout.
• Added GSI Logo.
Rev: 2.17 11/2004
39/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
De
sig
n
.
• Front page; Features - changed 2.5V I/O supply to 2.5V
or3.3V I/O supply; Core and Interface voltages - Changed
paragraph to include information for 3.3V;Completeness
• Absolute Maximum Ratings; Changed VDDQ - Value: From: .05 to VDD : to : -.05 to 3.6; Completeness.
• Recommended Operating Conditions;Changed: I/O Supply
Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from
VDD +0.3 to 3.6; Same page - took out Note 1;Completeness
• Electrical Characteristics - Added second Output High Voltage
line to table; completeness.
• Note: There was not a Rev 2.02 for the 8160Z or the 8161Z.
ed
fo
rN
ew
GS18/362.0 1/2000DGS18/
362.03 2/2000E
Content
• Updated pad out and pin description table (7D changed from
NC to GW)
816218_r2_04;
816218_r2_05
Content
• Updated BGA pin description table to comply with JEDEC
standards
816218_r2_05;
816218_r2_06
Content
• Changed the value of ZZ recovery in the AC Electrical
Characteristics table on page 19 from 20 ns to 100 ns
m
Re
co
m
ica
ti o
n
Content/Format
• Added 225 MHz speed bin
• Updated numbers in page 1 table, AC Characteristics table,
and Operating Currents table
• Updated format to comply with Technical Publications
standards
ar
eN
ot
816218_r2_06;
816218_r2_07
en
d
GS18/362.03 2/2000E;
816218_r2_04
Content
816218_r2_08;
816218_r2_09
Content
th
is
sp
ec
if
816218_r2_07;
816218_r2_08
• Updated Features list on page 1
• Completely reworked table on page 1
• Updated Mode Pin Functions table on page 9
Content
• Added 3.3 V references to entire document
• Updated Operating Conditions table
• Updated JTAG section
• Updated Boundary Scan Chain table
• Updated Operating Currents table and added note
• Updated Application Tips paragraph
• Update table on page 1; added power numbers
Content
• Updated JTAG ID Register table
• Updated Synchronous Truth table
• Updated Operating Currents table
• Updated table on page 1; updated power numbers
• Updated Recommended Operating Conditions table (added
VDDQ references)
pa
x3
6
Th
e
x1
8a
nd
816218_r2_10;
816218_r2_11
816218_r2_11;
816218_r2_12
Rev: 2.17 11/2004
• Updated numbers for Clock to Output Valid (PL) and Clock to
Output Valid (FT) for 166 MHz and 133 MHz on AC Electrical
Characteristics table
Content
rt
s
in
816218_r2_09;
816218_r2_10
• Changed VSSQ references to VSS
• Changed K4 and K8 in 209-bump BGA to NC
• Updated Capitance table—removed Input row and changed
Output row to I/O
40/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816218(B/D)/GS816236(B/D)/GS816272(C)
18Mb Sync SRAM Datasheet Revision History
Types of Changes
Format or Content
Page;Revisions;Reason
Content
• Updated table on page 1
• Added 119-Bump BGA Pin Description table
• Created recommended operating conditions tables on pages
16 and 17
• Updated AC Electrical Characteristics table
• Added Sleep mode description on page 29
• Updated Ordering Information for 225 MHz part (changed
from 7ns to 6.5 ns)
• Updated BSR table (2 and 3 changed to X (value undefined))
• Added 250 MHz speed bin
• Deleted 180 MHz speed bin
Content
• Updated AC Characteristics table
• Updated package designator for 209 BGA from B to C
• Updated VIH from 1.7 to 2.0
• Updated FT power numbers
• Updated Mb references from 16Mb to 18Mb
• Removed ByteSafe references
• Changed DP and QE pins to NC
• Updated ZZ recovery time diagram
• Add 165-bump FPBGA package
• Updated AC Test Conditions table and removed Output Load
2 diagram
Content
• Removed parity I/O bit designation from 165 BGA pinout
• Removed Preliminary banner
• Removed BSR table
• Removed pin locations from pin description tables
sp
ec
if
ica
ti o
816218_r2_14;
816218_r2_15
n
ar
eN
ot
816218_r2_13;
816218_r2_14
Re
co
m
m
en
d
ed
fo
rN
ew
816218_r2_12;
816218_r2_13
De
sig
n
.
DS/DateRev. Code: Old;
New
816218_r2_15;
816218_r2_16
is
Content
th
816218_r2_16;
816218_r2_17
• Updated format
• Updated timing diagrams
Th
e
x1
8a
nd
x3
6
pa
rt
s
in
Format/Content
• Removed 250 MHz and 225 MHz specs from x72
• Updated AC Characteristics table (tHZ, tOE, tOHZ equal to
tKQ (PL) for 250 MHz and 225 MHz)
• New timing diagrams added
Rev: 2.17 11/2004
41/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
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