GSI GS840E32B-180 256k x 18, 128k x 32, 128k x 36 4mb sync burst sram Datasheet

GS840E18/32/36T/B-180/166/150/100
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
TQFP, BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user configurable flow through or pipelined operation.
• Dual Cycle Deselect (DCD) Operation.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or 119 Bump BGA package.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
tCycle
tKQ
IDD
tKQ
tCycle
IDD
-180
5.5ns
3.2ns
330mA
8ns
10ns
190mA
-166
6.0ns
3.5ns
310mA
8.5ns
10ns
190mA
-150
6.6ns
3.8ns
275mA
10ns
10ns
190mA
-100
10ns
4.5ns
190mA
12ns
15ns
140mA
180Mhz - 100Mhz
3.3V VDD
3.3V & 2.5V I/O
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through / Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the
BGA, ). Holding the FT mode pin/bump low places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
DCD Pipelined Reads
The GS840E18/32/36 is a DCD (Dual Cycle Deselect) pipelined
synchronous SRAM. SCD (Single Cycle Deselect) versions are also
available. DCD SRAMs pipeline disable commands to the same
degree as read commands. DCD RAMs hold the deselect command
for one full cycle and then begin turning off their outputs just after the
second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Functional Description
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Applications
Core and Interface Voltages
The GS840E18/32/36 is a 4,718,592 bit (4,194,304 bit for x32
version) high performance synchronous SRAM with a 2 bit burst
address counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPU’s, the device
now finds application in synchronous SRAM applications ranging from
DSP main store to networking chip set support. The GS840E18/32/36
is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA
package.
The GS840E18/32/36 operates on a 3.3V power supply and all inputs/
outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ)
pins are used to de-couple output noise from the internal circuit.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
Rev: 2.05 6/2000
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS840E18/32/36T/B-180/166/150/100
A6
A7
E1
E2
NC
NC
BB
BA
E3
VDD
VSS
CK
GW
BW
G
ADSC
ADSP
ADV
A8
A9
GS840E18 100 Pin TQFP Pinout
LBO
A5
A4
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
FT
VDD
NC
VSS
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K
x
18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.05 6/2000
A17
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
NC
VSS
VDDQ
NC
NC
NC
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
NC
NC
NC
VDDQ
2/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
A6
A7
E1
E2
BD
BC
BB
BA
E3
VDD
VSS
CK
GW
BW
G
ADSC
ADSP
ADV
A8
A9
GS840E32 100 Pin TQFP Pinout
LBO
A5
A4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
128K
x
32
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.05 6/2000
NC
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
NC
DQC8
DQC7
VDDQ
3/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
A6
A7
E1
E2
BD
BC
BB
BA
E3
VDD
VSS
CK
GW
BW
G
ADSC
ADSP
ADV
A8
A9
GS840E36 100 Pin TQFP Pinout
LBO
A5
A4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
DQD9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
128K
x
36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.05 6/2000
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
DQC9
DQC8
DQC7
VDDQ
4/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
TQFP Pin Description
Pin Location
Symbol
Type
Description
37, 36
A0, A1
I
Address field LSB’s and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46,
47, 48, 49, 50
A2-16
I
Address Inputs
80
A17
I
Address Inputs (x18 versions)
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8
I/O
Data Input and Output pins. (x32, x36 Version)
51, 80, 1, 30
DQA9, DQB9,
DQC9, DQD9
I/O
Data Input and Output pins. (x36 Version)
51, 80, 1, 30
NC
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQA1-DQA9
DQB1-DQB9
I/O
Data Input and Output pins. (x18 Version)
51, 52, 53, 56, 57
75, 78, 79
1, 2, 3, 6, 7
25, 28, 29, 30
NC
-
No Connect (x18 Version)
87
BW
I
Byte Write. Writes all enabled bytes. Active Low.
93, 94
BA, BB
I
Byte Write Enable for DQA, DQB Data I/O’s. Active Low.
95, 96
BC, BD
I
Byte Write Enable for DQC, DQD Data I/O’s. Active Low.
(x32, x36 Version)
95, 96
NC
-
No Connect (x18 Version)
89
CK
I
Clock Input Signal. Active High.
88
GW
I
Global Write Enable. Writes all bytes. Active Low.
98, 92
E1, E3
I
Chip Enable. Active Low.
97
E2
I
Chip Enable. Active High.
86
G
I
Output Enable. Active Low.
83
ADV
I
Burst address counter advance enable. Active Low.
84, 85
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller). Active Low.
64
ZZ
I
Sleep Mode control. Active High.
14
FT
I
Flow Through or Pipeline mode. Active Low.
31
LBO
I
Linear Burst Order mode. Active Low.
15, 41, 65, 91
VDD
I
Core power supply.
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
VSS
I
I/O and Core Ground.
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
I
Output driver power supply.
16, 38, 39, 42, 43, 66
NC
-
No Connect.
Rev: 2.05 6/2000
No Connect (x32 Version)
5/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
GS840E18 Pad Out
119 Bump BGA - Top View
Rev: 2.05 6/2000
1
2
3
4
5
6
7
A
VDDQ
A6
A7
ADSP
A8
A9
VDDQ
B
NC
E2
A4
ADSC
A15
E3
NC
C
NC
A5
A3
VDD
A14
A16
NC
D
DQB1
NC
VSS
NC
VSS
DQA9
NC
E
NC
DQB2
VSS
E1
VSS
NC
DQA8
F
VDDQ
NC
VSS
G
VSS
DQA7
VDDQ
G
NC
DQB3
BB
ADV
NC
NC
DQA6
H
DQB4
NC
VSS
GW
VSS
DQA5
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
NC
DQB5
VSS
CK
VSS
NC
DQA4
L
DQB6
NC
NC
NC
BA
DQA3
NC
M
VDDQ
DQB7
VSS
BW
VSS
NC
VDDQ
N
DQB8
NC
VSS
A1
VSS
DQA2
NC
P
NC
DQB9
VSS
A0
VSS
NC
DQA1
R
NC
A2
LBO
VDD
FT
A13
NC
T
NC
A10
A11
NC
A12
A17
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
6/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
GS840E32 Pad Out
119 Bump BGA - Top View
Rev: 2.05 6/2000
1
2
3
4
5
6
7
A
VDDQ
A6
A7
ADSP
A8
A9
VDDQ
B
NC
E2
A4
ADSC
A15
E3
NC
C
NC
A5
A3
VDD
A14
A16
NC
D
DQC4
NC
VSS
NC
VSS
NC
DQB4
E
DQC3
DQC8
VSS
E1
VSS
DQB8
DQB3
F
VDDQ
DQC7
VSS
G
VSS
DQB7
VDDQ
G
DQC2
DQC6
BC
ADV
BB
DQB6
DQB2
H
DQC1
DQC5
VSS
GW
VSS
DQB5
DQB1
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQD1
DQD5
VSS
CK
VSS
DQA5
DQA1
L
DQD2
DQD6
BD
NC
BA
DQA6
DQA2
M
VDDQ
DQD78
VSS
BW
VSS
DQA7
VDDQ
N
DQD3
DQD8
VSS
A1
VSS
DQA8
DQA3
P
DQD4
NC
VSS
A0
VSS
NC
DQA4
R
NC
A2
LBO
VDD
FT
A13
NC
T
NC
NC
A10
A11
A12
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
7/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
GS840E36Pad Out
119 Bump BGA - Top View
Rev: 2.05 6/2000
1
2
3
4
5
6
7
A
VDDQ
A6
A7
ADSP
A8
A9
VDDQ
B
NC
E2
A4
ADSC
A15
E3
NC
C
NC
A5
A3
VDD
A14
A16
NC
D
DQC4
DQC9
VSS
NC
VSS
DQB9
DQB4
E
DQC3
DQC8
VSS
E1
VSS
DQB8
DQB3
F
VDDQ
DQC7
VSS
G
VSS
DQB7
VDDQ
G
DQC2
DQC6
BC
ADV
BB
DQB6
DQB2
H
DQC1
DQC5
VSS
GW
VSS
DQB5
DQB1
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQD1
DQD5
VSS
CK
VSS
DQA5
DQA1
L
DQD2
DQD6
BD
NC
BA
DQA6
DQA2
M
VDDQ
DQD78
VSS
BW
VSS
DQA7
VDDQ
N
DQD3
DQD8
VSS
A1
VSS
DQA8
DQA3
P
DQD4
DQD9
VSS
A0
VSS
DQA9
DQA4
R
NC
A2
LBO
VDD
FT
A13
NC
T
NC
NC
A10
A11
A12
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
8/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
BGA Pin Description
Pin Location
Symbol
Type
Description
N4, P4
A0, A1
I
Address field LSB’s and Address Counter Preset Inputs.
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, R2, R6, T3, T5
An
I
Address Inputs
T4
An
T2, T6
NC
-
No Connect (x32/36 Versions)
T2, T6
An
I
Address Input (x18 Version)
K7, K6, L7, L6, M6, N7, N6, P7
H7, H6, G7, G6, F6, E7, E6, D7
H1, H2, G1, G2, F2, E1, E2, D1
K1, K2, L1, L2, M2, N1, N2, P1
DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8
I/O
Data Input and Output pins. (x32/36 Versions)
P6, D6, D2, P2
DQA9, DQB9,
DQC9, DQD9
I/O
Data Input and Output pins. (x36 Version)
P6, D6, D2, P2
NC
-
No Connect (x32 Version)
L5, G5, G3, L3
BA, BB, BC, BD
I
Byte Write Enable for DQA, DQB, DQC, DQD I/O’s. Active Low. ( x36 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
DQA1-DQA9
DQB1-DQB9
I/O
Data Input and Output pins. (x18 Version)
L5, G3
BA, BB
I
Byte Write Enable for DQA, DQB I/O’s. Active Low. ( x18 Version)
B1, C1, R1, T1, U2, J3, U3, D4, L4,
U4, J5, U5, U6, B7, C7, R7
NC
-
No Connect
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, B1, E1, F2, G1, H2, K1, L2, N2,
P1, G5, L3, T4
NC
-
No Connect (x18 Version)
K4
CK
I
Clock Input Signal. Active High.
M4
BW
I
Byte Write. Writes all enabled bytes. Active Low.
H4
GW
I
Global Write Enable. Writes all bytes. Active Low.
E4, B6
E1, E3
I
Chip Enable. Active Low.
B2
E2
I
Chip Enable. Active High.
F4
G
I
Output Enable. Active Low.
G4
ADV
I
Burst address counter advance enable. Active Low.
A4, B4
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller). Active Low.
T7
ZZ
I
Sleep Mode control. Active High.
R5
FT
I
Flow Through or Pipeline mode. Active Low.
R3
LBO
I
Linear Burst Order mode. Active Low.
J2, C4, J4, R4, J6
VDD
I
Core power supply.
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
VSS
I
I/O and Core Ground.
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
VDDQ
I
Output driver power supply.
Rev: 2.05 6/2000
Address Input (x32/36 Versions)
9/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
GS840E18/32/36 Block Diagram
Register
A0-An
D
Q
A0
A0
D0
Q0
A1
A1
D1
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
D
36
Q
BB
36
4
Register
D
Q
D
Q
Q
D
D
Register
Register
Q
Register
BC
BD
Register
D
Q
Register
E1
E3
E2
D
Q
Register
D
Q
FT
G
ZZ
0
Power Down
DQx0-DQx9
Control
Note: Only x36 version shown for simplicity.
Rev: 2.05 6/2000
10/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Mode Pin Functions
Mode Name
Pin Name State
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
Function
L
Linear Burst
H or NC
Interleaved Burst
L
Flow Through
H or NC
Pipeline
L or NC
Active
H
Standby, IDD = ISB
Note:
There are pull up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Interleaved Burst Sequence
Linear Burst Sequence
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
3rd address
10
11
4th address
11
00
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
00
2nd address
01
00
11
10
00
01
3rd address
10
11
00
01
01
10
4th address
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte A
H
L
L
H
H
H
2, 3
Write byte B
H
L
H
L
H
H
2, 3
Write byte C
H
L
H
H
L
H
2, 3, 4
Write byte D
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Note:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 2.05 6/2000
11/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Synchronous Truth Table
Operation
State
Address Used Diagram
Key5
E1
E2
ADSP
ADSC
ADV
W3
DQ4
Deselect Cycle, Power Down
None
X
H
X
X
L
X
X
High-Z
Deselect Cycle, Power Down
None
X
L
F
L
X
X
X
High-Z
Deselect Cycle, Power Down
None
X
L
F
H
L
X
X
High-Z
Read Cycle, Begin Burst
External
R
L
T
L
X
X
X
Q
Read Cycle, Begin Burst
External
R
L
T
H
L
X
F
Q
Write Cycle, Begin Burst
External
W
L
T
H
L
X
T
D
Read Cycle, Continue Burst
Next
CR
X
X
H
H
L
F
Q
Read Cycle, Continue Burst
Next
CR
H
X
X
H
L
F
Q
Write Cycle, Continue Burst
Next
CW
X
X
H
H
L
T
D
Write Cycle, Continue Burst
Next
CW
H
X
X
H
L
T
D
Read Cycle, Suspend Burst
Current
X
X
H
H
H
F
Q
Read Cycle, Suspend Burst
Current
H
X
X
H
H
F
Q
Write Cycle, Suspend Burst
Current
X
X
H
H
H
T
D
Write Cycle, Suspend Burst
Current
H
X
X
H
H
T
D
Note:
1. X = Don’t Care, H = High, L = Low.
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5.
6.
7.
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 2.05 6/2000
12/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Simplified State Diagram
X
Deselect
W
R
Simple Burst Synchronous Operation
Simple Synchronous Operation
W
X
R
R
First Write
CW
First Read
CR
W
X
CR
R
R
X
Burst Write
Burst Read
X
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
Rev: 2.05 6/2000
13/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Simplified State Diagram with G
X
Deselect
W
R
W
X
R
R
First Write
CR
CW
W
CW
W
X
First Read
X
CR
R
Burst Write
R
CR
CW
W
Burst Read
X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 2.05 6/2000
14/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
-0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
-0.5 to VDD
V
VCK
Voltage on Clock Input Pin
-0.5 to 6
V
VI/O
Voltage on I/O Pins
-0.5 to VDDQ+0.5 (≤ 4.6 V max.)
V
VIN
Voltage on Other Input Pins
-0.5 to VDD+0.5 (≤ 4.6 V max.)
V
IIN
Input Current on Any Pin
+/- 20
mA
IOUT
Output Current on Any I/O Pin
+/- 20
mA
PD
Package Power Dissipation
1.5
W
TSTG
Storage Temperature
-55 to 125
oC
TBIAS
Temperature Under Bias
-55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Supply Voltage
VDD
3.135
3.3
3.6
V
I/O Supply Voltage
VDDQ
2.375
2.5
VDD
V
1
Input High Voltage
VIH
1.7
---
VDD+0.3
V
2
Input Low Voltage
VIL
-0.3
---
0.8
V
2
Ambient Temperature (Commercial Range Versions)
TA
0
25
70
°C
3
TA
°C
3
Ambient Temperature (Industrial Range Versions)
-40
25
85
Note:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V ≤ VDDQ ≤ 2.375V (i.e. 2.5V I/O)
and 3.6V ≤ VDDQ ≤ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be -2V > Vi < VDD+2V with a pulse width not to exceed 20% tKC.
Rev: 2.05 6/2000
15/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD+-2.0V
VSS
50%
50%
VDD
VSS-2.0V
20% tKC
VIL
Capacitance
(TA=25oC, f=1MHZ, VDD=3.3V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Control Input Capacitance
CI
VDD=3.3V
3
4
pF
Input Capacitance
CIN
VIN=0V
4
5
pF
COUT
VOUT=0V
6
7
pF
Output Capacitance
Note: This parameter is sample tested.
Package Thermal Characteristics
Rating
Layer Board
Symbol
TQFP Max
BGA Max
Unit
Notes
Junction to Ambient (at 200 lfm)
single
RΘJA
40
38
°C/W
1,2,4
Junction to Ambient (at 200 lfm)
four
RΘJA
24
21
°C/W
1,2,4
RΘJC
9
5
Junction to Case (TOP)
°C/W
3,4
Notes:
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
Rev: 2.05 6/2000
16/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
AC Test Conditions
Parameter
Conditions
Input high level
2.3V
Input low level
0.2V
Input slew rate
1V/ns
Input reference level
1.25V
Output reference level
1.25V
Output load
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ.
4. Device is deselected as defined by the Truth Table.
Output Load 2
Output Load 1
DQ
2.5V
50Ω
225Ω
DQ
30pF*
5pF*
VT=1.25V
225Ω
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
IIL
VIN = 0 to VDD
-1uA
1uA
ZZ Input Current
IINZZ
VDD ≥ VIN ≥ VIH
0V ≤ VIN ≤ VIH
-1uA
-1uA
1uA
300uA
Mode Pin Input Current
IINM
VDD ≥ VIN ≥ VIL
0V ≤ VIN ≤ VIL
-300uA
-1uA
1uA
1uA
Output Leakage Current
IOL
Output Disable,
VOUT = 0 to VDD
-1uA
1uA
Output High Voltage
VOH
IOH = - 4mA, VDDQ=2.375V
1.7V
Output High Voltage
VOH
IOH = - 4mA, VDDQ=3.135V
2.4V
Output Low Voltage
VOL
IOL = 4mA
Input Leakage Current
(except mode pins)
Rev: 2.05 6/2000
0.4V
17/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Operating Currents
-180
Parameter Test Conditions
Symbol
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
IDD
Pipeline
Operating
Current
Standby
Current
ZZ ≥ VDD - 0.2V
Deselect
Current
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
Rev: 2.05 6/2000
0 to
70°C
-40 to
85°C
-166
0 to
70°C
-40 to
85°C
-150
0 to
70°C
-40 to
85°C
-100
0 to
70°C
-40 to
85°C
330mA 340mA 310mA 320mA 275mA 285mA 190mA 200mA
IDD
190mA 200mA 190mA 200mA 190mA 200mA 140mA 150mA
Flow-Thru
ISB
Pipeline
30mA
40mA
30mA
40mA
30mA
40mA
30mA
40mA
ISB
Flow-Thru
30mA
40mA
30mA
40mA
30mA
40mA
30mA
40mA
120mA 130mA 110mA 120mA 105mA 115mA
80mA
90mA
80mA
65mA
75mA
IDD
Pipeline
IDD
Flow-Thru
90mA
80mA
90mA
80mA
90mA
18/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
AC Electrical Characteristics
Pipeline
FlowThru
Parameter
Symbol
Clock Cycle Time
-180
-166
-150
-100
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tKC
5.5
---
6.0
---
6.7
---
10
---
ns
Clock to Output Valid
tKQ
---
3.2
---
3.5
---
3.8
---
4.5
ns
Clock to Output Invalid
tKQX
1.5
---
1.5
---
1.5
---
1.5
---
ns
Clock to Output in Low-Z
tLZ
1
1.5
---
1.5
---
1.5
---
1.5
---
ns
Clock Cycle Time
tKC
10.0
---
10.0
---
10.0
---
15.0
---
ns
Clock to Output Valid
tKQ
---
8.0
---
8.5
---
10.0
---
12.0
ns
Clock to Output Invalid
tKQX
3.0
---
3.0
---
3.0
---
3.0
---
ns
Clock to Output in Low-Z
tLZ1
3.0
---
3.0
---
3.0
---
3.0
---
ns
Clock HIGH Time
tKH
1.3
---
1.3
---
1.5
---
2
---
ns
Clock LOW Time
tKL
1.5
---
1.5
---
1.7
---
2.2
---
ns
Clock to Output in High-Z
tHZ1
1.5
3.2
1.5
3.5
1.5
3.8
1.5
5
ns
G to Output Valid
tOE
---
3.2
---
3.5
---
3.8
---
5
ns
G to output in Low-Z
tOLZ1
0
---
0
---
0
---
0
---
ns
G to output in High-Z
tOHZ1
---
3.2
---
3.5
---
3.8
---
5
ns
Setup time
tS
1.5
---
1.5
---
1.5
---
2.0
---
ns
Hold time
tH
0.5
---
0.5
---
0.5
---
0.5
---
ns
ZZ setup time
tZZS2
5
---
5
---
5
---
5
---
ns
ZZ hold time
tZZH2
1
---
1
---
1
---
1
---
ns
ZZ recovery
tZZR
20
---
20
---
20
---
20
---
ns
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 2.05 6/2000
19/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Write Cycle Timing
Single Write
Burst Write
Deselected
Write
CK
tS tH
tKH tKL
tKC
ADSP is blocked by E1 inactive
ADSP
tS tH
ADSC initiated write
ADSC
tS tH
ADV
tS tH
A0-An
ADV must be inactive for ADSP Write
WR2
WR1
WR3
tS tH
GW
tS tH
BW
tS tH
BA - BD
WR1
WR1
WR2
tS tH
WR3
WR3
E1 masks ADSP
E1
tS tH
Deselected with E2
E2
tS tH
E2 and E3 only sampled with ADSP or ADSC
E3
G
tS tH
DQA - DQD
Rev: 2.05 6/2000
Hi-Z
Write specified byte for 2a and all bytes for 2b, 2c& 2d
D1a
D2a
D2b
D2c
D2d
20/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
D3a
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tKH
tS tH
tKC
ADSP is blocked by E1 inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
Suspend Burst
Suspend Burst
ADV
tS tH
A0-An
RD1
RD2
RD3
tS
tH
tS
tH
GW
BW
BA - BD
tS tH
E1 masks ADSP
E1
tS tH
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
tS tH
E3
tOE
tOHZ
G
tKQX
tOLZ
DQA-DQD
Q1a
Hi-Z
Q2a
tKQX
Q2b
Q2c
Q2d
Q3a
tLZ
tHZ
tKQ
Rev: 2.05 6/2000
21/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Flow Through Read-Write Cycle Timing
Single Write
Single Read
Burst Read
CK
tS tH
tKC
tKH tKL
ADSP is blocked by E inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0-An
WR1
RD1
RD2
tS tH
GW
tH
tS
BW
tS tH
BA - BD
WR1
tS tH
E1 masks ADSP
E1
tS tH
E2 and E3 only sampled with ADSP and ADSC
E2
tS tH
Deselected with E3
E3
tOE
tOHZ
G
tS
tKQ
DQA - DQD
Hi-Z
Q1a
tH
D1a
Q2a
Q2b
Q2c
Q2d
Q2a
Burst wrap around to it’s initial state
Rev: 2.05 6/2000
22/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Pipelined DCD Read Cycle Timing
Single Read
tKL
Burst Read
CK
tS tH
tKH
tKC
ADSP is blocked by E1 inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
Suspend Burst
ADV
tS tH
A0-An
RD1
RD3
RD2
tS
tH
tS
tH
GW
BW
BA - BD
tS tH
E1 masks ADSP
E1
tS tH
E2 and E3 only sampled with ADSP or ADSC
E2
tS tH
Deselected with E2
E3
tOE
G
tOHZ
Hi-Z
tOLZ
Q1a
DQA-DQD
tKQX
Q2a
tKQX
Q2b
Q2c
Q2d
Q3a
tLZ
tHZ
tKQ
Rev: 2.05 6/2000
23/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Pipelined DCD Read-Write Cycle Timing
Single Write
Burst Read
Single Read
tKL
CK
tS tH
tKH
ADSP is blocked by E1 inactive
tKC
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0-An
WR1
RD1
RD2
tS tH
GW
tS
tH
BW
tS tH
BA - BD
WR1
tS tH
E1 masks ADSP
E1
tS tH
E2 and E3 only sampled with ADSP and ADSC
E2
tS tH
Deselected with E3
E3
tOE
tOHZ
G
DQA - DQD
Rev: 2.05 6/2000
Hi-Z
tS tH
tKQ
Q1a
D1a
Q2a
24/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Q2b
Q2C
Q2d
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
CK
tS tH
tKC
tKH tKL
ADSP
ADSC
tZZS
ZZ
~ ~
~ ~
~ ~
~~
~ ~
~
Sleep Mode Timing Diagram
tZZH
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in
a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in
transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to
manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised
to avoid excessive bus contention.
Rev: 2.05 6/2000
25/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
GS 840E18/32/36 Output Driver Characteristics
60
Pull Down Drivers
40
20
VDDQ
I Out
0
I Out (mA)
VOut
VSS
-20
-40
Pull Up Drivers
-60
-80
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD LD
Rev: 2.05 6/2000
3.3V PD LD
3.1V PD LD
3.1V PU LD
26/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
3.3V PU LD
3.6V PU LD
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
TQFP Package Drawing
Description
Min.
Nom.
Max
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
L
Foot Length
L1
Lead Length
Y
Coplanarity
θ
Lead Angle
D
D1
0.60
e
b
0.75
1.00
0.10
0°
7°
A1
A2
Y
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion
Rev: 2.05 6/2000
c
0.20
0.65
0.45
L1
θ
Pin 1
Symbol
L
27/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
E1
E
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Package Dimensions - 119 Pin BGA
A
Pin 1
Corner
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
G
B
P
S
D
N
R
Bottom View
Top View
Symbol
Description
A
Width
13.8
14.0
14.2
B
Length
21.8
22.0
22.2
C
Package Height (including ball)
-
D
Ball Size
0.60
0.75
0.90
E
Ball Height
0.50
0.60
0.70
F
Package Height (excluding balls)
1.46
1.70
G
Width between Balls
1.27
K
Package Height above board
N
Cut-out Package Width
12.00
P
Foot Length
19.50
R
Width of package between balls
7.62
S
Length of package between balls
20.32
T
Variance of Ball Height
0.15
C
F
E
K
T
Package Dimensions - 119 Pin BGA
Min. Nom. Max
0.80
2.40
0.90
1.00
Unit: mm
Side View
Rev: 2.05 6/2000
28/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Ordering Information for GSI Synchronous Burst RAMS
Speed2
(Mhz/ TA3
ns)
Org
Part Number1
Type
Package
256K x 18
GS840E18T-180
Pipeline/Flow Through
TQFP
180/8
C
256K x 18
GS840E18T-166
Pipeline/Flow Through
TQFP
166/8.5
C
256K x 18
GS840E18T-150
Pipeline/Flow Through
TQFP
150/10
C
256K x 18
GS840E18T-100
Pipeline/Flow Through
TQFP
100/12
C
128K x 32
GS840E32T-180
Pipeline/Flow Through
TQFP
180/8
C
128K x 32
GS840E32T-166
Pipeline/Flow Through
TQFP
166/8.5
C
128K x 32
GS840E32T-150
Pipeline/Flow Through
TQFP
150/10
C
128K x 32
GS840E32T-100
Pipeline/Flow Through
TQFP
100/12
C
128K x 36
GS840E36T-180
Pipeline/Flow Through
TQFP
180/8
C
128K x 36
GS840E36T-166
Pipeline/Flow Through
TQFP
166/8.5
C
128K x 36
GS840E36T-150
Pipeline/Flow Through
TQFP
150/10
C
128K x 36
GS840E36T-100
Pipeline/Flow Through
TQFP
100/12
C
256K x 18
GS840E18T-180I
Pipeline/Flow Through
TQFP
180/8
I
256K x 18
GS840E18T-166I
Pipeline/Flow Through
TQFP
166/8.5
I
256K x 18
GS840E18T-150I
Pipeline/Flow Through
TQFP
150/10
I
256K x 18
GS840E18T-100I
Pipeline/Flow Through
TQFP
100/12
I
128K x 32
GS840E32T-180I
Pipeline/Flow Through
TQFP
180/8
I
128K x 32
GS840E32T-166I
Pipeline/Flow Through
TQFP
166/8.5
I
128K x 32
GS840E32T-150I
Pipeline/Flow Through
TQFP
150/10
I
128K x 32
GS840E32T-100I
Pipeline/Flow Through
TQFP
100/12
I
128K x 36
GS840E36T-180I
Pipeline/Flow Through
TQFP
180/8
I
128K x 36
GS840E36T-166I
Pipeline/Flow Through
TQFP
166/8.5
I
128K x 36
GS840E36T-150I
Pipeline/Flow Through
TQFP
150/10
I
128K x 36
GS840E36T-100I
Pipeline/Flow Through
TQFP
100/12
I
256K x 18
GS840E18B-180
Pipeline/Flow Through
BGA
180/8
C
256K x 18
GS840E18B-166
Pipeline/Flow Through
BGA
166/8.5
C
256K x 18
GS840E18B-150
Pipeline/Flow Through
BGA
150/10
C
256K x 18
GS840E18B-100
Pipeline/Flow Through
BGA
100/12
C
128K x 32
GS840E32B-180
Pipeline/Flow Through
BGA
180/8
C
Status
Not Available
Not Available
Not Available
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840E32T-7.5T.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode.
Each device is Pipeline / Flow through mode selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Rev: 2.05 6/2000
29/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Speed2
(Mhz/ TA3
ns)
Org
Part Number1
Type
Package
128K x 32
GS840E32B-166
Pipeline/Flow Through
BGA
166/8.5
C
128K x 32
GS840E32B-150
Pipeline/Flow Through
BGA
150/10
C
128K x 32
GS840E32B-100
Pipeline/Flow Through
BGA
100/12
C
128K x 36
GS840E36B-180
Pipeline/Flow Through
BGA
180/8
C
128K x 36
GS840E36B-166
Pipeline/Flow Through
BGA
166/8.5
C
128K x 36
GS840E36B-150
Pipeline/Flow Through
BGA
150/10
C
128K x 36
GS840E36B-100
Pipeline/Flow Through
BGA
100/12
C
256K x 18
GS840E18B-180I
Pipeline/Flow Through
BGA
180/8
I
256K x 18
GS840E18B-166I
Pipeline/Flow Through
BGA
166/8.5
I
256K x 18
GS840E18B-150I
Pipeline/Flow Through
BGA
150/10
I
256K x 18
GS840E18B-100I
Pipeline/Flow Through
BGA
100/12
I
128K x 32
GS840E32B-180I
Pipeline/Flow Through
BGA
180/8
I
128K x 32
GS840E32B-166I
Pipeline/Flow Through
BGA
166/8.5
I
128K x 32
GS840E32B-150I
Pipeline/Flow Through
BGA
150/10
I
128K x 32
GS840E32B-100I
Pipeline/Flow Through
BGA
100/12
I
128K x 36
GS840E36B-180I
Pipeline/Flow Through
BGA
180/8
I
128K x 36
GS840E36B-166I
Pipeline/Flow Through
BGA
166/8.5
I
128K x 36
GS840E36B-150I
Pipeline/Flow Through
BGA
150/10
I
128K x 36
GS840E36B-100I
Pipeline/Flow Through
BGA
100/12
I
Status
Not Available
Not Available
Not Available
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840E32T-7.5T.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode.
Each device is Pipeline / Flow through mode selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Rev: 2.05 6/2000
30/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
GS840E18/32/36T/B-180/166/150/100
Revision History
Rev. Code: Old;
New
GS840E18/32/36 Rev 1.02c 5/
1999;
GS840E18/32/36 2.00 8/1999D
GS840E18/32/362.00 8/
1999;GS840E18/32/362.01 9/
1999E
Types of Changes
Format or Content
Format/Typos
Content
Format/Typos
Content
Page /Revisions;Reason
• Document/Continued changing to new format.
• Added Fine Pitch BGA Package.
•
• Took “E” out of 840HE...in Core and Interface Voltages.
• Pin outs/New small caps format.
• Timing Diagrams/New format.
• Block Diagrams/New small caps format.
• Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to DQB3.
• Pin Description/Rearranged Address Inputs to match order on TQFP Pinout.
• TQFP Package Diagram/Corrected Dimension D Max from 20.1 to 22.1.
•
GS840E18/32/362.01 9/
1999E;GS840E18/32/362.02
• Took out Fine Pitch BGA Package. Package change in progress.
GS840E18/32/362.0210-11/
1999;GS840E18/32/362.032/
2000G
Format
• New GSI Logo
• Took “Pin” out of heading for consistency.
GS840E18/32/362.032/2000G;
840E18_r2_04
Content
840E18_r2_04; 840E18_r2_05
Content
Rev: 2.05 6/2000
• Updated pin description table
• Updated BGA pin description table to meet JEDEC standard
31/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
© 1999, Giga Semiconductor, Inc.
.
Similar pages