GSI GS881E36T-66I 512k x 18, 256k x 36 bytesafe 8mb sync burst sram Datasheet

Preliminary
GS881E18/36T-11/11.5/100/80/66
100-Pin TQFP
Commercial Temp
Industrial Temp
MHz
512K x 18, 256K x 36 ByteSafe™ 100 MHz–66
3.3 V VDD
8Mb Sync Burst SRAMs
3.3 V and 2.5 V I/O
1.10 9/2000Features
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
• FT pin for user-configurable flow through or pipelined
operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 100-lead TQFP package
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
DCD Pipelined Reads
The GS881E18//36T is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
-11
-11.5
-100
-80
-66
10 ns
10 ns 12.5 ns 15 ns
Pipeline tCycle 10 ns
4.0 ns 4.0 ns 4.0 ns 4.5 ns 5.0 ns
3-1-1-1
tKQ
225
mA 225 mA 225 mA 200 mA 185 mA
IDD
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
11 ns 11.5 ns 12 ns
14 ns
18 ns
Flow
tKQ
15 ns
15 ns
15 ns
20 ns
Through tCycle 15 ns
2-1-1-1
IDD 180 mA 180 mA 180 mA 175 mA 165 mA
ByteSafe™ Parity Functions
Functional Description
The GS881E18/36T features ByteSafe data security functions.
See detailed discussion following.
Applications
Sleep Mode
The GS881E18//36T is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Low power (Sleep mode) is attained through the assertion
(high) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS881E18//36T operates on a 3.3 V power supply, and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
Rev: 1.10 9/2000
1/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Rev: 1.10 9/2000
2/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A18
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
QE
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
NC
VSS
VDDQ
NC
NC
NC
A16
LBO
A5
A4
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
FT
VDD
DP
VSS
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
NC
A1
A0
TMS
TDI
VSS
VDD
TDO
TCK
A10
A11
A12
A13
A14
A15
VDDQ
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K
X
18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A3
A2
NC
NC
NC
CK
GW
BW
G
ADSC
ADSP
ADV
A8
A9
A6
A7
E1
E2
NC
NC
BB
BA
A17
VDD
VSS
GS881E18 100-Pin TQFP Pinout
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Rev: 1.10 9/2000
3/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
QE
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
A16
LBO
A5
A4
VSS
DQ C6
DQ C5
DQ C4
DQ C3
VSS
VDDQ
DQ C2
DQ C1
FT
VDD
DP
VSS
DQ D1
DQ D2
VDDQ
VSS
DQ D3
DQ D4
DQ D5
DQ D6
VSS
VDDQ
DQ D7
DQ D8
DQ D9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K
x
36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A3
A2
A1
A0
TMS
TDI
VSS
VDD
TDO
TCK
A10
A11
A12
A13
A14
A15
DQ C9
DQ C8
DQ C7
VDDQ
CK
GW
BW
G
ADSC
ADSP
ADV
A8
A9
A6
A7
E1
E2
BD
BC
BB
BA
A17
VDD
VSS
GS881E36 100-Pin TQFP Pinout
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
TQFP Pin Descriptio
Pin Location
Symbol
Typ
e
Description
37, 36
A0, A1
I
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 92
A2–A17
I
Address Inputs
80
A18
I
Address Inputs
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
DQA1–DQ A8
DQB1–DQ B8
DQC1–DQ C8
DQD1–DQ D8
I/O
Data Input and Output pins ( x36 Version)
51, 80, 1, 30
DQA9, DQB9,
DQC9, DQ D9
I/O
Data Input and Output pins
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQA1–DQ A9
DQB1–DQ B9
I/O
Data Input and Output pins
51, 52, 53, 56, 57
75, 78, 79,
1, 2, 3, 6, 7
25, 28, 29, 30
NC
—
No Connect
16
DP
I
Parity Input; 1 = Even, 0 = Odd
66
QE
O
Parity Error Out; Open Drain Output
87
BW
I
Byte Write—Writes all enabled bytes; active low
93, 94
BA, BB
I
Byte Write Enable for DQA, DQB Data I/Os; active low
95, 96
BC, BD
I
Byte Write Enable for DQC, DQD Data I/Os; active low ( x36 Version)
95, 96
NC
—
No Connect (x18 Version)
89
CK
I
Clock Input Signal; active high
88
GW
I
Global Write Enable—Writes all bytes; active low
98
E1
I
Chip Enable; active low
97
E2
I
Chip Enable; active high
86
G
I
Output Enable; active low
83
ADV
I
Burst address counter advance enable; active low
84, 85
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
Rev: 1.10 9/2000
4/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Pin Location
Symbol
Typ
e
Description
64
ZZ
I
Sleep mode control; active high
14
FT
I
Flow Through or Pipeline mode; active low
31
LBO
I
Linear Burst Order mode; active low
38
TMS
I
Scan Test Mode Select
39
TDI
I
Scan Test Data In
42
TDO
O
Scan Test Data Out
43
TCK
I
Scan Test Clock
15, 41, 65, 91
VDD
I
Core power supply
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
VSS
I
I/O and Core Ground
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
I
Output driver power supply
Rev: 1.10 9/2000
5/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
GS881E18/36 Block Diagram
Register
A0–An
D
Q
A0
A0
D0
Q0
A1
A1
D1
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
36
36
Register
D
Q
BB
4
4
Register
D
Q
Q
Register
D
D
Q
Q
D
D
Register
Register
Q
Register
BC
BD
Register
D
36
Q
36
36
Register
E1
E2
D
Q
4
32
36
Parity
Encode
Register
D
Q
4
Parity
Compare
FT
G
ZZ
36
Power Down
0
DQx0–DQx9
QE
DP
Control
Note: Only x36 version shown for simplicity.
Rev: 1.10 9/2000
6/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
ByteSafe™ Parity Functions
This SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow
Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are
reported one clock cycle later. (See Write Parity Error Output Timing Diagram.) The Data Parity Mode (DP) pin must be tied
high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data.
Validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a
parity error. Multiple Parity Error Output pins may share a common pull-up resistor.
Write Parity Error Output Timing Diagram
Pipelined Mode
Flow Through Mode
CK
DQ
D In A
D In B
D In C
tKQ
tLZ
QE
DQ
D In D
tHZ
tKQX
Err A
D In A
D In E
Err C
D In B
D In C
tKQ
tLZ
QE
D In D
D In E
tHZ
tKQX
Err A
Err C
BPR 1999.05.18
Rev: 1.10 9/2000
7/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Mode Pin Functions
Mode Name
Pin Name
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
ByteSafe Data Parity Control
DP
State
Function
L
Linear Burst
H or NC
Interleaved Burst
L
Flow Through
H or NC
Pipeline
L or NC
Active
H
Standby, IDD = ISB
L
Check for Odd Parity
H or NC
Check for Even Parity
Note:
There are pull-up devices on the LBO, DP and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above table.
Burst Counter Sequences
Interleaved Burst Sequence
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
1st address
00
01
10
11
2nd address
01
10
11
00
2nd address
01
00
11
10
3rd address
10
11
00
01
3rd address
10
11
00
01
4th address
11
00
01
10
4th address
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.10 9/2000
8/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Byte Write Truth Table
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x36 version.
Rev: 1.10 9/2000
9/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Synchronous Truth Table
Operation
Address
Used
State
Diagram
Key5
E1
Deselect Cycle, Power Down
None
X
H
X
X
Deselect Cycle, Power Down
None
X
L
F
Deselect Cycle, Power Down
None
X
L
Read Cycle, Begin Burst
External
R
Read Cycle, Begin Burst
External
Write Cycle, Begin Burst
E22
ADV
W3
DQ4
L
X
X
High-Z
L
X
X
X
High-Z
F
H
L
X
X
High-Z
L
T
L
X
X
X
Q
R
L
T
H
L
X
F
Q
External
W
L
T
H
L
X
T
D
Read Cycle, Continue Burst
Next
CR
X
X
H
H
L
F
Q
Read Cycle, Continue Burst
Next
CR
H
X
X
H
L
F
Q
Write Cycle, Continue Burst
Next
CW
X
X
H
H
L
T
D
Write Cycle, Continue Burst
Next
CW
H
X
X
H
L
T
D
Read Cycle, Suspend Burst
Current
X
X
H
H
H
F
Q
Read Cycle, Suspend Burst
Current
H
X
X
H
H
F
Q
Write Cycle, Suspend Burst
Current
X
X
H
H
H
T
D
Write Cycle, Suspend Burst
Current
H
X
X
H
H
T
D
(x36only)
ADSP ADSC
Notes:
1. X = Don’t Care, H = High, L = Low.
2. For x36 Version, E = T (True) if E2 = 1; E = F (False) if E2 = 0.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5.
6.
7.
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.10 9/2000
10/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Simplified State Diagram
X
Deselect
W
R
Simple Burst Synchronous Operation
Simple Synchronous Operation
W
X
R
R
First Write
CW
First Read
CR
W
X
CR
R
R
X
Burst Write
Burst Read
X
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1 and E2) and Write (BA, BB, BC, BD, BW, and GW) control
inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.10 9/2000
11/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Simplified State Diagram with G
X
Deselect
W
R
W
X
R
R
First Write
CR
CW
W
CW
W
X
First Read
X
CR
R
Burst Write
R
CR
CW
W
Burst Read
X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.10 9/2000
12/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
–0.5 to VDD
V
VCK
Voltage on Clock Input Pin
–0.5 to 6
V
VI/O
Voltage on I/O Pins
–0.5 to VDDQ +0.5 (≤ 4.6 V max.)
V
VIN
Voltage on Other Input Pins
–0.5 to VDD +0.5 (≤ 4.6 V max.)
V
IIN
Input Current on Any Pin
+/–20
mA
IOUT
Output Current on Any I/O Pin
+/–20
mA
PD
Package Power Dissipation
1.5
W
TSTG
Storage Temperature
–55 to 125
oC
TBIAS
Temperature Under Bias
–55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Supply Voltage
VDD
3.135
3.3
3.6
V
I/O Supply Voltage
VDDQ
2.375
2.5
VDD
V
1
Input High Voltage
VIH
1.7
—
VDD +0.3
V
2
Input Low Voltage
VIL
–0.3
—
0.8
V
2
Ambient Temperature (Commercial Range Versions)
TA
0
25
70
°C
3
Ambient Temperature (Industrial Range Versions)
TA
–40
25
85
°C
3
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ VDDQ ≤ 2.375 V
(i.e., 2.5 V I/O) and 3.6 V ≤ VDDQ ≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC.
Rev: 1.10 9/2000
13/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
VSS
50%
50%
VDD
VSS – 2.0 V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
4
5
pF
Input/Output Capacitance
CI/O
VOUT = 0 V
6
7
pF
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Layer Board
Symbol
Max
Unit
Notes
Junction to Ambient (at 200 lfm)
single
RΘJA
40
°C/W
1,2
Junction to Ambient (at 200 lfm)
four
RΘJA
24
°C/W
1,2
Junction to Case (TOP)
—
RΘJC
9
°C/W
3
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.10 9/2000
14/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
AC Test Conditions
Parameter
Conditions
Input high level
2.3 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
1.25 V
Output reference level
1.25 V
Output load
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
Output Load 1
DQ
2.5 V
50Ω
30pF*
225Ω
DQ
5pF*
VT = 1.25 V
225Ω
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
ZZ Input Current
IINZZ
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
300 uA
Mode Pin Input Current
IINM
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–300 uA
–1 uA
1 uA
1 uA
Output Leakage Current
IOL
Output Disable,
VOUT = 0 to VDD
–1 uA
1 uA
Output High Voltage
VOH
IOH = –8 mA, VDDQ = 2.375 V
1.7 V
—
Output High Voltage
VOH
IOH = –8 mA, VDDQ = 3.135 V
2.4 V
—
Output Low Voltage
VOL
IOL = 8 mA
—
0.4 V
Rev: 1.10 9/2000
15/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Operating Currents
-11
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Unit
IDD
Pipeline
225
235
225
235
225
235
200
210
185
195
mA
IDD
Flow-Thru
180
190
180
190
180
190
175
185
165
175
mA
ISB
Pipeline
30
40
30
40
30
40
30
40
30
40
mA
ISB
Flow-Thru
30
40
30
40
30
40
30
40
30
40
mA
IDD
Pipeline
80
90
80
90
80
90
70
80
60
70
mA
IDD
Flow-Thru
65
75
65
75
65
75
55
65
50
60
mA
Operating
Current
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
Deselect
Current
Rev: 1.10 9/2000
-66
0
to
70°C
Symbol
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
-80
–40
to
85°C
Test Conditions
ZZ ≥ VDD - 0.2V
-100
0
to
70°C
Parameter
Standby
Current
-11.5
16/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
AC Electrical Characteristics
Pipeline
FlowThru
Parameter
Symbol
Clock Cycle Time
-11
-11.5
-100
-80
-66
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tKC
10
—
10
—
10
—
12.5
—
15
—
ns
Clock to Output Valid
tKQ
—
4.0
—
4.0
—
4.0
—
4.5
—
5
ns
Clock to Output Invalid
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
1
Clock to Output in Low-Z
tLZ
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock Cycle Time
tKC
15.0
—
15.0
—
15.0
—
15.0
—
20
—
ns
Clock to Output Valid
tKQ
—
11.0
—
11.5
—
12.0
—
14.0
—
18
ns
Clock to Output Invalid
tKQX
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock to Output in Low-Z
tLZ1
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock HIGH Time
tKH
1.7
—
1.7
—
2
—
2
—
2.3
—
ns
Clock LOW Time
tKL
2
—
2
—
2.2
—
2.2
—
2.5
—
ns
Clock to Output in High-Z
tHZ1
1.5
4.0
1.5
4.2
1.5
4.5
1.5
4.5
1.5
4.8
ns
G to Output Valid
tOE
—
4.0
—
4.2
—
4.5
—
4.5
—
4.8
ns
G to output in Low-Z
tOLZ1
0
—
0
—
0
—
0
—
0
—
ns
G to output in High-Z
tOHZ1
—
4.0
—
4.2
—
4.5
—
4.5
—
4.8
ns
Setup time
tS
1.5
—
2.0
—
2.0
—
2.0
—
2.0
—
ns
Hold time
tH
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
ZZ setup time
tZZS2
5
—
5
—
5
—
5
—
5
—
ns
ZZ hold time
tZZH2
1
—
1
—
1
—
1
—
1
—
ns
ZZ recovery
tZZR
20
—
20
—
20
—
20
—
20
—
ns
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.10 9/2000
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Write Cycle Timing
Single Write
Burst Write
Deselected
Write
CK
tS tH
tKH tKL
tKC
ADSP is blocked by E inactive
ADSP
tS tH
ADSC initiated write
ADSC
tS tH
ADV
tS tH
A0–An
ADV must be inactive for ADSP Write
WR2
WR1
WR3
tS tH
GW
tS
tH
BW
tS tH
BA–BD
WR1
WR1
WR2
tS tH
WR3
WR3
E1 masks ADSP
E1
tS tH
Deselected with E2
E2
E2 only sampled with ADSP or ADSC
G
tS tH
DQA–DQD
Rev: 1.10 9/2000
Hi-Z
D1A
Write specified byte for 2A and all bytes for 2B, 2C& 2D
D2A
D2B
D2C
D2D
18/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
D3A
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tKH
tS tH
tKC
ADSP is blocked by E inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
Suspend Burst
Suspend Burst
ADV
tS tH
A0–An
RD1
RD2
RD3
tS
tH
tS
tH
GW
BW
BA–BD
tS tH
E1 masks ADSP
E1
tS tH
E2 only sampled with ADSP or ADSC
Deselected with E 2
E2
tOE
tOHZ
G
tKQX
tOLZ
DQA–DQD
Q1A
Hi-Z
Q2A
tKQX
Q2B
Q2c
Q2D
Q3A
tLZ
tHZ
tKQ
Rev: 1.10 9/2000
19/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Flow Through Read-Write Cycle Timing
Single Write
Single Read
Burst Read
CK
tS tH
tKC
tKH tKL
ADSP is blocked by E inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0–An
RD1
WR1
tS
RD2
tH
GW
tH
tS
BW
tS tH
BA–BD
WR1
tS tH
E1 masks ADSP
E1
tS tH
E2 only sampled with ADSP and ADSC
E2
tOE
tOHZ
G
tS
tKQ
DQA–DQD
Hi-Z
Q1A
tH
D1A
Q2A
Q2B
Q2c
Q2D
Q2A
Burst wrap around to it’s initial state
Rev: 1.10 9/2000
20/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Pipelined DCD Read Cycle Timing
Single Read
tKL
Burst Read
CK
tS tH
tKH
tKC
ADSP is blocked by E1 inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
Suspend Burst
ADV
tS tH
A0–An
RD1
RD3
RD2
tS
tH
tS
tH
GW
BW
BA–BD
tS tH
E1 masks ADSP
E1
tS tH
E2 only sampled with ADSP or ADSC
E2
tOE
G
tOHZ
Hi-Z
tOLZ
Q1A
DQA–DQD
tKQX
Q2A
tKQX
Q2B
Q2c
Q2D
Q3A
tLZ
tHZ
tKQ
Rev: 1.10 9/2000
21/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Pipelined DCD Read-Write Cycle Timing
Single Write
Burst Read
Single Read
tKL
CK
tS tH
tKH
tKC
ADSP is blocked by E1 inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0–An
WR1
RD1
RD2
tS tH
GW
tS
tH
BW
tH
tS
BA–BD
WR1
tS tH
E1 masks ADSP
E1
tS
tH
E2 only sampled with ADSP and ADSC
E2
tOE
tOHZ
G
DQA–DQD
Rev: 1.10 9/2000
Hi-Z
tS tH
tKQ
Q1A
D1a
Q2A
22/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q2B
Q2c
Q2D
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
CK
tS tH
tKC
tKH tKL
ADSP
ADSC
tZZS
ZZ
~
~ ~ ~
~ ~
~~
~ ~
Sleep Mode Timing Diagram
tZZH
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings) but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface
standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some
functions have been modified or eliminated because they can slow the RAM. Nevertheless, the RAM supports 1149.1-1990 TAP
(Test Access Port) Controller architecture, and can be expected to function in a manner that does not conflict with the operation of
Standard 1149.1 compliant devices. The JTAG Port interfaces with conventional TTL / CMOS logic level signaling.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits. To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
Rev: 1.10 9/2000
23/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the
falling edge of TCK.
TMS
Test Mode
Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state
machine. An undriven TMS input will produce the same result as a logic one input level.
TDI
Test Data In
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed
between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP
Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to
the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input
level.
TDO
Test Data Out
Out
Output that is active depending on the state of the TAP state machine. Output changes in response to the
falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS
as TCK is strobed. Each of the TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and
push serial data out on the next falling edge of TCK. When a register is selected it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAMs JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The
flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. Two TAP
instructions can be used to activate the Boundary Scan Register.
Rev: 1.10 9/2000
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
JTAG TAP Block Diagram
0
Bypass Register
2 1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
·
· · ·
2 1 0
Boundary Scan Register
n
· · · · · ·
· · ·
2 1 0
TMS
Test Access Port (TAP) Controller
TCK
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Die
Revision
Code
I/O
Configuration
Not Used
GSI Technology
JEDEC Vendor
ID Code
Presence Register
ID Register Contents
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
1
10 9 8 7 6 5 4 3 2 1
1
0
x36
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0 0 1 1 0 1 1 0 0 1
1
x18
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0 0 1 1 0 1 1 0 0 1
1
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor
all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This
device will not perform EXTEST, INTEST or the SAMPLE/PRELOAD command.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
Rev: 1.10 9/2000
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© 2000, Giga Semiconductor, Inc.
Preliminary
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instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
1
0
Test Logic Reset
0
Run Test Idle
1
Select DR
1
Select IR
0
0
1
1
Capture DR
Capture IR
0
0
Shift DR
1
1
1
Shift IR
0
1
1
Exit1 DR
0
Exit1 IR
0
0
Pause DR
1
Exit2 DR
1
0
Pause IR
1
Exit2 IR
0
1
Update DR
Update IR
1
1
0
0
0
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm
the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O
ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the
TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the UpdateDR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This
functionality is not Standard 1149.1-compliant.
Rev: 1.10 9/2000
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© 2000, Giga Semiconductor, Inc.
Preliminary
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EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in
the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not 1149.1-compliant. Nevertheless, this RAM’s TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction register the RAM responds just as it does in response to the BYPASS instruction described above.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the
Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
This RAM does not implement 1149.1 EXTEST function. *Not 1149.1 Compliant *
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1 Compliant *
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
1
1, 2
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.10 9/2000
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol Min.
Max.
Unit Notes
Test Port Input High Voltage
VIHT
1.7
VDD +0.3
V
1, 2
Test Port Input Low Voltage
VILT
–0.3
0.8
V
1, 2
TMS, TCK and TDI Input Leakage Current
IINTH
–300
1
uA
3
TMS, TCK and TDI Input Leakage Current
IINTL
–1
1
uA
4
TDO Output Leakage Current
IOLT
–1
1
uA
5
Test Port Output High Voltage
VOHT
2.4
—
V
6, 7
Test Port Output Low Voltage
VOLT
—
0.4
V
6, 8
Notes:
1. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
2. Input Under/overshoot voltage must be –2 V > Vi < V DD +2 V with a pulse width not to exceed 20%
tTKC.
3. VDD ≥ VIN ≥ VIL
4. 0 V ≤ VIN ≤ VIL
5. Output Disable, VOUT = 0 to VDD
6. The TDO output driver is served by the VDD supply.
7. IOH = –4 mA
8. IOL = +4 mA
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
2.3 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
1.25 V
Output reference level
1.25 V
DQ
50Ω
30pF*
VT = 1.25 V
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
Rev: 1.10 9/2000
JTAG Port AC Test Load
28/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
JTAG Port Timing Diagram
tTKH
tTKL
tTKC
TCK
tTS
tTH
TMS
TDI
TDO
tTKQ
JTAG Port AC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tTKC
20
—
ns
TCK Low to TDO Valid
tTKQ
—
10
ns
TCK High Pulse Width
tTKH
10
—
ns
TCK Low Pulse Width
tTKL
10
—
ns
TDI & TMS Set Up Time
tTS
5
—
ns
TDI & TMS Hold Time
tTH
5
—
ns
Rev: 1.10 9/2000
29/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
GS811E18/36T TQFP Boundary Scan Register
Order
x36
x18
Pin
Order
x36
x18
Pin
Order
x36
x18
Pin
1
PH = 0
n/a
30
A9
81
59
FT
14
2
PH = 0
n/a
31
A8
82
60
DP
16
3
A10
44
32
ADV
83
61
PH = 0
n/a
4
A11
45
33
ADSP
84
62
DQD1
DQB5
18
5
A12
46
34
ADSC
85
63
DQD2
DQB6
19
6
A13
47
35
G
86
64
DQD3
DQB7
22
7
A14
48
36
BW
87
65
DQD4
DQB8
23
8
A15
49
37
GW
88
66
DQD5
DQB9
24
9
A16
50
38
CK
89
67
DQD6
NC = 1
25
10
x36 = DQA9
NC = 1
51
39
PH = 0
n/a
68
DQD7
NC = 1
28
11
DQA8
NC = 1
52
40
PH = 0
n/a
69
DQD8
NC = 1
29
12
DQA7
NC = 1
53
41
A17
92
70
x36 = DQD9
NC = 1
30
13
DQA6
NC = 1
56
42
BA
93
71
LBO
31
14
DQA5
NC = 1
57
43
BB
94
72
A5
32
15
DQA4
DQA1
58
44
BC
NC = 1
95
73
A4
33
16
DQA3
DQA2
59
45
BD
NC = 1
96
74
A3
34
17
DQA2
DQA3
62
46
E2
97
75
A2
35
18
DQA1
DQA4
63
47
E1
98
76
A1
36
19
ZZ
64
48
A7
99
77
A0
37
20
QE
66
49
A6
100
78
PH = 0
n/a
21
DQB1
DQA5
68
50
x36 = DQC9
NC = 1
1
22
DQB2
DQA6
69
51
DQC8
NC = 1
2
23
DQB3
DQA7
72
52
DQC7
NC = 1
3
24
DQB4
DQA8
73
53
DQC6
NC = 1
6
25
DQB5
DQA9
74
54
DQC5
NC = 1
7
26
DQB6
NC = 1
75
55
DQC4
DQB1
8
27
DQB7
NC = 1
78
56
DQC3
DQB2
9
28
DQB8
NC = 1
79
57
DQC2
DQB3
12
29
x36 = DQB9
A18
80
58
DQC1
DQB4
13
BPR 1999.08.11
Notes:
1. The Boundary Scan Register contains a number of registers that are not connected to any pin. They default to the value shown at reset.
2. Registers are listed in exit order (i.e. Location 1 is the first out of the TDO pin.
3. NC = No Connect, NA = Not Active, PH = Place Holder (No associated pin)
Rev: 1.10 9/2000
30/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Output Driver Characteristics
120.0
100.0
Pull Down Drivers
80.0
60.0
40.0
20.0
VDDQ
I Out (mA)
I Out
0.0
VOut
-20.0
VSS
-40.0
-60.0
Pull Up Drivers
-80.0
-100.0
-120.0
-140.0
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD HD
3.3V PD HD
3.1V PD HD
3.1V PU HD
3.3V PU HD
3.6V PU HD
BPR 1999.05.18
Rev: 1.10 9/2000
31/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
TQFP Package Drawing
L
Min. Nom. Max
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
—
0.20
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
—
0.65
—
L
Foot Length
0.45
0.60
0.75
L1
Lead Length
—
1.00
—
Y
Coplanarity
—
—
0.10
θ
Lead Angle
0°
—
7°
c
e
D
A1
L1
D1
Description
Pin 1
Symbol
θ
b
A1
A2
E1
Y
E
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
BPR 1999.05.18
Rev: 1.10 9/2000
32/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Ordering Information for GSI Synchronous Burst RAMs
Org
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
514K x 18
GS881E18T-11
ByteSafe DCD Pipeline/Flow Through
TQFP
100/11
C
514K x 18
GS881E18T-11.5
ByteSafe DCD Pipeline/Flow Through
TQFP
100/11.5
C
514K x 18
GS881E18T-100
ByteSafe DCD Pipeline/Flow Through
TQFP
100/12
C
514K x 18
GS881E18T-80
ByteSafe DCD Pipeline/Flow Through
TQFP
80/14
C
514K x 18
GS881E18T-66
ByteSafe DCD Pipeline/Flow Through
TQFP
66/18
C
256K x 36
GS881E36T-11
ByteSafe DCD Pipeline/Flow Through
TQFP
100/11
C
256K x 36
GS881E36T-11.5
ByteSafe DCD Pipeline/Flow Through
TQFP
100/11.5
C
256K x 36
GS881E36T-100
ByteSafe DCD Pipeline/Flow Through
TQFP
100/12
C
256K x 36
GS881E36T-80
ByteSafe DCD Pipeline/Flow Through
TQFP
80/14
C
256K x 36
GS881E36T-66
ByteSafe DCD Pipeline/Flow Through
TQFP
66/18
C
514K x 18
GS881E18T-11I
ByteSafe DCD Pipeline/Flow Through
TQFP
100/11
I
514K x 18
GS881E18T-11.5I
ByteSafe DCD Pipeline/Flow Through
TQFP
100/11.5
I
514K x 18
GS881E18T-100I
ByteSafe DCD Pipeline/Flow Through
TQFP
100/12
I
514K x 18
GS881E18T-80I
ByteSafe DCD Pipeline/Flow Through
TQFP
80/14
I
514K x 18
GS881E18T-66I
ByteSafe DCD Pipeline/Flow Through
TQFP
66/18
I
256K x 36
GS881E36T-11I
ByteSafe DCD Pipeline/Flow Through
TQFP
100/11
I
256K x 36
GS881E36T-11.5I
ByteSafe DCD Pipeline/Flow Through
TQFP
100/11.5
I
256K x 36
GS881E36T-100I
ByteSafe DCD Pipeline/Flow Through
TQFP
100/12
I
256K x 36
GS881E36T-80I
ByteSafe DCD Pipeline/Flow Through
TQFP
80/14
I
256K x 36
GS881E36T-66I
ByteSafe DCD Pipeline/Flow Through
TQFP
66/18
I
Status
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS881E18TT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.10 9/2000
33/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Format/Typos
• Last Page/Fixed “GSGS..” in Ordering Information Note.
• Fromatted Pin Outs and Pin Description to new small caps.
• Formatted Block diagrams to new small caps.
• Formatted Timing Diagrams to new small caps.
• Changed “Flow thru” to “Flow Through” in Timing Diagrams.
• Boundary Scan Register/Formatted to new small caps.
• Package Diagram/Changed “Dimesion” to “Dimension”.
Content
• 5/Fixed pin description table to match pinouts.
• Pin Description/Changed chip enables to match pins.
• Pin Description/Changed pin 80 from NC to Address Input.
• Pin Description/Rearranged Address Inputs to match order of
Pinout
• Changed I to O for TDO
• Package Diagram/Changed Dimension D Max from 20.1 to
22.1
•
GS881E18/36TRev1.04h 5/
1999;
1.05 9/1999I
GS881E18/36T1.05 9/
1999I;1.05 11/1999J
GS881E18/36T1.05 11/
1999K881E18/36T1.06 1/
200010L
GS881E18/36T1.06 1/
2000L;
GS881E18/36T1.07 3/
2000N;
GS881E18/36T1.07 3/
2000N;
GS881E18/36T1.08 3/
2000O;
Content
Content
Content
Content
881E GS881E18/36T1.08 3/
2000O;
881E183236_r1_09
Content/Format
881E18_r1_09;
881E18_r1_10
Content
Rev: 1.10 9/2000
Page;Revisions;Reason
• First Release of 880 F.
• Changed order of TQFP Address Inputs to match pinout.
• Changed order of TQFP DATA Input and Output pins to
match pinout.
• New GSI Logo.
• Changed all speed bin information (headings, references,
tables, ordering info..) to reflect 150 - 80Mhz
• Corrections to AC Electrical Characteristics Table • Fixed Boundary Scan Register Added Pin 29
• Removed 150 MHz speed bin
• Changed 133 MHz and 117 MHz speed bins to 11 ns and
11.5 ns (100 MHz) numbers
• Updated format to comply with Technical Publications
standards
• Updated Capitance table—removed Input row and changed
Output row to I/O
34/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
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