Gennum GS9000CCPJ Serial digital decoder Datasheet

GENLINX™ GS9000C
Serial Digital Decoder
DATA SHEET
DEVICE DESCRIPTION
•
fully compatible with SMPTE 259M
•
decodes 8 and 10 bit serial digital signals for data
rates to 370Mb/s
The GS9000C is a CMOS integrated circuit specifically
designed to deserialize SMPTE 259M serial digital signals
at data rates to 370Mb/s.
•
pin and function compatible with GS9000S, GS9000
and GS9000B
•
325mW power dissipation at 270MHz clock rates
•
incorporates an automatic standards selection
function with the GS9005A Receiver or GS9015A
Reclocker
•
operates from single +5 or -5 volt supply
•
enables an adjustment-free Deserializer system
when used with GS9010A and GS9005A or
GS9015A
•
28 pin PLCC packaging
The device incorporates a descrambler, serial to parallel
convertor, sync processing unit, sync warning unit and
automatic standards select circuitry.
Differential pseudo-ECL inputs for both serial clock and
data are internally level shifted to CMOS levels. Digital
outputs such as parallel data, parallel clock, HSYNC,
Sync Warning and Standard Select are all TTL compatible.
The GS9000C is designed to directly interface with the
GS9005A Reclocking Receiver to form a complete
SMPTE-serial-in to CMOS level parallel-out deserializer.
The GS9000C may also be used with the GS9010A and
the GS9005A to form an adjustment-free receiving system
which automatically adapts to all serial digital data rates.
The GS9015A can replace the GS9005A in GS9000C
applications where cable equalization is not required.
APPLICATIONS
•
4ƒSC, 4:2:2 and 360Mb/s serial digital interfaces
•
Automatic standards select controller for serial routing
and distribution applications using GS9005A Receiver or
GS9015A Reclocker
The GS9000C is packaged in a 28 pin PLCC and operates
from a single 5 volt, ± 5% power supply.
GS9000C
SERIAL DATA IN
SERIAL DATA IN
SERIAL CLOCK IN
5
6
LEVEL
SHIFT
DESCRAMBLER
30 - BIT
SHIFT REG
PARALLEL DATA
OUT (10 BITS)
7
8
SERIAL CLOCK IN
LEVEL
SHIFT
SYNC DETECT
(3FF 000 000 HEX)
SCLK
Sync
SYNC CORRECTION
ENABLE
SP
14
Word
Boundary
PARALLEL
TIMING
GENERATOR
PARALLEL CLOCK
OUT
SYNC CORRECTION
Sync Error
HSYNC OUTPUT
SYNC WARNING
(Schmitt Trigger
Comparator)
SYNC WARNING 15
CONTROL
SYNC WARNING
FLAG
AUTO STANDARD SELECT
STANDARDS SELECT 11
CONTROL
OSC
2 BIT
COUNTER
SS0
SS1
Hsync Reset
FUNCTIONAL BLOCK DIAGRAM
Revision Date: February 2000
Document No. 522 - 49 - 01
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
GS9000C
FEATURES
GS9000C DECODER - DC ELECTRICAL CHARACTERISTICS
V DD = 5V, TA = 0°C to 70°C unless otherwise shown
PARAMETER
SYMBOL
MIN
TYP
MAX
VS
Operating Range
4.75
5.00
5.25
V
1
PC
ƒ = 143MHz
-
235
-
mW
7
ƒ = 270MHz
-
325
-
mW
7
VIHM I N
ƒ = 360MHz
TA = 25° C
3.4
385
-
-
mW
V
1
1
VILM A X
VOHM I N
IO H = 4mA, 25° C
2.4
4.5
1.5
-
V
V
1
1
VOHM A X
II N
IO L = 4mA, 25° C
VIN = VD D or VS S
-
0.2
-
0.5
±10
V
µA
1
1
TA = 25° C
700
800
1000
mV p-p
1
TA = 25° C,
3.0
-
4.0
V
Supply Voltage
GS9000C
Power Consumption
(outputs unloaded)
CMOS Input Voltage
Output Voltage
Input Leakage Current
Serial Clock and Data Inputs
Signal Swing
VIN
Signal Offset
VIN O S
UNITS
VIN = 700 to 1000mVp-p
NOTES
TEST
LEVEL
CONDITIONS
Centre of
swing
1
GS9000C DECODER - AC ELECTRICAL CHARACTERISTICS
V DD = 5V, TA = 0°C to 70°C unless otherwise shown
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
TEST
LEVEL
NOTES
ƒS C I
100
370
MHz
1
DRS D I
100
370
Mb/s
1
Serial Input Clock Frequency
Serial Input Data Rate
CONDITIONS
TA = 25° C
Serial Data and Clock Inputs:
Risetime
tR
-
600
-
ps
7
Setup
tS U
1.0
-
-
ns
7
Hold
tH O LD
Parallel Clock: Jitter
tJ C L K
Parallel Data: Risetime and
Falltime
tR -P D n
PDn to PCLK Delay Tolerance
TA = 25° C
TA = 25° C,
1.0
-
-
ns
7
-
1.0
-
ns p-p
7
-
3
-
ns
20% to
80%
7
ns
Rising
edge of
PCLK to bit
period
centre
7
CL = 10pF
-
tD
-
±3
Test Level Legend
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
ABSOLUTE MAXIMUM RATINGS
8. Not tested. Based on existing design/characterization data
of similar product.
PARAMETER
VALUE
Supply Voltage (VS = VDD - VSS)
ORDERING INFORMATION
Input Voltage Range (any input)
PART NUMBER
PACKAGE
TEMPERATURE
GS9000CCPJ
28 Pin PLCC
0°C to 70°C
GS9000CCTJ
28 Pin PLCC Tape
0°C to 70°C
7V
-0.3 to (VDD + 0.3)V
DC Input Current (any one input)
Operating Temperature Range
Storage Temperature Range
522 - 49 - 01
Lead Temperature (Soldering, 10 seconds)
2
± 10µA
0°C to 70°C
-65°C to +150°C
260°C
VSS
4
(MSB)
SWF VSS HSYNC PD9
3
2
28
PD8
VSS
27
26
5
25
PD7
SDI
6
24
PD6
SCI
7
23
PD5
22
PD4
GS9000C
TOP VIEW
SCI
8
SS1
9
21
PD3
SS0
10
20
PD2
SSC
11
19
PD1
12
13
14
VDD
VDD
SCE
15
16
SWC PCLK
17
GS9000C
SDI
18
PD0 VDD
(LSB)
Fig. 1 GS9000C Pin Outs, 28 Pin PLCC Package
GS9000C PIN DESCRIPTIONS
PIN NO.
SYMBOL
TYPE
DESCRIPTION
1
HSYNC
Output
2
VSS
3
SWF
4
VSS
5,6
SDI/SDI
Inputs
Differential, pseudo-ECL serial data inputs. ECL voltage levels with offset of 3.0V to 4.0V
for operation up to 370MHz. See AC Electrical Characteristics Table for details.
7,8
SCI/SCI
Inputs
Differential, pseudo-ECL serial clock inputs. ECL voltage levels with offset of 3.0V to 4.0V
for operation up to 370MHz. See AC Electrical Characteristics Table for details.
9,10
SS1/SS0
Output
Standard Select Outputs. CMOS (TTL compatible) outputs used with the GS9005A Receiver in
order to perform an automatic standards select function. These outputs are generated by a 2
bit internal binary counter which stops cycling when there is no CARRIER present at the
GS9005A Receiver input or when a valid TRS is detected by the GS9000C.
11
SSC
Input
Standards Select Control. Analog input used to set a time constant for the standards select hunt
period. An external RC sets the time constant. When a GS9005A Receiver is used, the open
collector CARRIER DETECT output also connects to this pin in order to enable or disable the
internal 2 bit binary counter which controls the hunting process.
12
VDD
Power Supply. Most positive power supply connection.
13
VDD
Power Supply. Most positive power supply connection.
14
SCE
Horizontal Sync Output. CMOS (TTL compatible) output that toggles for each TRS detected.
Power Supply. Most negative power supply connection.
Output
Sync Error Warning Flag. CMOS (TTL compatible) active high output that indicates the
preselected HSYNC Error Rate (HER). The HER is set with an RC time constant on the
SWC input.
Power Supply. Most negative power supply connection.
Input
Sync Correction Enable. Active high CMOS input which enables sync correction by not resetting
the GS9000C’s internal parallel timing on the first sync error. If the next incoming sync is in error,
internal parallel timing will be reset. This is to guard against spurious HSYNC errors. When SCE
is low, a valid sync will always reset the GS9000C’s parallel timing generator.
3
522 - 49 - 01
GS9000C PIN DESCRIPTIONS
GS9000C
PIN NO.
SYMBOL
TYPE
DESCRIPTION
15
SWC
Input
Sync Warning Control. Analog input used to set the HSYNC Error Rate (HER). This is
accomplished by an external RC time constant connected to this pin.
16
PCLK
Output
Parallel Clock Output. CMOS (TTL compatible) clock output where the rising edge of the clock is
located at the centre of the parallel data window within a given tolerance. See Fig. 7.
17
PD0
Output
Parallel Data Output - Bit 0 (LSB). CMOS (TTL compatible) descrambled parallel data output from
the serial to parallel convertor representing the least significant bit (LSB).
18
VDD
19 - 25
PD1 - PD7
26
VSS
27
PD8
Output
Parallel Data Output. CMOS (TTL compatible) descrambled parallel data output from the serial to
parallel convertor representing data bit 8.
28
PD9
Output
Parallel Data Output - Bit 9 (MSB). CMOS (TTL compatible) descrambled data output from the serial
to parallel convertor representing the most significant bit (MSB).
Power Supply. Most positive power supply connection.
Outputs
Parallel Data Outputs - Bit 1 to Bit 7. CMOS (TTL compatible) descrambled parallel data outputs from
the serial to parallel convertor representing data bit 1 through data bit 7.
Power Supply. Most negative power supply connection.
INPUT / OUTPUT CIRCUITS
VDD
VDD
VDD
VDD
REXT
SSC
SCE
EXTERNAL
COMPONENTS
VDD
Fig. 2 Pin 11 SSC
Fig. 3 Pin 14 SCE
SDI
SCI
BIAS
VDD
SDI
SCI
Fig. 4 Pins 5 - 8 SDI - SCI
522 - 49 - 01
4
VDD
VDD
VDD
REXT
SWC
6k8
GS9000C
OUTPUT
CEXT
EXTERNAL
COMPONENTS
GND
Fig. 5 Pin 15 SWC
Fig. 6 Pins 3, 16, 17, 19 - 25, 27, 28
SWF, HSYNC, SSI, SSD, PCLK, PD0-9
1/
PARALLEL
DATA
(PDn)
50%
SERIAL
CLOCK
(SCI)
1/ T
2
2 T
tCLKL = tCLKH
PARALLEL
CLOCK
(PCLK)
SERIAL
DATA
(SDI)
tSU
tHOLD
50%
tD
Fig. 7 Waveforms
TEST SET-UP & APPLICATION INFORMATION
In order to maintain very short interconnections when
interfacing with the GS9005A Receiver, the critical high
speed inputs such as Serial Data (pins 5 and 6) and Serial
Clock (pins 7 and 8) are located along one side of the device
package.
Figure 8 shows the test set-up for the GS9000C operating
from a VDD supply of +5 volts. The differential pseudo ECL
inputs for DATA and CLOCK (pins 5,6,7 and 8) must be
biased between +3.0 and +4.0 volts. In the circuit shown,
these inputs with the resistor values shown, can be directly
driven from the outputs of the GS9005A Reclocking Receiver.
If the automatic standard select function is not used, the
Standard Select bits (pins 9 and 10) do not need to be
connected, however the control input (pin 11) should be
grounded.
In other cases, such as true ECL level driver outputs, two
biasing resistors are needed on the DATA and CLOCK inputs
and the signals must be AC coupled.
It is critical that the decoupling capacitors connected to pins
12,13 and 18 be chip types and be located as close as
possible to the device pins.
5
522 - 49 - 01
** Locate the three 0.10µF decoupling
capacitors as close as possible to the
corresponding pins on the GS9000C.
Chip capacitors are recommended.
+5V
22µ
3 x 100n
HSYNC OUTPUT
GS9000C
**
12
SDIIN
SDIIN
SCIIN
SCIIN
STANDARDS SELECT BIT 1
STANDARDS SELECT BIT 0
+5V
100k
820p
13 18
1
VDD VDD VDD HSYNC
17
PD0
DECODER
19
PDI
5 SDI
GS9000C
20
PD2
6 SDI
21
PD3
7 SCI
PD4 22
8 SCI
23
PD5
9 SS1
24
PD6
10 SS0
PD7 25
11 SSC
PD8 27
PARALLEL DATA BIT 0
PARALLEL DATA BIT 1
PARALLEL DATA BIT 2
PARALLEL DATA BIT 3
PARALLEL DATA BIT 4
PARALLEL DATA BIT 5
PARALLEL DATA BIT 6
PARALLEL DATA BIT 7
PARALLEL DATA BIT 8
PD9 28
PCLK
SCE
VSS VSS VSS SWC SWF
2
4
26
PARALLEL DATA BIT 9
16
PARALLEL CLOCK OUT
14
SYNC CORRECTION ENABLE
3
15
10p
SYNC WARNING FLAG
13 x 425Ω
39k
All resistors in ohms,
all capacitors in farads,
unless otherwise specified.
+5V
Fig. 8 GS9000C Test Set-Up
4ƒSC
DATA
STREAM
With correctly synchronized serial data and clock connected
to the GS9000C, the HSYNC output (pin 1) will toggle for each
HSYNC detected. The Parallel Data bits PD0 through PD9
along with the Parallel Clock can be observed on an
oscilloscope or fed to a logic analyzer. These outputs can
also be fed through a suitable TTL to ECL converter to directly
drive parallel inputs to receiving equipment such as monitors
or digital to analog converters.
T
R
S
ACTIVE VIDEO
& H BLANKING
E
A
V
H
BLNK
T
R
S
ACTIVE VIDEO
& H BLANKING
T
R
S
HSYNC
OUT
4:2:2
DATA
STREAM
In operation, the HSYNC output from the GS9000C decoder
toggles on each occurrence of the timing reference signal
(TRS). The state of the HSYNC output is not significant, just
the time at which it toggles.
S
A
V
ACTIVE
VIDEO
E
A
V
H
BLNK
S
A
V
HSYNC
OUT
Fig. 9 Operation of HSYNC Output
The HSYNC output toggles to indicate the presence of the
TRS on the falling edge of PCLK, one data symbol prior to the
output of the first word in the TRS. In the following diagram,
data is indicated in 10 bit Hex.
PCLK
PDN
XXX 3FF 000 000 XXX
XXX 3FF 000 000 XXX
HSYNC
Fig. 10 Operation of HSYNC with Respect to PCLK
522 - 49 - 01
6
SSI
0µ1
10µ
+
DVCC
+5V
VCC
+5V
SWF
VCC
100
100
3k3
0µ1
VCC
DGND
5
6
7
8
9
10
11
100
100
VCC
390
390
113
(2)
SDI
SDI
SCI
SCI
SS1
SS0
SSC
1 28 27 26
GS9000C
25
24
23
22
21
20
19
PD7
PD6
PD5
PD4
PD3
PD2
PD1
DVCC 12 13 14 15 16 17
VDD
390
100
100
3 2
VSS
SWF
VSS
HSYNC
PD9
PD8
VSS
25
SDO 24
SDO 23
SCO 22
SCO 21
SS1 20
SS0
19
CD
4
12 13 14 15 16 17 18 V
CC
5p6
22n(1)
GS9005A
DGND
390
1 28 27 26
PDO
75
5
VCC 6 DDI
DDI
0µ1
7
VCC2
47p
8 SDI
9 SDI
10 ƒ/2
47p
11 V
EE3
3 2
INPUT SELECTION
SYNC WARNING FLAG
HSYNC OUTPUT
PARALLEL DATA BIT 9
PARALLEL DATA BIT 8
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
100
100
100
100
100
100
100
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
DVCC
18
0µ1
0µ1
910
100 100
GS9000C
75
4
PCLK
DGND
ECL
DATA
INPUT
INPUT
100
0µ1
VCC1
VEE1
AGC
A/D
SSI
VEE2
VCC4
GND
DGND
VCC
0µ1
VDD
VDD
SCE
SWC
10µ
+
LOOP
RVCO0
RVCO1
RVCO2
EYEOUT
RVCO3
VCC3
10µ
+
DGND
10n
DGND
1k2
VCC
DVCC
1k2
(3)
0µ1
68k
50k
22n
VCC
120
STAR
ROUTED
DGND
GS9010A
6µ8
+
1
(2)
2
6µ8 +
3
4
3n3 5
6
7
VCC
8
16
STDT
P/N
VCC 15
OUT
CD 14
IN13
COMP HSYNC
GND 12
LF
OSC 11
ƒ/2
DLY 10
VCC
FVCAP 9
SWF
0.1µ
VCC
STANDARD TRUTH TABLE
100k
82n
0µ68
(2)
VCC
0µ1
SWF
180n
ƒ/2
P/N
0
0
4:2:2 - 270
STANDARD
0
1
4:2:2 - 360
1
0
4ƒsc - NTSC
1
1
4ƒsc - PAL
(1) Typical value for input return loss matching
(2) To reduce board space, the two anti-series 6.8µF capacitors (connected across pins 2 and 3 of the GS9010A)
may be replaced with a 1.0µF non-polarized capacitor provided that
(a) the 0.68µF capacitor connected to the OSC pin (11) of the GS9010A is replaced with a 0.33µF capacitor and
(b) the GS9005A /15A Loop Filter Capacitor is 10nF.
(3) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
Fig. 11 Application Circuit - Adjustment Free Multi-standard Serial to Parallel Convertor
GS9000C, GS9005A and GS9010A INTERCONNECTIONS
Figure 11 shows an application of the GS9000C in an
adjustment free, multi-standard serial to parallel convertor.
This circuit uses the GS9010A Automatic Tuning Sub-system
IC and a GS9005A Serial Digital Receiver. The GS9005A may
be replaced with a GS9015A Reclocker IC if cable equalization
is not required.
The GS9010A ATS eliminates the need to manually set or
externally temperature compensate the Receiver or Reclocker
VCO. The GS9010A can also determine whether the incoming
data stream is 4ƒsc NTSC,4ƒsc PAL or component 4:2:2.
The GS9010A includes a ramp generator/oscillator which
repeatedly sweeps the Receiver/Reclocker VCO frequency
over a set range until the system is correctly locked. An
automatic fine tuning (AFT) loop maintains the VCO control
voltage at its centre point through continuous, long term
adjustments of the VCO centre frequency.
During normal operation, the GS9000C Decoder provides
continuous HSYNC pulses which disable the ramp/oscillator
of the GS9010A. This maintains the correct Receiver/
Reclocker VCO frequency. When an interruption to the incoming
data stream is detected by the Receiver/Reclocker, the
Carrier Detect goes LOW and tri-states the AFT loop in order
to maintain the correct VCO frequency for a period of about
2 seconds. This allows the Receiver/Reclocker to rapidly
relock when the signal is re-established.
7
522 - 49 - 01
VDD
GS9000C
SYNC WARNING FLAG OPERATION
Each time HSYNC is not correctly detected, the Sync Warning
Flag output (pin 3 ) will go HIGH. The RC network connected
to the Sync Warning Control input (pin 15) sets the number
of sync errors that will cause the SWF pin to go HIGH. The
component values of the RC network shown in Figure 10 set
the SWF error rate to approximately one HSYNC error in 10
lines. These component values are chosen for optimum
performance of the SWF pin, and should not be adjusted.
COMPARATOR
15
VDD
SYNC
WARNING
CONTROL
6k8
3
+
SYNC
WARNING
FLAG
(SWF)
SYNC
ERROR
Typically, HSYNC errors will become visible on a monitor
before the SWF will provide an indication of HSYNC errors.
As a result, the SWF function can be used in applications
where the detection of significant signal degradation is
desired.
Fig. 10 Sync Warning Flag Circuit
A high SWF will go low as soon as the input error rate
decreases below the set rate. This response time is
determined by C, as mentioned earlier. A small amount of
hysteris in the comparator ensures noise immunity.
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
REVISION NOTES
DOCUMENT IDENTIFICATION:
Updated values in Electrical Characteristics tables and added test levels
with legend; Updated Figure 8 (Test Set-Up); Changed document from
preliminary data sheet to data sheet; Standardized artwork.
DATA SHEET
The product is in production. Gennum reserves the right to make changes
at any time to improve reliability, function or design, in order to provide
the best product possible.
For the latest product information, visit www.gennum.com.
GENNUM CORPORATION
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168-0081, Japan
Tel. +81 (3) 3334-7700 Fax: +81 (3) 3247-8839
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax +1 (905) 632-2814
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0) 1252 747000 Fax +44 (0) 1252 726523
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright August 1999 Gennum Corporation.
All rights reserved.
522 - 49 - 01
8
Printed in Canada.
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