Intel GT28F800B3B90 3 volt advanced boot block flash memory Datasheet

3 Volt Advanced Boot Block Flash
Memory
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Preliminary Datasheet
Product Features
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Flexible SmartVoltage Technology
— 2.7 V–3.6 V Read/Program/Erase
— 12 V VPP Fast Production Programming
2.7 V or 1.65 V I/O Option
— Reduces Overall System Power
High Performance
— 2.7 V–3.6 V: 70 ns Max Access Time
Optimized Block Sizes
— Eight 8-KB Blocks for Data,Top or
Bottom Locations
— Up to One Hundred Twenty-Seven 64KB Blocks for Code
Block Locking
— VCC-Level Control through WP#
Low Power Consumption
— 9 mA Typical Read Current
Absolute Hardware-Protection
— VPP = GND Option
— VCC Lockout Voltage
Extended Temperature Operation
— –40 °C to +85 °C
Automated Program and Block Erase
— Status Registers
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Intel® Flash Data Integrator Software
— Flash Memory Manager
— System Interrupt Manager
— Supports Parameter Storage, Streaming
Data (e.g., Voice)
Extended Cycling Capability
— Minimum 100,000 Block Erase Cycles
Guaranteed
Automatic Power Savings Feature
— Typical ICCS after Bus Inactivity
Standard Surface Mount Packaging
— 48-Ball CSP Packages
— 40- and 48-Lead TSOP Packages
Density and Footprint Upgradeable for
common package
— 4-, 8-, 16-, 32- and 64-Mbit Densities
ETOX™ VII (0.18 µ) Flash Technology
— 28F160/320/640B3xC
— 4-, 8-, 16-, and 32-Mbit also exist on
ETOX™ V (0.4µ) and/or ETOX ™ VI
(0.25µ) Flash Technology
x8 not recommended for new designs
4-Mbit density not recommended for new
designs
The 3 Volt Advanced Boot Block flash memory, manufactured on Intel’s latest 0.18 µm
technology, represents a feature-rich solution at overall lower system cost. The 3 Volt Advanced
Boot Block flash memory products in x16 will be available in 48-lead TSOP and 48-ball CSP
packages. The x8 option of this product family will only be available in 40-lead TSOP and 48ball µBGA* packages. Additional information on this product family can be obtained by
accessing Intel’s website at: http://www.intel.com/design/flash.
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 290580-012
October 2000
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products
are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation 1999– 2000.
*Other brands and names are the property of their respective owners.
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Contents
1.0
Introduction .................................................................................................................. 1
1.1
2.0
Product Description .................................................................................................. 3
2.1
2.2
3.0
3.2
3.3
3.4
3.5
3.6
3.7
Bus Operation ....................................................................................................... 7
3.1.1 Read......................................................................................................... 8
3.1.2 Output Disable.......................................................................................... 8
3.1.3 Standby .................................................................................................... 8
3.1.4 Deep Power-Down / Reset.......................................................................8
3.1.5 Write ......................................................................................................... 9
Modes of Operation............................................................................................... 9
3.2.1 Read Array ............................................................................................... 9
3.2.2 Read Identifier ........................................................................................11
3.2.3 Read Status Register .............................................................................11
3.2.4 Program Mode........................................................................................12
3.2.5 Erase Mode ............................................................................................12
Block Locking ......................................................................................................14
3.3.1 WP# = VIL for Block Locking ..................................................................14
3.3.2 WP# = VIH for Block Unlocking ..............................................................15
VPP Program and Erase Voltages .......................................................................15
3.4.1 VPP = VIL for Complete Protection .........................................................15
Power Consumption ............................................................................................15
3.5.1 Active Power ..........................................................................................16
3.5.2 Automatic Power Savings (APS)............................................................16
3.5.3 Standby Power .......................................................................................16
3.5.4 Deep Power-Down Mode .......................................................................16
Power-Up/Down Operation .................................................................................16
3.6.1 RP# Connected to System Reset...........................................................17
3.6.2 VCC, VPP and RP# Transitions ...............................................................17
Power Supply Decoupling ...................................................................................17
Electrical Specifications ........................................................................................18
4.1
4.2
4.3
4.4
4.5
4.6
4.7
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Package Pinouts ................................................................................................... 3
Block Organization ................................................................................................ 7
2.2.1 Parameter Blocks ..................................................................................... 7
2.2.2 Main Blocks .............................................................................................. 7
Principles of Operation ............................................................................................ 7
3.1
4.0
Product Overview .................................................................................................. 2
Absolute Maximum Ratings.................................................................................18
Operating Conditions...........................................................................................19
Capacitance ........................................................................................................19
DC Characteristics ..............................................................................................20
AC Characteristics —Read Operations...............................................................23
AC Characteristics —Write Operations ...............................................................27
Program and Erase Timings................................................................................31
iii
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
5.0
Reset Operations ..................................................................................................... 33
6.0
Ordering Information .............................................................................................. 34
7.0
Additional Information ........................................................................................... 36
Appendix A
Write State Machine Current/Next States ................................................. 37
Appendix B
Architecture Block Diagram ........................................................................... 38
Appendix C
Word-Wide Memory Map Diagrams............................................................. 39
Appendix D
Byte-Wide Memory Map Diagrams .............................................................. 45
Appendix E
Program and Erase Flowcharts .................................................................... 48
iv
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Revision History
Number
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Description
-001
Original version
-002
Section 3.4, VPP Program and Erase Voltages, added
Updated Figure 9: Automated Block Erase Flowchart
Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table)
Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)
IPPR maximum specification change from ±25 µA to ±50 µA
Program and Erase Suspend Latency specification change
Updated Appendix A: Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes)
Minor wording changes
-003
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V VPP read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
Moved Ordering Information from Appendix to Section 6.0; updated information
Moved Additional Information from Appendix to Section 7.0
Updated figure Appendix B, Access Time vs. Capacitive Load
Updated figure Appendix C, Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated Program Flowchart
Updated Program Suspend/Resume Flowchart
Minor text edits throughout
-004
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A1–A20 = 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1)
Combined IPPW and ICCW into one specification (Section 4.4)
Combined IPPE and ICCE into one specification (Section 4.4)
Max Parameter Block Erase Time (tWHQV2/tEHQV2) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (tWHQV3/tEHQV3) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (tWHRH2/tEHRH2) changed to 5 µs typical and 20 µs maximum
(Section 4.7)
Ordering Information updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
-005
µBGA package diagrams corrected (Figures 3 and 4)
IPPD test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
µBGA package top side mark information added (Section 6)
-006
VIH and VILSpecification change (Section 4.4)
ICCS test conditions clarification (Section 4.4)
Added Command Sequence Error Note (Table 7)
Datasheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text changes
-007
Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions
Corrected typographical error fixed in Ordering Information
v
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Number
vi
Description
-008
4-Mbit packaging and addressing information corrected throughout document
-009
Corrected 4-Mbit memory addressing tables in Appendices D and E
-010
Max ICCD changed to 25 µA
VCCMax on 32 M (28F320B3) changed to 3.3 V
-011
Added 64-Mbit density and faster speed offerings
Removed access time vs. capacitance load curve
-012
Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product
offering.
Changed VccMax=3.3V reference to indicate the affected product is the 0.25µm 32Mbit
device.
Minor text edits throughout document.
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1.0
Introduction
This datasheet contains the specifications for the 3 Volt Advanced Boot Block flash memory
family, which is optimized for low power, portable systems. This family of products features
1.65 V–2.5 V or 2.7 V–3.6 V I/Os and a low VCC/VPP operating range of 2.7 V–3.6 V for read,
program, and erase operations. In addition this family is capable of fast programming at 12 V.
Throughout this document, the term “2.7 V” refers to the full voltage range 2.7 V–3.6 V (except
where noted otherwise) and “VPP = 12 V” refers to 12 V ±5%. Section 1.0 and 2.0 provide an
overview of the flash memory family including applications, pinouts and pin descriptions. Section
3.0 describes the memory organization and operation for these products. Sections 4.0 and 5.0
contain the operating specifications. Finally, Sections 6.0 and 7.0 provide ordering and other
reference information.
The 3 Volt Advanced Boot Block flash memory features:
• Enhanced blocking for easy segmentation of code and data or additional design flexibility
• Program Suspend to Read command
• VCCQ input of 1.65 V–2.5 V on all I/Os. See Figures 1 through 4 for pinout diagrams and
VCCQ location
• Maximum program and erase time specification for improved data storage.
Table 1.
3 Volt Advanced Boot Block Feature Summary
Feature
28F004B3(2), 28F008B3,
28F016B3
VCC Read Voltage
VPP Program/Erase Voltage
1.65 V–2.5 V or 2.7 V– 3.6 V
Section 4.2, 4.4
2.7 V– 3.6 V or 11.4 V– 12.6 V
Section 4.2, 4.4
8 bit
Speed
16 bit
70 ns, 80 ns, 90 ns, 100 ns, 110 ns
Memory Arrangement
Blocking (top or bottom)
Locking
Reference
Section 4.2,
Section 4.4
2.7 V– 3.6 V
VCCQ I/O Voltage
Bus Width
28F400B3(2), 28F800B3,
28F160B3, 28F320B3(3),
28F640B3
512 Kbit x 8 (4 Mbit)
1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit)
256 Kbit x 16 (4 Mbit),
512 Kbit x 16 (8 Mbit),
1024 Kbit x 16 (16 Mbit),
2048 Kbit x 16 (32 Mbit),
4096 Kbit x 16 (64 Mbit)
Table 3
Section 4.5
Section 2.2
Eight 8-Kbyte parameter blocks and
Seven 64-Kbyte blocks (4 Mbit) or
Fifteen 64-Kbyte blocks (8 Mbit) or
Thirty-one 64-Kbyte main blocks (16 Mbit)
Sixty-three 64-Kbyte main blocks (32 Mbit)
One hundred twenty-seven 64-Kbyte main blocks (64 Mbit)
Section 2.2
Appendix C
WP# locks/unlocks parameter blocks
All other blocks protected using VPP
Section 3.3
Table 8
Operating Temperature
Extended: –40 °C to +85 °C
Section 4.2, 4.4
Program/Erase Cycling
100,000 cycles
Section 4.2, 4.4
(1)
Packages
40-lead TSOP ,
48-Ball µBGA* CSP(2)
48-Lead TSOP,
48-Ball µBGA CSP(2),
48-Ball VF BGA(4)
Figure 3, Figure 4
NOTES:
1. 32-Mbit and 64-Mbit densities not available in 40-lead TSOP.
2. 4-Mbit density not available in µBGA* CSP.
3. VCCMax is 3.3 V on 0.25µm 32-Mbit devices.
4. 4- and 64-Mbit densities not available on 48-Ball VF BGA.
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
1.1
Product Overview
Intel provides the most flexible voltage solution in the flash industry, providing three discrete
voltage supply pins: VCC for read operation, VCCQ for output swing, and VPP for program and
erase operation. All 3 Volt Advanced Boot Block flash memory products provide program/erase
capability at 2.7 V or 12 V (for fast production programming) and read with VCC at 2.7 V. Since
many designs read from the flash memory a large percentage of the time, 2.7 V VCC operation can
provide substantial power savings.
The 3 Volt Advanced Boot Block flash memory products are available in either x8 or x16 packages
in the following densities: (see Section 6.0, “Ordering Information” on page 34 for availability.)
• 4-Mbit (4,194,304-bit) flash memory organized as 256 Kwords of 16 bits each or 512 Kbytes
of 8-bits each
• 8-Mbit (8,388,608-bit) flash memory organized as 512 Kwords of 16 bits each or 1024 Kbytes
of 8-bits each
• 16-Mbit (16,777,216-bit) flash memory organized as 1024 Kwords of 16 bits each or
2048 Kbytes of 8-bits each
• 32-Mbit (33,554,432-bit) flash memory organized as 2048 Kwords of 16 bits each
• 64-Mbit (67,108,864-bit) flash memory organized as 4096 Kwords of 16 bits each
The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix)
of the address map in order to accommodate different microprocessor protocols for kernel code
location. The upper two (or lower two) parameter blocks can be locked to provide complete code
security for system initialization code. Locking and unlocking is controlled by WP# (see Section
3.3, “Block Locking” on page 14 for details).
The Command User Interface (CUI) serves as the interface between the microprocessor or
microcontroller and the internal operation of the flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and timings necessary for program and erase
operations, including verification, thereby un-burdening the microprocessor or microcontroller.
The status register indicates the status of the WSM by signifying block erase or word program
completion and status.
The 3 Volt Advanced Boot Block flash memory is also designed with an Automatic Power Savings
(APS) feature which minimizes system current drain, allowing for very low power designs. This
mode is entered following the completion of a read cycle (approximately 300 ns later).
The RP# pin provides additional protection against unwanted command writes that may occur
during system reset and power-up/down sequences due to invalid system bus conditions (see
Section 3.6, “Power-Up/Down Operation” on page 16).
Section 3.0, “Principles of Operation” on page 7 gives detailed explanation of the different modes
of operation. Complete current and voltage specifications can be found in Section 4.4, “DC
Characteristics” on page 20. Refer to Section 4.5, “AC Characteristics —Read Operations” on
page 23 for read, program and erase performance specifications.
2
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2.0
Product Description
This section explains device pin description and package pinouts.
2.1
Package Pinouts
The 3 Volt Advanced Boot Block flash memory is available in 40-lead TSOP (x8, Figure 1),
48-lead TSOP (x16, Figure 2) and 48-ball µBGA(x8 and x16, Figure 3 and Figure 4, respectively)
and 48-ball VF BGA (x16, Figure 4) packages. In all figures, pin changes necessary for density
upgrades have been circled.
Figure 1. 40-Lead TSOP Package for x8 Configurations
4M
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
VPP
WP#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Advanced Boot Block
40-Lead TSOP
10 mm x 20 mm
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCCQ
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
GND
CE#
A0
16 M
8M
0580_01
NOTES:
1. 40-Lead TSOP available for 8- and 16-Mbit densities only.
2. Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on
Pin 38.
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 2. 48-Lead TSOP Package for x16 Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RP#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
64 M
32 M
16 M
A16
VCCQ
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Advanced Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
0580_02
NOTE: Lower densities will have NC on the upper address pins. For example, an 16-Mbit device will have NC
on Pins 9 and 10.
Figure 3. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
1
2
3
4
5
6
7
8
A
A14
A12
A8
VPP
WP#
A20
A7
A4
B
A15
A10
WE#
RP#
A18
A5
A2
C
A16
A13
A9
A6
A3
A1
D
A17
NC
D5
NC
D2
NC
CE#
A0
E
VCCQ
A11
D6
NC
D3
NC
D0
GND
F
GND
D7
NC
D4
VCC
NC
D1
OE#
16M
8M
A19
0580_04
NOTES:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the
upper address solder balls. Routing is not recommended in this area. A20 is the upgrade address for the
16-Mbit device.
2. 4-Mbit density not available in µBGA* CSP.
4
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Figure 4. x16 48-Ball Very Thin Profile Pitch BGA and µBGA* Chip Size Package (Top View,
Ball Down)
1
2
3
4
5
6
7
8
A
A13
A11
A8
VPP
WP#
A19
A7
A4
B
A14
A10
WE#
RP#
A18
A17
A5
A2
16M
32M
64M
C
A15
A12
A9
A21
A20
A6
A3
A1
D
A16
D14
D5
D11
D2
D8
CE#
A0
E
VCCQ
D15
D6
D12
D3
D9
D0
GND
F
GND
D7
D13
D4
VCC
D10
D1
OE#
0580_03
NOTES:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the
upper address solder balls. Routing is not recommended in this area. A19 is the upgrade address for the
16-Mbit device. A20 is the upgrade address for the 32-Mbit device. A21 is the upgrade address for the 64-Mbit
device.
2. 4-Mbit density not available in µBGA CSP.
Table 2, “3 Volt Advanced Boot Block Pin Descriptions” on page 6 details the usage of each device
pin.
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 2.
Symbol
A0–A21
3 Volt Advanced Boot Block Pin Descriptions
Type
INPUT
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or
erase cycle.
28F004B3: A[0-18], 28F008B3: A[0-19], 28F016B3: A[0-20],
28F400B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19],
28F320B3: A[0-20], 28F640B3: A[0-21]
DQ0–DQ7
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program
command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, identifier and status register data. The data pins float to tri-state when
the chip is de-selected or the outputs are disabled.
DQ8–
DQ15
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program
command. Data is internally latched. Outputs array and identifier data. The data pins float to tri-state
when the chip is de-selected. Not included on x8 products.
CE#
INPUT
CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE#
is active low. CE# high de-selects the memory device and reduces power consumption to standby
levels.
OE#
INPUT
OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a read operation.
OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low.
Addresses and data are latched on the rising edge of the second WE# pulse.
RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep power-down
mode.
RP#
INPUT
When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs
to High-Z, resets the Write State Machine, and minimizes current levels (ICCD).
When RP# is at logic high, the device is in standard operation. When RP# transitions from logiclow to logic-high, the device defaults to the read array mode.
WRITE PROTECT: Provides a method for locking and unlocking the two lockable parameter blocks.
WP#
INPUT
When WP# is at logic low, the lockable blocks are locked, preventing program and erase
operations to those blocks. If a program or erase operation is attempted on a locked block, SR.1 and
either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased.
See Section 3.3 for details on write protection.
VCCQ
INPUT
OUTPUT VCC: Enables all outputs to be driven to 1.8 V – 2.5 V while the VCC is at 2.7 V–3.3 V. If the
VCC is regulated to 2.7 V–2.85 V, VCCQ can be driven at 1.65 V–2.5 V to achieve lowest power
operation (see Section 4.4).
This input may be tied directly to VCC (2.7 V–3.6 V).
VCC
VPP
DEVICE POWER SUPPLY: 2.7 V–3.6 V
PROGRAM/ERASE POWER SUPPLY: Supplies power for program and erase operations. VPP may
be the same as VCC (2.7 V–3.6 V) for single supply voltage operation. For fast programming at
manufacturing, 11.4 V–12.6 V may be supplied to VPP. This pin cannot be left floating. Applying
11.4 V–12.6 V to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500
cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum (see
Section 3.4 for details).
VPP < VPPLK protects memory contents against inadvertent or unintended program and erase
commands.
GND
GROUND: For all internal circuitry. All ground inputs must be connected.
NC
NO CONNECT: Pin may be driven or left floating.
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2.2
Block Organization
The 3 Volt Advanced Boot Block is an asymmetrically-blocked architecture that enables system
integration of code and data within a single flash device. Each block can be erased independently
of the others up to 100,000 times. For the address locations of each block, see the memory maps in
Appendix C.
2.2.1
Parameter Blocks
The 3 Volt Advanced Boot Block flash memory architecture includes parameter blocks to facilitate
storage of frequently updated small parameters (e.g., data that would normally be stored in an
EEPROM). By using software techniques, the word-rewrite functionality of EEPROMs can be
emulated. Each device contains eight parameter blocks of 8-Kbytes/4-Kwords (8192 bytes/4,096
words) each.
2.2.2
Main Blocks
After the parameter blocks, the remainder of the array is divided into equal size main blocks
(65,536 bytes/32,768 words) for data or code storage. The 4-Mbit device contains seven main
blocks; 8-Mbit device contains fifteen main blocks; 16-Mbit flash has thirty-one main blocks;
32-Mbit has sixty-three main blocks; 64-Mbit has one hundred twenty-seven main blocks.
3.0
Principles of Operation
Flash memory combines EEPROM functionality with in-circuit electrical program and erase
capability. The 3 Volt Advanced Boot Block flash memory family utilizes a Command User
Interface (CUI) and automated algorithms to simplify program and erase operations. The CUI
allows for 100% CMOS-level control inputs and fixed power supplies during erasure and
programming.
When VPP < VPPLK, the device will only execute the following commands successfully: Read
Array, Read Status Register, Clear Status Register and Read Identifier. The device provides
standard EEPROM read, standby and output disable operations. Manufacturer identification and
device identification data can be accessed through the CUI. All functions associated with altering
memory contents, namely program and erase, are accessible via the CUI. The internal Write State
Machine (WSM) completely automates program and erase operations while the CUI signals the
start of an operation and the status register reports status. The CUI handles the WE# interface to the
data and address latches, as well as system status requests during WSM operation.
3.1
Bus Operation
3 Volt Advanced Boot Block flash memory devices read, program and erase in-system via the local
CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash component:
CE#, OE#, WE# and RP#. These bus operations are summarized in Table 3.
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Table 3.
Bus Operations(1)
Mode
Read (Array, Status, or Identifier)
Note
RP#
CE#
OE#
WE#
DQ0–7
DQ8–15
2–4
VIH
VIL
VIL
VIH
DOUT
DOUT
Output Disable
2
VIH
VIL
VIH
VIH
High Z
High Z
Standby
2
VIH
VIH
X
X
High Z
High Z
Reset
2, 7
VIL
X
X
X
High Z
High Z
Write
2, 5–7
VIH
VIL
VIH
VIL
DIN
DIN
NOTES:
1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15].
2. X must be VIL, VIH for control pins and addresses.
3. See DC Characteristics for VPPLK, VPP1, VPP2, VPP3, VPP4 voltages.
4. Manufacturer and device codes may also be accessed in read identifier mode (A1–A21 = 0). See Table 5.
5. Refer to Table 6 for valid DIN during a write operation.
6. To program or erase the lockable blocks, hold WP# at VIH.
7. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.
3.1.1
Read
The flash memory has four read modes available: read array, read identifier, read status and read
query. These modes are accessible independent of the V PP voltage. The appropriate Read Mode
command must be issued to the CUI to enter the corresponding mode. Upon initial device powerup or after exit from reset, the device automatically defaults to read array mode.
CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection
control; when active it enables the flash memory device. OE# is the data output control and it
drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at
VIH. Figure 7 illustrates a read cycle.
3.1.2
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins are placed in a
high-impedance state.
3.1.3
Standby
Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during program or erase operation, the device continues to consume active power until
the program or erase operation is complete.
3.1.4
Deep Power-Down / Reset
From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a highimpedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required
until the initial read access outputs are valid. A delay (tPHWL or tPHEL) is required after return from
reset before a write can be initiated. After this wake-up interval, normal operation is restored. The
CUI resets to read array mode, and the status register is set to 80H. This case is shown in
Figure 9A.
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If RP# is taken low for time tPLPH during a program or erase operation, the operation will be
aborted and the memory contents at the aborted location (for a program) or block (for an erase) are
no longer valid, since the data may be partially erased or written. The abort process goes through
the following sequence: When RP# goes low, the device shuts down the operation in progress, a
process which takes time tPLRH to complete. After this time tPLRH, the part will either reset to read
array mode (if RP# has gone high during tPLRH, Figure 9B) or enter reset mode (if RP# is still logic
low after tPLRH, Figure 9C). In both cases, after returning from an aborted operation, the relevant
time tPHQV or tPHWL/tPHEL must be waited before a read or write operation is initiated, as
discussed in the previous paragraph. However, in this case, these delays are referenced to the end
of tPLRH rather than when RP# goes high.
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, processor expects to read from the flash memory. Automated flash memories
provide status information when read during program or block erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU initialization may not occur because the flash
memory may be providing status information instead of array data. Intel® Flash memories allow
proper CPU initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.1.5
Write
A write takes place when both CE# and WE# are low and OE# is high. Commands are written to
the Command User Interface (CUI) using standard microprocessor write timings to control flash
operations. The CUI does not occupy an addressable memory location. The address and data buses
are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. Figure 8
illustrates a program and erase operation. The available commands are shown in Table 6, and
Appendix A provides detailed information on moving between the different modes of operation
using CUI commands.
There are two commands that modify array data: Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User Interface (CUI) initiates a sequence of internallytimed functions that culminate in the completion of the requested task (unless that operation is
aborted by either RP# being driven to VIL for tPLRH or an appropriate suspend command).
3.2
Modes of Operation
The flash memory has four read modes and two write modes. The read modes are read array, read
identifier, read status and read query (see Appendix B). The write modes are program and block
erase. Three additional modes (erase suspend to program, erase suspend to read and program
suspend to read) are available only during suspended operations. These modes are reached using
the commands summarized in Table 4. A comprehensive chart showing the state transitions is in
Appendix A.
3.2.1
Read Array
When RP# transitions from VIL (reset) to VIH, the device defaults to read array mode and will
respond to the read control inputs (CE#, address inputs, and OE#) without any additional CUI
commands.
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When the device is in read array mode, four control signals control data output:
•
•
•
•
WE# must be logic high (VIH)
CE# must be logic low (VIL)
OE# must be logic low (VIL)
RP# must be logic high (VIH)
In addition, the address of the desired location must be applied to the address pins. If the device is
not in read array mode, as would be the case after a program or erase operation, the Read Array
command (FFH) must be written to the CUI before array reads can take place.
Table 4.
Command Codes and Descriptions
Code
Device Mode
00, 01,
60, 2F,
C0, 98
Invalid/
Reserved
Unassigned commands that should not be used. Intel reserves the right to redefine these
codes for future functions.
FF
Read Array
Places the device in read array mode, such that array data will be output on the data pins.
40
Program Set-Up
This is a two-cycle command. The first cycle prepares the CUI for a program operation. The
second cycle latches addresses and data information and initiates the WSM to execute the
Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read
Array command is required after programming to read array data. See Section 3.2.4.
10
Alternate
Program Set-Up
(See 40H/Program Set-Up)
20
Erase Set-Up
Erase Confirm
D0
Description
Prepares the CUI for the Erase Confirm command. If the next command is not an Erase
Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,”
(b) place the device into the read status register mode, and (c) wait for another command. See
Section 3.2.5.
If the previous command was an Erase Set-Up command, then the CUI will close the address
and data latches, and begin erasing the block indicated on the address pins. During erase, the
device will only respond to the Read Status Register and Erase Suspend commands. The
device will output status register data when CE# or OE# is toggled.
Program / Erase
Resume
If a program or erase operation was previously suspended, this command will resume that
operation
B0
Program / Erase
Suspend
Issuing this command will begin to suspend the currently executing program/erase operation.
The status register will indicate when the operation has been successfully suspended by
setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM status bit
(SR.7) to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the
state of all input control pins except RP#, which will immediately shut down the WSM and the
remainder of the chip if it is driven to VIL. See Section 3.2.4.1 and Section 3.2.4.1.
70
Read Status
Register
This command places the device into read status register mode. Reading the device will output
the contents of the status register, regardless of the address presented to the device. The
device automatically enters this mode after a program or erase operation has been initiated.
See Section 3.2.3.
50
Clear Status
Register
The WSM can set the block lock status (SR.1) , VPP status (SR.3), program status (SR.4), and
erase status (SR.5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this
command clears those bits to “0.”
90
Read Identifier
Puts the device into the intelligent identifier read mode, so that reading the device will output
the manufacturer and device codes (A0 = 0 for manufacturer, A0 = 1 for device, all other
address inputs must be 0). See Section Section 3.2.2.
NOTE: See Appendix A for mode transition information.
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3.2.2
Read Identifier
To read the manufacturer and device codes, the device must be in read identifier mode, which can
be reached by writing the Read Identifier command (90H). Once in read identifier mode, A0 = 0
outputs the manufacturer’s identification code and A0 = 1 outputs the device identifier (see
Table 5) Note: A1–A21 = 0. To return to read array mode, write the Read Array command (FFH).
Table 5.
Read Identifier Table
Device Identifier
Size
Mfr. ID
-T
(Top Boot)
-B
(Bottom Boot)
D4H
D5H
28F400B3
8894H
8895H
28F008B3
D2H
D3H
28F004B3
0089H
28F800B3
8892H
8893H
28F016B3
D0H
D1H
28F160B3
8890H
8891H
8896H
8897H
8898H
8899H
28F320B3
28F640B3
3.2.3
0089H
0089H
Read Status Register
The device status register indicates when a program or erase operation is complete and the success
or failure of that operation. To read the status register issue the Read Status Register (70H)
command to the CUI. This causes all subsequent read operations to output data from the status
register until another command is written to the CUI. To return to reading from the array, issue the
Read Array (FFH) command.
The status register bits are output on DQ0–DQ7. The upper byte, DQ8–DQ15, outputs 00H during a
Read Status Register command.
The contents of the status register are latched on the falling edge of OE# or CE#. This prevents
possible bus errors which might occur if status register contents change while being read. CE# or
OE# must be toggled with each subsequent status read, or the status register will not indicate
completion of a program or erase operation.
When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status
register indicate whether or not the WSM was successful in performing the desired operation (see
Table 7 on page 14).
3.2.3.1
Clearing the Status Register
The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear
status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and 5 indicate various error conditions, these
bits can only be cleared through the Clear Status Register (50H) command. By allowing the system
software to control the resetting of these bits, several operations may be performed (such as
cumulatively programming several addresses or erasing multiple blocks in sequence) before
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reading the status register to determine if an error occurred during that series. Clear the status
register before beginning another command or sequence. Note, again, that the Read Array
command must be issued before data can be read from the memory array.
3.2.4
Program Mode
Programming is executed using a two-write sequence. The Program Setup command (40H) is
written to the CUI followed by a second write which specifies the address and data to be
programmed. The WSM will execute a sequence of internally timed events to program desired bits
of the addressed location, then verify the bits are sufficiently programmed. Programming the
memory results in specific bits within an address location being changed to a “0.” If the user
attempts to program “1”s, the memory cell contents do not change and no error occurs.
The status register indicates programming status: while the program sequence executes, status bit 7
is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the
only valid commands are Read Status Register, Program Suspend, and Program Resume.
When programming is complete, the Program Status bits should be checked. If the programming
operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If
SR.3 is set then VPP was not within acceptable limits, and the WSM did not execute the program
command. If SR.1 is set, a program operation was attempted on a locked block and the operation
was aborted.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, to prevent inadvertent status register reads, be
sure to reset the CUI to read array mode.
3.2.4.1
Suspending and Resuming Program
The Program Suspend halts the in-progress program operation to read data from another location of
memory. Once the programming process starts, writing the Program Suspend command to the CUI
requests that the WSM suspend the program sequence (at predetermined points in the program
algorithm). The device continues to output status register data after the Program Suspend command
is written. Polling status register bits SR.7 and SR.2 will determine when the program operation
has been suspended (both will be set to “1”). tWHRH1/tEHRH1 specify the program suspend latency.
A Read Array command can now be written to the CUI to read data from blocks other than that
which is suspended. The only other valid commands while program is suspended, are Read Status
Register, Read Identifier, and Program Resume. After the Program Resume command is written to
the flash memory, the WSM will continue with the program process and status register bits SR.2
and SR.7 will automatically be cleared. After the Program Resume command is written, the device
automatically outputs status register data when read (see Appendix E for Program Suspend and
Resume Flowchart). VPP must remain at the same VPP level used for program while in program
suspend mode. RP# must also remain at VIH.
3.2.5
Erase Mode
To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an
address identifying the block to be erased. This address is latched internally when the Erase
Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only
one block can be erased at a time. The WSM will execute a sequence of internally-timed events to
program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all
bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”
12
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When the status register indicates that erasure is complete, check the erase status bit to verify that
the erase operation was successful. If the erase operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase failure. If VPP was not within acceptable limits after
the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead,
SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to identify that
VPP supply voltage was not within acceptable limits.
After an erase operation, clear the status register (50H) before attempting the next operation. Any
CUI instruction can follow after erasure is completed; however, to prevent inadvertent status
register reads, it is advisable to place the flash in read array mode after the erase is complete.
3.2.5.1
Suspending and Resuming Erase
Since an erase operation requires on the order of seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in order to read data from or program data to
another block in memory. Once the erase sequence is started, writing the Erase Suspend command
to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase
algorithm. The status register will indicate if/when the erase operation has been suspended.
A Read Array/Program command can now be written to the CUI in order to read data from/
program data to blocks other than the one currently suspended. The Program command can
subsequently be suspended to read yet another array location. The only valid commands while
erase is suspended are Erase Resume, Program, Read Array, Read Status Register, or Read
Identifier. During erase suspend mode, the chip can be placed in a pseudo-standby mode by taking
CE# to VIH. This reduces active current consumption.
Erase Resume continues the erase sequence when CE# = VIL. As with the end of a standard erase
operation, the status register must be read and cleared before the next instruction is issued.
Table 6.
Command Bus Definitions (1,4)
First Bus Cycle
Command
Notes
Read Array
Read Identifier
Oper
Addr
Data
Write
X
FFH
Oper
Addr
Data
Write
X
90H
Read
IA
ID
Read Status Register
Write
X
70H
Read
X
SRD
Clear Status Register
Write
X
50H
Write
X
40H /
10H
Write
PA
PD
Block Erase/Confirm
Write
X
20H
Write
BA
D0H
Program/Erase Suspend
Write
X
B0H
Program/Erase Resume
Write
X
D0H
Program
2
Second Bus Cycle
3
NOTES:
PA: Program Address
PD: Program Data
BA: Block Address
IA: Identifier Address
ID: Identifier Data
SRD: Status Register Data
1. Bus operations are defined in Table 3.
2. Following the Intelligent Identifier command, two read operations access manufacturer and device codes.
A 0 = 0 for manufacturer code, A0 = 1 for device code. A1–A21 = 0.
3. Either 40H or 10H command is valid although the standard is 40H.
4. When writing commands to the device, the upper data bus [DQ 8–DQ15] should be either VIL or VIH, to
minimize current draw.
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Table 7.
Status Register Bit Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check Write State Machine bit first to determine word program
or block erase completion, before checking program or erase
status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When erase suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set at “1” until
an Erase Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the max. number
of erase pulses to the block and is still unable to verify
successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Word Program
0 = Successful Word Program
When this bit is set to “1,” WSM has attempted but failed to
program a word.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous indication of
VPP level. The WSM interrogates VPP level only after the
Program or Erase command sequences have been entered,
and informs the system if VPP has not been switched on. The
VPP is also checked before the operation is verified by the
WSM. The VPP status bit is not guaranteed to report accurate
feedback between VPPLK max and VPP1 min or between VPP1
max and VPP4 min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When program suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”
until a Program Resume command is issued.
SR.1 = BLOCK LOCK STATUS
1 = Program/Erase attempted on locked block;
Operation aborted
0 = No operation to locked blocks
If a program or erase operation is attempted to one of the
locked blocks, this bit is set by the WSM. The operation
specified is aborted and the device is returned to read status
mode.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
This bit is reserved for future use and should be masked out
when polling the status register.
NOTE: A Command Sequence Error is indicated when both SR.4, SR.5 and SR.7 are set.
3.3
Block Locking
The 3 Volt Advanced Boot Block flash memory architecture features two hardware-lockable
parameter blocks.
3.3.1
WP# = VIL for Block Locking
The lockable blocks are locked when WP# = VIL; any program or erase operation to a locked block
will result in an error, which will be reflected in the status register. For top configuration, the top
two parameter blocks (blocks #133 and #134 for the 64 Mbit, #69 and #70 for the 32 Mbit, blocks
#37 and #38 for the 16 Mbit, blocks #21 and #22 for the 8 Mbit, blocks #13 and #14 for the 4 Mbit)
are lockable. For the bottom configuration, the bottom two parameter blocks (blocks #0 and #1 for
4 /8 /16 /32/64 Mbit) are lockable. Unlocked blocks can be programmed or erased normally (unless
VPP is below VPPLK).
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3.3.2
WP# = VIH for Block Unlocking
WP# = VIH unlocks all lockable blocks.
These blocks can now be programmed or erased.
Note that RP# does not override WP# locking as in previous Boot Block devices. WP# controls all
block locking and VPP provides protection against spurious writes. Table 8 defines the write
protection methods.
Table 8.
3.4
Write Protection Truth Table for the Advanced Boot Block Flash Memory Family
VPP
WP#
RP#
Write Protection Provided
X
X
VIL
All Blocks Locked
VIL
X
VIH
All Blocks Locked
≥ VPPLK
VIL
VIH
Lockable Blocks Locked
≥ VPPLK
VIH
VIH
All Blocks Unlocked
VPP Program and Erase Voltages
Intel® 3 Volt Advanced Boot Block products provide in-system programming and erase at 2.7 V.
For customers requiring fast programming in their manufacturing environment, 3 Volt Advanced
Boot Block includes an additional low-cost 12 V programming feature.
The 12 V VPP mode enhances programming performance during the short period of time typically
found in manufacturing processes; however, it is not intended for extended use. 12 V may be
applied to VPP during program and erase operations for a maximum of 1000 cycles on the main
blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80
hours maximum.
Warning:
Stressing the device beyond these limits may cause permanent damage.
During read operations or idle times, VPP may be tied to a 5 V supply. For program and erase
operations, a 5 V supply is not permitted. The VPP must be supplied with either 2.7 V–3.6 V or
11.4 V–12.6 V during program and erase operations.
3.4.1
VPP = VIL for Complete Protection
The VPP programming voltage can be held low for complete write protection of all blocks in the
flash device. When VPP is below VPPLK, any program or erase operation will result in a error,
prompting the corresponding status register bit (SR.3) to be set.
3.5
Power Consumption
Intel Flash devices have a tiered approach to power savings that can significantly reduce overall
system power consumption. The Automatic Power Savings (APS) feature reduces power
consumption when the device is selected but idle. If the CE# is deasserted, the flash enters its
standby mode, where current consumption is even lower. The combination of these features can
minimize memory power consumption, and therefore, overall system power consumption.
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3.5.1
Active Power
With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer
to the DC Characteristic tables for ICC current values. Active power is the largest contributor to
overall system power consumption. Minimizing the active current could have a profound effect on
system power consumption, especially for battery-operated devices.
3.5.2
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is read from
the memory array and the address lines are quiescent, APS circuitry places the device in a mode
where typical current is comparable to ICCS. The flash stays in this static state with outputs valid
until a new location is read.
3.5.3
Standby Power
With CE# at a logic-high level (VIH) and device in read mode, the flash memory is in standby
mode, which disables much of the device’s circuitry and substantially reduces power consumption.
Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE#
transitions to a logic-high level during erase or program operations, the device will continue to
perform the operation and consume corresponding active power until the operation is completed.
System engineers should analyze the breakdown of standby time versus active time and quantify
the respective power consumption in each mode for their specific application. This will provide a
more accurate measure of application-specific power and energy requirements.
3.5.4
Deep Power-Down Mode
The deep power-down mode is activated when RP# = VIL (GND ± 0.2 V). During read modes,
RP# going low de-selects the memory and places the outputs in a high impedance state. Recovery
from deep power-down requires a minimum time of tPHQV (see AC Characteristics—Read
Operations, Section 4.5).
During program or erase modes, RP# transitioning low will abort the in-progress operation. The
memory contents of the address being programmed or the block being erased are no longer valid as
the data integrity has been compromised by the abort. During deep power-down, all internal
circuits are switched to a low power savings mode (RP# transitioning to VIL or turning off power to
the device clears the status register).
3.6
Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions.
Power supply sequencing is not required, since the device is indifferent as to which power supply,
VPP or VCC, powers-up first.
16
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.6.1
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting RP# to the
system CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when VCC voltages are above VLKO. Since
both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs.
By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
3.6.2
VCC, VPP and RP# Transitions
The CUI latches commands as issued by system software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
VCC transitions above VLKO (Lockout voltage), is read array mode.
After any program or block erase operation is complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the
flash memory array is desired.
3.7
Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling. System
designers should consider three supply current issues:
1. Standby current levels (ICCS)
2. Read current levels (ICCR)
3. Transient peaks produced by falling and rising edges of CE#.
Transient current magnitudes depend on the device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor selection will suppress these transient voltage
peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each VCC and
GND, and between its VPP and GND. These high-frequency, inherently low-inductance capacitors
should be placed as close as possible to the package leads.
3UHOLPLQDU\
17
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.0
Electrical Specifications
4.1
Absolute Maximum Ratings
Parameter
Maximum Rating
Extended Operating Temperature
During Read
–40 °C to +85 °C
During Block Erase and Program
–40 °C to +85 °C
Temperature under Bias
–40 °C to +85 °C
Storage Temperature
–65 °C to +125 °C
Voltage On Any Pin (except VCC, VCCQ and VPP) with Respect to GND
–0.5 V to +3.7 V(1)
VPP Voltage (for Block Erase and Program) with Respect to GND
–0.5 V to +13.5 V(1,2,3)
VCC and VCCQ Supply Voltage with Respect to GND
–0.2 V to +3.7 V(4)
Output Short Circuit Current
100 mA(5)
NOTES:
1. Minimum DC voltage is -0.5 V on input/output pins, with allowable undershoot to -2.0 V for periods <20 ns.
Maximum DC voltage on input/output pins is VCC +0.5 V, with allowable overshoot to VCC +1.5 for periods of
<20 ns
2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns.
3. VPP Program voltage is normally 2.7 V–3.6 V. Connection to a 11.4 V–12.6 V supply can be done for a
maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase.
VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.4 for details.
4. Minimum DC voltage is -0.5 V on VCC and VCCQ, with allowable undershoot to -2.0 V for periods <20 ns.
Maximum DC voltage on VCC and VCCQ pins is VCC +0.5 V, with allowable overshoot to VCC +1.5 for periods
of <20 ns.
5. Output shorted for no more than one second. No more than one output shorted at a time.
NOTICE: This datasheet contains preliminary information on new products in production. Specifications are
subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before
finalizing a design.
Warning:
18
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.2
Operating Conditions
Symbol
TA
Parameter
Notes
Operating Temperature
VCC1
VCC2
1, 2
–40
+85
°C
3.6
2.85
2.7
3.3
2.7
3.6
1.65
2.5
1.8
2.5
2.7
3.6
2.7
2.85
2.7
3.3
3, 4
11.4
12.6
4
100,000
1
I/O Supply Voltage
VCCQ3
VPP1
1
Program and Erase Voltage
VPP4
Volts
Volts
Volts
VPP3
Cycling
Units
2.7
VCCQ1
VPP2
Max
2.7
VCC Supply Voltage
VCC3
VCCQ2
Min
Block Erase Cycling
Cycles
NOTES:
1. VCC1, VCCQ1, and VPP3 must share the same supply when all three are between 2.7 V and 3.6 V.
2. VCCMax is 3.3 V on 0.25µm 32-Mbit devices.
3. During read operations or idle time, 5 V may be applied to VPP indefinitely. VPP must be at valid levels for
program and erase operations
4. Applying VPP = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on
the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of
80 hours maximum. See Section 3.4 for details.
4.3
Capacitance
TA = 25 °C, f = 1 MHz
Sym
Parameter
Notes
Typ
Max
Units
Conditions
CIN
Input Capacitance
1
6
8
pF
VIN = 0 V
COUT
Output Capacitance
1
10
12
pF
VOUT = 0 V
NOTE: Sampled, not 100% tested.
3UHOLPLQDU\
19
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.4
Sym
DC Characteristics
Parameter
VCC
2.7 V–3.6 V
2.7 V–2.85 V
2.7 V–3.3 V
VCCQ
2.7 V–3.6 V
1.65 V–2.5 V
1.8 V–2.5 V
Note
Typ
Typ
Typ
Max
Max
Unit
Test Conditions
Max
ILI
Input Load Current
1,2
±1
±1
±1
µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
ILO
Output Leakage Current
1,2
± 10
± 10
± 10
µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
VCC Standby Current for
0.18 Micron Product
1,2
7
15
20
50
150
250
µA
VCC Standby Current for
0.25 Micron and
0.4 Micron Product
1,2
18
35
20
50
150
250
µA
VCC Power-Down Current
for 0.18 Micron Product
1,2
7
15
7
20
7
20
µA
VCC Power-Down Current
for 0.25 Micron and
0.4 Micron Product
1,2
7
25
7
25
7
25
µA
VCC Read Current for
0.18 Micron Product
1,2,3
9
18
8
15
9
15
mA
VCC Read Current for
0.25 and 0.4 Micron
Product
1,2,3
10
18
8
15
9
15
mA
0.2
5
0.2
5
0.2
5
µA
RP# = GND ± 0.2 V
VPP ≤ VCC
ICCS
ICCD
ICCR
IPPD
VPP Deep Power-Down
Current
IPPR
VPP Read Current
VCC + VPP Program
Current for 0.18 Micron
Product
WP# = VCCQ or GND
20
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
RP# = GND ± 0.2 V
VCC = VCCMax
VCCQ = VCCQMax
OE# = VIH , CE# =VIL
f = 5 MHz, IOUT=0 mA
Inputs = VIL or VIH
2
±15
2
±15
2
±15
µA
VPP ≤ VCC
50
200
50
200
50
200
µA
VPP > VCC
18
55
18
55
18
55
mA
VPP =VPP1, 2, 3
Program in Progress
8
15
10
30
10
30
mA
VPP = VPP4
Program in Progress
18
55
18
55
18
55
mA
VPP =VPP1, 2, 3
Program in Progress
10
30
10
30
10
30
mA
VPP = VPP4
Program in Progress
1,4
1,2,4
ICCW+
IPPW
VCC + VPP Program
Current for 0.25 Micron
and 0.4 Micron Product
VCC = VCCMax
CE# = RP# = VCCQ
or during Program/
Erase Suspend
1,2,4
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
DC Characteristics, Continued
Sym
Parameter
VCC + VPP Erase Current
for 0.18 Micron Product
VCC
2.7 V–3.6 V
2.7 V–2.85 V
2.7 V–3.3 V
VCCQ
2.7 V–3.6 V
1.65 V–2.5 V
1.8 V–2.5 V
Note
Typ
Max
Typ
Max
Typ
Max
16
45
21
45
21
45
mA
VPP = VPP1, 2, 3
Program in
Progress
16
45
16
45
16
45
mA
VPP = VPP4
Program in
Progress
20
45
21
45
21
45
mA
VPP = VPP1, 2, 3
Program in
Progress
16
45
16
45
16
45
mA
VPP = VPP4
Program in
Progress
50
200
50
200
50
200
µA
VPP = VPP1, 2, 3, 4
Program or Erase
Suspend in
Progress
Unit
1,2,4
ICCE
+IPPE
VCC + VPP Erase Current
for 0.25 Micron and 0.4
Micron Product
IPPES
IPPWS
VPP Erase Suspend
Current
1,2,4
1,4
Test Conditions
DC Characteristics, Continued
Sym
Parameter
VCC
2.7 V–3.6 V
2.7 V–2.85 V
2.7 V–3.3 V
VCCQ
2.7 V–3.6 V
1.65 V–2.5 V
1.8 V–2.5 V
Note
Min
Max
Min
Max
Min
Max
Unit
Test Conditions
VIL
Input Low Voltage
–0.4
VCC *
0.22 V
–0.4
0.4
–0.4
0.4
V
VIH
Input High Voltage
2.0
VCCQ
+0.3V
VCCQ
–0.4V
VCCQ
+0.3V
VCCQ
–0.4V
VCCQ
+0.3V
V
VOL
Output Low Voltage
–0.1
0.1
-0.1
0.1
-0.1
0.1
V
VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
VOH
Output High Voltage
VCCQ
–0.1V
V
VCC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
VPPLK
VPP Lock-Out Voltage
V
Complete Write
Protection
5
VPP1
5
VPP2
5
VPP3
VPP during Program and
Erase Operations
1.5
2.7
VCCQ
–0.1V
1.5
V
2.7
11.4
1.5
3.6
2.85
5
5,6
VPP4
VCCQ
–0.1V
12.6
11.4
12.6
V
2.7
3.3
V
11.4
12.6
V
VLKO
VCC Prog/Erase
Lock Voltage
1.5
1.5
1.5
V
VLKO2
VCCQ Prog/Erase
Lock Voltage
1.2
1.2
1.2
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25 °C.
3UHOLPLQDU\
21
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
2. Since each column lists specifications for a different VCC and VCCQ voltage range combination, the test
conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or VCCQ
voltage listed at the top of each column. VCCMax is 3.3 V on 0.25µm 32-Mbit devices.
3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation.
4. Sampled, not 100% tested.
5. Erase and program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of
VPP1, VPP2, VPP3 and VPP4. For read operations or during idle time, a 5 V supply may be applied to VPP
indefinitely. However, VPP must be at valid levels for program and erase operations.
6. Applying VPP = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the
main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours
maximum. See Section 3.4 for details. For read operations or during idle time, a 5 V supply may be applied to
VPP indefinitely. However, VPP must be at valid levels for program and erase operations.
Figure 5. Input/Output Reference Waveform
VCCQ
VCCQ
INPUT
2
VCCQ
TEST POINTS
2
OUTPUT
0.0
0580_05
NOTE: AC test inputs are driven at VCCQ for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output
timing ends, at VCCQ/2. Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are
when VCCQ = VCCQMin.
Figure 6. Test Configuration
VCCQ
R
1
Device
under
Test
Out
CL
R
2
0580_06
NOTE: See table for component values.
Test Configuration Component Values for Worst
Case Speed Conditions
CL (pF)
R1 (Ω)
R2 (Ω)
VCCQ1 Standard Test
50
25 K
25 K
VCCQ2 Standard Test
50
14.5 K
14.5 K
VCCQ3 Standard Test
50
16 K
16 K
Test Configuration
NOTE: CL includes jig capacitance.
22
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.5
AC Characteristics —Read Operations
Density
4/8 Mbit
Product
#
Sym
90 ns
110 ns
Parameter
Unit
VCC
3.0 V–3.6 V
2.7 V–3.6 V
3.0 V–3.6 V
2.7 V–3.6 V
Min
Min
Min
Min
Max
Max
Max
Max
R1
tAVAV
Read Cycle Time
R2
tAVQV
Address to Output Delay
80
90
100
110
ns
R3
tELQV
CE# to Output Delay(1)
80
90
100
110
ns
R4
tGLQV
(1)
OE# to Output Delay
30
30
30
30
ns
R5
tPHQV
RP# to Output Delay
600
600
600
600
R6
tELQX
CE# to Output in Low Z(2)
0
0
0
0
ns
R7
tGLQX
OE# to Output in Low Z(2)
0
0
0
0
ns
R8
tEHQZ
CE# to Output in High Z
(2)
25
25
25
25
ns
R9
tGHQZ
OE# to Output in High Z(2)
25
25
25
25
ns
tOH
Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First(2)
R10
80
0
90
0
100
0
110
0
ns
ns
ns
NOTES:
1. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
2. Sampled, but not 100% tested.
See Figure 7, “AC Waveform: Read Operations” on page 26.
See Figure 5, “Input/Output Reference Waveform” on page 22 for timing measurements and maximum allowable
input slew rate.
3UHOLPLQDU\
23
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
AC Characteristics, Continued
Density
#
R1
Sym
Parameter
16 Mbit
Product
70 ns
80 ns
90 ns
110 ns
VCC
2.7 V–3.6 V
2.7 V–3.6 V
3.0 V–3.6 V
2.7 V–3.6 V
3.0 V–3.6 V
2.7 V–3.6 V
Min
Min
Min
Min
Min
Min
Unit
Max
Max
Max
Max
Max
Max
tAVAV
Read Cycle Time
tAVQV
Address to Output
Delay
70
80
80
90
100
110
ns
R3
tELQV
CE# to Output
Delay(1)
70
80
80
90
100
110
ns
R4
tGLQV
OE# to Output
Delay(1)
20
20
30
30
30
30
ns
R5
tPHQV
RP# to Output Delay
150
150
600
600
600
600
ns
R6
tELQX
CE# to Output in
Low Z(2)
0
0
0
0
0
0
ns
R7
tGLQX
OE# to Output in
Low Z(2)
0
0
0
0
0
0
ns
R8
tEHQZ
CE# to Output in
High Z(2)
20
20
25
25
25
25
ns
R9
tGHQZ
OE# to Output in
High Z(2)
20
20
25
25
25
25
ns
R10
tOH
R2
Output Hold from
Address, CE#, or
OE# Change,
Whichever Occurs
First(2)
70
0
80
0
80
0
90
0
100
0
110
ns
0
ns
NOTES:
1. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
2. Sampled, but not 100% tested.
See Figure 7, “AC Waveform: Read Operations” on page 26.
See Figure 5, “Input/Output Reference Waveform” on page 22 for timing measurements and maximum
allowable input slew rate.
24
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
AC Characteristics, Continued
Density
#
R1
Sym
Parameter
32 Mbit
Product
70 ns
90 ns
100 ns
110 ns
VCC
2.7 V–3.6 V
2.7 V–3.6 V
3.0 V–3.3 V
2.7 V–3.3 V
3.0 V–3.3 V
2.7 V–3.3 V
Min
Min
Min
Min
Min
Min
Unit
Max
Max
Max
Max
Max
Max
tAVAV
Read Cycle Time
R2
tAVQV
Address to Output
Delay
70
90
90
100
100
110
ns
R3
tELQV
CE# to Output
Delay(1)
70
90
90
100
100
110
ns
R4
tGLQV
OE# to Output
Delay(1)
20
20
30
30
30
30
ns
R5
tPHQV
RP# to Output
Delay
150
150
600
600
600
600
ns
R6
tELQX
CE# to Output in
Low Z(2)
0
0
0
0
0
0
ns
R7
tGLQX
OE# to Output in
Low Z(2)
0
0
0
0
0
0
ns
R8
tEHQZ
CE# to Output in
High Z(2)
20
20
25
25
25
25
ns
R9
tGHQZ
OE# to Output in
High Z(2)
20
20
25
25
25
25
ns
R10
tOH
Output Hold from
Address, CE#, or
OE# Change,
Whichever Occurs
First(2)
70
0
90
0
90
0
100
0
100
0
110
ns
0
ns
NOTES:
1. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
2. Sampled, but not 100% tested.
See Figure 7, “AC Waveform: Read Operations” on page 26.
See Figure 5, “Input/Output Reference Waveform” on page 22 for timing measurements and maximum
allowable input slew rate.
3UHOLPLQDU\
25
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
AC Characteristics, Continued
Density
#
Sym
64 Mbit
Product
90 ns
100 ns
VCC
2.7 V–3.6 V
2.7 V–3.6 V
Min
Min
Parameter
Unit
Note
Max
Max
R1
tAVAV
Read Cycle Time
R2
tAVQV
Address to Output Delay
R3
tELQV
CE# to Output Delay
1
R4
tGLQV
OE# to Output Delay
1
R5
tPHQV
RP# to Output Delay
R6
tELQX
CE# to Output in Low Z
2
0
0
ns
R7
tGLQX
OE# to Output in Low Z
2
0
0
ns
R8
tEHQZ
CE# to Output in High Z
2
20
20
ns
R9
tGHQZ
OE# to Output in High Z
2
20
20
ns
R10
tOH
Output Hold from Address, CE#, or
OE# Change, Whichever Occurs First
2
90
0
100
ns
90
100
ns
90
100
ns
20
20
ns
150
150
ns
0
ns
NOTES:
1. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
2. Sampled, but not 100% tested.
See Figure 7 for the AC waveform for read operations.
See Figure 5, “Input/Output Reference Waveform” on page 22 for timing measurements and maximum
allowable input slew rate.
Figure 7. AC Waveform: Read Operations
Standby
Device
Address Selection
Data Valid
VIH
ADDRESSES (A)
Address Stable
VIL
R1
VIH
CE# (E)
VIL
R8
OE# (G)
VIH
VIL
WE# (W)
R9
VIH
R4
VIL
DATA (D/Q)
VOH
R7
R3
High Z
R6
Valid Output
R10
High Z
VOL
R2
VIH
RP# (P)
26
VIL
R5
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.6
AC Characteristics —Write Operations
Density
4/8 Mbit
Product
#
Sym
Parameter
VCC
Note
90 ns
110 ns
Unit
3.0 V –
3.6 V
2.7 V –
3.6 V
3.0 V –
3.6 V
2.7 V –
3.6 V
Min
Min
Min
Min
600
600
600
600
ns
0
0
0
0
ns
W1
tPHWL /
tPHEL
RP# High Recovery to WE# (CE#) Going Low
W2
tELWL /
tWLEL
CE# (WE#) Setup to WE# (CE#) Going Low
W3
tELEH /
tWLWH
WE# (CE#) Pulse Width
1
70
70
70
70
ns
W4
tDVWH /
tDVEH
Data Setup to WE# (CE#) Going High
2
50
50
60
60
ns
W5
tAVWH /
tAVEH
Address Setup to WE# (CE#) Going High
2
70
70
70
70
ns
W6
tWHEH /
tEHWH
CE# (WE#) Hold Time from WE# (CE#) High
0
0
0
0
ns
W7
tWHDX /
tEHDX
Data Hold Time from WE# (CE#) High
2
0
0
0
0
ns
W8
tWHAX /
tEHAX
Address Hold Time from WE# (CE#) High
2
0
0
0
0
ns
W9
tWHWL /
tEHEL
WE# (CE#) Pulse Width High
1
30
30
30
30
ns
W10
tVPWH /
tVPEH
VPP Setup to WE# (CE#) Going High
3
200
200
200
200
ns
W11
tQVVL
VPP Hold from Valid SRD
3
0
0
0
0
ns
NOTES:
1. Refer to command definition table (Table 6) for valid AIN or DIN.
2. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going
high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, Write pulse width
high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
(whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
3. Sampled, but not 100% tested.
Read timing characteristics during program suspend and erase suspend are the same as during read-only
operations.
See Figure 5 for timing measurements and maximum allowable input slew rate.
See Figure 8, “AC Waveform: Program and Erase Operations” on page 32.
3UHOLPLQDU\
27
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
AC Characteristics—Write Operations, continued
Density
Product
#
Sym
16 Mbit
70 ns
80 ns
VCC
2.7 V –
3.6 V
2.7 V –
3.6 V
3.0 V –
3.6 V
2.7 V –
3.6 V
3.0 V –
3.6 V
2.7 V –
3.6 V
Note
Min
Min
Min
Min
Min
Min
150
150
600
600
600
600
ns
0
0
0
0
0
0
ns
Parameter
90 ns
110 ns
Unit
W1
tPHWL /
tPHEL
RP# High Recovery to WE# (CE#)
Going Low
W2
tELWL /
tWLEL
CE# (WE#) Setup to WE# (CE#) Going
Low
W3
tELEH /
tWLWH
WE# (CE#) Pulse Width
1
45
50
70
70
70
70
ns
W4
tDVWH /
tDVEH
Data Setup to WE# (CE#) Going High
2
40
40
50
50
60
60
ns
W5
tAVWH /
tAVEH
Address Setup to WE# (CE#) Going
High
2
50
50
70
70
70
70
ns
W6
tWHEH /
tEHWH
CE# (WE#) Hold Time from WE#
(CE#) High
0
0
0
0
0
0
ns
W7
tWHDX /
tEHDX
Data Hold Time from WE# (CE#) High
2
0
0
0
0
0
0
ns
W8
tWHAX /
tEHAX
Address Hold Time from WE# (CE#)
High
2
0
0
0
0
0
0
ns
W9
tWHWL /
tEHEL
WE# (CE#) Pulse Width High
1
25
30
30
30
30
30
ns
W10
tVPWH /
tVPEH
VPP Setup to WE# (CE#) Going High
3
200
200
200
200
200
200
ns
W11
tQVVL
VPP Hold from Valid SRD
3
0
0
0
0
0
0
ns
NOTES:
1. Refer to command definition table (Table 6) for valid AIN or DIN.
2. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going
high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, Write pulse width
high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
(whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
3. Sampled, but not 100% tested.
Read timing characteristics during program suspend and erase suspend are the same as during read-only
operations.
See Figure 5 for timing measurements and maximum allowable input slew rate.
See Figure 8, “AC Waveform: Program and Erase Operations” on page 32.
28
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
AC Characteristics—Write Operations, continued
Density
#
Sym
32 Mbit
Product
70 ns
90 ns
VCC
2.7 V –
3.6 V
2.7 V –
3.6 V
3.0 V –
3.3 V
2.7 V –
3.3 V
3.0 V –
3.3 V
2.7 V –
3.3 V
Note
Min
Min
Min
Min
Min
Min
150
150
600
600
600
600
ns
0
0
0
0
0
0
ns
Parameter
90 ns
110 ns
Unit
W1
tPHWL /
tPHEL
RP# High Recovery to WE# (CE#)
Going Low
W2
tELWL /
tWLEL
CE# (WE#) Setup to WE# (CE#) Going
Low
W3
tELEH /
tWLWH
WE# (CE#) Pulse Width
1
45
60
70
70
70
70
ns
W4
tDVWH /
tDVEH
Data Setup to WE# (CE#) Going High
2
40
40
50
50
60
60
ns
W5
tAVWH /
tAVEH
Address Setup to WE# (CE#) Going
High
2
50
60
70
70
70
70
ns
W6
tWHEH /
tEHWH
CE# (WE#) Hold Time from WE#
(CE#) High
0
0
0
0
0
0
ns
W7
tWHDX /
tEHDX
Data Hold Time from WE# (CE#) High
2
0
0
0
0
0
0
ns
W8
tWHAX /
tEHAX
Address Hold Time from WE# (CE#)
High
2
0
0
0
0
0
0
ns
W9
tWHWL /
tEHEL
WE# (CE#) Pulse Width High
1
25
30
30
30
30
30
ns
W10
tVPWH /
tVPEH
VPP Setup to WE# (CE#) Going High
3
200
200
200
200
200
200
ns
W11
tQVVL
VPP Hold from Valid SRD
3
0
0
0
0
0
0
ns
NOTES:
1. Refer to command definition table (Table 6) for valid AIN or DIN.
2. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going
high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, Write pulse width
high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
(whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
3. Sampled, but not 100% tested.
Read timing characteristics during program suspend and erase suspend are the same as during read-only
operations.
See Figure 5 for timing measurements and maximum allowable input slew rate.
See Figure 8, “AC Waveform: Program and Erase Operations” on page 32.
3UHOLPLQDU\
29
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
AC Characteristics—Write Operations, continued
Density
Product
#
Sym
Parameter
VCC
Note
64 Mbit
90 ns
100 ns
2.7 V –
3.6 V
2.7 V –
3.6 V
Min
Min
150
150
ns
0
0
ns
Unit
W1
tPHWL /
tPHEL
RP# High Recovery to WE# (CE#) Going Low
W2
tELWL /
tWLEL
CE# (WE#) Setup to WE# (CE#) Going Low
W3
tELEH /
tWLWH
WE# (CE#) Pulse Width
1
60
70
ns
W4
tDVWH /
tDVEH
Data Setup to WE# (CE#) Going High
2
40
40
ns
W5
tAVWH /
tAVEH
Address Setup to WE# (CE#) Going High
2
60
60
ns
W6
tWHEH /
tEHWH
CE# (WE#) Hold Time from WE# (CE#) High
0
0
ns
W7
tWHDX /
tEHDX
Data Hold Time from WE# (CE#) High
2
0
0
ns
W8
tWHAX /
tEHAX
Address Hold Time from WE# (CE#) High
2
0
0
ns
W9
tWHWL /
tEHEL
WE# (CE#) Pulse Width High
1
30
30
ns
W10
tVPWH /
tVPEH
VPP Setup to WE# (CE#) Going High
3
200
200
ns
W11
tQVVL
VPP Hold from Valid SRD
3
0
0
ns
NOTES:
1. Refer to command definition table (Table 6) for valid AIN or DIN.
2. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going
high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, Write pulse width
high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
(whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
3. Sampled, but not 100% tested.
Read timing characteristics during program suspend and erase suspend are the same as during read-only
operations.
See Figure 5 for timing measurements and maximum allowable input slew rate.
See Figure 8, “AC Waveform: Program and Erase Operations” on page 32.
30
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.7
Program and Erase Timings
VPP
Symbol
tBWPB
tBWMB
tWHQV2 / tEHQV2
tWHQV3 / tEHQV3
11.4 V–12.6 V
Units
Notes
Typ(1)
Max
Typ(1)
Max
8-KB Parameter Block
Program Time (Byte)
2, 3
0.16
0.48
0.08
0.24
s
4-KW Parameter Block
Program Time (Word)
2, 3
0.10
0.30
0.03
0.12
s
64-KB Main Block
Program Time (Byte)
2, 3, 4
1.2
3.7
0.6
1.7
s
32-KW Main Block
Program Time(Word)
2, 3
0.8
2.4
0.24
1
s
Byte Program Time
tWHQV1 / tEHQV1
2.7 V–3.6 V
Parameter
2, 3, 4
17
165
8
185
µs
Word Program Time for
0.18 Micron Product
2,3
12
200
8
185
µs
Word Program Time for 0.25
Micron and 0.4 Micron Products
2, 3
22
200
8
185
µs
8-KB Parameter Block
Erase Time (Byte)
2, 3, 4
1
4
0.8
4
s
4-KW Parameter Block
Erase Time (Word)
2, 3
0.5
4
0.4
4
s
64-KB Main Block
Erase Time (Byte)
2, 3, 4
1
5
1
5
s
32-KW Main Block
Erase Time (Word)
2, 3
1
5
0.6
5
s
tWHRH1 / tEHRH1
Program Suspend Latency
5
10
5
10
µs
tWHRH2 / tEHRH2
Erase Suspend Latency
5
20
5
20
µs
NOTES:
1.
2.
3.
4.
3UHOLPLQDU\
Typical values measured at nominal voltages and TA = +25 °C.
Excludes external system-level overhead.
Sampled, not 100% tested.
x8 not available on 0.18 µm offerings
31
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 8. AC Waveform: Program and Erase Operations
VIH
A
B
C
AIN
ADDRESSES [A]
VIL
VIH
D
W8
W5
CE#(WE#) [E(W)]
VIL
E
F
AIN
(Note 1)
W6
VIH W2
OE# [G]
VIL
W9
(Note 1)
VIH
WE#(CE#) [W(E)]
VIL
W3
W4
VIH
DATA [D/Q]
High Z
VIL
RP# [P]
W7
DIN
DIN
W1
Valid
SRD
DIN
VIH
VIL
VIH
WP#
V
[V]
PP
VIL
W10
W11
VPPH 2
VPPH1
VPPLK
VIL
0580_08
NOTES:
1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading
Status Register Data.
A. VCC Power-Up and Standby.
B. Write Program or Erase Setup Command.
C. Write Valid Address and Data (for Program) or Erase Confirm Command.
D. Automated Program or Erase Delay.
E. Read Status Register Data (SRD): reflects completed program/erase operation.
F.Write Read Array Command.
32
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
5.0
Reset Operations
Figure 9. AC Waveform: Deep Power-Down/Reset Operation
RP# (P)
VIH
VIL
t PLPH
(A) Reset during Read Mode
t PHQV
t PHWL
t PHEL
Abort
Complete
t PLRH
RP# (P)
VIH
t PHQV
t PHWL
t PHEL
V IL
t PLPH
(B) Reset during Program or Block Erase, t PLPH < t PLRH
Abort Deep
Complete PowerDown
RP# (P)
VIH
VIL
t PLRH
t PHQV
t PHWL
t PHEL
t PLPH
(C) Reset Program or Block Erase, t PLPH > t PLRH
0580_09
Reset Specifications
VCC = 2.7 V–3.6 V
Symbol
Parameter
Unit
Notes
Min
tPLPH
RP# Low to Reset during Read
(If RP# is tied to VCC, this specification is not applicable)
1,2
tPLRH
RP# Low to Reset during Block Erase or Program
2,3
Max
100
ns
22
µs
NOTES:
1. If tPLPH is <100 ns the device may still RESET but this is not guaranteed
2. .Sampled, but not 100% tested.
3. If RP# is asserted while a block erase or word program operation is not executing, the reset will complete
within 100 ns.
3UHOLPLQDU\
33
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
6.0
Ordering Information
T E2 8 F 3 2 0 B3 T C7 0
Package
TE = 40-Lead/48-Lead TSOP
GT = 48-Ball µBGA* CSP
GE = VF BGA CSP
Product line designator
for all Intel® Flash products
Device Density
640 = x16 (64 Mbit)
320 = x16 (32 Mbit)
160 = x16 (16 Mbit)
800 = x16 (8 Mbit)
400 = x16 (4 Mbit)
016 = x8 (16 Mbit)
008 = x8 (8 Mbit)
004 = x8 (4 Mbit)
34
Access Speed (ns)
(70, 80, 90, 100, 110)
Lithography
Not Present = 0.4 µm
A = 0.25 µm
C = 0.18 µm
T = Top Blocking
B = Bottom Blocking
Product Family
B3 = 3 Volt Advanced Boot Block
VCC = 2.7 V - 3.6 V
VPP = 2.7 V - 3.6 V or
11.4 V - 12.6 V
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Ordering Information Valid Combinations
48-Ball µBGA* CSP(1,2)
40-Lead TSOP
Ext. Temp.
64 Mbit
Ext. Temp
4 Mbit
GT28F640B3TC90
TE28F640B3BC90
GT28F640B3BC90
TE28F640B3TC100
GT28F640B3TC100
TE28F640B3BC100
GT28F640B3BC100
GE28F320B3TC70
TE28F320B3BC70
GE28F320B3BC70
TE28F320B3TC90
GE28F320B3TC90
GE28F320B3BC90
TE28F320B3TA100
GT28F320B3TA100
TE28F320B3BA100
GT28F320B3BA100
TE28F320B3TA110
GT28F320B3TA110
TE28F320B3BA110
GT28F320B3BA110
TE28F160B3TC70
GE28F160B3TC70
TE28F160B3BC70
GE28F160B3BC70
TE28F160B3TC80
GE28F160B3TC80
GE28F160B3BC80
TE28F016B3TA90(3)
GT28F016B3TA90(3)
TE28F160B3TA90(3)
GT28F160B3TA90(3)
TE28F016B3BA90(3)
GT28F016B3BA90(3)
TE28F160B3BA90(3)
GT28F160B3BA90(3)
(3)
48-Ball VF BGA
TE28F320B3TC70
TE28F160B3BC80
(3)
Ext. Temp.
8 Mbit
TE28F640B3TC90
TE28F320B3BC90
Ext. Temp.
32 Mbit
Ext. Temp.
16 Mbit
48-Ball µBGA CSP(1,2)
48-Lead TSOP
TE28F016B3TA110
GT28F016B3TA110
TE28F160B3TA110
GT28F160B3TA110(3)
TE28F016B3BA110(3)
GT28F016B3BA110(3)
TE28F160B3BA110(3)
GT28F160B3BA110(3)
TE28F008B3TA90(3)
GT28F008B3T90
TE28F800B3TA90(3)
GT28F800B3T90
GE28F800B3TA90
TE28F008B3BA90(3)
GT28F008B3B90
TE28F800B3BA90(3)
GT28F800B3B90
GE28F800B3BA90
TE28F008B3TA110(3)
GT28F008B3T110
TE28F800B3TA110(3)
GT28F800B3T110
GE28F008B3TA90
TE28F008B3BA110(3)
GT28F008B3B110
TE28F800B3BA110(3)
GT28F800B3B110
GE28F008B3BA90
TE28F004B3T90
TE28F400B3T90
TE28F004B3B90
TE28F400B3B90
TE28F004B3T110
TE28F400B3T110
TE28F004B3B110
TE28F400B3B110
(3)
NOTES:
1. The 48-ball µBGA package top side mark reads F160B3 [or F800B3]. This mark is identical for both x8 and
x16 products. All product shipping boxes or trays provide the correct information regarding bus architecture.
However, once the devices are removed from the shipping media, it may be difficult to differentiate based on
the top side mark. The device identifier (accessible through the Device ID command: see Section 3.2.2 for
further details) enables x8 and x16 µBGA package product differentiation.
2. The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples only, the
first character signifies either “E” for engineering samples or “S” for silicon daisy chain samples. All other
assembly codes without an “E” or “S” as the first character are production units.
3. Product can be ordered in either 0.25 µm or 0.4 µm material. The “A” before the access speed specifies
0.25 µm material. For new designs, Intel recommends using 0.25 µm Advanced Boot Block devices.
3UHOLPLQDU\
35
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
7.0
Additional Information
Order Number
Document/Tool
297948
3 Volt Advanced Boot Block Flash Memory Family Specification Update
292199
AP-641 Achieving Low Power with the 3 Volt Advanced Boot Block Flash Memory
292200
AP-642 Designing for Upgrade to the 3 Volt Advanced Boot Block Flash Memory
Note 2
3 Volt Advanced Boot Block Algorithms (‘C’ and assembly)
http://developer.intel.com/design/flash/swtools
Contact your Intel Representative
297874
Intel® Flash Data Integrator (IFDI) Software Developer’s Kit
IFDI Interactive: Play with Intel® Flash Data Integrator on Your PC
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International
customers should contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical
documentation and tools.
3. For the most current information on Intel Advanced and Advanced+ Boot Block Flash memory, visit our
microsite at http://developer.intel.com/design/flash/abblock.
36
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Appendix A Write State Machine Current/Next States
Command Input (and Next State)
Current State
SR.7
Data
When
Read
Read
Array
(FFH)
Program
Setup (10/
40H)
Erase
Setup
(20H)
Read Array
“1”
Array
Read
Array
Program
Setup
Erase
Setup
Read Status
“1”
Status
Read
Array
Program
Setup
Read
Identifier
“1”
Identifier
Read
Array
Program
Setup
Prog. Setup
“1”
Status
Program
(continue)
“0”
Status
Program
Suspend to
Read Status
“1”
Status
Prog.
Sus. to
Read
Array
Program Suspend
to Read Array
Program
(continue)
Program
Susp. to
Read Array
Program
(continue)
Prog.
Susp. to
Read
Status
Prog.
Sus. to
Read
Array
Prog.
Susp. to
Read
Identifier
Program
Suspend to
Read Array
“1”
Array
Prog.
Susp. to
Read
Array
Program Suspend
to Read Array
Program
(continue)
Program
Susp. to
Read Array
Program
(continue)
Prog.
Susp. to
Read
Status
Prog.
Sus. to
Read
Array
Prog.
Susp. to
Read
Identifier
Prog. Susp. to
Read
Identifier
“1”
Identifier
Prog.
Susp. to
Read
Array
Program Suspend
to Read Array
Program
(continue)
Program
Susp. to
Read Array
Program
(continue)
Prog.
Susp. to
Read
Status
Prog.
Sus. to
Read
Array
Prog.
Susp. to
Read
Identifier
Program
(complete)
“1”
Status
Read
Array
Read
Status
Read
Array
Read
Identifier
Erase Setup
“1”
Status
Erase Cmd.
Error
“1”
Status
Erase
(continue)
“0”
Status
Erase
Suspend to
Status
“1”
Status
Erase
Susp. to
Read
Array
Program
Setup
Erase
Susp. to
Read
Array
Erase
Erase
Susp. to
Read Array
Erase
Erase
Susp. to
Read
Status
Erase
Susp. to
Read
Array
Ers. Susp.
to Read
Identifier
Erase Susp.
to Read
Array
“1”
Array
Erase
Susp. to
Read
Array
Program
Setup
Erase
Susp. to
Read
Array
Erase
Erase
Susp. to
Read Array
Erase
Erase
Susp. to
Read
Status
Erase
Susp. to
Read
Array
Ers. Susp.
to Read
Identifier
Erase Susp.
to Read
Identifier
“1”
Identifier
Erase
Susp. to
Read
Array
Program
Setup
Erase
Susp. to
Read
Array
Erase
Erase
Susp. to
Read Array
Erase
Erase
Susp. to
Read
Status
Erase
Susp. to
Read
Array
Ers. Susp.
to Read
Identifier
Erase
(complete)
“1”
Status
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array
Read
Identifier
3UHOLPLQDU\
Erase
Confirm
(D0H)
Prog/Ers
Suspend
(B0H)
Prog/Ers
Resume
(D0H)
Read
Status
(70H)
Clear
Status
(50H)
Read
Identifier.
(90H)
Read Array
Read
Status
Read
Array
Read
Identifier
Erase
Setup
Read Array
Read
Status
Read
Array
Read
Identifier
Erase
Setup
Read Array
Read
Status
Read
Array
Read
Identifier
Program (Command Input = Data to be Programmed)
Prog. Susp.
to Rd.
Status
Program (continue)
Program
Setup
Erase
Setup
Erase Command Error
Read
Array
Program (continue)
Read Array
Erase
(continue)
Erase
Cmd. Error
Erase
(continue)
Erase Command Error
Erase
Setup
Read Array
Read
Status
Erase (continue)
Erase Sus.
to Read
Status
Erase (continue)
Program
Setup
Read Array
Read
Array
Read
Identifier
37
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Appendix B Architecture Block Diagram
DQ0-DQ15
VCCQ
Power
Reduction
Control
Input Buffer
Identifier
Register
Status
Register
Data
Register
Output
Multiplexer
Output Buffer
I/O Logic
CE#
WE#
OE#
RP#
Command
User
Interface
Data
Comparator
WP#
A0-A19
Y-Decoder
Y-Gating/Sensing
Write State
Machine
Address
Counter
32-KWord
Main Block
X-Decoder
4-KWord
Parameter Block
32-KWord
Main Block
Address
Latch
4-KWord
Parameter Block
Input Buffer
Program/Erase
Voltage Switch
VPP
VCC
GND
0580-C1
38
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Appendix C Word-Wide Memory Map Diagrams
16-Mbit and 32-Mbit Word-Wide Memory Addressing
Top Boot
Size
(KW)
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
3UHOLPLQDU\
16 Mbit
Bottom Boot
32 Mbit
FF000-FFFFF
1FF000-1FFFFF
FE000-FEFFF
1FE000-1FEFFF
FD000-FDFFF
1FD000-1FDFFF
FC000-FCFFF
1FC000-1FCFFF
FB000-FBFFF
1FB000-1FBFFF
FA000-FAFFF
1FA000-1FAFFF
F9000-F9FFF
1F9000-1F9FFF
F8000-F8FFF
1F8000-1F8FFF
F0000-F7FFF
1F0000-1F7FFF
E8000-EFFFF
1E8000-1EFFFF
E0000-E7FFF
1E0000-1E7FFF
D8000-DFFFF
1D8000-1DFFFF
D0000-D7FFF
1D0000-1D7FFF
C8000-CFFFF
1C8000-1CFFFF
C0000-C7FFF
1C0000-1C7FFF
B8000-BFFFF
1B8000-1BFFFF
B0000-B7FFF
1B0000-1B7FFF
A8000-AFFFF
1A8000-1AFFFF
A0000-A7FFF
1A0000-1A7FFF
98000-9FFFF
198000-19FFFF
90000-97FFF
190000-197FFF
88000-8FFFF
188000-18FFFF
80000-87FFF
180000-187FFF
78000-7FFFF
178000-17FFFF
70000-77FFF
170000-177FFF
68000-6FFFF
168000-16FFFF
60000-67FFF
160000-167FFF
58000-5FFFF
158000-15FFFF
50000-57FFF
150000-157FFF
48000-4FFFF
148000-14FFFF
40000-47FFF
140000-147FFF
38000-3FFFF
138000-13FFFF
30000-37FFF
130000-137FFF
28000-2FFFF
128000-12FFFF
20000-27FFF
120000-127FFF
18000-1FFFF
118000-11FFFF
10000-17FFF
110000-117FFF
08000-0FFFF
108000-10FFFF
00000-07FFF
100000-107FFF
This column continues on next page
Size
(KW)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
8 Mbit
16 Mbit
32 Mbit
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
F8000-FFFFF
0F8000-0FFFFF
F0000-F7FFF
0F0000-0F7FFF
E8000-EFFFF 0E8000-0EFFFF
E0000-E7FFF
0E0000-0E7FFF
D8000-DFFFF 0D8000-0DFFFF
D0000-D7FFF 0D0000-0D7FFF
C8000-CFFFF 0C8000-0CFFFF
This column continues on next page
39
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
16-Mbit and 32-Mbit Word-Wide Memory Addressing (Continued)
Top Boot
Size
(KW)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
40
16 Mbit
Bottom Boot
32 Mbit
Size
(KW)
16 Mbit
32 Mbit
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4-Mbit and 8-Mbit Word-Wide Memory Addressing
Top Boot
Size
(KW)
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
Size
(KW)
4 Mbit
3F000-3FFFF
3E000-3EFFF
3D000-3DFFF
3C000-3CFFF
3B000-3BFFF
3A000-3AFFF
39000-39FFF
38000-38FFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
3UHOLPLQDU\
Bottom Boot
7F000-7FFFF
7E000-7EFFF
7D000-7DFFF
7C000-7CFFF
7B000-7BFFF
7A000-7AFFF
79000-79FFF
78000-78FFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
4 Mbit
8 Mbit
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
41
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot
Size
(KW)
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
42
16 Mbit
FF000-FFFFF
FE000-FEFFF
FD000-FDFFF
FC000-FCFFF
FB000-FBFFF
FA000-FAFFF
F9000-F9FFF
F8000-F8FFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
32 Mbit
Bottom Boot
64 Mbit
1FF000-1FFFFF
3FF000-3FFFFF
1FE000-1FEFFF
3FE000-3FEFFF
1FD000-1FDFFF
3FD000-3FDFFF
1FC000-1FCFFF
3FC000-3FCFFF
1FB000-1FBFFF
3FB000-3FBFFF
1FA000-1FAFFF
3FA000-3FAFFF
1F9000-1F9FFF
3F9000-3F9FFF
1F8000-1F8FFF
3F8000-3F8FFF
1F0000-1F7FFF
3F0000-3F7FFF
1E8000-1EFFFF
3E8000-3EFFFF
1E0000-1E7FFF
3E0000-3E7FFF
1D8000-1DFFFF
3D8000-3DFFFF
1D0000-1D7FFF
3D0000-3D7FFF
1C8000-1CFFFF
3C8000-3CFFFF
1C0000-1C7FFF
3C0000-3C7FFF
1B8000-1BFFFF
3B8000-3BFFFF
1B0000-1B7FFF
3B0000-3B7FFF
1A8000-1AFFFF
3A8000-3AFFFF
1A0000-1A7FFF
3A0000-3A7FFF
198000-19FFFF
398000-39FFFF
190000-197FFF
390000-397FFF
188000-18FFFF
388000-38FFFF
180000-187FFF
380000-387FFF
178000-17FFFF
378000-37FFFF
170000-177FFF
370000-377FFF
168000-16FFFF
368000-36FFFF
160000-167FFF
360000-367FFF
158000-15FFFF
358000-35FFFF
150000-157FFF
350000-357FFF
148000-14FFFF
348000-34FFFF
140000-147FFF
340000-347FFF
138000-13FFFF
338000-33FFFF
130000-137FFF
330000-337FFF
128000-12FFFF
328000-32FFFF
120000-127FFF
320000-327FFF
118000-11FFFF
318000-31FFFF
110000-117FFF
310000-317FFF
108000-10FFFF
308000-30FFFF
100000-107FFF
300000-307FFF
0F8000-0FFFFF
2F8000-2FFFFF
0F0000-0F7FFF
2F0000-2F7FFF
0E8000-0EFFFF
2E8000-2EFFFF
0E0000-0E7FFF
2E0000-2E7FFF
0D8000-0DFFFF
2D8000-2DFFFF
0D0000-0D7FFF
2D0000-2D7FFF
0C8000-0CFFFF
2C8000-2CFFFF
0C0000-0C7FFF
2C0000-2C7FFF
0B8000-0BFFFF
2B8000-2BFFFF
0B0000-0B7FFF
2B0000-2B7FFF
This column continues on next page
Size
(KW)
16 Mbit
32 Mbit
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
64 Mbit
3F8000-3FFFFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
This column continues on next page
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing (Continued)
Top Boot
Size
(KW)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
3UHOLPLQDU\
16 Mbit
32 Mbit
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
Bottom Boot
64 Mbit
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-21FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
This column continues on next page
Size
(KW)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16 Mbit
32 Mbit
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
F8000-FFFFF
F8000-FFFFF
F0000-F7FFF
F0000-F7FFF
E8000-EFFFF
E8000-EFFFF
E0000-E7FFF
E0000-E7FFF
D8000-DFFFF
D8000-DFFFF
D0000-D7FFF
D0000-D7FFF
C8000-CFFFF
C8000-CFFFF
This column continues on next page
64 Mbit
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
F8000-FFFFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
43
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing (Continued)
Top Boot
Size
(KW)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
44
16 Mbit
32 Mbit
Bottom Boot
64 Mbit
Size
(KW)
16 Mbit
32 Mbit
64 Mbit
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Appendix D Byte-Wide Memory Map Diagrams
8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing
Top Boot
Size (KB)
8 Mbit
8
8
8
8
8
8
8
8
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
FE000-FFFFF
FC000-FDFFF
FA000-FBFFF
F8000-F9FFF
F6000-F7FFF
F4000-F5FFF
F2000-F3FFF
F0000-F1FFF
E0000-EFFFF
D0000-DFFFF
C0000-CFFFF
B0000-BFFFF
A0000-AFFFF
90000-9FFFF
80000-8FFFF
70000-7FFFF
60000-6FFFF
50000-5FFFF
40000-4FFFF
30000-3FFFF
20000-2FFFF
10000-1FFFF
00000-0FFFF
3UHOLPLQDU\
Bottom Boot
16 Mbit
1FE000-1FFFFF
1FC000-1FDFFF
1FA000-1FBFFF
1F8000-1F9FFF
1F6000-1F7FFF
1F4000-1F5FFF
1F2000-1F3FFF
1F0000-1F1FFF
1E0000-1EFFFF
1D0000-1DFFFF
1C0000-1CFFFF
1B0000-1BFFFF
1A0000-1AFFFF
190000-19FFFF
180000-18FFFF
170000-17FFFF
160000-16FFFF
150000-15FFFF
140000-14FFFF
130000-13FFFF
120000-12FFFF
110000-11FFFF
100000-10FFFF
0F0000-0FFFFF
0E0000-0EFFFF
0D0000-0DFFFF
0C0000-0CFFFF
0B0000-0BFFFF
0A0000-0AFFFF
090000-09FFFF
080000-08FFFF
070000-07FFFF
060000-06FFFF
050000-05FFFF
040000-04FFFF
030000-03FFFF
020000-02FFFF
010000-01FFFF
000000-00FFFF
This column continues on next page
Size (KB)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
8 Mbit
16 Mbit
1F0000-1FFFFF
1E0000-1EFFFF
1D0000-1DFFFF
1C0000-1CFFFF
1B0000-1BFFFF
1A0000-1AFFFF
190000-19FFFF
This column continues on next page
45
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
8-Mbit and 16-Mbit Byte-Wide Memory Addressing (Continued)
Top Boot
Size (KB)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
46
8 Mbit
Bottom Boot
16 Mbit
Size (KB)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
8
8
8
8
8
8
8
8
8 Mbit
16 Mbit
F0000-FFFFF
E0000-EFFFF
D0000-DFFFF
C0000-CFFFF
B0000-BFFFF
A0000-AFFFF
90000-9FFFF
80000-8FFFF
70000-7FFFF
60000-6FFFF
50000-5FFFF
40000-4FFFF
30000-3FFFF
20000-2FFFF
10000-1FFFF
0E000-0FFFF
0C000-0DFFF
0A000-0BFFF
08000-09FFF
06000-07FFF
04000-05FFF
02000-03FFF
00000-01FFF
180000-18FFFF
170000-17FFFF
160000-16FFFF
150000-15FFFF
140000-14FFFF
130000-13FFFF
120000-12FFFF
110000-11FFFF
100000-10FFFF
0F0000-0FFFFF
0E0000-0EFFFF
0D0000-0DFFFF
0C0000-0CFFFF
0B0000-0BFFFF
0A0000-0AFFFF
090000-09FFFF
080000-08FFFF
070000-07FFFF
060000-06FFFF
050000-05FFFF
040000-04FFFF
030000-03FFFF
020000-02FFFF
010000-01FFFF
00E000-00FFFF
00C000-00DFFF
00A000-00BFFF
008000-009FFF
006000-007FFF
004000-005FFF
002000-003FFF
000000-001FFF
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4-Mbit Byte-Wide Memory Addressing
Top Boot
Bottom Boot
Size
(KB)
4 Mbit
Size
(KB)
4 Mbit
8
8
8
8
8
8
8
8
64
64
64
64
64
64
64
7E000-7FFFF
7C000-7DFFF
7A000-7BFFF
78000-79FFF
76000-77FFF
74000-75FFF
72000-73FFF
70000-71FFF
60000-6FFFF
50000-5FFFF
40000-4FFFF
30000-3FFFF
20000-2FFFF
10000-1FFFF
00000-0FFFF
64
64
64
64
64
64
64
8
8
8
8
8
8
8
8
70000-7FFFF
60000-6FFFF
50000-5FFFF
40000-4FFFF
30000-3FFFF
20000-2FFFF
10000-1FFFF
0E000-0FFFF
0C000-0DFFF
0A000-0BFFF
08000-09FFF
06000-07FFF
04000-05FFF
02000-03FFF
00000-01FFF
3UHOLPLQDU\
47
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Appendix E Program and Erase Flowcharts
Figure 10. Program Flowchart
Start
Write 40H
Bus Operation
Command
Write
Program Setup
Write
Program
Program Address/Data
Data = 40H
Data = Data to Program
Addr = Location to Program
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Read
Read Status Register
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Repeat for subsequent programming operations.
No
SR.7 = 1?
Comments
SR Full Status Check can be done after each program or after a sequence of
program operations.
Yes
Write FFH after the last program operation to reset device to read array mode.
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
1
SR.3 =
0
VPP Range Error
Programming Error
0
1
SR.1 =
Comments
Standby
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4
1 = VPP Program Error
Standby
Check SR.1
1 = Attempted Program to
Locked Block - Program
Aborted
1
SR.4 =
Command
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
Attempted Program to
Locked Block - Aborted
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases where multiple bytes are programmed before full status is checked.
0
Program Successful
If an error is detected, clear the status register before attempting retry or other
error recovery.
0580_E1
48
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 11. Program Suspend/Resume Flowchart
Start
Bus
Operation
Command
Write
Program
Suspend
Data = B0H
Addr = X
Write
Read Status
Data = 70H
Addr = X
Comments
Write B0H
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Write 70H
Read
Read Status Register
0
SR.7 =
1
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.2
1 = Program Suspended
0 = Program Completed
Write
0
SR.2 =
Read Array
Program Completed
Read array data from block
other than the one being
programmed.
Read
1
Write FFH
Write
Data = FFH
Addr = X
Program
Resume
Data = D0H
Addr = X
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Program Resumed
Read Array Data
0580_E2
3UHOLPLQDU\
49
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 12. Block Erase Flowchart
Start
Bus Operation
Write 20H
Write D0H and
Block Address
Command
Write
Erase Setup
Write
Erase Confirm
Data = D0H
Addr = Within Block to Be
Erased
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Read
Read Status Register
Suspend
Erase Loop
0
SR.7 =
No
Suspend Erase
Comments
Data = 20H
Addr = Within Block to Be
Erased
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Yes
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase or after a sequence of
block erasures.
1
Full Status
Check if Desired
Write FFH after the last write operation to reset device to read array mode.
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
1
SR.3 =
0
1
Command Sequence
Error
0
1
SR.5 =
Block Erase Error
Comments
Standby
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4,5
Both 1 = Command Sequence
Error
Standby
Check SR.5
1 = Block Erase Error
Standby
Check SR.1
1 = Attempted Erase of
Locked Block - Erase Aborted
VPP Range Error
SR.4,5 =
Command
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
0
1
SR.1 =
0
Attempted Erase of
Locked Block - Aborted
SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases
where multiple bytes are erased before full status is checked.
If an error is detected, clear the status register before attempting retry or other
error recovery.
Block Erase
Successful
0580_E3
50
3UHOLPLQDU\
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 13. Erase Suspend/Resume Flowchart
Start
Bus Operation
Command
Comments
Write
Erase Suspend
Data = B0H
Addr = X
Write
Read Status
Data = 70H
Addr = X
Write B0H
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Write 70H
Read
Read Status Register
0
SR.7 =
1
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.6
1 = Erase Suspended
0 = Erase Completed
Write
0
SR.6 =
Read Array
Erase Completed
Read array data from block
other than the one being
erased.
Read
1
Write FFH
Write
Data = FFH
Addr = X
Erase Resume
Data = D0H
Addr = X
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Erase Resumed
Read Array Data
0580_E4
3UHOLPLQDU\
51
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