H7N0401LD, H7N0401LS, H7N0401LM Silicon N Channel MOS FET High Speed Power Switching REJ03G1129-0500 (Previous: ADE-208-1527C) Rev.5.00 Apr 07, 2006 Features • Low on-resistance RDS (on) = 3.1 mΩ typ. • 4.5 V gate drive devices • High Speed Switching Outline RENESAS Package code: PRSS0004AE-A (Package name: LDPAK (L) ) RENESAS Package code: PRSS0004AE-B (Package name: LDPAK (S)-(1) ) 4 4 1. Gate 2. Drain 3. Source 4. Drain 1 1 2 2 3 3 H7N0401LD H7N0401LS RENESAS Package code: PRSS0004AE-C (Package name: LDPAK (S)-(2) ) D 4 G 1 2 3 H7N0401LM Rev.5.00 Apr 07, 2006 page 1 of 8 S H7N0401LD, H7N0401LS, H7N0401LM Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Symbol VDSS Value 40 Unit V VGSS ID ±20 95 V A 380 95 A A Note 1 Drain peak current Body to drain diode reverse drain current ID (pulse) IDR Note 3 Avalanche current Avalanche energy IAP Note 3 EAR 65 560 A mJ Channel dissipation Channel temperature Pch Tch Note 2 100 150 W °C –55 to +150 °C Storage temperature Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at Tc = 25°C 3. Value at Tch = 25°C, Rg ≥ 50 Ω Tstg Electrical Characteristics (Ta = 25°C) Item Symbol Min Typ Max Unit V (BR) DSS IDSS 40 — — — — 10 V µA ID = 10 mA, VGS = 0 VDS = 40 V, VGS = 0 Gate to source leak current Gate to source cutoff voltage IGSS VGS (off) — 1.5 — — ±0.1 2.5 µA V VGS = ±20 V, VDS = 0 Note 4 VDS = 10 V, ID = 1 mA Forward transfer admittance Static drain to source on state resistance |yfs| RDS (on) 60 — 100 3.1 — 4.2 S mΩ ID = 47.5 A, VDS = 10 V Note 4 ID = 47.5 A, VGS = 10 V Input capacitance Ciss — — 4.8 9300 7.0 — mΩ pF Output capacitance Reverse transfer capacitance Coss Crss — — 1300 670 — — pF pF ID = 47.5 A, VGS = 4.5 V VDS = 10 V VGS = 0 f = 1 MHz Total gate charge Gate to source charge Qg Qgs — — 160 36 — — nC nC Gate to drain charge Turn-on delay time Qgd td (on) — — 40 45 — — nC ns Rise time Turn-off delay time tr td (off) — — 270 130 — — ns ns Fall time Body to drain diode forward voltage tf VDF — — 85 0.95 — — ns V trr — 50 — ns Drain to source breakdown voltage Zero gate voltage drain current Body to drain diode reverse recovery time Note: 4. Pulse test Rev.5.00 Apr 07, 2006 page 2 of 8 Test Conditions Note 4 VDD = 25 V VGS = 10 V ID = 95 A VGS = 10 V ID = 47.5 A RL = 0.63 Ω Rg = 4.7 Ω IF = 95 A, VGS = 0 IF = 95 A, VGS = 0 diF/dt = 100 A/µs Note 4 H7N0401LD, H7N0401LS, H7N0401LM Main Characteristics Maximum Safe Operation Area Power vs. Temperature Derating 1000 10 ID (A) 300 120 Drain Current Channel Dissipation Pch (W) 160 80 40 10 100 1m 30 3 Operation in this area is 1 limited by RDS(on) 50 100 0.1 0.1 200 150 Case Temperature 200 10 V 10 4V 100 VDS (V) 160 120 80 Drain Current 120 3.5 V 40 80 Tc = 75°C 40 25°C VGS = 3 V –25°C 0 0 0 2 4 6 Drain to Source Voltage 8 0 10 Pulse Test 0.4 0.3 0.2 ID = 50 A 0.1 20 A 10 A 0 0 4 8 12 16 20 Gate to Source Voltage VGS (V) Rev.5.00 Apr 07, 2006 page 3 of 8 2 3 5 4 VGS (V) Static Drain to Source on State Resistance vs. Drain Current Drain to Source on State Resistance RDS(on) (mΩ) 0.5 1 Gate to Source Voltage VDS (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage Drain to Source Saturation Voltage VDS(on) (V) 30 VDS = 10 V Pulse Test ID (A) ID (A) 3 200 Pulse Test 4.5 V 1 Typical Transfer Characteristics 6V 160 0.3 Drain to Source Voltage Tc (°C) Typical Output Characteristics Drain Current PW = 10 ms (1shot) Ta = 25°C 0 s s DC Operation (Tc = 25°C) 10 0.3 0 0µ µs 100 Pulse Test 30 10 VGS = 4.5 V 3 10 V 1 0.3 0.1 1 3 10 30 100 300 Drain Current ID (A) 1000 H7N0401LD, H7N0401LS, H7N0401LM Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Drain to Source on State Resistance RDS(on) (mΩ) Static Drain to Source on State Resistance vs. Temperature 10 Pulse Test 8 ID = 10, 20, 50 A 6 VGS = 4.5 V 4 10, 20, 50 A 2 10 V 0 –50 0 50 100 Case Temperature 150 200 1000 300 Tc = –25°C 100 25°C 30 75°C 10 3 VDS = 10 V Pulse Test 1 1 3 Tc (°C) Capacitance C (pF) Reverse Recovery Time trr (ns) 200 100 50 20 10 20 Reverse Drain Current 3000 Coss 1000 Crss 300 VGS = 0 f = 1 MHz 50 100 0 10 VGS VDS 40 12 VDD = 10 V 25 V 40 V 20 8 VDD = 40 V 25 V 10 V 0 0 40 80 120 160 Gate Charge Qg (nc) Rev.5.00 Apr 07, 2006 page 4 of 8 4 0 200 1000 500 Switching Time t (ns) 16 VGS (V) 20 ID = 95 A 80 30 40 50 Switching Characteristics Gate to Source Voltage VDS (V) Drain to Source Voltage 100 20 Drain to Source Voltage VDS (V) IDR (A) Dynamic Input Characteristics 60 1000 Ciss 10000 100 10 300 30000 di / dt = 100 A / µs 500 VGS = 0, Ta = 25°C 5 100 Typical Capacitance vs. Drain to Source Voltage 1000 2 30 Drain Current ID (A) Body to Drain Diode Reverse Recovery Time 1 10 VGS = 10 V, VDD = 30 V PW = 5 µs, duty ≤ 1 % Rg = 4.7 Ω 200 100 td(off) tf 50 td(on) tr 20 10 0.1 0.3 1 3 Drain Current 10 30 ID (A) 100 H7N0401LD, H7N0401LS, H7N0401LM Maximum Avalanche Energy vs. Channel Temperature Derating Repetitive Avalanche Energy EAR (mJ) Reverse Drain Current IDR (A) Reverse Drain Current vs. Source to Drain Voltage 200 10 V 160 120 VGS = 0, –5 V 5V 80 40 Pulse Test 0 0 0.4 0.8 1.2 1.6 Source to Drain Voltage 2.0 800 IAP = 65 A VDD = 25 V duty < 0.1 % Rg ≥ 50 Ω 640 480 320 160 0 25 VSD (V) 50 75 100 125 150 Channel Temperature Tch (°C) Normalized Transient Thermal Impedance γ s (t) Normalized Transient Thermal Impedance vs. Pulse Width 3 Tc = 25°C 1 D=1 0.5 0.3 0.2 0.1 θch – c (t) = γ s (t) • θch – c θch – c = 1.25°C/W, Tc = 25°C 0.1 0.05 PDM 0.02 0.03 0.0 1s 1 t ho D= lse PW pu 0.01 10 µ PW T T 100 µ 1m 10 m 100 m 10 1 Pulse Width PW (S) Avalanche Test Circuit VDS Monitor Avalanche Waveform L EAR = 1 • L • IAP2 • 2 VDSS VDSS – VDD IAP Monitor Rg V(BR)DSS IAP D.U.T VDD VDS ID Vin 15 V 50 Ω 0 Rev.5.00 Apr 07, 2006 page 5 of 8 VDD H7N0401LD, H7N0401LS, H7N0401LM Switching Time Test Circuit Waveform 90% Vout Monitor Vin Monitor D.U.T. Rg Vin Vout Vin 10 V VDS = 30 V 10% 10% 90% td(on) Rev.5.00 Apr 07, 2006 page 6 of 8 10% RL tr 90% td(off) tf H7N0401LD, H7N0401LS, H7N0401LM Package Dimensions RENESAS Code PRSS0004AE-A MASS[Typ.] 1.40g 4.44 ± 0.2 1.3 ± 0.15 1.3 ± 0.2 1.37 ± 0.2 0.76 ± 0.1 2.54 ± 0.5 2.54 ± 0.5 JEITA Package Code SC-83 RENESAS Code PRSS0004AE-B 2.49 ± 0.2 11.0 ± 0.5 0.2 0.86 +– 0.1 Package Name LDPAK(S)-(1) Unit: mm 10.2 ± 0.3 8.6 ± 0.3 11.3 ± 0.5 0.3 10.0 +– 0.5 Previous Code LDPAK(L) / LDPAK(L)V Previous Code LDPAK(S)-(1) / LDPAK(S)-(1)V 0.4 ± 0.1 MASS[Typ.] 1.30g (1.5) 10.0 Rev.5.00 Apr 07, 2006 page 7 of 8 2.54 ± 0.5 0.4 ± 0.1 0.3 3.0 +– 0.5 2.54 ± 0.5 0.2 0.86 +– 0.1 7.8 7.0 2.49 ± 0.2 0.2 0.1 +– 0.1 1.37 ± 0.2 1.3 ± 0.2 7.8 6.6 1.3 ± 0.15 + 0.3 – 0.5 8.6 ± 0.3 (1.5) (1.4) 4.44 ± 0.2 10.2 ± 0.3 Unit: mm 1.7 JEITA Package Code (1.4) Package Name LDPAK(L) 2.2 H7N0401LD, H7N0401LS, H7N0401LM JEITA Package Code RENESAS Code PRSS0004AE-C Previous Code LDPAK(S)-(2) / LDPAK(S)-(2)V MASS[Typ.] 1.35g 7.8 6.6 (2.3) 10.0 2.49 ± 0.2 7.8 7.0 1.3 ± 0.15 + 0.3 – 0.5 8.6 ± 0.3 (1.5) (1.4) 4.44 ± 0.2 10.2 ± 0.3 Unit: mm 1.7 Package Name LDPAK(S)-(2) 0.2 0.1 +– 0.1 2.2 1.37 ± 0.2 2.54 ± 0.5 0.2 0.86 +– 0.1 2.54 ± 0.5 0.4 ± 0.1 0.3 5.0 +– 0.5 1.3 ± 0.2 Ordering Information Part Name H7N0401LD-E H7N0401LSTL-E Quantity 500 pcs 1000 pcs Shipping Container Box (Conductive Sack) Taping H7N0401LMTL-E 1000 pcs Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.5.00 Apr 07, 2006 page 8 of 8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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