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Hitachi 16-Bit Single-Chip Microcomputer H8S/2169F-ZTAT™ H8S/2149F-ZTAT™ H8S/2169 HD64F2169 H8S/2149 HD64F2149 Hardware Manual ADE-602-190A Rev. 2.0 02/21/01 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Preface The H8S/2149 and H8S/2169 F-ZTAT™ comprises high-performance microcomputers with a 32bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen internal 16-bit general registers with a 32-bit configuration, and a concise and optimized instruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently. Single-power-supply flash memory (F-ZTAT™*) is available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. On-chip peripheral functions include a 16-bit free-running timer (FRT), 8-bit timer (TMR), watchdog timer (WDT), two PWM timers (PWM and PWMX), a serial communication interface (SCI, IrDA), I 2C bus interface (IIC), PS/2-compatible keyboard buffer controller, host interface (HIF:XBS and LPC), D/A converter (DAC), A/D converter (ADC), and I/O ports. An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer without CPU intervention. Use of the H8S/2149 and H8S/2169 F-ZTAT™ enables compact, high-performance systems to be implemented easily. The comprehensive PC-related interface functions and 16 × 8 matrix keyscan functions are ideal for applications such as notebook PC keyboard control and intelligent battery and power supply control. In particular, the provision of two on-chip host interfaces—a conventional X-BUS (ISA) interface and an LPC interface (a new standard)—provide flexible support for PC systems in a period of transition. This manual describes the hardware of the H8S/2149 and H8S/2169 F-ZTAT™. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set. This manual describes the hardware of the H8S/2149 and H8S/2169 F-ZTAT™. Although the H8S/2169 is not explicitly mentioned in Section 2 to 7 or Section 9 to 22, the descriptions in these Sections apply to both the H8S/2149 and H8S/2169. Note: * F-ZTAT™ (Flexible-ZTAT) is a trademark of Hitachi, Ltd. Main Revisions and Additions in this Edition Page Item All pages of this manual 2 to 6 Revision (See Manual for Details) Amendments due to introduction of the H8S/2169 1. Overview Table 1.1 Overview CPU: operating frequency, and arithmetic operations amended PWM: maximum carrier frequency amended PWMX: maximum carrier frequency amended A/D converter: minimum conversion time amended I/O ports: H8S/2169 added Packages: TFP-144 (H8S/2169) added Product lineup: amended 8 1.2 Internal Block Diagram Figure 1.1(b) Internal Block Diagram of H8S/2169 added 10 1.3.1 Pin Arrangement 11 1.3.2 Pin Functions in Each Table 1.2(a) H8S/2149 Pin Functions in Each Operating Operating Mode Mode Pin No.9 : Pin function of Flash memory programmer mode amended 16 to 21 1.3.2 Pin Functions in Each Table 1.2(b) H8S/2169 Pin Functions in Each Operating Operating Mode Mode 22 to 30 1.3.3 Pin Functions Figure 1.2(b) H8S/2169 Pin Arrangement added Table 1.3 Pin Functions Power (VCL), (VCCB) description amended Clock (X1), (X2) description amended Ports C to G description added TFP-144 pin function added All pages of section 2 Notes on TAS instruction added Notes on STM/LDM instruction added 32 2.1.1 Features High-speed operation amended 73 2.9.4 On-Chip Supporting Module Access Timing (Internal I/O Register 3) Added 78 3.2.2 System Control Register Address amended when bits 6 is 1 79 3.2.3 Bus Control Register Address amended when bits 1 and 0 are 1, respectively 83 3.4 Pin Function in Each Operating Mode Table 3.3 Pin Functions in Each Mode 3.5 Memory Map in Each Operating Mode Figure 3.1 H8S/2169 or H8S/2149 Memory Map in Each Operating Mode amended 84, 85 Ports C to G added Page Item Revision (See Manual for Details) 89 4.1.3 Exception Source and Table 4.2 Exception Vector Table Vector Table Internal interrupt address amended 98 5.1.2 Block Diagram Figure 5.1 Block Diagram of Interrupt Controller Names of Internal interrupt request amended 102 5.2.2 Interrupt Control Registers A to C Description amended (address break) 105 5.2.5 IRQ Status Register Bits 7 to 0: Note added 105, 106 5.2.6 Keyboard Matrix interrupt Mask Register Description and note amended 112 5.3.1 External Interrupt Description on IRQ6 pin added 114 5.3.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source name amended (address break (PC break)) 119 5.5.1 Interrupt Control Modes and Interrupt Operation Description amended (address break) 120 Table 5.6 Interrupt Selected in Each Interrupt Control Mode Description amended (address break) 122 5.5.2 Interrupt Control Mode 0 123 Description amended (address break) Figure 5.8 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Interrupt name amended (IBFI3) 124, 125 5.5.3 Interrupt Control Mode 1 126 Description amended (address break) Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 Interrupt name amended (IBFI3) 129 5.5.5 Interrupt Response Times Table 5.8 Interrupt Response Times 139 6.2.2.Wait State Control Register Bits 7 and 6 description amended 143 6.3.4 I/O Select Signal Table 6.4 IOS Signal Output Range Settings Number of wait states until execution instruction ends amended Address amended when IOS1 and IOS0 are 1, respectively 155 6.4.5 Wait Control Figure 6.13 Example of Wait State Insertion Timing HWR, LWR timing amended Page Item Revision (See Manual for Details) 189 8.1 Overview Amendments due to introduction of the H8S/2169 Description added 253, 254 8.12.3 Pin Functions Table 8.24 Port B Pin Functions PB1 and PB0 : Table amended 255 to 256 8.13 Additional Overview for H8S/2169 Added 256 to 261 8.14 Ports C, D Added 261 to 265 8.15 Ports E, F Added 266 to 269 8.16 Port G Added 271 9.1.1 Features Carrier frequency amended 273 9.1.4 Register Configuration Table 9.2 PWM Timer Module Registers 275 Note 2 added 9.2.1 PWM Register Select Table 9.3 Resolution, PWM Conversion Period, and Carrier Frequency when φ = 10 MHz Completely amended due to changes of the system clock 285 10.1.4 Register Configuration Table 10.2 Register Configuration 287 10.2.2 D/A Data Registers A and B Address amended when bit 1 is 1 326 11.6 Usage Notes Figure 11.21 Contention between OCRAR/OCRAF Write and Compare-Match Added 342 12.2.6 Serial/Timer Control Bit 3: Description amended Register 352 to 354 12.3.6 Input Capture Operation Added 377 13.3.1 PWM Decoding Table 13.4 Examples of TCORB Settings Note 2 amended φ = 12 MHz or more deleted Figure 13.2 Timing Chart for PWM Decoding IHI signal amended 379 13.3.3 Measurement of 8Bit Timer Divided Waveform Period External reset signal description amended 396, 398, 399 14.2.2 Timer Control/Status Bit 7: Note added Register Bits 2 to 0: Overflow Period amended 406 to 407 14.5.6 OVF Flag Clear Condition Added 410 15.1.1 Features Capability of transmit and receive clock output Added Page Item Revision (See Manual for Details) 428 to 432 15.2.8 Bit Rate Register Note added Table 15.3 BRR Settings for Various Bit Rates φ = 12 MHz or more deleted Table 15.4 BRR Settings for Various Bit Rates φ = 16 MHz or more deleted Table 15.5 Maximum Bit Rate for Each Frequency φ = 12 MHz or more deleted Table 15.6 Maximum Bit Rate with External Clock Input φ = 12 MHz or more deleted Table 15.7 Maximum Bit Rate with External Clock Input φ = 12 MHz or more deleted 449 15.3.2 Operation in Asynchronous Mode Figure 15.8 Example of SCI Operation in Reception 15.3.3 Multiprocessor Communication Function Figure 15.10 Sample Multiprocessor Serial Transmission Flowchart Amended (Stop bit) Amended 469 15.3.5 IrDA Operation Table 15.12 Bit IrCKS2 to IrCKS0 Settings φ = 12 MHz or more deleted 2 482 16.2.1 I C Bus Data Register TDRE flag: Description amended when TDRE is 1 487 16.2.4 I2C Bus Mode Register Bits 5 to 3: Transfer rate φ = 16 MHz or more deleted 489, 493 16.2.5 I2C Bus Control Register Bits 7: Description amended when ICE is 0 499 2 16.2.6 I C Bus Status Register Bits 1: Description amended when IRIC is 1 Bit 0: Description added "When writing to this bit, ...bit-manipulation instructions." 501 16.2.7 Serial/Timer Control Bit 3: Description amended Register 505 16.3.1 I2C Bus Data Format Figure 16.4 Formatless added 506 to 508 16.3.2 Master Transmit Operation Completely amended 508 to 510 16.3.3 Master Receive Operation Completely amended 517 16.3.7 Automatic Switching Description on preconditions amended (formatless from Formatless Mode to operation) I 2C Bus Format Page Item Revision (See Manual for Details) 520 16.3.10 Sample Flowcharts Figure 16.14 Flowchart for Master Transmit Mode Completely amended 521 Figure 16.15 Flowchart for Master Receive Mode Completely amended 523, 524 16.3.11 Initialization of Internal State Notes on Initialization: Description amended 526 16.4 Usage Notes Table 16.7 Permissible SCL Rise Time Values φ = 16 MHz or more deleted Table16.8 I2C Bus Timing 527 φ = 16 MHz or more deleted 529, 530 Notes on start condition Issuance for Retransmission Notes on I2C Bus Interface Stop Condition Instruction Issuance added 538 17.2.4 Module Stop Control Added Register 557 18A.2.1 System Control Register Bit 1: Description amended 572 18A.5 Usage Note (2) Data contention on the host interface data bus (HDB) added 587 18B.2.3 Host Interface Control Registers 2 and 3 HICR2 bits 3 to 0: Description amended when IBFIE3 is set to 1 589 18B.2.4 LPC Channel 3 Address Register LADR3L bit 2: Description amended 596 to 603 18B.2.9 SERIRQ Control Registers Names of SERIRQ interrupt sources amended 610 18B.3.4 Host Interface Shutdown Function Table 18B.5 Scope of HIF Pin Shutdown CLKRUN I/O amended Note added 616 18B.4.1 IBF1, IBF2, IBF3, ERRI Table 18B.7 Receive Complete Interrupts are Error interrupt IBF3 description amended 618, 619 18B.5 Usage Note (3) added 627 20.1.1 Features Conversion time amended 634 20.2.3 A/D Control Register Bits 5 to 0: Description amended 645 20.6 Usage Notes Table 20.5 Analog Pin Ratings Permissible signal source impedance max. value amended Note added Page Item Revision (See Manual for Details) 649 20.6 Usage Notes Permissible Signal Source Impedance: Impedance value amended 651 21.1.1 Block Diagram Figure 21.1 Block Diagram of RAM Address amended 653 21.3.1 Example Mode Address amended when the RAME bit is cleared to 0 21.3.2 Single-Chip Mode Description amended 658 22.4.1 Features Programming/erase times: Amended 660 22.4.3 Flash Memory Operating Modes Figure 22.3 Flash Memory Mode Transitions 667 22.5.2 Flash Memory Control Register 2 Bits 6 to 2: Description amended 672 22.6.1 Boot Mode Figure 22.8 Boot Mode Execution Procedure Bit name amended (User mode ⇔ User program mode) Amended 673 Table 22.8 System Clock Frequencies for which Automatic Adjustment of the Chip Bit Rate is Possible System clock frequency amended 673, 674 On-Chip RAM Area Divisions in Boot Mode: Description amended Figure 22.10 RAM Areas in Boot Mode Amended 685 22.10.1 Programmer Mode Note added Setting 696 22.11 Flash Memory Description for PROM programmer amended Programming and Erasing Precautions 702 23.3.1 Connecting a Crystal Resonator Table 23.2 Damping Resistance Value φ = 12 MHz or more deleted Table 23.3 Crystal Resonator Parameters φ = 12 MHz or more deleted 704 23.3.2 External Clock Input Table 23.4 External Clock Input Conditions Vcc range amended 705 Table 23.5 External Clock Output Setting Delay Time Conditions amended 706 23.7 Subclock Input Circuit Table 23.6 Subclock Input Conditions Vcc range amended 707 23.9 Clock Selection Circuit Added Page Item Revision (See Manual for Details) 708 23.10 X1 and X2 Pins Added 710 24.1 Overview Table 24.1 The Chip's Internal States in Each Mode HIF: LPC added I/O: State amended in subsleep mode 713 24.1.1 Register Configuration Table 24.3 Power-Down State Registers 717 24.2.2 Low-Power Control Register Bits 3, 2 to 0 description amended 722 24.5.1 Module Stop Mode Table 24.4 MSTP Bits and Corresponding On-Chip Supporting Modules Note 2 added MSTP2 bit module amended 724 24.6.3 Setting Occillation Table 24.5 Oscillation Setting Time Settings Setting Time after Clearing φ = 12 MHz or more deleted Software Standby Mode Note amended 733 25.1 Absolute Maximum Ratings Table 25.1 Absolute Maximum Ratings Value amended Note added 734 to 739 25.2 DC Characteristics Completely amended 741 25.3.1 Clock Timing Table 25.5 Clock Timing Amendment due to condition change 743 745 25.3.2 Control Signal Timing Table 25.6 Control Signal Timing 25.3.3 Bus Timing Table 25.7 Bus Timing Amendment due to condition change Amendment due to condition change 752, 756 758 25.3.4 Timing of On-Chip Supporting Modules Table 25.8 Timing of On-Chip Supporting Modules Amendment due to condition change Table 25.9 Keyboard Buffer Controller Timing Amendment due to condition change 759 Table 25.10 I 2C Bus Timing Amendment due to condition change 760 Table 25.11 LPC Module Timing Amendment due to condition change 761 Figure 25.28 Host Interface(LPC) Timing LCLK timing amended Page Item Revision (See Manual for Details) 762, 763 25.4 A/D Conversion Characteristics Table 25.12 and Table 25.13 A/D Conversion Characteristics Amendment due to condition change Permissible, signal-source impedance value amended 763 764, 765 25.5 D/A Conversion Characteristics Table 25.14 D/A Conversion Characteristics 25.6 Flash Memory Characteristics Table25.15 Flash Memory Characteristics Amendment due to condition change Amendment due to condition change Notes 4 and 5 amended 766 25.7 Usage Note All pages of Appendix A 841 to 850 Completely amended Note on TAS instruction added Note on STM/LDM instruction added B.2 Amendments due to introduction of the H8S/2169 Page Item Revision (See Manual for Details) - B.3 Functions Registers amended H’FE35: LADR3L H’FE36, H’FE37: SIRQCR0, SIRQCR1 H’FE42: HICR2 H’FE80: HICR2 H’FEEB: ISR H’FF82, H’FF83: EBR1, EBR2 H’FF87: MSTPCRL H’FF88, H’FFD8: ICCR1, ICCR0 H’FF8F, H’FFDF: ICMR1, ICMR0 H’FFC4, SYSCR H’FFC6, BCR H’FE16: PGNOCR H’FE18: PENOCR H’FE19: PFNOCR H’FE1C: PCNOCR H’FE1D: PDNOCR H’FE46: PGODR H’FE47(R): PGPIN H’FE47(W): PGDDR H’FE48: PEODR H’FE49: PFODR H’FE4A(R): PEPIN H’FE4A(W): PEDDR H’FE4B(R): PFPIN H’FE4B(W): PFDDR H’FE4C: PCODR H’FE4D: PDODR H’FE4E(R): PCPIN H’FE4E(W): PCDDR H’FE4F(R): PDPIN H’FE4F(W): PDDDR 951 C. I/O Port Block Diagrams Figure C.2 Port 2 Block Diagram (Pins P20 to P23) amended 952 Figure C.3 Port 2 Block Diagram (Pins P24 to P26) amended 953 Figure C.4 Port 2 Block Diagram (Pin P27) amended Page Item 959 C. I/O Port Block Diagrams Figure C.10 Port 4 Block Diagram (Pin P42) amended 966 Figure C.17 Port 5 Block Diagram (Pin P52) amended 973 Figure C.25 Port 8 Block Diagram (Pin P80) amended 979 Figure C.31 Port 8 Block Diagram (Pin P86) amended 980 Figure C.32 Port 9 Block Diagram (Pin P90) amended 982 Figure C.34 Port 9 Block Diagram (Pins P93 to P95) amended 984 Figure C.36 Port 9 Block Diagram (Pin P97) amended 985 Figure C.37 Port A Block Diagram (Pins PA0, PA1) amended 986 Figure C.38 Port A Block Diagram (Pins PA2, PA3) amended 987 Figure C.39 Port A Block Diagram (Pins PA4 to PA7) amended 989 Figure C.41 Port B Block Diagram (Pins PB2, PB3) amended 991 Figure C.43 Ports C, D, E, F, G Block Diagram amended 993 Revision (See Manual for Details) D.1 Port States in Each Processing State Table D.1 I/O Port States in Each Processing State 995 F. Product Code Lineup Table F.1 Product Codes amended 998 G. Package Dimensions Figure G.3 Package Dimensions(TFP-144) added Ports C to G added Contents Section 1 1.1 1.2 1.3 Overview ........................................................................................................... Overview............................................................................................................................ Block Diagram................................................................................................................... Pin Arrangement and Functions ........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode................................................................ 1.3.3 Pin Functions........................................................................................................ Section 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 CPU ..................................................................................................................... Overview............................................................................................................................ 2.1.1 Features................................................................................................................. 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.3 Differences from H8/300 CPU............................................................................. 2.1.4 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... Address Space.................................................................................................................... Register Configuration ...................................................................................................... 2.4.1 Overview .............................................................................................................. 2.4.2 General Registers.................................................................................................. 2.4.3 Control Registers.................................................................................................. 2.4.4 Initial Register Values .......................................................................................... Data Formats...................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats.......................................................................................... Instruction Set.................................................................................................................... 2.6.1 Overview .............................................................................................................. 2.6.2 Instructions and Addressing Modes ..................................................................... 2.6.3 Table of Instructions Classified by Function........................................................ 2.6.4 Basic Instruction Formats..................................................................................... 2.6.5 Notes on Use of Bit-Manipulation Instructions.................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Addressing Mode.................................................................................................. 2.7.2 Effective Address Calculation.............................................................................. Processing States ............................................................................................................... 2.8.1 Overview .............................................................................................................. 2.8.2 Reset State ............................................................................................................ 2.8.3 Exception-Handling State .................................................................................... 2.8.4 Program Execution State ...................................................................................... 2.8.5 Bus-Released State ............................................................................................... 1 1 7 9 9 11 22 31 31 31 32 33 33 34 39 40 40 41 42 43 44 44 46 47 47 48 50 57 58 58 58 61 65 65 66 67 68 68 i 2.8.6 Power-Down State................................................................................................ 2.9 Basic Timing...................................................................................................................... 2.9.1 Overview .............................................................................................................. 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 2.9.3 On-Chip Supporting Module Access Timing (Internal I/O Register 1 and 2) ..... 2.9.4 On-Chip Supporting Module Access Timing (Interna I/O Register 3) ................ 2.9.5 External Address Space Access Timing............................................................... 2.10 Usage Note ........................................................................................................................ 2.10.1 TAS Instruction .................................................................................................... 2.10.2 STM/LDM Instruction.......................................................................................... 68 69 69 69 71 73 74 74 74 74 Section 3 3.1 3.2 3.3 3.4 3.5 MCU Operating Modes ................................................................................ 75 Overview............................................................................................................................ 75 3.1.1 Operating Mode Selection.................................................................................... 75 3.1.2 Register Configuration ......................................................................................... 76 Register Descriptions......................................................................................................... 76 3.2.1 Mode Control Register (MDCR).......................................................................... 76 3.2.2 System Control Register (SYSCR) ...................................................................... 77 3.2.3 Bus Control Register (BCR) ................................................................................ 79 3.2.4 Serial Timer Control Register (STCR)................................................................. 80 Operating Mode Descriptions............................................................................................ 82 3.3.1 Mode 1.................................................................................................................. 82 3.3.2 Mode 2.................................................................................................................. 82 3.3.3 Mode 3.................................................................................................................. 82 Pin Functions in Each Operating Mode............................................................................. 83 Memory Map in Each Operating Mode............................................................................. 83 Section 4 4.1 4.2 4.3 4.4 4.5 4.6 Exception Handling........................................................................................ Overview............................................................................................................................ 4.1.1 Exception Handling Types and Priority ............................................................... 4.1.2 Exception Handling Operation ............................................................................. 4.1.3 Exception Sources and Vector Table.................................................................... Reset .................................................................................................................................. 4.2.1 Overview .............................................................................................................. 4.2.2 Reset Sequence..................................................................................................... 4.2.3 Interrupts after Reset ............................................................................................ Interrupts............................................................................................................................ Trap Instruction ................................................................................................................. Stack Status after Exception Handling .............................................................................. Notes on Use of the Stack.................................................................................................. Section 5 5.1 ii 87 87 87 88 88 90 90 90 92 93 94 95 96 Interrupt Controller ........................................................................................ 97 Overview............................................................................................................................ 97 5.2 5.3 5.4 5.5 5.6 5.7 5.1.1 Features ................................................................................................................ 5.1.2 Block Diagram...................................................................................................... 5.1.3 Pin Configuration ................................................................................................. 5.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 5.2.1 System Control Register (SYSCR) ...................................................................... 5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)............................................ 5.2.3 IRQ Enable Register (IER) .................................................................................. 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 5.2.5 IRQ Status Register (ISR) .................................................................................... 5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR).......................................... 5.2.7 Keyboard Matrix Interrupt Mask Register A (KMIMRA) Wakeup Event Interrupt Mask Registr B (WUEMRB) ................................................................ 5.2.8 Address Break Control Register (ABRKCR)....................................................... 5.2.9 Break Address Registers A, B, C (BARA, BARB, BARC)................................. Interrupt Sources................................................................................................................ 5.3.1 External Interrupts................................................................................................ 5.3.2 Internal Interrupts ................................................................................................. 5.3.3 Interrupt Exception Vector Table......................................................................... Address Breaks.................................................................................................................. 5.4.1 Features ................................................................................................................ 5.4.2 Block Diagram...................................................................................................... 5.4.3 Operation .............................................................................................................. 5.4.4 Usage Notes.......................................................................................................... Interrupt Operation ............................................................................................................ 5.5.1 Interrupt Control Modes and Interrupt Operation ................................................ 5.5.2 Interrupt Control Mode 0...................................................................................... 5.5.3 Interrupt Control Mode 1...................................................................................... 5.5.4 Interrupt Exception Handling Sequence .............................................................. 5.5.5 Interrupt Response Times..................................................................................... Usage Notes ....................................................................................................................... 5.6.1 Contention between Interrupt Generation and Disabling..................................... 5.6.2 Instructions that Disable Interrupts ...................................................................... 5.6.3 Interrupts during Execution of EEPMOV Instruction.......................................... DTC Activation by Interrupt ............................................................................................. 5.7.1 Overview .............................................................................................................. 5.7.2 Block Diagram...................................................................................................... 5.7.3 Operation .............................................................................................................. Section 6 6.1 Bus Controller.................................................................................................. Overview............................................................................................................................ 6.1.1 Features ................................................................................................................ 6.1.2 Block Diagram...................................................................................................... 97 98 99 100 101 101 102 103 103 104 105 106 109 110 111 111 113 113 116 116 116 117 117 119 119 122 124 127 129 130 130 131 131 132 132 132 133 135 135 135 136 iii 6.2 6.3 6.4 6.5 6.6 6.7 6.1.3 Pin Configuration ................................................................................................. 6.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 6.2.1 Bus Control Register (BCR) ................................................................................ 6.2.2 Wait State Control Register (WSCR)................................................................... Overview of Bus Control................................................................................................... 6.3.1 Bus Specifications ................................................................................................ 6.3.2 Advanced Mode.................................................................................................... 6.3.3 Normal Mode........................................................................................................ 6.3.4 I/O Select Signal................................................................................................... Basic Bus Interface............................................................................................................ 6.4.1 Overview .............................................................................................................. 6.4.2 Data Size and Data Alignment ............................................................................. 6.4.3 Valid Strobes ........................................................................................................ 6.4.4 Basic Timing ........................................................................................................ 6.4.5 Wait Control ......................................................................................................... Burst ROM Interface ......................................................................................................... 6.5.1 Overview .............................................................................................................. 6.5.2 Basic Timing ........................................................................................................ 6.5.3 Wait Control ......................................................................................................... Idle Cycle........................................................................................................................... 6.6.1 Operation .............................................................................................................. 6.6.2 Pin States in Idle Cycle ........................................................................................ Bus Arbitration .................................................................................................................. 6.7.1 Overview .............................................................................................................. 6.7.2 Operation .............................................................................................................. 6.7.3 Bus Transfer Timing ............................................................................................ Section 7 7.1 7.2 iv 137 137 138 138 139 141 141 142 142 142 143 143 143 145 146 154 156 156 156 157 158 158 159 159 159 159 160 Data Transfer Controller .............................................................................. 161 Overview............................................................................................................................ 7.1.1 Features ................................................................................................................ 7.1.2 Block Diagram...................................................................................................... 7.1.3 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 7.2.1 DTC Mode Register A (MRA)............................................................................. 7.2.2 DTC Mode Register B (MRB) ............................................................................. 7.2.3 DTC Source Address Register (SAR) .................................................................. 7.2.4 DTC Destination Address Register (DAR) .......................................................... 7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 7.2.6 DTC Transfer Count Register B (CRB) ............................................................... 7.2.7 DTC Enable Registers (DTCER) ......................................................................... 7.2.8 DTC Vector Register (DTVECR) ........................................................................ 7.2.9 Module Stop Control Register (MSTPCR) .......................................................... 161 161 162 163 164 164 166 167 167 167 168 168 169 170 7.3 7.4 7.5 Operation ........................................................................................................................... 7.3.1 Overview .............................................................................................................. 7.3.2 Activation Sources................................................................................................ 7.3.3 DTC Vector Table ................................................................................................ 7.3.4 Location of Register Information in Address Space ............................................ 7.3.5 Normal Mode........................................................................................................ 7.3.6 Repeat Mode ........................................................................................................ 7.3.7 Block Transfer Mode............................................................................................ 7.3.8 Chain Transfer...................................................................................................... 7.3.9 Operation Timing ................................................................................................. 7.3.10 Number of DTC Execution States........................................................................ 7.3.11 Procedures for Using the DTC ............................................................................. 7.3.12 Examples of Use of the DTC................................................................................ Interrupts............................................................................................................................ Usage Notes ....................................................................................................................... Section 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 171 171 173 174 176 177 178 179 181 182 183 185 186 188 188 I/O Ports ............................................................................................................ 189 Overview............................................................................................................................ Port 1.................................................................................................................................. 8.2.1 Overview .............................................................................................................. 8.2.2 Register Configuration ......................................................................................... 8.2.3 Pin Functions in Each Mode ................................................................................ 8.2.4 MOS Input Pull-Up Function ............................................................................... Port 2.................................................................................................................................. 8.3.1 Overview .............................................................................................................. 8.3.2 Register Configuration ......................................................................................... 8.3.3 Pin Functions in Each Mode ................................................................................ 8.3.4 MOS Input Pull-Up Function ............................................................................... Port 3.................................................................................................................................. 8.4.1 Overview .................................................................................................................. 8.4.2 Register Configuration ......................................................................................... 8.4.3 Pin Functions in Each Mode ................................................................................ 8.4.4 MOS Input Pull-Up Function ............................................................................... Port 4.................................................................................................................................. 8.5.1 Overview .............................................................................................................. 8.5.2 Register Configuration ......................................................................................... 8.5.3 Pin Functions........................................................................................................ Port 5.................................................................................................................................. 8.6.1 Overview .............................................................................................................. 8.6.2 Register Configuration ......................................................................................... 8.6.3 Pin Functions........................................................................................................ Port 6.................................................................................................................................. 8.7.1 Overview .............................................................................................................. 189 195 195 196 198 199 200 200 202 204 205 207 207 208 210 211 212 212 212 213 217 217 217 219 220 220 v 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.7.2 Register Configuration ......................................................................................... 8.7.3 Pin Functions........................................................................................................ 8.7.4 MOS Input Pull-Up Function ............................................................................... Port 7.................................................................................................................................. 8.8.1 Overview .............................................................................................................. 8.8.2 Register Configuration ......................................................................................... 8.8.3 Pin Functions........................................................................................................ Port 8.................................................................................................................................. 8.9.1 Overview .............................................................................................................. 8.9.2 Register Configuration ......................................................................................... 8.9.3 Pin Functions........................................................................................................ Port 9.................................................................................................................................. 8.10.1 Overview .............................................................................................................. 8.10.2 Register Configuration ......................................................................................... 8.10.3 Pin Functions........................................................................................................ Port A................................................................................................................................. 8.11.1 Overview .............................................................................................................. 8.11.2 Register Configuration ......................................................................................... 8.11.3 Pin Functions........................................................................................................ 8.11.4 MOS Input Pull-Up Function ............................................................................... Port B ................................................................................................................................. 8.12.1 Overview .............................................................................................................. 8.12.2 Register Configuration ......................................................................................... 8.12.3 Pin Functions........................................................................................................ 8.12.4 MOS Input Pull-Up Function ............................................................................... Additional Overview for H8S/2169 .................................................................................. Ports C, D .......................................................................................................................... 8.14.1 Overview .............................................................................................................. 8.14.2 Register Configuration ......................................................................................... 8.14.3 Pin Functions........................................................................................................ 8.14.4 MOS Input Pull-Up Function ............................................................................... Ports E, F ........................................................................................................................... 8.15.1 Overview .............................................................................................................. 8.15.2 Register Configuration ......................................................................................... 8.15.3 Pin Functions........................................................................................................ 8.15.4 MOS Input Pull-Up Function ............................................................................... Port G................................................................................................................................. 8.16.1 Overview .............................................................................................................. 8.16.2 Register Configuration ......................................................................................... 8.16.3 Pin Functions........................................................................................................ 8.16.4 MOS Input Pull-Up Function ............................................................................... Section 9 vi 221 224 226 227 227 227 228 229 229 229 230 234 234 235 236 240 240 241 242 246 247 247 248 250 255 255 256 256 257 260 260 261 261 262 265 265 266 266 266 268 268 8-Bit PWM Timers ......................................................................................... 271 9.1 9.2 9.3 Overview............................................................................................................................ 9.1.1 Features ................................................................................................................ 9.1.2 Block Diagram...................................................................................................... 9.1.3 Pin Configuration ................................................................................................. 9.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 9.2.1 PWM Register Select (PWSL) ............................................................................. 9.2.2 PWM Data Registers (PWDR0 to PWDR15) ...................................................... 9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB).................... 9.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) ................. 9.2.5 Peripheral Clock Select Register (PCSR) ............................................................ 9.2.6 Port 1 Data Direction Register (P1DDR) ............................................................. 9.2.7 Port 2 Data Direction Register (P2DDR) ............................................................. 9.2.8 Port 1 Data Register (P1DR) ................................................................................ 9.2.9 Port 2 Data Register (P2DR) ................................................................................ 9.2.10 Module Stop Control Register (MSTPCR) .......................................................... Operation ........................................................................................................................... 9.3.1 Correspondence between PWM Data Register Contents and Output Waveform 271 271 272 273 273 274 274 276 276 277 278 278 279 279 279 280 281 281 Section 10 14-Bit PWM Timer ........................................................................................ 283 10.1 Overview............................................................................................................................ 10.1.1 Features ................................................................................................................ 10.1.2 Block Diagram...................................................................................................... 10.1.3 Pin Configuration ................................................................................................. 10.1.4 Register Configuration ......................................................................................... 10.2 Register Descriptions......................................................................................................... 10.2.1 PWM (D/A) Counter (DACNT) .......................................................................... 10.2.2 D/A Data Registers A and B (DADRA and DADRB)......................................... 10.2.3 PWM (D/A) Control Register (DACR)................................................................ 10.2.4 Module Stop Control Register (MSTPCR) .......................................................... 10.3 Bus Master Interface.......................................................................................................... 10.4 Operation ........................................................................................................................... 283 283 284 284 285 285 285 286 287 289 290 293 Section 11 16-Bit Free-Running Timer ......................................................................... 297 11.1 Overview............................................................................................................................ 11.1.1 Features ................................................................................................................ 11.1.2 Block Diagram...................................................................................................... 11.1.3 Input and Output Pins........................................................................................... 11.1.4 Register Configuration ......................................................................................... 11.2 Register Descriptions......................................................................................................... 11.2.1 Free-Running Counter (FRC)............................................................................... 11.2.2 Output Compare Registers A and B (OCRA, OCRB) ......................................... 11.2.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 297 297 298 299 300 301 301 301 302 vii 11.3 11.4 11.5 11.6 11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF) ............................... 11.2.5 Output Compare Register DM (OCRDM) ........................................................... 11.2.6 Timer Interrupt Enable Register (TIER) .............................................................. 11.2.7 Timer Control/Status Register (TCSR) ................................................................ 11.2.8 Timer Control Register (TCR) ............................................................................. 11.2.9 Timer Output Compare Control Register (TOCR) .............................................. 11.2.10 Module Stop Control Register (MSTPCR) .......................................................... Operation ........................................................................................................................... 11.3.1 FRC Increment Timing ........................................................................................ 11.3.2 Output Compare Output Timing .......................................................................... 11.3.3 FRC Clear Timing................................................................................................ 11.3.4 Input Capture Input Timing.................................................................................. 11.3.5 Timing of Input Capture Flag (ICF) Setting ........................................................ 11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB)................................ 11.3.7 Setting of FRC Overflow Flag (OVF).................................................................. 11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF.......................................... 11.3.9 ICRD and OCRDM Mask Signal Generation ...................................................... Interrupts............................................................................................................................ Sample Application ........................................................................................................... Usage Notes ....................................................................................................................... 303 304 304 306 309 311 313 314 314 315 316 316 318 319 320 320 321 322 322 323 Section 12 8-Bit Timers ..................................................................................................... 329 12.1 Overview............................................................................................................................ 12.1.1 Features ................................................................................................................ 12.1.2 Block Diagram...................................................................................................... 12.1.3 Pin Configuration ................................................................................................. 12.1.4 Register Configuration ......................................................................................... 12.2 Register Descriptions......................................................................................................... 12.2.1 Timer Counter (TCNT) ........................................................................................ 12.2.2 Time Constant Register A (TCORA) ................................................................... 12.2.3 Time Constant Register B (TCORB) ................................................................... 12.2.4 Timer Control Register (TCR) ............................................................................. 12.2.5 Timer Control/Status Register (TCSR) ................................................................ 12.2.6 Serial/Timer Control Register (STCR) ................................................................ 12.2.7 System Control Register (SYSCR) ...................................................................... 12.2.8 Timer Connection Register S (TCONRS)............................................................ 12.2.9 Input Capture Register (TICR) [TMRX Additional Function] ............................ 12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function]................... 12.2.11 Input Capture Registers R and F (TICRR, TICRF) [TMRX Additional Functions] ............................................................................. 12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function]..................... 12.2.13 Module Stop Control Register (MSTPCR) .......................................................... 12.3 Operation ........................................................................................................................... viii 329 329 330 331 332 333 333 334 335 335 339 342 343 343 344 344 345 345 346 347 12.3.1 TCNT Incrementation Timing.............................................................................. 12.3.2 Compare-Match Timing ....................................................................................... 12.3.3 TCNT External Reset Timing .............................................................................. 12.3.4 Timing of Overflow Flag (OVF) Setting.............................................................. 12.3.5 Operation with Cascaded Connection .................................................................. 12.3.6 Input Capture Operation ....................................................................................... 12.4 Interrupt Sources................................................................................................................ 12.5 8-Bit Timer Application Example ..................................................................................... 12.6 Usage Notes ....................................................................................................................... 12.6.1 Contention between TCNT Write and Clear........................................................ 12.6.2 Contention between TCNT Write and Increment ................................................ 12.6.3 Contention between TCOR Write and Compare-Match ...................................... 12.6.4 Contention between Compare-Matches A and B ................................................. 12.6.5 Switching of Internal Clocks and TCNT Operation............................................. 347 348 350 350 351 352 354 355 356 356 357 358 359 359 Section 13 Timer Connection ........................................................................................... 363 13.1 Overview............................................................................................................................ 13.1.1 Features ................................................................................................................ 13.1.2 Block Diagram...................................................................................................... 13.1.3 Input and Output Pins........................................................................................... 13.1.4 Register Configuration ......................................................................................... 13.2 Register Descriptions......................................................................................................... 13.2.1 Timer Connection Register I (TCONRI).............................................................. 13.2.2 Timer Connection Register O (TCONRO) .......................................................... 13.2.3 Timer Connection Register S (TCONRS)............................................................ 13.2.4 Edge Sense Register (SEDGR) ............................................................................ 13.2.5 Module Stop Control Register (MSTPCR) .......................................................... 13.3 Operation ........................................................................................................................... 13.3.1 PWM Decoding (PDC Signal Generation) .......................................................... 13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ..................... 13.3.3 Measurement of 8-Bit Timer Divided Waveform Period .................................... 13.3.4 IHI Signal and 2fH Modification ......................................................................... 13.3.5 IVI Signal Fall Modification and IHI Synchronization........................................ 13.3.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) 13.3.7 HSYNCO Output.................................................................................................. 13.3.8 VSYNCO Output.................................................................................................. 13.3.9 CBLANK Output.................................................................................................. 363 363 364 365 366 366 366 369 371 373 375 376 376 378 379 381 383 384 387 388 389 Section 14 Watchdog Timer (WDT) .............................................................................. 391 14.1 Overview............................................................................................................................ 14.1.1 Features ................................................................................................................ 14.1.2 Block Diagram...................................................................................................... 14.1.3 Pin Configuration ................................................................................................. 391 391 392 393 ix 14.2 14.3 14.4 14.5 14.1.4 Register Configuration.......................................................................................... Register Descriptions......................................................................................................... 14.2.1 Timer Counter (TCNT) ........................................................................................ 14.2.2 Timer Control/Status Register (TCSR) ................................................................ 14.2.3 System Control Register (SYSCR) ...................................................................... 14.2.4 Notes on Register Access ..................................................................................... Operation ........................................................................................................................... 14.3.1 Watchdog Timer Operation.................................................................................. 14.3.2 Interval Timer Operation...................................................................................... 14.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 14.3.4 RESO Signal Output Timing................................................................................ Interrupts............................................................................................................................ Usage Notes ....................................................................................................................... 14.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 14.5.2 Changing Value of CKS2 to CKS0...................................................................... 14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 14.5.4 System Reset by RESO Signal............................................................................. 14.5.5 Counter Value in Transitions between High-Speed Mode, Subactive Mode, and Watch Mode .................................................................................................. 14.5.6 OVF Flag Clear Condition ................................................................................... 394 394 394 395 399 400 401 401 402 403 404 404 405 405 405 405 406 406 407 Section 15 Serial Communication Interface (SCI, IrDA) ........................................ 409 15.1 Overview............................................................................................................................ 15.1.1 Features ................................................................................................................ 15.1.2 Block Diagram...................................................................................................... 15.1.3 Pin Configuration ................................................................................................. 15.1.4 Register Configuration ......................................................................................... 15.2 Register Descriptions......................................................................................................... 15.2.1 Receive Shift Register (RSR)............................................................................... 15.2.2 Receive Data Register (RDR) .............................................................................. 15.2.3 Transmit Shift Register (TSR).............................................................................. 15.2.4 Transmit Data Register (TDR) ............................................................................. 15.2.5 Serial Mode Register (SMR)................................................................................ 15.2.6 Serial Control Register (SCR).............................................................................. 15.2.7 Serial Status Register (SSR)................................................................................. 15.2.8 Bit Rate Register (BRR)....................................................................................... 15.2.9 Serial Interface Mode Register (SCMR) .............................................................. 15.2.10 Module Stop Control Register (MSTPCR) .......................................................... 15.2.11 Keyboard Comparator Control Register (KBCOMP) .......................................... 15.3 Operation ........................................................................................................................... 15.3.1 Overview .............................................................................................................. 15.3.2 Operation in Asynchronous Mode........................................................................ 15.3.3 Multiprocessor Communication Function............................................................ x 409 409 411 412 412 414 414 414 415 415 416 418 422 426 433 434 435 437 437 439 450 15.3.4 Operation in Synchronous Mode.......................................................................... 15.3.5 IrDA Operation .................................................................................................... 15.4 SCI Interrupts .................................................................................................................... 15.5 Usage Notes ....................................................................................................................... 458 467 470 471 Section 16 I2 C Bus Interface ............................................................................................. 475 16.1 Overview............................................................................................................................ 16.1.1 Features ................................................................................................................ 16.1.2 Block Diagram...................................................................................................... 16.1.3 Input/Output Pins.................................................................................................. 16.1.4 Register Configuration ......................................................................................... 16.2 Register Descriptions......................................................................................................... 16.2.1 I2C Bus Data Register (ICDR).............................................................................. 16.2.2 Slave Address Register (SAR) ............................................................................. 16.2.3 Second Slave Address Register (SARX).............................................................. 16.2.4 I2C Bus Mode Register (ICMR) ........................................................................... 16.2.5 I2C Bus Control Register (ICCR) ......................................................................... 16.2.6 I2C Bus Status Register (ICSR)............................................................................ 16.2.7 Serial/Timer Control Register (STCR) ................................................................ 16.2.8 DDC Switch Register (DDCSWR) ...................................................................... 16.2.9 Module Stop Control Register (MSTPCR) .......................................................... 16.3 Operation ........................................................................................................................... 16.3.1 I2C Bus Data Format............................................................................................. 16.3.2 Master Transmit Operation .................................................................................. 16.3.3 Master Receive Operation .................................................................................... 16.3.4 Slave Receive Operation ...................................................................................... 16.3.5 Slave Transmit Operation..................................................................................... 16.3.6 IRIC Setting Timing and SCL Control ................................................................ 16.3.7 Automatic Switching from Formatless Mode to I 2C Bus Format........................ 16.3.8 Operation Using the DTC .................................................................................... 16.3.9 Noise Canceler...................................................................................................... 16.3.10 Sample Flowcharts ............................................................................................... 16.3.11 Initialization of Internal State............................................................................... 16.4 Usage Notes ....................................................................................................................... 475 475 476 478 479 480 480 483 484 485 488 495 500 501 503 504 504 506 508 511 513 515 516 518 519 519 523 525 Section 17 Keyboard Buffer Controller ........................................................................ 531 17.1 Overview............................................................................................................................ 17.1.1 Features ................................................................................................................ 17.1.2 Block Diagram...................................................................................................... 17.1.3 Input/Output Pins.................................................................................................. 17.1.4 Register Configuration ......................................................................................... 17.2 Register Descriptions......................................................................................................... 17.2.1 Keyboard Control Register H (KBCRH) ............................................................. 531 531 532 533 533 534 534 xi 17.2.2 Keyboard Control Register L (KBCRL) .............................................................. 17.2.3 Keyboard Data Buffer Register (KBBR) ............................................................. 17.2.4 Module Stop Control Register (MSTPCR) .......................................................... 17.3 Operation ........................................................................................................................... 17.3.1 Receive Operation ................................................................................................ 17.3.2 Transmit Operation .............................................................................................. 17.3.3 Receive Abort....................................................................................................... 17.3.4 KCLKI and KDI Read Timing ............................................................................. 17.3.5 KCLKO and KDO Write Timing ......................................................................... 17.3.6 KBF Setting Timing and KCLK Control ............................................................. 17.3.7 Receive Timing .................................................................................................... 17.3.8 KCLK Fall Interrupt Operation............................................................................ 17.3.9 Usage Note ........................................................................................................... 536 538 538 539 539 541 544 547 547 548 549 550 551 Section 18A Host Interface X-Bus Interface (XBS).............................................................................. 553 18A.1 Overview .......................................................................................................................... 18A.1.1 Features ............................................................................................................ 18A.1.2 Block Diagram.................................................................................................. 18A.1.3 Input and Output Pins....................................................................................... 18A.1.4 Register Configuration ..................................................................................... 18A.2 Register Descriptions........................................................................................................ 18A.2.1 System Control Register (SYSCR) .................................................................. 18A.2.2 System Control Register 2 (SYSCR2) ............................................................. 18A.2.3 Host Interface Control Register (HICR) .......................................................... 18A.2.4 Input Data Register (IDR) ................................................................................ 18A.2.5 Output Data Register (ODR)............................................................................ 18A.2.6 Status Register (STR) ....................................................................................... 18A.2.7 Module Stop Control Register (MSTPCR) ...................................................... 18A.3 Operation .......................................................................................................................... 18A.3.1 Host Interface Activation ................................................................................. 18A.3.2 Control States ................................................................................................... 18A.3.3 A20 Gate .......................................................................................................... 18A.3.4 Host Interface Pin Shutdown Function ............................................................ 18A.4 Interrupts .......................................................................................................................... 18A.4.1 IBF1, IBF2, IBF3, IBF4 ................................................................................... 18A.4.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ............................................ 18A.5 Usage Note ....................................................................................................................... 553 553 554 555 556 557 557 558 559 561 561 562 564 564 564 566 566 568 570 570 570 572 Section 18B Host Interface LPC Interface (LPC).................................................................................. 573 18B.1 Overview .......................................................................................................................... 573 18B.1.1 Features ............................................................................................................ 573 xii 18B.2 18B.3 18B.4 18B.5 18B.1.2 Block Diagram.................................................................................................. 18B.1.3 Pin Configuration ............................................................................................. 18B.1.4 Register Configuration ..................................................................................... Register Descriptions........................................................................................................ 18B.2.1 System Control Registers (SYSCR, SYSCR2) ................................................ 18B.2.2 Host Interface Control Registers 0 and 1 (HICR0, HICR1) ............................ 18B.2.3 Host Interface Control Registers 2 and 3 (HICR2, HICR3) ............................ 18B.2.4 LPC Channel 3 Address Register (LADR3) .................................................... 18B.2.5 Input Data Registers (IDR1, IDR2, IDR3)....................................................... 18B.2.6 Output Data Registers (ODR1, ODR2, ODR3)................................................ 18B.2.7 Two-Way Data Registers (TWR0 to TWR15)................................................. 18B.2.8 Status Registers (STR1, STR2, STR3)............................................................. 18B.2.9 SERIRQ Control Registers (SIRQCR0, SIRQCR1) ........................................ 18B.2.10 Module Stop Control Register (MSTPCR) ...................................................... Operation .......................................................................................................................... 18B.3.1 Host Interface Activation ................................................................................. 18B.3.2 LPC I/O Cycles ................................................................................................ 18B.3.3 A20 Gate .......................................................................................................... 18B.3.4 Host Interface Shutdown Function (LPCPD)................................................... 18B.3.5 Host Interface Serial Interrupt Operation (SERIRQ) ....................................... 18B.3.6 Host Interface Clock Start Request (CLKRUN) .............................................. Interrupt Sources .............................................................................................................. 18B.4.1 IBF1, IBF2, IBF3, ERRI .................................................................................. 18B.4.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, HIRQ12 .......................... Usage Notes...................................................................................................................... 574 575 576 577 577 578 585 588 589 590 591 592 595 603 604 604 604 606 609 612 615 616 616 616 618 Section 19 D/A Converter ................................................................................................. 621 19.1 Overview............................................................................................................................ 19.1.1 Features ................................................................................................................ 19.1.2 Block Diagram...................................................................................................... 19.1.3 Input and Output Pins........................................................................................... 19.1.4 Register Configuration ......................................................................................... 19.2 Register Descriptions......................................................................................................... 19.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 19.2.2 D/A Control Register (DACR)............................................................................. 19.2.3 Module Stop Control Register (MSTPCR) .......................................................... 19.3 Operation ........................................................................................................................... 621 621 621 623 623 624 624 624 626 627 Section 20 A/D Converter ................................................................................................. 629 20.1 Overview............................................................................................................................ 20.1.1 Features ................................................................................................................ 20.1.2 Block Diagram...................................................................................................... 20.1.3 Pin Configuration ................................................................................................. 629 629 630 631 xiii 20.2 20.3 20.4 20.5 20.6 20.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 20.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 20.2.2 A/D Control/Status Register (ADCSR)................................................................ 20.2.3 A/D Control Register (ADCR)............................................................................. 20.2.4 Keyboard Comparator Control Register (KBCOMP) .......................................... 20.2.5 Module Stop Control Register (MSTPCR) .......................................................... Interface to Bus Master...................................................................................................... Operation ........................................................................................................................... 20.4.1 Single Mode (SCAN = 0) ..................................................................................... 20.4.2 Scan Mode (SCAN = 1) ....................................................................................... 20.4.3 Input Sampling and A/D Conversion Time.......................................................... 20.4.4 External Trigger Input Timing ............................................................................. Interrupts............................................................................................................................ Usage Notes ....................................................................................................................... 632 632 632 633 636 637 638 639 640 640 642 644 645 645 646 Section 21 RAM ................................................................................................................... 653 21.1 Overview............................................................................................................................ 21.1.1 Block Diagram...................................................................................................... 21.1.2 Register Configuration ......................................................................................... 21.2 System Control Register (SYSCR).................................................................................... 21.3 Operation ........................................................................................................................... 21.3.1 Expanded Mode (Modes 1, 2, and 3 (EXPE = 1))................................................ 21.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0)) ................................................. 653 653 654 654 655 655 655 Section 22 ROM ................................................................................................................... 657 22.1 Overview............................................................................................................................ 22.1.1 Block Diagram...................................................................................................... 22.1.2 Register Configuration.......................................................................................... 22.2 Register Descriptions......................................................................................................... 22.2.1 Mode Control Register (MDCR).......................................................................... 22.3 Operation ........................................................................................................................... 22.4 Overview of Flash Memory............................................................................................... 22.4.1 Features ................................................................................................................ 22.4.2 Block Diagram...................................................................................................... 22.4.3 Flash Memory Operating Modes.......................................................................... 22.4.4 Pin Configuration ................................................................................................. 22.4.5 Register Configuration ......................................................................................... 22.5 Register Descriptions......................................................................................................... 22.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 22.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 22.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)..................................................... 22.5.4 Serial/Timer Control Register (STCR) ................................................................ xiv 657 657 658 658 658 659 660 660 661 662 666 666 667 667 669 670 671 22.6 On-Board Programming Modes ........................................................................................ 22.6.1 Boot Mode............................................................................................................ 22.6.2 User Program Mode ............................................................................................. 22.7 Programming/Erasing Flash Memory................................................................................ 22.7.1 Program Mode...................................................................................................... 22.7.2 Program-Verify Mode .......................................................................................... 22.7.3 Erase Mode........................................................................................................... 22.7.4 Erase-Verify Mode ............................................................................................... 22.8 Flash Memory Protection .................................................................................................. 22.8.1 Hardware Protection............................................................................................. 22.8.2 Software Protection .............................................................................................. 22.8.3 Error Protection .................................................................................................... 22.9 Interrupt Handling when Programming/Erasing Flash Memory ....................................... 22.10 Flash Memory Programmer Mode .................................................................................... 22.10.1 Programmer Mode Setting ................................................................................... 22.10.2 Socket Adapters and Memory Map...................................................................... 22.10.3 Writer Mode Operation ........................................................................................ 22.10.4 Memory Read Mode............................................................................................. 22.10.5 Auto-Program Mode ............................................................................................ 22.10.6 Auto-Erase Mode.................................................................................................. 22.10.7 Status Read Mode................................................................................................. 22.10.8 Status Polling........................................................................................................ 22.10.9 Writer Mode Transition Time .............................................................................. 22.10.10 Notes On Memory Programming ....................................................................... 22.11 Flash Memory Programming and Erasing Precautions ..................................................... 672 673 678 679 679 680 682 682 684 684 684 685 686 687 687 688 688 690 693 694 696 697 697 698 698 Section 23 Clock Pulse Generator .................................................................................. 701 23.1 Overview............................................................................................................................ 23.1.1 Block Diagram...................................................................................................... 23.1.2 Register Configuration ......................................................................................... 23.2 Register Descriptions......................................................................................................... 23.2.1 Standby Control Register (SBYCR) .................................................................... 23.2.2 Low-Power Control Register (LPWRCR)............................................................ 23.3 Oscillator............................................................................................................................ 23.3.1 Connecting a Crystal Resonator ........................................................................... 23.3.2 External Clock Input ............................................................................................ 23.4 Duty Adjustment Circuit.................................................................................................... 23.5 Medium-Speed Clock Divider........................................................................................... 23.6 Bus Master Clock Selection Circuit .................................................................................. 23.7 Subclock Input Circuit....................................................................................................... 23.8 Subclock Waveform Shaping Circuit................................................................................ 23.9 Clock Selection Circuit...................................................................................................... 23.10 X1 and X2 Pins.................................................................................................................. 701 701 701 702 702 703 703 703 705 708 708 708 708 709 709 710 xv Section 24 Power-Down State.......................................................................................... 711 24.1 Overview............................................................................................................................ 24.1.1 Register Configuration ......................................................................................... 24.2 Register Descriptions......................................................................................................... 24.2.1 Standby Control Register (SBYCR) .................................................................... 24.2.2 Low-Power Control Register (LPWRCR)............................................................ 24.2.3 Timer Control/Status Register (TCSR) ................................................................ 24.2.4 Module Stop Control Register (MSTPCR) .......................................................... 24.3 Medium-Speed Mode ........................................................................................................ 24.4 Sleep Mode........................................................................................................................ 24.4.1 Sleep Mode........................................................................................................... 24.4.2 Clearing Sleep Mode ............................................................................................ 24.5 Module Stop Mode ............................................................................................................ 24.5.1 Module Stop Mode ............................................................................................... 24.5.2 Usage Note ........................................................................................................... 24.6 Software Standby Mode .................................................................................................... 24.6.1 Software Standby Mode ....................................................................................... 24.6.2 Clearing Software Standby Mode ........................................................................ 24.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode .......... 24.6.4 Software Standby Mode Application Example .................................................... 24.6.5 Usage Note ........................................................................................................... 24.7 Hardware Standby Mode ................................................................................................... 24.7.1 Hardware Standby Mode...................................................................................... 24.7.2 Hardware Standby Mode Timing ......................................................................... 24.8 Watch Mode ...................................................................................................................... 24.8.1 Watch Mode ......................................................................................................... 24.8.2 Clearing Watch Mode .......................................................................................... 24.9 Subsleep Mode .................................................................................................................. 24.9.1 Subsleep Mode ..................................................................................................... 24.9.2 Clearing Subsleep Mode ...................................................................................... 24.10 Subactive Mode ................................................................................................................. 24.10.1 Subactive Mode.................................................................................................... 24.10.2 Clearing Subactive Mode ..................................................................................... 24.11 Direct Transition................................................................................................................ 24.11.1 Overview of Direct Transition.............................................................................. 711 715 715 715 717 719 720 721 722 722 722 723 723 724 725 725 725 726 726 727 728 728 729 730 730 730 731 731 731 732 732 732 733 733 Section 25 Electrical Characteristics .............................................................................. 735 25.1 Absolute Maximum Ratings.............................................................................................. 25.2 DC Characteristics ............................................................................................................. 25.3 AC Characteristics ............................................................................................................. 25.3.1 Clock Timing........................................................................................................ 25.3.2 Control Signal Timing.......................................................................................... 25.3.3 Bus Timing ........................................................................................................... xvi 735 736 742 743 745 747 25.4 25.5 25.6 25.7 25.3.4 Timing of On-Chip Supporting Modules ............................................................. A/D Conversion Characteristics ........................................................................................ D/A Conversion Characteristics ........................................................................................ Flash Memory Characteristics ........................................................................................... Usage Note (Internal Step-Down) ..................................................................................... 754 764 765 766 768 Appendix A Instruction Set ............................................................................................... 769 A.1 A.2 A.3 A.4 A.5 Instruction.......................................................................................................................... Instruction Codes ............................................................................................................... Operation Code Map.......................................................................................................... Number of States Required for Execution......................................................................... Bus States During Instruction Execution .......................................................................... 769 787 801 805 818 Appendix B Internal I/O Registers.................................................................................. 834 B.1 B.2 B.3 Addresses........................................................................................................................... 834 Register Selection Conditions............................................................................................ 843 Functions............................................................................................................................ 853 Appendix C I/O Port Block Diagrams ........................................................................... 952 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 Port 1 Block Diagram........................................................................................................ Port 2 Block Diagrams ...................................................................................................... Port 3 Block Diagram........................................................................................................ Port 4 Block Diagrams ...................................................................................................... Port 5 Block Diagrams ...................................................................................................... Port 6 Block Diagrams ...................................................................................................... Port 7 Block Diagrams ...................................................................................................... Port 8 Block Diagrams ...................................................................................................... Port 9 Block Diagrams ...................................................................................................... Port A Block Diagrams...................................................................................................... Port B Block Diagram ....................................................................................................... Port C, D, E, F, G Block Diagram ..................................................................................... 952 953 956 959 966 969 974 975 982 987 990 993 Appendix D Pin States........................................................................................................ 994 D.1 Port States in Each Processing State.................................................................................. 994 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode................................................................................................ 996 E.1 E.2 Timing of Transition to Hardware Standby Mode ............................................................ 996 Timing of Recovery from Hardware Standby Mode......................................................... 996 xvii Appendix F Product Codes................................................................................................ 997 Appendix G Package Dimensions ................................................................................... 998 xviii Section 1 Overview 1.1 Overview The H8S/2149 and H8S/2169 F-ZTAT™ is a microcomputer (MCU) built around the H8S/2000 CPU, employing Hitachi’s proprietary architecture, and equipped with on-chip supporting functions required for system configuration. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip supporting functions required for system configuration include a data transfer controller (DTC) bus master, ROM and RAM memory, a 16-bit free-running timer module (FRT), an 8-bit timer module (TMR), watchdog timer module (WDT), two PWM timers (PWM and PWMX), serial communication interface (SCI), PS/2-compatible keyboard buffer controller, I 2C bus interface (IIC), host interfaces (HIF:LPC and HIF:XBS), D/A converter (DAC), A/D converter (ADC), and I/O ports. The H8S/2169 F-ZTAT™ has all of the same I/O ports as the H8S/2149 FZTAT™, plus 40 additional I/O ports. The on-chip ROM is 64-kbyte flash memory (F-ZTAT™*). The ROM is connected to the CPU by a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Three operating modes, modes 1 to 3, are provided, and there is a choice of address space and single-chip mode or externally expanded modes. The features of the H8S/2149 and H8S/2169 F-ZTAT™ are shown in table 1.1. Note: * F-ZTAT is a trademark of Hitachi, Ltd. 1 Table 1.1 Overview Item Specifications CPU • General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control Maximum operating frequency: 10 MHz/3 V High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 100 ns (10 MHz operation) 16 × 16-bit register-register multiply: 2000 ns (10 MHz operation) 32 ÷ 16-bit register-register divide: 2000 ns (10 MHz operation) • Instruction set suitable for high-speed operation Sixty-five basic instructions 8/16/32-bit transfer/arithmetic and logic instructions Unsigned/signed multiply and divide instructions Powerful bit-manipulation instructions • Two CPU operating modes Normal mode: 64-kbyte address space Advanced mode: 16-Mbyte address space Operating modes • Three MCU operating modes External Data Bus Mode CPU Operating Mode 1 Normal 2 Advanced On-Chip ROM Initial Value Max. Value Expanded mode with on-chip ROM disabled Disabled 8 bits 16 bits Expanded mode with on-chip ROM enabled Enabled 8 bits 16 bits Description Single-chip mode 3 Normal Expanded mode with on-chip ROM enabled Single-chip mode Bus controller 2 None Enabled 8 bits 16 bits None • 2-state or 3-state access space can be designated for external expansion areas • Number of program wait states can be set for external expansion areas Item Specifications Data transfer controller (DTC) • Can be activated by internal interrupt or software • Multiple transfers or multiple types of transfer possible for one activation source • Transfer possible in repeat mode, block transfer mode, etc. • Request can be sent to CPU for interrupt that activated DTC 16-bit free-running • timer module (FRT: • 1 channel) • One 16-bit free-running counter (usable for external event counting) Two output compare outputs Four input capture inputs (with buffer operation capability) 8-bit timer module Each channel has: (2 channels: TMR0, • One 8-bit up-counter (usable for external event counting) TMR1) • Two timer constant registers • The two channels can be connected Input/output and FRT, TMR1, TMRX, TMRY can be interconnected Timer connection and 8-bit timer • Measurement of input signal or frequency-divided waveform pulse width module (TMR) and cycle (FRT, TMR1) (2 channels: TMRX, TMRY) • Output of waveform obtained by modification of input signal edge (FRT, TMR1) • Determination of input signal duty cycle (TMRX) • Output of waveform synchronized with input signal (FRT, TMRX, TMRY) • Automatic generation of cyclical waveform (FRT, TMRY) Watchdog timer module (WDT: 2 channels) • Watchdog timer or interval timer function selectable • Subclock operation capability (channel 1 only) 8-bit PWM timer (PWM) • Up to 16 outputs • Pulse duty cycle settable from 0 to 100% • Resolution: 1/256 • 625 kHz maximum carrier frequency (10 MHz operation) • Up to 2 outputs • Resolution: 1/16384 • 156.25 kHz maximum carrier frequency (10 MHz operation) • Asynchronous mode or synchronous mode selectable • Multiprocessor communication function 14-bit PWM timer (PWMX) Serial communication interface (SCI: 2 channels, SCI0, SCI1) 3 Item Specifications SCI with IrDA: 1 channel (SCI2) • Asynchronous mode or synchronous mode selectable • Multiprocessor communication function • Conforms to IrDA standard version 1.0 • IrDA format encoding/decoding of TxD and RxD • Conforms to PS/2 interface • Direct manipulation of transmission output by software • Receive data input to 8-bit shift register • Data/receive/completed interrupt, parity error detection, stop bit monitoring • 8-bit host interface (ISA/X-BUS) port • Five host interrupt requests (HIRQ11, HIRQ1, HIRQ12, HIRQ3, HIRQ4) • Normal and fast A20 gate output • Four register sets (each comprising two data registers and a status register) • Single-channel LPC port Keyboard buffer controller (PS2: 3 channels) Host interface (HIF:XBS) Host interface (HIF:LPC) XBS three register set equivalence, plus 16 two-way register bytes • Seven serial host interrupt requests (SMI, HIRQ1, HIRQ6, HIRQ9 to HIRQ12) • Normal and fast A20 gate output • Three register sets (each comprising two data registers and a status register) Keyboard controller • Matrix keyboard control using keyboard scan with wakeup interrupt and sense port configuration A/D converter • Resolution: 10 bits • Input: 8 channels (dedicated analog pins) 16 channels (same pins as keyboard sense port) 4 • High-speed conversion: 13.4 µs minimum conversion time (10 MHz operation) • Single or scan mode selectable • Sample-and-hold function • A/D conversion can be activated by external trigger or timer trigger Item Specifications D/A converter • Resolution: 8 bits • Output: 2 channels I/O ports • 74 input/output pins (including 24 with LED drive capability) (H8S/2149) • Eight input-only pins • Eight of the input/output pins are driven by VCCB (separate power supply) I/O ports • 114 input/output pins (including 24 with LED drive capability) (H8S/2169) • Eight input-only pins • 32 of the input/output pins are driven by VCCB (separate power supply) • Flash memory: 64 kbytes • High-speed static RAM: 2 kbytes • Nine external interrupt pins (NMI, IRQ0 to IRQ7) • 48 internal interrupt sources • Three priority levels settable • Medium-speed mode • Sleep mode • Module stop mode • Software standby mode • Hardware standby mode • Subclock operation Clock pulse generator • Built-in duty correction circuit Packages • 100-pin plastic QFP (FP-100B) (H8S/2149) • 100-pin plastic TQFP (TFP-100B) Packages • 144-pin plastic TQFP (TFP-144) • Conforms to Philips I2C bus interface standard • Single master mode/slave mode • Arbitration lost condition can be identified • Supports two slave addresses Memory Interrupt controller Power-down state (H8S/2169) I 2C bus interface (IIC: 2 channels) 5 Item Specifications Product lineup Product Code (F-ZTAT Version) ROM/RAM (Bytes) Packages HD64F2149YV 64 k/2 k FP-100B, TFP-100B HD64F2169YV 64 k/2 k TFP-144 6 1.2 Block Diagram VCC VCL VSS VSS VSS VSS Figure 1.1(a) is a block diagram of the H8S/2149. Figure 1.1(b) is a block diagram of the H8S/2169. PA7/A23/KIN15/CIN15/PS2CD PA6/A22/KIN14/CIN14/PS2CC P93/RD/IOR P92/IRQ0 P91/IRQ1 Interrup controller P27/A15/PW15/CBLANK P26/A14/PW14 DTC Port 9 P95/AS/IOS/CS1 P94/HWR/IOW PA0/A16/KIN8/CIN8 Port 2 P97/WAIT/SDA0 P96/ø/EXCL PA5/A21/KIN13/CIN13/PS2BD PA4/A20/KIN12/CIN12/PS2BC PA3/A19/KIN11/CIN11/PS2AD PA2/A18/KIN10/CIN10/PS2AC PA1/A17/KIN9/CIN9 Bus controller STBY RESO H8S/2000 CPU Internal data bus MD0 NMI Internal address bus EXTAL VCCB MD1 Port A Clock pulse generator RES XTAL P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 ROM P17/A7/PW7 P16/A6/PW6 WDT0, WDT1 Port 6 PB7/D7/WUE7 PB6/D6/WUE6 PB5/D5/WUE5 PB4/D4/WUE4 PB3/D3/WUE3/CS4 PB2/D2/WUE2/CS3 PB1/D1/WUE1/HIRQ4/LSCI PB0/D0/WUE0/HIRQ3/LSMI (LPC, XBS) 10-bit A/D converter 8-bit D/A converter IIC × 2 channels Port 8 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 P37/D15/HDB7/SERIRQ P36/D14/HDB6/LCLK P35/D13/HDB5/LRESET P34/D12/HDB4/LFRAME P33/D11/HDB3/LAD3 P32/D10/HDB2/LAD2 P31/D9/HDB1/LAD1 P30/D8/HDB0/LAD0 Host interfaces SCI × 3 channels (IrDA × 1 channel) P15/A5/PW5 P14/A4/PW4 Port 3 8-bit timer × 4 channels (TMR0, TMR1, TMRX, TMRY) Timer connection P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 Port 7 AVref AVCC AVSS P86/IRQ5/SCK1/SCL1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83/LPCPD P82/HIFSD/CLKRUN P81/CS2/GA20 P80/HA0/PME P52/SCK0/SCL0 P51/RxD0 P50/TxD0 8-bit PWM 14-bit PWM Port 4 P47/PWX1 P46/PWX0 P45/TMRI1/HIRQ12/CSYNCI P44/TMO1/HIRQ1/HSYNCO P43/TMCI1/HIRQ11/HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD Keyboard buffer controller × 3 channels 16-bit FRT Port 5 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4/CLAMPO P63/FTIB/CIN3/KIN3/VFBACKI P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P61/FTOA/CIN1/KIN1/VSYNCO P60/FTCI/CIN0/KIN0/HFBACKI/TMIX RAM Port B P67/TMOX/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 Port 1 P90/LWR/IRQ2/ADTRG/ECS2 Figure 1.1(a) Internal Block Diagram of H8S/2149 7 VCC VCC VCL VSS VSS VSS VSS VSS PA7/A23/KIN15/CIN15/PS2CD Port A PA6/A22/KIN14/CIN14/PS2CC PA5/A21/KIN13/CIN13/PS2BD X1 X2 RES PA1/A17/KIN9/CIN9 PA0/A16/KIN8/CIN8 Clock pulse generator STBY RESO P97/WAIT/SDA0 Interrupt P96/ø/EXCL controller P26/A14/PW14 P25/A13/PW13 Port 2 NMI P27/A15/PW15/CBLANK H8S/2000 CPU Bus controller MD1 MD0 Internal data bus VCCB Internal address bus EXTAL P21/A9/PW9 P20/A8/PW8 DTC P17/A7/PW7 Port 1 ROM P13/A3/PW3 P11/A1/PW1 P10/A0/PW0 P90/LWR/IRQ2/ADTRG/ECS2 8-bit PWM 16-bit FRT Port 3 Keyboard buffer controller × 3 channels P37/D15/HDB7/SERIRQ P36/D14/HDB6/LCLK P35/D13/HDB5/LRESET P34/D12/HDB4/LFRAME P33/D11/HDB3/LAD3 P32/D10/HDB2/LAD2 P31/D9/HDB1/LAD1 P30/D8/HDB0/LAD0 Port B Port 6 RAM PB7/D7/WUE7 PB6/D6/WUE6 PB5/D5/WUE5 PB4/D4/WUE4 PB3/D3/WUE3/CS4 PB2/D2/WUE2/CS3 PB1/D1/WUE1/HIRQ4/LSCI PB0/D0/WUE0/HIRQ3/LSMI 14-bit PWM Port 4 8-bit timer × 4 channels (TMR0, TMR1, TMRX, TMRY) Timer connection Host interfaces (LPC, XBS) 10-bit A/D converter SCI × 3 channels (IrDA × 1 channel) Port 5 8-bit D/A converter IIC × 2 channels Port C P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P14/A4/PW4 P12/A2/PW2 WDT0, WDT1 P47/PWX1 P46/PWX0 P45/TMRI1/HIRQ12/CSYNCI P44/TMO1/HIRQ1/HSYNCO P43/TMCI1/HIRQ11/HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD P23/A11/PW11 P16/A6/PW6 P15/A5/PW5 P92/IRQ0 P91/IRQ1 P67/TMOX/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4/CLAMPO P63/FTIB/CIN3/KIN3/VFBACKI P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P61/FTOA/CIN1/KIN1/VSYNCO P60/FTCI/CIN0/KIN0/HFBACKI/TMIX P24/A12/PW12 P22/A10/PW10 Port 9 P93/RD/IOR PA3/A19/KIN11/CIN11/PS2AD PA2/A18/KIN10/CIN10/PS2AC XTAL P95/AS/IOS/CS1 P94/HWR/IOW PA4/A20/KIN12/CIN12/PS2BC PC7 PC6 PC5 PC4 PC3 Port E PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Port F PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Port G PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 Port 7 AVref AVCC AVSS P86/IRQ5/SCK1/SCL1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83/LPCPD P82/HIFSD/CLKRUN P81/CS2/GA20 P80/HA0/PME Port 8 Figure 1.1(b) Internal Block Diagram of H8S/2169 8 Port D PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 1.3 Pin Arrangement and Functions 1.3.1 Pin Arrangement P42/TMRI0/SCK2/SDA1 P43/TMCI1/HIRQ11/HSYNCI P44/TMO1/HIRQ1/HSYNCO P45/TMRI1/HIRQ12/CSYNCI P46/PWX0 P47/PWX1 PB7/D7/WUE7 PB6/D6/WUE6 VCC P27/A15/PW15/CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 PB4/D4/WUE4 PB5/D5/WUE5 VSS VSS P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 Figure 1.2(a) shows the arrangement of the H8S/2149’s pins. Figure 1.2(b) shows the arrangement of the H8S/2169’s pins. P13/A3/PW3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 P41/TMO0/RxD2/IrRxD P12/A2/PW2 77 49 P40/TMCI0/TxD2/IrTxD P11/A1/PW1 78 48 PA0/A16/CIN8/KIN8 P10/A0/PW0 79 47 PA1/A17/CIN9/KIN9 PB3/D3/WUE3/CS4 80 46 AVSS PB2/D2/WUE2/CS3 81 45 P77/AN7/DA1 P30/D8 /HDB0/LAD0 82 44 P76/AN6/DA0 P31/D9 /HDB1/LAD1 83 43 P75/AN5 P32/D10/HDB2/LAD2 84 42 P74/AN4 P33/D11/HDB3/LAD3 85 41 P73/AN3 P34/D12/HDB4/LFRAME 86 40 P72/AN2 P35/D13/HDB5/LRESET 87 39 P71/AN1 P36/D14/HDB6/LCLK 88 38 P70/AN0 P37/D15/HDB7/SERIRQ 89 37 AVCC PB1/D1/HIRQ4/WUE1/LSCI 90 36 AVref PB0/D0/HIRQ3/WUE0/LSMI 91 35 P67/TMOX/CIN7/KIN7/IRQ7 VSS 92 34 P66/FTOB/CIN6/KIN6/IRQ6 P80/HA0/PME 93 33 P65/FTID/CIN5/KIN5 P81/CS2/GA20 94 32 P64/FTIC/CIN4/KIN4/CLAMPO P82/HIFSD/CLKRUN 95 31 PA2/A18/CIN10/KIN10/PS2AC P83/LPCPD 96 30 PA3/A19/CIN11/KIN11/PS2AD P84/IRQ3/TxD1 97 29 P63/FTIB/CIN3/KIN3/VFBACKI P85/IRQ4/RxD1 98 28 P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P86/IRQ5/SCK1/SCL1 99 27 P61/FTOA/CIN1/KIN1/VSYNCO RESO 100 P60/FTCI/CIN0/KIN0/HFBACKI/TMIX P90/LWR/ECS2/IRQ2/ ADTRG P91/ IRQ1 P92/ IRQ0 P93/ RD/IOR PA4/A20/CIN12/KIN12/PS2BC PA5/A21/CIN13/KIN13/PS2BD NMI P94/ HWR/IOW MD0 P95/ AS/ IOS/CS1 MD1 P96/φ/EXCL VCCB P97/WAIT/SDA0 EXTAL VSS RES 26 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P50/TxD0 7 P51/RxD0 6 P52/SCK0/SCL0 5 PA6/A22/CIN14/KIN14/PS2CC 4 VCL 3 PA7/A23/CIN15/KIN15/PS2CD 2 STBY 1 XTAL FP-100B TFP-100B (Top View) Figure 1.2(a) H8S/2149 Pin Arrangement (FP-100B, TFP-100B: Top View) 9 P11/A1/PW1 VSS P75/AN5 P76/AN6/DA0 P77/AN7/DA1 P60/FTCI/CIN0/KIN0/HFBACKI/TMIX AVCC P61/FTOA/CIN1/KIN1/VSYNCO AVref P64/FTIC/CIN4/KIN4/CLAMPO P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P63/FTIB/CIN3/KIN3/VFBACKI P65/FTID/CIN5/KIN5 P66/FTOB/CIN6/KIN6/IRQ6 P67/TMOX/CIN7/KIN7/IRQ7 VCC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 VSS P27/A15/PW15/CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 109 71 110 P74/AN4 P73/AN3 111 70 P72/AN2 P10/A0/PW0 112 69 P71/AN1 PB7/D7/WUE7 113 68 P70/AN0 PB6/D6/WUE6 114 67 AVSS PB5/D5/WUE5 115 66 PD0 PB4/D4/WUE4 116 65 PD1 PB3/D3/WUE3/CS4 117 64 PD2 PB2/D2/WUE2/CS3 118 63 PD3 PB1/D1/HIRQ4/WUE1/LSCI 119 62 PD4 PB0/D0/HIRQ3/WUE0/LSMI 120 61 PD5 P30/D8/HDB0/LAD0 121 60 PD6 P31/D9/HDB1/LAD1 122 59 PD7 P32/D10/HDB2/LAD2 123 58 PG0 P33/D11/HDB3/LAD3 124 57 PG1 P34/D12/HDB4/LFRAME 125 56 PG2 P35/D13/HDB5/LRESET 126 55 PG3 P36/D14/HDB6/LCLK TFP-144 (Top View) 127 54 PG4 P37/D15/HDB7/SERIRQ 128 53 PG5 P80/HA0/PME 129 52 PG6 P81/CS2/GA20 130 51 PG7 P82/HIFSD/CLKRUN 131 50 PF0 P83/LPCPD 132 49 PF1 P84/IRQ3/TxD1 133 48 PF2 P85/IRQ4/RxD1 134 47 PF3 PF4 P86/IRQ5/SCK1/SCL1 135 46 P40/TMCI0/TxD2/IrTxD 136 45 PF5 P41/TMO0/RxD2/IrRxD 137 44 PF6 P42/TMRI0/SCK2/SDA1 138 43 PF7 VSS 139 42 VSS X1 140 41 PA0/A16/CIN8/KIN8 X2 141 40 PA1/A17/CIN9/KIN9 RESO VCCB PA5/A21/CIN13/KIN13/PS2BD PA6/A22/CIN14/KIN14/PS2CC PE0 PA7/A23/CIN15/KIN15/PS2CD PE1 PE2 PE3 PE4 PE5 PE6 PE7 P90/LWR/ECS2/IRQ2/ADTRG P91/IRQ1 P92/IRQ0 P93/RD/IOR P94/HWR/IOW P95/AS/IOS/CS1 P96/ø/ EXCL MD1 P50/TxD0 RES P97/WAIT/SDA0 VSS P51/ RxD0 8 VCL 7 P52/SCK0/SCL0 6 STBY 5 NMI 4 MD0 3 P47/PWX1 PA4/A20/CIN12/KIN12/PS2BC 2 37 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 P46/PWX0 144 1 P45/TMRI1/HIRQ12/CSYNCI PA3/A19/CIN11/KIN11/PS2AD EXTAL P44/TMO1/HIRQ1/HSYNCO PA2/A18/CIN10/KIN10/PS2AC 143 38 VCC 39 P43/TMCI1/HIRQ11/HSYNCI 142 XTAL Figure 1.2(b) H8S/2169 Pin Arrangement (TFP-144: Top View) 10 1.3.2 Pin Functions in Each Operating Mode Tables 1.2(a) and table 1.2(b), respectively, show the pin functions of the H8S/2149 and H8S/2169, for each of the operating modes. (B) following the pin number indicates VCCB drive, and (N) indicates an NMOS push-pull/open-drain drive. Table 1.2(a) H8S/2149 Pin Functions in Each Operating Mode Pin Name Pin No. Expanded Modes Single-Chip Modes Flash Memory FP-100B TFP-100B Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Programmer Mode 1 RES RES RES RES 2 XTAL XTAL XTAL XTAL 3 EXTAL EXTAL EXTAL EXTAL 4 VCCB VCCB VCCB VCC 5 MD1 MD1 MD1 VSS 6 MD0 MD0 MD0 VSS 7 NMI NMI NMI FA9 8 STBY STBY STBY VCC 9 VCL VCL VCL VCC 10 (B) PA7/CIN15/KIN15/ PS2CD PA7/A23/CIN15/ KIN15/PS2CD PA7/CIN15/KIN15/ PS2CD NC 11 (B) PA6/CIN14/KIN14/ PS2CC PA6/A22/CIN14/ KIN14/PS2CC PA6/CIN14/KIN14/ PS2CC NC 12 (N) P52/SCK0/SCL0 P52/SCK0/SCL0 P52/SCK0/SCL0 NC 13 P51/RxD0 P51/RxD0 P51/RxD0 FA17 14 P50/TxD0 P50/TxD0 P50/TxD0 NC 15 VSS VSS VSS VSS 16 (N) P97/WAIT/SDA0 P97/WAIT/SDA0 P97/SDA0 VCC 17 P96/ø/EXCL P96/ø/EXCL P96/ø/EXCL NC 18 AS/IOS AS/IOS P95/CS1 FA16 19 HWR HWR P94/IOW FA15 20 (B) PA5/CIN13/KIN13/ PS2BD PA5/A21/CIN13/ KIN13/PS2BD PA5/CIN13/KIN13/ PS2BD NC 21 (B) PA4/CIN12/KIN12/ PS2BC PA4/A20/CIN12/ KIN12/PS2BC PA4/CIN12/KIN12/ PS2BC NC 11 Pin Name Pin No. Expanded Modes Single-Chip Modes Flash Memory FP-100B TFP-100B Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Programmer Mode 22 RD RD P93/IOR WE 23 P92/IRQ0 P92/IRQ0 P92/IRQ0 VSS 24 P91/IRQ1 P91/IRQ1 P91/IRQ1 VCC 25 P90/LWR/IRQ2/ ADTRG P90/LWR/IRQ2/ ADTRG P90/ECS2/IRQ2/ ADTRG VCC 26 P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX NC 27 P61/FTOA/CIN1/ KIN1/VSYNCO P61/FTOA/CIN1/ KIN1/VSYNCO P61/FTOA/CIN1/ KIN1/VSYNCO NC 28 P62/FTIA/CIN2/ P62/FTIA/CIN2/ KIN2/VSYNCI/TMIY KIN2/VSYNCI/TMIY P62/FTIA/CIN2/ KIN2/VSYNCI/TMIY NC 29 P63/FTIB/CIN3/ KIN3/VFBACKI P63/FTIB/CIN3/ KIN3/VFBACKI P63/FTIB/CIN3/ KIN3/VFBACKI NC 30 (B) PA3/CIN11/KIN11/ PS2AD PA3/A19/CIN11/ KIN11/PS2AD PA3/CIN11/KIN11/ PS2AD NC 31 (B) PA2/CIN10/KIN10/ PS2AC PA2/A18/CIN10/ KIN10/PS2AC PA2/CIN10/KIN10/ PS2AC NC 32 P64/FTIC/CIN4/ KIN4/CLAMPO P64/FTIC/CIN4/ KIN4/CLAMPO P64/FTIC/CIN4/ KIN4/CLAMPO NC 33 P65/FTID/CIN5/ KIN5 P65/FTID/CIN5/ KIN5 P65/FTID/CIN5/ KIN5 NC 34 P66/FTOB/CIN6/ KIN6/IRQ6 P66/FTOB/CIN6/ KIN6/IRQ6 P66/FTOB/CIN6/ KIN6/IRQ6 NC 35 P67/TMOX/CIN7/ KIN7/IRQ7 P67/TMOX/CIN7/ KIN7/IRQ7 P67/TMOX/CIN7/ KIN7/IRQ7 VSS 36 AVref AVref AVref VCC 37 AVCC AVCC AVCC VCC 38 P70/AN0 P70/AN0 P70/AN0 NC 39 P71/AN1 P71/AN1 P71/AN1 NC 40 P72/AN2 P72/AN2 P72/AN2 NC 41 P73/AN3 P73/AN3 P73/AN3 NC 12 Pin Name Pin No. Expanded Modes Single-Chip Modes Flash Memory FP-100B TFP-100B Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Programmer Mode 42 P74/AN4 P74/AN4 P74/AN4 NC 43 P75/AN5 P75/AN5 P75/AN5 NC 44 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 NC 45 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 NC 46 AVSS AVSS AVSS VSS 47 (B) PA1/CIN9/KIN9 PA1/A17/CIN9/KIN9 PA1/CIN9/KIN9 NC 48 (B) PA0/CIN8/KIN8 PA0/A16/CIN8/KIN8 PA0/CIN8/KIN8 NC 49 P40/TMCI0/TxD2/ IrTxD P40/TMCI0/TxD2/ IrTxD P40/TMCI0/TxD2/ IrTxD NC 50 P41/TMO0/RxD2/ IrRxD P41/TMO0/RxD2/ IrRxD P41/TMO0/RxD2/ IrRxD NC 51 P42/TMRI0/SCK2/ SDA1 P42/TMRI0/SCK2/ SDA1 P42/TMRI0/SCK2/ SDA1 NC 52 P43/TMCI1/ HSYNCI P43/TMCI1/ HSYNCI P43/TMCI1/HIRQ11/ HSYNCI NC 53 P44/TMO1/ HSYNCO P44/TMO1/ HSYNCO P44/TMO1/HIRQ1/ HSYNCO NC 54 P45/TMRI1/ CSYNCI P45/TMRI1/ CSYNCI P45/TMRI1/HIRQ12/ CSYNCI NC 55 P46/PWX0 P46/PWX0 P46/PWX0 NC 56 P47/PWX1 P47/PWX1 P47/PWX1 NC 57 PB7/D7/WUE7 PB7/D7/WUE7 PB7/WUE7 NC 58 PB6/D6/WUE6 PB6/D6/WUE6 PB6/WUE6 NC 59 VCC VCC VCC VCC 60 A15 P27/A15/PW15/ CBLANK P27/PW15/ CBLANK CE 61 A14 P26/A14/PW14 P26/PW14 FA14 62 A13 P25/A13/PW13 P25/PW13 FA13 63 A12 P24/A12/PW12 P24/PW12 FA12 64 A11 P23/A11/PW11 P23/PW11 FA11 13 Pin Name Pin No. Expanded Modes Single-Chip Modes Flash Memory FP-100B TFP-100B Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Programmer Mode 65 A10 P22/A10/PW10 P22/PW10 FA10 66 A9 P21/A9/PW9 P21/PW9 OE 67 A8 P20/A8/PW8 P20/PW8 FA8 68 PB5/D5/WUE5 PB5/D5/WUE5 PB5/WUE5 NC 69 PB4/D4/WUE4 PB4/D4/WUE4 PB4/WUE4 NC 70 VSS VSS VSS VSS 71 VSS VSS VSS VSS 72 A7 P17/A7/PW7 P17/PW7 FA7 73 A6 P16/A6/PW6 P16/PW6 FA6 74 A5 P15/A5/PW5 P15/PW5 FA5 75 A4 P14/A4/PW4 P14/PW4 FA4 76 A3 P13/A3/PW3 P13/PW3 FA3 77 A2 P12/A2/PW2 P12/PW2 FA2 78 A1 P11/A1/PW1 P11/PW1 FA1 79 A0 P10/A0/PW0 P10/PW0 FA0 80 PB3/D3/WUE3 PB3/D3/WUE3 PB3/WUE3/CS4 NC 81 PB2/D2/WUE2 PB2/D2/WUE2 PB2/WUE2/CS3 NC 82 D8 D8 P30/HDB0/LAD0 FO0 83 D9 D9 P31/HDB1/LAD1 FO1 84 D10 D10 P32/HDB2/LAD2 FO2 85 D11 D11 P33/HDB3/LAD3 FO3 86 D12 D12 P34/HDB4/LFRAME FO4 87 D13 D13 P35/HDB5/LRESET FO5 88 D14 D14 P36/HDB6/LCLK FO6 89 D15 D15 P37/HDB7/SERIRQ FO7 90 PB1/D1/WUE1 PB1/D1/WUE1 PB1/HIRQ4/WUE1/ LSCI NC 91 PB0/D0/WUE0 PB0/D0/WUE0 PB0/HIRQ3/ WUE0/ LSMI NC 14 Pin Name Pin No. Expanded Modes Single-Chip Modes Flash Memory FP-100B TFP-100B Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Programmer Mode 92 VSS VSS VSS VSS 93 P80 P80 P80/HA0/PME NC 94 P81 P81 P81/CS2/GA20 NC 95 P82 P82 P82/HIFSD/ CLKRUN NC 96 P83 P83 P83/LPCPD NC 97 P84/IRQ3/TxD1 P84/IRQ3/TxD1 P84/IRQ3/TxD1 NC 98 P85/IRQ4/RxD1 P85/IRQ4/RxD1 P85/IRQ4/RxD1 NC 99 P86/IRQ5/SCK1/ SCL1 P86/IRQ5/SCK1/ SCL1 P86/IRQ5/SCK1/ SCL1 NC 100 RESO RESO RESO NC 15 Table 1.2(b) H8S/2169 Pin Functions in Each Operating Mode Pin Name Pin No. Expanded modes Single-Chip Modes Flash Memory TFP-144 Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Programmer Mode 1 VCC VCC VCC VCC 2 P43/TMCI1/ HSYNCI P43/TMCI1/ HSYNCI P43/TMCI1/HIRQ11/ NC HSYNCI 3 P44/TMO1/ HSYNCO P44/TMO1/ HSYNCO P44/TMO1/HIRQ1/ HSYNCO 4 P45/TMRI1/ CSYNCI P45/TMRI1/ CSYNCI P45/TMRI1/HIRQ12/ NC CSYNCI 5 P46/PWX0 P46/PWX0 P46/PWX0 NC 6 P47/PWX1 P47/PWX1 P47/PWX1 NC 7 VSS VSS VSS VSS 8 RES RES RES RES 9 MD1 MD1 MD1 VSS 10 MD0 MD0 MD0 VSS 11 NMI NMI NMI FA9 12 STBY STBY STBY VCC 13 VCL VCL VCL VCC 14 (N) P52/SCK0/SCL0 P52/SCK0/SCL0 P52/SCK0/SCL0 FA18 15 P51/RxD0 P51/RxD0 P51/RxD0 FA17 16 P50/TxD0 P50/TxD0 P50/TxD0 NC 17 (N) P97/WAIT/SAD0 P97/WAIT/SDA0 P97/SDA0 VCC 18 P96/ø/EXCL P96/ø/EXCL P96/ø/EXCL NC 19 AS/IOS AS/IOS P95/CS1 FA16 20 HWR HWR P94/IOW FA15 21 RD RD P93/IOR WE 22 P92/IRQ0 P92/IRQ0 P92/IRQ0 VSS 23 P91/IRQ1 P91/IRQ1 P91/IRQ1 VCC 24 P90/LWR/IRQ2/ ADTRG P90/LWR/IRQ2/ ADTRG P90/IRQ2/ADTRG/ ECS2 VCC 25 (B) PE7 PE7 PE7 NC 26 (B) PE6 PE6 PE6 NC 16 NC Pin Name Pin No. Expanded modes Single-Chip Modes Flash Memory TFP-144 Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Programmer Mode 27 (B) PE5 PE5 PE5 NC 28 (B) PE4 PE4 PE4 NC 29 (B) PE3 PE3 PE3 NC 30 (B) PE2 PE2 PE2 NC 31 (B) PE1 PE1 PE1 NC 32 (B) PE0 PE0 PE0 NC 33 (B) PA7/CIN15/KIN15/ PS2CD PA7/A23/CIN15/ KIN15/PS2CD PA7/CIN15/KIN15/ PS2CD NC 34 (B) PA6/CIN14/KIN14/ PS2CC PA6/A22/CIN14/ KIN14/PS2CC PA6/CIN14/KIN14/ PS2CC NC 35 (B) PA5/CIN13/KIN13/ PS2BD PA5/A21/CIN13/ KIN13/PS2BD PA5/CIN13/KIN13/ PS2BD NC 36 VCCB VCCB VCCB VCC 37 (B) PA4/CIN12/KIN12/ PS2BC PA4/A20/CIN12/ KIN12/PS2BC PA4/CIN12/KIN12/ PS2BC NC 38 (B) PA3/CIN11/KIN11/ PS2AD PA3/A19/CIN11/ KIN11/PS2AD PA3/CIN11/KIN11/ PS2AD NC 39 (B) PA2/CIN10/KIN10/ PS2AC PA2/A18/CIN10/ KIN10/PS2AC PA2/CIN10/KIN10/ PS2AC NC 40 (B) PA1/CIN9/KIN9 PA1/A17/CIN9/KIN9 PA1/CIN9/KIN9 NC 41 (B) PA0/CIN8/KIN8 PA0/A16/CIN8/KIN8 PA0/CIN8/KIN8 NC 42 VSS VSS VSS VSS 43 (B) PF7 PF7 PF7 NC 44 (B) PF6 PF6 PF6 NC 45 (B) PF5 PF5 PF5 NC 46 (B) PF4 PF4 PF4 NC 47 (B) PF3 PF3 PF3 NC 48 (B) PF2 PF2 PF2 NC 49 (B) PF1 PF1 PF1 NC 50 (B) PF0 PF0 PF0 NC 51 (B) PG7 PG7 PG7 NC 52 (B) PG6 PG6 PG6 NC 17 Pin Name Pin No. Expanded modes Single-Chip Modes Flash Memory TFP-144 Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Programmer Mode 53 (B) PG5 PG5 PG5 NC 54 (B) PG4 PG4 PG4 NC 55 (B) PG3 PG3 PG3 NC 56 (B) PG2 PG2 PG2 NC 57 (B) PG1 PG1 PG1 NC 58 (B) PG0 PG0 PG0 NC 59 PD7 PD7 PD7 NC 60 PD6 PD6 PD6 NC 61 PD5 PD5 PD5 NC 62 PD4 PD4 PD4 NC 63 PD3 PD3 PD3 NC 64 PD2 PD2 PD2 NC 65 PD1 PD1 PD1 NC 66 PD0 PD0 PD0 NC 67 AVSS AVSS AVSS VSS 68 P70/AN0 P70/AN0 P70/AN0 NC 69 P71/AN1 P71/AN1 P71/AN1 NC 70 P72/AN2 P72/AN2 P72/AN2 NC 71 P73/AN3 P73/AN3 P73/AN3 NC 72 P74/AN4 P74/AN4 P74/AN4 NC 73 P75/AN5 P75/AN5 P75/AN5 NC 74 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 NC 75 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 NC 76 AVCC AVCC AVCC VCC 77 AVref AVref AVref VCC 78 P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX P60/FTCI/CIN0/ KIN0/HFBACKI/ TMIX NC 79 P61/FTOA/CIN1/ KIN1/VSYNCO P61/FTOA/CIN1/ KIN1/VSYNCO P61/FTOA/CIN1/ KIN1/VSYNCO NC 80 P62/FTIA/CIN2/ P62/FTIA/CIN2/ KIN2/VSYNCI/TMIY KIN2/VSYNCI/TMIY P62/FTIA/CIN2/ KIN2/VSYNCI/TMIY NC 18 Pin Name Pin No. Expanded modes Single-Chip Modes Flash Memory TFP-144 Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Programmer Mode 81 P63/FTIB/CIN3/ KIN3/VFBACKI P63/FTIB/CIN3/ KIN3/VFBACKI P63/FTIB/CIN3/ KIN3/VFBACKI NC 82 P64/FTIC/CIN4/ KIN4/CLAMPO P64/FTIC/CIN4/ KIN4/CLAMPO P64/FTIC/CIN4/ KIN4/CLAMPO NC 83 P65/FTID/CIN5/KIN5 P65/FTID/CIN5/KIN5 P65/FTID/CIN5/KIN5 NC 84 P66/FTOB/CIN6/ KIN6/IRQ6 P66/FTOB/CIN6/ KIN6/IRQ6 P66/FTOB/CIN6/ KIN6/IRQ6 NC 85 P67/TMOX/CIN7/ KIN7/IRQ7 P67/TMOX/CIN7/ KIN7/IRQ7 P67/TMOX/CIN7/ KIN7/IRQ7 VSS 86 VCC VCC VCC VCC 87 PC7 PC7 PC7 NC 88 PC6 PC6 PC6 NC 89 PC5 PC5 PC5 NC 90 PC4 PC4 PC4 NC 91 PC3 PC3 PC3 NC 92 PC2 PC2 PC2 NC 93 PC1 PC1 PC1 NC 94 PC0 PC0 PC0 NC 95 VSS VSS VSS VSS 96 A15 P27/A15/PW15/ CBLANK P27/PW15/CBLANK CE 97 A14 P26/A14/PW14 P26/PW14 FA14 98 A13 P25/A13/PW13 P25/PW13 FA13 99 A12 P24/A12/PW12 P24/PW12 FA12 100 A11 P23/A11/PW11 P23/PW11 FA11 101 A10 P22/A10/PW10 P22/PW10 FA10 102 A9 P21/A9/PW9 P21/PW9 OE 103 A8 P20/A8/PW8 P20/PW8 FA8 104 A7 P17/A7/PW7 P17/PW7 FA7 105 A6 P16/A6/PW6 P16/PW6 FA6 106 A5 P15/A5/PW5 P15/PW5 FA5 107 A4 P14/A4/PW4 P14/PW4 FA4 19 Pin Name Pin No. Expanded modes Single-Chip Modes Flash Memory TFP-144 Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Programmer Mode 108 A3 P13/A3/PW3 P13/PW3 FA3 109 A2 P12/A2/PW2 P12/PW2 FA2 110 A1 P11/A1/PW1 P11/PW1 FA1 111 VSS VSS VSS VSS 112 A0 P10/A0/PW0 P10/PW0 FA0 113 PB7/D7/WUE7 PB7/D7/WUE7 PB7/WUE7 NC 114 PB6/D6/WUE6 PB6/D6/WUE6 PB6/WUE6 NC 115 PB5/D5/WUE5 PB5/D5/WUE5 PB5/WUE5 NC 116 PB4/D4/WUE4 PB4/D4/WUE4 PB4/WUE4 NC 117 PB3/D3/WUE3 PB3/D3/WUE3 PB3/WUE3/CS4 NC 118 PB2/D2/WUE2 PB2/D2/WUE2 PB2/WUE2/CS3 NC 119 PB1/D1/WUE1 PB1/D1/WUE1 PB1/HIRQ4/WUE1/ LSCI NC 120 PB0/D0/WUE0 PB0/D0/WUE0 PB0/HIRQ3/WUE0/ LSMI NC 121 D8 D8 P30/HDB0/LAD0 FO0 122 D9 D9 P31/HDB1/LAD1 FO1 123 D10 D10 P32/HDB2/LAD2 FO2 124 D11 D11 P33/HDB3/LAD3 FO3 125 D12 D12 P34/HDB4/LFRAME FO4 126 D13 D13 P35/HDB5/LRESET FO5 127 D14 D14 P36/HDB6/LCLK FO6 128 D15 D15 P37/HDB7/SERIRQ FO7 129 P80 P80 P80/HA0/PME NC 130 P81 P81 P81/CS2/GA20 NC 131 P82 P82 P82/HIFSD/ CLKRUN NC 132 P83 P83 P83/LPCPD NC 133 P84/IRQ3/TxD1 P84/IRQ3/TxD1 P84/IRQ3/TxD1 NC 134 P85/IRQ4/RxD1 P85/IRQ4/RxD1 P85/IRQ4/RxD1 NC 20 Pin Name Pin No. Expanded modes Single-Chip Modes Flash Memory TFP-144 Mode 1 Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Programmer Mode 135 P86/IRQ5/SCK1/ SCL1 P86/IRQ5/SCK1/ SCL1 P86/IRQ5/SCK1/ SCL1 NC 136 P40/TMCI0/TxD2/ IrTxD P40/TMCI0/TxD2/ IrTxD P40/TMCI0/TxD2/ IrTxD NC 137 P41/TMO0/RxD2/ IrRxD P41/TMO0/RxD2/ IrRxD P41/TMO0/RxD2/ IrRxD NC 138 P42/TMRI0/SCK2/ SDA1 P42/TMRI0/SCK2/ SDA1 P42/TMRI0/SCK2/ SDA1 NC 139 VSS VSS VSS VSS 140 X1 X1 X1 NC 141 X2 X2 X2 NC 142 RESO RESO RESO NC 143 XTAL XTAL XTAL XTAL 144 EXTAL EXTAL EXTAL EXTAL 21 1.3.3 Pin Functions Table 1.3 summarizes the functions of the H8S/2149 and H8S/2169 pins. Table 1.3 Pin Functions Pin No. Type Symbol FP-100B, TFP-100B TFP-144 I/O Power VCC 59 1, 86 Input Power: For connection to the power supply. Connect the VCC pin to the system power supply. VCL 9 13 Input Power supply stabilization capacitance: Connect the VCL pin to the system power supply together with the VCC pin. VCCB 4 36 Input Input/output buffer power: The power supply for the port A, E, F, and G input/output buffer. VSS 15, 70, 71, 7, 42, 95, Input 92 111, 139 Ground: For connection to the power supply (0 V). Connect all VSS pins to the system power supply (0 V). XTAL 2 143 Input Connected to a crystal oscillator. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. EXTAL 3 144 Input Connected to a crystal oscillator. The EXTAL pin can also input an external clock. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. ø 17 EXCL 17 18 Input External subclock input: Input a 32.768 kHz external subclock. X1 — 140 Input Leave open. X2 — 141 Input Leave open. Clock 22 Name and Function Output System clock: Supplies the system clock to external devices. Pin No. Type Symbol Operating MD1 mode MD0 control FP-100B, TFP-100B TFP-144 I/O 5 6 9 10 Input Name and Function Mode pins: These pins set the operating mode. The relation between the settings of pins MD1 and MD0 and the operating mode is shown below. These pins should not be changed while the MCU is operating. Operating MD1 MD0 Mode Description 0 1 Mode 1 Normal Expanded mode with on-chip ROM disabled 1 0 Mode 2 Advanced Expanded mode with on-chip ROM enabled or singlechip mode 1 1 Mode 3 Normal Expanded mode with on-chip ROM enabled or singlechip mode System control Address bus RES 1 8 Input RESO 100 142 Output Reset output: Outputs reset signal to external device. STBY 8 12 Input Reset input: When this pin is driven low, the chip is reset. Standby: When this pin is driven low, a transition is made to hardware standby mode. A23 to A16 10, 11, 20, 33, 34, 21, 30, 31, 35, 37, 47, 48 38, 39, 40, 41 Output Address bus (advanced): Outputs address when 16-Mbyte space is used. A15 to A0 Output Address bus: These pins output an address. 60–67, 72–79 96-110, 112 23 Pin No. Type Symbol Data bus D15 to D8 Bus control Interrupt Signals 16-bit freerunning timer (FRT) 24 FP-100B, TFP-100B TFP-144 I/O 89–82 128-121 Input/ output Name and Function Data bus (upper): Bidirectional data bus. Used for 8-bit data and upper byte of 16-bit data. D7 to D0 57, 58, 68, 113-130 Input/ 69, 80, 81, output 90, 91 Data bus (lower): Bidirectional data bus. Used for lower byte of 16-bit data. WAIT 16 17 Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3state address space. RD 22 21 Output Read: When this pin is low, it indicates that the external address space is being read. HWR 19 20 Output High write: When this pin is low, it indicates that the external address space is being written to. The upper half of the data bus is valid. LWR 25 24 Output Low write: When this pin is low, it indicates that the external address space is being written to. The lower half of the data bus is valid. AS/IOS 18 19 Output Address strobe: When this pin is low, it indicates that address output on the address bus is valid. NMI 7 11 Input Nonmaskable interrupt: Requests a nonmaskable interrupt. IRQ0 to IRQ7 23–25, 97–99, 34, 35 22-24, Input 133-135, 84, 85 Interrupt request 0 to 7: These pins request a maskable interrupt. FTCI 26 78 Input FRT counter clock input: Input pin for an external clock signal for the free-running counter (FRC). FTOA 27 79 Output FRT output compare A output: The output compare A output pin. FTOB 34 84 Output FRT output compare B output: The output compare B output pin. FTIA 28 80 Input FRT input capture A input: The input capture A input pin. Pin No. Type Symbol FP-100B, TFP-100B TFP-144 I/O 16-bit freerunning timer (FRT) FTIB 29 81 Input FRT input capture B input: The input capture B input pin. FTIC 32 82 Input FRT input capture C input: The input capture C input pin. FTID 33 83 Input FRT input capture D input: The input capture D input pin. 8-bit timer (TMR0, TMR1, TMRX, TMRY) TMO0 TMO1 TMOX 50 53 35 137 3 85 Output Compare-match output: TMR0, TMR1, and TMRX compare-match output pins. TMCI0 TMCI1 49 52 136 2 Input Counter external clock input: Input pins for the external clock input to the TMR0 and TMR1 counters. TMRI0 TMRI1 51 54 138 4 Input Counter external reset input: TMR0 and TMR1 counter reset input pins. TMIX TMIY 26 28 78 80 Input Counter external clock input/reset input: Dual function as TMRX and TMRY counter clock input pin and reset input pin. PWM timer (PWM) PW15 to PW0 60–67, 72–79 96-110, 112 Output PWM timer output: PWM timer pulse output pins. 14-bit PWM timer (PWMX) PWX0 PWX1 55 56 5 6 Output PWMX timer output: PWM D/A pulse output pins. Serial communication interface (SCI0, SCI1, SCI2) TxD0 TxD1 TxD2 14 97 49 16 133 136 Output Transmit data: Data output pins. RxD0 RxD1 RxD2 13 98 50 15 134 137 Input Receive data: Data input pins. SCK0 SCK1 SCK2 12 99 51 14 135 138 Input/ Ouput Serial clock: Clock input/output pins. IrTxD 49 136 Output IrDA transmit data/receive data: Input and output pins for data encoded for IrDA use. IrRxD 50 137 Input SCI with IrDA (SCI2) Name and Function The SCK0 output type is NMOS push-pull. 25 Pin No. Type Symbol FP-100B, TFP-100B TFP-144 I/O Keyboard buffer controller (PS2) PS2AC PS2BC PS2CC 31 21 11 39 37 34 Input/ Ouput PS2 clock: Keyboard buffer controller synchronization clock input/output pins. PS2AD PS2BD PS2CD 30 20 10 38 35 33 Input/ Ouput PS2 data: Keyboard buffer controller data input/output pins. 89–82 128-121 Input/ Ouput Host interface data bus: Bidirectional 8-bit bus for accessing the host interface (XBS). 18, 94, 25, 81, 80 19, 130, 24, 118, 117 Input Chip select 1, 2, 3, 4: Input pins for selecting host interface (XBS) channel 1 to 4. IOR 22 21 Input I/O read: Input pin that enables reading from the host interface (XBS). IOW 19 20 Input I/O write: Input pin that enables writing to the host interface (XBS). HA0 93 129 Input Command/data: Input pin that indicates whether an access is a data access or command access. GA20 94 130 Output GATE A20: A20 gate control signal output pin. HIRQ11 HIRQ1 HIRQ12 HIRQ3 HIRQ4 52 53 54 91 90 2 3 4 120 119 Output Host interrupt 11, 1, 12, 3, 4: Output pins for interrupt requests to the host. HIFSD 95 131 Input 85–82 124-121 Input/ Ouput Address/data: LPC command, address, and data input/output pins. 86 125 Input LPC frame: Input pin that indicates the start of an LPC cycle or forced termination of an abnormal LPC cycle. LRESET 87 126 Input LPC reset: Input pin that indicates an LPC reset. LCLK 88 127 Input LPC clock: The LPC clock input pin. Host HDB7 to interface HDB0 (HIF:XBS) CS1, CS2 ECS2, CS3, CS4 Host LAD3 to interface LAD0 (HIF:LPC) LFRAME 26 Name and Function Host interface shutdown: Control input pin used to place host interface (XBS) input/output pins in the high-impedance / cutoff state. Pin No. Type Symbol Host SERIRQ interface (HIF:LPC) FP-100B, TFP-100B TFP-144 I/O Input/ Ouput Serial host interrupt: Input/output pin for LPC serialized host interrupts (HIRQ1, HIRQ6, HIRQ9 to HIRQ12). LSCI, 90, 91, 93 LSMI, PME 119, 120, Input/ 129 Ouput LSCI, LSMI, power management event: LPC auxiliary output pins. Functionally, they are general I/O ports. GA20 94 130 Input/ Ouput GATE A20: A20 gate control signal output pin. Output state monitoring input is possible. CLKRUN 95 131 Input/ Ouput LCLK clock run: Input/output pin that requests the start of LCLK operation when LCLK is stopped. LPCPD 96 132 Input LPC power-down: Input pin that controls LPC module shutdown. Input Keyboard input: Matrix keyboard input pins. P10 to P17 and P20 to P27 are used as key-scan outputs. This allows a maximum 16-output × 16-input, 256-key matrix to be configured. 91, 90, 81, 120-113 Input 80, 69, 68, 58, 57 Wakeup event input: Wakeup event input pins. These pins have a similar function to the keyboard input pins, and allow the same kind of wakeup as key-wakeup from various sources. 45–38 Keyboard KIN0 to control KIN15 WUE0 to WUE7 A/D AN7 to converter AN0 (ADC) 89 128 Name and Function 78-85, 26–29, 41-37, 32–35, 48, 47, 31, 35-33 30, 21, 20, 11, 10 68-75 Input Analog input: A/D converter analog input pins. CIN0 to CIN15 78-85, 26–29, 41-37, 32–35, 48, 47, 31, 35-33 30, 21, 20, 11, 10 Input Expansion A/D input: Expansion A/D input pins can be connected to the A/D converter, but since they are also used as digital input/output pins, precision will fall. ADTRG 25 24 Input A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. 44 45 74 75 Output Analog output: D/A converter analog output pins. D/A DA0 converter DA1 (DAC) 27 Pin No. Type Symbol A/D AVCC converter FP-100B, TFP-100B TFP-144 I/O 37 76 Input D/A converter Name and Function Analog power: The analog power supply pin for the A/D converter and D/A converter. When the A/D and D/A converters are not used, this pin should be connected to the system power supply (+5 V or +3 V). AVref 36 77 Input Analog reference voltage: The reference power supply pin for the A/D converter and D/A converter. When the A/D and D/A converters are not used, this pin should be connected to the system power supply (+5 V or +3 V). Timer connection I 2C bus interface (IIC) AVSS 46 67 Input Analog ground: The ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). VSYNCI HSYNCI CSYNCI VFBACKI HFBACKI 28 52 54 29 26 80 2 4 81 78 Input Timer connection input: Timer connection synchronous signal input pins. VSYNCO HSYNCO CLAMPO CBLANK 27 53 32 60 79 3 82 96 Output Timer connection output: Timer connection synchronous signal output pins. SCL0 SCL1 12 99 14 135 Input/ I 2C clock input/output (channels 0 and Output 1): I 2C clock I/O pins. These pins have a bus drive function. The SCL0 output type is NMOS opendrain. SDA0 SDA1 16 51 17 138 Input/ I 2C data input/output (channels 0 and 1): Output I 2C data I/O pins. These pins have a bus drive function. The SDA0 output type is NMOS opendrain. I/O ports 28 P17–P10 72–79 104-110, Input/ Port 1: Eight input/output pins. The data 112 Output direction of each pin can be selected in the port 1 data direction register (P1DDR). These pins have built-in MOS input pullups, and also have LED drive capability. Pin No. Type Symbol FP-100B, TFP-100B TFP-144 I/O I/O ports P27–P20 60–67 96-103 P37–P30 89–82 128-121 Input/ Port 3: Eight input/output pins. The data Output direction of each pin can be selected in the port 3 data direction register (P3DDR). These pins have built-in MOS input pullups, and also have LED drive capability. P47–P40 56–49 6-2, Input/ Port 4: Eight input/output pins. The data 138-136 Output direction of each pin can be selected in the port 4 data direction register (P4DDR). P52–P50 12–14 14-16 Input/ Port 5: Three input/output pins. The data Output direction of each pin can be selected in the port 5 data direction register (P5DDR). P52 is an NMOS push-pull output. P67–P60 35–32 29–26 85-78 Input/ Port 6: Eight input/output pins. The data Output direction of each pin can be selected in the port 6 data direction register (P6DDR). These pins have built-in MOS input pullups. P77–P70 45–38 75-68 Input P86–P80 99–93 135-129 Input/ Port 8: Seven input/output pins. The data Output direction of each pin can be selected in the port 8 data direction register (P8DDR). P97–P90 16–19 22–25 17-24 Input/ Port 9: Eight input/output pins. The data Output direction of each pin (except P96) can be selected in the port 9 data direction register (P9DDR). P97 is an NMOS push-pull output. PA7–PA0 10, 11, 20, 33-35, 21, 30, 31, 37-41 47, 48 Input/ Port A: Eight input/output pins. The data Output direction of each pin can be selected in the port A data direction register (PADDR). These pins have built-in MOS input pullups. These are VCCB drive pins. PB7–PB0 57, 58, 68, 113-120 Input/ Port B: Eight input/output pins. The data 69, 80, 81, Output direction of each pin can be selected in the 90, 91 port B data direction register (PBDDR). These pins have built-in MOS input pullups. Name and Function Input/ Port 2: Eight input/output pins. The data Output direction of each pin can be selected in the port 2 data direction register (P2DDR). These pins have built-in MOS input pullups, and also have LED drive capability. Port 7: Eight input pins. 29 Pin No. Type Symbol FP-100B, TFP-100B TFP-144 I/O I/O ports PC7–PC0 — 87-94 Input/ Port C: Eight input/output pins. The data Output direction of each pin can be selected in the port C data direction register (PCDDR). These pins have built-in MOS input pullups. PD7–PD0 — 59-66 Input/ Port D: Eight input/output pins. The data Output direction of each pin can be selected in the port D data direction register (PDDDR). These pins have built-in MOS input pullups. PE7–PE0 — 25-32 Input/ Port E: Eight input/output pins. The data Output direction of each pin can be selected in the port E data direction register (PEDDR). These pins have built-in MOS input pullups. These are VCCB drive pins. PF7–PF0 — 43-50 Input/ Port F: Eight input/output pins. The data Output direction of each pin can be selected in the port F data direction register (PFDDR). These pins have built-in MOS input pullups. These are VCCB drive pins. PG7–PG0 — 51-58 Input/ Port G: Eight input/output pins. The data Output direction of each pin can be selected in the port G data direction register (PGDDR). These pins have built-in MOS input pullups. These are VCCB drive pins. 30 Name and Function Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features. • Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs • General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions • Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] • 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes (4 Gbytes architecturally) 31 • High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 10 MHz 8/16/32-bit register-register add/subtract: 100 ns 8 × 8-bit register-register multiply: 1200 ns 16 ÷ 8-bit register-register divide: 1200 ns 16 × 16-bit register-register multiply: 2000 ns 32 ÷ 16-bit register-register divide: 2000 ns • Two CPU operating modes Normal mode Advanced mode • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU. • Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. • Number of execution states The number of execution states of the MULXU and MULXS instructions differ as follows. Number of Execution States Instruction Mnemonic H8S/2600 H8S/2000 MULXU MULXU.B Rs, Rd 3 12 MULXU.W Rs, ERd 4 20 MULXS.B Rs, Rd 4 13 MULXS.W Rs, ERd 5 21 MULXS There are also differences in the address space, EXR register functions, power-down state, etc., depending on the product. 32 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers Eight 16-bit extended registers, and one 8-bit control register, have been added. • Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. • Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. • Higher speed Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. • Additional control register One 8-bit control register has been added. • Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. • Higher speed Basic instructions execute twice as fast. 33 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16 Mbytes for the program area and a maximum of 4 Gbytes for the data area). The mode is selected by the mode pins of the microcontroller. Normal mode Maximum 64 kbytes for program and data areas combined CPU operating modes Advanced mode Maximum 16 Mbytes for program and data areas combined Figure 2.1 CPU Operating Modes (1) Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. 34 Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. 35 Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) SP CCR CCR* PC (16 bits) (a) Subroutine Branch (b) Exception Handling Note: * Ignored when returning. Figure 2.3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. 36 Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved H'00000007 H'00000008 Exception vector table H'0000000B (Reserved for system use) H'0000000C H'00000010 Reserved Exception vector 1 Figure 2.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. 37 Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP Reserved PC (24 bits) (a) Subroutine Branch CCR SP PC (24 bits) (b) Exception Handling Figure 2.5 Stack Structure in Advanced Mode 38 2.3 Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2169 or H8S/2149 H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Figure 2.6 Memory Map 39 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 07 07 0 ER0 E0 R0H R0L ER1 E1 R1H R1L ER2 E2 R2H R2L ER3 E3 R3H R3L ER4 E4 R4H R4L ER5 E5 R5H R5L ER6 E6 R6H R6L ER7 (SP) E7 R7H R7L Control Registers (CR) 23 0 PC 7 6 5 4 3 2 1 0 EXR* T — — — — I2 I1 I0 7 6 5 4 3 2 1 0 CCR I UI H U N Z V C Legend: SP: PC: EXR: T: I2 to I0: CCR: I: UI: Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Note: * Does not affect operation in the H8S/2169 or H8S/2149. Figure 2.7 CPU Registers 40 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8bit registers. Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected independently. • Address registers • 32-bit registers • 16-bit registers • 8-bit registers E registers (extended registers) (E0 to E7) RH registers (R0H to R7H) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) Figure 2.8 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack. 41 Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR): An 8-bit register. In the H8S/2169 or H8S/2149, this register does not affect operation. Bit 7—Trace Bit (T): This bit is reserved. In the H8S/2169 or H8S/2149, this bit does not affect operation. Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1. Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits are reserved. In the H8S/2169 or H8S/2149, these bits do not affect operation. (3) Condition-Code Register (CCR): This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. 42 Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, refer to section 5, Interrupt Controller. Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to store the carry The carry flag is also used as a bit accumulator by bit-manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, List of Instructions. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. 43 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.10 shows the data formats in general registers. Data Type General Register Data Format 1-bit data RnH 7 0 7 6 5 4 3 2 1 0 Don’t care Don’t care 7 0 7 6 5 4 3 2 1 0 4 3 7 0 Upper digit Lower digit Don’t care Don’t care 4 3 7 0 Upper digit Lower digit 1-bit data 4-bit BCD data 4-bit BCD data Byte data RnL RnH RnL RnH 7 0 Don’t care MSB Byte data LSB RnL 7 0 Don’t care MSB Figure 2.10 General Register Data Formats 44 LSB Data Type General Register Word data Rn Data Format 15 0 MSB Word data En 15 0 MSB Longword data LSB ERn 31 MSB LSB 16 15 En 0 Rn LSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.10 General Register Data Formats (cont) 45 2.5.2 Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address Data Format 7 1-bit data Address L Byte data Address L MSB Word data 7 0 6 5 4 2 1 0 LSB Address 2M MSB Address 2M + 1 Longword data 3 LSB Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.11 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. 46 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* 5 LDM* , STM* 1 MOVFPE* , MOVTPE* Arithmetic operations Types BWL 5 WL 5 3 Size L 3 B ADD, SUB, CMP, EG BWL ADDX, SUBX, DAA, DAS B INC, DEC BWL ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS BW EXTU, EXTS WL TAS* 4 19 B Logic operations AND, OR, XOR, NOT BWL 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8 Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR B 14 Branch Bcc* 2, JMP, BSR, JSR, RTS — 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9 Block data transfer EEPMOV — 1 Total: 65 types Notes: B: byte size; W: word size; L: longword size. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in the H8S/2169 or H8S/2149. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 5. Only registers ER0 to ER6 should be used when using the STM/LDM instruction. 47 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 — @–ERn/@ERn+ @(d:32,ERn) BWL — BWL — — — — — — — — — — — — — — — — — WL LDM* 3, STM* 3 — — — — — — — — — — — — — L — — — — — — — B — — — — — — MOVFPE* , MOVTPE* 1 Logic operations B POP, PUSH 1 Arithmetic operations @ERn BWL BWL BWL BWL BWL BWL @aa:16 MOV @aa:8 Data transfer Rn Instruction #xx Function @(d:16,ERn) Addressing Modes ADD, CMP — — — — — — — — — — — — WL BWL — — — — — — — — — — — — ADDX, SUBX B B — — — — — — — — — — — — ADDS, SUBS — L — — — — — — — — — — — — INC, DEC — BWL — — — — — — — — — — — — DAA, DAS — B — — — — — — — — — — — — MULXU, DIVXU — BW — — — — — — — — — — — — MULXS, DIVXS — BW — — — — — — — — — — — — NEG — BWL — — — — — — — — — — — — EXTU, EXTS — WL — — — — — — — — — — — — TAS* 2 — — B — — — — — — — — — — — — — — — — — — — — — — — — — — — SUB AND, OR, XOR NOT BWL BWL BWL BWL — BWL — — — — — — — — Shift — BWL — — — — — — — — — — — — Bit manipulation — B B — — — B B — B — — — — Branch Bcc, BSR — — — — — — — — — JMP, JSR — — — — — — — — — — — RTS — — — — — — — — — — — 48 — — — — — — System control — @@aa:8 @(d:16,PC) @(d:8,PC) @aa:32 @aa:24 @aa:16 @aa:8 @–ERn/@ERn+ @(d:32,ERn) @ERn Rn Instruction #xx Function @(d:16,ERn) Addressing Modes TRAPA — — — — — — — — — — — — — RTE — — — — — — — — — — — — — SLEEP — — — — — — — — — — — — — LDC B B W W W W — W — W — — — — STC — B W W W W — W — W — — — — ANDC, ORC, XORC B — — — — — — — — — — — — — NOP — — — — — — — — — — — — — — — — — — — — — — — — — — Block data transfer BW Legend: B: Byte W: Word L: Longword Notes: 1. Cannot be used in the H8S/2169 or H8S/2149. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction. 49 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction × Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Logical exclusive OR → Move ¬ NOT (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 50 Table 2.3 Instructions Classified by Function Type Instruction Size* 1 Function Data transfer MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in the H8S/2169 or H8S/2149. MOVTPE B Cannot be used in the H8S/2169 or H8S/2149. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn → @–SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP. 3 L @SP+ → Rn (register list) Pops two or more general registers from the stack. STM* 3 L Rn (register list) → @–SP Pushes two or more general registers onto the stack. ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) ADDX SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. INC DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) ADDS SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. DAA DAS B Rd decimal adjust → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. LDM* Arithmetic operations 51 Type Instruction Size* 1 Function Arithmetic operations MULXU B/W Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. MULXS B/W Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. DIVXU B/W Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. NEG B/W/L 0 – Rd → Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. TAS B @ERd – 0, 1 → (<bit 7> of @ERd)* 2 Tests memory contents, and sets the most significant bit (bit 7) to 1. 52 Type Instruction Size* 1 Function Logic operations AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L ¬ (Rd) → (Rd) Takes the one's complement (logical complement) of general register contents. SHAL SHAR B/W/L Rd (shift) → Rd Performs an arithmetic shift on general register contents. A 1-bit or 2-bit shift is possible. SHLL SHLR B/W/L Rd (shift) → Rd Performs a logical shift on general register contents. A 1-bit or 2-bit shift is possible. ROTL ROTR B/W/L Rd (rotate) → Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. ROTXL ROTXR B/W/L Rd (rotate) → Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. BSET B 1 → (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ¬ (<bit-No.> of <EAd>) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. Shift operations Bitmanipulation instructions 53 Type Instruction Size* 1 Function Bitmanipulation instructions BAND B C ∧ (<bit-No.> of <EAd>) → C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIAND B C ∧ ¬ (<bit-No.> of <EAd>) → C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B C ∨ ¬ (<bit-No.> of <EAd>) → C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BXOR B C ⊕ (<bit-No.> of <EAd>) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ (<bit-No.> of <EAd>) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (<bit-No.> of <EAd>) → C Transfers a specified bit in a general register or memory operand to the carry flag. BILD B ¬ (<bit-No.> of <EAd>) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C → (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B ¬ C → (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. 54 Type Instruction Size* 1 Function Branch instructions Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never BHI High C∨Z=0 BLS Low or same C∨Z=1 BCC(BHS) Carry clear (high or same) C=0 BCS(BLO) Carry set (low) C=1 BNE Not equal Z=0 BEQ Equal Z=1 BVC Overflow clear V=0 BVS Overflow set V=1 BPL Plus N=0 BMI Minus N=1 BGE Greater or equal N⊕V=0 BLT Less than N⊕V=1 BGT Greater than Z∨(N ⊕ V) = 0 BLE Less or equal Z∨(N ⊕ V) = 1 JMP — Branches unconditionally to a specified address. BSR — Branches to a subroutine at a specified address. JSR — Branches to a subroutine at a specified address. RTS — Returns from a subroutine System control TRAPA instructions RTE — Starts trap-instruction exception handling. — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. 55 Size* 1 Function System control LDC instructions B/W (EAs) → CCR, (EAs) → EXR Moves contents of a general register or memory or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR → (EAd), EXR → (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP — PC + 2 → PC Only increments the program counter. EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Type Block data transfer instructions Instruction Block transfer instruction. Transfers the number of data bytes specified by R4L or R4 from locations starting at the address indicated by ER5 to locations starting at the address indicated by ER6. After the transfer, the next instruction is executed. Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction. 56 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. Condition Field: Specifies the branching condition of Bcc instructions. Figure 2.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc Figure 2.12 Instruction Formats (Examples) 57 2.6.5 Notes on Use of Bit-Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit manipulation, then write back the byte of data. Caution is therefore required when using these instructions on a register containing write-only bits, or a port. The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling routine, etc. 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.4 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment Register indirect with pre-decrement @ERn+ @–ERn 5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 58 Register Indirect—@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand in memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. • Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). 59 Table 2.5 indicates the accessible absolute address ranges. Table 2.5 Absolute Address Access Ranges Absolute Address Data address Normal Mode Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) Program instruction address H'000000 to H'FFFFFF 24 bits (@aa:24) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. 60 Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. 61 Table 2.6 Effective Address Calculation No. Addressing Mode and Instruction Format 1 Register direct (Rn) op 2 Effective Address Calculation Effective Address (EA) Operand is general register contents. rm rn Register indirect (@ERn) 31 0 3 24 23 0 Don’t care General register contents op 31 r Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) 31 0 General register contents 31 op r disp 31 0 0 Sign extension 4 24 23 Don’t care disp Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ 31 0 24 23 0 Don’t care General register contents op 31 r 1, 2, or 4 • Register indirect with pre-decrement @–ERn 31 0 General register contents 31 op r Operand Size Byte Word Longword 62 24 23 Don’t care Value Added 1 2 4 1, 2, or 4 0 No. Addressing Mode and Instruction Format 5 Absolute address Effective Address Calculation Effective Address (EA) @aa:8 31 op 24 23 Don’t care abs @aa:16 abs @aa:24 31 op 24 23 0 H'FFFF 24 23 16 15 Sign Don’t extencare sion 31 op 87 0 0 Don’t care abs @aa:32 op 31 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 24 23 0 Don’t care Operand is immediate data. IMM Program-counter relative @(d:8, PC)/@(d:16, PC) 0 23 PC contents op disp 23 Sign extension 0 disp 31 24 23 0 Don’t care 63 No. Addressing Mode and Instruction Format 8 Memory indirect @@aa:8 • Effective Address Calculation Effective Address (EA) Normal mode op abs 31 87 0 abs H'000000 31 24 23 Don’t care 16 15 0 H'00 0 15 Memory contents • Advanced mode op abs 31 87 H'000000 31 abs 0 Memory contents 64 0 31 24 23 Don’t care 0 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode, sub-active mode, sub-sleep mode, and watch mode. Figure 2.14 Processing States 65 End of bus request Bus request Program execution state End of bus request SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1 Bus request Bus-released state End of exception handling SLEEP instruction with LSON = 0, SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt Software standby mode RES = high Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For details, refer to section 24, Power-Down State. Figure 2.15 State Transitions 2.8.2 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. All interrupts are disabled in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 14, Watchdog Timer. 66 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. Types of Exception Handling and Their Priority: Exception handling is performed for resets, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.7 Exception Handling Types and Priority Priority Type of Exception Detection Timing Start of Exception Handling High Reset Synchronized with clock Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. Interrupt End of instruction execution or end of exception-handling sequence* 1 When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence. Trap instruction When TRAPA instruction is executed Exception handling starts when a trap (TRAPA) instruction is executed.* 2 Low Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 2. Trap instruction exception handling is always accepted in the program execution state. Reset Exception Handling: After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. Interrupt Exception Handling and Trap Instruction Exception Handling: When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. 67 Figure 2.16 shows the stack after exception handling ends. Normal mode SP Advanced mode CCR CCR* SP PC (16 bits) CCR PC (24 bits) Note: * Ignored when returning. Figure 2.16 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, all CPU internal operations are halted. There is one other bus master in addition to the CPU: the data transfer controller (DTC). For further details, refer to section 6, Bus Controller. 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode, and watch mode. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode, the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. Subactive mode, subsleep mode, and watch mode are power-down modes that use subclock input. For details, refer to section 24, Power-Down State. 68 Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) and the LSON bit in the low-power control register (LPWRCR) are both cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1 and the LSON bit in LPWRCR and the PSS bit in the WDT1 timer control/status register (TCSR) are both cleared to 0. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. 2.9 Basic Timing 2.9.1 Overview The CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is referred to as a “state.” The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows the pin states. 69 Bus cycle T1 ø Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.17 On-Chip Memory Access Cycle Bus cycle T1 ø Address bus Unchanged AS High RD High HWR, LWR High Data bus High impedance Figure 2.18 Pin States during On-Chip Memory Access 70 2.9.3 On-Chip Supporting Module Access Timing (Internal I/O Register 1 and 2) The on-chip supporting modules (Internal I/O Register 1 and 2) are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules (Internal I/O Register 1 and 2). Figure 2.20 shows the pin states. Bus cycle T1 T2 ø Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.19 On-Chip Supporting Module (Internal I/O Register 1 and 2)Access Cycle 71 Bus cycle T1 T2 ø Address bus Unchanged AS High RD High HWR, LWR High Data bus High impedance Figure 2.20 Pin States during On-Chip Supporting Module (Internal I/O Register 1 and 2) Access 72 2.9.4 On-Chip Supporting Module Access Timing (Internal I/O Register 3) The on-chip supporting modules (internal I/O register 3) are accessed in three states. The data bus is 8 bits wide. Figure 2.21 shows the access timing fo the on-chip supporting modules (internal I/O register 3). Figure 2.22 shows the pin states. Bus cycle T1 T2 T3 φ Internal address bus Read access Write access Address Internal read signal Internal data bus Read data Internal write signal Internal data bus Write data Figure 2.21 On-Chip Supporting Module (Internal I/O Register 3) Access Cycle Bus cycle T1 T2 T3 φ Address bus Unchanged AS High RD High HWR, LWR High Data bus High impedance Figure 2.22 Pin States during On-Chip Supporting Module (Internal I/O Register 3) Access 73 2.9.5 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. 2.10 Usage Note 2.10.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. 2.10.2 STM/LDM Instruction ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored by one STM/LDM instruction. The following ranges can be specified in the register list. Two registers: ER0—ER1, ER2—ER3, or ER4—ER5 Three registers: ER0—ER2 or ER4—ER6 Four registers: ER0—ER3 The STM/LDM instruction including ER7 is not generated by the Hitachi H8S and H8/300 series C/C++compilers. 74 Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8S/2169 or H8S/2149 has three operating modes (modes 1 to 3). These modes enable selection of the CPU operating mode and enabling/disabling of on-chip ROM, by setting the mode pins (MD1 and MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection MCU Operating Mode MD1 0 0 1 2 1 MD0 CPU Operating Mode Description On-Chip ROM 0 — — — 1 Normal Expanded mode with on-chip ROM disabled Disabled 0 Advanced Expanded mode with on-chip ROM enabled Enabled Single-chip mode 3 1 Normal Expanded mode with on-chip ROM enabled Single-chip mode The CPU’s architecture allows for 4 Gbytes of address space, but the H8S/2169 or H8S/2149 actually access a maximum of 16 Mbytes. Mode 1 is an externally expanded mode that allows access to external memory and peripheral devices. With modes 2 and 3, operation begins in single-chip mode after reset release, but a transition can be made to external expansion mode by setting the EXPE bit in MDCR. The H8S/2169 or H8S/2149 can only be used in modes 1 to 3. These means that the mode pins must select one of these modes. Do not changes the inputs at the mode pins during operation. 75 3.1.2 Register Configuration The H8S/2169 or H8S/2149 has a mode control register (MDCR) that indicates the inputs at the mode pins (MD1 and MD0), a system control register (SYSCR) and bus control register (BCR) that control the operation of the MCU, and a serial/timer control register (STCR) that controls the operation of the supporting modules. Table 3.2 summarizes these registers. Table 3.2 MCU Registers Name Abbreviation R/W Initial Value Address* Mode control register MDCR R/W Undetermined H'FFC5 System control register SYSCR R/W H'09 H'FFC4 Bus control register BCR R/W H'D7 H'FFC6 Serial/timer control register STCR R/W H'00 H'FFC3 Note: * Lower 16 bits of the address. 3.2 Register Descriptions 3.2.1 Mode Control Register (MDCR) 7 6 5 4 3 2 1 0 EXPE — — — — — MDS1 MDS0 Initial value —* 0 0 0 0 0 —* —* Read/Write R/W* — — — — — R R Bit Note: * Determined by pins MD1 and MD0. MDCR is an 8-bit read-only register that indicates the operating mode setting and the current operating mode of the MCU. The EXPE bit is initialized in coordination with the mode pin states by a reset and in hardware standby mode. 76 Bit 7—Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, this bit is fixed at 1 and cannot be modified. In modes 2 and 3, this bit has an initial value of 0, and can be read and written. Bit 7 EXPE Description 0 Single chip mode is selected 1 Expanded mode is selected Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0. Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate the input levels at pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0 correspond to MD1 and MD0. MDS1 and MDS0 are read-only bits—they cannot be written to. The mode pin (MD1 and MD0) input levels are latched into these bits when MDCR is read. 3.2.2 System Control Register (SYSCR) 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W Bit SYSCR is an 8-bit readable/writable register that performs selection of system pin functions, reset source monitoring, interrupt control mode selection, NMI detected edge selection, supporting module pin location selection, supporting module register access control, and RAM address space control. Only bits 7, 6, 3, 1, and 0 are described here. For a detailed description of these bits, refer also to the description of the relevant modules (host interface, bus controller, watchdog timer, RAM, etc.). For information on bits 5, 4, and 2, see section 5.2.1, System Control Register (SYSCR). SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Chip Select 2 Enable (CS2E): Specifies the location of the host interface control pin (CS2). For details, see section 18A, Host Interface (XBS). 77 Bit 6—IOS Enable (IOSE): Controls the function of the AS/IOS pin in expanded mode. Bit 6 IOSE Description 0 The AS/IOS pin functions as the address strobe pin (Low output when accessing an external area) 1 (Initial value) The AS/IOS pin functions as the I/O strobe pin (Low output when accessing a specified address from H'(FF)F000 to H'(FF)F7FF) Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow. Bit 3 XRST Description 0 A reset is generated by watchdog timer overflow 1 A reset is generated by an external reset (Initial value) Bit 1—Host Interface Enable (HIE): This bit controls CPU access to the host interface (HIF:XBS) data registers and control registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2), the keyboard controller and MOS input pull-up control registers (KMIMR, KMPCR, and KMIMRA), the 8-bit timer (channel X and Y) data registers and control registers (TCRX/TCRY, TCSRX/TCSRY, TICRR/TCORAY, TICRF/TCORBY, TCNTX/TCNTY, TCORC/TISR, TCORAX, and TCORBX), and the timer connection control registers (TCONRI, TCONRO, TCONRS, and SEDGR). Bit 1 HIE Description 0 In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection control registers, is permitted 1 In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to host interface data registers and control registers, and keyboard controller and MOS input pull-up control registers, is permitted 78 (Initial value) Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip RAM is enabled 3.2.3 (Initial value) Bus Control Register (BCR) 7 Bit ICIS1 6 5 4 3 ICIS0 BRSTRM BRSTS1 BRSTS0 2 1 0 — IOS1 IOS0 Initial value 1 1 0 1 0 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W BCR is an 8-bit readable/writable register that specifies the external memory space access mode, and the I/O area range when the AS pin is designated for use as the I/O strobe. For details on bits 7 to 2, see section 6.2.1, Bus Control Register (BCR). BCR is initialized to H'D7 by a reset and in hardware standby mode. Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): These bits specify the addresses for which the AS/IOS pin output goes low when IOSE = 1. BCR Bit 1 Bit 0 IOS1 IOS0 Description 0 0 The AS/IOS pin output goes low in accesses to addresses H'(FF)F000 to H'(FF)F03F 1 The AS/IOS pin output goes low in accesses to addresses H'(FF)F000 to H'(FF)F0FF 0 The AS/IOS pin output goes low in accesses to addresses H'(FF)F000 to H'(FF)F3FF 1 The AS/IOS pin output goes low in accesses to addresses H'(FF)F000 to H'(FF)F7FF (Initial value) 1 79 3.2.4 Serial Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 IICS IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 0 0 0 R/W R/W Initial value 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode (when the on-chip IIC option is included), an on-chip flash memory control, and also selects the TCNT input clock. For details of functions other than register access control, see the descriptions of the relevant modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit. STCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 5—I2C Control (IICS, IICX1, IICX0): These bits control the operation of the I2C bus interface and others when the on-chip IIC option is included. For details, see section 16, I2C Bus Interface. Bit 4—I2C Master Enable (IICE): Controls CPU access to the I2C bus interface data registers and control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR), the PWMX data registers and control registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL), and the SCI control registers (SMR, BRR, and SCMR). Bit 4 IICE Description 0 Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used for SCI1 control register access Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used for SCI2 control register access Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used for SCI0 control register access 1 Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used for IIC1 data register and control register access Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used for PWMX data register and control register access Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used for IIC0 data register and control register access 80 (Initial value) Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), the power-down mode control registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and the supporting module control register (PCSR and SYSCR2). Bit 3 FLSHE Description 0 Addresses H'(FF)FF80 to H'(FF)FF87 are used for power-down mode control register and supporting module control register access 1 Addresses H'(FF)FF80 to H'(FF)FF87 are used for flash memory control register access (Initial value) Bit 2—Reserved: Do not write 1 to this bit. Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12, 8-Bit Timers. 81 3.3 Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled. Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing the ABW bit to 0 in the WSCR register makes port B a data bus. 3.3.2 Mode 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use external addresses. When the EXPE bit in MDCR is set to 1, ports 1, 2 and A function as input ports after a reset. They can be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing the ABW bit to 0 in the WSCR register makes port B a data bus. 3.3.3 Mode 3 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled. After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use external addresses. When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They can be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing the ABW bit to 0 in the WSCR register makes port B a data bus. In this operating mode, the available amount of on-chip ROM in products with 64 kbytes or more of ROM is limited to 56 kbytes. 82 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1 to 3, 9, A, and B vary depending on the operating mode. Table 3.3 shows their functions in each operating mode. Table 3.3 Pin Functions in Each Mode Port Mode 1 Mode 2 Mode 3 Port 1 A P*/A P*/A Port 2 A P*/A P*/A Port A P P*/A P Port 3 D P*/D P*/D Port B P*/D P*/D P*/D P97 P*/C P*/C P*/C P96 C */P P*/C P*/C P95 to P93 C P*/C P*/C P92 to P91 P P P P90 P*/C P*/C P*/C Port C to Port G P P P Port 9 Legend: P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *: After reset 3.5 Memory Map in Each Operating Mode Figure 3.1 shows memory maps for each of the operating modes. The address space is 64 kbytes in modes 1 and 3 (normal modes), and 16 Mbytes in mode 2 (advanced mode). The on-chip ROM capacity is 64 kbytes, but only 56 kbytes are available in mode 3 (normal mode). Do not access reserved area. For details, see section 6, Bus Controller. 83 Mode 1 (normal expanded mode with on-chip ROM disabled) Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) H'0000 H'0000 External address space Mode 3/EXPE = 0 (normal single-chip mode) H'0000 On-chip ROM H'DFFF On-chip ROM H'DFFF External address space H'E080 H'E080 Reserved area* H'E880 H'E080 Reserved area* H'E880 On-chip RAM* H'EFFF External address H'F000 space H'F7FF H'F800 Internal I/O registers 3 H'FE4F H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O registers 1 H'FFFF Reserved area H'E880 On-chip RAM* H'EFFF External address H'F000 space H'F7FF H'F800 Internal I/O registers 3 H'FE4F H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O registers 1 H'FFFF On-chip RAM H'EFFF H'F800 H'FE4F Internal I/O registers 3 H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes) H'FF7F H'FF80 Internal I/O registers 1 H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.1 H8S/2169 or H8S/2149 Memory Map in Each Operating Mode 84 Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 H'000000 On-chip ROM On-chip ROM H'00FFFF H'00FFFF Reserved area H'01FFFF H'020000 H'FFE080 Reserved area H'01FFFF External address space Reserved area* H'FFE880 On-chip RAM* H'FFEFFF External address H'FFF000 space H'FFF7FF H'FFF800 Internal I/O registers 3 H'FFFE4F H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)* H'FFFF7F H'FFFF80 Internal I/O registers 1 H'FFFFFF H'FFE080 Reserved area H'FFE880 On-chip RAM H'FFEFFF H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.1 H8S/2169 or H8S/2149 Memory Map in Each Operating Mode (cont) 85 86 Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR. Table 4.1 Exception Types and Priority Priority Exception Type Start of Exception Handling High Reset Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. Trace* 1 Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1. Interrupt Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued.* 2 Direct transition Started by a direct transition resulting from execution of a SLEEP instruction. Low Trap instruction (TRAPA)*3 Started by execution of a trap instruction (TRAPA). Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. (They cannot be used in the H8S/2169 or H8S/2149.) Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in the program execution state. 87 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Sources and Vector Table The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Reset Trace Exception sources (Cannot be used in the H8S/2169 or H8S/2149) External interrupts: NMI, IRQ7 to IRQ0 Interrupts Internal interrupts: interrupt sources in on-chip supporting modules Direct transition Trap instruction Figure 4.1 Exception Sources 88 Table 4.2 Exception Vector Table Vector Address* 1 Exception Source Vector Number Normal Mode Advanced Mode Reset 0 H'0000 to H'0001 H'0000 to H'0003 Reserved for system use 1 H'0002 to H'0003 H'0004 to H'0007 2 H'0004 to H'0005 H'0008 to H'000B 3 H'0006 to H'0007 H'000C to H'000F 4 H'0008 to H'0009 H'0010 to H'0013 5 H'000A to H'000B H'0014 to H'0017 6 H'000C to H'000D H'0018 to H'001B 7 H'000E to H'000F H'001C to H'001F 8 H'0010 to H'0011 H'0020 to H'0023 9 H'0012 to H'0013 H'0024 to H'0027 10 H'0014 to H'0015 H'0028 to H'002B 11 H'0016 to H'0017 H'002C to H'002F 12 H'0018 to H'0019 H'0030 to H'0033 13 H'001A to H'001B H'0034 to H'0037 14 H'001C to H'001D H'0038 to H'003B 15 H'001E to H'001F H'003C to H'003F IRQ0 16 H'0020 to H'0021 H'0040 to H'0043 IRQ1 17 H'0022 to H'0023 H'0044 to H'0047 IRQ2 18 H'0024 to H'0025 H'0048 to H'004B IRQ3 19 H'0026 to H'0027 H'004C to H'004F IRQ4 20 H'0028 to H'0029 H'0050 to H'0053 IRQ5 21 H'002A to H'002B H'0054 to H'0057 IRQ6 22 H'002C to H'002D H'0058 to H'005B IRQ7 23 H'002E to H'002F H'005C to H'005F 24 107 H'0030 to H'0031 H'00CE to H'00DF H'0060 to H'0063 H'019C to H'01BF Direct transition External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt Internal interrupt* 2 Notes: 1. Lower 16 bits of the address. 2. For details on internal interrupt vectors, see section 5.3.3, Interrupt Exception Vector Table. 89 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the MCU enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. The MCU can also be reset by overflow of the watchdog timer. For details, see section 14, Watchdog Timer. 4.2.2 Reset Sequence The MCU enters the reset state when the RES pin goes low. To ensure that the chip is reset, hold the RES pin low for at least 20 ms when powering on. To reset the chip during operation, hold the RES pin low for at least 20 states. For pin states in a reset, see Appendix D.1, Pin States at Reset. When the RES pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: [1] The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit is set to 1 in CCR. [2] The reset exception vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.2 and 4.3 show examples of the reset sequence. 90 Fetch of Vector Internal first program fetch processing instruction ø RES Internal address bus (1) (3) Internal read signal Internal write signal Internal data bus High (2) (4) (1) Reset exception vector address ((1) = H'0000) (2) Start address (contents of reset exception vector address) (3) Start address ((3) = (2)) (4) First program instruction Figure 4.2 Reset Sequence (Mode 3) 91 Vector fetch Internal processing Fetch of first program instruction * * * (1) (3) (5) ø RES Address bus RD High HWR, LWR (2) D15 to D8 (4) (6) (1) (3) Reset exception vector address ((1) = H'0000, (3) = H'0001) (2) (4) Start address (contents of reset exception vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Note: * 3 program wait states are inserted. Figure 4.3 Reset Sequence (Mode 1) 4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP). 92 4.3 Interrupts Interrupt exception handling can be requested by nine external sources (NMI and IRQ7 to IRQ0) from 31 input pins (NMI, IRQ7 to IRQ0, and KIN15 to KIN0, WUE7 to WUE0), and internal sources in the on-chip supporting modules. Figure 4.4 shows the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit free-running timer (FRT), 8-bit timer (TMR), serial communication interface (SCI), data transfer controller (DTC), A/D converter (ADC), host interface (HIF:XBS, LPC), keyboard buffer controller (PS2), and I2C bus interface. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI and address break to either three priority/mask levels to enable multiplexed interrupt control. For details on interrupts, see section 5, Interrupt Controller. External interrupts Interrupts Internal interrupts NMI (1) IRQ7 to IRQ0 (8) WDT* (2) FRT (7) TMR (10) SCI (12) DTC (1) ADC (1) HIF:XBS(4), LPC(4) PS2 (3) IIC (3) Other (1) Note: Numbers in parentheses are the numbers of interrupt sources. * When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. Figure 4.4 Interrupt Sources and Number of Interrupts 93 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.3 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.3 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 1 — — — 1 1 1 — — Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. 94 4.5 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR* PC (16 bits) Interrupt control modes 0 and 1 Note: * Ignored on return. Figure 4.5 (1) Stack Status after Exception Handling (Normal Mode) SP CCR PC (24bits) Interrupt control modes 0 and 1 Note: * Ignored on return. Figure 4.5 (2) Stack Status after Exception Handling (Advanced Mode) 95 4.6 Notes on Use of the Stack When accessing word data or longword data, the chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what happens when the SP value is odd. CCR SP R1L SP PC PC SP H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF TRAP instruction executed MOV.B R1L, @–ER7 SP set to H'FFFEFF Data saved above SP Contents of CCR lost Legend: CCR: Condition-code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.6 Operation when SP Value is Odd 96 Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The MCU control interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI and address break. • Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. • Thirty-one external interrupt pins (nine external sources) NMI is the highest-priority interrupt, and is accepted at all times. A rising or falling edge at the NMI pin can be selected for the NMI interrupt. Falling edge, rising edge, or both edge detection, or level sensing, at pins IRQ7 to IRQ0 can be selected for interrupts IRQ7 to IRQ0. The IRQ6 interrupt is shared by the interrupt from the IRQ6 pin and eight external interrupt inputs (KIN7 to KIN0), and the IRQ7 interrupt is shared by the interrupt from the IRQ7 pin and sixteen external interrupt inputs (KIN15 to KIN8 and WUE7 to WUE0). KIN15 to KIN0 and WUE7 to WUE0 can be masked individually by the user program. • DTC control DTC activation is controlled by means of interrupts. 97 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5.1. CPU INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input IRQ input unit ISR ISCR IER Interrupt request Vector number Priority determination I, UI Internal interrupt requests SWDTEND to IBFI3 ICR Interrupt controller Legend: ISCR: IER: ISR: ICR: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt control register System control register Figure 5.1 Block Diagram of Interrupt Controller 98 CCR 5.1.3 Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol I/O Function Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or falling edge can be selected External interrupt requests 7 to 0 IRQ7 to IRQ0 Input Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected. Key input interrupt requests 15 to 0 KIN15 to KIN0 Input Maskable external interrupts: falling edge or level sensing can be selected. Wakeup event interrupt requests 7 to 0 WUE7 to WUE0 Input Maskable external interrupts: falling edge or level sensing can be selected. 99 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.2 Interrupt Controller Registers Name Abbreviation R/W Initial Value Address* 1 System control register SYSCR R/W H'09 H'FFC4 IRQ sense control register H ISCRH R/W H'00 H'FEEC IRQ sense control register L ISCRL R/W H'00 H'FEED IRQ enable register IER R/W H'00 H'FFC2 H'00 H'FEEB IRQ status register ISR R/(W)* 2 Keyboard matrix interrupt mask KMIMR register R/W H'BF H'FFF1* 3 Keyboard matrix interrupt mask KMIMRA register A R/W H'FF H'FFF3* 3 Wakeup event interrupt mask register B WUEMRB R/W H'FF H'FE44 Interrupt control register A ICRA R/W H'00 H'FEE8 Interrupt control register B ICRB R/W H'00 H'FEE9 Interrupt control register C ICRC R/W H'00 H'FEEA Address break control register ABRKCR R/W H'00 H'FEF4 Break address register A BARA R/W H'00 H'FEF5 Break address register B BARB R/W H'00 H'FEF6 Break address register C BARC R/W H'00 H'FEF7 Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, for flag clearing. 3. When setting KMIMR and KMIMRA, the HIE bit in SYSCR must be set to 1 and the MSTP2 bit in MSTPCRL must be cleared to 0. 100 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W Bit SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI, among other functions. Only bits 5, 4, and 2 are described here; for details on the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of four interrupt control modes for the interrupt controller. The INTM1 bit must not be set to 1. Bit 5 Bit 4 INTM1 INTM0 Interrupt Control Mode Description 0 0 0 Interrupts are controlled by I bit 1 1 Interrupts are controlled by I and UI bits and ICR 0 2 Cannot be used in the chip 1 3 Cannot be used in the chip 1 (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 2 NMIEG Description 0 Interrupt request generated at falling edge of NMI input 1 Interrupt request generated at rising edge of NMI input (Initial value) 101 5.2.2 Interrupt Control Registers A to C (ICRA to ICRC) Bit 7 6 5 4 3 2 1 0 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 0 0 0 R/W R/W Initial value 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for interrupts other than NMI and address break. The correspondence between ICR settings and interrupt sources is shown in table 5.3. The ICR registers are initialized to H'00 by a reset and in hardware standby mode. Bit n—Interrupt Control Level (ICRn): Sets the control level for the corresponding interrupt source. Bit n ICRn Description 0 Corresponding interrupt source is control level 0 (non-priority) 1 Corresponding interrupt source is control level 1 (priority) (Initial value) (n = 7 to 0) Table 5.3 Correspondence between Interrupt Sources and ICR Settings Bits Register 7 6 5 4 3 2 1 ICRA IRQ1 IRQ2 IRQ4 IRQ6 DTC IRQ3 IRQ5 IRQ7 Watchdog Watchdog timer 0 timer 1 — — 8-bit 8-bit 8-bit timer timer timer channel 0 channel 1 channels X, Y IRQ0 ICRB A/D Freeconverter running timer ICRC SCI SCI SCI IIC IIC — channel 0 channel 1 channel 2 channel 0 channel 1 102 HIF:LPC 0 HIF:XBS Keyboard buffer controller — 5.2.3 IRQ Enable Register (IER) Bit 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E 0 0 0 R/W R/W Initial value 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE Description 0 IRQn interrupt disabled 1 IRQn interrupt enabled (Initial value) (n = 7 to 0) 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) • ISCRH Bit 15 14 13 12 11 10 9 8 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 • ISCRL Bit IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 103 ISCRH and ISCRL are 8-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. Each of the ISCR registers is initialized to H'00 by a reset and in hardware standby mode. ISCRH Bits 7 to 0, ISCRL Bits 7 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) ISCRH Bits 7 to 0 ISCRL Bits 7 to 0 IRQ7SCB to IRQ0SCB IRQ7SCA to IRQ0SCA 0 0 Interrupt request generated at IRQ7 to IRQ0 input low level (Initial value) 1 Interrupt request generated at falling edge of IRQ7 to IRQ0 input 0 Interrupt request generated at rising edge of IRQ7 to IRQ0 input 1 Interrupt request generated at both falling and rising edges of IRQ7 to IRQ0 input 1 5.2.5 Description IRQ Status Register (ISR) Bit 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F 0 0 0 R/(W)* R/(W)* Initial value 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. 104 Bit n IRQnF Description 0 [Clearing conditions] • • • 1 (Initial value) Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF When interrupt exception handling is executed while low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high* When IRQn interrupt exception handling is executed while falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)* [Setting conditions] • • • • When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in IRQn input while falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in IRQn input while rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in IRQn input while both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 7 to 0) Note: 5.2.6 * When a product, in which a DTC is incorporated, is used in the following settings, the corresponding flag bit is not automatically cleared even when exception handing, which is a clear condition, is executed and the bit is held at 1. (1) When DTCEA3 is set to 1(ADI is set to an interrupt source), of IRQ4F flag is not automatically cleared. (2) When DTCEA2 is set to 1(ICIA is set to an interrupt source), clearing of IRQ5F flag is not automatically cleared. (3) When DTCEA1 is set to 1(ICIB is set to an interrupt source), clearing of IRQ6F flag is not automatically cleared. (4) When DTCEA0 is set to 1(OCIA is set to an interrupt source), clearing of IRQ7F flag is not automatically cleared. When activation interrupt sources of DTC and IRQ interrupts are used with the above combinations, clear the interrupt flag by software in the interrupt handling routine of the corresponding IRQ. Keyboard Matrix Interrupt Mask Register (KMIMR) Bit 7 6 5 4 3 2 1 0 KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial value 1 0 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W KMIMR is an 8-bit readable/writable register that performs mask control for the keyboard matrix interrupt inputs (pins KIN7 to KIN0) and pin IRQ6. To enable key-sense input interrupts from multiple pin inputs in keyboard matrix scanning/sensing, clear the corresponding mask bits to 0. 105 KMIMR is initialized to H'BF by a reset or in hardware standby mode and only IRQ6 (KIN6) input is enabled. Bits 7 to 0—Keyboard Matrix Interrupt Mask (KMIMR7 to KMIMR0): These bits control key-sense input interrupt requests (KIN7 to KIN0). Bits 7 to 0 KMIMR7 to KMIMR0 Description 0 Key-sense input interrupt requests enabled 1 Key-sense input interrupt requests disabled (Initial value)* Note: * However, the initial value of KMIMR6 is 0, as KMIMR6 bit masks the IRQ6 interrupt request and enables key-sense input. 5.2.7 Keyboard Matrix Interrupt Mask Register A (KMIMRA) Wakeup Event Interrupt Mask Registr B (WUEMRB) Bit 7 6 5 4 3 2 KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 1 0 KMIMR9 KMIMR8 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit WUEMR7 WUEMR6 WUEMR5 WUEMR4 WUEMR3 WUEMR2 WUEMR1 WUEMR0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W KMIMRA is an 8-bit readable/writable register that performs mask control for the keyboard matrix interrupt inputs (pins KIN15 to KIN8). To enable key-sense input interrupts from multiple pin inputs in keyboard matrix scanning/sensing, clear the corresponding mask bits to 0. KMIMRA is initialized to H'FF by a reset and in hardware standby mode. Bits 7 to 0—Keyboard Matrix Interrupt Mask (KMIMR15 to KMIMR8): These bits control key-sense input interrupt requests (KIN15 to KIN8). 106 Bits 7 to 0 KMIMR15 to KMIMR8 Description 0 Key-sense input interrupt requests enabled 1 Key-sense input interrupt requests disabled (Initial value) WUEMRB is an 8-bit readable/writable register that performs mask control for the wakeup event interrupt inputs (pins WUE7 to WUE0). A wakeup event interrupt is enabled by clearing the corresponding mask bit to 0. WUEMRB is initialized to H'FF by a reset and in hardware standby mode. Bits 7 to 0—Wakeup Event Interrupt Mask (WUEMR7 to WUEMR0): These bits control wakeup event interrupt requests (WUE7 to WUE0). Bits 7 to 0 WUEMR7 to WUEMR0 Description 0 Wakeup event interrupt requests enabled 1 Wakeup event interrupt requests disabled (Initial value) Figure 5.2 shows the relationship between interrupts IRQ7 and IRQ6, interrupts KIN15 to KIN0, interrupts WUE7 to WUE0, and registers KMIMR, KMIMRA, and WUEMRB. 107 KMIMR0 (initial value 1) P60/KIN0 KMIMR5 (initial value 1) P65/KIN5 IRQ6 internal signal KMIMR6 (initial value 0) P66/KIN6/IRQ6 KMIMR7 (initial value 1) P67/KIN7/IRQ7 KMIMR8 (initial value 1) PA0/KIN8 IRQ6E IRQ6SC IRQ6 interrupt IRQ7 internal signal KMIMR9 (initial value 1) PA1/KIN9 WUEMR7 (initial value 1) PB7/WUE7 Edge/level selection enable/disable circuit IRQ7E IRQ7SC Edge/level selection enable/disable circuit IRQ7 interrupt Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0, Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB If any of bits KMIMR15 to KMIMR8 or WUEMRB7 to WUEMRB0 is cleared to 0, interrupt input from the IRQ7 pin will be ignored. When pins KIN7 to KIN0, KIN15 to KIN8, or WUE7 to WUE0 are used as key-sense interrupt input pins or wakeup event interrupt input pins, either lowlevel sensing or falling-edge sensing must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6 or IRQ7). 108 5.2.8 Address Break Control Register (ABRKCR) Bit 7 6 5 4 3 2 1 0 CMF — — — — — — BIE Initial value 0 0 0 0 0 0 0 0 Read/Write R — — — — — — R/W ABRKCR is an 8-bit readable/writable register that performs address break control. ABRKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Condition Match Flag (CMF): This is the address break source flag, used to indicate that the address set by BAR has been prefetched. When the CMF flag and BIE flag are both set to 1, an address break is requested. Bit 7 CMF Description 0 [Clearing condition] When address break interrupt exception handling is executed 1 (Initial value) [Setting condition] When address set by BARA to BARC is prefetched while BIE = 1 Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 0. Bit 0—Break Interrupt Enable (BIE): Selects address break enabling or disabling. Bit 0 BIE Description 0 Address break disabled 1 Address break enabled (Initial value) 109 5.2.9 Break Address Registers A, B, C (BARA, BARB, BARC) Bit BARA 7 6 5 4 3 2 1 0 A23 A22 A21 A20 A19 A18 A17 A16 0 0 0 Initial value 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit BARB 7 6 5 4 3 2 1 0 A7 A6 A5 A4 A3 A2 A1 — Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W — Bit BARC BAR consists of three 8-bit readable/writable registers (BARA, BARB, and BARC), and is used to specify the address at which an address break is to be executed. Each of the BAR registers is initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. BARA Bits 7 to 0—Address 23 to 16 (A23 to A16) BARB Bits 7 to 0—Address 15 to 8 (A15 to A8) BARC Bits 7 to 1—Address 7 to 1 (A7 to A1) These bits specify the address at which an address break is to be executed. BAR bits A23 to A1 are compared with internal address bus lines A23 to A1, respectively. The address at which the first instruction byte is located should be specified as the break address. Occurrence of the address break condition may not be recognized for other addresses. In normal mode, no comparison is made with address lines A23 to A16. BARC Bit 0—Reserved: This bit cannot be modified and is always read as 0. 110 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts. 5.3.1 External Interrupts There are nine external interrupt sources from 33 input pins (31 actual pins): NMI, IRQ7 to IRQ0, KIN15 to KIN0, and WUE7 to WUE0. WUE7 to WUE0 and KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6, and IRQ2 to IRQ0 can be used to restore the H8S/2149 chip from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode and the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: • Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. • Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. • The interrupt control level can be set with ICR. • The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.3. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit S Q IRQn interrupt request R IRQn input Clear signal Note: n: 7 to 0 Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 111 Figure 5.4 shows the timing of IRQnF setting. ø IRQn input pin IRQnF Figure 5.4 Timing of IRQnF Setting The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. Therefore, when a pin is used as an external interrupt input pin, clear the corresponding DDR bit to 0 and do not use the pin as an I/O pin for another function. When IRQ6 pin is assigned as IRQ6 interrupt input pin, then clear the KMIMR6 bit to 0. When the IRQ7 pin is used as the IRQ7 interrupt input pin, bits KMIMR15 to KMIMR8 and WUEMRB7 to WUEMRB0 must all be set to 1. If any of these bits is cleared to 0, an IRQ7 interrupt input from the IRQ7 pin will be ignored. As interrupt request flags IRQ7F to IRQ0F are set when the setting condition is met, regardless of the IER setting, only the necessary flags should be referenced. Interrupts KIN15 to KIN0 and WUE7 to WUE0: Interrupts KIN15 to KIN0 and WUE7 to WUE0 are requested by input signals at pins KIN15 to KIN0 and WUE7 to WUE0. When any of pins KIN15 to KIN0 or WUE7 to WUE0 are used as key-sense inputs or wakeup events, the corresponding KMIMR or WUEMR bits should be cleared to 0 to enable those key-sense input interrupts or wakeup event interrupts. The remaining unused key-sense input KMIMR bits and WUEMR bits should be set to 1 to disable those interrupts. Interrupts WUE7 to WUE0 and KIN15 to KIN8 correspond to the IRQ7 interrupt, and interrupts KIN7 to KIN0 correspond to the IRQ6 interrupt. Interrupt request generation pin conditions, interrupt request enabling, interrupt control level setting, and interrupt request status indications, are all in accordance with the IRQ7 and IRQ6 interrupt settings. When pins KIN7 to KIN0, KIN15 to KIN8, or WUE7 to WUE0 are used as key-sense interrupt or wakeup event interrupt input pins, either low-level sensing or falling-edge sensing must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6 or IRQ7). 112 5.3.2 Internal Interrupts There are 48 sources for internal interrupts from on-chip supporting modules, plus one software interrupt source (address break). • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If any one of these is set to 1, an interrupt request is issued to the interrupt controller. • The interrupt control level can be set by means of ICR. • The DTC can be activated by an FRT, TMR, SCI, or other interrupt request. When the DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect. 5.3.3 Interrupt Exception Vector Table Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of ICR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4. Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Source Vector Address Vector Normal Number Mode Advanced Mode ICR Priority 7 H'000E H'00001C High 16 H'0020 H'000040 ICRA7 IRQ1 17 H'0022 H'000044 ICRA6 IRQ2 IRQ3 18 19 H'0024 H'0026 H'000048 H'00004C ICRA5 IRQ4 IRQ5 20 21 H'0028 H'002A H'000050 H'000054 ICRA4 IRQ6, KIN7 to KIN0 IRQ7, KIN15 to KIN8, WUE7 to WUE0 22 23 H'002C H'002E H'000058 H'00005C ICRA3 Interrupt Source NMI IRQ0 External pin SWDTEND (software activation interrupt end) DTC 24 H'0030 H'000060 ICRA2 WOVI0 (interval timer) Watchdog timer 0 25 H'0032 H'000064 ICRA1 WOVI1 (interval timer) Watchdog timer 1 26 H'0034 H'000068 ICRA0 Low 113 Vector Address Interrupt Source Origin of Interrupt Source Vector Normal Number Mode Advanced Mode ICR Priority Address break (PC break) — 27 H'0036 H'00006C High ADI (A/D conversion end) A/D 28 H'0038 H'000070 Reserved — 29 to 47 H'003A to H'005E H'000074 to H'0000BC ICIA (input capture A) ICIB (input capture B) ICIC (input capture C) ICID (input capture D) OCIA (output compare A) OCIB (output compare B) FOVI (overflow) Reserved Free-running 48 timer 49 50 51 52 53 54 55 H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0000C0 H'0000C4 H'0000C8 H'0000CC H'0000D0 H'0000D4 H'0000D8 H'0000DC Reserved — 56 to 63 H'0070 to H'007E H'0000E0 to H'0000FC CMIA0 (compare-match A) CMIB0 (compare-match B) OVI0 (overflow) Reserved 8-bit timer channel 0 64 65 66 67 H'0080 H'0082 H'0084 H'0086 H'000100 H'000104 H'000108 H'00010C ICRB3 CMIA1 (compare-match A) CMIB1 (compare-match B) OVI1 (overflow) Reserved 8-bit timer channel 1 68 69 70 71 H'0088 H'008A H'008C H'008E H'000110 H'000114 H'000118 H'00011C ICRB2 CMIAY (compare-match A) CMIBY (compare-match B) OVIY (overflow) ICIX (input capture X) 8-bit timer channels Y, X 72 73 74 75 H'0090 H'0092 H'0094 H'0096 H'000120 H'000124 H'000128 H'00012C ICRB1 76 77 78 79 H'0098 H'009A H'009C H'009E H'000130 H'000134 H'000138 H'00013C ICRB0 80 81 82 83 H'00A0 H'00A2 H'00A4 H'00A6 H'000140 H'000144 H'000148 H'00014C ICRC7 IBF1 (IDR1 reception completed) Host IBF2 (IDR2 reception completed) interface IBF3 (IDR3 reception completed) (XBS) IBF4 (IDR4 reception completed) ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0) 114 SCI channel 0 ICRB7 ICRB6 Low Interrupt Source Origin of Interrupt Source Vector Address Vector Normal Number Mode Advanced Mode ICR Priority ERI1 (receive error 1) RXI1 (reception completed 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) SCI channel 1 84 85 86 87 H'00A8 H'00AA H'00AC H'00AE H'000150 H'000154 H'000158 H'00015C ICRC6 High ERI2 (receive error 2) RXI2 (reception completed 2) TXI2 (transmit data empty 2) TEI2 (transmission end 2) SCI channel 2 88 89 90 91 H'00B0 H'00B2 H'00B4 H'00B6 H'000160 H'000164 H'000168 H'00016C ICRC5 IICI0 (1-byte transmission/ reception completed) DDCSWI (format switch) IIC channel 0 92 H'00B8 H'000170 ICRC4 93 H'00BA H'000174 IICI1 (1-byte transmission/ reception completed) Reserved IIC channel 1 94 H'00BC H'000178 95 H'00BE H'00017C PS2IA (reception completed A) PS2IB (reception completed B) PS2IC (reception completed C) Reserved Keyboard buffer controller (PS2) 96 97 98 99 H'00C0 H'00C2 H'00C4 H'00C6 H'000180 H'000184 H'000188 H'00018C Reserved — 100 to 103 H'00C8 to H'00CE H'000190 to H'00019C 104 105 106 107 H'00D8 H'00DA H'00DC H'00DE H'0001B0 H'0001B4 H'0001B8 H'0001BC Host ERRI (transfer error, etc.) IBFI1 (IDR1 reception completed) interface IBFI2 (IDR2 reception completed) (LPC) IBFI3 (IDR3 reception completed) ICRC3 ICRB0 ICRC1 Low 115 5.4 Address Breaks 5.4.1 Features With the H8S/2169 or H8S/2149, it is possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an address break interrupt is generated, address break interrupt exception handling is executed. This function can be used to detect the beginning of execution of a bug location in the program, and branch to a correction routine. 5.4.2 Block Diagram A block diagram of the address break function is shown in figure 5.5. BAR Comparator ABRKCR Match signal Control logic Address break interrupt request Internal address Prefetch signal (internal signal) Figure 5.5 Block Diagram of Address Break Function 116 5.4.3 Operation ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the address is prefetched, and the interrupt controller determines the interrupt priority. When the interrupt is accepted, interrupt exception handling is started on completion of the currently executing instruction. With an address break interrupt, interrupt mask control by the I and UI bits in the CPU’s CCR is ineffective. The register settings when the address break function is used are as follows. 1. Set the break address in bits A23 to A1 in BAR. 2. Set the BIE bit in ABRKCR to 1 to enable address breaks. An address break will not be requested if the BIE bit is cleared to 0. When the setting condition occurs, the CMF flag in ABRKCR is set to 1 and an interrupt is requested. If necessary, the source should be identified in the interrupt handling routine. 5.4.4 Usage Notes • With the address break function, the address at which the first instruction byte is located should be specified as the break address. Occurrence of the address break condition may not be recognized for other addresses. • In normal mode, no comparison is made with address lines A23 to A16. • If a branch instruction (Bcc, BSR), jump instruction (JMP, JSR), RTS instruction, or RTE instruction is located immediately before the address set in BAR, execution of this instruction will output a prefetch signal for that address, and an address break may be requested. This can be prevented by not making a break address setting for an address immediately following one of these instructions, or by determining within the interrupt handling routine whether interrupt handling was initiated by a genuine condition occurrence. • As an address break interrupt is generated by a combination of the internal prefetch signal and address, the timing of the start of interrupt exception handling depends on the content and execution cycle of the instruction at the set address and the preceding instruction. Figure 5.6 shows some address timing examples. 117 • Program area in on-chip memory, 1-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Vector fetch Stack save Internal Instruction fetch operation ø Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 Interrupt exception handling NOP NOP NOP execution execution execution Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Breakpoint NOP instruction is executed at breakpoint address H'0312 and next address, H'0314; fetch from address H'0316 starts after end of exception handling. • Program area in on-chip memory, 2-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal fetch operation fetch fetch fetch fetch Vector fetch Stack save Internal Instruction operation fetch ø Address bus H'0310 H'0312 H'0314 NOP execution H'0316 H'0318 SP-2 SP-4 H'0036 Interrupt exception handling MOV.W execution Break request signal H'0310 H'0312 H'0316 H'0318 NOP MOV.W #xx:16,Rd NOP NOP Breakpoint MOV instruction is executed at breakpoint address H'0312, NOP instruction at next address, H'0316, is not executed; fetch from address H'0316 starts after end of exception handling. • Program area in external memory (2-state access, 16-bit-bus access), 1-state execution instruction at specified break address Instruction fetch Instruction fetch Instruction fetch Internal operation Stack save Vector fetch Internal operation ø Address bus H'0310 H'0312 H'0314 SP-2 SP-4 H'0036 Interrupt exception handling NOP execution Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Breakpoint NOP instruction at breakpoint address H'0312 is not executed; fetch from address H'0312 starts after end of exception handling. Figure 5.6 Examples of Address Break Timing 118 5.5 Interrupt Operation 5.5.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2169 or H8S/2149 differ depending on the interrupt control mode. NMI and address break interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR, and the masking state indicated by the I and UI bits in the CPU’s CCR. Table 5.5 Interrupt Control Modes SYSCR Interrupt Priority Setting Control Mode INTM1 INTM0 Register Interrupt Mask Bits Description 0 I 0 0 ICR Interrupt mask control is performed by the I bit Priority can be set with ICR 1 1 ICR I, UI 3-level interrupt mask control is performed by the I and UI bits Priority can be set with ICR 119 Figure 5.7 shows a block diagram of the priority decision circuit. I UI ICR Interrupt acceptance control and 3-level mask control Interrupt source Default priority determination Vector number Interrupt control modes 0 and 1 Figure 5.7 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR, and ICR (control level). Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode Interrupt Mask Bits Interrupt Control Mode I UI Selected Interrupts 0 0 * All interrupts (control level 1 has priority) 1 * NMI and address break interrupt 0 * All interrupts (control level 1 has priority) 1 0 NMI, address break and control level 1 interrupts 1 NMI and address break interrupt 1 Legend: *: Don’t care 120 Default Priority Determination: The priority is determined for the selected interrupt, and a vector number is generated. If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.7 shows operations and control signal functions in each interrupt control mode. Table 5.7 Operations and Control Signal Functions in Each Interrupt Control Mode Control Mode INTM1 INTM0 0 0 0 1 1 Interrupt Acceptance Control 3-Level Control Setting Interrupt Default Priority I UI ICR Determination T (Trace) O IM — PR O — O IM IM PR O — Legend: O: Interrupt operation control performed IM: Used as interrupt mask bit PR: Sets priority —: Not used 121 5.5.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR, and ICR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Control level 1 interrupt sources have higher priority. Figure 5.8 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending. If a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. 3. The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI and address break interrupt is accepted, and other interrupt requests are held pending. 4. When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This disables all interrupts except NMI and address break interrupt. 7. A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 122 Program execution state No Interrupt generated? Yes Yes NMI? No No Control level 1 interrupt? Hold pending Yes No No IRQ0? Yes IRQ0? No Yes IRQ1? Yes No IRQ1? Yes IBFI3? IBFI3? Yes Yes I = 0? No Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.8 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 123 5.5.3 Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU’s CCR, and ICR. • Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when set to 1. • Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and disabled when both the I bit and the UI bit are set to 1. For example, if the interrupt enable bit for an interrupt request is set to 1, and H'20, H'00, and H'00 are set in ICRA, ICRB, and ICRC, respectively, (i.e. IRQ2 and IRQ3 interrupts are set to control level 1 and other interrupts to control level 0), the situation is as follows: • When I = 0, all interrupts are enabled (Priority order: NMI > IRQ2 > IRQ3 > address break > IRQ0 > IRQ1 ...) • When I = 1 and UI = 0, only NMI, IRQ2, IRQ3 and address break interrupts are enabled • When I = 1 and UI = 1, only NMI and address break interrupts are enabled Figure 5.9 shows the state transitions in these cases. I←0 All interrupts enabled Only NMI, address break, IRQ2, and IRQ3 interrupts enabled I←1, UI←0 I←0 UI←0 Exception handling execution or I←1, UI←1 Exception handling execution or UI←1 Only NMI and address break interrupts enabled Figure 5.9 Example of State Transitions in Interrupt Control Mode 1 124 Figure 5.10 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending. If a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. 3. The I bit is then referenced. If the I bit is cleared to 0, the UI bit has no effect. An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If the I bit is set to 1, only an NMI and address break interrupt are accepted, and other interrupt requests are held pending. An interrupt request set to interrupt control level 1 has priority over an interrupt request set to interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bit is set to 1 and the UI bit is cleared to 0. When both the I bit and the UI bit are set to 1, only an NMI and address break interrupt are accepted, and other interrupt requests are held pending. 4. When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I and UI bits in CCR are set to 1. This disables all interrupts except NMI and address break. 7. A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 125 Program execution state No Interrupt generated? Yes Yes NMI? No No Control level 1 interrupt? Hold pending Yes IRQ0? Yes No No IRQ0? No Yes IRQ1? No IRQ1? Yes Yes IBFI3? IBFI3? Yes Yes No I = 0? Yes UI = 0? I=0 No No Yes Yes Save PC and CCR I ← 1, UI ← 1 Read vector address Branch to interrupt handling routine Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 126 5.5.4 Interrupt Exception Handling Sequence Figure 5.11 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. 127 Figure 5.11 Interrupt Exception Handling 128 (1) (2) (4) (3) Instruction prefetch Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (1) Internal data bus Internal write signal Internal read signal Internal address bus Interrupt request signal ø Interrupt level determination Wait for end of instruction Interrupt acceptance (5) (7) (8) (9) (10) Vector fetch (12) (11) (14) (13) Interrupt handling routine instruction prefetch (6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine (6) Stack Internal operation 5.5.5 Interrupt Response Times The H8S/2149 is capable of fast word access to on-chip memory, and high-speed processing can be achieved by providing the program area in on-chip ROM and the stack area in on-chip RAM. Table 5.8 shows interrupt response times—the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols used in table 5.8 are explained in table 5.9. Table 5.8 Interrupt Response Times Number of States No. Item 1 Normal Mode Advanced Mode 3 3 1 Interrupt priority determination* 2 Number of wait states until executing instruction ends* 2 1 to (19+2·SI) 1 to (19+2·SI) 3 PC, CCR stack save 2·S K 2·S K 4 Vector fetch SI 2·S I 2·S I 2·S I 2 2 11 to 31 12 to 32 5 6 Instruction fetch* 3 Internal processing* 4 Total (using on-chip memory) Notes: 1. 2. 3. 4. Table 5.9 Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Number of States in Interrupt Handling Routine Execution Object of Access External Device 8-Bit Bus 16-Bit Bus Symbol Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access Instruction fetch SI 1 4 6+2m 2 3+m Branch address read SJ Stack manipulation SK Legend: m: Number of wait states in an external device access 129 5.6 Usage Notes 5.6.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.12 shows an example in which the CMIEA bit in 8-bit timer register TCR is cleared to 0. TCR write cycle by CPU CMIA exception handling ø Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.12 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 130 5.6.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts except NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.6.3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W R4,R4 BNE L1 131 5.7 DTC Activation by Interrupt 5.7.1 Overview The DTC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Both of the above For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller. 5.7.2 Block Diagram Figure 5.13 shows a block diagram of the DTC and interrupt controller. Interrupt request IRQ interrupt On-chip supporting module Interrupt source clear signal DTC activation request vector number Selection circuit Select signal Clear signal DTCER Control logic DTC Clear signal DTVECR SWDTE clear signal Interrupt controller Determination of priority Figure 5.13 Interrupt Control for DTC 132 CPU interrupt request vector number CPU I, UI 5.7.3 Operation The interrupt controller has three main functions in DTC control. Selection of Interrupt Source: It is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERE in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC performs the specified number of data transfers and the transfer counter reaches 0, following the DTC data transfer the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU. Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table, for the respective priorities. Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.10 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB in the DTC. Table 5.10 Interrupt Source Selection and Clearing Control Settings DTC Interrupt Source Selection/Clearing Control DTCE DISEL DTC CPU 0 * × ∆ 1 0 ∆ × 1 ∆ Legend ∆: The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. ×: The relevant bit cannot be used. *: Don’t care Usage Note: SCI, IIC, and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register, and are not dependent upon the DISEL bit. 133 134 Section 6 Bus Controller 6.1 Overview The H8S/2169 or H8S/2149 has a built-in bus controller (BSC) that allows external address space bus specifications, such as bus width and number of access states, to be set. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC). 6.1.1 Features The features of the bus controller are listed below. • Basic bus interface 2-state access or 3-state access can be selected Program wait states can be inserted • Burst ROM interface External space can be designated as ROM interface space 1-state or 2-state burst access can be selected • Idle cycle insertion An idle cycle can be inserted when an external write cycle immediately follows an external read cycle • Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC 135 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. External bus control signals Internal control signals Bus controller Bus mode signal WSCR BCR WAIT Internal data bus Wait controller CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal Figure 6.1 Block Diagram of Bus Controller 136 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that address output on address bus is enabled (when IOSE bit is 0) I/O select IOS Output I/O select signal (when IOSE bit is 1) Read RD Output Strobe signal indicating that external space is being read High write HWR Output Strobe signal indicating that external space is being written to, and that the upper data bus (D15 to D8) is enabled Low write LWR Output Strobe signal indicating that external space is being written to, and that the lower data bus (D7 to D0) is enabled Wait WAIT Input Wait request signal when external 3-state access space is accessed 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Name Abbreviation R/W Initial Value Address* Bus control register BCR R/W H'D7 H'FFC6 Wait state control register WSCR R/W H'33 H'FFC7 Note: * Lower 16 bits of the address. 137 6.2 Register Descriptions 6.2.1 Bus Control Register (BCR) 7 6 ICIS1 ICIS0 Initial value 1 1 0 1 0 Read/Write R/W R/W R/W R/W R/W Bit 5 4 3 BRSTRM BRSTS1 BRSTS0 2 1 0 — IOS1 IOS0 1 1 1 R/W R/W R/W BCR is an 8-bit readable/writable register that specifies the external memory space access mode, and the extent of the I/O area when the I/O strobe function has been selected for the AS pin. BCR is initialized to H'D7 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Idle Cycle Insert 1 (ICIS1): Reserved. Do not write 0 to this bit. Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not a one-state idle cycle is to be inserted between bus cycles when successive external read and external write cycles are performed. Bit 6 ICIS0 Description 0 Idle cycle not inserted in case of successive external read and external write cycles 1 Idle cycle inserted in case of successive external read and external write cycles (Initial value) Bit 5—Burst ROM Enable (BRSTRM): Selects whether external space is designated as a burst ROM interface space. The selection applies to the entire external space . Bit 5 BRSTRM Description 0 Basic bus interface 1 Burst ROM interface (Initial value) Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. 138 Bit 4 BRSTS1 Description 0 Burst cycle comprises 1 state 1 Burst cycle comprises 2 states (Initial value) Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max. 8 words in burst access (Initial value) Bit 2—Reserved: Do not write 0 to this bit. Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): See table 6.4. 6.2.2 Wait State Control Register (WSCR) 7 6 5 4 3 2 1 0 RAMS RAM0 ABW AST WMS1 WMS0 WC1 WC0 Initial value 0 0 1 1 0 0 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit WSCR is an 8-bit readable/writable register that specifies the data bus width, number of access states, wait mode, and number of wait states for external memory space. The on-chip memory and internal I/O register bus width and number of access states are fixed, irrespective of the WSCR settings. WSCR is initialized to H'33 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—RAM Select (RAMS)/Bit 6—RAM Area Setting (RAM0): Reserved bits. Do not write 1 to these bits. Bit 5—Bus Width Control (ABW): Specifies whether the external memory space is 8-bit access space or 16-bit access space. 139 Bit 5 ABW Description 0 External memory space is designated as 16-bit access space 1 External memory space is designated as 8-bit access space (Initial value) Bit 4—Access State Control (AST): Specifies whether the external memory space is 2-state access space or 3-state access space, and simultaneously enables or disables wait state insertion. Bit 4 AST Description 0 External memory space is designated as 2-state access space Wait state insertion in external memory space accesses is disabled 1 External memory space is designated as 3-state access space Wait state insertion in external memory space accesses is enabled (Initial value) Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1, WMS0): These bits select the wait mode when external memory space is accessed while the AST bit is set to 1. Bit 3 Bit 2 WMS1 WMS0 Description 0 0 Program wait mode 1 Wait-disabled mode 0 Pin wait mode 1 Pin auto-wait mode 1 (Initial value) Bits 1 and 0—Wait Count 1 and 0 (WC1, WC0): These bits select the number of program wait states when external memory space is accessed while the AST bit is set to 1. Bit 1 Bit 0 WC1 WC0 Description 0 0 No program wait states are inserted 1 1 program wait state is inserted in external memory space accesses 0 2 program wait states are inserted in external memory space accesses 1 3 program wait states are inserted in external memory space accesses (Initial value) 1 140 6.3 Overview of Bus Control 6.3.1 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and wait mode and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with the ABW bit. Number of Access States: Two or three access states can be selected with the AST bit. When 2-state access space is designated, wait insertion is disabled. The number of access states on the burst ROM interface is determined without regard to the AST bit setting. Wait Mode and Number of Program Wait States: When 3-state access space is designated by the AST bit, the wait mode and the number of program wait states to be inserted automatically is selected with WMS1, WMS0, WC1, and WC0. From 0 to 3 program wait states can be selected. Table 6.3 shows the bus specifications for each basic bus interface area. Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) Bus Specifications (Basic Bus Interface) ABW AST WMS1 WMS0 WC1 WC0 Bus Width Access States Program Wait States 0 0 — — — — 16 2 0 1 0 1 — — 16 3 0 —* —* 0 0 3 0 1 1 1 1 0 2 1 3 0 — — — — 8 2 0 1 0 1 — — 8 3 0 —* —* 0 0 3 0 1 1 1 0 2 1 3 Note: * Except when WMS1 = 0 and WMS0 = 1 141 6.3.2 Advanced Mode The initial state of the external space is basic bus interface, three-state access space. In ROMenabled expanded mode, the space excluding the on-chip ROM, on-chip RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. 6.3.3 Normal Mode The initial state of the external memory space is basic bus interface, three-state access space. In ROM-disabled expanded mode, the space excluding the on-chip RAM and internal I/O registers is external space. In ROM-enabled expanded mode, the space excluding the on-chip ROM, on-chip RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the onchip RAM is disabled and the corresponding space becomes external space. 6.3.4 I/O Select Signal In the H8S/2169 or H8S/2149, an I/O select signal (IOS) can be output, with the signal output going low when the designated external space is accessed. Figure 6.2 shows an example of IOS signal output timing. Bus cycle T1 T2 ø Address bus External address in IOS set range IOS Figure 6.2 IOS Signal Output Timing 142 T3 Enabling or disabling of IOS signal output is controlled by the setting of the IOSE bit in SYSCR. In expanded mode, this pin operates as the AS output pin after a reset, and therefore the IOSE bit in SYSCR must be set to 1 in order to use this pin as the IOS signal output. See section 8, I/O Ports, for details. The range of addresses for which the IOS signal is output can be set with bits IOS1 and IOS0 in BCR. The IOS signal address ranges are shown in table 6.4. Table 6.4 IOS Signal Output Range Settings IOS1 IOS0 IOS Signal Output Range 0 0 H'(FF)F000 to H'(FF)F03F 1 H'(FF)F000 to H'(FF)F0FF 0 H'(FF)F000 to H'(FF)F3FF 1 H'(FF)F000 to H'(FF)F7FF 1 6.4 Basic Bus Interface 6.4.1 Overview (Initial value) The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with the ABW bit, the AST bit, and the WMS1, WMS0, WC1, and WC0 bits (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. 143 Upper data bus Lower data bus D15 D8 D7 D0 Byte size Word size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space: Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Lower data bus Upper data bus D15 D8 D7 D0 Byte size • Even address Byte size • Odd address Word size Longword size 1st bus cycle 2nd bus cycle Figure 6.4 Access Sizes and Data Alignment Control (16-Bit Access Space) 144 6.4.3 Valid Strobes Table 6.5 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.5 Area 8-bit access space Data Buses Used and Valid Strobes Access Read/ Size Write Byte 16-bit access Byte space Address Valid Strobe Upper Data Bus (D15 to D8) Lower Data Bus (D7 to D0) Read — RD Valid Port, etc. Write — HWR Even RD Read Odd Valid Invalid Invalid Valid Even HWR Valid Undefined Odd LWR Undefined Valid Read — RD Valid Valid Write — HWR, LWR Valid Valid Write Word Port, etc. Notes: Undefined: Undefined data is output. Invalid: Input state; input value is ignored. Port, etc.: Pins are used as port or on-chip supporting module input/output pins, and not as data bus pins. 145 6.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted. Bus cycle T2 T1 ø Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.5 Bus Timing for 8-Bit 2-State Access Space 146 8-Bit 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. Bus cycle T1 T2 T3 ø Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.6 Bus Timing for 8-Bit 3-State Access Space 147 16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show the bus timing for 16-bit, 2-state access space. When 16-bit access space is accessed, the upper data bus (D15 to D8) is used for even addresses and the lower data bus (D7 to D0) for odd addresses. Wait states cannot be inserted. Bus cycle T2 T1 ø Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid Undefined Figure 6.7 16-Bit, 2-State Access Space Bus Timing (1) (Even Address Byte Access) 148 Bus cycle T2 T1 ø Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Invalid D7 to D0 Valid HWR HIgh LWR Write D15 to D8 D7 to D0 Undefined Valid Figure 6.8 16-Bit, 2-State Access Space Bus Timing (2) (Odd Address Byte Access) 149 Bus cycle T1 T2 ø Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 6.9 16-Bit, 2-State Access Space Bus Timing (3) (Word Access) 150 16-Bit, 3-State Access Space: Figures 6.10 to 6.12 show the bus timing for 16-bit, 3-state access space. When 16-bit access space is accessed, the upper data bus (D15 to D8) is used for even addresses and the lower data bus (D7 to D0) for odd addresses. Wait states can be inserted. Bus cycle T1 T2 T3 ø Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 Valid D7 to D0 Undefined Figure 6.10 16-Bit, 3-State Access Space Bus Timing (1) (Even Address Byte Access) 151 Bus cycle T1 T2 T3 ø Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 Undefined D7 to D0 Valid Figure 6.11 16-Bit, 3-State Access Space Bus Timing (2) (Odd Address Byte Access) 152 Bus cycle T1 T2 T3 ø Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 6.12 16-Bit, 3-State Access Space Bus Timing (3) (Word Access) 153 6.4.5 Wait Control When accessing external space, the MCU can extend the bus cycle by inserting one or more wait states (TW). There are three ways of inserting wait states: program wait insertion, pin wait insertion using the WAIT pin, and a combination of the two. Program Wait Mode In program wait mode, the number of TW states specified by bits WC1 and WC0 are always inserted between the T2 and T 3 states when external space is accessed. Pin Wait Mode In pin wait mode, the number of TW states specified by bits WC1 and WC0 are always inserted between the T 2 and T 3 states when external space is accessed. If the WAIT pin is low at the fall of ø in the last T2 or TW state, another TW state is inserted. If the WAIT pin is held low, TW states are inserted until it goes high. Pin wait mode is useful for inserting four or more wait states, or for changing the number of TW states for different external devices. Pin Auto-Wait Mode In pin auto-wait mode, if the WAIT pin is low at the fall of ø in the T2 state, the number of T W states specified by bits WC1 and WC0 are inserted when external space is accessed. No additional TW states are inserted even if the WAIT pin remains low. Pin auto-wait mode can be used for an easy interface to low-speed memory, simply by routing the chip select signal to the WAIT pin. Figure 6.13 shows an example of wait state insertion timing. 154 By program wait T1 T2 Tw By WAIT pin Tw Tw T3 ø WAIT Address bus AS (IOSE = 0) RD Read Data bus Read data HWR, LWR Write Data bus Note: Write data indicates the timing of WAIT pin sampling using the ø clock. Figure 6.13 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, insertion of 3 program wait states, and WAIT input disabled. 155 6.5 Burst ROM Interface 6.5.1 Overview With the H8S/2169 or H8S/2149, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. External space can be designated as burst ROM space by means of the BRSTRM bit in BCR. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 6.5.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST bit. Also, when the AST bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCR. Wait states cannot be inserted. When the BRSTS0 bit in BCR is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figure 6.14 (a) and (b). The timing shown in figure 6.14 (a) is for the case where the AST and BRSTS1 bits are both set to 1, and that in figure 6.14 (b) is for the case where both these bits are cleared to 0. Full access T1 T2 Burst access T3 T1 T2 T1 T2 ø Only lower address changed Address bus AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.14 (a) Example of Burst ROM Access Timing (When AST = BRSTS1 = 1) 156 Full access T1 T2 Burst access T1 T1 ø Only lower address changed Address bus AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.14 (b) Example of Burst ROM Access Timing (When AST = BRSTS1 = 0) 6.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. 157 6.6 Idle Cycle 6.6.1 Operation When the H8S/2169 or H8S/2149 chip accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. If an external write occurs after an external read while the ICIS0 bit in BCR is set to 1, an idle cycle is inserted at the start of the write cycle. This is enabled in advanced mode and normal mode. Figure 6.15 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 T2 Bus cycle B T3 T1 Bus cycle A T2 T1 RD HWR, LWR Data bus ,, Long output floating time (a) Idle cycle not inserted TI T1 Address bus RD HWR, LWR Data bus Data collision (b) Idle cycle inserted Figure 6.15 Example of Idle Cycle Operation 158 T3 ø ø Address bus T2 Bus cycle B T2 6.6.2 Pin States in Idle Cycle Table 6.5 shows pin states in an idle cycle. Table 6.5 Pin States in Idle Cycle Pins Pin State A23 to A0, IOS Contents of next bus cycle D15 to D0 High impedance AS High RD High HWR, LWR High 6.7 Bus Arbitration 6.7.1 Overview The H8S/2169 or H8S/2149 has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and the DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 6.7.2 Operation The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from both bus masters, the bus request acknowledge signal is sent to the one with the higher priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DTC > CPU (Low) 159 6.7.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the DTC. The timing for transfer of the bus is as follows: • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not transferred. • If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC does not release the bus until it has completed a series of processing operations. 160 Section 7 Data Transfer Controller 7.1 Overview The H8S/2169 or H8S/2149 includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 7.1.1 Features • Transfer possible over any number of channels Transfer information is stored in memory One activation source can trigger a number of data transfers (chain transfer) • Wide range of transfer modes Normal, repeat, and block transfer modes available Incrementing, decrementing, and fixing of transfer source and destination addresses can be selected • Direct specification of 16-Mbyte address space possible 24-bit transfer source and destination addresses can be specified • Transfer can be set in byte or word units • A CPU interrupt can be requested for the interrupt that activated the DTC An interrupt request can be issued to the CPU after one data transfer ends An interrupt request can be issued to the CPU after all specified data transfers have ended • Activation by software is possible • Module stop mode can be set The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode 161 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Internal address bus On-chip RAM CPU interrupt request Internal data bus Legend: MRA, MRB: DTC mode registers A and B CRA, CRB: DTC transfer count registers A and B SAR: DTC source address register DAR: DTC destination address register DTCERA to DTCERE: DTC enable registers A to E DTVECR: DTC vector register Figure 7.1 Block Diagram of DTC 162 Register information MRA MRB CRA CRB DAR SAR DTC Control logic DTC activation request DTVECR Interrupt request DTCERA to DTCERE Interrupt controller 7.1.3 Register Configuration Table 7.1 summarizes the DTC registers. Table 7.1 DTC Registers Name Abbreviation R/W Initial Value Address* 1 DTC mode register A MRA —* 2 Undefined —* 3 DTC mode register B MRB —* 2 Undefined —* 3 DTC source address register SAR —* 2 Undefined —* 3 DTC destination address register DAR —* 2 Undefined —* 3 DTC transfer count register A CRA —* 2 Undefined —* 3 DTC transfer count register B CRB —* 2 Undefined —* 3 DTC enable registers DTCER R/W H'00 H'FEEE to H'FEF2 DTC vector register DTVECR R/W H'00 H'FEF3 Module stop control register MSTPCRH R/W H'3F H'FF86 MSTPCRL R/W H'FF H'FF87 Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Allocated to on-chip RAM addresses H'EC00 to H'EFFF as register information. They cannot be located in external memory space. When the DTC is used, do not clear the RAME bit in SYSCR to 0. 163 7.2 Register Descriptions 7.2.1 DTC Mode Register A (MRA) 7 Bit Initial value Read/Write 6 5 4 3 2 1 0 SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 Bit 6 SM1 SM0 Description 0 — SAR is fixed 1 0 SAR is incremented after a transfer (by 1 when Sz = 0; by 2 when Sz = 1) 1 SAR is decremented after a transfer (by 1 when Sz = 0; by 2 when Sz = 1) Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 Bit 4 DM1 DM0 Description 0 — DAR is fixed 1 0 DAR is incremented after a transfer (by 1 when Sz = 0; by 2 when Sz = 1) 1 DAR is decremented after a transfer (by 1 when Sz = 0; by 2 when Sz = 1) 164 Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 Bit 2 MD1 MD0 Description 0 0 Normal mode 1 Repeat mode 0 Block transfer mode 1 — 1 Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS Description 0 Destination side is repeat area or block area 1 Source side is repeat area or block area Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz Description 0 Byte-size transfer 1 Word-size transfer 165 7.2.2 DTC Mode Register B (MRB) Bit Initial value Read/Write 7 6 5 4 3 2 1 0 CHNE DISEL — — — — — — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — MRB is an 8-bit register that controls the DTC operating mode. Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. In chain transfer, multiple data transfers can be performed consecutively in response to a single transfer request. With data transfer for which CHNE is set to 1, there is no determination of the end of the specified number of transfers, clearing of the interrupt source flag, or clearing of DTCER. Bit 7 CHNE Description 0 End of DTC data transfer (activation waiting state is entered) 1 DTC chain transfer (new register information is read, then data is transferred) Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL Description 0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) 1 After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0—Reserved: In the chip these bits have no effect on DTC operation, and should always be written with 0. 166 7.2.3 DTC Source Address Register (SAR) 23 Bit Initial value Read/write 22 21 20 19 4 Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — 3 2 1 0 Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.4 DTC Destination Address Register (DAR) 23 Bit Initial value Read/write 22 21 20 19 4 Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — 3 2 1 0 Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 7.2.5 DTC Transfer Count Register A (CRA) Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — CRAH CRAL CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA register functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are transferred when the count reaches H'00. This operation is repeated. 167 7.2.6 DTC Transfer Count Register B (CRB) 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — Initial value Read/Write CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 7.2.7 DTC Enable Registers (DTCER) 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit The DTC enable registers comprise five 8-bit readable/writable registers, DTCERA to DTCERE, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn 0 Description DTC activation by interrupt is disabled (Initial value) [Clearing conditions] 1 • When data transfer ends with the DISEL bit set to 1 • When the specified number of transfers end DTC activation by interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number generated by the interrupt controller in each case. 168 For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register. 7.2.8 DTC Vector Register (DTVECR) 7 Bit 6 5 4 3 2 0 1 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W 0 R/W 0 0 R/W R/W Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—DTC Software Activation Enable (SWDTE): Specifies enabling or disabling of DTC software activation. To clear the SWDTE bit by software, read SWDTE when set to 1, then write 0 in the bit. Bit 7 SWDTE Description 0 DTC software activation is disabled (Initial value) [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 DTC software activation is enabled [Holding conditions] • When data transfer ends with the DISEL bit set to 1 • When the specified number of transfers end • During software-activated data transfer Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is H'0400 + (vector number) << 1 (where << 1 indicates a 1-bit left shift). For example, if DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. 169 7.2.9 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 Initial value Read/Write 0 0 1 1 1 1 1 1 7 6 5 4 3 2 1 0 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP14 bit in MSTPCR is set to 1, the DTC operation stops at the end of the bus cycle and a transition is made to module stop mode. Note that 1 cannot be written to the MSTP14 bit when the DTC is being activated. For details, see section 24.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 6—Module Stop (MSTP14): Specifies the DTC module stop mode. MSTPCRH Bit 6 MSTP14 Description 0 DTC module stop mode is cleared 1 DTC module stop mode is set 170 (Initial value) 7.3 Operation 7.3.1 Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation. Figure 7.2 shows a flowchart of DTC operation. Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? Yes No Transfer counter = 0 or DISEL = 1? Yes No Clear activation flag Clear DTCER End Interrupt exception handling Figure 7.2 Flowchart of DTC Operation 171 The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Table 7.2 outlines the functions of the DTC. Table 7.2 DTC Functions Address Registers Transfer Mode • Normal mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 Up to 65,536 transfers possible • Repeat mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers (1 to 256), the initial state resumes and operation continues • Block transfer mode One transfer request transfers a block of the specified size Block size is from 1 to 256 bytes or words Up to 65,536 transfers possible A block area can be designated at either the source or destination 172 Activation Source • IRQ • FRT ICI, OCI • 8-bit timer CMI • Host interface IBF • SCI TXI or RXI • A/D converter ADI • IIC IICI • Software Transfer Source Transfer Destination 24 bits 24 bits 7.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software (software activation). An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. The interrupt request is directed to the DTC when the corresponding bit is set to 1, and to the CPU when the bit is cleared to 0. At the end of one data transfer (or the last of the consecutive transfers in the case of chain transfer) the interrupt source or the corresponding DTCER bit is cleared. Table 7.3 shows activation sources and DTCER clearing. The interrupt source flag for RXI0, for example, is the RDRF flag in SCI0. Table 7.3 Activation Sources and DTCER Clearing When DISEL Bit Is 0 and Specified Number of Transfers Have Not Ended When DISEL Bit Is 1 or Specified Number of Transfers Have Ended Software activation SWDTE bit cleared to 0 • SWDTE bit held at 1 • Interrupt request sent to CPU Interrupt activation • Corresponding DTCER bit held at 1 • Corresponding DTCER bit cleared to 0 • Activation source flag cleared to 0 • Activation source flag held at 1 • Activation source interrupt request sent to CPU Activation Source Figure 7.3 shows a block diagram of activation source control. For details see section 5, Interrupt Controller. 173 Source flag cleared Clear control Clear DTCER Clear request On-chip supporting module IRQ interrupt Interrupt request DTVECR Selection circuit Select DTC Interrupt controller CPU Interrupt mask Figure 7.3 Block Diagram of DTC Activation Source Control When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC is activated in accordance with the default priorities. 7.3.3 DTC Vector Table Figure 7.4 shows the correspondence between DTC vector addresses and register information. Table 7.4 shows the correspondence between activation sources, vector addresses, and DTCER bits. When the DTC is activated by software, the vector address is obtained from: H'0400 + DTVECR[6:0] << 1 (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. The register information can be placed at predetermined addresses in the on-chip RAM. The start address of the register information should be an integral multiple of four. The configuration of the vector address is the same in both normal and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM. 174 DTC vector address Register information start address Register information Chain transfer Figure 7.4 Correspondence between DTC Vector Address and Register Information Table 7.4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Interrupt Source Origin of Vector Interrupt Source Number Write to DTVECR Software IRQ0 External pin Vector Address DTCE* Priority DTVECR H'0400 + (decimal DTVECR indication) [6:0] << 1 — High 16 H'0420 DTCEA7 IRQ1 17 H'0422 DTCEA6 IRQ2 18 H'0424 DTCEA5 IRQ3 19 H'0426 DTCEA4 28 H'0438 DTCEA3 ADI (A/D conversion end) A/D ICIA (FRT input capture A) FRT 48 H'0460 DTCEA2 ICIB (FRT input capture B) 49 H'0462 DTCEA1 OCIA (FRT output compare A) 52 H'0468 DTCEA0 OCIB (FRT output compare B) 54 H'046A DTCEB7 CMIA0 (TMR0 compare-match A) TMR0 64 H'0480 DTCEB2 CMIB0 (TMR0 compare-match B) 65 H'0482 DTCEB1 CMIA1 (TMR1 compare-match A) TMR1 68 H'0488 DTCEB0 CMIB1 (TMR1 compare-match B) 69 H'048A DTCEC7 CMIAY (TMRY compare-match A) TMRY 72 H'0490 DTCEC6 CMIBY (TMRY compare-match B) 73 H'0492 DTCEC5 76 H'0498 DTCEC4 77 H'049A DTCEC3 81 H'04A2 DTCEC2 82 H'04A4 DTCEC1 IBF1 (IDR1 reception completed) HIF IBF2 (IDR2 reception completed) RXI0 (reception completed 0) TXI0 (transmit data empty 0) SCI channel 0 175 Interrupt Source Origin of Vector Interrupt Source Number Vector Address DTCE* RXI1 (reception completed 1) SCI channel 1 85 H'04AA DTCEC0 86 H'04AC DTCED7 89 H'04B2 DTCED6 90 H'04B4 DTCED5 TXI1 (transmit data empty 1) RXI2 (reception completed 2) SCI channel 2 TXI2 (transmit data empty 2) IICI0 (IIC0 1-byte transmission/ reception completed) IIC0 92 H'04B8 DTCED4 IICI1 (IIC1 1-byte transmission/ reception completed) IIC1 94 H'04BC DTCED3 ERRI (transfer error etc.) LPC Priority 104 H'04D8 DTCEE3 IBFI1 (IDR1 reception completed) 105 H'04DA DTCEE2 IBFI2 (IDR2 reception completed) 106 H'04DC DTCEE1 IBFI3 (IDR3 reception completed) 107 H'04DE DTCEE0 Low Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0. 7.3.4 Location of Register Information in Address Space Figure 7.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (vector address contents). In chain transfer, locate the register information in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFEC00 to H'FFEFFF). 176 Lower address 0 Register information start address Chain transfer 1 2 3 MRA SAR MRB DAR CRA Register information CRB MRA SAR MRB DAR CRA CRB Register information for 2nd transfer in chain transfer 4 bytes Figure 7.5 Location of DTC Register Information in Address Space 7.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 7.5 lists the register information in normal mode and figure 7.6 shows memory mapping in normal mode. Table 7.5 Register Information in Normal Mode Name Abbreviation Function DTC source address register SAR Transfer source address DTC destination address register DAR Transfer destination address DTC transfer count register A CRA Transfer count DTC transfer count register B CRB Not used 177 SAR DAR Transfer Figure 7.6 Memory Mapping in Normal Mode 7.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial address register state specified by the transfer counter and repeat area resumes and transfer is repeated. In repeat mode the transfer counter does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 7.6 lists the register information in repeat mode and figure 7.7 shows memory mapping in repeat mode. Table 7.6 Register Information in Repeat Mode Name Abbreviation Function DTC source address register SAR Transfer source address DTC destination address register DAR Transfer destination address DTC transfer count register AH CRAH Holds number of transfers DTC transfer count register AL CRAL Transfer count DTC transfer count register B CRB Not used 178 SAR or DAR DAR or SAR Repeat area Transfer Figure 7.7 Memory Mapping in Repeat Mode 7.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is specified as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified in the block area is restored. The other address register is successively incremented or decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested. Table 7.7 lists the register information in block transfer mode and figure 7.8 shows memory mapping in block transfer mode. Table 7.7 Register Information in Block Transfer Mode Name Abbreviation Function DTC source address register SAR Transfer source address DTC destination address register DAR Transfer destination address DTC transfer count register AH CRAH Holds block size DTC transfer count register AL CRAL Block size count DTC transfer count register B CRB Transfer counter 179 First block SAR or DAR · · · Block area Transfer Nth block Figure 7.8 Memory Mapping in Block Transfer Mode 180 DAR or SAR 7.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.9 shows memory mapping for chain transfer. Source Destination Register information CHNE = 1 DTC vector address Register information start address Register information CHNE = 0 Source Destination Figure 7.9 Memory Mapping in Chain Transfer In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. 181 7.3.9 Operation Timing Figures 7.10 to 7.12 show examples of DTC operation timing. ø DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 7.10 DTC Operation Timing (Normal Mode or Repeat Mode) ø DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information read Transfer information write Figure 7.11 DTC Operation Timing (Block Transfer Mode, with Block Size of 2) 182 ø DTC activation request DTC request Data transfer Data transfer Read Write Read Write Vector read Address Transfer information read Transfer Transfer information information write read Transfer information write Figure 7.12 DTC Operation Timing (Chain Transfer) 7.3.10 Number of DTC Execution States Table 7.8 lists execution phases for a single DTC data transfer, and table 7.9 shows the number of states required for each execution phase. Table 7.8 DTC Execution Phases Mode Vector Read I Register Information Read/Write Data Read J K Data Write L Internal Operation M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 N: Block size (initial setting of CRAH and CRAL) 183 Table 7.9 Number of States Required for Each Execution Phase Object of Access OnOnChip Chip Internal I/O RAM ROM Registers External Devices Bus width 32 16 8 16 8 8 16 16 Access states 1 1 2 2 2 3 2 3 Execution phase Vector read SI — 1 — — 4 6+2m 2 3+m Register information read/write SJ 1 — — — — — — — Byte data read SK 1 1 2 2 2 3+m 2 3+m Word data read SK 1 1 4 2 4 6+2m 2 3+m Byte data write SL 1 1 2 2 2 3+m 2 3+m Word data write SL 1 1 4 2 4 6+2m 2 3+m Internal operation SM 1 1 1 1 1 1 1 1 The number of execution states is calculated from the formula below. Note that Σ means the sum of all transfers activated by one activation event (the number for which the CHNE bit is set to one, plus 1). Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. 184 7.3.11 Procedures for Using the DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software: The procedure for using the DTC with software activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Check that the SWDTE bit is 0. 4. Write 1 in the SWDTE bit and the vector number to DTVECR. 5. Check the vector number written to DTVECR. 6. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested. 185 7.3.12 Examples of Use of the DTC Normal Mode: An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing. 186 Software Activation: An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. 187 7.4 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software-activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 7.5 Usage Notes Module Stop: When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC enters the module stop state. However, 1 cannot be written in the MSTP14 bit while the DTC is operating. When the DTC is placed in the module stop state, the DTCER registers must all be in the cleared state when the MSTP14 bit is set to 1. On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. DTCE Bit Setting: For DTCE bit setting, read/write operations must be performed using bitmanipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register. 188 Section 8 I/O Ports 8.1 Overview The H8S/2149 has ten I/O ports (ports 1 to 6, 8, 9, A, and B), and one input-only port (port 7). For additional ports C, D, E, F, and G in H8S/2169, see section 8.13 Additional Overview for H8S/2169. Tables 8.1 is a summary of the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port) and data registers (DR, ODR) that store output data. Ports 1 to 3, 6, A, and B have a built-in MOS input pull-up function. For ports A and B, the on/off status of the MOS input pull-up is controlled by DDR and ODR. Ports 1 to 3 and 6 have a MOS input pull-up control register (PCR), in addition to DDR and DR, to control the on/off status of the MOS input pull-ups. Ports 1 to 6, 8, 9, A, and B can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a Darlington transistor when in output mode. Ports 1, 2, and 3 can drive an LED (10 mA sink current). Port A input and output use by the VCCB power supply, which is independent of the VCC power supply. When the VCCB voltage is 5V, the pins on port A will be 5-V tolerant. PA4 to PA7 of port A have bus-buffer drive capability. P52 in port 5 and P97 in port 9 are NMOS push-pull outputs. P52 and P97 are thus 5-V tolerant, with DC characteristics that are dependent on the VCC voltage. 189 Table 8.1 H8S/2169 or H8S/2149 Port Functions Expanded Modes Port Description Pins Mode 1 Mode 2, Mode 3 (EXPE = 1) Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as PWM timer output (PW7 to PW0) P17 to P10/ Port 1 • 8-bit I/O port A7 to A0/ PW7 to PW0 • Built-in MOS input pull-ups • LED drive capability Lower address output (A7 to A0) When DDR = 0 (after reset): input port Port 2 • 8-bit I/O port • Built-in MOS input pull-ups • LED drive capability Upper address output (A15 to A8) When DDR = 0 (after reset): input port or timer connection output (CBLANK) P27/A15/PW15/ CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 Port 3 • 8-bit I/O port • Built-in MOS input pull-ups • LED drive capability P37/D15/HDB7/ SERIRQ P36/D14/HDB6/ LCLK P35/D13/HDB5/ LRESET P34/D12/HDB4/ LFRAME P33 to P30/ D11 to D8/ HDB3 to HDB0/ LAD3 to LAD0 190 Single-Chip Mode When DDR = 1: lower address output (A7 to A0) or PWM timer output (PW7 to PW0) I/O port also functioning as PWM timer output (PW15 to PW8) and timer connection output (CBLANK) When DDR = 1: upper address output (A15 to A8), PWM timer output (PW15 to PW12), timer connection output (CBLANK), or output ports (P27 to P24) Data bus input/output (D15 to D8) I/O port also functioning as XBS data bus input/output (HDB7 to HDB0) and LPC input/output (SERIRQ, LCLK, LRESET, LFRAME, LAD3 to LAD0) Expanded Modes Port Description Pins Port 4 • 8-bit I/O port P47/PWX1 Mode 2, Mode 3 (EXPE = 1) I/O port also functioning as 14-bit PWM timer output P46/PWX0 (PWX1, PWX0), 8-bit timer 0 P45/TMRI1/ and 1 input/output (TMCI0, HIRQ12/CSYNCI TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection P44/TMO1/ HIRQ1/HSYNCO input/output (HSYNCO, CSYNCI, HSYNCI), SCI2 P43/TMCI1/ input/output (TxD2, RxD2, HIRQ11/HSYNCI SCK2), IrDA interface P42/TMRI0/ input/output (IrTxD, IrRxD), SCK2/SDA1 and I2C bus interface 1 input/output (SDA1) P41/TMO0/ RxD2/IrRxD P40/TMCI0/ TxD2/IrTxD Port 5 • 3-bit I/O port Mode 1 P52/SCK0/SCL0 P51/RxD0 Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as 14-bit PWM timer output (PWX1, PWX0), 8-bit timer 0 and 1 input/ output (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection input/output (HSYNCO, CSYNCI, HSYNCI), host interface (XBS) host CPU interrupt request output (HIRQ12, HIRQ1, HIRQ11), SCI2 input/ output (TxD2, RxD2, SCK2), IrDA interface input/output (IrTxD, IrRxD), and I2C bus interface 1 input/output (SDA1) I/O port also functioning as SCI0 input/output (TxD0, RxD0, SCK0) and I 2C bus interface 0 input/output (SCL0) P50/TxD0 Port 6 • 8-bit I/O port P67/IRQ7/TMOX/ I/O port also functioning as external interrupt input (IRQ7, KIN7/CIN7 IRQ6), FRT input/output (FTCI, FTOA, FTIA, FTIB, FTIC, P66/IRQ6/FTOB/ FTID, FTOB), 8-bit timer X and Y input/output (TMOX, TMIX, TMIY), timer connection input/output (CLAMPO, KIN6/CIN6 VFBACKI, VSYNCI, VSYNCO, HFBACKI), key-sense P65/FTID/KIN5/ interrupt input (KIN7 to KIN0), and expansion A/D CIN5 converter input (CIN7 to CIN0) P64/FTIC/KIN4/ CIN4/CLAMPO P63/FTIB/KIN3/ CIN3/VFBACKI P62/FTIA/TMIY/ KIN2/CIN2/ VSYNCI P61/FTOA/KIN1/ CIN1/VSYNCO P60/FTCI/TMIX/ KIN0/CIN0/ HFBACKI 191 Expanded Modes Port Description Pins Port 7 • 8-bit input port P77/AN7/DA1 P76/AN6/DA0 P75/AN5 Mode 1 Mode 2, Mode 3 (EXPE = 1) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) Input port also functioning as A/D converter analog input (AN7 to AN0) and D/A converter analog output (DA1, DA0) P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 Port 8 • 7-bit I/O port P86/IRQ5/SCK1/ I/O port also functioning as SCL1 external interrupt input (IRQ5, P85/IRQ4/RxD1 IRQ4, IRQ3), SCI1 input/ output (TxD1, RxD1, SCK1), P84/IRQ3/TxD1 and I2C bus interface 1 input/output (SCL1) P83/LPCPD P82/HIFSD/ CLKRUN P81/CS2/GA20 P80/HA0/PME Port 9 • 8-bit I/O port P97/WAIT/SDA0 I/O port also functioning as expanded data bus control input (WAIT) and I2C bus interface 0 input/output (SDA0) P96/ø/EXCL When DDR = 0: input port or EXCL input I/O port also functioning as external interrupt input (IRQ5, IRQ4, IRQ3), SCI1 input/output (TxD1, RxD1, SCK1), host interface (XBS) control input/output (CS2, GA20, HA0, HIFSD), host interface (LPC) control input/output (LPCPD, CLKRUN, GA20, PME), and I2C bus interface 1 input/output (SCL1) I/O port also functioning as I 2C bus interface 0 input/output (SDA0) When DDR = 0 (after reset): input port or EXCL input When DDR = 1: ø output When DDR = 1 (after reset): ø output P95/AS/IOS/CS1 Expanded data bus control output (AS/IOS, HWR, RD) P94/HWR/IOW P93/RD/IOR 192 I/O port also functioning as host interface (XBS) control input (CS1, IOW, IOR) Expanded Modes Port Description Pins Port 9 • 8-bit I/O port Port A • 8-bit I/O port P92/IRQ0 P91/IRQ1 Mode 1 Mode 2, Mode 3 (EXPE = 1) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as external interrupt input (IRQ0, IRQ1) P90/LWR/IRQ2/ ADTRG/ECS2 I/O port also functioning as expanded data bus control output (LWR), external interrupt input (IRQ2), and A/D converter external trigger input (ADTRG) I/O port also functioning as external interrupt input (IRQ2), A/D converter external trigger input (ADTRG), and host interface (XBS) control input (ECS2) PA7/A23/KIN15/ CIN15/PS2CD I/O port also functioning as keysense interrupt input (KIN15 to KIN8), expansion A/D converter input (CIN15 to CIN8), and keyboard buffer controller input/output (PS2CD, PS2CC, PS2BD, PS2BC, PS2AD, PS2AC) I/O port also functioning as address output (A23 to A16), key-sense interrupt input (KIN15 to KIN8), expansion A/D converter input (CIN15 to CIN8), and keyboard buffer controller input/output (PS2CD, PS2CC, PS2BD, PS2BC, PS2AD, PS2AC) I/O port also functioning as key-sense interrupt input (KIN15 to KIN8), expansion A/D converter input (CIN15 to CIN8), and keyboard buffer controller input/output (PS2CD, PS2CC, PS2BD, PS2BC, PS2AD, PS2AC) PA6/A22/KIN14/ CIN14/PS2CC PA5/A21/KIN13/ CIN13/PS2BD PA4/A20/KIN12/ CIN12/PS2BC PA3/A19/KIN11/ CIN11/PS2AD PA2/A18/KIN10/ CIN10/PS2AC PA1/A17/KIN9/ CIN9 PA0/A16/KIN8/ CIN8 193 Expanded Modes Port Description Pins Port B • 8-bit I/O port PB7/D7/WUE7 PB6/D6/WUE6 PB5/D5/WUE5 PB4/D4/WUE4 PB3/D3/WUE3/ CS4 PB2/D2/WUE2/ CS3 PB1/D1/WUE1/ HIRQ4/LSCI PB0/D0/WUE0/ HIRQ3/LSMI 194 Mode 1 Mode 2, Mode 3 (EXPE = 1) In 8-bit bus mode (ABW = 1): I/O port also functioning as wakeup event interrupt input (WUE7 to WUE0) In 16-bit bus mode (ABW = 0): data bus input/output (D7 to D0) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as host interface (XBS) control input/output (CS3, CS4, HIRQ3, HIRQ4), host interface (LPC) control input/output (LSCI, LSMI), and wakeup event interrupt input (WUE7 to WUE0) 8.2 Port 1 8.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as address bus output function, and as 8-bit PWM output pins (PW7 to PW0). Port 1 functions change according to the operating mode. Port 1 has a built-in MOS input pull-up function that can be controlled by software. Figure 8.1 shows the port 1 pin configuration. Port 1 Port 1 pins Pin functions in mode 1 P17/A7/PW7 A7 (Output) P16/A6/PW6 A6 (Output) P15/A5/PW5 A5 (Output) P14/A4/PW4 A4 (Output) P13/A3/PW3 A3 (Output) P12/A2/PW2 A2 (Output) P11/A1/PW1 A1 (Output) P10/A0/PW0 A0 (Output) Pin functions in modes 2 and 3 (EXPE = 1) A7 (Output)/P17 (Input)/PW7 (Output) A6 (Output)/P16 (Input)/PW6 (Output) A5 (Output)/P15 (Input)/PW5 (Output) A4 (Output)/P14 (Input)/PW4 (Output) A3 (Output)/P13 (Input)/PW3 (Output) A2 (Output)/P12 (Input)/PW2 (Output) A1 (Output)/P11 (Input)/PW1 (Output) A0 (Output)/P10 (Input)/PW0 (Output) Pin functions in modes 2 and 3 (EXPE = 0) P17 (I/O)/PW7 (Output) P16 (I/O)/PW6 (Output) P15 (I/O)/PW5 (Output) P14 (I/O)/PW4 (Output) P13 (I/O)/PW3 (Output) P12 (I/O)/PW2 (Output) P11 (I/O)/PW1 (Output) P10 (I/O)/PW0 (Output) Figure 8.1 Port 1 Pin Functions 195 8.2.2 Register Configuration Table 8.2 shows the port 1 register configuration. Table 8.2 Port 1 Registers Name Abbreviation R/W Initial Value Address* Port 1 data direction register P1DDR W H'00 H'FFB0 Port 1 data register P1DR R/W H'00 H'FFB2 Port 1 MOS pull-up control register P1PCR R/W H'00 H'FFAC Note: * Lower 16 bits of the address. Port 1 Data Direction Register (P1DDR) Bit 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value 0 0 0 0 0 Read/Write W W W W W 0 W 0 0 W W P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be returned. P1DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. The address output pins maintain their output state in a transition to software standby mode. • Mode 1 The corresponding port 1 pins are address outputs, regardless of the P1DDR setting. In hardware standby mode, the address outputs go to the high-impedance state. • Modes 2 and 3 (EXPE = 1) The corresponding port 1 pins are address outputs or PWM outputs when P1DDR bits are set to 1, and input ports when cleared to 0. • Modes 2 and 3 (EXPE = 0) The corresponding port 1 pins are output ports or PWM outputs when P1DDR bits are set to 1, and input ports when cleared to 0. 196 Port 1 Data Register (P1DR) Bit Initial value R/W 7 6 5 4 3 2 1 0 P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read directly, regardless of the actual pin states. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. P1DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port 1 MOS Pull-Up Control Register (P1PCR) Bit 7 6 5 4 3 2 1 0 P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Initial value R/W 0 0 0 0 0 R/W R/W R/W R/W R/W 0 R/W 0 0 R/W R/W P1PCR is an 8-bit readable/writable register that controls the port 1 built-in MOS input pull-ups on a bit-by-bit basis. In modes 2 and 3, the MOS input pull-up is turned on when a P1PCR bit is set to 1 while the corresponding P1DDR bit is cleared to 0 (input port setting). P1PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 197 8.2.3 Pin Functions in Each Mode Mode 1: In mode 1, port 1 pins automatically function as address outputs. The port 1 pin functions are shown in figure 8.2. A7 (Output) A6 (Output) A5 (Output) Port 1 A4 (Output) A3 (Output) A2 (Output) A1 (Output) A0 (Output) Figure 8.2 Port 1 Pin Functions (Mode 1) Modes 2 and 3 (EXPE = 1): In modes 2 and 3 (when EXPE = 1), port 1 pins function as address outputs, PWM outputs, or input ports, and input or output can be specified on a bit-by-bit basis. When a bit in P1DDR is set to 1, the corresponding pin functions as an address output or PWM output, and when cleared to 0, as an input port. The port 1 pin functions are shown in figure 8.3. Port 1 When P1DDR = 1 and PWOERA = 0 When P1DDR = 0 When P1DDR = 1 and PWOERA = 1 A7 (Output) P17 (Input) PW7 (Output) A6 (Output) P16 (Input) PW6 (Output) A5 (Output) P15 (Input) PW5 (Output) A4 (Output) P14 (Input) PW4 (Output) A3 (Output) P13 (Input) PW3 (Output) A2 (Output) P12 (Input) PW2 (Output) A1 (Output) P11 (Input) PW1 (Output) A0 (Output) P10 (Input) PW0 (Output) Figure 8.3 Port 1 Pin Functions (Modes 2 and 3 (EXPE = 1)) 198 Modes 2 and 3 (EXPE = 0): In modes 2 and 3 (when EXPE = 0), port 1 pins function as PWM outputs or I/O ports, and input or output can be specified on a bit-by-bit basis. When a bit in P1DDR is set to 1, the corresponding pin functions as a PWM output or output port, and when cleared to 0, as an input port. The port 1 pin functions are shown in figure 8.4. Port 1 P1n: Input pin when P1DDR = 0, output pin when P1DDR = 1 and PWOERA = 0 When P1DDR = 1 and PWOERA = 1 P17 (I/O) PW7 (Output) P16 (I/O) PW6 (Output) P15 (I/O) PW5 (Output) P14 (I/O) PW4 (Output) P13 (I/O) PW3 (Output) P12 (I/O) PW2 (Output) P11 (I/O) PW1 (Output) P10 (I/O) PW0 (Output) Figure 8.4 Port 1 Pin Functions (Modes 2 and 3 (EXPE = 0)) 8.2.4 MOS Input Pull-Up Function Port 1 has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bit-bybit basis. When a P1DDR bit is cleared to 0 in mode 2 or 3, setting the corresponding P1PCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.4 summarizes the MOS input pull-up states. 199 Table 8.3 MOS Input Pull-Up States (Port 1) Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1 Off Off Off Off 2, 3 Off Off On/Off On/Off Legend: Off: MOS input pull-up is always off. On/Off: On when P1DDR = 0 and P1PCR = 1; otherwise off. 8.3 Port 2 8.3.1 Overview Port 2 is an 8-bit I/O port. Port 2 pins also function as address bus output function, 8-bit PWM output pins (PW15 to PW8), and the timer connection output pin (CBLANK). Port 2 functions change according to the operating mode. Port 2 has a built-in MOS input pull-up function that can be controlled by software. Figure 8.5 shows the port 2 pin configuration. 200 Port 2 Port 2 pins Pin functions in mode 1 P27/A15/PW15/CBLANK A15 (Output) P26/A14/PW14 A14 (Output) P25/A13/PW13 A13 (Output) P24/A12/PW12 A12 (Output) P23/A11/PW11 A11 (Output) P22/A10/PW10 A10 (Output) P21/A9/PW9 A9 (Output) P20/A8/PW8 A8 (Output) Pin functions in modes 2 and 3 (EXPE = 1) A15 (Output)/P27 (I/O)/PW15 (Output)/CBLANK (Output) A14 (Output)/P26 (I/O)/PW14 (Output) A13 (Output)/P25 (I/O)/PW13 (Output) A12 (Output)/P24 (I/O)/PW12 (Output) A11 (Output)/P23 (Input)/PW11 (Output) A10 (Output)/P22 (Input)/PW10 (Output) A9 (Output)/P21 (Input)/PW9 (Output) A8 (Output)/P20 (Input)/PW8 (Output) Pin functions in modes 2 and 3 (EXPE = 0) P27 (I/O)/PW15 (Output)/CBLANK (Output) P26 (I/O)/PW14 (Output) P25 (I/O)/PW13 (Output) P24 (I/O)/PW12 (Output) P23 (I/O)/PW11 (Output) P22 (I/O)/PW10 (Output) P21 (I/O)/PW9 (Output) P20 (I/O)/PW8 (Output) Figure 8.5 Port 2 Pin Functions 201 8.3.2 Register Configuration Table 8.4 shows the port 2 register configuration. Table 8.4 Port 2 Registers Name Abbreviation R/W Initial Value Address* Port 2 data direction register P2DDR W H'00 H'FFB1 Port 2 data register P2DR R/W H'00 H'FFB3 Port 2 MOS pull-up control register P2PCR R/W H'00 H'FFAD Note: * Lower 16 bits of the address. Port 2 Data Direction Register (P2DDR) Bit 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value 0 0 0 0 0 Read/Write W W W W W 0 W 0 0 W W P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be returned. P2DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. The address output pins maintain their output state in a transition to software standby mode. • Mode 1 The corresponding port 2 pins are address outputs, regardless of the P2DDR setting. In hardware standby mode, the address outputs go to the high-impedance state. • Modes 2 and 3 (EXPE = 1) The corresponding port 2 pins are address outputs or PWM outputs when P2DDR bits are set to 1, and input ports when cleared to 0. P27 to P24 are switched from address outputs to output ports by setting the IOSE bit to 1. P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting, but to ensure normal access to external space, P27 should not be set as an on-chip supporting module output pin when port 2 pins are used as address output pins. 202 • Modes 2 and 3 (EXPE = 0) The corresponding port 2 pins are output ports or PWM outputs when P2DDR bits are set to 1, and input ports when cleared to 0. P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting. Port 2 Data Register (P2DR) Bit Initial value R/W 7 6 5 4 3 2 1 0 P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR 0 0 0 R/W R/W 0 0 0 0 0 R/W R/W R/W R/W R/W R/W P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P27 to P20). If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read directly, regardless of the actual pin states. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. P2DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port 2 MOS Pull-Up Control Register (P2PCR) Bit 7 6 5 4 3 2 1 0 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P2PCR is an 8-bit readable/writable register that controls the port 2 built-in MOS input pull-ups on a bit-by-bit basis. In modes 2 and 3, the MOS input pull-up is turned on when a P2PCR bit is set to 1 while the corresponding P2DDR bit is cleared to 0 (input port setting). P2PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 203 8.3.3 Pin Functions in Each Mode Mode 1: In mode 1, port 2 pins automatically function as address outputs. The port 2 pin functions are shown in figure 8.6. A15 (Output) A14 (Output) A13 (Output) Port 2 A12 (Output) A11 (Output) A10 (Output) A9 (Output) A8 (Output) Figure 8.6 Port 2 Pin Functions (Mode 1) Modes 2 and 3 (EXPE = 1): In modes 2 and 3 (when EXPE = 1), port 2 pins function as address outputs, PWM outputs, or I/O ports, and input or output can be specified on a bit-by-bit basis. When a bit in P2DDR is set to 1, the corresponding pin functions as an address output or PWM output, and when cleared to 0, as an input port. P27 to P24 are switched from address outputs to output ports by setting the IOSE bit to 1. P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting, but to ensure normal access to external space, P27 should not be set as an on-chip supporting module output pin when port 2 pins are used as address output pins. The port 2 pin functions are shown in figure 8.7. When P2DDR = 1 and PWOERB = 0 When P2DDR = 0 When P2DDR = 1 and PWOERB = 1 A15 (Output)/P27 (Output) P27 (Input)/CBLANK (Output) PW15 (Output)/CBLANK (Output) Port 2 A14 (Output)/P26 (Output) P26 (Input) PW14 (Output) A13 (Output)/P25 (Output) P25 (Input) PW13 (Output) A12 (Output)/P24 (Output) P24 (Input) PW12 (Output) A11 (Output) P23 (Input) PW11 (Output) A10 (Output) P22 (Input) PW10 (Output) A9 (Output) P21 (Input) PW9 (Output) A8 (Output) P20 (Input) PW8 (Output) Figure 8.7 Port 2 Pin Functions (Modes 2 and 3 (EXPE = 1)) 204 Modes 2 and 3 (EXPE = 0): In modes 2 and 3 (when EXPE = 0), port 2 pins function as PWM outputs (timer connection output (CBLANK)) or I/O ports, and input or output can be specified on a bit-by-bit basis. When a bit in P2DDR is set to 1, the corresponding pin functions as a PWM output or output port, and when cleared to 0, as an input port. P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting. The port 2 pin functions are shown in figure 8.8. Port 2 P2n: Input pin when P2DDR = 0, output pin when P2DDR = 1 and PWOERB = 0 When P2DDR = 1 and PWOERB = 1 P27 (I/O)/CBLANK (Output) PW15 (Output)/CBLANK (Output) P26 (I/O) PW14 (Output) P25 (I/O) PW13 (Output) P24 (I/O) PW12 (Output) P23 (I/O) PW11 (Output) P22 (I/O) PW10 (Output) P21 (I/O) PW9 (Output) P20 (I/O) PW8 (Output) Figure 8.8 Port 2 Pin Functions (Modes 2 and 3 (EXPE = 0)) 8.3.4 MOS Input Pull-Up Function Port 2 has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bit-bybit basis. When a P2DDR bit is cleared to 0 in mode 2 or 3, setting the corresponding P2PCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.5 summarizes the MOS input pull-up states. 205 Table 8.5 MOS Input Pull-Up States (Port 2) Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1 Off Off Off Off 2, 3 Off Off On/Off On/Off Legend: Off: MOS input pull-up is always off. On/Off: On when P2DDR = 0 and P2PCR = 1; otherwise off. 206 8.4 Port 3 8.4.1 Overview Port 3 is an 8-bit I/O port. Port 3 pins also have host interface (LPC) input/output (SERIRQ, LCLK, LRESET, LFRAME, LAD3 to LAD0), host interface (XBS) data bus input/output (HDB7 to HDB0), and as data bus I/O pins. Port 3 functions change according to the operating mode. Port 3 has a built-in MOS input pull-up function that can be controlled by software. Figure 8.9 shows the port 3 pin configuration. Port 3 Port 3 pins Pin functions in modes 1, 2 and 3 (EXPE = 1) P37/D15/HDB7/SERIRQ D15 (I/O) P36/D14/HDB6/LCLK D14 (I/O) P35/D13/HDB5/LRESET D13 (I/O) P34/D12/HDB4/LFRAME D12 (I/O) P33/D11/HDB3/LAD3 D11 (I/O) P32/D10/HDB2/LAD2 D10 (I/O) P31/D9/HDB1/LAD1 D9 (I/O) P30/D8/HDB0/LAD0 D8 (I/O) Pin functions in modes 2 and 3 (EXPE = 0) P37 (I/O)/HDB7 (I/O)/SERIRQ (I/O) P36 (I/O)/HDB6 (I/O)/LCLK (Input) P35 (I/O)/HDB5 (I/O)/LRESET (Input) P34 (I/O)/HDB4 (I/O)/LFRAME (Input) P33 (I/O)/HDB3 (I/O)/LAD3 (I/O) P32 (I/O)/HDB2 (I/O)/LAD2 (I/O) P31 (I/O)/HDB1 (I/O)/LAD1 (I/O) P30 (I/O)/HDB0 (I/O)/LAD0 (I/O) Figure 8.9 Port 3 Pin Functions 207 8.4.2 Register Configuration Table 8.6 shows the port 3 register configuration. Table 8.6 Port 3 Registers Name Abbreviation R/W Initial Value Address* Port 3 data direction register P3DDR W H'00 H'FFB4 Port 3 data register P3DR R/W H'00 H'FFB6 Port 3 MOS pull-up control register P3PCR R/W H'00 H'FFAE Note: * Lower 16 bits of the address. Port 3 Data Direction Register (P3DDR) Bit 7 6 5 4 3 2 1 0 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value 0 0 0 0 0 Read/Write W W W W W 0 W 0 0 W W P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. P3DDR cannot be read; if it is, an undefined value will be returned. P3DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. • Modes 1, 2, and 3 (EXPE = 1) The input/output direction specified by P3DDR is ignored, and pins automatically function as data I/O pins. After a reset, and in hardware standby mode or software standby mode, the data I/O pins go to the high-impedance state. • Modes 2 and 3 (EXPE = 0) The corresponding port 3 pins are output ports when P3DDR bits are set to 1, and input ports when cleared to 0. 208 Port 3 Data Register (P3DR) 7 6 5 4 3 2 1 0 P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P37 to P30). If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly, regardless of the actual pin states. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. P3DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port 3 MOS Pull-Up Control Register (P3PCR) Bit 7 6 5 4 3 2 1 0 P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Initial value 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W 0 R/W 0 0 R/W R/W P3PCR is an 8-bit readable/writable register that controls the port 3 built-in MOS input pull-ups on a bit-by-bit basis. In modes 2 and 3 (when EXPE = 0), the MOS input pull-up is turned on when a P3PCR bit is set to 1 while the corresponding P3DDR bit is cleared to 0 (input port setting). P3PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. The MOS input pull-up function cannot be used when the host interface is enabled. 209 8.4.3 Pin Functions in Each Mode Modes 1, 2, and 3 (EXPE = 1): In modes 1, 2, and 3 (when EXPE = 1), port 3 pins automatically function as data I/O pins. It is recommended that all the host interface enable bits multiplexed as port 3 bits in single-chip mode (bit HI12E in SYSCR2 and bits LPC3E to LPC1E in HICR0) be cleared to 0. The port 3 pin functions are shown in figure 8.10. D15 (I/O) D14 (I/O) D13 (I/O) Port 3 D12 (I/O) D11(I/O) D10 (I/O) D9 (I/O) D8 (I/O) Figure 8.10 Port 3 Pin Functions (Modes 1, 2, and 3 (EXPE = 1)) Modes 2 and 3 (EXPE = 0): In modes 2 and 3 (when EXPE = 0), port 3 functions as host interface (LPC) I/O pins (SERIRQ, LCLK, LRESET, LFRAME, LAD3 to LAD0), as host interface (XBS) data bus I/O pins (HDB7 to HDB0), or as an I/O port. The priority order for pin function settings is: LPC, XBS, I/O port. When at least one of bits LPC3E to LPC1E is set to 1 in HICR0, port 3 functions as host interface (LPC) I/O pins. Even in this state, it is recommended that the HI12E bit be cleared to 0 in SYSCR2. P3DR and P3DDR should be cleared to H'00. When the HI12E bit is set to 1 in SYSCR2, port 3 functions as the host interface (XBS) data bus. In this case, P3DR and P3DDR should be cleared to H'00. When bits LPC3E to LPC1E and HI12E are all cleared to 0, port 3 functions as an I/O port, and input or output can be specified on a bit-by-bit basis. When a bit in P3DDR is set to 1, the corresponding pin functions as an output port, and when cleared to 0, as an input port. The port 3 pin functions are shown in figure 8.11. 210 P37 (I/O)/HDB7 (I/O)/SERIRQ (I/O) P36 (I/O)/HDB6 (I/O)/LCLK (Input) P35 (I/O)/HDB5 (I/O)/LRESET (Input) Port 3 P34 (I/O)/HDB4 (I/O)/LFRAME (Input) P33 (I/O)/HDB3 (I/O)/LAD3 (I/O) P32 (I/O)/HDB2 (I/O)/LAD2 (I/O) P31 (I/O)/HDB1 (I/O)/LAD1 (I/O) P30 (I/O)/HDB0 (I/O)/LAD0 (I/O) Figure 8.11 Port 3 Pin Functions (Modes 2 and 3 (EXPE = 0)) 8.4.4 MOS Input Pull-Up Function Port 3 has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2 and 3 (when EXPE = 0), and can be specified as on or off on a bit-by-bit basis. When a P3DDR bit is cleared to 0 in mode 2 or 3 (when EXPE = 0), setting the corresponding P3PCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.7 summarizes the MOS input pull-up states. Table 8.7 MOS Input Pull-Up States (Port 3) Hardware Standby Mode Software Standby Mode In Other Operations 1, 2, 3 (EXPE = 1) Off Off Off Off 2, 3 (EXPE = 0) Off On/Off On/Off Mode Reset Off Legend: Off: MOS input pull-up is always off. On/Off: On when P3DDR = 0 and P3PCR = 1; otherwise off. 211 8.5 Port 4 8.5.1 Overview Port 4 is an 8-bit I/O port. Port 4 pins also function as 14-bit PWM output pins (PWX1, PWX0), 8-bit timer 0 and 1 (TMR0, TMR1) I/O pins (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection I/O pins (CSYNCI, HSYNCI, HSYNCO), SCI2 I/O pins (TxD2, RxD2, SCK2), IrDA interface I/O pins (IrTxD, IrRxD), host interface (XBS) output pins (HIRQ12, HIRQ1, HIRQ11), and the IIC1 I/O pin (SDA1). Port 4 pin functions are the same in all operating modes. Figure 8.12 shows the port 4 pin configuration. Port 4 pins P47 (I/O)/PWX1 (Output) P46 (I/O)/PWX0 (Output) P45 (I/O)/TMRI1 (Input)/HIRQ12 (Output)/CSYNCI (Input) Port 4 P44 (I/O)/TMO1 (Output)/HIRQ1 (Output)/HSYNCO (Output) P43 (I/O)/TMCI1 (Input)/HIRQ11 (Output)/HCYNCI (Input) P42 (I/O)/TMRI0 (Input)/SCK2 (I/O)/SDA1 (I/O) P41 (I/O)/TMO0 (Output)/RxD2 (Input)/IrRxD (Input) P40 (I/O)/TMCI0 (Input)/TxD2 (Output)/IrTxD (Output) Figure 8.12 Port 4 Pin Functions 8.5.2 Register Configuration Table 8.8 shows the port 4 register configuration. Table 8.8 Port 4 Registers Name Abbreviation R/W Initial Value Address* Port 4 data direction register P4DDR W H'00 H'FFB5 Port 4 data register P4DR R/W H'00 H'FFB7 Note: * Lower 16 bits of the address. 212 Port 4 Data Direction Register (P4DDR) 7 Bit 6 5 4 3 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W P4DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 4. P4DDR cannot be read; if it is, an undefined value will be returned. When a bit in P4DDR is set to 1, the corresponding pin functions as an output port, and when cleared to 0, as an input port. P4DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. As 14-bit PWM and SCI2 are initialized in software standby mode, the pin states are determined by the TMR0, TMR1, XBS, IIC1, P4DDR, and P4DR specifications. Port 4 Data Register (P4DR) 7 6 5 4 3 2 1 0 P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit P4DR is an 8-bit readable/writable register that stores output data for the port 4 pins (P47 to P40). If a port 4 read is performed while P4DDR bits are set to 1, the P4DR values are read directly, regardless of the actual pin states. If a port 4 read is performed while P4DDR bits are cleared to 0, the pin states are read. P4DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 8.5.3 Pin Functions Port 4 pins also function as 14-bit PWM output pins (PWX1, PWX0), 8-bit timer 0 and 1 (TMR0, TMR1) I/O pins (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection I/O pins (CSYNCI, HSYNCI, HSYNCO), SCI2 I/O pins (TxD2, RxD2, SCK2), IrDA interface I/O pins (IrTxD, IrRxD), host interface (XBS) output pins (HIRQ12, HIRQ1, HIRQ11), and the IIC1 I/O pin (SDA1). The port 4 pin functions are shown in table 8.9. 213 Table 8.9 Port 4 Pin Functions Pin Selection Method and Pin Functions P47/PWX1 The pin function is switched as shown below according to the combination of bit OEB in DACR of 14-bit PWM, and bit P47DDR. OEB 0 P47DDR Pin function P46/PWX0 0 1 — P47 input pin P47 output pin PWX1 output pin The pin function is switched as shown below according to the combination of bit OEA in DACR of 14-bit PWM, and bit P46DDR. OEA 0 P46DDR Pin function P45/TMRI1/ HIRQ12/CSYNCI 1 1 0 1 — P46 input pin P46 output pin PWX0 output pin The pin function is switched as shown below according to the combination of bit HI12E in SYSCR2, and bit P45DDR. P45DDR 0 HI12E — 0 1 P45 input pin P45 output pin HIRQ12 output pin Pin function 1 TMRI1 input pin, CSYNCI input pin When bits CCLR1 and CCLR0 in TCR1 of TMR1 are set to 1, this pin is used as the TMRI1 input pin. It can also be used as the CSYNCI input pin. P44/TMO1/ HIRQ1/HSYNCO The pin function is switched as shown below according to the combination of bit HI12E in SYSCR2, bits OS3 to OS0 in TCSR of TMR1, bit HOE in TCONRO of the timer connection function, and bit P44DDR. HOE 0 OS3 to OS0 All 0 1 Not all 0 — — — P44DDR 0 HI12E — 0 1 — — P44 input pin P44 output pin HIRQ1 output pin TMO1 output pin HSYNCO output pin Pin function 214 1 Pin Selection Method and Pin Functions P43/TMCI1/ HIRQ11/HSYNCI The pin function is switched as shown below according to the combination of bit HI12E in SYSCR2 and bit P43DDR. P43DDR 0 HI12E — 0 1 P43 input pin P43 output pin HIRQ11 output pin Pin function 1 TMCI1 input pin, HSYNCI input pin When an external clock is selected with bits CKS2 to CKS0 in TCR1 of TMR1, this pin is used as the TMCI1 input pin. It can also be used as the HSYNCI input pin. P42/TMRI0/ SCK2/SDA1 The pin function is switched as shown below according to the combination of bit ICE in ICCR of IIC1, bits CKE1 and CKE0 in SCR of SCI2, bit C/A in SMR of SCI2, and bit P42DDR. ICE 0 CKE1 0 C/A Pin function 1 0 1 — 0 1 — — 0 — — — — 0 CKE0 P42DDR 1 0 0 1 P42 P42 SCK2 SCK2 SCK2 input pin output pin output pin output pin input pin SDA1 I/O pin TMRI0 input pin When this pin is used as the SDA1 I/O pin, bits CKE1 and CKE0 in SCR of SCI2 and bit C/A in SMR of SCI2 must all be cleared to 0. SDA1 is an NMOSonly output, and has direct bus drive capability. When bits CCLR1 and CCLR0 in TCR0 of TMR0 are set to 1, this pin is used as the TMRI0 input pin. 215 Pin Selection Method and Pin Functions P41/TMO0/RxD2/ The pin function is switched as shown below according to the combination of IrRxD bits OS3 to OS0 in TCSR of TMR0, bit RE in SCR of SCI2 and bit P41DDR. OS3 to OS0 All 0 RE P41DDR Pin function Not all 0 0 1 0 0 1 — — P41 input pin P41 output pin RxD2/IrRxD input pin TMO0 output pin When this pin is used as the TMO0 output pin, bit RE in SCR of SCI2 must be cleared to 0. P40/TMCI0/TxD2/ The pin function is switched as shown below according to the combination of IrTxD bit TE in SCR of SCI2 and bit P40DDR. TE P40DDR Pin function 0 1 0 1 — P40 input pin P40 output pin TxD2/IrTxD output pin TMCI0 input pin When an external clock is selected with bits CKS2 to CKS0 in TCR0 of TMR0, this pin is used as the TMCI0 input pin. 216 8.6 Port 5 8.6.1 Overview Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI0 I/O pins (TxD0, RxD0, SCK0), and the IIC0 I/O pin (SCL0). P52 and SCK0 are NMOS push-pull outputs, and SCL0 is an NMOS opendrain output. Port 5 pin functions are the same in all operating modes. Figure 8.13 shows the port 5 pin configuration. Port 5 pins P52 (I/O)/SCK0 (I/O)/SCL0 (I/O) Port 5 P51 (I/O)/RxD0 (Input) P50 (I/O)/TxD0 (Output) Figure 8.13 Port 5 Pin Functions 8.6.2 Register Configuration Table 8.10 shows the port 5 register configuration. Table 8.10 Port 5 Registers Name Abbreviation R/W Initial Value Address* Port 5 data direction register P5DDR W H'F8 H'FFB8 Port 5 data register P5DR R/W H'F8 H'FFBA Note: * Lower 16 bits of the address. 217 Port 5 Data Direction Register (P5DDR) 7 6 5 4 3 — — — — — Initial value 1 1 1 1 1 0 0 0 Read/Write — — — — — W W W Bit 2 1 0 P52DDR P51DDR P50DDR P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be returned. Bits 7 to 3 are reserved. Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P5DDR is initialized to H'F8 by a reset and in hardware standby mode. It retains its prior state in software standby mode. As SCI0 is initialized, the pin states are determined by the IIC0 ICCR, P5DDR, and P5DR specifications. Port 5 Data Register (P5DR) Bit 7 6 5 4 3 2 1 0 — — — — — P52DR P51DR P50DR 0 0 0 R/W R/W Initial value 1 1 1 1 1 Read/Write — — — — — R/W P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P52 to P50). If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly, regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read. Bits 7 to 3 are reserved; they cannot be modified and are always read as 1. P5DR is initialized to H'F8 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 218 8.6.3 Pin Functions Port 5 pins also function as SCI0 I/O pins (TxD0, RxD0, SCK0) and the IIC0 I/O pin (SCL0). The port 5 pin functions are shown in table 8.11. Table 8.11 Port 5 Pin Functions Pin Selection Method and Pin Functions P52/SCK0/SCL0 The pin function is switched as shown below according to the combination of bits CKE1 and CKE0 in SCR of SCI0, bit C/A in SMR of SCI0, bit ICE in ICCR of IIC0, and bit P52DDR. ICE 0 CKE1 0 C/A Pin function 1 0 1 — 0 1 — — 0 — — — — 0 CKE0 P52DDR 1 0 0 1 P52 P52 SCK0 SCK0 SCK0 input pin output pin output pin output pin input pin SCL0 I/O pin When this pin is used as the SCL0 I/O pin, bits CKE1 and CKE0 in SCR of SCI0 and bit C/A in SMR of SCI0 must all be cleared to 0. SCL0 is an NMOS open-drain output, and has direct bus drive capability. When set as the P52 output pin or SCK0 output pin, this pin is an NMOS pushpull output. P51/RxD0 The pin function is switched as shown below according to the combination of bit RE in SCR of SCI0 and bit P51DDR. RE P51DDR Pin function P50/TxD0 0 1 0 1 — P51 input pin P51 output pin RxD0 input pin The pin function is switched as shown below according to the combination of bit TE in SCR of SCI0 and bit P50DDR. TE P50DDR Pin function 0 1 0 1 — P50 input pin P50 output pin TxD0 output pin 219 8.7 Port 6 8.7.1 Overview Port 6 is an 8-bit I/O port. Port 6 pins also function as the 16-bit free-running timer (FRT) I/O pins (FTOA, FTOB, FTIA to FTID, FTCI), timer X (TMRX) I/O pins (TMOX, TMIX), the timer Y (TMRY) input pin (TMIY), timer connection I/O pins (HFBACKI, VSYNCI, VSYNCO, VFBACKI, CLAMPO), key-sense interrupt input pins (KIN7 to KIN0), expansion A/D converter input pins (CIN7 to CIN0), and external interrupt input pins (IRQ7, IRQ6). The port 6 input level can be switched in four stages. Port 6 pin functions are the same in all operating modes. Figure 8.14 shows the port 6 pin configuration. Port 6 pins P67 (I/O)/TMOX (Output)/KIN7 (Input)/CIN7 (Input)/IRQ7 (Input) P66 (I/O)/FTOB (Output)/KIN6 (Input)/CIN6 (Input)/IRQ6 (Input) P65 (I/O)/FTID (Input)/KIN5 (Input)/CIN5 (Input) Port 6 P64 (I/O)/FTIC (Input)/KIN4 (Input)/CIN4 (Input)/CLAMPO (Output) P63 (I/O)/FTIB (Input)/KIN3 (Input)/CIN3 (Input)/VFBACKI (Input) P62 (I/O)/FTIA (Input)/KIN2 (Input)/CIN2 (Input)/VSYNCI (Input)/TMIY (Input) P61 (I/O)/FTOA (Output)/KIN1 (Input)/CIN1 (Input)/VSYNCO (Output) P60 (I/O)/FTCI (Input)/KIN0 (Input)/CIN0 (Input)/HFBACKI (Input)/TMIX (Input) Figure 8.14 Port 6 Pin Functions 220 8.7.2 Register Configuration Table 8.12 shows the port 6 register configuration. Table 8.12 Port 6 Registers Name Abbreviation R/W Initial Value Address* 1 Port 6 data direction register P6DDR W H'00 H'FFB9 Port 6 data register P6DR R/W H'00 H'FFBB Port 6 MOS pull-up control register KMPCR R/W H'00 H'FFF2* 2 System control register SYSCR2 R/W H'00 H'FF83 Notes: 1. Lower 16 bits of the address. 2. KMPCR has the same address as TICRR/TCORAY of TMRX/TMRY. To select KMPCR, set the HIE bit to 1 in SYSCR and set the MSTP2 bit to 0 in MSTPCRL. Port 6 Data Direction Register (P6DDR) Bit 7 6 5 4 3 2 1 0 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value 0 0 0 0 0 Read/Write W W W W W 0 W 0 0 W W P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be returned. Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P6DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 221 Port 6 Data Register (P6DR) 7 6 5 4 3 2 1 0 P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P67 to P60). If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read directly, regardless of the actual pin states. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read. P6DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port 6 MOS Pull-Up Control Register (KMPCR) Bit 7 6 5 4 3 2 1 0 KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W KMPCR is an 8-bit readable/writable register that controls the port 6 built-in MOS input pull-ups on a bit-by-bit basis. The MOS input pull-up is turned on when a KMPCR bit is set to 1 while the corresponding P6DDR bit is cleared to 0 (input port setting). KMPCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 222 System Control Register 2 (SYSCR2) Bit 7 6 5 4 3 2 1 0 KWUL1 KWUL0 P6PUE — SDE CS4E CS3E HI12E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W — R/W R/W R/W R/W SYSCR2 is an 8-bit readable/writable register that controls port 6 input level selection and the operation of host interface functions. Only bits 7, 6, and 5 are described here. See section 18A.2.2, System Control Register 2 (SYSCR2), for information on bits 4 to 0. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6—Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level setting can be changed by software, using these bits. The setting of these bits also changes the input level of the pin functions multiplexed with port 6. Bit 7 Bit 6 KWUL1 KWUL0 Description 0 0 Standard input level is selected as port 6 input level 1 Input level 1 is selected as port 6 input level 0 Input level 2 is selected as port 6 input level 1 Input level 3 is selected as port 6 input level 1 (Initial value) Bit 5—Port 6 Input Pull-Up Extra (P6PUE): Controls and selects the current specification for the port 6 MOS input pull-up function connected by means of KMPCR settings. Bit 5 P6PUE Description 0 Standard current specification is selected for port 6 MOS input pull-up function (Initial value) 1 Current-limit specification is selected for port 6 MOS input pull-up function 223 8.7.3 Pin Functions Port 6 pins also function as the 16-bit free-running timer (FRT) I/O pins (FTOA, FTOB, FTIA to FTID, FTCI), timer X (TMRX) I/O pins (TMOX, TMIX), the timer Y (TMRY) input pin (TMIY), timer connection I/O pins (HFBACKI, VSYNCI, VSYNCO, VFBACKI, CLAMPO), key-sense interrupt input pins (KIN7 to KIN0), expansion A/D input pins (CIN7 to CIN0), and interrupt input pins (IRQ7, IRQ6). The port 6 input level can be switched in four stages. The port 6 pin functions are shown in table 8.13. Table 8.13 Port 6 Pin Functions Pin Selection Method and Pin Functions P67/TMOX/IRQ7/ KIN7/CIN7 The pin function is switched as shown below according to the combination of bits OS3 to OS0 in TCSR of TMRX and bit P67DDR. OS3 to OS0 P67DDR Pin function All 0 Not all 0 0 1 — P67 input pin P67 output pin TMOX output pin IRQ7 input pin, KIN7 input pin, CIN7 input pin This pin is used as the IRQ7 input pin when bit IRQ7E is set to 1 in IER. It can always be used as the KIN7 or CIN7 input pin. P66/FTOB/IRQ6/ KIN6/CIN6 The pin function is switched as shown below according to the combination of bit OEB in TOCR of the FRT and bit P66DDR. OEB P66DDR Pin function 0 1 0 1 — P66 input pin P66 output pin FTOB output pin IRQ6 input pin, KIN6 input pin, CIN6 input pin This pin is used as the IRQ6 input pin when bit IRQ6E is set to 1 in IER. It can always be used as the KIN6 or CIN6 input pin. P65/FTID/KIN5/ CIN5 P65DDR Pin function 0 1 P65 input pin P65 output pin FTID input pin, KIN5 input pin, CIN5 input pin This pin can always be used as the FTID, KIN5, or CIN5 input pin. 224 Pin Selection Method and Pin Functions P64/FTIC/KIN4/ CIN4/CLAMPO The pin function is switched as shown below according to the combination of bit CLOE in TCONRO of the timer connection function and bit P64DDR. CLOE 0 P64DDR Pin function 1 0 1 — P64 input pin P64 output pin CLAMPO output pin FTIC input pin, KIN4 input pin, CIN4 input pin This pin can always be used as the FTIC, KIN4, or CIN4 input pin. P63/FTIB/KIN3/ CIN3/VFBACKI P63DDR Pin function 0 1 P63 input pin P63 output pin FTIB input pin, VFBACKI input pin, KIN3 input pin, CIN3 input pin This pin can always be used as the FTIB, KIN3, CIN3, or VFBACKI input pin. P62/FTIA/TMIY/ KIN2/CIN2/ VSYNCI P62DDR Pin function 0 1 P62 input pin P62 output pin FTIA input pin, VSYNCI input pin, TMIY input pin, KIN2 input pin, CIN2 input pin This pin can always be used as the FTIA, TMIY, KIN2, CIN2, or VSYNCI input pin. P61/FTOA/KIN1/ CIN1/VSYNCO The pin function is switched as shown below according to the combination of bit OEA in TOCR of the FRT, bit VOE in TCONRO of the timer connection function, and bit P61DDR. VOE 0 OEA P61DDR Pin function 0 1 1 0 0 1 — — P61 input pin P61 output pin FTOA output pin VSYNCO output pin KIN1 input pin, CIN1 input pin When this pin is used as the VSYNCO pin, bit OEA in TOCR of the FRT must be cleared to 0. This pin can always be used as the KIN1 or CIN1 input pin. 225 Pin Selection Method and Pin Functions P60/FTCI/TMIX/ KIN0/CIN0/ HFBACKI P60DDR Pin function 0 1 P60 input pin P60 output pin FTCI input pin, HFBACKI input pin, TMIX input pin, KIN0 input pin, CIN0 input pin This pin is used as the FTCI input pin when an external clock is selected with bits CKS1 and CKS0 in TCR of the FRT. It can always be used as the TMIX, KIN0, CIN0, or HFBACKI input pin. 8.7.4 MOS Input Pull-Up Function Port 6 has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis. When a P6DDR bit is cleared to 0, setting the corresponding KMPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up current specification can be changed by means of the P6PUE bit. When a pin is designated as an on-chip supporting module output pin, the MOS input pull-up is always off. The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.14 summarizes the MOS input pull-up states. Table 8.14 MOS Input Pull-Up States (Port 6) Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1, 2, 3 Off Off On/Off On/Off Legend: Off: MOS input pull-up is always off. On/Off: On when P6DDR = 0 and KMPCR = 1; otherwise off. 226 8.8 Port 7 8.8.1 Overview Port 7 is an 8-bit input only port. Port 7 pins also function as the A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0, DA1). Port 7 functions are the same in all operating modes. Figure 8.15 shows the port 7 pin configuration. Port 7 pins P77 (Input)/AN7 (Input)/DA1 (Output) P76 (Input)/AN6 (Input)/DA0 (Output) P75 (Input)/AN5 (Input) P74 (Input)/AN4 (Input) Port 7 P73 (Input)/AN3 (Input) P72 (Input)/AN2 (Input) P71 (Input)/AN1 (Input) P70 (Input)/AN0 (Input) Figure 8.15 Port 7 Pin Functions 8.8.2 Register Configuration Table 8.15 shows the port 7 register configuration. Port 7 is an input-only port, and does not have a data direction register or data register. Table 8.15 Port 7 Registers Name Abbreviation R/W Initial Value Address* 1 Port 7 input data register P7PIN R Undefined H'FFBE* 2 Notes: 1. Lower 16 bits of the address. 2. P7PIN has the same address as PBDDR. 227 Port 7 Input Data Register (P7PIN) 7 Bit P77PIN 6 5 4 3 2 P76PIN P75PIN P74PIN P73PIN P72PIN 1 0 P71PIN P70PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R R Note: * Determined by the state of pins P77 to P70. When a P7PIN read is performed, the pin states are always read. P7PIN has the same address as PBDDR; if a write is performed, data will be written into PBDDR and the port B setting will be changed. 8.8.3 Pin Functions Port 7 pins also function as the A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0, DA1). 228 8.9 Port 8 8.9.1 Overview Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI1 I/O pins (TxD1, RxD1, SCK1), the IIC1 I/O pin (SCL1), host interface (XBS) I/O pins (CS2, GA20, HA0, HIFSD), host interface (LPC) I/O pins (PME, GA20, CLKRUN, LPCPD), and interrupt input pins (IRQ5 to IRQ3). Port 8 pin functions are the same in all operating modes except host interface function. Figure 8.16 shows the port 8 pin configuration. Port 8 pins P86 (I/O)/IRQ5 (Input)/SCK1 (I/O)/SCL1 (I/O) P85 (I/O)/IRQ4 (Input)/RxD1 (Input) P84 (I/O)/IRQ3 (Input)/TxD1 (Output) Port 8 P83 (I/O)/LPCPD (Input) P82 (I/O)/HIFSD (Input)/CLKRUN (I/O) P81 (I/O)/CS2 (Input)/GA20 (I/O) P80 (I/O)/HA0 (Input)/PME (I/O) Figure 8.16 Port 8 Pin Functions 8.9.2 Register Configuration Table 8.16 summarizes the port 8 registers. Table 8.16 Port 8 Registers Name Abbreviation R/W Initial Value Address*1 Port 8 data direction register P8DDR W H'80 H'FFBD* 2 Port 8 data register P8DR R/W H'80 H'FFBF Notes: 1. Lower 16 bits of the address. 2. P8DDR has the same address as PBPIN. 229 Port 8 Data Direction Register (P8DDR) Bit 7 — 6 5 4 3 2 1 0 P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial value 1 0 0 0 0 0 0 0 Read/Write — W W W W W W W P8DDR is a 7-bit write-only register, the individual bits of which specify input or output for the pins of port 8. P8DDR has the same address as PBPIN, and if read, the port B state will be returned. Setting a P8DDR bit to 1 makes the corresponding port 8 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P8DDR is initialized to H'80 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port 8 Data Register (P8DR) Bit 7 6 5 4 3 2 1 0 — P86DR P85DR P84DR P83DR P82DR P81DR P80DR Initial value 1 0 0 0 0 0 0 0 Read/Write — R/W R/W R/W R/W R/W R/W R/W P8DR is a 7-bit readable/writable register that stores output data for the port 8 pins (P86 to P80). If a port 8 read is performed while P8DDR bits are set to 1, the P8DR values are read directly, regardless of the actual pin states. If a port 8 read is performed while P8DDR bits are cleared to 0, the pin states are read. P8DR is initialized to H'80 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 8.9.3 Pin Functions Port 8 pins also function as SCI1 I/O pins (TxD1, RxD1, SCK1), the IIC1 I/O pin (SCL1), host interface (HIF) I/O pins (CS2, GA20, HA0, HIFSD), host interface (LPC) I/O pins (PME, GA20, CLKRUN, LPCPD), and interrupt input pins (IRQ5 to IRQ3). The port 8 pin functions are shown in table 8.17. 230 Table 8.17 Port 8 Pin Functions Pin Selection Method and Pin Functions P86/IRQ5/SCK1/ SCL1 The pin function is switched as shown below according to the combination of bits CKE1 and CKE0 in SCR of SCI1, bit C/A in SMR of SCI1, bit ICE in ICCR of IIC1, and bit P86DDR. ICE 0 CKE1 0 C/A Pin function 1 0 1 — 0 1 — — 0 — — — — 0 CKE0 P86DDR 1 0 0 1 P86 P86 SCK1 SCK1 SCK1 input pin output pin output pin output pin input pin SCL1 I/O pin IRQ5 input pin When the IRQ5E bit in IER is set to 1, this pin is used as the IRQ5 input pin. When this pin is used as the SCL1 I/O pin, bits CKE1 and CKE0 in SCR of SCI1 and bit C/A in SMR of SCI1 must all be cleared to 0. SCL1 is an NMOSonly output, and has direct bus drive capability. P85/IRQ4/RxD1 The pin function is switched as shown below according to the combination of bit RE in SCR of SCI1 and bit P85DDR. RE P85DDR Pin function 0 1 0 1 — P85 input pin P85 output pin RxD1 input pin IRQ4 input pin When the IRQ4E bit in IER is set to 1, this pin is used as the IRQ4 input pin. P84/IRQ3/TxD1 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI1 and bit P84DDR. TE P84DDR Pin function 0 1 0 1 — P84 input pin P84 output pin TxD1 output pin IRQ3 input pin When the IRQ3E bit in IER is set to 1, this pin is used as the IRQ3 input pin. 231 Pin Selection Method and Pin Functions P83/LPCPD The pin function is switched as shown below according to bit P83DDR. P83DDR Pin function 0 1 P83 input pin P83 output pin LPCPD input pin When at least one of bits LPC3E to LPC1E is set to 1 in HICR0, this pin is used as the LPCPD input pin. The LPCPD input pin can only be used in mode 2 or 3 (EXPE = 0). P82/HIFSD/ CLKRUN The pin function is switched as shown below according to the combination of bits HI12E and SDE in SYSCR2, bits LPC3E to LPC1E in HICR0, and bit P82DDR. Note: * When at least one of bits LPC3E to LPC1E is set to 1, bits HI12E and P82DDR should be cleared to 0. LPC3E to LPC1E All 0 HI12E 0 SDE — P82DDR Pin function 0 Not all 0 1 0 1 0 1 —* 1 — — —* P82 P82 P82 P82 HIFSD CLKRUN input pin output pin input pin output pin input pin I/O pin The HIFSD input pin and CLKRUN I/O pin can only be used in mode 2 or 3 (EXPE = 0). 232 Pin Selection Method and Pin Functions P81/GA20/CS2 The pin function is switched as shown below according to the combination of bit HI12E in SYSCR2, bit CS2E in SYSCR, bit FGA20E in HICR, bit FGA20E in HICR0, and bit P81DDR. Note: * When bit FGA20E is set to 1 in HICR0, bits HI12E and P81DDR should be cleared to 0. FGA20E (LPC) 0 HI12E 0 FGA20E (XBS) — CS2E — P81DDR Pin function 0 1 —* 0 0 1 P81 input pin 1 0 1 1 — — — — 0 P81 CS2 output input pin pin P81 P81 output input pin pin 1 P81 input pin 1 — GA20 GA20 output output pin pin GA20 input pin The GA20 output pin and CS2 input pin can only be used in mode 2 or 3 (EXPE = 0). P80/HA0/PME The pin function is switched as shown below according to the combination of bit HI12E in SYSCR2, bit PMEE in HICR0, and bit P80DDR. Note: * When bit PMEE is set to 1 in HICR0, bits HI12E and P80DDR should be cleared to 0. PMEE 0 HI12E P80DDR Pin function 1 0 0 P80 input pin 1 1 —* — —* P80 output pin HA0 input pin PME output pin PME input pin The HA0 input pin can only be used in mode 2 or 3 (EXPE = 0). 233 8.10 Port 9 8.10.1 Overview Port 9 is an 8-bit I/O port. Port 9 pins also function as external interrupt input pins (IRQ0 to IRQ2), the A/D converter external trigger input pin (ADTRG), host interface (XBS) input pins (ECS2, CS1, IOW, IOR), the IIC0 I/O pin (SDA0), the subclock input pin (EXCL), bus control signal I/O pins (AS/IOS, RD, HWR, LWR, WAIT), and the system clock (ø) output pin. P97 is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and has direct bus drive capability. Figure 8.17 shows the port 9 pin configuration. Port 9 Port 9 pins Pin functions in modes 1, 2 and 3 (EXPE = 1) P97/WAIT/SDA0 WAIT (Input)/P97 (I/O)/SDA0 (I/O) P96/ø/EXCL ø (Output)/P96 (Input)/EXCL (Input) P95/AS/IOS/CS1 AS (Output)/IOS (Output) P94/HWR/IOW HWR (Output) P93/RD/IOR RD (Output) P92/IRQ0 P92 (I/O)/IRQ0 (Input) P91/IRQ1 P91 (I/O)/IRQ1 (Input) P90/LWR/IRQ2/ADTRG/ECS2 P90 (I/O)/LWR (Output)/IRQ2 (Input)/ADTRG (Input) Pin functions in modes 2 and 3 (EXPE = 0) P97 (I/O)/SDA0 (I/O) P96 (Input)/ø (Output)/EXCL (Input) P95 (I/O)/CS1 (Input) P94 (I/O)/IOW (Input) P93 (I/O)/IOR (Input) P92 (I/O)/IRQ0 (Input) P91 (I/O)/IRQ1 (Input) P90 (I/O)/IRQ2 (Input)/ADTRG (Input)/ECS2 (Input) Figure 8.17 Port 9 Pin Functions 234 8.10.2 Register Configuration Table 8.18 summarizes the port 9 registers. Table 8.18 Port 9 Registers Name Abbreviation R/W Initial Value Address*1 Port 9 data direction register P9DDR W H'40/H'00* 2 H'FFC0 Port 9 data register P9DR R/W H'00 H'FFC1 Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode. Port 9 Data Direction Register (P9DDR) Bit 7 6 5 4 3 2 1 0 P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Mode 1 Initial value 0 1 0 0 0 0 0 0 Read/Write W W W W W W W W Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Modes 2 and 3 P9DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 9. P9DDR cannot be read; if it is, an undefined value will be returned. P9DDR is initialized to H'40 (mode 1) or H'00 (modes 2 and 3) by a reset and in hardware standby mode. It retains its prior state in software standby mode. • Modes 1, 2, and 3 (EXPE = 1) Pin P97 functions as a bus control input (WAIT), the IIC0 I/O pin (SDA0), or an I/O port, according to the wait mode setting. When P97 functions as an I/O port, it becomes an output port when P97DDR is set to 1, and an input port when P97DDR is cleared to 0. Pin P96 functions as the ø output pin when P96DDR is set to 1, and as the subclock input (EXCL) or an input port when P96DDR is cleared to 0. Pins P95 to P93 automatically become bus control outputs (AS/IOS, HWR, RD), regardless of the input/output direction indicated by P95DDR to P93DDR. Pins P92 and P91 become output ports when P92DDR and P91DDR are set to 1, and input ports when P92DDR and P91DDR are cleared to 0. 235 When the ABW bit in WSCR is cleared to 0, pin P90 becomes a bus control output (LWR), regardless of the input/output direction indicated by P90DDR. When the ABW bit is 1, pin P90 becomes an output port if P90DDR is set to 1, and an input port if P90DDR is cleared to 0. • Modes 2 and 3 (EXPE = 0) When the corresponding P9DDR bits are set to 1, pin P96 functions as the ø output pin and pins P97 and P95 to P90 become output ports. When P9DDR bits are cleared to 0, the corresponding pins become input ports. Port 9 Data Register (P9DR) Bit 7 6 5 4 3 2 1 0 P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR Initial value 0 —* 0 0 0 0 0 0 Read/Write R/W R R/W R/W R/W R/W R/W R/W Note: * Determined by the state of pin P96. P9DR is an 8-bit readable/writable register that stores output data for the port 9 pins (P97 to P90). With the exception of P96, if a port 9 read is performed while P9DDR bits are set to 1, the P9DR values are read directly, regardless of the actual pin states. If a port 9 read is performed while P9DDR bits are cleared to 0, the pin states are read. P9DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 8.10.3 Pin Functions Port 9 pins also function as external interrupt input pins (IRQ0 to IRQ2), the A/D converter trigger input pin (ADTRG), host interface (XBS) input pins (ECS2, CS1, IOW, IOR), the IIC0 I/O pin (SDA0), the subclock input pin (EXCL), bus control signal I/O pins (AS/IOS, RD, HWR, LWR, WAIT), and the system clock (ø) output pin. The pin functions differ between the mode 1, 2, and 3 (EXPE = 1) expanded modes and the mode 2 and 3 (EXPE = 0) single-chip modes. The port 9 pin functions are shown in table 8.19. 236 Table 8.19 Port 9 Pin Functions Pin Selection Method and Pin Functions P97/WAIT/SDA0 The pin function is switched as shown below according to the combination of operating mode, bit WMS1 in WSCR, bit ICE in ICCR of IIC0, and bit P97DDR. Operating mode Modes 1, 2, 3 (EXPE = 1) WMS1 0 ICE P97DDR Pin function Modes 2, 3 (EXPE = 0) 1 0 1 — — 0 1 0 1 — — 0 1 — P97 input pin P97 output pin SDA0 I/O pin WAIT input pin P97 input pin P97 output pin SDA0 I/O pin When this pin is set as the P97 output pin, it is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and has direct bus drive capability. P96/ø/EXCL The pin function is switched as shown below according to the combination of bit EXCLE in LPWRCR and bit P96DDR. P96DDR 0 EXCLE Pin function 1 0 1 0 P96 input pin EXCL input pin ø output pin When this pin is used as the EXCL input pin, P96DDR should be cleared to 0. P95/AS/IOS/CS1 The pin function is switched as shown below according to the combination of operating mode, bit IOSE in SYSCR, bit HI12E in SYSCR2, and bit P95DDR. Operating mode Modes 1, 2, 3 (EXPE = 1) HI12E — P95DDR — IOSE Pin function Modes 2, 3 (EXPE = 0) 0 1 0 1 — 0 1 — — — AS output pin IOS output pin P95 input pin P95 output pin CS1 input pin 237 Pin Selection Method and Pin Functions P94/HWR/IOW The pin function is switched as shown below according to the combination of operating mode, bit HI12E in SYSCR2, and bit P94DDR. Operating mode — P94DDR — 0 1 — HWR output pin P94 input pin P94 output pin IOW input pin 0 1 The pin function is switched as shown below according to the combination of operating mode, bit HI12E in SYSCR2, and bit P93DDR. Operating mode Modes 1, 2, 3 (EXPE = 1) Modes 2, 3 (EXPE = 0) HI12E — P93DDR — 0 1 — RD output pin P93 input pin P93 output pin IOR input pin Pin function P92/IRQ0 Modes 2, 3 (EXPE = 0) HI12E Pin function P93/RD/IOR Modes 1, 2, 3 (EXPE = 1) P92DDR Pin function 0 1 0 1 P92 input pin P92 output pin IRQ0 input pin When bit IRQ0E in IER is set to 1, this pin is used as the IRQ0 input pin. P91/IRQ1 P91DDR Pin function 0 1 P91 input pin P91 output pin IRQ1 input pin When bit IRQ1E in IER is set to 1, this pin is used as the IRQ1 input pin. 238 Pin Selection Method and Pin Functions P90/LWR/IRQ2/ ADTRG/ECS2 The pin function is switched as shown below according to the combination of operating mode, bit ABW in WSCR, bits HI12E and CS2E in SYSCR2, bit FGA20E in HICR, and bit P90DDR. Operating mode ABW Modes 1, 2, 3 (EXPE = 1) 0 Modes 2, 3 (EXPE = 0) 1 — HI12E — FGA20E — 1 CS2E — 1 P90DDR Pin function — 0 Any one 0 1 0 1 1 — LWR P90 P90 P90 P90 ECS2 output pin input pin output pin input pin output pin input pin IRQ2 input pin, ADTRG input pin When the IRQ2E bit in IER is set to 1 in mode 1, 2, or 3 (EXPE = 1) with the ABW bit in WSCR set to 1, or in mode 2 and 3 (EXPE = 0), this pin is used as the IRQ2 input pin. When TRGS1 and TRGS0 in ADCR of the A/D converter are both set to 1, this pin is used as the ADTRG input pin. 239 8.11 Port A 8.11.1 Overview Port A is an 8-bit I/O port. Port A pins also function as keyboard buffer controller I/O pins (PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD), key-sense interrupt input pins (KIN15 to KIN8), expansion A/D converter input pins (CIN15 to CIN8), and address output pins (A23 to A16). Port A pin functions are the same in all operating modes. Figure 8.18 shows the port A pin configuration. Port A Port A pins Pin functions in modes 1 and 2 (EXPE = 0) and mode 3 PA7/A23/KIN15/CIN15/PS2CD PA7 (I/O)/KIN15 (Input)/CIN15 (Input)/PS2CD (I/O) PA6/A22/KIN14/CIN14/PS2CC PA6 (I/O)/KIN14 (Input)/CIN14 (Input)/PS2CC (I/O) PA5/A21/KIN13/CIN13/PS2BD PA5 (I/O)/KIN13 (Input)/CIN13 (Input)/PS2BD (I/O) PA4/A20/KIN12/CIN12/PS2BC PA4 (I/O)/KIN12 (Input)/CIN12 (Input)/PS2BC (I/O) PA3/A19/KIN11/CIN11/PS2AD PA3 (I/O)/KIN11 (Input)/CIN11 (Input)/PS2AD (I/O) PA2/A18/KIN10/CIN10/PS2AC PA2 (I/O)/KIN10 (Input)/CIN10 (Input)/PS2AC (I/O) PA1/A17/KIN9/CIN9 PA1 (I/O)/KIN9 (Input)/CIN9 (Input) PA0/A16/KIN8/CIN8 PA0 (I/O)/KIN8 (Input)/CIN8 (Input) Pin functions in mode 2 (EXPE = 1) PA7 (I/O)/A23 (Output)/KIN15 (Input)/CIN15 (Input)/PS2CD (I/O) PA6 (I/O)/A22 (Output)/KIN14 (Input)/CIN14 (Input)/PS2CC (I/O) PA5 (I/O)/A21 (Output)/KIN13 (Input)/CIN13 (Input)/PS2BD (I/O) PA4 (I/O)/A20 (Output)/KIN12 (Input)/CIN12 (Input)/PS2BC (I/O) PA3 (I/O)/A19 (Output)/KIN11 (Input)/CIN11 (Input)/PS2AD (I/O) PA2 (I/O)/A18 (Output)/KIN10 (Input)/CIN10 (Input)/PS2AC (I/O) PA1 (I/O)/A17 (Output)/KIN9 (Input)/CIN9 (Input) PA0 (I/O)/A16 (Output)/KIN8 (Input)/CIN8 (Input) Figure 8.18 Port A Pin Functions 240 8.11.2 Register Configuration Table 8.20 summarizes the port A registers. Table 8.20 Port A Registers Name Abbreviation R/W Initial Value Address*1 Port A data direction register PADDR W H'00 H'FFAB* 2 Port A output data register PAODR R/W H'00 H'FFAA Port A input data register PAPIN R Undefined H'FFAB* 2 Notes: 1. Lower 16 bits of the address. 2. PADDR and PAPIN have the same address. Port A Data Direction Register (PADDR) Bit 7 6 5 4 3 2 1 0 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port A. Setting a PADDR bit to 1 makes the corresponding port A pin an output pin, while clearing the bit to 0 makes the pin an input pin. PADDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port A Output Data Register (PAODR) Bit 7 6 5 4 3 2 1 0 PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PAODR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to PA0). PAODR can always be read or written to, regardless of the contents of PADDR. PAODR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 241 Port A Input Data Register (PAPIN) Bit 7 PA7PIN 6 5 4 PA6PIN PA5PIN 3 2 PA4PIN PA3PIN 1 PA2PIN PA1PIN 0 PA0PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R R Note: * Determined by the state of pins PA7 to PA0. Reading PAPIN always returns the pin states. 8.11.3 Pin Functions Port A pins also function as keyboard buffer controller I/O pins (PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD), key-sense interrupt input pins (KIN15 to KIN8), expansion A/D converter input pins (CIN15 to CIN8), and address output pins (A23 to A16). The port A pin functions are shown in table 8.21. Table 8.21 Port A Pin Functions Pin Selection Method and Pin Functions PA7/A23/PS2CD/ KIN15/CIN15 The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCR2H of the keyboard buffer controller, the IOSE bit in SYSCR, and bit PA7DDR. Operating mode Modes 1, 2 (EXPE = 0), 3 KBIOE 0 Mode 2 (EXPE = 1) 1 0 1 PA7DDR 0 1 — 0 IOSE — — — — 0 1 — PA7 input pin A23 output pin PA7 output pin PS2CD output pin Pin function PA7 input pin PA7 PS2CD output output pin pin 1 — KIN15 input pin, CIN15 input pin, PS2CD input pin When the IICS bit in STCR is set to 1, this pin functions as a bus buffer. This pin can always be used as the PS2CD, KIN15, or CIN15 input pin. 242 Pin Selection Method and Pin Functions PA6/A22/PS2CC/ KIN14/CIN14 The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCR2H of the keyboard buffer controller, the IOSE bit in SYSCR, and bit PA6DDR. Operating mode Modes 1, 2 (EXPE = 0), 3 KBIOE 0 Mode 2 (EXPE = 1) 1 0 1 PA6DDR 0 1 — 0 IOSE — — — — 0 1 — PA6 input pin A22 output pin PA6 output pin PS2CC output pin Pin function PA6 input pin PA6 PS2CC output output pin pin 1 — KIN14 input pin, CIN14 input pin, PS2CC input pin When the IICS bit in STCR is set to 1, this pin functions as a bus buffer. This pin can always be used as the PS2CC, KIN14, or CIN14 input pin. PA5/A21/PS2BD/ KIN13/CIN13 The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCR1H of the keyboard buffer controller, the IOSE bit in SYSCR, and bit PA5DDR. Operating mode Modes 1, 2 (EXPE = 0), 3 KBIOE 0 Mode 2 (EXPE = 1) 1 0 1 PA5DDR 0 1 — 0 IOSE — — — — 0 1 — PA5 input pin A21 output pin PA5 output pin PS2BD output pin Pin function PA5 input pin PA5 PS2BD output output pin pin 1 — KIN13 input pin, CIN13 input pin, PS2BD input pin When the IICS bit in STCR is set to 1, this pin functions as a bus buffer. This pin can always be used as the PS2BD, KIN13, or CIN13 input pin. 243 Pin Selection Method and Pin Functions PA4/A20/PS2BC/ KIN12/CIN12 The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCR1H of the keyboard buffer controller, the IOSE bit in SYSCR, and bit PA4DDR. Operating mode Modes 1, 2 (EXPE = 0), 3 KBIOE 0 Mode 2 (EXPE = 1) 1 0 1 PA4DDR 0 1 — 0 IOSE — — — — 0 1 — PA4 input pin A20 output pin PA4 output pin PS2BC output pin Pin function PA4 input pin PA4 PS2BC output output pin pin 1 — KIN12 input pin, CIN12 input pin, PS2BC input pin When the IICS bit in STCR is set to 1, this pin functions as a bus buffer. This pin can always be used as the PS2BC, KIN12, or CIN12 input pin. PA3/A19/PS2AD/ KIN11/CIN11 The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCR0H of the keyboard buffer controller, the IOSE bit in SYSCR, and bit PA3DDR. Operating mode Modes 1, 2 (EXPE = 0), 3 KBIOE 0 Mode 2 (EXPE = 1) 1 0 1 PA3DDR 0 1 — 0 IOSE — — — — 0 1 — PA3 input pin A19 output pin PA3 output pin PS2AD output pin Pin function PA3 input pin PA3 PS2AD output output pin pin 1 — KIN11 input pin, CIN11 input pin, PS2AD input pin This pin can always be used as the PS2AD, KIN11, or CIN11 input pin. 244 Pin Selection Method and Pin Functions PA2/A18/PS2AC/ KIN10/CIN10 The pin function is switched as shown below according to the combination of operating mode, the KBIOE bit in KBCR0H of the keyboard buffer controller, the IOSE bit in SYSCR, and bit PA2DDR. Operating mode Modes 1, 2 (EXPE = 0), 3 KBIOE 0 Mode 2 (EXPE = 1) 1 0 1 PA2DDR 0 1 — 0 IOSE — — — — 0 1 — PA2 input pin A18 output pin PA2 output pin PS2AC output pin Pin function PA2 input pin PA2 PS2AC output output pin pin 1 — KIN10 input pin, CIN10 input pin, PS2AC input pin This pin can always be used as the PS2AC, KIN10, or CIN10 input pin. PA1/A17/KIN9/ CIN9 The pin function is switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR and bit PA1DDR. Operating mode Modes 1, 2 (EXPE = 0), 3 Mode 2 (EXPE = 1) PA1DDR 0 1 0 IOSE — — — 0 1 PA1 input pin PA1 output pin PA1 input pin A17 output pin PA1 output pin Pin function 1 KIN9 input pin, CIN9 input pin This pin can always be used as the KIN9 or CIN9 input pin. PA0/A16/KIN8/ CIN8 The pin function is switched as shown below according to the combination of operationg mode, the IOSE bit in SYSCR and bit PA0DDR. Operating mode Modes 1, 2 (EXPE = 0), 3 Mode 2 (EXPE = 1) PA0DDR 0 1 0 IOSE — — — 0 1 PA0 input pin PA0 output pin PA0 input pin A16 output pin PA0 output pin Pin function 1 KIN8 input pin, CIN8 input pin This pin can always be used as the KIN8 or CIN8 input pin. 245 8.11.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis. When a PADDR bit is cleared to 0, setting the corresponding PAODR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up for pins PA7 to PA4 is always off when IICS is set to 1. When the keyboard buffer control pin function is selected for pins PA7 to PA2, the MOS input pull-up is always off. The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.22 summarizes the MOS input pull-up states. Table 8.22 MOS Input Pull-Up States (Port A) Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1, 2, 3 Off Off On/Off On/Off Legend: Off: MOS input pull-up is always off. On/Off: On when PADDR = 0 and PAODR = 1; otherwise off. 246 8.12 Port B 8.12.1 Overview Port B is an 8-bit I/O port. Port B pins also have host interface (XBS) input/output pins (CS3, CS4, HIRQ3, HIRQ4), host interface (LPC) input/output pins (LSCI, LSMI), wakeup event interrupt input pins (WUE7 to WUE0), and a data bus input/output function (as D7 to D0). The pin functions depend on the operating mode. Figure 8.19 shows the port B pin configuration. Port B Port B pins Modes 1, 2, and 3 (EXPE = 1) when ABW = 0 PB7/D7/WUE7 D7 (I/O) PB6/D6/WUE6 D6 (I/O) PB5/D5/WUE5 D5 (I/O) PB4/D4/WUE4 D4 (I/O) PB3/D3/WUE3/CS4 D3 (I/O) PB2/D2/WUE2/CS3 D2 (I/O) PB1/D1/WUE1/HIRQ4/LSCI D1 (I/O) PB0/D0/WUE0/HIRQ3/LSMI D0 (I/O) Modes 1, 2, and 3 (EXPE = 1) when ABW = 1, and modes 1, 2, and 3 (EXPE = 0) PB7 (I/O)/WUE7 (Input) PB6 (I/O)/WUE6 (Input) PB5 (I/O)/WUE5 (Input) PB4 (I/O)/WUE4 (Input) PB3 (I/O)/WUE3 (Input)/CS4 (Input) PB2 (I/O)/WUE2 (Input)/CS3 (Input) PB1 (I/O)/WUE1 (Input)/HIRQ4 (Output)/LSCI (I/O) PB0 (I/O)/WUE0 (Input)/HIRQ3 (Output)/LSMI (I/O) Figure 8.19 Port B Pin Functions 247 8.12.2 Register Configuration Table 8.23 summarizes the port B registers. Table 8.23 Port B Registers Name Abbreviation R/W Initial Value Address*1 Port B data direction register PBDDR W H'00 H'FFBE* 2 Port B output data register PBODR R/W H'00 H'FFBC Port B input data register PBPIN R Undefined H'FFBD* 3 Notes: 1. Lower 16 bits of the address. 2. PBDDR has the same address as P7PIN. 3. PBPIN has the same address as P8DDR. Port B Data Direction Register (PBDDR) Bit 7 6 5 4 3 2 1 0 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR has the same address as P7PIN, and if read, the port 7 pin states will be returned. Setting a PBDDR bit to 1 makes the corresponding port B pin an output pin, while clearing the bit to 0 makes the pin an input pin. PBDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. • Modes 1, 2, and 3 (EXPE = 1) When the ABW bit in WSCR is cleared to 0, port B pins automatically become data I/O pins (D7 to D0), regardless of the input/output direction indicated by PBDDR. When the ABW bit is 1, a port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an input port if the bit is cleared to 0. Data I/O pins go to the high-impedance state after a reset, and in hardware standby mode or software standby mode. • Modes 2 and 3 (EXPE = 0) A port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an input port if the bit is cleared to 0. 248 Port B Output Data Register (PBODR) Bit 7 6 5 4 3 2 1 0 PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PBODR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBODR can always be read or written to, regardless of the contents of PBDDR. PBODR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port B Input Data Register (PBPIN) Bit 7 PB7PIN 6 5 PB6PIN PB5PIN 4 3 PB4PIN PB3PIN 2 1 PB2PIN PB1PIN 0 PB0PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R R Note: * Determined by the state of pins PB7 to PB0. Reading PBPIN always returns the pin states. PBPIN has the same address as P8DDR. If a write is performed, data will be written to P8DDR and the port 8 settings will change. 249 8.12.3 Pin Functions Port B pins also function as host interface (XBS) I/O pins (CS3, CS4, HIRQ3, HIRQ4), host interface (LPC) I/O pins (LSCI, LSMI), wakeup event interrupt input pins (WUE7 to WUE0), and data bus I/O pins (D7 to D0). The port B pin functions are shown in table 8.24. Table 8.24 Port B Pin Functions Pin Selection Method and Pin Functions PB7/D7/WUE7 The pin function is switched as shown below according to the combination of the operating mode, bit PB7DDR, and bit ABW in WSCR. Operating mode Modes 1, 2, 3 (EXPE = 1) Modes 2, 3 (EXPE = 0) ABW 0 PB7DDR — 0 1 0 1 D7 I/O pin PB7 input pin PB7 output pin PB7 input pin PB7 output pin Pin function 1 — WUE7 input pin Except when used as a data bus pin, this pin can always be used as the WUE7 input pin. PB6/D6/WUE6 The pin function is switched as shown below according to the combination of the operating mode, bit PB6DDR, and bit ABW in WSCR. Operating mode Modes 1, 2, 3 (EXPE = 1) Modes 2, 3 (EXPE = 0) ABW 0 PB6DDR — 0 1 0 1 D6 I/O pin PB6 input pin PB6 output pin PB6 input pin PB6 output pin Pin function 1 — WUE6 input pin Except when used as a data bus pin, this pin can always be used as the WUE6 input pin. 250 Pin Selection Method and Pin Functions PB5/D5/WUE5 The pin function is switched as shown below according to the combination of the operating mode, bit PB5DDR, and bit ABW in WSCR. Operating mode Modes 1, 2, 3 (EXPE = 1) Modes 2, 3 (EXPE = 0) ABW 0 PB5DDR — 0 1 0 1 D5 I/O pin PB5 input pin PB5 output pin PB5 input pin PB5 output pin Pin function 1 — WUE5 input pin Except when used as a data bus pin, this pin can always be used as the WUE5 input pin. PB4/D4/WUE4 The pin function is switched as shown below according to the combination of the operating mode, bit PB4DDR, and bit ABW in WSCR. Operating mode Modes 1, 2, 3 (EXPE = 1) Modes 2, 3 (EXPE = 0) ABW 0 PB4DDR — 0 1 0 1 D4 I/O pin PB4 input pin PB4 output pin PB4 input pin PB4 output pin Pin function 1 — WUE4 input pin Except when used as a data bus pin, this pin can always be used as the WUE4 input pin. 251 Pin Selection Method and Pin Functions PB3/D3/WUE3/ CS4 The pin function is switched as shown below according to the combination of the operating mode, bits HI12E and CS4E in SYSCR2, bit ABW in WSCR, and bit PB3DDR. Operating mode Modes 1, 2, 3 (EXPE = 1) HI12E — CS4E — ABW 0 PB3DDR — Pin function D3 I/O pin Modes 2, 3 (EXPE = 0) Either cleared to 0 1 1 1 0 — 1 0 — 1 — PB3 PB3 PB3 PB3 CS4 input pin output pin input pin output pin input pin WUE3 input pin Except when used as a data bus pin, this pin can always be used as the WUE3 input pin. The CS4 input pin can only be used in mode 2 or 3 (EXPE = 0). PB2/D2/WUE2/ CS3 The pin function is switched as shown below according to the combination of the operating mode, bits HI12E and CS3E in SYSCR2, bit ABW in WSCR, and bit PB2DDR. Operating mode Modes 1, 2, 3 (EXPE = 1) HI12E — CS3E — ABW 0 PB2DDR — Pin function D2 I/O pin Modes 2, 3 (EXPE = 0) Either cleared to 0 1 1 0 — 1 0 — 1 — PB2 PB2 PB2 PB2 CS3 input pin output pin input pin output pin input pin WUE2 input pin Except when used as a data bus pin, this pin can always be used as the WUE2 input pin. The CS3 input pin can only be used in mode 2 or 3 (EXPE = 0). 252 1 Pin Selection Method and Pin Functions PB1/D1/WUE1/ HIRQ4/LSCI The pin function is switched as shown below according to the combination of the operating mode, bits HI12E and CS4E in SYSCR2, bit ABW in WSCR, and bit PB1DDR. Note: * When bit LSCIE is set to 1 in HICR0, bits HI12E and PB1DDR should be cleared to 0. Operating mode Modes 1, 2, 3 (EXPE = 1) LSCIE — HI12E — CS4E — Modes 2, 3 (EXPE = 0) 0 Either cleared to 0 — 1 —* 1 — — — ABW 0 PB1DDR — 0 1 0 1 1 —* D1 I/O pin PB1 input pin PB1 output pin PB1 input pin PB1 output pin HIRQ4 output pin LSCI output pin Pin function 1 1 LSCI input pin WUE1 input pin Except when used as a data bus pin, this pin can always be used as the WUE1 input pin. The HIRQ4 output pin and LSCI I/O pin can only be used in mode 2 or 3 (EXPE = 0). 253 Pin Selection Method and Pin Functions PB0/D0/WUE0/ HIRQ3/LSMI The pin function is switched as shown below according to the combination of the operating mode, bits HI12E and CS3E in SYSCR2, bit ABW in WSCR, and bit PB0DDR. Operating mode Modes 1, 2, 3 (EXPE = 1) LSMIE — HI12E — CS3E — Modes 2, 3 (EXPE = 0) 0 Either cleared to 0 — 1 —* 1 —* — — ABW 0 PB0DDR — 0 1 0 1 1 —* D0 I/O pin PB0 input pin PB0 output pin PB0 input pin PB0 output pin HIRQ3 output pin LSMI output pin Pin function 1 1 LSMI input pin WUE0 input pin Except when used as a data bus pin, this pin can always be used as the WUE0 input pin. The HIRQ3 output pin and LSMI I/O pin can only be used in mode 2 or 3 (EXPE = 0). 254 8.12.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 1, 2, and 3 (EXPE = 1) with the ABW bit in WSCR set to 1, and in modes 2 and 3 (EXPE = 0), and can be specified as on or off on a bit-by-bit basis. When a PBDDR bit is cleared to 0, setting the corresponding PBODR bit to 1 turns on the MOS input pull-up for that pin. When a pin is designated as an on-chip supporting module output pin, the MOS input pull-up is always off. The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.25 summarizes the MOS input pull-up states. Table 8.25 MOS Input Pull-Up States (Port B) Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations 1, 2, 3 (EXPE = 1) with ABW in WSCR = 0 Off Off Off Off 1, 2, 3 (EXPE = 1) with ABW in WSCR = 1, and 2, 3 (EXPE = 0) Off Off On/Off On/Off Legend: Off: MOS input pull-up is always off. On/Off: On when PBDDR = 0 and PBODR = 1; otherwise off. 8.13 Additional Overview for H8S/2169 The H8S/2169 has fifteen I/O ports (ports 1 to 6, 8, 9, A, B, C, D, E, F, and G), and one input-only port (port 7). Table 8.26 is a summary of the additional port functions. As the functions of ports 1 to 9, A, and B are the same on the H8S/2149, table 8.1 provides a summary. Each extra port includes a data direction register (DDR) that controls input/output, and data registers (ODR) for storing output data. Ports C, D, E, F, and G have a built-in MOS input pull-up function. On ports C, D, E, F, and G, whether the MOS input pull-up is on or off is controlled by the corresponding DDR and ODR. Ports C, D, E, F, and G can drive a single-TTL load and 30-pF-capacitive load. All I/O port pins are capable of driving a Darlington transistor when they are in output mode. 255 Input and output on ports E, F, and G are powered by VCCB, which is independent of the V CC power supply. So, when the VCCB voltage is 5 V, the pins on ports E, F, and G can be 5-V tolerant. Table 8.26 H8S/2169 Additional Port Functions Expanded Modes Single-Chip Mode Port Description Pins Mode 2, Mode 3 Mode 1 (EXPE = 1) Mode 2, Mode 3 (EXPE = 0) Port C • • • • • • • • • • PC7 to PC0 I/O port I/O port I/O port PD7 to PD0 I/O port I/O port I/O port PE7 to PE0 I/O port I/O port I/O port PF7 to PF0 I/O port I/O port I/O port PG7 to PG0 I/O port I/O port I/O port Port D Port E Port F Port G 8-bit I/O port Built-in MOS input pull-ups 8-bit I/O port Built-in MOS input pull-ups 8-bit I/O port Built-in MOS input pull-ups 8-bit I/O port Built-in MOS input pull-ups 8-bit I/O port Built-in MOS input pull-ups 8.14 Ports C, D 8.14.1 Overview Port C and port D are two sets of 8-bit I/O ports. The pin functions are the same in all operating modes. Figure 8.20 shows the pin configuration for ports C and D. 256 Port C pins Port D pins PC7 (I/O) PD7 (I/O) PC6 (I/O) PD6 (I/O) PC5 (I/O) PD5 (I/O) PC4 (I/O) Port C Port D PD4 (I/O) PC3 (I/O) PD3 (I/O) PC2 (I/O) PD2 (I/O) PC1 (I/O) PD1 (I/O) PC0 (I/O) PD0 (I/O) Figure 8.20 Pin Functions for Ports C and D 8.14.2 Register Configuration Table 8.27 is a summary of the port C and port D registers. Table 8.27 Port C and port D Registers Name Abbreviation R/W Initial Value Address* 1 Port C data direction register PCDDR W H'00 H'FE4E*2 Port C output data register PCODR R/W H'00 H'FE4C Port C input data register PCPIN R Undefined H'FE4E*2 Port C Nch-OD control register PCNOCR R/W H'00 H'FE1C Port D data direction register PDDDR W H'00 H'FE4F*3 Port D output data register PDODR R/W H'00 H'FE4D Port D input data register PDPIN R Undefined H'FE4F* 3 Port D Nch-OD control register PDNOCR R/W H'00 H'FE1D Notes: 1. Lower 16 bits of the address. 2. PCDDR has the same address as PCPIN. 3. PDDDR has the same address as PDPIN. 257 Port C and port D Data Direction Registers (PCDDR, PDDDR) Bit 7 6 5 4 3 2 1 0 PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Bit 7 6 5 4 3 2 1 0 PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PCDDR and PDDDR are 8-bit write-only registers, the individual bits of which select input or output for the pins of port C and port D. PCDDR and PDDDR are at the same addresses as PCPIN and PDPIN, respectively, and if read, will return the port C and port D pin states. Setting a PCDDR or PDDDR bit to 1 makes the corresponding pin on port C or port D an output pin. Clearing the bit to 0 makes the pin an input pin. PCDDR and PDDDR are initialized to H'00 by a reset and in hardware standby mode. They retain their prior states in software standby mode. Port C and port D Output Data Registers (PCODR, PDODR) Bit 7 6 5 4 3 2 1 0 PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit PD7ODR PD6ODR PD5ODR PD4ODR PD3ODR PD2ODR PD1ODR PD0ODR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PCODR and PDODR are 8-bit read/write registers that store output data for the pins on ports C and D (PC7 to PC0 and PD7 to PD0). PCODR and PDODR can always be read from or written to, regardless of the PCDDR and PDDDR settings. PCODR and PDODR are initialized to H'00 by a reset and in hardware standby mode. They retain their prior states in software standby mode. 258 Port C and port D Input Data Registers (PCPIN, PDPIN) Bit 7 6 5 4 3 2 1 0 PC7PIN PC6PIN PC5PIN PC4PIN PC3PIN PC2PIN PC1PIN PC0PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R R Note: * Determined by the state of pins PC7 to PC0. Bit 7 6 5 4 3 2 1 0 PD7PIN PD6PIN PD5PIN PD4PIN PD3PIN PD2PIN PD1PIN PD0PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R R Note: * Determined by the state of pins PD7 to PD0. Reading PCPIN and PDPIN always returns the pin states. PCPIN and PDPIN are at the same addresses as PCDDR and PDDDR, respectively. Writing is to PCDDR or PDDDR and the port C or port D settings will change unless the given byte represents the current setting. Port C and port D Nch-OD Control Register (PCNOCR, PDNOCR) Bit 7 6 5 4 3 2 1 0 PC7NOC PC6NOC PC5NOC PC4NOC PC3NOC PC2NOC PC1NOC PC0NOC Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit PD7NOC PD6NOC PD5NOC PD4NOC PD3NOC PD2NOC PD1NOC PD0NOC Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 259 PCNOCR and PDNOCR are 8-bit read/write registers, the individual bits of which specify the output driver type for pins on ports C and D which are configured as outputs. Setting a PCNOCR or PDNOCR bit to 1 disables the P-channel driver for the corresponding pin on port C or port D. Clearing the bit to 0 enables the P-channel driver for the pin. Although the Pchannel drivers are always connected, the output driver type will be CMOS when the bit is cleared to 0 and N-channel open-drain when it is set to 1. PCNOCR and PDNOCR are initialized to H'00 by a reset and in hardware standby mode. They retain their prior states in software standby mode. DDR 0 NOCR — ODR 0 1 0 1 1 0 1 0 1 ON OFF N-ch. driver OFF ON OFF P-ch. driver OFF OFF ON MOS Input Pul-Up 8.14.3 OFF ON OFF OFF Pin Functions The port C and port D pins have only one special function. 8.14.4 MOS Input Pull-Up Function Port C and port D have a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be switched on or off on a bit-by-bit basis. When a PCDDR or PDDDR bit is cleared to 0, setting the corresponding PCODR or PDODR bit to 1 will turn on the MOS input pull-up for that pin. The MOS input pull-up function is off after a reset and in hardware standby mode. The prior state is retained when in software standby mode. Table 8.28 is a summary of the MOS input pull-up states. 260 Table 8.28 MOS Input Pull-Up States (Port C and port D) Mode Reset Hardware Standby Mode Software Standby Mode Other Operations 1, 2, 3 Off Off On/Off On/Off Legend: Off: MOS input pull-up is always off. On/Off: On when PCDDR = 0 and PCODR = 1 (PDDDR = 0 and PDODR = 1); otherwise off. 8.15 Ports E, F 8.15.1 Overview Port E and port F are two sets of 8-bit I/O ports. The pins of ports E and F have the same functions in all operating modes. Figure 8.21 shows the pin configuration of port E and port F. Port E Port E pins Port F pins PE7 (I/O) PF7 (I/O) PE6 (I/O) PF6 (I/O) PE5 (I/O) PF5 (I/O) PE4 (I/O) Port F PF4 (I/O) PE3 (I/O) PF3 (I/O) PE2 (I/O) PF2 (I/O) PE1 (I/O) PF1 (I/O) PE0 (I/O) PF0 (I/O) Figure 8.21 Pin Functions for Ports E and F 261 8.15.2 Register Configuration Table 8.29 is a summary of the port E and port F registers. Table 8.29 Port E and port F Registers Name Abbreviation R/W Initial Value Address* 1 Port E data direction register PEDDR W H'00 H'FE4A* 2 Port E output data register PEODR R/W H'00 H'FE48 Port E input data register PEPIN R Undefined H'FE4A* 2 Port E Nch-OD control register PENOCR R/W H'00 H'FE18 Port F data direction register PFDDR W H'00 H'FE4B* 3 Port F output data register PFODR R/W H'00 H'FE49 Port F input data register PFPIN R Undefined H'FE4B* 3 Port F Nch-OD control register PFNOCR R/W H'00 H'FE19 Notes: 1. Lower 16 bits of the address. 2. PEDDR has the same address as PEPIN. 3. PFDDR has the same address as PFPIN. Port E and port F Data Direction Registers (PEDDR, PFDDR) Bit 7 6 5 4 3 2 1 0 PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Bit 7 6 5 4 3 2 1 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PEDDR and PFDDR are 8-bit write-only registers, the individual bits of which select input or output for the pins of port E and port F. PEDDR and PFDDR are at the same addresses as PEPIN and PFPIN, respectively, and if read, will return the port E and port F pin states. Setting a PEDDR or PFDDR bit to 1 makes the corresponding pin on port E or port F an output pin, while clearing the bit to 0 makes the pin an input pin. PEDDR and PFDDR are initialized to H'00 by a reset and in hardware standby mode. They retain their prior states in software standby mode. 262 Port E and port F Output Data Registers (PEODR, PFODR) Bit 7 6 5 4 3 2 1 0 PE7ODR PE6ODR PE5ODR PE4ODR PE3ODR PE2ODR PE1ODR PE0ODR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit PF7ODR PF6ODR PF5ODR PF4ODR PF3ODR PF2ODR PF1ODR PF0ODR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PEODR and PFODR are 8-bit read/write registers that store output data for the pins on ports E and F (PE7 to PE0 and PF7 to PF0). PEODR and PFODR can always be read from or written to, regardless of the PEDDR and PFDDR settings. PEODR and PFODR are initialized to H'00 by a reset and in hardware standby mode. They retain their prior states in software standby mode. Port E and port F Input Data Registers (PEPIN, PFPIN) Bit 7 6 5 4 3 2 1 0 PE7PIN PE6PIN PE5PIN PE4PIN PE3PIN PE2PIN PE1PIN PE0PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R R Note: * Determined by the state of pins PE7 to PE0. Bit 7 6 5 4 3 2 1 0 PF7PIN PF6PIN PF5PIN PF4PIN PF3PIN PF2PIN PF1PIN PF0PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R R Note: * Determined by the state of pins PF7 to PF0. Reading PEPIN and PFPIN always returns the pin states. PEPIN and PFPIN are at the same addresses as PEDDR and PFDDR, respectively. Writing is to PEDDR or PFDDR and the port E or port F settings will change unless the given byte represents the current setting. 263 Port E and port F Nch-OD Control Registers (PENOCR, PFNOCR) Bit 7 6 5 4 3 2 1 0 PE7NOC PE6NOC PE5NOC PE4NOC PE3NOC PE2NOC PE1NOC PE0NOC Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit PF7NOC PF6NOC PF5NOC PF4NOC PF3NOC PF2NOC PF1NOC PF0NOC Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PENOCR and PFNOCR are 8-bit read/write registers, the individual bits of which specify the output driver type for pins on ports E and F which are configured as outputs. Setting a PENOCR or PFNOCR bit to 1 disables the P-channel driver for the corresponding pin on port E or port F. Clearing the bit to 0 enables the P-channel driver for the pin. Although the Pchannel drivers are always connected, the output driver type will be CMOS when the bit is cleared to 0 and N-channel open-drain when it is set to 1. PENOCR and PFNOCR are initialized to H'00 by a reset and in hardware standby mode. They retain their prior states in software standby mode. DDR 0 NOCR — ODR 0 1 0 1 1 0 1 0 1 ON OFF N-ch. driver OFF ON OFF P-ch. driver OFF OFF ON MOS Input Pul-Up 264 OFF ON OFF OFF 8.15.3 Pin Functions The port E and port F pins have only one special function. 8.15.4 MOS Input Pull-Up Function Port E and port F have a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be switched as on or off on a bit-by-bit basis. When a PEDDR or PFDDR bit is cleared to 0, setting the corresponding PEODR or PFODR bit to 1 will turn on the MOS input pull-up for that pin. The MOS input pull-up function is off after a reset and in hardware standby mode. The prior state is retained when in software standby mode. Table 8.30 is a summary of the MOS input pull-up states. Table 8.30 MOS Input Pull-Up States (Port E and port F) Mode Reset Hardware Standby Mode Software Standby Mode Other Operations 1, 2, 3 Off Off On/Off On/Off Legend: Off: MOS input pull-up is always off. On/Off: On when PEDDR = 0 and PEODR = 1 (PFDDR = 0 and PFODR = 1); otherwise off. 265 8.16 Port G 8.16.1 Overview Port G is an 8-bit I/O port. Port G pin functions are the same in all operating modes. Figure 8.22 shows the pin configuration of port G. Port C pins PG7 (I/O) PG6 (I/O) PG5 (I/O) Port G PG4 (I/O) PG3 (I/O) PG2 (I/O) PG1 (I/O) PG0 (I/O) Figure 8.22 Pin Functions for Port G 8.16.2 Register Configuration Table 8.31 is a summary of the port G registers. Table 8.31 Port G Registers Name Abbreviation R/W Initial Value Address* 1 Port G data direction register PGDDR W H'00 H'FE47* 2 Port G output data register PGODR R/W H'00 H'FE46 Port G input data register PGPIN R Undefined H'FE47* 3 Port G Nch-OD control register PGNOCR R/W H'00 H'FE16 Notes: 1. Lower 16 bits of the address. 2. PGDDR has the same address as PGPIN. 266 Port G Data Direction Register (PGDDR) Bit 7 6 5 4 3 2 1 0 PG7DDR PG6DDR PG5DDR PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PGDDR is an 8-bit write-only register, the individual bits of which select input or output for the pins of port G. PGDDR is at the same address as PGPIN, and if read, will return the port G pin states. Setting a PGDDR bit to 1 makes the corresponding pins on port G an output pin, while clearing the bit to 0 makes the pin an input pin. PGDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port G Output Data Register (PGODR) Bit 7 6 5 4 3 2 1 0 PG7ODR PG6ODR PG5ODR PG4ODR PG3ODR PG2ODR PG1ODR PG0ODR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PGODR is an 8-bit read/write register that stores output data for the pins on port G (PG7 to PG0). PGODR can always be read from or written to, regardless of the PGDDR settings. PGODR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port G Input Data Register (PGPIN) Bit 7 PG7PIN 6 5 PG6PIN PG5PIN 4 3 PG4PIN PG3PIN 2 1 PG2PIN PG1PIN 0 PG0PIN Initial value —* —* —* —* —* —* —* —* Read/Write R R R R R R R R Note: * Determined by the state of pins PG7 to PG0. Reading PGPIN always returns the pin states. PGPIN is at the same address as PGDDR. Writing is to PGDDR and the port G settings will change unless the given byte represents the current settings. 267 Port G Nch-OD Control Register (PGNOCR) Bit 7 6 5 4 3 2 1 0 PG7NOC PG6NOC PG5NOC PG4NOC PG3NOC PG2NOC PG1NOC PG0NOC Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PGNOCR is an 8-bit read/write register, the individual bits of which specify the output driver type for pins on port G which are configured as outputs. Setting a PENOCR or PFNOCR bit to 1 disables the P-channel driver for the corresponding pin on port G. Clearing the bit to 0 enables the P-channel driver for the pin. Although the P-channel drivers are always connected, the output driver type will look like CMOS when the bit is cleared to 0 and N-channel open-drain when it is set to 1. PGNOCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. DDR 0 NOCR — ODR 0 1 0 1 1 0 1 0 1 ON OFF N-ch. driver OFF ON OFF P-ch. driver OFF OFF ON MOS Input Pul-Up 8.16.3 OFF ON OFF OFF Pin Functions The port G pins have only one special function. 8.16.4 MOS Input Pull-Up Function Port G has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be switched on or off on a bit-by-bit basis. When a PGDDR bit is cleared to 0, setting the corresponding PGODR bit to 1 will turn on the MOS input pull-up for that pin. The MOS input pull-up function is off after a reset and in hardware standby mode. The prior state is retained when in software standby mode. Table 8.32 is a summary of the MOS input pull-up states. 268 Table 8.32 MOS Input Pull-Up States (Port G) Mode Reset Hardware Standby Mode Software Standby Mode Other Operations 1, 2, 3 Off Off On/Off On/Off Legend: Off: MOS input pull-up is always off. On/Off: On when PGDDR = 0 and PGODR = 1; otherwise off. 269 270 Section 9 8-Bit PWM Timers 9.1 Overview The H8S/2169 or H8/2149 has an on-chip pulse width modulation (PWM) timer module with sixteen outputs. Sixteen output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division. The PWM timer module has sixteen 8-bit PWM data registers (PWDRs), and an output pulse with a duty cycle of 0 to 100% can be obtained as specified by PWDR and the port data register (P1DR or P2DR). 9.1.1 Features The PWM timer module has the following features. • Operable at a maximum carrier frequency of 625 kHz using pulse division (at 10 MHz operation) • Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output) • Direct or inverted PWM output, and PWM output enable/disable control 271 9.1.2 Block Diagram Figure 9.1 shows a block diagram of the PWM timer module. PWDR0 Comparator 1 PWDR1 P12/PW2 Comparator 2 PWDR2 P13/PW3 Comparator 3 PWDR3 P14/PW4 Comparator 4 PWDR4 Comparator 5 PWDR5 Comparator 6 PWDR6 Comparator 7 PWDR7 Comparator 8 PWDR8 P15/PW5 P16/PW6 P17/PW7 P20/PW8 P21/PW9 P22/PW10 Comparator 9 PWDR9 Comparator 10 PWDR10 Comparator 11 PWDR11 P24/PW12 Comparator 12 PWDR12 P25/PW13 Comparator 13 PWDR13 P26/PW14 Comparator 14 PWDR14 P27/PW15 Comparator 15 PWDR15 TCNT Clock selection P23/PW11 PWDPRB PWDPRA PWOERB PWOERA P2DDR P1DDR P2DR P1DR Legend: PWSL: PWDR: PWDPRA: PWDPRB: PWOERA: PWOERB: PCSR: P1DDR: P2DDR: P1DR: P2DR: PWM register select PWM data register PWM data polarity register A PWM data polarity register B PWM output enable register A PWM output enable register B Peripheral clock select register Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register Module data bus ø/16 ø/8 ø/4 ø/2 ø Internal clock Figure 9.1 Block Diagram of PWM Timer Module 272 Bus interface Comparator 0 P11/PW1 Port/PWM output control P10/PW0 PWSL PCSR Internal data bus 9.1.3 Pin Configuration Table 9.1 shows the PWM output pin. Table 9.1 Pin Configuration Name Abbreviation I/O Function PWM output pin 0 to 15 PW0 to PW15 Output PWM timer pulse output 0 to 15 9.1.4 Register Configuration Table 9.2 lists the registers of the PWM timer module. Table 9.2 PWM Timer Module Registers Name Abbreviation R/W Initial Value Address* 1 PWM register select PWSL R/W H'20 H'FFD6 PWM data registers 0 to 15 PWDR0 to PWDR15 R/W H'00 H'FFD7 PWM data polarity register A PWDPRA R/W H'00 H'FFD5 PWM data polarity register B PWDPRB R/W H'00 H'FFD4 PWM output enable register A PWOERA R/W H'00 H'FFD3 PWM output enable register B PWOERB R/W H'00 H'FFD2 Port 1 data direction register P1DDR W H'00 H'FFB0 Port 2 data direction register P2DDR W H'00 H'FFB1 Port 1 data register P1DR R/W H'00 H'FFB2 Port 2 data register P2DR R/W H'00 H'FFB3 Peripheral clock select register PCSR R/W H'00 H'FF82* 2 Module stop control register MSTPCRH R/W H'3F H'FF86 MSTPCRL R/W H'FF H'FF87 Note: 1. Lower 16 bits of the address. 2. Some PWM Timer Module registers are assigned to the same addresses as other registers. In this case, registers selection is performed by the FLSHE bit in the serial timer control register (STCR). 273 9.2 Register Descriptions 9.2.1 PWM Register Select (PWSL) Bit 7 6 PWCKE PWCKS 5 4 3 2 1 0 — — RS3 RS2 RS1 RS0 Initial value 0 0 1 0 0 0 0 0 Read/Write R/W R/W — — R/W R/W R/W R/W PWSL is an 8-bit readable/writable register used to select the PWM timer input clock and the PWM data register. PWSL is initialized to H'20 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. Bits 7 and 6—PWM Clock Enable, PWM Clock Select (PWCKE, PWCKS): These bits, together with bits PWCKA and PWCKB in PCSR, select the internal clock input to TCNT in the PWM timer. PWSL PCSR Bit 7 Bit 6 Bit 2 Bit 1 PWCKE PWCKS PWCKB PWCKA Description 0 — — — Clock input is disabled 1 0 — — ø (system clock) is selected 1 0 0 ø/2 is selected 1 ø/4 is selected 0 ø/8 is selected 1 ø/16 is selected 1 (Initial value) The PWM resolution, PWM conversion period, and carrier frequency depend on the selected internal clock, and can be found from the following equations. Resolution (minimum pulse width) = 1/internal clock frequency PWM conversion period = resolution × 256 Carrier frequency = 16/PWM conversion period Thus, with a 10 MHz system clock (ø), the resolution, PWM conversion period, and carrier frequency are as shown followings. 274 Table 9.3 Resolution, PWM Conversion Period, and Carrier Frequency when ø = 10 MHz Internal Clock Frequency Resolution PWM Conversion Period Carrier Frequency ø 100 ns 25.6 µs 625 kHz ø/2 200 ns 51.2 µs 312.5 kHz ø/4 400 ns 102.4 µs 156.3 kHz ø/8 800 ns 204.8 µs 78.1 kHz ø/16 1600 ns 409.6 µs 39.1 kHz Bit 5—Reserved: This bit is always read as 1 and cannot be modified. Bit 4—Reserved: This bit is always read as 0 and cannot be modified. Bits 3 to 0—Register Select (RS3 to RS0): These bits select the PWM data register. Bit 3 Bit 2 Bit 1 Bit 0 RS3 RS2 RS1 RS0 Register Selection 0 0 0 0 PWDR0 selected 1 PWDR1 selected 0 PWDR2 selected 1 PWDR3 selected 0 PWDR4 selected 1 PWDR5 selected 0 PWDR6 selected 1 PWDR7 selected 0 PWDR8 selected 1 PWDR9 selected 0 PWDR10 selected 1 PWDR11 selected 0 PWDR12 selected 1 PWDR13 selected 0 PWDR14 selected 1 PWDR15 selected 1 1 0 1 1 0 0 1 1 0 1 275 9.2.2 PWM Data Registers (PWDR0 to PWDR15) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Each PWDR is an 8-bit readable/writable register that specifies the duty cycle of the basic pulse to be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper 4 bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The lower 4 bits specify how many extra pulses are to be added within the conversion period comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios within the conversion period. For 256/256 (100%) output, port output should be used. PWDR is initialized to H'00 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. 9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB) PWDPRA Bit 7 6 5 4 3 2 1 0 OS7 OS6 OS5 OS4 OS3 OS2 OS1 OS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PWDPRB Bit 7 6 5 4 3 2 1 0 OS15 OS14 OS13 OS12 OS11 OS10 OS9 OS8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Each PWDPR is an 8-bit readable/writable register that controls the polarity of the PWM output. Bits OS0 to OS15 correspond to outputs PW0 to PW15. PWDPR is initialized to H'00 by a reset and in hardware standby mode. 276 OS Description 0 PWM direct output (PWDR value corresponds to high width of output) 1 PWM inverted output (PWDR value corresponds to low width of output) 9.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) (Initial value) PWOERA Bit 7 6 5 4 3 2 1 0 OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 OE15 OE14 OE13 OE12 OE11 OE10 OE9 OE8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PWOERB Bit Each PWOER is an 8-bit readable/writable register that switches between PWM output and port output. Bits OE15 to OE0 correspond to outputs PW15 to PW0. To set a pin in the output state, a setting in the port direction register is also necessary. Bits P17DDR to P10DDR correspond to outputs PW7 to PW0, and bits P27DDR to P20DDR correspond to outputs PW15 to PW8. PWOER is initialized to H'00 by a reset and in hardware standby mode. DDR OE Description 0 0 Port input 1 Port input 0 Port output or PWM 256/256 output 1 PWM output (0 to 255/256 output) 1 (Initial value) 277 9.2.5 Peripheral Clock Select Register (PCSR) Bit 7 6 5 4 3 — — — — — 2 1 PWCKB PWCKA 0 — Initial value 0 0 0 0 0 0 0 0 Read/Write — — — — — R/W R/W — PCSR is an 8-bit readable/writable register that selects the PWM timer input clock. PCSR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 0. Bits 2 and 1—PWM Clock Select (PWCKB, PWCKA): Together with bits PWCKE and PWCKS in PWSL, these bits select the internal clock input to TCNT in the PWM timer. For details, see section 9.2.1, PWM Register Select (PWSL). Bit 0—Reserved: Do not set this bit to 1. 9.2.6 Port 1 Data Direction Register (P1DDR) Bit 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W P1DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for each pin of port 1 on a bit-by-bit basis. Port 1 pins are multiplexed with pins PW0 to PW7. The bit corresponding to a pin to be used for PWM output should be set to 1. For details on P1DDR, see section 8.2, Port 1. 278 9.2.7 Port 2 Data Direction Register (P2DDR) Bit 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W P2DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for each pin of port 2 on a bit-by-bit basis. Port 2 pins are multiplexed with pins PW8 to PW15. The bit corresponding to a pin to be used for PWM output should be set to 1. For details on P2DDR, see section 8.3, Port 2. 9.2.8 Port 1 Data Register (P1DR) Bit 7 6 5 4 3 2 1 0 P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P1DR is an 8-bit readable/writable register used to fix PWM output at 1 (when OS = 0) or 0 (when OS = 1). For details on P1DR, see section 8.2, Port 1. 9.2.9 Port 2 Data Register (P2DR) Bit 7 6 5 4 3 2 1 0 P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P2DR is an 8-bit readable/writable register used to fix PWM output at 1 (when OS = 0) or 0 (when OS = 1). For details on P2DR, see section 8.3, Port 2. 279 9.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. When the MSTP11 bit is set to 1, 8-bit PWM timer operation is halted and a transition is made to module stop mode. For details, see section 24.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 3—Module Stop (MSTP11): Specifies PWM module stop mode. MSTPCRH Bit 3 MSTP11 Description 0 PWM module stop mode is cleared 1 PWM module stop mode is set 280 (Initial value) 9.3 Operation 9.3.1 Correspondence between PWM Data Register Contents and Output Waveform The upper 4 bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16, as shown in table 9.4. Table 9.4 Duty Cycle of Basic Pulse Upper 4 Bits 0000 Basic Pulse Waveform (Internal) 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 281 The lower 4 bits of PWDR specify the position of pulses added to the 16 basic pulses, as shown in table 9.5. An additional pulse consists of a high period (when OS = 0) with a width equal to the resolution, added before the rising edge of a basic pulse. When the upper 4 bits of PWDR are 0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. Table 9.5 Position of Pulses Added to Basic Pulses Basic Pulse No. Lower 4 Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 Yes 0010 Yes Yes 0011 Yes Yes Yes Yes 0100 Yes Yes Yes 0101 Yes Yes Yes Yes Yes 0110 Yes Yes Yes Yes Yes Yes 0111 Yes Yes Yes Yes Yes Yes Yes Yes 1000 Yes Yes Yes Yes Yes Yes Yes 1001 Yes Yes Yes Yes Yes Yes Yes Yes Yes 1010 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1011 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1100 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1101 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1110 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1111 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No additional pulse Resolution width Additional pulse provided Additional pulse Figure 9.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = 1000) 282 Section 10 14-Bit PWM Timer 10.1 Overview The H8S/2169 or H8S/2149 has an on-chip 14-bit pulse-width modulator (PWM) with two output channels. Each channel can be connected to an external low-pass filter to operate as a 14-bit D/A converter. Both channels share the same counter (DACNT) and control register (DACR). 10.1.1 Features The features of the 14-bit PWM (D/A) are listed below. • The pulse is subdivided into multiple base cycles to reduce ripple. • Two resolution settings and two base cycle settings are available The resolution can be set equal to one or two system clock cycles. The base cycle can be set equal to T × 64 or T × 256, where T is the resolution. • Four operating rates The two resolution settings and two base cycle settings combine to give a selection of four operating rates. 283 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the PWM D/A module. Internal clock ø Internal data bus ø/2 Clock Clock selection Bus interface Basic cycle compare-match A PWX0 Fine-adjustment pulse addition A PWX1 Basic cycle compare-match B Fine-adjustment pulse addition B Comparator A DADRA Comparator B DADRB Control logic Basic cycle overflow DACNT DACR Module data bus Legend: DACR: DADRA: DADRB: DACNT: PWM D/A control register ( 6 bits) PWM D/A data register A (15 bits) PWM D/A data register B (15 bits) PWM D/A counter (14 bits) Figure 10.1 PWM D/A Block Diagram 10.1.3 Pin Configuration Table 10.1 lists the pins used by the PWM (D/A) module. Table 10.1 Input and Output Pins Name Abbreviation I/O Function PWM output pin 0 PWX0 Output PWM output, channel A PWM output pin 1 PWX1 Output PWM output, channel B 284 10.1.4 Register Configuration Table 10.2 lists the registers of the PWM (D/A) module. Table 10.2 Register Configuration Name Abbreviation R/W Initial value Address* 1 PWM (D/A) control register DACR R/W H'30 H'FFA0* 2 PWM (D/A) data register A high DADRAH R/W H'FF H'FFA0* 2 PWM (D/A) data register A low DADRAL R/W H'FF H'FFA1* 2 PWM (D/A) data register B high DADRBH R/W H'FF H'FFA6* 2 PWM (D/A) data register B low DADRBL R/W H'FF H'FFA7* 2 PWM (D/A) counter high DACNTH R/W H'00 H'FFA6* 2 PWM (D/A) counter low DACNTL R/W H'03 H'FFA7* 2 Module stop control register MSTPCRH R/W H'3F H'FF86 MSTPCRL R/W H'FF H'FF87 Notes: 1. Lower 16 bits of the address. 2. Some of the PWM registers are located in the same addresses as other registers, switching is made by setting IICE bit in serial/timer control register (STCR). The same addresses are shared by DADRAH and DACR, and by DADRB and DACNT. Switching is performed by the REGS bit in DACNT or DADRB. 10.2 Register Descriptions 10.2.1 PWM (D/A) Counter (DACNT) DACNTH DACNTL Bit (CPU) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BIT (Counter) 7 6 5 4 3 2 1 0 8 9 10 11 12 13 — — — REGS Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 1 — R/W DACNT is a 14-bit readable/writable up-counter that increments on an input clock pulse. The input clock is selected by the clock select bit (CKS) in DACR. The CPU can read and write the DACNT value, but since DACNT is a 16-bit register, data transfers between it and the CPU are performed using a temporary register (TEMP). See section 10.3, Bus Master Interface, for details. 285 DACNT functions as the time base for both PWM (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12-bit precision, it uses the lower 12 (counter) bits and ignores the upper two (counter) bits. DACNT is initialized to H'0003 by a reset, in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode, and by the PWME bit. Bit 1 of DACNTL (CPU) is not used, and is always read as 1. DACNTL Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS bit can be accessed regardless of whether DADRB or DACNT is selected. Bit 0 REGS Description 0 DADRA and DADRB can be accessed 1 DACR and DACNT can be accessed 10.2.2 (Initial value) D/A Data Registers A and B (DADRA and DADRB) DADRH DADRL Bit (CPU) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit (Data) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — DADRA Initial value DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 — 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DADRB DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS Initial value Read/Write 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 — 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W There are two 16-bit readable/writable D/A data registers: DADRA and DADRB. DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM D/A channel B. The CPU can read and write the PWM D/A data register values, but since DADRA and DADRB are 16-bit registers, data transfers between them and the CPU are performed using a temporary register (TEMP). See section 10.3, Bus Master Interface, for details. The least significant (CPU) bit of DADRA is not used and is always read as 1. DADR is initialized to H'FFFF by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. 286 Bits 15 to 2—PWM D/A Data 13 to 0 (DA13 to DA0): The digital value to be converted to an analog value is set in the upper 14 bits of the PWM (D/A) data register. In each base cycle, the DACNT value is continually compared with these upper 14 bits to determine the duty cycle of the output waveform, and to decide whether to output a fineadjustment pulse equal in width to the resolution. To enable this operation, the data register must be set within a range that depends on the carrier frequency select bit (CFS). If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA0 and DA1) cleared to 0 and writing the data to be converted in the upper 12 bits. The two lowest data bits correspond to the two highest counter (DACNT) bits. Bit 1—Carrier Frequency Select (CFS) Bit 1 CFS Description 0 Base cycle = resolution (T) × 64 DADR range = H'0401 to H'FFFD 1 Base cycle = resolution (T) × 256 DADR range = H'0103 to H'FFFF (Initial value) DADRA Bit 0—Reserved: This bit cannot be modified and is always read as 1. DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS bit can be accessed regardless of whether DADRB or DACNT is selected. Bit 0 REGS Description 0 DADRA and DADRB can be accessed 1 DACR and DACNT can be accessed 10.2.3 (Initial value) PWM (D/A) Control Register (DACR) 7 6 5 4 3 2 1 0 TEST PWME — — OEB OEA OS CKS Initial value 0 0 1 1 0 0 0 0 Read/Write R/W R/W — — R/W R/W R/W R/W Bit 287 DACR is an 8-bit readable/writable register that selects test mode, enables the PWM outputs, and selects the output phase and operating speed. DACR is initialized to H'30 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7—Test Mode (TEST): Selects test mode, which is used in testing the chip. Normally this bit should be cleared to 0. Bit 7 TEST Description 0 PWM (D/A) in user state: normal operation 1 PWM (D/A) in test state: correct conversion results unobtainable (Initial value) Bit 6—PWM Enable (PWME): Starts or stops the PWM (D/A) counter (DACNT). Bit 6 PWME Description 0 DACNT operates as a 14-bit up-counter 1 DACNT halts at H'0003 (Initial value) Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 1. Bit 3—Output Enable B (OEB): Enables or disables output on PWM (D/A) channel B. Bit 3 OEB Description 0 PWM (D/A) channel B output (at the PWX1 pin) is disabled 1 PWM (D/A) channel B output (at the PWX1 pin) is enabled (Initial value) Bit 2—Output Enable A (OEA): Enables or disables output on PWM (D/A) channel A. Bit 2 OEA Description 0 PWM (D/A) channel A output (at the PWX0 pin) is disabled 1 PWM (D/A) channel A output (at the PWX0 pin) is enabled 288 (Initial value) Bit 1—Output Select (OS): Selects the phase of the PWM (D/A) output. Bit 1 OS Description 0 Direct PWM output 1 Inverted PWM output (Initial value) Bit 0—Clock Select (CKS): Selects the PWM (D/A) resolution. If the system clock (ø) frequency is 10 MHz, resolutions of 100 ns and 200 ns can be selected. Bit 0 CKS Description 0 Operates at resolution (T) = system clock cycle time (tcyc ) 1 Operates at resolution (T) = system clock cycle time (tcyc ) × 2 10.2.4 (Initial value) Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. When the MSTP11 bit is set to 1, 14-bit PWM timer operation is halted and a transition is made to module stop mode. For details, see section 24.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 3—Module Stop (MSTP11): Specifies PWMX module stop mode. MSTPCRH Bit 3 MSTP11 Description 0 PWMX module stop mode is cleared 1 PWMX module stop mode is set (Initial value) 289 10.3 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip supporting modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written and read as follows (taking the example of the CPU interface). • Write When the upper byte is written, the upper-byte write data is stored in TEMP. Next, when the lower byte is written, the lower-byte write data and TEMP value are combined, and the combined 16-bit value is written in the register. • Read When the upper byte is read, the upper-byte value is transferred to the CPU and the lower-byte value is transferred to TEMP. Next, when the lower byte is read, the lower-byte value in TEMP is transferred to the CPU. These registers should always be accessed 16 bits at a time using an MOV instruction (by word access or two consecutive byte accesses), and the upper byte should always be accessed before the lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction cannot be used to access these registers. Figure 10.2 shows the data flow for access to DACNT. The other registers are accessed similarly. Example 1: Write to DACNT MOV.W R0, @DACNT ; Write R0 contents to DACNT Example 2: Read DADRA MOV.W @DADRA, R0 ; Copy contents of DADRA to R0 Table 10.3 Read and Write Access Methods for 16-Bit Registers Read Write Register Name Word Byte Word Byte DADRA and DADRB Yes Yes Yes × DACNT Yes × Yes × Notes: Yes: Permitted type of access. Word access includes successive byte accesses to the upper byte (first) and lower byte (second). ×: This type of access may give incorrect results. 290 Upper-Byte Write CPU (H'AA) Upper byte Module data bus Bus interface TEMP (H'AA) DACNTH ( ) DACNTL ( ) Lower-Byte Write CPU (H'57) Lower byte Module data bus Bus interface TEMP (H'AA) DACNTH (H'AA) DACNTL (H'57) Figure 10.2 (a) Access to DACNT (CPU Writes H'AA57 to DACNT) 291 Upper-Byte Read CPU (H'AA) Upper byte Module data bus Bus interface TEMP (H'57) DACNTH (H'AA) DACNTL (H'57) Lower-Byte Read CPU (H'57) Lower byte Module data bus Bus interface TEMP (H'57) DACNTH ( ) DACNTL ( ) Figure 10.2 (b) Access to DACNT (CPU Reads H'AA57 from DACNT) 292 10.4 Operation A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. When OS = 0, the value in DADR corresponds to the total width (TL ) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output waveform is inverted and the DADR value corresponds to the total width (TH) of the high (1) output pulses. Figure 10.4 shows the types of waveform output available. 1 conversion cycle (T × 214 (= 16384)) tf Basic cycle (T × 64 or T × 256) tL T: Resolution m TL = ∑ tLn (when OS = 0) n=1 (When CFS = 0, m = 256; when CFS = 1, m = 64) Figure 10.3 PWM D/A Operation Table 10.4 summarizes the relationships of the CKS, CFS, and OS bit settings to the resolution, base cycle, and conversion cycle. The PWM output remains flat unless DADR contains at least a certain minimum value. Table 10.4 indicates the range of DADR settings that give an output waveform like the one in figure 10.3, and lists the conversion cycle length when low-order DADR bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits. 293 Table 10.4 Settings and Operation (Examples when ø = 10 MHz) Fixed DADR Bits Bit Data Resolution Base Conversion TL (if OS = 0) CKS T (µs) CFS Cycle (µs) Cycle (µs) TH (if OS = 1) 0 0.1 0 6.4 1638.4 Precision Conversion (Bits) 3 2 1 0 Cycle* (µs) 1. Always low (or high) 14 1638.4 (DADR = H'0001 to H'03FD) 2. (Data value) × T 12 0 0 409.6 10 0 0 0 0 102.4 (DADR = H'0401 to H'FFFD) 1 25.6 1638.4 1. Always low (or high) 14 1638.4 (DADR = H'0003 to H'00FF) 2. (Data value) × T 12 0 0 409.6 10 0 0 0 0 102.4 (DADR = H'0103 to H'FFFF) 1 0.2 0 12.8 3276.8 1. Always low (or high) 14 3276.8 (DADR = H'0001 to H'03FD) 2. (Data value) × T 12 0 0 819.2 10 0 0 0 0 204.8 (DADR = H'0401 to H'FFFD) 1 51.2 3276.8 1. Always low (or high) 14 3276.8 (DADR = H'0003 to H'00FF) 2. (Data value) × T 12 0 0 819.2 10 0 0 0 0 204.8 (DADR = H'0103 to H'FFFF) Note: * This column indicates the conversion cycle when specific DADR bits are fixed. 294 1. OS = 0 (DADR corresponds to TL) a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tL1 tf2 tf255 tL2 tL3 tL255 tf256 tL256 tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64 tL1 + tL2 + tL3 + · · · + tL255 + tL256 = TL Figure 10.4 (1) Output Waveform b. CFS = 1 [base cycle = resolution (T) × 256] 1 conversion cycle tf1 tL1 tf2 tL2 tf63 tL3 tL63 tf64 tL64 tf1 = tf2 = tf3 = · · · = tf63 = tf64 = T × 256 tL1 + tL2 + tL3 + · · · + tL63 + tL64 = TL Figure 10.4 (2) Output Waveform 295 2. OS = 1 (DADR corresponds to TH) a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tH1 tf2 tf255 tH2 tH3 tH255 tf256 tH256 tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64 tH1 + tH2 + tH3 + · · · + tH255 + tH256 = TH Figure 10.4 (3) Output Waveform b. CFS = 1 [base cycle = resolution (T) × 256] 1 conversion cycle tf1 tH1 tf2 tH2 tf63 tH3 tH63 tf1 = tf2 = tf3 = · · · = tf63 = tf64 = T × 256 tH1 + tH2 + tH3 + · · · + tH63 + tH64 = TH Figure 10.4 (4) Output Waveform 296 tf64 tH64 Section 11 16-Bit Free-Running Timer 11.1 Overview The H8S/2169 or H8S/2149 has a single-channel on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free-running counter as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 11.1.1 Features The features of the free-running timer module are listed below. • Selection of four clock sources The free-running counter can be driven by an internal clock source (ø/2, ø/8, or ø/32), or an external clock input (enabling use as an external event counter). • Two independent comparators Each comparator can generate an independent waveform. • Four input capture channels The current count can be captured on the rising or falling edge (selectable) of an input signal. The four input capture registers can be used separately, or in a buffer mode. • Counter can be cleared under program control The free-running counters can be cleared on compare-match A. • Seven independent interrupts Two compare-match interrupts, four input capture interrupts, and one overflow interrupt can be requested independently. • Special functions provided by automatic addition function The contents of OCRAR and OCRAF can be added to the contents of OCRA automatically, enabling a periodic waveform to be generated without software intervention. The contents of ICRD can be added automatically to the contents of OCRDM × 2, enabling input capture operations in this interval to be restricted. 297 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the free-running timer. External clock source Internal clock sources ø/2 ø/8 ø/32 FTCI Clock select OCRA R/F (H/L) + Clock OCRA (H/L) Comparematch A Comparator A FTOA Overflow FTOB Clear Bus interface FRC (H/L) Comparematch B OCRB (H/L) Control logic Input capture FTIA ICRA (H/L) ICRB (H/L) FTIB Internal data bus Module data bus Comparator B ICRC (H/L) FTIC ICRD (H/L) FTID + Comparator M Compare-match M ×1 ×2 OCRDM L TCSR TIER TCR TOCR ICIA ICIB ICIC ICID OCIA OCIB FOVI Legend: OCRA, B: FRC: ICRA, B, C, D: TCSR: Interrupt signals Output compare register A, B (16 bits) Free-running counter (16 bits) Input capture register A, B, C, D (16 bits) Timer control/status register (8 bits) TIER: Timer interrupt enable register (8 bits) TCR: Timer control register (8 bits) TOCR: Timer output compare control register (8 bits) Figure 11.1 Block Diagram of 16-Bit Free-Running Timer 298 11.1.3 Input and Output Pins Table 11.1 lists the input and output pins of the free-running timer module. Table 11.1 Input and Output Pins of Free-Running Timer Module Name Abbreviation I/O Function Counter clock input FTCI Input FRC counter clock input Output compare A FTOA Output Output compare A output Output compare B FTOB Output Output compare B output Input capture A FTIA Input Input capture A input Input capture B FTIB Input Input capture B input Input capture C FTIC Input Input capture C input Input capture D FTID Input Input capture D input 299 11.1.4 Register Configuration Table 11.2 lists the registers of the free-running timer module. Table 11.2 Register Configuration Name Abbreviation R/W Timer interrupt enable register TIER R/W 2 Initial Value Address* 1 H'01 H'FF90 H'00 H'FF91 Timer control/status register TCSR R/(W)* Free-running counter FRC R/W H'0000 H'FF92 Output compare register A OCRA R/W H'FFFF H'FF94* 3 Output compare register B OCRB R/W H'FFFF H'FF94* 3 Timer control register TCR R/W H'00 H'FF96 Timer output compare control register TOCR R/W H'00 H'FF97 Input capture register A ICRA R H'0000 H'FF98* 4 Input capture register B ICRB R H'0000 H'FF9A* 4 Input capture register C ICRC R H'0000 H'FF9C* 4 Input capture register D ICRD R H'0000 H'FF9E Output compare register AR OCRAR R/W H'FFFF H'FF98* 4 Output compare register AF OCRAF R/W H'FFFF H'FF9A* 4 Output compare register DM OCRDM R/W H'0000 H'FF9C* 4 Module stop control register MSTPCRH R/W H'3F H'FF86 MSTPCRL R/W H'FF H'FF87 Notes: 1. Lower 16 bits of the address. 2. Bits 7 to 1 are read-only; only 0 can be written to clear the flags. Bit 0 is readable/writable. 3. OCRA and OCRB share the same address. Access is controlled by the OCRS bit in TOCR. 4. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF, and OCRDM. Access is controlled by the ICRS bit in TOCR. 300 11.2 Register Descriptions 11.2.1 Free-Running Counter (FRC) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can also be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in TCSR is set to 1. FRC is initialized to H'0000 by a reset and in hardware standby mode. 11.2.2 Output Compare Registers A and B (OCRA, OCRB) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in the FRC. When a match is detected, the corresponding output compare flags (OCFA or OCFB) is set in TCSR. In addition, if the output enable bit (OEA or OEB) in TOCR is set to 1, when OCR and FRC values match, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match. OCR is initialized to H'FFFF by a reset and in hardware standby mode. 301 11.2.3 Input Capture Registers A to D (ICRA to ICRD) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R There are four input capture registers, A to D, each of which is a 16-bit read-only register. When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is detected, the current FRC value is copied to the corresponding input capture register (ICRA to ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to 1. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR. ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, and made to perform buffer operations, by means of buffer enable bits A and B (BUFEA, BUFEB) in TCR. Figure 11.2 shows the connections when ICRC is specified as the ICRA buffer register (BUFEA = 1). When ICRC is used as the ICRA buffer, both rising and falling edges can be specified as transitions of the external input signal by setting IEDGA ≠ IEDGC. When IEDGA = IEDGC, either the rising or falling edge is designated. See table 11.3. Note: The FRC contents are transferred to the input capture register regardless of the value of the input capture flag (ICF). IEDGA BUFEA IEDGC FTIA Edge detect and capture signal generating circuit ICRC ICRA Figure 11.2 Input Capture Buffering (Example) 302 FRC Table 11.3 Buffered Input Capture Edge Selection (Example) IEDGA IEDGC Description 0 0 Captured on falling edge of input capture A (FTIA) 1 Captured on both rising and falling edges of input capture A (FTIA) 1 (Initial value) 0 1 Captured on rising edge of input capture A (FTIA) To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock periods (1.5ø). When triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clock periods (2.5ø). ICR is initialized to H'0000 by a reset and in hardware standby mode. 11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA. The write operation is performed on the occurrence of compare-match A. In the first compare-match A after the OCRAMS bit is set to 1, OCRAF is added. The operation due to compare-match A varies according to whether the compare-match follows addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output on a compare-match A following addition of OCRAF, while 0 is output on a compare-match A following addition of OCRAR. When the OCRA automatically addition function is used, do not set internal clock ø/2 as the FRC counter input clock together with an OCRAR (or OCRAF) value of H'0001 or less. OCRAR and OCRAF are initialized to H'FFFF by a reset and in hardware standby mode. 303 11.2.5 Output Compare Register DM (OCRDM) Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00. When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, the operation of ICRD is changed to include the use of OCRDM. The point at which input capture D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to the contents of ICRD, and the result is compared with the FRC value. The point at which the values match is taken as the end of the mask interval. New input capture D events are disabled during the mask interval. A mask interval is not generated when the ICRDMS bit is set to 1 and the contents of OCRDM are H'0000. OCRDM is initialized to H'0000 by a reset and in hardware standby mode. 11.2.6 Timer Interrupt Enable Register (TIER) Bit 7 6 5 4 3 2 1 0 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — Initial value 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W — TIER is an 8-bit readable/writable register that enables and disables interrupts. TIER is initialized to H'01 by a reset and in hardware standby mode. Bit 7—Input Capture Interrupt A Enable (ICIAE): Selects whether to request input capture interrupt A (ICIA) when input capture flag A (ICFA) in TCSR is set to 1. Bit 7 ICIAE Description 0 Input capture interrupt request A (ICIA) is disabled 1 Input capture interrupt request A (ICIA) is enabled 304 (Initial value) Bit 6—Input Capture Interrupt B Enable (ICIBE): Selects whether to request input capture interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1. Bit 6 ICIBE Description 0 Input capture interrupt request B (ICIB) is disabled 1 Input capture interrupt request B (ICIB) is enabled (Initial value) Bit 5—Input Capture Interrupt C Enable (ICICE): Selects whether to request input capture interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1. Bit 5 ICICE Description 0 Input capture interrupt request C (ICIC) is disabled 1 Input capture interrupt request C (ICIC) is enabled (Initial value) Bit 4—Input Capture Interrupt D Enable (ICIDE): Selects whether to request input capture interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1. Bit 4 ICIDE Description 0 Input capture interrupt request D (ICID) is disabled 1 Input capture interrupt request D (ICID) is enabled (Initial value) Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. Bit 3 OCIAE Description 0 Output compare interrupt request A (OCIA) is disabled 1 Output compare interrupt request A (OCIA) is enabled (Initial value) Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects whether to request output compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. Bit 2 OCIBE Description 0 Output compare interrupt request B (OCIB) is disabled 1 Output compare interrupt request B (OCIB) is enabled (Initial value) 305 Bit 1—Timer Overflow Interrupt Enable (OVIE): Selects whether to request a free-running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1. Bit 1 OVIE Description 0 Timer overflow interrupt request (FOVI) is disabled 1 Timer overflow interrupt request (FOVI) is enabled (Initial value) Bit 0—Reserved: This bit cannot be modified and is always read as 1. 11.2.7 Timer Control/Status Register (TCSR) Bit 7 6 5 4 3 2 1 0 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA 0 0 0 0 R/(W)* R/(W)* R/(W)* R/W Initial value 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written in bits 7 to 1 to clear these flags. TCSR is an 8-bit register used for counter clear selection and control of interrupt request signals. TCSR is initialized to H'00 by a reset and in hardware standby mode. Timing is described in section 11.3, Operation. Bit 7—Input Capture Flag A (ICFA): This status flag indicates that the FRC value has been transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been transferred to ICRA. ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 7 ICFA Description 0 [Clearing condition] Read ICFA when ICFA = 1, then write 0 in ICFA 1 [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRA 306 (Initial value) Bit 6—Input Capture Flag B (ICFB): This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB. ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 6 ICFB Description 0 [Clearing condition] (Initial value) Read ICFB when ICFB = 1, then write 0 in ICFB 1 [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRB Bit 5—Input Capture Flag C (ICFC): This status flag indicates that the FRC value has been transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of the signal transition in FTIC (input capture signal) specified by the IEDGC bit, ICFC is set but data is not transferred to ICRC. Therefore, in buffer operation, ICFC can be used as an external interrupt signal (by setting the ICICE bit to 1). ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 5 ICFC Description 0 [Clearing condition] (Initial value) Read ICFC when ICFC = 1, then write 0 in ICFC 1 [Setting condition] When an input capture signal is received Bit 4—Input Capture Flag D (ICFD): This status flag indicates that the FRC value has been transferred to ICRD by means of an input capture signal. When BUFEB = 1, on occurrence of the signal transition in FTID (input capture signal) specified by the IEDGD bit, ICFD is set but data is not transferred to ICRD. Therefore, in buffer operation, ICFD can be used as an external interrupt by setting the ICIDE bit to 1. ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software. 307 Bit 4 ICFD Description 0 [Clearing condition] (Initial value) Read ICFD when ICFD = 1, then write 0 in ICFD 1 [Setting condition] When an input capture signal is received Bit 3—Output Compare Flag A (OCFA): This status flag indicates that the FRC value matches the OCRA value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 3 OCFA 0 Description [Clearing condition] (Initial value) Read OCFA when OCFA = 1, then write 0 in OCFA 1 [Setting condition] When FRC = OCRA Bit 2—Output Compare Flag B (OCFB): This status flag indicates that the FRC value matches the OCRB value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 2 OCFB Description 0 [Clearing condition] (Initial value) Read OCFB when OCFB = 1, then write 0 in OCFB 1 [Setting condition] When FRC = OCRB Bit 1—Timer Overflow Flag (OVF): This status flag indicates that the FRC has overflowed (changed from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. 308 Bit 1 OVF Description 0 [Clearing condition] (Initial value) Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] When FRC changes from H'FFFF to H'0000 Bit 0—Counter Clear A (CCLRA): This bit selects whether the FRC is to be cleared at comparematch A (when the FRC and OCRA values match). Bit 0 CCLRA Description 0 FRC clearing is disabled 1 FRC is cleared at compare-match A 11.2.8 (Initial value) Timer Control Register (TCR) Bit 7 6 5 4 3 2 1 0 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. TCR is initialized to H'00 by a reset and in hardware standby mode Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A signal (FTIA). Bit 7 IEDGA Description 0 Capture on the falling edge of FTIA 1 Capture on the rising edge of FTIA (Initial value) Bit 6—Input Edge Select B (IEDGB): Selects the rising or falling edge of the input capture B signal (FTIB). 309 Bit 6 IEDGB Description 0 Capture on the falling edge of FTIB 1 Capture on the rising edge of FTIB (Initial value) Bit 5—Input Edge Select C (IEDGC): Selects the rising or falling edge of the input capture C signal (FTIC). Bit 5 IEDGC Description 0 Capture on the falling edge of FTIC 1 Capture on the rising edge of FTIC (Initial value) Bit 4—Input Edge Select D (IEDGD): Selects the rising or falling edge of the input capture D signal (FTID). Bit 4 IEDGD Description 0 Capture on the falling edge of FTID 1 Capture on the rising edge of FTID (Initial value) Bit 3—Buffer Enable A (BUFEA): Selects whether ICRC is to be used as a buffer register for ICRA. Bit 3 BUFEA Description 0 ICRC is not used as a buffer register for input capture A 1 ICRC is used as a buffer register for input capture A (Initial value) Bit 2—Buffer Enable B (BUFEB): Selects whether ICRD is to be used as a buffer register for ICRB. Bit 2 BUFEB Description 0 ICRD is not used as a buffer register for input capture B 1 ICRD is used as a buffer register for input capture B 310 (Initial value) Bits 1 and 0—Clock Select (CKS1, CKS0): Select external clock input or one of three internal clock sources for the FRC. External clock pulses are counted on the rising edge of signals input to the external clock input pin (FTCI). Bit 1 Bit 0 CKS1 CKS0 Description 0 0 ø/2 internal clock source 1 ø/8 internal clock source 0 ø/32 internal clock source 1 External clock source (rising edge) 1 11.2.9 (Initial value) Timer Output Compare Control Register (TOCR) Bit 7 6 ICRDMS OCRAMS 5 4 3 2 1 0 ICRS OCRS OEA OEB OLVLA OLVLB Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TOCR is an 8-bit readable/writable register that enables output from the output compare pins, selects the output levels, switches access between output compare registers A and B, controls the ICRD and OCRA operating mode, and switches access to input capture registers A, B, and C. TOCR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—Input Capture D Mode Select (ICRDMS): Specifies whether ICRD is used in the normal operating mode or in the operating mode using OCRDM. Bit 7 ICRDMS Description 0 The normal operating mode is specified for ICRD 1 The operating mode using OCRDM is specified for ICRD (Initial value) Bit 6—Output Compare A Mode Select (OCRAMS): Specifies whether OCRA is used in the normal operating mode or in the operating mode using OCRAR and OCRAF. 311 Bit 6 OCRAMS Description 0 The normal operating mode is specified for OCRA 1 The operating mode using OCRAR and OCRAF is specified for OCRA (Initial value) Bit 5—Input Capture Register Select (ICRS): The same addresses are shared by ICRA and OCRAR, by ICRB and OCRAF, and by ICRC and OCRDM. The ICRS bit determines which registers are selected when the shared addresses are read or written to. The operation of ICRA, ICRB, and ICRC is not affected. Bit 5 ICRS Description 0 The ICRA, ICRB, and ICRC registers are selected 1 The OCRAR, OCRAF, and OCRDM registers are selected (Initial value) Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. This bit does not affect the operation of OCRA or OCRB. Bit 4 OCRS Description 0 The OCRA register is selected 1 The OCRB register is selected (Initial value) Bit 3—Output Enable A (OEA): Enables or disables output of the output compare A signal (FTOA). Bit 3 OEA Description 0 Output compare A output is disabled 1 Output compare A output is enabled (Initial value) Bit 2—Output Enable B (OEB): Enables or disables output of the output compare B signal (FTOB). 312 Bit 2 OEB Description 0 Output compare B output is disabled 1 Output compare B output is enabled (Initial value) Bit 1—Output Level A (OLVLA): Selects the logic level to be output at the FTOA pin in response to compare-match A (signal indicating a match between the FRC and OCRA values). When the OCRAMS bit is 1, this bit is ignored. Bit 1 OLVLA Description 0 0 output at compare-match A 1 1 output at compare-match A (Initial value) Bit 0—Output Level B (OLVLB): Selects the logic level to be output at the FTOB pin in response to compare-match B (signal indicating a match between the FRC and OCRB values). Bit 0 OLVLB Description 0 0 output at compare-match B 1 1 output at compare-match B 11.2.10 (Initial value) Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP13 bit is set to 1, FRT operation is stopped at the end of the bus cycle, and module stop mode is entered. For details, see section 24.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. 313 MSTPCRH Bit 5—Module Stop (MSTP13): Specifies the FRT module stop mode. Bit 5 MSTPCRH Description 0 FRT module stop mode is cleared 1 FRT module stop mode is set 11.3 Operation 11.3.1 FRC Increment Timing (Initial value) FRC increments on a pulse generated once for each period of the selected (internal or external) clock source. Internal Clock: Any of three internal clocks (ø/2, ø/8, or ø/32) created by division of the system clock (ø) can be selected by making the appropriate setting in bits CKS1 and CKS0 in TCR. Figure 11.3 shows the increment timing. ø Internal clock FRC input clock FRC N–1 N N+1 Figure 11.3 Increment Timing with Internal Clock Source External Clock: If external clock input is selected by bits CKS1 and CKS0 in TCR, FRC increments on the rising edge of the external clock signal. The pulse width of the external clock signal must be at least 1.5 system clock (ø) periods. The counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods. Figure 11.4 shows the increment timing. 314 ø External clock input pin FRC input clock FRC N N+1 Figure 11.4 Increment Timing with External Clock Source 11.3.2 Output Compare Output Timing When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the timing of this operation for compare-match A. ø FRC N OCRA N+1 N N+1 N N Compare-match A signal Clear* OLVLA Output compare A output pin FTOA Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 11.5 Timing of Output Compare A Output 315 11.3.3 FRC Clear Timing FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this operation. ø Compare-match A signal FRC N H'0000 Figure 11.6 Clearing of FRC by Compare-Match A 11.3.4 Input Capture Input Timing Input Capture Input Timing: An internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin, as selected by the corresponding IEDGx (x = A to D) bit in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is selected (IEDGx = 1). ø Input capture input pin Input capture signal Figure 11.7 Input Capture Signal Timing (Usual Case) If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock (ø) period. Figure 11.8 shows the timing for this case. 316 ICRA/B/C/D read cycle T1 T2 ø Input capture input pin Input capture signal Figure 11.8 Input Capture Signal Timing (Input Capture Input when ICRA/B/C/D is Read) Buffered Input Capture Input Timing: ICRC and ICRD can operate as buffers for ICRA and ICRB. Figure 11.9 shows how input capture operates when ICRA and ICRC are used in buffer mode and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDG A = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. ø FTIA Input capture signal FRC n ICRA M ICRC m n+1 N N+1 n n N M M n Figure 11.9 Buffered Input Capture Timing (Usual Case) 317 When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered input capture, if the upper byte of either of the two registers to which data will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives, input capture is delayed by one system clock (ø) period. Figure 11.10 shows the timing when BUFEA = 1. Read cycle: CPU reads ICRA or ICRC T1 T2 ø FTIA Input capture signal Figure 11.10 Buffered Input Capture Timing (Input Capture Input when ICRA or ICRC is Read) 11.3.5 Timing of Input Capture Flag (ICF) Setting The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRx). Figure 11.11 shows the timing of this operation. 318 ø Input capture signal ICFA/B/C/D N FRC ICRA/B/C/D N Figure 11.11 Setting of Input Capture Flag (ICFA/B/C/D) 11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB) The output compare flags are set to 1 by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. Accordingly, when the FRC and OCR values match, the compare-match signal is not generated until the next period of the clock source. Figure 11.12 shows the timing of the setting of OCFA and OCFB. ø FRC N OCRA or OCRB N+1 N Compare-match signal OCFA or OCFB Figure 11.12 Setting of Output Compare Flag (OCFA, OCFB) 319 11.3.7 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 11.13 shows the timing of this operation. ø FRC H'FFFF H'0000 Overflow signal OVF Figure 11.13 Setting of Overflow Flag (OVF) 11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed. The OCRA write timing is shown in figure 11.14. ø FRC N N+1 OCRA N N+A OCRAR, F A Compare-match signal Figure 11.14 OCRA Automatic Addition Timing 320 11.3.9 ICRD and OCRDM Mask Signal Generation When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture function is generated. The mask signal is set by the input capture signal. The mask signal setting timing is shown in figure 11.15. The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and an FRC compare-match. The mask signal clearing timing is shown in figure 11.16. ø Input capture signal Input capture mask signal Figure 11.15 Input Capture Mask Signal Setting Timing ø FRC N ICRD + OCRDM × 2 N+1 N Compare-match signal Input capture mask signal Figure 11.16 Input Capture Mask Signal Clearing Timing 321 11.4 Interrupts The free-running timer can request seven interrupts (three types): input capture A to D (ICIA, ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 11.4 lists information about these interrupts. Table 11.4 Free-Running Timer Interrupts Interrupt Description DTC Activation Priority ICIA Requested by ICFA Possible High ICIB Requested by ICFB Possible ICIC Requested by ICFC Not possible ICID Requested by ICFD Not possible OCIA Requested by OCFA Possible OCIB Requested by OCFB Possible FOVI Requested by OVF Not possible 11.5 Low Sample Application In the example below, the free-running timer is used to generate pulse outputs with a 50% duty cycle and arbitrary phase relationship. The programming is as follows: • The CCLRA bit in TCSR is set to 1. • Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in TOCR (OLVLA or OLVLB). FRC H'FFFF Counter clear OCRA OCRB H'0000 FTOA FTOB Figure 11.17 Pulse Output (Example) 322 11.6 Usage Notes Application programmers should note that the following types of contention can occur in the freerunning timer. Contention between FRC Write and Clear: If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 11.18 shows this type of contention. FRC write cycle T1 T2 ø Address FRC address Internal write signal Counter clear signal FRC N H'0000 Figure 11.18 FRC Write-Clear Contention 323 Contention between FRC Write and Increment: If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 11.19 shows this type of contention. FRC write cycle T1 T2 ø Address FRC address Internal write signal FRC input clock FRC N M Write data Figure 11.19 FRC Write-Increment Contention 324 Contention between OCR Write and Compare-Match: If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is inhibited. Figure 11.20 shows this type of contention. If automatic addition of OCRAR/OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is inhibited. Consequently, the result of the automatic addition is not written to OCRA. Figure 11.21 shows this timing OCRA or OCRB write cycle T1 T2 ø Address OCR address Internal write signal FRC N OCR N N+1 M Write data Compare-match signal Inhibited Figure 11.20 Contention between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used) 325 φ Address OCRAR ( OCRAF ) address Internal write signal OCRAR (OCRAF) Compare-match signal Old Data New Data Inhibited FRC N OCRA N N+1 Compare-match signal is inhibited and automatic addition does not occur. Figure 11.21 Contention between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function is Used) 326 Switching of Internal Clock and FRC Operation: When the internal clock is changed, the changeover may cause FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 11.5. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (ø). If the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 11.5, the changeover is regarded as a falling edge that triggers the FRC increment clock pulse. Switching between an internal and external clock can also cause FRC to increment. Table 11.5 Switching of Internal Clock and FRC Operation No. 1 Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation Switching from low to low Clock before switchover Clock after switchover FRC clock FRC N+1 N CKS bit rewrite 2 Switching from low to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite 327 No. 3 Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation Switching from high to low Clock before switchover Clock after switchover * FRC clock FRC N N+1 N+2 CKS bit rewrite 4 Switching from high to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. 328 Section 12 8-Bit Timers 12.1 Overview The H8S/2169 or H8S/2149 includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-matches. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of a rectangular-wave output with an arbitrary duty cycle. The H8S/2169 or H8S/2149 also has two similar 8-bit timer channels (TMRX and TMRY). These channels can be used in a connected configuration using the timer connection function. TMRX and TMRY have greater input/output and interrupt function related restrictions than TMR0 and TMR1. 12.1.1 Features • Selection of clock sources TMR0, TMR1: The counter input clock can be selected from six internal clocks and an external clock (enabling use as an external event counter). TMRX, TMRY: The counter input clock can be selected from three internal clocks and an external clock (enabling use as an external event counter). • Selection of three ways to clear the counters The counters can be cleared on compare-match A or B, or by an external reset signal. • Timer output controlled by two compare-match signals The timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or PWM output with an arbitrary duty cycle. (Note: TMRY does not have a timer output pin.) • Cascading of the two channels (TMR0, TMR1) Operation as a 16-bit timer can be performed using channel 0 as the upper half and channel 1 as the lower half (16-bit count mode). Channel 1 can be used to count channel 0 compare-match occurrences (compare-match count mode). • Multiple interrupt sources for each channel TMR0, TMR1, TMRY: Two compare-match interrupts and one overflow interrupt can be requested independently. TMRX: One input capture source is available. 329 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the 8-bit timer module (TMR0 and TMR1). TMRX and TMRY have a similar configuration, but cannot be cascaded. TMRX also has an input capture function. For details, see section 13, Timer Connection. External clock sources Internal clock sources TMCI0 TMCI1 TMR0 ø/8, ø/2 ø/64, ø/32 ø/1024, ø/256 TMR1 ø/8, ø/2 ø/64, ø/128 ø/1024, ø/2048 TMRX ø ø/2 ø/4 TMRY ø/4 ø/256 ø/2048 Clock 1 Clock 0 Clock select TCORA0 Compare-match A1 Compare-match A0 Comparator A0 TCNT0 Comparator A1 TCNT1 Clear 0 Clear 1 Compare-match B1 Compare-match B0 Comparator B0 TMO1 TMRI1 Comparator B1 Control logic TCORB0 TCORB1 TCSR0 TCSR1 TCR0 TCR1 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals Figure 12.1 Block Diagram of 8-Bit Timer Module 330 Internal bus Overflow 1 Overflow 0 TMO0 TMRI0 TCORA1 12.1.3 Pin Configuration Table 12.1 summarizes the input and output pins of the 8-bit timer module. Table 12.1 8-Bit Timer Input and Output Pins Channel Name Symbol* I/O Function 0 Timer output TMO0 Output Output controlled by compare-match Timer clock input TMCI0 Input External clock input for the counter Timer reset input TMRI0 Input External reset input for the counter Timer output TMO1 Output Output controlled by compare-match Timer clock input TMCI1 Input External clock input for the counter Timer reset input TMRI1 Input External reset input for the counter Timer output TMOX Output Output controlled by compare-match Timer clock/ reset input HFBACKI/TMIX Input (TMCIX/TMRIX) External clock/reset input for the counter Timer clock/reset input VSYNCI/TMIY Input (TMCIY/TMRIY) External clock/reset input for the counter 1 X Y Note: * The abbreviations TMO, TMCI, and TMRI are used in the text, omitting the channel number. Channel X and Y I/O pins have the same internal configuration as channels 0 and 1, and therefore the same abbreviations are used. 331 12.1.4 Register Configuration Table 12.2 summarizes the registers of the 8-bit timer module. Table 12.2 8-Bit Timer Registers Channel Name Abbreviation* 3 R/W 0 Timer control register 0 TCR0 1 Common Y 2 Address* 1 H'00 H'FFC8 Timer control/status register 0 TCSR0 R/(W)* H'00 H'FFCA Time constant register A0 TCORA0 R/W H'FF H'FFCC Time constant register B0 TCORB0 R/W H'FF H'FFCE Time counter 0 TCNT0 R/W H'00 H'FFD0 Timer control register 1 TCR1 R/W H'00 H'FFC9 Timer control/status register 1 TCSR1 R/(W)*2 H'10 H'FFCB Time constant register A1 TCORA1 R/W H'FF H'FFCD Time constant register B1 TCORB1 R/W H'FF H'FFCF Timer counter 1 TCNT1 R/W H'00 H'FFD1 Serial/timer control register STCR R/W H'00 H'FFC3 Module stop control register X R/W Initial value MSTPCRH R/W H'3F H'FF86 MSTPCRL R/W H'FF H'FF87 Timer connection register S TCONRS R/W H'00 H'FFFE Timer control register X TCRX R/W H'00 H'FFF0 Timer control/status register X TCSRX R/(W)*2 H'00 H'FFF1 Time constant register AX TCORAX R/W H'FF H'FFF6 Time constant register BX TCORBX R/W H'FF H'FFF7 Timer counter X TCNTX R/W H'00 H'FFF4 Time constant register C TCORC R/W H'FF H'FFF5 Input capture register R TICRR R H'00 H'FFF2 Input capture register F TICRF R H'00 H'FFF3 Timer control register Y TCRY R/W H'00 H'FFF0 Timer control/status register Y TCSRY R/(W)*2 H'00 H'FFF1 Time constant register AY TCORAY R/W H'FF H'FFF2 Time constant register BY TCORBY R/W H'FF H'FFF3 Timer counter Y TCNTY R/W H'00 H'FFF4 Timer input select register TISR R/W H'FE H'FFF5 Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written in bits 7 to 5, to clear these flags. 3. The abbreviations TCR, TCSR, TCORA, TCORB, and TCNT are used in the text, omitting the channel designation (0, 1, X, or Y). 332 Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the upper 8 bits for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word access. (Access is not divided into two 8-bit accesses.) In the H8S/2169 or H8S/2149, certain of the channel X and channel Y registers are assigned to the same address. The TMRX/Y bit in TCONRS determines which register is accessed. 12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) TCNT0 TCNT1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNTX,TCNTY Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Each TCNT is an 8-bit readable/writable up-counter. TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by word access. TCNT increments on pulses generated from an internal or external clock source. This clock source is selected by clock select bits CKS2 to CKS0 in TCR. TCNT can be cleared by an external reset input signal or compare-match signal. Counter clear bits CCLR1 and CCLR0 in TCR select the method of clearing. When TCNT overflows from H'FF to H'00, the overflow flag (OVF) in TCSR is set to 1. The timer counters are initialized to H'00 by a reset and in hardware standby mode. 333 12.2.2 Time Constant Register A (TCORA) TCORA0 TCORA1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORAX, TCORAY Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCORA is an 8-bit readable/writable register. TCORA0 and TCORA1 comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCORA write cycle. The timer output can be freely controlled by these compare-match signals and the settings of output select bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF by a reset and in hardware standby mode. 334 12.2.3 Time Constant Register B (TCORB) TCORB0 TCORB1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORBX, TCORBY Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCORB is an 8-bit readable/writable register. TCORB0 and TCORB1 comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCORB write cycle. The timer output can be freely controlled by these compare-match signals and the settings of output select bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF by a reset and in hardware standby mode. 12.2.4 Timer Control Register (TCR) Bit 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCR is an 8-bit readable/writable register that selects the clock source and the time at which TCNT is cleared, and enables interrupts. TCR is initialized to H'00 by a reset and in hardware standby mode. For details of the timing, see section 12.3, Operation. 335 Bit 7—Compare-Match Interrupt Enable B (CMIEB): Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. Note that a CMIB interrupt is not requested by TMRX, regardless of the CMIEB value. Bit 7 CMIEB Description 0 CMFB interrupt request (CMIB) is disabled 1 CMFB interrupt request (CMIB) is enabled (Initial value) Bit 6—Compare-Match Interrupt Enable A (CMIEA): Selects whether the CMFA interrupt request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1. Note that a CMIA interrupt is not requested by TMRX, regardless of the CMIEA value. Bit 6 CMIEA Description 0 CMFA interrupt request (CMIA) is disabled 1 CMFA interrupt request (CMIA) is enabled (Initial value) Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. Note that an OVI interrupt is not requested by TMRX, regardless of the OVIE value. Bit 5 OVIE Description 0 OVF interrupt request (OVI) is disabled 1 OVF interrupt request (OVI) is enabled (Initial value) Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select the method by which the timer counter is cleared: by compare-match A or B, or by an external reset input. Bit 4 Bit 3 CCLR1 CCLR0 Description 0 0 Clearing is disabled 1 Cleared on compare-match A 0 Cleared on compare-match B 1 Cleared on rising edge of external reset input 1 336 (Initial value) Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to TCNT is an internal or external clock. The input clock can be selected from either six or three clocks, all divided from the system clock (ø). The falling edge of the selected internal clock triggers the count. When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. Some functions differ between channel 0 and channel 1, because of the cascading function. TCR STCR Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description 0 1 0 0 0 — — Clock input disabled (Initial value) 0 0 1 — 0 ø/8 internal clock source, counted on the falling edge 0 0 1 — 1 ø/2 internal clock source, counted on the falling edge 0 1 0 — 0 ø/64 internal clock source, counted on the falling edge 0 1 0 — 1 ø/32 internal clock source, counted on the falling edge 0 1 1 — 0 ø/1024 internal clock source, counted on the falling edge 0 1 1 — 1 ø/256 internal clock source, counted on the falling edge 1 0 0 — — Counted on TCNT1 overflow signal* 0 0 0 — — Clock input disabled 0 0 1 0 — ø/8 internal clock source, counted on the falling edge 0 0 1 1 — ø/2 internal clock source, counted on the falling edge 0 1 0 0 — ø/64 internal clock source, counted on the falling edge 0 1 0 1 — ø/128 internal clock source, counted on the falling edge 0 1 1 0 — ø/1024 internal clock source, counted on the falling edge 0 1 1 1 — ø/2048 internal clock source, counted on the falling edge 1 0 0 — — Counted on TCNT0 compare-match A* (Initial value) 337 TCR STCR Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description X 0 0 0 — — Clock input disabled 0 0 1 — — Counted on ø internal clock source 0 1 0 — — ø/2 internal clock source, counted on the falling edge 0 1 1 — — ø/4 internal clock source, counted on the falling edge 1 0 0 — — Clock input disabled 0 0 0 — — Clock input disabled 0 0 1 — — ø/4 internal clock source, counted on the falling edge 0 1 0 — — ø/256 internal clock source, counted on the falling edge 0 1 1 — — ø/2048 internal clock source, counted on the falling edge 1 0 0 — — Clock input disabled Common 1 0 1 — — External clock source, counted at rising edge 1 1 0 — — External clock source, counted at falling edge 1 1 1 — — External clock source, counted at both rising and falling edges Y (Initial value) (Initial value) Note: * If the clock input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare-match signal, no incrementing clock will be generated. Do not use this setting. 338 12.2.5 Timer Control/Status Register (TCSR) TCSR0 Bit 7 6 5 4 3 2 1 0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 CMFB CMFA OVF — OS3 OS2 OS1 OS0 Initial value 0 0 0 1 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* — R/W R/W R/W R/W 7 6 5 4 3 2 1 0 CMFB CMFA OVF ICF OS3 OS2 OS1 OS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W 7 6 5 4 3 2 1 0 CMFB CMFA OVF ICIE OS3 OS2 OS1 OS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W TCSR1 Bit TCSRX Bit TCSRY Bit Note: * Only 0 can be written in bits 7 to 5, and in bit 4 in TCSRX, to clear these flags. TCSR is an 8-bit register that indicates compare-match and overflow statuses (and input capture status in TMRX only), and controls compare-match output. TCSR0, TCSRX, and TCSRY are initialized to H'00, and TCSR1 is initialized to H'10, by a reset and in hardware standby mode. Bit 7—Compare-Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match. 339 Bit 7 CMFB Description 0 [Clearing conditions] 1 • Read CMFB when CMFB = 1, then write 0 in CMFB • When the DTC is activated by a CMIB interrupt (Initial value) [Setting condition] When TCNT = TCORB Bit 6—Compare-match Flag A (CMFA): Status flag indicating whether the values of TCNT and TCORA match. Bit 6 CMFA Description 0 [Clearing conditions] 1 • Read CMFA when CMFA = 1, then write 0 in CMFA • When the DTC is activated by a CMIA interrupt (Initial value) [Setting condition] When TCNT = TCORA Bit 5 —Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed from H'FF to H'00). Bit 5 OVF Description 0 [Clearing condition] (Initial value) Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] When TCNT overflows from H'FF to H'00 TCSR0 Bit 4—A/D Trigger Enable (ADTE): Enables or disables A/D converter start requests by compare-match A. Bit 4 ADTE Description 0 A/D converter start requests by compare-match A are disabled 1 A/D converter start requests by compare-match A are enabled 340 (Initial value) TCSR1 Bit 4—Reserved: This bit cannot be modified and is always read as 1. TCSRX Bit 4—Input Capture Flag (ICF): Status flag that indicates detection of a rising edge followed by a falling edge in the external reset signal after the ICST bit in TCONRI has been set to 1. Bit 4 ICF Description 0 [Clearing condition] (Initial value) Read ICF when ICF = 1, then write 0 in ICF 1 [Setting condition] When a rising edge followed by a falling edge is detected in the external reset signal after the ICST bit in TCONRI has been set to 1 TCSRY Bit 4—Input Capture Interrupt Enable (ICIE): Selects enabling or disabling of the interrupt request by ICF (ICIX) when the ICF bit in TCSRX is set to 1. Bit 4 ICIE Description 0 Interrupt request by ICF (ICIX) is disabled 1 Interrupt request by ICF (ICIX) is enabled (Initial value) Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is to be changed by a compare-match of TCOR and TCNT. OS3 and OS2 select the effect of compare-match B on the output level, OS1 and OS0 select the effect of compare-match A on the output level, and both of them can be controlled independently. Note, however, that priorities are set such that: trigger output > 1 output > 0 output. If comparematches occur simultaneously, the output changes according to the compare-match with the higher priority. Timer output is disabled when bits OS3 to OS0 are all 0. After a reset, the timer output is 0 until the first compare-match occurs. 341 Bit 3 Bit 2 OS3 OS2 Description 0 0 No change when compare-match B occurs 1 0 is output when compare-match B occurs 0 1 is output when compare-match B occurs 1 Output is inverted when compare-match B occurs (toggle output) 1 (Initial value) Bit 1 Bit 0 OS1 OS0 Description 0 0 No change when compare-match A occurs 1 0 is output when compare-match A occurs 0 1 is output when compare-match A occurs 1 Output is inverted when compare-match A occurs (toggle output) 1 12.2.6 (Initial value) Serial/Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 IICS IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode (when the on-chip IIC option is included), and on-chip flash memory and also selects the TCNT input clock. For details on functions not related to the 8-bit timers, see section 3.2.4, Serial/Timer Control Register (STCR), and the descriptions of the relevant modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit. STCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4—I2C Control (IICS, IICX1, IICX0, IICE): These bits control the operation of the I2C bus interface, etc. when the IIC option is included on-chip. See section 3.2.4, Serial/Timer Control Register (STCR) and section 16, I2C Bus Interface, for details. Bit 3—Flash Memory Control Register Enable (FLSHE): Controls the access of CPU to the flash memory control registers, the power-down mode control registers, and the supporting module control registers. See section 3.2.4, Serial/Timer Control Register (STCR). 342 Bit 2—Reserved: Do not write 1 to this bit. Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12.2.4, Timer Control Register. 12.2.7 System Control Register (SYSCR) 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W Bit Only bit 1 is described here. For details on functions not related to the 8-bit timers, see sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules. Bit 1—Host Interface Enable (HIE): Controls CPU access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection control registers. Bit 1 HIE Description 0 CPU access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection control registers, is enabled 1 CPU access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection control registers, is disabled 12.2.8 (Initial value) Timer Connection Register S (TCONRS) Bit 7 6 5 4 3 2 1 0 TMRX/Y ISGENE HOMOD1HOMOD0 VOMOD1 VOMOD0 CLMOD1 CLMOD0 Initial value 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W 0 R/W 0 0 R/W R/W TCONRS is an 8-bit readable/writable register that controls access to the TMRX and TMRY registers and timer connection operation. TCONRS is initialized to H'00 by a reset and in hardware standby mode. 343 Bit 7—TMRX/TMRY Access Select (TMRX/Y): The TMRX and TMRY registers can only be accessed when the HIE bit in SYSCR is cleared to 0. Some of the TMRX registers and the TMRY registers are assigned to the same memory space addresses (H'FFF0 to H'FFF5), and the TMRX/Y bit determines which registers are accessed. Accessible Registers Bit 7 TMRX/Y H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 0 TMRX (Initial value) TCRX TMRX TMRX TMRX TMRX TMRX TMRX TMRX TCSRX TICRR TICRF TCNTX TCORC TCORAX TCORBX 1 TMRY TMRY TMRY TMRY TMRY TMRY TCRY TCSRY TCORAY TCORBY TCNTY 12.2.9 H'FFF0 TISR Input Capture Register (TICR) [TMRX Additional Function] Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write — — — — — — — — TICR is an 8-bit internal register to which the contents of TCNT are transferred on the falling edge of external reset input. The CPU cannot read or write to TICR directly. The TICR function is used in timer connection. For details, see section 13, Timer Connection. 12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function] Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCORC is an 8-bit readable/writable register. The sum of the contents of TCORC and TICR is continually compared with the value in TCNT. When a match is detected, a compare-match C signal is generated. Note, however, that comparison is disabled during the T2 state of a TCORC write cycle and a TICR input capture cycle. TCORC is initialized to H'FF by a reset and in hardware standby mode. The TCORC function is used in timer connection. For details, see section 13, Timer Connection. 344 12.2.11 Input Capture Registers R and F (TICRR, TICRF) [TMRX Additional Functions] 7 Bit 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R TICRR and TICRF are 8-bit read-only registers. When the ICST bit in TCONRI is set to 1, TICRR and TICRF capture the contents of TCNT successively on the rise and fall of the external reset input. When one capture operation ends, the ICST bit is cleared to 0. TICRR and TICRF are each initialized to H'00 by a reset and in hardware standby mode. The TICRR and TICRF functions are used in timer connection. For details, see section 12.3.6, Input Capture Operation and section 13, Timer Connection. 12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function] 7 6 5 4 3 2 1 0 — — — — — — — IS Initial value 1 1 1 1 1 1 1 0 Read/Write — — — — — — — R/W Bit TISR is an 8-bit readable/writable register that selects the external clock/reset signal source for the counter. TISR is initialized to H'FE by a reset and in hardware standby mode. Bits 7 to 1—Reserved: Do not write 0 to these bits. Bit 0—Input Select (IS): Selects the internal synchronization signal (IVG signal) or the timer clock/reset input pin (VSYNCI/TMIY (TMCIY/TMRIY)) as the external clock/reset signal source for the counter. Bit 0 IS Description 0 IVG signal is selected 1 VSYNCI/TMIY (TMCIY/TMRIY) is selected (Initial value) 345 12.2.13 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. When the MSTP12 bit or MSTP8 bit is set to 1, 8-bit timer operation is halted on channels 0 and 1 or channels X and Y, respectively, and a transition is made to module stop mode. For details, see section 24.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 4—Module Stop (MSTP12): Specifies 8-bit timer (channel 0/1) module stop mode. MSTPCRH Bit 4 MSTP12 Description 0 8-bit timer (channel 0/1) module stop mode is cleared 1 8-bit timer (channel 0/1) module stop mode is set (Initial value) MSTPCRH Bit 0—Module Stop (MSTP8): Specifies 8-bit timer (channel X/Y) and timer connection module stop mode. MSTPCRH Bit 0 MSTP8 Description 0 8-bit timer (channel X/Y) and timer connection module stop mode is cleared 1 8-bit timer (channel X/Y) and timer connection module stop mode is set 346 (Initial value) 12.3 Operation 12.3.1 TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: An internal clock created by dividing the system clock (ø) can be selected by setting bits CKS2 to CKS0 in TCR. Figure 12.2 shows the count timing. ø Internal clock TCNT input clock TCNT N–1 N N+1 Figure 12.2 Count Timing for Internal Clock Input External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR: at the rising edge, the falling edge, and both rising and falling edges. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. Figure 12.3 shows the timing of incrementation at both edges of an external clock signal. 347 ø External clock input pin TCNT input clock TCNT N–1 N N+1 Figure 12.3 Count Timing for External Clock Input 12.3.2 Compare-Match Timing Setting of Compare-Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCOR and TCNT values match. The compare-match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare-match signal is not generated until the next incrementation clock input. Figure 12.4 shows this timing. ø TCNT N TCOR N Compare-match signal CMF Figure 12.4 Timing of CMF Setting 348 N+1 Timer Output Timing: When compare-match A or B occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in TCSR. Depending on these bits, the output can remain the same, be set to 0, be set to 1, or toggle. Figure 12.5 shows the timing when the output is set to toggle at compare-match A. ø Compare-match A signal Timer output pin Figure 12.5 Timing of Timer Output Timing of Compare-Match Clear: TCNT is cleared when compare-match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12.6 shows the timing of this operation. ø Compare-match signal TCNT N H'00 Figure 12.6 Timing of Compare-Match Clear 349 12.3.3 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 12.7 shows the timing of this operation. ø External reset input pin Clear signal TCNT N–1 N H'00 Figure 12.7 Timing of Clearing by External Reset Input 12.3.4 Timing of Overflow Flag (OVF) Setting OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 12.8 shows the timing of this operation. ø TCNT H'FF H'00 Overflow signal OVF Figure 12.8 Timing of OVF Setting 350 12.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit timer mode) or compare-matches of 8-bit channel 0 can be counted by the timer of channel 1 (comparematch count mode). In this case, the timer operates as described below. 16-Bit Count Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. • Setting of compare-match flags The CMF flag in TCSR0 is set to 1 when a 16-bit compare-match occurs. The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare-match occurs. • Counter clear specification If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare-match, the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare-match occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has also been set. The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot be cleared independently. • Pin output Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with the 16-bit compare-match conditions. Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with the lower 8-bit compare-match conditions. Compare-Match Count Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare-match A’s for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each channel. Usage Note: If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided. 351 12.3.6 Input Capture Operation TMRX has input capture registers of TICR, TICRR and TICRF. Narrow pulse width can be measured with TICRR and TICRF, using capture operation controlled by the ICST bit in the TCONRI register of the timer connection. When TMRIX detects rising edge and falling edge successively after the ICST bit is set to 1, the value of TCNT at the time is transferred to TICRR and TICRF, respectively. Input signal to TMRIX can be switched by the setting of the other bits in TCONRI register. (1) Input capture signal input timing Timing of the input capture operation is shown in figure 12.9. φ TMRIX Input capture signal TCNTX n TICRR M TICRF m n+1 n N N+1 n m N Figure12.9 Timing of Input Capture Operation If input capture signal is input while TICRR and TICRF is read, the input capture signal delays by one system clock (φ) period internally. Figure 12.10 shows the timing of this operation. 352 TICRR, TICRF read cycle T1 T2 φ TMRIX Input capture signal Figure 12.10 Timing of Input Capture Signal (Input capture signal is input during TICRR and TICRF read) (2) Selection of the input capture signal input The input capture signal in TMRX is switched according to the setting of the bits in TCONRI register. Input capture signal selections are shown in figure 12.11 and table 12.3. For details, see section 13.2.1, Timer Connection Register I (TCONRI). TMRX TMIX pin Polarity inversion TMRI1 pin Polarity inversion TMCI1 pin Polarity inversion HFINV, HIINV Signal selector TMRIX SIMOD1, SIMOD0 ICST Figure 12.11 Input Capture Signal selections 353 Table 12.3 Input Capture Signal Selection TCONRI Bit 4 Bit 7 Bit 6 Bit 3 Bit 1 ICST SIMOD1 SIMOD0 HFINV HIINV Description 0 — — — — Input capture function not used 1 0 0 0 — TMIX pin input selection 1 — Inverted TMIX pin input selection — 0 TMRI1 pin input selection — 1 Inverted TMRI1 pin input selection — 0 TMCI1 pin input selection — 1 Inverted TMCI1 pin input selection 1 1 12.4 1 Interrupt Sources The TMR0, TMR1, and TMRY 8-bit timers can generate three types of interrupt: compare-match A and B (CMIA and CMIB), and overflow (OVI). TMRX can generate only an ICIX interrupt. An interrupt is requested when the corresponding interrupt enable bit is set in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. It is also possible to activate the DTC by means of CMIA and CMIB interrupts from TMR0, TMR1 and TMRY. An overview of 8-bit timer interrupt sources is given in tables 12.4 to 12.6. Table 12.4 TMR0 and TMR1 8-Bit Timer Interrupt Sources Interrupt source Description DTC Activation Interrupt Priority CMIA Requested by CMFA Possible High CMIB Requested by CMFB Possible OVI Requested by OVF Not possible Table 12.5 TMRX 8-Bit Timer Interrupt Source Interrupt source Description DTC Activation ICIX Requested by ICF Not possible 354 Low Table 12.6 TMRY 8-Bit Timer Interrupt Sources Interrupt source Description DTC Activation Interrupt Priority CMIA Requested by CMFA Possible High CMIB Requested by CMFB Possible OVI Requested by OVF Not possible 12.5 Low 8-Bit Timer Application Example In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12.12. The control bits are set as follows: • In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared by a TCORA compare-match. • In TCSR, bits OS3 to OS0 are set to B'0110, causing 1 output at a TCORA compare-match and 0 output at a TCORB compare-match. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. TCNT H'FF Counter clear TCORA TCORB H'00 TMO Figure 12.12 Pulse Output (Example) 355 12.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer module. 12.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12.13 shows this operation. TCNT write cycle by CPU T1 T2 ø Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 12.13 Contention between TCNT Write and Clear 356 12.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 12.14 shows this operation. TCNT write cycle by CPU T1 T2 ø Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.14 Contention between TCNT Write and Increment 357 12.6.3 Contention between TCOR Write and Compare-Match During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match occurs and the compare-match signal is disabled. Figure 12.15 shows this operation. With TMRX, an ICR input capture contends with a compare-match in the same way as with a write to TCORC. In this case, the input capture has priority and the compare-match signal is inhibited. TCOR write cycle by CPU T1 T2 ø Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare-match signal Inhibited Figure 12.15 Contention between TCOR Write and Compare-Match 358 12.6.4 Contention between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 12.7. Table 12.7 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 12.6.5 Low Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 12.8 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 12.8, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. Erroneous incrementation can also happen when switching between internal and external clocks. 359 Table 12.8 Switching of Internal Clock and TCNT Operation No. 1 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from low to low* 1 Clock before switchover Clock after switchover TCNT clock TCNT N N+1 CKS bit rewrite 2 Switching from low to high* 2 Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite 360 No. 3 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high to low* 3 Clock before switchover Clock after switchover *4 TCNT clock TCNT N N+1 N+2 CKS bit rewrite 4 Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. 361 362 Section 13 Timer Connection 13.1 Overview The H8S/2169 or H8S/2149 allows interconnection between a combination of input signals, the input/output of the single free-running timer (FRT) channel and the three 8-bit timer channels (TMR1, TMRX, and TMRY). This capability can be used to implement complex functions such as PWM decoding and clamp waveform output. All the timers are initially set for independent operation. 13.1.1 Features The features of the timer connection facility are as follows. • Five input pins and four output pins, all of which can be designated for phase inversion. Positive logic is assumed for all signals used within the timer connection facility. • An edge-detection circuit is connected to the input pins, simplifying signal input detection. • TMRX can be used for PWM input signal decoding and clamp waveform generation. • An external clock signal divided by TMR1 can be used as the FRT capture input signal. • An internal synchronization signal can be generated using the FRT and TMRY. • A signal generated/modified using an input signal and timer connection can be selected and output. 363 364 Figure 13.1 Block Diagram of Timer Connection Facility HFBACKI/ FTCI/TMIX CSYNCI/ TMRI1 HSYNCI/ TMCI1 FTID FTIC VFBACKI/ FTIB VSYNCI/ FTIA/TMIY Phase inversion Phase inversion Phase inversion Phase inversion Phase inversion Edge detection Edge detection Edge detection Edge detection Edge detection IHI signal selection IVI signal selection FRT input selection IVI signal READ flag IHI signal READ flag 16-bit FRT VSYNC modify FTOA ICR +1C compare match ICR 8-bit TMRX PWM decoding PDC signal TMRI CMA TMO CMB CMB TMCI 8-bit TMR1 TMO CLAMP waveform generation CM1C TMRI TMCI TMR1 input selection CBLANK waveform generation SET RES 2f H mask generation 2f H mask/flag FTIB OCRA +VR, +VF CMA(R) FTIC ICRD +1M, +2M CMA(F) compare match FTOB FTID CM1M CM2M FTIA SET sync RES CL1 signal CL2 signal CL3 signal RES VSYNC generation SET CL signal selection CL4 signal FRT output selection phase inversion phase inversion Phase inversion TMO1 output selection TMRI/TMCI 8-bit TMRY TMO IVO signal Phase inversion CL4 generation IHO signal selection TMIY signal selection IVG signal IVO signal selection CLAMPO/ FTIC TMOX HSYNCO/ TMO1 CBLANK IHG signal VSYNCO/ FTOA 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the timer connection facility. 13.1.3 Input and Output Pins Table 13.1 lists the timer connection input and output pins. Table 13.1 Timer Connection Input and Output Pins Name Abbreviation Input/ Output Vertical synchronization signal input pin VSYNCI Input Vertical synchronization signal input pin or FTIA input pin/TMIY input pin Horizontal synchronization signal input pin HSYNCI Input Horizontal synchronization signal input pin or TMCI1 input pin Composite synchronization signal input pin CSYNCI Input Composite synchronization signal input pin or TMRI1 input pin Spare vertical synchronization signal input pin VFBACKI Input Spare vertical synchronization signal input pin or FTIB input pin Spare horizontal synchronization signal input pin HFBACKI Input Spare horizontal synchronization signal input pin or FTCI input pin/TMIX input pin Vertical synchronization signal output pin VSYNCO Output Vertical synchronization signal output pin or FTOA output pin Horizontal synchronization signal output pin HSYNCO Output Horizontal synchronization signal output pin or TMO1 output pin Clamp waveform output pin CLAMPO Output Clamp waveform output pin or FTIC input pin Blanking waveform output pin CBLANK Output Blanking waveform output pin Function 365 13.1.4 Register Configuration Table 13.2 lists the timer connection registers. Timer connection registers can only be accessed when the HIE bit in SYSCR is 0. Table 13.2 Register Configuration Name Abbreviation R/W Initial Value Address* 1 Timer connection register I TCONRI R/W H'00 H'FFFC Timer connection register O TCONRO R/W H'00 H'FFFD Timer connection register S TCONRS R/W H'00 2 H'00* H'FFFE 3 Edge sense register SEDGR R/(W)* H'FFFF Module stop control register MSTPRH R/W H'3F H'FF86 MSTPRL R/W H'FF H'FF87 Notes: 1. Lower 16 bits of the address. 2. Bits 7 to 2: Only 0 can be written, to clear the flags. 3. Bits 1 and 0: Undefined (reflect the pin states). 13.2 Register Descriptions 13.2.1 Timer Connection Register I (TCONRI) Bit 7 6 5 SIMOD1 SIMOD0 SCONE 4 3 2 1 0 ICST HFINV VFINV HIINV VIINV Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCONRI is an 8-bit readable/writable register that controls connection between timers, the signal source for synchronization signal input, phase inversion, etc. TCONR1 is initialized to H'00 by a reset and in hardware standby mode. 366 Bits 7 and 6—Input Synchronization Mode Select 1 and 0 (SIMOD1, SIMOD0): These bits select the signal source of the IHI and IVI signals. Bit 7 Bit 6 SIMOD1 SIMOD0 Mode 0 0 No signal 1 S-on-G mode CSYNCI input PDC input 0 Composite mode HSYNCI input PDC input 1 Separate mode HSYNCI input VSYNCI input 1 Description IHI Signal (Initial value) HFBACKI input IVI Signal VFBACKI input Bit 5—Synchronization Signal Connection Enable (SCONE): Selects the signal source of the FRT FTI input and the TMR1 TMCI1/TMRI1 input. Bit 5 Description SCONE Mode FTIA FTIB FTIC FTID TMCI1 TMRI1 0 Normal connection (Initial value) FTIA input FTIB input FTIC input FTID input TMCI1 TMRI1 input input 1 Synchronization signal connection mode TMO1 signal VFBACKI IHI input signal IVI signal IHI signal IVI inverse signal Bit 4—Input Capture Start Bit (ICST): The TMRX external reset input (TMRIX) is connected to the IHI signal. TMRX has input capture registers (TICR, TICRR, and TICRF). TICRR and TICRF can measure the width of a short pulse by means of a single capture operation under the control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF, respectively, and the ICST bit is cleared to 0. Bit 4 ICST Description 0 The TICRR and TICRF input capture functions are stopped (Initial value) [Clearing condition] When a rising edge followed by a falling edge is detected on TMRIX 1 The TICRR and TICRF input capture functions are operating (Waiting for detection of a rising edge followed by a falling edge on TMRIX) [Setting condition] When 1 is written in ICST after reading ICST = 0 367 Bits 3 to 0—Input Synchronization Signal Inversion (HFINV, VFINV, HIINV, VIINV): These bits select inversion of the input phase of the spare horizontal synchronization signal (HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal synchronization signal and composite synchronization signal (HSYNCI, CSYNCI), and the vertical synchronization signal (VSYNCI). Bit 3 HFINV Description 0 The HFBACKI pin state is used directly as the HFBACKI input 1 The HFBACKI pin state is inverted before use as the HFBACKI input (Initial value) Bit 2 VFINV Description 0 The VFBACKI pin state is used directly as the VFBACKI input 1 The VFBACKI pin state is inverted before use as the VFBACKI input (Initial value) Bit 1 HIINV Description 0 The HSYNCI and CSYNCI pin states are used directly as the HSYNCI and CSYNCI inputs 1 (Initial value) The HSYNCI and CSYNCI pin states are inverted before use as the HSYNCI and CSYNCI inputs Bit 0 VIINV Description 0 The VSYNCI pin state is used directly as the VSYNCI input 1 The VSYNCI pin state is inverted before use as the VSYNCI input 368 (Initial value) 13.2.2 Timer Connection Register O (TCONRO) Bit 7 6 5 4 3 2 HOE VOE CLOE CBOE HOINV VOINV Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 1 0 CLOINV CBOINV TCONRO is an 8-bit readable/writable register that controls output signal output, phase inversion, etc. TCONRO is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 4—Output Enable (HOE, VOE, CLOE, CBOE): These bits control enabling/disabling of horizontal synchronization signal (HSYNCO), vertical synchronization signal (VSYNCO), clamp waveform (CLAMPO), and blanking waveform (CBLANK) output. When output is disabled, the state of the relevant pin is determined by the port DR and DDR, FRT, TMR, and PWM settings. Output enabling/disabling control does not affect the port, FRT, or TMR input functions, but some FRT and TMR input signal sources are determined by the SCONE bit in TCONRI. Bit 7 HOE Description 0 The P44/TMO1/HIRQ1/HSYNCO pin functions as the P44/TMO1/ HIRQ1 pin 1 The P44/TMO1/HIRQ1/HSYNCO pin functions as the HSYNCO pin (Initial value) Bit 6 VOE Description 0 The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the P61/FTOA/ KIN1/CIN1 pin 1 The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the VSYNCO pin (Initial value) Bit 5 CLOE Description 0 The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the P64/FTIC/KIN4/CIN4 pin 1 The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the CLAMPO pin (Initial value) 369 Bit 4 CBOE Description 0 The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin 1 In mode 1 (expanded mode with on-chip ROM disabled): The P27/A15/PW15/CBLANK pin functions as the A15 pin (Initial value) In modes 2 and 3 (modes with on-chip ROM enabled): The P27/A15/PW15/CBLANK pin functions as the CBLANK pin Bits 3 to 0—Output Synchronization Signal Inversion (HOINV, VOINV, CLOINV, CBOINV): These bits select inversion of the output phase of the horizontal synchronization signal (HSYNCO), the vertical synchronization signal (VSYNCO), the clamp waveform (CLAMPO), and the blank waveform (CBLANK). Bit 3 HOINV Description 0 The IHO signal is used directly as the HSYNCO output 1 The IHO signal is inverted before use as the HSYNCO output (Initial value) Bit 2 VOINV Description 0 The IVO signal is used directly as the VSYNCO output 1 The IVO signal is inverted before use as the VSYNCO output (Initial value) Bit 1 CLOINV Description 0 The CLO signal (CL1, CL2, CL3, or CL4 signal) is used directly as the CLAMPO output 1 The CLO signal (CL1, CL2, CL3, or CL4 signal) is inverted before use as the CLAMPO output (Initial value) Bit 0 CBOINV Description 0 The CBLANK signal is used directly as the CBLANK output 1 The CBLANK signal is inverted before use as the CBLANK output 370 (Initial value) 13.2.3 Timer Connection Register S (TCONRS) Bit 7 6 5 4 3 2 0 1 TMRX/Y ISGENE HOMOD1 HOMOD0VOMOD1 VOMOD0 CLMOD1 CLMOD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCONRS is an 8-bit readable/writable register that selects 8-bit timer TMRX/TMRY access and the synchronization signal output signal source and generation method. TCONRS is initialized to H'00 by a reset and in hardware standby mode. Bit 7—TMRX/TMRY Access Select (TMRX/Y): The TMRX and TMRY registers can only be accessed when the HIE bit in SYSCR is cleared to 0. Some of the TMRX registers and the TMRY registers are assigned to the same memory space addresses (H'FFF0 to H'FFF5), and the TMRX/Y bit determines which registers are accessed. Bit 7 TMRX/Y Description 0 The TMRX registers are accessed at addresses H'FFF0 to H'FFF5 1 The TMRY registers are accessed at addresses H'FFF0 to H'FFF5 (Initial value) Bit 6—Internal Synchronization Signal Select (ISGENE): Selects internal synchronization signals (IHG, IVG, and CL4 signals) as the signal sources for the IHO, IVO, and CLO signals. Bits 5 and 4—Horizontal Synchronization Output Mode Select 1 and 0 (HOMOD1, HOMOD0): These bits select the signal source and generation method for the IHO signal. Bit 6 Bit 5 Bit 4 ISGENE VOMOD1 VOMOD0 Description 0 0 0 The IHI signal (without 2fH modification) is selected 1 The IHI signal (with 2fH modification) is selected 0 The CL1 signal is selected 1 (Initial value) 1 1 0 0 The IHG signal is selected 1 1 0 1 371 Bits 3 and 2—Vertical Synchronization Output Mode Select 1 and 0 (VOMOD1, VOMOD0): These bits select the signal source and generation method for the IVO signal. Bit 6 Bit 3 Bit 2 ISGENE VOMOD1 VOMOD0 Description 0 0 0 The IVI signal (without fall modification or IHI synchronization) is selected 1 The IVI signal (without fall modification, with IHI synchronization) is selected 0 The IVI signal (with fall modification, without IHI synchronization) is selected 1 The IVI signal (with fall modification and IHI synchronization) is selected 0 The IVG signal is selected 1 1 0 (Initial value) 1 1 0 1 Bits 1 and 0—Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits select the signal source for the CLO signal (clamp waveform). Bit 6 Bit 1 Bit 0 ISGENE CLMOD1 CLMOD2 Description 0 0 0 The CL1 signal is selected 1 The CL2 signal is selected 0 The CL3 signal is selected 1 1 1 0 0 1 1 0 1 372 The CL4 signal is selected (Initial value) 13.2.4 Edge Sense Register (SEDGR) Bit Initial value Read/Write 7 6 5 VEDG HEDG CEDG 0 0 *1 R/(W) 4 0 *1 R/(W) HFEDG VFEDG PREQF 0 *1 R/(W) 2 3 0 0 *1 R/(W) *1 R/(W) R/(W) *1 1 0 IHI IVI —*2 —*2 R R Notes: 1. Only 0 can be written, to clear the flags. 2. The initial value is undefined since it depends on the pin states. SEDGR is an 8-bit readable/writable register used to detect a rising edge on the timer connection input pins and the occurrence of 2fH modification, and to determine the phase of the IVI and IHI signals. The upper 6 bits of SEDGR are initialized to 0 by a reset and in hardware standby mode. The initial value of the lower 2 bits is undefined, since it depends on the pin states. Bit 7—VSYNCI Edge (VEDG): Detects a rising edge on the VSYNCI pin. Bit 7 VEDG Description 0 [Clearing condition] When 0 is written in VEDG after reading VEDG = 1 1 [Setting condition] When a rising edge is detected on the VSYNCI pin (Initial value) Bit 6—HSYNCI Edge (HEDG): Detects a rising edge on the HSYNCI pin. Bit 6 HEDG Description 0 [Clearing condition] When 0 is written in HEDG after reading HEDG = 1 1 [Setting condition] When a rising edge is detected on the HSYNCI pin (Initial value) 373 Bit 5—CSYNCI Edge (CEDG): Detects a rising edge on the CSYNCI pin. Bit 5 CEDG Description 0 [Clearing condition] When 0 is written in CEDG after reading CEDG = 1 1 [Setting condition] When a rising edge is detected on the CSYNCI pin (Initial value) Bit 4—HFBACKI Edge (HFEDG): Detects a rising edge on the HFBACKI pin. Bit 4 HFEDG Description 0 [Clearing condition] When 0 is written in HFEDG after reading HFEDG = 1 1 [Setting condition] When a rising edge is detected on the HFBACKI pin (Initial value) Bit 3—VFBACKI Edge (VFEDG): Detects a rising edge on the VFBACKI pin. Bit 3 VFEDG Description 0 [Clearing condition] When 0 is written in VFEDG after reading VFEDG = 1 1 [Setting condition] When a rising edge is detected on the VFBACKI pin (Initial value) Bit 2—Pre-Equalization Flag (PREQF): Detects the occurrence of an IHI signal 2fH modification condition. The generation of a falling/rising edge in the IHI signal during a mask interval is expressed as the occurrence of a 2fH modification condition. For details, see section 13.3.4, IHI Signal 2fH Modification. Bit 2 PREQF Description 0 [Clearing condition] When 0 is written in PREQF after reading PREQF = 1 1 [Setting condition] When an IHI signal 2fH modification condition is detected 374 (Initial value) Bit 1—IHI Signal Level (IHI): Indicates the current level of the IHI signal. Signal source and phase inversion selection for the IHI signal depends on the contents of TCONRI. Read this bit to determine whether the input signal is positive or negative, then maintain the IHI signal at positive phase by modifying TCONRI. Bit 1 IHI Description 0 The IHI signal is low 1 The IHI signal is high Bit 0—IVI Signal Level (IVI): Indicates the current level of the IVI signal. Signal source and phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to determine whether the input signal is positive or negative, then maintain the IVI signal at positive phase by modifying TCONRI. Bit 0 IVI Description 0 The IVI signal is low 1 The IVI signal is high 13.2.5 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP13, MSTP12, and MSTP8 bits are set to 1, the 16-bit free-running timer, 8-bit timer channels 0 and 1, and 8-bit timer channels X and Y and timer connection, respectively, halt and enter module stop mode. See section 24.5, Module Stop Mode, for details. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. 375 MSTPCRH Bit 5—Module Stop (MSTP13): Specifies FRT module stop mode. MSTPCRH Bit 5 MSTP13 Description 0 FRT module stop mode is cleared 1 FRT module stop mode is set (Initial value) MSTPCRH Bit 4—Module Stop (MSTP12): Specifies 8-bit timer channel 0 and 1 module stop mode. MSTPCRH Bit 4 MSTP12 Description 0 8-bit timer channel 0 and 1 module stop mode is cleared 1 8-bit timer channel 0 and 1 module stop mode is set (Initial value) MSTPCRH Bit 0—Module Stop (MSTP8): Specifies 8-bit timer channel X and Y and timer connection module stop mode. MSTPCRH Bit 0 MSTP8 Description 0 8-bit timer channel X and Y and timer connection module stop mode is cleared 1 8-bit timer channel X and Y and timer connection module stop mode is set 13.3 Operation 13.3.1 PWM Decoding (PDC Signal Generation) (Initial value) The timer connection facility and TMRX can be used to decode a PWM signal in which 0 and 1 are represented by the pulse width. To do this, a signal in which a rising edge is generated at regular intervals must be selected as the IHI signal. The timer counter (TCNT) in TMRX is set to count the internal clock pulses and to be cleared on the rising edge of the external reset signal (IHI signal). The value to be used as the threshold for deciding the pulse width is written in TCORB. The PWM decoder contains a delay latch which uses the IHI signal as data and compare-match signal B (CMB) as a clock, and the state of the IHI signal (the result of the pulse width decision) at the compare-match signal B timing after TCNT is 376 reset by the rise of the IHI signal is output as the PDC signal. The pulse width setting using TICRR and TICRF of TMRX can be used to determine the pulse width decision threshold. Examples of TCR and TCORB settings are shown in tables 13.3 and 13.4, and the timing chart is shown in figure 13.2. Table 13.3 Examples of TCR Settings Bit(s) Abbreviation Contents Description 7 CMIEB 0 6 CMIEA 0 Interrupts due to compare-match and overflow are disabled 5 OVIE 0 4 and 3 CCLR1, CCLR0 11 TCNT is cleared by the rising edge of the external reset signal (IHI signal) 2 to 0 CKS2 to CKS0 001 Incremented on internal clock: ø Table 13.4 Examples of TCORB (Pulse Width Threshold) Settings ø:10 MHz H'07 0.8 µs H'0F 1.6 µs H'1F 3.2 µs H'3F 6.4 µs H'7F 12.8 µs IHI signal is tested at compare-match IHI signal PDC signal TCNT TCORB (threshold) Counter reset caused by IHI signal Counter clear caused by TCNT overflow At the 2nd compare-match, IHI signal is not tested Figure 13.2 Timing Chart for PWM Decoding 377 13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) The timer connection facility and TMRX can be used to generate signals with different duty cycles and rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI signal). Three clamp waveforms can be generated: the CL1, CL2, and CL3 signals. In addition, the CL4 signal can be generated using TMRY. The CL1 signal rises simultaneously with the rise of the IHI signal, and when the CL1 signal is high, the CL2 signal rises simultaneously with the fall of the IHI signal. The fall of both the CL1 and the CL2 signal can be specified by TCORA. The rise of the CL3 signal can be specified as simultaneous with the sampling of the fall of the IHI signal using the system clock, and the fall of the CL3 signal can be specified by TCORC. TCNT in TMRX is set to count internal clock pulses and to be cleared on the rising edge of the external reset signal (IHI signal). The CL3 signal can also fall when the IHI signal rises. The value to be used as the CL1 signal pulse width is written in TCORA. Write a value of H'02 or more in TCORA when internal clock ø is selected as the TMRX counter clock, and a value or H'01 or more when ø/2 is selected. When internal clock ø is selected, the CL1 signal pulse width is (TCORA set value + 3 ± 0.5). When the CL2 signal is used, the setting must be made so that this pulse width is greater than the IHI signal pulse width. The value to be used as the CL3 signal pulse width is written in TCORC. The TICR register in TMRX captures the value of TCNT at the inverse of the external reset signal edge (in this case, the falling edge of the IHI signal). The timing of the fall of the CL3 signal is determined by the sum of the contents of TICR and TCORC. Caution is required if the rising edge of the IHI signal precedes the fall timing set by the contents of TCORC, since the IHI signal will cause the CL3 signal to fall. Examples of TMRX TCR settings are the same as those in table 13.3. The clamp waveform timing charts are shown in figures 13.3 and 13.4. Since the rise of the CL1 and CL2 signals is synchronized with the edge of the IHI signal, and their fall is synchronized with the system clock, the pulse width variation is equivalent to the resolution of the system clock. Both the rise and the fall of the CL3 signal are synchronized with the system clock and the pulse width is fixed, but there is a variation in the phase relationship with the IHI signal equivalent to the resolution of the system clock. 378 IHI signal CL1 signal CL2 signal TCNT TCORA Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals) IHI signal CL3 signal TCNT TICR+TCORC TICR Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal) 13.3.3 Measurement of 8-Bit Timer Divided Waveform Period The timer connection facility, TMR1, and the free-running timer (FRT) can be used to measure the period of an IHI signal divided waveform. Since TMR1 can be cleared by a rising edge of the external reset signal (Inverse of the IVI signal), the rise and fall of the IHI signal divided waveform can be virtually synchronized with the IVI signal. This enables period measurement to be carried out efficiently. To measure the period of an IHI signal divided waveform, TCNT in TMR1 is set to count the external clock (IHI signal) pulses and to be cleared on the rising edge of the external reset signal (Inverse of the IVI signal). The value to be used as the division factor is written in TCORA, and the TMO output method is specified by the OS bits in TCSR. Examples of TCR and TCSR settings are shown in table 13.5, and the timing chart for measurement of the IVI signal and IHI signal divided waveform periods is shown in figure 13.5. The period of the IHI signal divided waveform is given by (ICRD(3) – ICRD(2)) × the resolution. 379 Table 13.5 Examples of TCR and TCSR Settings Register Bit(s) Abbreviation Contents Description TCR in TMR1 7 CMIEB 0 Interrupts due to compare-match and overflow are disabled 6 CMIEA 0 5 OVIE 0 4 and 3 CCLR1, CCLR0 11 TCNT is cleared by the rising edge of the external reset signal (Inverse of the IVI signal) 2 to 0 CKS2 to CKS0 101 TCNT is incremented on the rising edge of the external clock (IHI signal) 3 to 0 OS3 to OS0 0011 Not changed by compare-match B; output inverted by compare-match A (toggle output): division by 512 TCSR in TMR1 1001 TCR in FRT 6 IEDGB 0/1 or when TCORB < TCORA, 1 output on compare-match B, and 0 output on compare-match A: division by 256 0: FRC value is transferred to ICRB on falling edge of input capture input B (IHI divided signal waveform) 1: FRC value is transferred to ICRB on rising edge of input capture input B (IHI divided signal waveform) TCSR in FRT 380 1 and 0 CKS1, CKS0 01 FRC is incremented on internal clock: ø/8 0 0 FRC clearing is disabled CCLRA IVI signal IHI signal divided waveform ICRB(4) ICRB(3) ICRB(2) ICRB(1) FRC ICRB Figure 13.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods 13.3.4 IHI Signal and 2fH Modification By using the timer connection FRT, even if there is a part of the IHI signal with twice the frequency, this can be eliminated. In order for this function to operate properly, the duty cycle of the IHI signal must be approximately 30% or less, or approximately 70% or above. The 8-bit OCRDM contents or twice the OCRDM contents can be added automatically to the data captured in ICRD in the FRT, and compare-matches generated at these points. The interval between the two compare-matches is called a mask interval. A value equivalent to approximately 1/3 the IHI signal period is written in OCRDM. ICRD is set so that capture is performed on the rise of the IHI signal. Since the IHI signal supplied to the IHO signal selection circuit is normally set on the rise of the IHI signal and reset on the fall, its waveform is the same as that of the original IHI signal. When 2fH modification is selected, IHI signal edge detection is disabled during mask intervals. Capture is also disabled during these intervals. Examples of FRT TCR settings are shown in table 13.6, and the 2fH modification timing chart is shown in figure 13.6. 381 Table 13.6 Examples of TCR, TCSR, TCOR, and OCRDM Settings Register Bit(s) Abbreviation Contents Description TCR in FRT 4 IEDGD 1 FRC value is transferred to ICRD on the rising edge of input capture input D (IHI signal) 1 and 0 CKS1, CKS0 01 FRC is incremented on internal clock: ø/8 TCSR in FRT 0 CCLRA 0 FRC clearing is disabled TCOR in FRT 7 ICRDMS 1 ICRD is set to the operating mode in which OCRDM is used OCRDM7 to 0 H'01 to H'FF Specifies the period during which ICRD operation is masked OCRDM in FRT 7 to 0 IHI signal (without 2fH modification) IHI signal (with 2fH modification) Mask interval ICRD + OCRDM × 2 ICRD + OCRDM FRC ICRD Figure 13.6 2fH Modification Timing Chart 382 13.3.5 IVI Signal Fall Modification and IHI Synchronization By using the timer connection TMR1, the fall of the IVI signal can be shifted backward by the specified number of IHI signal waveforms. Also, the fall of the IVI signal can be synchronized with the rise of the IHI signal. To perform 8-bit timer divided waveform period measurement, TCNT in TMR1 is set to count external clock (IHI signal) pulses, and to be cleared on the rising edge of the external reset signal (inverse of the IVI signal). The number of IHI signal pulses until the fall of the IVI signal is written in TCORB. Since the IVI signal supplied to the IVO signal selection circuit is normally set on the rise of the IVI signal and reset on the fall, its waveform is the same as that of the original IVI signal. When fall modification is selected, a reset is performed on a TMR1 TCORB compare-match. The fall of the waveform generated in this way can be synchronized with the rise of the IHI signal, regardless of whether or not fall modification is selected. Examples of TMR1 TCORB, TCR, and TCSR settings are shown in table 13.7, and the fall modification/IHI synchronization timing chart is shown in figure 13.7. Table 13.7 Examples of TCORB, TCR, and TCSR Settings Register Bit(s) Abbreviation Contents Description TCR in TMR1 7 CMIEB 0 Interrupts due to compare-match and overflow are disabled 6 CMIEA 0 5 OVIE 0 4 and 3 CCLR1, CCLR0 11 TCNT is cleared by the rising edge of the external reset signal (inverse of the IVI signal) 2 to 0 CKS2 to CKS0 101 TCNT is incremented on the rising edge of the external clock (IHI signal) 3 to 0 OS3 to OS0 0011 Not changed by compare-match B; output inverted by compare-match A (toggle output) TCSR in TMR1 1001 TCORB in TMR1 H'03 (example) or when TCORB ≤ TCORA, 1 output on compare-match B, 0 output on comparematch A Compare-match on the 4th (example) rise of the IHI signal after the rise of the inverse of the IVI signal 383 IHI signal IVI signal (PDC signal) IVO signal (without fall modification, with IHI synchronization) IVO signal (with fall modification, without IHI synchronization) IVO signal (with fall modification and IHI synchronization) TCNT 0 1 2 3 4 5 TCNT = TCORB (3) Figure 13.7 Fall Modification/IHI Synchronization Timing Chart 13.3.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) By using the timer connection FRT and TMRY, it is possible to automatically generate internal signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG signal is synchronized with the rise of the IVG signal, the IHG signal period must be made a divisor of the IVG signal period in order to keep it constant. In addition, the CL4 signal can be generated in synchronization with the IHG signal. The contents of OCRA in the FRT are updated by the automatic addition of the contents of OCRAR or OCRAF, alternately, each time a compare-match occurs. A value corresponding to the 0 interval of the IVG signal is written in OCRAR, and a value corresponding to the 1 interval of the IVG signal is written in OCRAF. The IVG signal is set by a compare-match after an OCRAR addition, and reset by a compare-match after an OCRAF addition. The IHG signal is the TMRY 8-bit timer output. TMRY is set to count internal clock pulses, and to be cleared on TCORA compare-match, to fix the period and set the timer output. TCORB is set so as to reset the timer output. The IVG signal is connected as the TMRY reset input (TMRI), and the rise of the IVG signal can be treated in the same way as a TCORA compare-match. The CL4 signal is a waveform that rises within one system clock period after the fall of the IHG signal, and has a 1 interval of 6 system clock periods. Examples of settings of TCORA, TCORB, TCR, and TCSR in TMRY, and OCRAR, OCRAF, and TCR in the FRT, are shown in table 13.8, and the IHG signal/IVG signal timing chart is shown in figure 13.8. 384 Table 13.8 Examples of OCRAR, OCRAF, TOCR, TCORA, TCORB, TCR, and TCSR Settings Register Bit(s) Abbreviation Contents Description TCR in TMRY 7 CMIEB 0 Interrupts due to compare-match and overflow are disabled 6 CMIEA 0 5 OVIE 0 4 and 3 CCLR1, CCLR0 01 2 to 0 CKS2 to CKS0 001 TCNT is incremented on internal clock: ø/4 3 to 0 OS3 to OS0 0110 0 output on compare-match B 1 output on compare-match A TOCRA in TMRY H'3F (example) IHG signal period = ø × 256 TOCRB in TMRY H'03 (example) IHG signal 1 interval = ø × 16 01 FRC is incremented on internal clock: ø/8 OCRAR in FRT H'7FEF (example) IVG signal 0 interval = ø × 262016 OCRAF in FRT H'000F (example) IVG signal 1 interval = ø × 128 1 OCRA is set to the operating mode in which OCRAR and OCRAF are used TCSR in TMRY TCR in FRT TOCR in FRT 1 and 0 6 CKS1, CKS0 OCRAMS TCNT is cleared by compare-match A IVG signal period = ø × 262144 (1024 times IHG signal) 385 IVG signal OCRA (1) = OCRA (0) + OCRAF OCRA (2) = OCRA (1) + OCRAR OCRA (3) = OCRA (2) + OCRAF OCRA (4) = OCRA (3) + OCRAR OCRA FRC 6 system clocks 6 system clocks 6 system clocks CL4 signal IHG signal TCORA TCORB TCNT Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart 386 13.3.7 HSYNCO Output With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IHI signal source and the waveform required by external circuitry. The meaning of the HSYNCO output in each mode is shown in table 13.9. Table 13.9 Meaning of HSYNCO Output in Each Mode Mode IHI Signal IHO Signal Meaning of IHO Signal No signal HFBACKI input IHI signal (without 2fH modification) HFBACKI input is output directly IHI signal (with 2fH modification) Meaningless unless there is a double-frequency part in the HFBACKI input CL1 signal HFBACKI input 1 interval is changed before output IHG signal Internal synchronization signal is output IHI signal (without 2fH modification) CSYNCI input (composite synchronization signal) is output directly IHI signal (with 2fH modification) Double-frequency part of CSYNCI input (composite synchronization signal) is eliminated before output CL1 signal CSYNCI input (composite synchronization signal) horizontal synchronization signal part is separated before output IHG signal Internal synchronization signal is output IHI signal (without 2fH modification) HSYNCI input (composite synchronization signal) is output directly IHI signal (with 2fH modification) Double-frequency part of HSYNCI input (composite synchronization signal) is eliminated before output CL1 signal HSYNCI input (composite synchronization signal) horizontal synchronization signal part is separated before output IHG signal Internal synchronization signal is output IHI signal (without 2fH modification) HSYNCI input (horizontal synchronization signal) is output directly IHI signal (with 2fH modification) Meaningless unless there is a double-frequency part in the HSYNCI input (horizontal synchronization signal) CL1 signal HSYNCI input (horizontal synchronization signal) 1 interval is changed before output IHG signal Internal synchronization signal is output S-on-G mode CSYNCI input Composite HSYNCI mode input Separate mode HSYNCI input 387 13.3.8 VSYNCO Output With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IVI signal source and the waveform required by external circuitry. The meaning of the VSYNCO output in each mode is shown in table 13.10. Table 13.10 Meaning of VSYNCO Output in Each Mode Mode IVI Signal IVO Signal Meaning of IVO Signal No signal VFBACKI input IVI signal (without fall modification or IHI synchronization) VFBACKI input is output directly IVI signal (without fall modification, with IHI synchronization) Meaningless unless VFBACKI input is synchronized with HFBACKI input IVI signal (with fall modification, without IHI synchronization) VFBACKI input fall is modified before output IVI signal (with fall modification and IHI synchronization) VFBACKI input fall is modified and signal is synchronized with HFBACKI input before output IVG signal Internal synchronization signal is output IVI signal (without fall modification or IHI synchronization) CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated before output IVI signal (without fall modification, with IHI synchronization) CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated, and signal is synchronized with CSYNCI/HSYNCI input before output IVI signal (with fall modification, without IHI synchronization) CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated, and fall is modified before output IVI signal (with fall modification and IHI synchronization) CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated, fall is modified, and signal is synchronized with CSYNCI/HSYNCI input before output IVG signal Internal synchronization signal is output PDC signal S-on-G mode or composite mode 388 Mode IVI Signal IVO Signal Meaning of IVO Signal Separate mode VSYNCI input IVI signal (without fall modification or IHI synchronization) VSYNCI input (vertical synchronization signal) is output directly IVI signal (without fall modification, with IHI synchronization) Meaningless unless VSYNCI input (vertical synchronization signal) is synchronized with HSYNCI input (horizontal synchronization signal) IVI signal (with fall modification, without IHI synchronization) VSYNCI input (vertical synchronization signal) fall is modified before output IVI signal (with fall modification and IHI synchronization) VSYNCI input (vertical synchronization signal) fall is modified and signal is synchronized with HSYNCI input (horizontal synchronization signal) before output IVG signal Internal synchronization signal is output 13.3.9 CBLANK Output Using the signals generated/selected with timer connection, it is possible to generate a waveform based on the composite synchronization signal (blanking waveform). One kind of blanking waveform is generated by combining HFBACKI and VFBACKI inputs, with the phase polarity made positive by means of bits HFINV and VFINV in TCONRI, with the IVO signal. The composition logic is shown in figure 13.9. HFBACKI input (positive) VFBACKI input (positive) Falling edge sensing Reset Rising edge sensing Set Q CBLANK signal (positive) IVO signal (positive) Figure 13.9 CBLANK Output Waveform Generation 389 390 Section 14 Watchdog Timer (WDT) 14.1 Overview The H8S/2169 or H8S/2149 has an on-chip watchdog timer with two channels (WDT0, WDT1) for monitoring system operation. The WDT outputs an overflow signal (RESO) if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal or internal NMI interrupt signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer mode, an interval timer interrupt is generated each time the counter overflows. 14.1.1 Features WDT features are listed below. • Switchable between watchdog timer mode and interval timer mode • Internal reset or internal interrupt generated when the timer counter overflows WOVI interrupt generation in interval timer mode Choice of internal reset or NMI interrupt generation in watchdog timer mode • RESO output in watchdog timer mode In watchdog timer mode, a low-level signal is output from the RESO pin when the counter overflows (when internal reset is selected) • Choice of 8 (WDT0) or 16 (WDT1) counter input clocks Maximum WDT interval: system clock period × 131072 × 256 Subclock can be selected for the WDT1 input counter Maximum interval when the subclock is selected: subclock period × 256 × 256 391 14.1.2 Block Diagram Figures 14.1 (a) and (b) show block diagrams of WDT0 and WDT1. WOVI0 (interrupt request signal) RESO signal*1 Interrupt control Overflow Clock Clock select Reset control Internal reset signal*1 Internal clock source TCNT TCSR Module bus Bus interface Internal bus Internal NMI interrupt request signal*2 ø/2 ø/64 ø/128 ø/512 ø/2048 ø/8192 ø/32768 ø/131072 WDT0 Legend: TCSR: Timer control/status register TCNT: Timer counter Notes: 1. RESO pin output goes low when the internal reset signal is generated by overflow of TCNT in either WDT0 or WDT1. The reset of the WDT that overflowed first takes precedence over the internal reset signal. 2. The internal NMI interrupt request signal can be output independently by either WDT0 or WDT1. The interrupt controller does not distinguish between NMI interrupt requests from WDT0 and WDT1. Figure 14.1 (a) Block Diagram of WDT0 392 Internal NMI (interrupt request signal)*2 RESO signal*1 Interrupt control Overflow Clock ø/2 ø/64 ø/128 ø/512 ø/2048 ø/8192 ø/32768 ø/131072 Clock select Reset control Internal reset signal*1 Internal clock source TCNT øSUB/2 øSUB/4 øSUB/8 øSUB/16 øSUB/32 øSUB/64 øSUB/128 øSUB/256 TCSR Bus interface Module bus Internal bus WOVI1 (interrupt request signal) WDT1 Legend: TCSR: Timer control/status register TCNT: Timer counter Notes: 1. RESO pin output goes low when the internal reset signal is generated by overflow of TCNT in either WDT0 or WDT1. The reset of the WDT that overflowed first takes precedence over the internal reset signal. 2. The internal NMI interrupt request signal can be output independently by either WDT0 or WDT1. The interrupt controller does not distinguish between NMI interrupt requests from WDT0 and WDT1. Figure 14.1 (b) Block Diagram of WDT1 14.1.3 Pin Configuration Table 14.1 describes the WDT input pin. Table 14.1 WDT Pin Name Symbol I/O Function Reset output pin RESO Output Watchdog timer mode counter overflow signal output External subclock input pin EXCL Input WDT1 prescaler counter input clock 393 14.1.4 Register Configuration The WDT has four registers, as summarized in table 14.2. These registers control clock selection, WDT mode switching, the reset signal, etc. Table 14.2 WDT Registers Address* 1 Channel 0 1 Common Name Abbreviation R/W Timer control/status register 0 TCSR0 R/(W)* Timer counter 0 TCNT0 R/W 3 3 Initial Value Write*2 Read H'00 H'FFA8 H'FFA8 H'00 H'FFA8 H'FFA9 H'00 H'FFEA H'FFEA Timer control/status register 1 TCSR1 R/(W)* Timer counter 1 TCNT1 R/W H'00 H'FFEA H'FFEB System control register SYSCR R/W H'09 H'FFC4 H'FFC4 Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 14.2.4, Notes on Register Access. 3. Only 0 can be written in bit 7, to clear the flag. 14.2 Register Descriptions 14.2.1 Timer Counter (TCNT) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), the OVF flag in TCSR is set to 1. Watchdog timer overflow signal (RESO) output, an internal reset, NMI interrupt, interval timer interrupt (WOVI), etc., can be generated, depending on the mode selected by the WT/IT bit and RST/NMI bit. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. 394 Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 14.2.4, Notes on Register Access. 14.2.2 Timer Control/Status Register (TCSR) • TCSR0 Bit 7 6 5 4 3 2 1 0 OVF WT/IT TME RSTS RST/NMI CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written, to clear the flag. • TCSR1 Bit 7 6 5 4 3 2 1 0 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written, to clear the flag. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCSR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 14.2.4, Notes on Register Access. 395 Bit 7—Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF to H'00. Bit 7 OVF Description 0 [Clearing conditions] 1 • Write 0 in the TME bit • Read TCSR when OVF = 1*, then write 0 in OVF (Initial value) [Setting condition] When TCNT overflows (changes from H'FF to H'00) (When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.) Note: When OVF flag is polled and the interval timer interrupt is disabled, OVF=1 must be read at last twice. Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates a reset or NMI interrupt when TCNT overflows. When internal reset is selected in watchdog timer mode, a lowlevel signal is output from the RESO pin. Bit 6 WT/IT Description 0 Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows 1 (Initial value) Watchdog timer mode: Generates a reset or NMI interrupt when TCNT overflows At the same time, a low-level signal is output from the RESO pin (when internal reset is selected) Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME Description 0 TCNT is initialized to H'00 and halted 1 TCNT counts 396 (Initial value) TCSR0 Bit 4—Reset Select (RSTS): Reserved. This bit should not be set to 1. TCSR1 Bit 4—Prescaler Select (PSS): Selects the input clock source for TCNT in WDT1. For details, see the description of the CKS2 to CKS0 bits below. Bit 4 PSS Description 0 TCNT counts ø-based prescaler (PSM) divided clock pulses 1 TCNT counts øSUB-based prescaler (PSS) divided clock pulses (Initial value) Bit 3—Reset or NMI (RST/NMI): Specifies whether an internal reset or NMI interrupt is requested on TCNT overflow in watchdog timer mode. Bit 3 RST/NMI Description 0 An NMI interrupt is requested 1 An internal reset is requested (Initial value) 397 Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source, obtained by dividing the system clock (ø), or subclock (øSUB) for input to TCNT. • WDT0 input clock selection Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Clock Overflow Period* (when ø = 10 MHz) 0 0 0 ø/2 (Initial value) 51.2 µs 1 ø/64 1.6 ms 0 ø/128 3.2 ms 1 ø/512 13.1 ms 0 ø/2048 52.4 ms 1 ø/8192 209.7 ms 0 ø/32768 838.9 ms 1 ø/131072 3.36 s 1 1 0 1 Description Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. 398 • WDT1 input clock selection Bit 4 Bit 2 Bit 1 Bit 0 PSS CKS2 CKS1 CKS0 Clock 0 0 0 0 ø/2 (Initial value) 51.2 µs 1 ø/64 1.6 ms 0 ø/128 3.2 ms 1 ø/512 13.1 ms 0 ø/2048 52.4 ms 1 ø/8192 209.7 ms 0 ø/32768 838.9 ms 1 ø/131072 3.36 s 0 øSUB/2 15.6 ms 1 øSUB/4 31.3 ms 0 øSUB/8 62.5 ms 1 øSUB/16 125 ms 0 øSUB/32 250 ms 1 øSUB/64 500 ms 0 øSUB/128 1s 1 øSUB/256 2s 1 1 0 1 1 0 0 1 1 0 1 Description Overflow Period* (when ø = 10 MHz and øSUB = 32.768 kHz) Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. 14.2.3 System Control Register (SYSCR) 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W Bit Only bit 3 is described here. For details on functions not related to the watchdog timer, see sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules. 399 Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a read-only bit. It is set to 1 by an external reset, and when the RST/NMI bit is 1, is cleared to 0 by an internal reset due to watchdog timer overflow. Bit 3 XRST Description 0 Reset is generated by watchdog timer overflow 1 Reset is generated by external reset input 14.2.4 (Initial value) Notes on Register Access The watchdog timer’s TCNT and TCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR (Example of WDT0): These registers must be written to by a word transfer instruction. They cannot be written to with byte transfer instructions. Figure 14.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR. TCNT write 15 8 7 H'5A Address: H'FFA8 0 Write data TCSR write 15 Address: H'FFA8 8 7 H'A5 0 Write data Figure 14.2 Format of Data Written to TCNT and TCSR (Example of WDT0) Reading TCNT and TCSR (Example of WDT0): These registers are read in the same way as other registers. The read addresses are H'FFA8 for TCSR, and H'FFA9 for TCNT. 400 14.3 Operation 14.3.1 Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before overflow occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, an internal reset or NMI interrupt request is generated. When the RST/NMI bit is set to 1, the chip is reset for 518 system clock periods (518 ø) by a counter overflow, and at the same time a low-level signal is output from the RESO pin for 132 states. This is illustrated in figure 14.3. The system can be reset using this RESO signal. When the RST/NMI bit cleared to 0, an NMI interrupt request is generated by a counter overflow. In this case, the RESO output signal remains high. An internal reset request from the watchdog timer and reset input from the RES pin are handled via the same vector. The reset source can be identified from the value of the XRST bit in SYSCR. If a reset caused by an input signal from the RES pin and a reset caused by WDT overflow occur simultaneously, the RES pin reset has priority, and the XRST bit in SYSCR is set to 1. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are handled via the same vector. Simultaneous handling of a watchdog timer NMI interrupt request and an NMI pin interrupt request must therefore be avoided. 401 TCNT value Overflow H'FF Time H'00 WT/IT = 1 TME = 1 H'00 written to TCNT OVF = 1* WT/IT = 1 H'00 written TME = 1 to TCNT RESO and internal reset generated RESO signal 132 system clock periods Internal reset signal WT/IT: Timer mode select bit TME: Timer enable bit OVF: Overflow flag 518 system clock periods Note: * Cleared to 0 by an internal reset when OVF is set to 1. XRST is cleared to 0. Figure 14.3 Operation in Watchdog Timer Mode (RST/NMI = 1) 14.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 14.4. This function can be used to generate interrupt requests at regular intervals. 402 TCNT count Overflow H'FF Overflow Overflow Overflow Time H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Legend: WOVI: Interval timer interrupt request generation Figure 14.4 Operation in Interval Timer Mode 14.3.3 Timing of Setting of Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 14.5. If NMI request generation is selected in watchdog timer mode, when TCNT overflows the OVF bit in TCSR is set to 1 and at the same time an NMI interrupt is requested. ø TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 14.5 Timing of OVF Setting 403 14.3.4 RESO Signal Output Timing When TCNT overflows in watchdog timer mode, the OVF bit is set to 1 in TCSR. If the RST/NMI bit is 1 at this time, an internal reset signal is generated for the entire chip, and at the same time a low-level signal is output from the RESO pin. The timing is shown in figure 14.6. ø TCNT H'FF H'00 Overflow signal (internal signal) OVF RESO signal Internal reset signal 132 states 518 states Figure 14.6 RESO Signal Output Timing 14.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in watchdog timer mode, an overflow generates an NMI interrupt request. 404 14.5 Usage Notes 14.5.1 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.7 shows this operation. TCNT write cycle T1 T2 ø Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.7 Contention between TCNT Write and Increment 14.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 405 14.5.4 System Reset by RESO Signal If the RESO output signal is input to the chip’s RES pin, the chip will not be initialized correctly. Ensure that the RESO signal is not logically input to the chip’s RES pin. When resetting the entire system with the RESO signal, use a circuit such as that shown in figure 14.8. Chip Reset input Reset signal to entire system RES RESO Figure 14.8 Sample Circuit for System Reset by RESO Signal 14.5.5 Counter Value in Transitions between High-Speed Mode, Subactive Mode, and Watch Mode If the mode is switched between high-speed mode and subactive mode or between high-speed mode and watch mode when WDT1 is used as a realtime clock counter, an error will occur in the counter value when the internal clock is switched. When the mode is switched from high-speed mode to subactive mode or watch mode, the increment timing is delayed by approximately 2 or 3 clock cycles when the WDT1 control clock is switched from the main clock to the subclock. Also, since the main clock oscillator is halted during subclock operation, when the mode is switched from watch mode or subactive mode to high-speed mode, the clock is not supplied until internal oscillation stabilizes. As a result, after oscillation is started, counter incrementing is halted during the oscillation stabilization time set by bits STS2 to STS0 in SBYCR, and there is a corresponding discrepancy in the counter value. Caution is therefore required when using WDT1 as the realtime clock counter. No error occurs in the counter value while WDT1 is operating in the same mode. 406 14.5.6 OVF Flag Clear Condition To clear OVF flag in WOVI handling routine, read TCSR when OVF=1, then write with 0 to OVF, as stated above. When WOVI is masked and OVF flag is poling, if contention between OVF flag set and TCSR read is occurred, OVF=1 is read but OVF can not be cleared by writing with 0 to OVF. In this case, reading TCSR when OVF=1 two times meet the requirements of OVF clear condition. Please read TCSR when OVF=1 two times before writing with 0 to OVF. LOOP BTST.B BEQ MOV.B MOV.W MOV.W #7,@TCSR LOOP @TCSR,R0L #H'A521,R0 R0,@TCSR ; ; ; ; ; OVF flag read if OVF=1, exit from loop OVF=1 read again OVF flag clear : 407 408 Section 15 Serial Communication Interface (SCI, IrDA) 15.1 Overview The H8S/2169 or H8S/2149 is equipped with a 3-channel serial communication interface (SCI). The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). One of the three SCI channels can transmit and receive IrDA communication waveforms based on IrDA specification version 1.0. 15.1.1 Features SCI features are listed below. • Choice of asynchronous or synchronous serial communication mode Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) A multiprocessor communication function is provided that enables serial data communication with a number of processors Choice of 12 serial data transfer formats Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Multiprocessor bit: Receive error detection: Break detection: Even, odd, or none 1 or 0 Parity, overrun, and framing errors Break can be detected by reading the RxD pin level directly in case of a framing error Synchronous mode Serial data communication is synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function One serial data transfer format Data length: 8 bits Receive error detection: Overrun errors detected 409 • Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data • LSB-first or MSB-first transfer can be selected This selection can be made regardless of the communication mode (with the exception of 7bit data transfer in asynchronous mode)* Note: * LSB-first transfer is used in the examples in this section. • Built-in baud rate generator allows any bit rate to be selected • Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin • Capability of transmit and receive clock output The P86/SCK and P42/SCK2 pins are CMOS type outputs The P52/SCK0 pin is an NMOS push-pull type output (When using the P52/SCK pin as an output, an external pull-up resistor must be connected in order to output high level) • Four interrupt sources Four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive error) that can issue requests independently The transmit-data-empty interrupt and receive-data-full interrupt can activate the data transfer controller (DTC) to execute data transfer 410 15.1.2 Block Diagram Bus interface Figure 15.1 shows a block diagram of the SCI. Module data bus RDR RxD TxD RSR TDR TSR BRR ø Baud rate generator Transmission/ reception control Parity generation Parity check SCK Legend: RSR: RDR: TSR: TDR: SMR: SCR: SSR: SCMR: BRR: SCMR SSR SCR SMR Internal data bus ø/4 ø/16 ø/64 Clock External clock TEI TXI RXI ERI Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Serial interface mode register Bit rate register Figure 15.1 Block Diagram of SCI 411 15.1.3 Pin Configuration Table 15.1 shows the serial pins used by the SCI. Table 15.1 SCI Pins Channel Pin Name Symbol* I/O Function 0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output Serial clock pin 1 SCK1 I/O SCI1 clock input/output Receive data pin 1 RxD1 Input SCI1 receive data input Transmit data pin 1 TxD1 Output SCI1 transmit data output Serial clock pin 2 SCK2 I/O SCI2 clock input/output Receive data pin 2 RxD2/IrRxD Input SCI2 receive data input (normal/IrDA) Transmit data pin 2 TxD2/IrTxD Output SCI2 transmit data output (normal/IrDA) 1 2 Note: * The abbreviations SCK, RxD, and TxD are used in the text, omitting the channel number. 15.1.4 Register Configuration The SCI has the internal registers shown in table 15.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. 412 Table 15.2 SCI Registers Channel Name Abbreviation R/W Initial Value Address* 1 0 Serial mode register 0 SMR0 R/W H'00 H'FFD8* 3 Bit rate register 0 BRR0 R/W H'FF H'FFD9* 3 Serial control register 0 SCR0 R/W H'00 H'FFDA Transmit data register 0 TDR0 R/W H'FF H'FFDB H'84 H'FFDC 1 2 Common 2 Serial status register 0 SSR0 R/(W)* Receive data register 0 RDR0 R H'00 H'FFDD Serial interface mode register 0 SCMR0 R/W H'F2 H'FFDE* 3 Serial mode register 1 SMR1 R/W H'00 H'FF88* 3 Bit rate register 1 BRR1 R/W H'FF H'FF89* 3 Serial control register 1 SCR1 R/W H'00 H'FF8A Transmit data register 1 TDR1 R/W H'FF H'FF8B H'84 H'FF8C 2 Serial status register 1 SSR1 R/(W)* Receive data register 1 RDR1 R H'00 H'FF8D Serial interface mode register 1 SCMR1 R/W H'F2 H'FF8E* 3 Serial mode register 2 SMR2 R/W H'00 H'FFA0* 3 Bit rate register 2 BRR2 R/W H'FF H'FFA1* 3 Serial control register 2 SCR2 R/W H'00 H'FFA2 Transmit data register 2 TDR2 R/W H'FF H'FFA3 H'84 H'FFA4 2 Serial status register 2 SSR2 R/(W)* Receive data register 2 RDR2 R H'00 H'FFA5 Serial interface mode register 2 SCMR2 R/W H'F2 H'FFA6* 3 Keyboard comparator control register KBCOMP R/W H'00 H'FEE4 Module stop control register MSTPCRH R/W H'3F H'FF86 MSTPCRL R/W H'FF H'FF87 Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, to clear flags. 3. Some serial communication interface registers are assigned to the same addresses as other registers. In this case, register selection is performed by the IICE bit in the serial timer control register (STCR). 413 15.2 Register Descriptions 15.2.1 Receive Shift Register (RSR) Bit 7 6 5 4 3 2 1 0 Read/Write — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 15.2.2 Receive Data Register (RDR) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. 414 15.2.3 Transmit Shift Register (TSR) Bit 7 6 5 4 3 2 1 0 Read/Write — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. 15.2.4 Transmit Data Register (TDR) Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. 415 15.2.5 Serial Mode Register (SMR) Bit 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 0 0 R/W R/W Initial value 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7—Communication Mode (C/A): Selects asynchronous mode or synchronous mode as the SCI operating mode. Bit 7 C/A Description 0 Asynchronous mode 1 Synchronous mode (Initial value) Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR Description 0 8-bit data 1 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and LSB-first/MSBfirst selection is not available. Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, or when a multiprocessor format is used, parity bit addition and checking is not performed, regardless of the PE bit setting. 416 Bit 5 PE Description 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* (Initial value) Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, when parity bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. Bit 4 O/E Description 0 Even parity* 1 1 Odd parity* (Initial value) 2 Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description 0 1 stop bit* 1 1 2 stop bits* (Initial value) 2 Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. 417 In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. For details of the multiprocessor communication function, see section 15.3.3, Multiprocessor Communication Function. Bit 2 MP Description 0 Multiprocessor function disabled 1 Multiprocessor format selected (Initial value) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.8, Bit Rate Register. Bit 1 Bit 0 CKS1 CKS0 Description 0 0 ø clock 1 ø/4 clock 0 ø/16 clock 1 ø/64 clock 1 15.2.6 (Initial value) Serial Control Register (SCR) 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. 418 SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE Description 0 Transmit-data-empty interrupt (TXI) request disabled* 1 Transmit-data-empty interrupt (TXI) request enabled (Initial value) Note: * TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE Description 0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled* (Initial value) 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5 TE Description 0 Transmission disabled* 1 1 Transmission enabled* (Initial value) 2 Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transmission format before setting the TE bit to 1. 419 Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE Description 0 Reception disabled* 1 1 Reception enabled* (Initial value) 2 Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SMR setting must be performed to decide the reception format before setting the RE bit to 1. Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) (Initial value) [Clearing conditions] 1 • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data with MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit-end interrupt (TEI) request generation if there is no valid transmit data in TDR when the MSB is transmitted. 420 Bit 2 TEIE Description 0 Transmit-end interrupt (TEI) request disabled* 1 Transmit-end interrupt (TEI) request enabled* (Initial value) Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of external clock operation (CKE1 = 1). The setting of bits CKE1 and CKE0 must be carried out before the SCI’s operating mode is determined using SMR. For details of clock source selection, see table 15.9 in section 15.3, Operation. Bit 1 Bit 0 CKE1 CKE0 Description 0 0 Asynchronous mode Internal clock/SCK pin functions as I/O port* 1 Synchronous mode Internal clock/SCK pin functions as serial clock output* 1 Asynchronous mode Internal clock/SCK pin functions as clock output* 2 Synchronous mode Internal clock/SCK pin functions as serial clock output Asynchronous mode External clock/SCK pin functions as clock input* 3 Synchronous mode External clock/SCK pin functions as serial clock input Asynchronous mode External clock/SCK pin functions as clock input* 3 Synchronous mode External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. 421 15.2.7 Serial Status Register (SSR) Bit 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 R R/W Initial value 1 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R Note:* Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE 0 1 Description [Clearing conditions] • When 0 is written in TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] (Initial value) • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. 422 Bit 6 RDRF Description 0 [Clearing conditions] (Initial value) • When 0 is written in RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER Description 0 [Clearing condition] (Initial value)*1 When 0 is written in ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1*2 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. 423 Bit 4 FER Description 0 [Clearing condition] (Initial value)*1 When 0 is written in FER after reading FER = 1 1 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER Description 0 [Clearing condition] (Initial value)*1 When 0 is written in PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR* 2 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. 424 Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND Description 0 [Clearing conditions] 1 • When 0 is written in TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] (Initial value) • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Bit 1—Multiprocessor Bit (MPB): When reception is performed using a multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB Description 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received (Initial value)* Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting, and in synchronous mode. Bit 0 MPBT Description 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted (Initial value) 425 15.2.8 Bit Rate Register (BRR) Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 15.3 shows sample BRR settings in asynchronous mode, and table 15.4 shows sample BRR settings in synchronous mode. 426 Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency ø (MHz) ø = 2 MHz ø = 2.097152 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 150 1 103 0.16 1 300 0 207 0.16 600 0 103 1200 0 2400 ø = 2.4576 MHz N Error (%) –0.04 1 174 108 0.21 1 0 217 0.21 0.16 0 108 0.21 51 0.16 0 54 0 25 0.16 0 4800 0 12 0.16 9600 — — 19200 — 31250 38400 ø = 3 MHz N Error (%) –0.26 1 212 0.03 127 0.00 1 155 0.16 0 255 0.00 1 77 0.16 0 127 0.00 0 155 0.16 –0.70 0 63 0.00 0 77 0.16 26 1.14 0 31 0.00 0 38 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34 — 0 6 –2.48 0 7 0.00 0 9 –2.34 — — — — — 0 3 0.00 0 4 –2.34 0 1 0.00 — — — — — — 0 2 0.00 — — — — — — 0 1 0.00 — — — n n Operating Frequency ø (MHz) ø = 3.6864 MHz ø = 4 MHz ø = 4.9152 MHz ø = 5 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 — — — 0 7 0.00 0 7 1.73 31250 — — — 0 3 0.00 0 4 –1.70 0 4 0.00 38400 0 2 0.00 — — — 0 3 0.00 3 1.73 0 427 Operating Frequency ø (MHz) ø = 6 MHz Bit Rate (bits/s) n N Error (%) 110 2 106 150 2 300 ø = 6.144 MHz ø = 7.3728 MHz N Error (%) n N Error (%) –0.44 2 108 0.08 2 130 77 0.16 2 79 0.00 2 1 155 0.16 1 159 0.00 600 1 77 0.16 1 79 1200 0 155 0.16 0 2400 0 77 0.16 4800 0 38 0.16 9600 0 19200 ø = 8 MHz N Error (%) –0.07 2 141 0.03 95 0.00 2 103 0.16 1 191 0.00 1 207 0.16 0.00 1 95 0.00 1 103 0.16 159 0.00 0 191 0.00 0 207 0.16 0 79 0.00 0 95 0.00 0 103 0.16 0 39 0.00 0 47 0.00 0 51 0.16 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 — — — 0 7 0.00 38400 0 4 –2.34 0 4 0.00 0 5 0.00 — — — n n Operating Frequency ø (MHz) ø = 9.8304 MHz ø = 10 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) 110 2 174 –0.26 2 177 –0.25 150 2 127 0.00 2 129 0.16 300 1 255 0.00 2 64 0.16 600 1 127 0.00 1 129 0.16 1200 0 255 0.00 1 64 0.16 2400 0 127 0.00 0 129 0.16 4800 0 63 0.00 0 64 0.16 9600 0 31 0.00 0 32 –1.36 19200 0 15 0.00 0 15 1.73 31250 0 9 –1.70 0 9 0.00 38400 0 7 0.00 0 7 1.73 Note: As far as possible, the setting should be made so that the error is no more than 1% Maximum operating frequency of H8S/2169 and H8S/2149 is 10 MHz. Legend: —: Can be set, but there will be a degree of error. 428 Table 15.4 BRR Settings for Various Bit Rates (Synchronous Mode) Operating Frequency ø (MHz) ø = 2 MHz Bit Rate ø = 4 MHz (bits/s) n N n N 110 3 70 — — 250 2 124 2 500 1 249 1k 1 2.5 k ø = 8 MHz ø = 10 MHz n N n N 249 3 124 — — 2 124 2 249 — — 124 1 249 2 124 — — 0 199 1 99 1 199 1 249 5k 0 99 0 199 1 99 1 124 10 k 0 49 0 99 0 199 0 249 25 k 0 19 0 39 0 79 0 99 50 k 0 9 0 19 0 39 0 49 100 k 0 4 0 9 0 19 0 24 250 k 0 1 0 3 0 7 0 9 500 k 0 0* 0 1 0 3 0 4 0 0* 0 1 0 0* 1M 2.5 M 5M Note: As far as possible, the setting should be made so that the error is no more than 1%. Maximum operating frequency of H8S/2169 and H8S/2149 is 10 MHz. Legend: Blank: Cannot be set. —: Can be set, but there will be a degree of error. *: Continuous transfer is not possible. 429 The BRR setting is found from the following equations. Asynchronous mode: N= φ × 106 – 1 64 × 22n–1 × B Synchronous mode: N= Where B: N: ø: n: φ × 106 – 1 8 × 22n–1 × B Bit rate (bits/s) BRR setting for baud rate generator (0 ≤ N ≤ 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n Clock CKS1 CKS0 0 ø 0 0 1 ø/4 0 1 2 ø/16 1 0 3 ø/64 1 1 The bit rate error in asynchronous mode is found from the following equation: φ × 106 Error (%) = – 1 × 100 2n–1 (N + 1) × B × 64 × 2 430 Table 15.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 15.6 and 15.7 show the maximum bit rates with external clock input. Table 15.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ø (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 Note: Maximum operating frequency of H8S/2169 and H8S/2149 is 10 MHz. 431 Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 Note: Maximum operating frequency of H8S/2169 and H8S/2149 is 10 MHz. Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 Note: Maximum operating frequency of H8S/2169 and H8S/2149 is 10 MHz. 432 15.2.9 Serial Interface Mode Register (SCMR) 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value 1 1 1 1 0 0 1 0 Read/Write — — — — R/W R/W — R/W Bit SCMR is an 8-bit readable/writable register used to select SCI functions. SCMR is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1. Bit 3—Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR Description 0 TDR contents are transmitted LSB-first (Initial value) Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Bit 2—Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in SMR. Bit 2 SINV Description 0 TDR contents are transmitted without modification (Initial value) Receive data is stored in RDR without modification 1 TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Bit 1—Reserved: This bit cannot be modified and is always read as 1. Bit 0—Serial Communication Interface Mode Select (SMIF): Reserved bit. 1 should not be written in this bit. 433 Bit 0 SMIF Description 0 Normal SCI mode 1 Reserved mode 15.2.10 (Initial value) Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When bit MSTP7, MSTP6, or MSTP5 is set to 1, SCI0, SCI1, or SCI2 operation, respectively, stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 24.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Module Stop (MSTP7): Specifies the SCI0 module stop mode. MSTPCRL Bit 7 MSTP7 Description 0 SCI0 module stop mode is cleared 1 SCI0 module stop mode is set (Initial value) Bit 6—Module Stop (MSTP6): Specifies the SCI1 module stop mode. MSTPCRL Bit 6 MSTP6 Description 0 SCI1 module stop mode is cleared 1 SCI1 module stop mode is set 434 (Initial value) Bit 5—Module Stop (MSTP5): Specifies the SCI2 module stop mode. MSTPCRL Bit 5 MSTP5 Description 0 SCI2 module stop mode is cleared 1 SCI2 module stop mode is set 15.2.11 (Initial value) Keyboard Comparator Control Register (KBCOMP) 7 6 5 4 3 2 1 0 IrE IrCKS2 IrCKS1 IrCKS0 KBADE KBCH2 KBCH1 KBCH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit KBCOMP is an 8-bit readable/writable register that selects the functions of SCI2 and the A/D converter. KBCOMP is initialized to H'00 by a reset and in hardware standby mode. Bit 7—IrDA Enable (IrE): Specifies normal SCI operation or IrDA operation for SCI2 input/output. Bit 7 IrE Description 0 The TxD2/IrTxD and RxD2/IrRxD pins function as TxD2 and RxD2 1 The TxD2/IrTxD and RxD2/IrRxD pins function as IrTxD and IrRxD (Initial value) Bits 6 to 4—IrDA Clock Select 2 to 0 (IrCKS2 to IrCKS0): These bits specify the high pulse width in IrTxD output pulse encoding when the IrDA function is enabled. 435 Bit 6 Bit 5 Bit 4 IrCKS2 IrCKS1 IrCKS0 Description 0 0 0 B × 3/16 (3/16 of the bit rate) 1 ø/2 0 ø/4 1 ø/8 0 ø/16 1 ø/32 0 ø/64 1 ø/128 1 1 0 1 (Initial value) Bits 3 to 0—Keyboard Comparator Control: See the description in section 20, A/D converter. 436 15.3 Operation 15.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR as shown in table 15.8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 15.9. Asynchronous Mode • Data length: Choice of 7 or 8 bits • Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) • Detection of framing, parity, and overrun errors, and breaks, during reception • Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the built-in baud rate generator is not used) Synchronous Mode • Transfer format: Fixed 8-bit data • Detection of overrun errors during reception • Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip When external clock is selected: The built-in baud rate generator is not used, and the SCI operates on the input serial clock 437 Table 15.8 SMR Settings and Serial Transfer Format Selection SMR Settings SCI Transfer Format Data Multiprocessor Parity Stop Bit Mode Length Bit Bit Length 0 Asynchronous 8-bit data No No 1 bit 1 mode Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 C/A CHR MP PE STOP 0 0 0 0 1 2 bits 0 Yes 1 1 0 2 bits 0 7-bit data No 1 1 1 1 0 Yes 1 — — 0 Asynchronous — 1 mode (multi- 0 — 1 — — 1 bit 2 bits — — 1 bit 2 bits 1 0 1 bit processor format) 8-bit data Yes No 1 bit 2 bits 7-bit data 1 bit 2 bits Synchronous mode 8-bit data No None Table 15.9 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Setting SCI Transfer Clock Bit 7 Bit 1 Bit 0 C/A CKE1 CKE0 Mode 0 0 0 Asynchronous mode 1 1 0 Clock Source SCK Pin Function Internal SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Internal Outputs serial clock External Inputs serial clock 1 1 0 0 1 1 0 1 438 Synchronous mode 15.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-bycharacter basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data LSB 0 D0 1 MSB D1 D2 D3 D4 D5 Start bit Transmit/receive data 1 bit 7 or 8 bits D6 D7 0/1 1 1 Parity Stop bit(s) bit 1 bit, or none 1 or 2 bits One unit of transfer data (character or frame) Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 439 Data Transfer Format: Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected by settings in SMR. Table 15.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length CHR PE MP STOP 1 0 0 0 0 S 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 — 1 0 S 8-bit data MPB STOP 0 — 1 1 S 8-bit data MPB STOP STOP 1 — 1 0 S 7-bit data MPB STOP 1 — 1 1 S 7-bit data MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit 440 2 3 4 5 6 7 8 9 10 11 12 Clock: Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 15.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.3. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 15.3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. 441 Figure 15.4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR [2] Set value in BRR [3] Wait No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. This is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] <Initialization completed> Figure 15.4 Sample SCI Initialization Flowchart 442 Serial Data Transmission (Asynchronous Mode): Figure 15.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization [1] Start transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1? Yes No Break output? Yes [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, one frame of 1s is output and transmission is enabled. [4] [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit-data-empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 <End> Figure 15.5 Sample Serial Transmission Flowchart 443 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. 444 Figure 15.6 shows an example of the operation for transmission in asynchronous mode. 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) 445 Serial Data Reception (Asynchronous Mode): Figure 15.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error handling and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes handling, ensure that the ORER, PER∨FER∨ORER= 1? PER, and FER flags are all [3] cleared to 0. Reception cannot No Error handling be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be detected by reading the value of [4] Read RDRF flag in SSR the input port corresponding to the RxD pin. No RDRF= 1? [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 <End> [5] [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC is activated by an RXI interrupt and the RDR value is read. Figure 15.7 Sample Serial Reception Data Flowchart 446 [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes No Break? Yes Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 15.7 Sample Serial Reception Data Flowchart (cont) 447 In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in RSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. a. Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR. b. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. c. Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 15.11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. 4. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive-error interrupt (ERI) request is generated. 448 Table 15.11 Receive Errors and Conditions for Occurrence Receive Error Abbreviation Occurrence Condition Data Transfer Overrun error ORER When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to in SSR is set to 1 RDR Framing error FER When the stop bit is 0 Parity error PER When the received data differs Receive data is transferred from the parity (even or odd) set from RSR to RDR in SMR Receive data is transferred from RSR to RDR Figure 15.8 shows an example of the operation for reception in asynchronous mode. 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 0 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ERI interrupt request generated by framing error 1 frame Figure 15.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) 449 15.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 15.9 shows an example of inter-processor communication using a multiprocessor format. Data Transfer Format: There are four data transfer formats. When a multiprocessor format is specified, the parity bit specification is invalid. For details, see table 15.10. Clock: See the section on asynchronous mode. 450 Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmission cycle: receiving station specification (MPB = 0) Data transmission cycle: data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 15.9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Data Transfer Operations Multiprocessor Serial Data Transmission: Figure 15.10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. 451 [1] [1] SCI initialization: Initialization Start transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, one frame of 1s is output and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmitdata-empty interrupt (TXI) request, and data is written to TDR. TEND = 1? Yes No Break output? [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Yes Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 <End> Figure 15.10 Sample Multiprocessor Serial Transmission Flowchart 452 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Multiprocessor bit One multiprocessor bit (MPBT value) is output. d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 453 Figure 15.11 shows an example of SCI operation for transmission using a multiprocessor format. 1 Start bit 0 Multiprocessor Stop bit bit Data D0 D1 D7 0/1 1 Start bit 0 Multiproces- Stop 1 sor bit bit Data D0 D1 D7 0/1 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 15.11 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Multiprocessor Serial Data Reception: Figure 15.12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. 454 Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [2] ID reception cycle: Set the MPIE bit in SCR to 1. Start reception Read MPIE bit in SCR Read ORER and FER flags in SSR [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. Yes FER∨ORER = 1? No Read RDRF flag in SSR [3] No RDRF = 1? Yes [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. Read receive data in RDR No This station's ID? Yes [5] Receive error handling and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error handling, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Read ORER and FER flags in SSR Yes FER∨ORER = 1? No Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR No All data received? [5] Error handling Yes Clear RE bit in SCR to 0 (Continued on next page) <End> Figure 15.12 Sample Multiprocessor Serial Reception Flowchart 455 [5] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 15.12 Sample Multiprocessor Serial Reception Flowchart (cont) 456 Figure 15.13 shows an example of SCI operation for multiprocessor format reception. 1 Start bit 0 Data (ID1) MPB D0 D1 D7 1 Stop bit Start bit 1 0 Data (Data1) MPB D0 D1 D7 0 Stop bit 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine If not this station’s ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not match station’s ID 1 Start bit 0 Data (ID2) MPB D0 D1 D7 1 Stop bit Start bit 1 0 Data (Data2) MPB D0 D1 D7 0 Stop bit 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 ID2 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine Matches this station’s ID, so reception continues, and data is received in RXI interrupt handling routine Data2 MPIE bit set to 1 again (b) Data matches station’s ID Figure 15.13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) 457 15.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.14 shows the general format for synchronous serial communication. One unit of transfer data (character or frame) * * Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don’t care Don’t care Note: * High except in continuous transfer Figure 15.14 Data Format in Synchronous Communication In synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In synchronous serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. 458 Data Transfer Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details on SCI clock source selection, see table 15.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To perform receive operations in units of one character, select an external clock as the clock source. Data Transfer Operations SCI Initialization (Synchronous Mode): Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the settings of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 15.15 shows a sample SCI initialization flowchart. 459 [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Start initialization Clear TE and RE bits in SCR to 0 [2] Set the data transfer format in SMR and SCMR. Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] [3] Write a value corresponding to the bit rate to BRR. This is not necessary if an external clock is used. Set data transfer format in SMR and SCMR [2] Set value in BRR [3] [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Wait No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] <Transfer start> Note: In simultaneous transmit and receive operations, the TE bit and RE bit should both be cleared to 0 or set to 1 simultaneously. Figure 15.15 Sample SCI Initialization Flowchart 460 Serial Data Transmission (Synchronous Mode): Figure 15.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] Initialization Start transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes Read TEND flag in SSR [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit-data-empty interrupt (TXI) request and data is written to TDR. No TEND = 1? Yes Clear TE bit in SCR to 0 <End> Figure 15.16 Sample Serial Transmission Flowchart 461 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). 3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 4. After completion of serial transmission, the SCK pin is held in a constant state. Figure 15.17 shows an example of SCI operation in transmission. Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated TXI interrupt Data written to TDR request generated and TDRE flag cleared to 0 in TXI interrupt handling routine 1 frame Figure 15.17 Example of SCI Operation in Transmission 462 TEI interrupt request generated Serial Data Reception (Synchronous Mode): Figure 15.18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. 463 Initialization [1] Start reception [2] Read ORER flag in SSR Yes [3] ORER= 1? No Error handling (Continued below) Read RDRF flag in SSR [4] No RDRF= 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error handling: If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC is activated by a receive-data-full interrupt (RXI) request and the RDR value is read. <End> [3] Error handling Overrun error handling Clear ORER flag in SSR to 0 <End> Figure 15.18 Sample Serial Reception Flowchart 464 In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in the error check, the operation is as shown in table 15.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. 3. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive-error interrupt (ERI) request is generated. Figure 15.19 shows an example of SCI operation in reception. Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine RXI interrupt request generated ERI interrupt request generated by overrun error 1 frame Figure 15.19 Example of SCI Operation in Reception Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. 465 Initialization [1] SCI initialization: [1] The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Start transmission/reception Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [3] Receive error handling: If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. Read ORER flag in SSR ORER = 1? No Read RDRF flag in SSR Yes [3] Error handling [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [4] No RDRF = 1? Yes [5] Serial transmission/reception Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? [5] Yes Clear TE and RE bits in SCR to 0 <End> Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit-data-empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive-datafull interrupt (RXI) request and the RDR value is read. Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations 466 15.3.5 IrDA Operation Figure 15.21 shows a block diagram of the IrDA function. When the IrDA function is enabled with bit IrE in KBCOMP, the SCI channel 2 TxD2 and RxD2 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to implement infrared transmission/reception conforming to the IrDA specification version 1.0 system. In the IrDA specification version 1.0 system, communication is started at a transfer rate of 9600 bps, and subsequently the transfer rate can be varied as necessary. As the IrDA interface in the H8S/2169 or H8S/2149 does not include a function for varying the transfer rate automatically, the transfer rate setting must be changed by software. SCI2 IrDA TxD2/IrTxD Pulse encoder RxD2/IrRxD Pulse decoder TxD RxD KBCOMP Figure 15.21 Block Diagram of IrDA Function Transmission: In transmission, the output signal (UART frame) from the SCI is converted to an IR frame by the IrDA interface (see figure 15.22). When the serial data is 0, a high-level pulses of 3/16 the bit rate (interval equivalent to the width of one bit) is output (initial value). The high-level pulse can be varied according to the setting of bits IrCKS2 to IrCKS0 in KBCOMP. The high-level pulse width is fixed at a minimum of 1.41 µs, and a maximum of (3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 µs. 467 When the serial data is 1, no pulse is output. UART frame Data Start bit 0 1 0 1 0 0 Stop bit 1 Transmission 1 0 1 Reception IR frame Data Start bit 0 Bit interval 1 0 1 0 0 Stop bit 1 1 0 1 Pulse width is 1.6 µs to 3/16 bit interval Figure 15.22 IrDA Transmit/Receive Operations Reception: In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the SCI. When a high-level pulse is detected, 0 data is output, and if there is no pulse during a one-bit interval, 1 data is output. Note that a pulse shorter than the minimum pulse width of 1.41 µs will be identified as a 0 signal. High-Level Pulse Width Selection: Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and H8S/2169 or H8S/2149 operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. 468 Table 15.12 Bit IrCKS2 to IrCKS0 Settings Bit Rate (bps) (Upper Row) / Bit Interval × 3/16 (µs) (Lower Row) Operating Frequency ø (MHz) 2400 9600 19200 38400 57600 115200 78.13 19.53 9.77 4.88 3.26 1.63 2 010 010 010 010 010 — 2.097152 010 010 010 010 010 — 2.4576 010 010 010 010 010 — 3 011 011 011 011 011 — 3.6864 011 011 011 011 011 011 4.9152 011 011 011 011 011 011 5 011 011 011 011 011 011 6 100 100 100 100 100 100 6.144 100 100 100 100 100 100 7.3728 100 100 100 100 100 100 8 100 100 100 100 100 100 9.8304 100 100 100 100 100 100 10 100 100 100 100 100 100 Note: Maximum operating frequency of H8S/2169 and H8S/2149 is 10 MHz. Legend: —: An SCI bit rate setting cannot be mode. 469 15.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 15.13 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request. Table 15.13 SCI Interrupt Sources Channel Interrupt Source Description DTC Activation 0 ERI Receive error (ORER, FER, or PER) Not possible RXI Receive data register full (RDRF) Possible TXI Transmit data register empty (TDRE) Possible TEI Transmit end (TEND) Not possible ERI Receive error (ORER, PER, or PER) Not possible RXI Receive data register full (RDRF) Possible TXI Transmit data register empty (TDRE) Possible TEI Transmit end (TEND) Not possible ERI Receive error (ORER, PER, or PER) Not possible RXI Receive data register full (RDRF) Possible TXI Transmit data register empty (TDRE) Possible TEI Transmit end (TEND) Not possible 1 2 Priority* High Low Note: * The table shows the initial state immediately after a reset. Relative channel priorities can be changed by the interrupt controller. The TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt will have priority for acceptance, 470 and the TDRE flag and TEND flag may be cleared. Note that the TEI interrupt will not be accepted in this case. 15.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 15.14. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 15.14 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF ORER FER PER Receive Data Transfer RSR to RDR Receive Errors 1 1 0 0 X Overrun error 0 0 1 0 O Framing error 0 0 0 1 O Parity error 1 1 1 0 X Overrun error + framing error 1 1 0 1 X Overrun error + parity error 0 0 1 1 O Framing error + parity error 1 1 1 1 X Overrun error + framing error + parity error Notes: O: Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR. 471 Break Detection and Processing: When a framing error (FER) is detected, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Sending a Break: The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This feature can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Consequently, DDR and DR for the port corresponding to the TxD pin should first be set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Reception Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the base clock. This is illustrated in figure 15.23. 472 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 15.23 Receive Data Sampling Timing in Asynchronous Mode Thus the receive margin in asynchronous mode is given by equation (1) below. M = 0.5 – Where M: N: D: L: F: 1 D – 0.5 (1 + F) × 100% – (L – 0.5)F – 2N N .......... (1) Receive margin (%) Ratio of bit rate to clock (N = 16) Clock duty (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in equation (1), a receive margin of 46.875% is given by equation (2) below. When D = 0.5 and F = 0, M = 0.5 – 1 × 100% 2 × 16 = 46.875% .......... (2) However, this is only a theoretical value, and a margin of 20% to 30% should be allowed in system design. 473 Restrictions on Use of DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 ø clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 clock cycles after TDR is updated. (Figure 15.24) • When RDR is read by the DTC, be sure to set the activation source to the relevant SCI receivedata-full interrupt (RXI). SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 Note: When operating on an external clock, set t > 4 states. Figure 15.24 Example of Synchronous Transmission by DTC 474 D7 Section 16 I2 C Bus Interface 16.1 Overview A two-channel I2C bus interface is available for the H8S/2169 or H8S/2149. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Each I2C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer data, saving board and connector space. 16.1.1 Features • Selection of addressing format or non-addressing format I2C bus format: addressing format with acknowledge bit, for master/slave operation Serial format: non-addressing format without acknowledge bit, for master operation only • Conforms to Philips I2C bus interface (I2C bus format) • Two ways of setting slave address (I2C bus format) • Start and stop conditions generated automatically in master mode (I2C bus format) • Selection of acknowledge output levels when receiving (I2C bus format) • Automatic loading of acknowledge bit when transmitting (I2C bus format) • Wait function in master mode (I 2C bus format) A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. • Wait function in slave mode (I2C bus format) A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible. • Three interrupt sources Data transfer end (including transmission mode transition with I 2C bus format and address reception after loss of master arbitration) Address match: when any slave address matches or the general call address is received in slave receive mode (I2C bus format) Stop condition detection 475 • Selection of 16 internal clocks (in master mode) • Direct bus drive (with SCL and SDA pins) Two pins—P52/SCL0 and P97/SDA0—(normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected. Two pins—P86/SCL1 and P42/SDA1—(normally CMOS pins) function as NMOS-only outputs when the bus drive function is selected. • Automatic switching from formatless mode to I2C bus format (channel 0 only) Formatless operation (no start/stop conditions, non-addressing mode) in slave mode Operation using a common data pin (SDA) and independent clock pins (VSYNCI, SCL) Automatic switching from formatless mode to I2C bus format on the fall of the SCL pin 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the I2C bus interface. Figure 16.2 shows an example of I/O pin connections to external circuits. Channel 0 I/O pins and channel 1 I/O pins differ in structure, and have different specifications for permissible applied voltages. For details, see section 25, Electrical Characteristics. 476 Formatless dedicated clock (channel 0 only) ø PS ICCR SCL Clock control Noise canceler Bus state decision circuit SDA ICSR Arbitration decision circuit ICDRT Output data control circuit ICDRS Internal data bus ICMR ICDRR Noise canceler Address comparator SAR, SARX Legend: ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register SAR: Slave address register SARX: Slave address register X Prescaler PS: Interrupt generator Interrupt request Figure 16.1 Block Diagram of I2C Bus Interface 477 Vcc VCC SCL SCL SDA SDA SCL in SDA out (Master) SCL in H8S/2149 chip SCL out SCL out SDA in SDA in SDA out SDA out SCL SDA SDA in SCL SDA SCL out SCL in (Slave 1) (Slave 2) Figure 16.2 I2C Bus Interface Connections (Example: H8S/2169 or H8S/2149 Chip as Master) 16.1.3 Input/Output Pins Table 16.1 summarizes the input/output pins used by the I2C bus interface. Table 16.1 I2C Bus Interface Pins Channel Name Abbreviation* I/O Function 0 Serial clock SCL0 I/O IIC0 serial clock input/output Serial data SDA0 I/O IIC0 serial data input/output Formatless serial clock VSYNCI Input IIC0 formatless serial clock input Serial clock SCL1 I/O IIC1 serial clock input/output Serial data SDA1 I/O IIC1 serial data input/output 1 Note: * In the text, the channel subscript is omitted, and only SCL and SDA are used. 478 16.1.4 Register Configuration Table 16.2 summarizes the registers of the I2C bus interface. Table 16.2 Register Configuration Channel Name Abbreviation R/W Initial Value Address* 1 0 I 2C bus control register ICCR0 R/W H'01 H'FFD8 2 ICSR0 R/W H'00 H'FFD9 2 I C bus data register ICDR0 R/W — H'FFDE* 2 I 2C bus mode register ICMR0 R/W H'00 H'FFDF* 2 Slave address register SAR0 R/W H'00 H'FFDF* 2 Second slave address register SARX0 R/W H'01 H'FFDE* 2 I 2C bus control register I C bus status register 1 ICCR1 R/W H'01 H'FF88 2 ICSR1 R/W H'00 H'FF89 2 I C bus data register ICDR1 R/W — H'FF8E* 2 I 2C bus mode register ICMR1 R/W H'00 H'FF8F* 2 Slave address register SAR1 R/W H'00 H'FF8F* 2 Second slave address register SARX1 R/W H'01 H'FF8E* 2 Serial/timer control register STCR R/W H'00 H'FFC3 DDC switch register DDCSWR R/W H'0F H'FEE6 Module stop control register MSTPCRH R/W H'3F H'FF86 MSTPCRL R/W H'FF H'FF87 I C bus status register Common Notes: 1. Lower 16 bits of the address. 2. The register that can be written or read depends on the ICE bit in the I 2C bus control register. The slave address register can be accessed when ICE = 0, and the I2C bus mode register can be accessed when ICE = 1. The I 2C bus interface registers are assigned to the same addresses as other registers. Register selection is performed by means of the IICE bit in the serial/timer control register (STCR). 479 16.2 Register Descriptions 16.2.1 I2C Bus Data Register (ICDR) Bit 7 6 5 4 3 2 1 0 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 Initial value — — — — — — — — Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 • ICDRR Bit ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 Initial value — — — — — — — — Read/Write R R R R R R R R 7 6 5 4 3 2 1 0 • ICDRS Bit ICDRS7 ICDRS6 ICDRR5 ICDRS4 ICDRS3 ICDRS2 ICDRS1 ICDRS0 Initial value — — — — — — — — Read/Write — — — — — — — — 7 6 5 4 3 2 1 0 • ICDRT Bit ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 Initial value — — — — — — — — Read/Write W W W W W W W W — — • TDRE, RDRF (internal flags) Bit TDRE RDRF Initial value 0 0 Read/Write — — 480 ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the three registers are performed automatically in coordination with changes in the bus state, and affect the status of internal flags such as TDRE and RDRF. If IIC is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRT to ICDRS. If IIC is in receive mode and no previous data remains in ICDRR (the RDRF flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRS to ICDRR. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. ICDR is assigned to the same address as SARX, and can be written and read only when the ICE bit is set to 1 in ICCR. The value of ICDR is undefined after a reset. The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the TDRE and RDRF flags affects the status of the interrupt flags. 481 TDRE Description 0 The next transmit data is in ICDR (ICDRT), or transmission cannot be started (Initial value) [Clearing conditions] • • • • When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) When a stop condition is detected in the bus line state after a stop condition is issued with the I 2C bus format or serial format selected When a stop condition is detected with the I 2C bus format selected In receive mode (TRS = 0) (A 0 write to TRS during transfer is valid after reception of a frame containing an acknowledge bit) 1 The next transmit data can be written in ICDR (ICDRT) [Setting conditions] • • • • In transmit mode (TRS = 1), when a start condition is detected in the bus line state after a start condition is issued in master mode with the I 2C bus format or serial format selected At the first transmit mode setting (TRS = 1) (first transmit mode setting only) after I 2C bus mode is switched to formatless mode When data is transferred from ICDRT to ICDRS (Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is empty) When receive mode (TRS = 0) is switched to transmit mode (TRS = 1 ) after detection of a start condition (first transmit mode setting only) RDRF Description 0 The data in ICDR (ICDRR) is invalid (Initial value) [Clearing condition] When ICDR (ICDRR) receive data is read in receive mode 1 The ICDR (ICDRR) receive data can be read [Setting condition] When data is transferred from ICDRS to ICDRR (Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and RDRF = 0) 482 16.2.2 Slave Address Register (SAR) Bit 7 6 5 4 3 2 1 0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SAR is assigned to the same address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR. SAR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0, differing from the addresses of other slave devices connected to the I2C bus. Bit 0—Format Select (FS): Used together with the FSX bit in SARX and the SW bit in DDCSWR to select the communication format. • I2C bus format: addressing format with acknowledge bit • Synchronous serial format: non-addressing format without acknowledge bit, for master mode only • Formatless mode (channel 0 only): non-addressing format with or without acknowledge bit, slave mode only, start/stop conditions not detected The FS bit also specifies whether or not SAR slave address recognition is performed in slave mode. 483 DDCSWR Bit 6 SAR Bit 0 SARX Bit 0 SW FS FSX Operating Mode 0 0 0 I 2C bus format • 1 I C bus format • • 1 (Initial value) SAR slave address recognized SARX slave address ignored I 2C bus format 0 • • 1 SAR slave address ignored SARX slave address recognized Synchronous serial format • 1 SAR and SARX slave addresses recognized 2 SAR and SARX slave addresses ignored 0 0 Formatless mode (start/stop conditions not detected) 0 1 • 1 0 1 1 Acknowledge bit used Formatless mode* (start/stop conditions not detected) • No acknowledge bit Note: * Do not set this mode when automatic switching to the I 2C bus format is performed by means of the DDCSWR setting. 16.2.3 Second Slave Address Register (SARX) Bit 7 6 5 4 3 2 1 0 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX Initial value 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SARX is an 8-bit readable/writable register that stores the second slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SARX is assigned to the same address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR. SARX is initialized to H'01 by a reset and in hardware standby mode. Bits 7 to 1—Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to SVAX0, differing from the addresses of other slave devices connected to the I2C bus. 484 Bit 0—Format Select X (FSX): Used together with the FS bit in SAR and the SW bit in DDCSWR to select the communication format. • I2C bus format: addressing format with acknowledge bit • Synchronous serial format: non-addressing format without acknowledge bit, for master mode only • Formatless mode: non-addressing format with or without acknowledge bit, slave mode only, start/stop conditions not detected The FSX bit also specifies whether or not SARX slave address recognition is performed in slave mode. For details, see the description of the FS bit in SAR. 16.2.4 I2C Bus Mode Register (ICMR) Bit 7 6 5 4 3 2 1 0 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and read only when the ICE bit is set to 1 in ICCR. ICMR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or LSB-first. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. Do not set this bit to 1 when the I 2C bus format is used. Bit 7 MLS Description 0 MSB-first 1 LSB-first (Initial value) 485 Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the I2C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the WAIT setting. The setting of this bit is invalid in slave mode. Bit 6 WAIT Description 0 Data and acknowledge bits transferred consecutively 1 Wait inserted between data and acknowledge bits 486 (Initial value) Bits 5 to 3—Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel 1) or IICX0 (channel 0) bit in the STCR register, select the serial clock frequency in master mode. They should be set according to the required transfer rate. STCR Bit 5 or 6 Bit 5 Bit 4 Bit 3 IICX CKS2 CKS1 CKS0 Clock ø= 5 MHz ø= 8 MHz ø= 10 MHz 0 0 0 0 ø/28 179 kHz 286 kHz 357 kHz 1 ø/40 125 kHz 200 kHz 250 kHz 0 ø/48 104 kHz 167 kHz 208 kHz 1 ø/64 78.1 kHz 125 kHz 156 kHz 0 ø/80 62.5 kHz 100 kHz 125 kHz 1 ø/100 50.0 kHz 80.0 kHz 100 kHz 0 ø/112 44.6 kHz 71.4 kHz 89.3 kHz 1 ø/128 39.1 kHz 62.5 kHz 78.1 kHz 0 ø/56 89.3 kHz 143 kHz 179 kHz 1 ø/80 62.5 kHz 100 kHz 125 kHz 0 ø/96 52.1 kHz 83.3 kHz 104 kHz 1 ø/128 39.1 kHz 62.5 kHz 78.1 kHz 0 ø/160 31.3 kHz 50.0 kHz 62.5 kHz 1 ø/200 25.0 kHz 40.0 kHz 50.0 kHz 0 ø/224 22.3 kHz 35.7 kHz 44.6 kHz 1 ø/256 19.5 kHz 31.3 kHz 39.1 kHz 1 1 0 1 1 0 0 1 1 0 1 Transfer Rate Note: Maximum operating frequency of H8S/2169 and H8S/2149 is 10 MHz. 487 Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be transferred next. With the I 2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 by a reset and when a start condition is detected. The value returns to 000 at the end of a data transfer, including the acknowledge bit. Bit 2 Bit 1 Bit 0 BC2 BC1 BC0 Synchronous Serial Format I 2C Bus Format 0 0 0 8 9 1 1 2 0 2 3 1 3 4 0 4 5 1 5 6 0 6 7 1 7 8 1 1 0 1 16.2.5 Bits/Frame (Initial value) I2C Bus Control Register (ICCR) Bit 7 6 5 4 3 2 1 0 ICE IEIC MST TRS ACKE BBSY IRIC SCP Initial value 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/(W)* W Note: * Only 0 can be written, to clear the flag. ICCR is an 8-bit readable/writable register that enables or disables the I2C bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or disables acknowledgement, confirms the I2C bus interface bus status, issues start/stop conditions, and performs interrupt flag confirmation. ICCR is initialized to H'01 by a reset and in hardware standby mode. 488 Bit 7—I2C Bus Interface Enable (ICE): Selects whether or not the I2C bus interface is to be used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer operations are enabled. When ICE is cleared to 0, the I2C bus interface module is disabled and the internal state is cleared. The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can be accessed when ICE is 1. Bit 7 ICE Description 0 I 2C bus interface module disabled, with SCL and SDA signal pins set to port function (Initial value) I 2C bus interface module internal state initialized SAR and SARX can be accessed 1 I 2C bus interface module enabled for transfer operations (pins SCL and SCA are driving the bus) ICMR and ICDR can be accessed Bit 6—I2C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I2C bus interface to the CPU. Bit 6 IEIC Description 0 Interrupts disabled 1 Interrupts enabled (Initial value) Bit 5—Master/Slave Select (MST) Bit 4—Transmit/Receive Select (TRS) MST selects whether the I2C bus interface operates in master mode or slave mode. TRS selects whether the I2C bus interface operates in transmit mode or receive mode. In master mode with the I2C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. In slave receive mode with the addressing format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to the R/W bit in the first frame after a start condition. Modification of the TRS bit during transfer is deferred until transfer of the frame containing the acknowledge bit is completed, and the changeover is made after completion of the transfer. MST and TRS select the operating mode as follows. 489 Bit 5 Bit 4 MST TRS Operating Mode 0 0 Slave receive mode 1 Slave transmit mode 0 Master receive mode 1 Master transmit mode 1 (Initial value) Bit 5 MST Description 0 Slave mode (Initial value) [Clearing conditions] 1. When 0 is written by software 2. When bus arbitration is lost after transmission is started in I 2C bus format master mode 1 Master mode [Setting conditions] 1. When 1 is written by software (in cases other than clearing condition 2) 2. When 1 is written in MST after reading MST = 0 (in case of clearing condition 2) Bit 4 TRS Description 0 Receive mode (Initial value) [Clearing conditions] 1. When 0 is written by software (in cases other than setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (in case of clearing condition 3) 3. When bus arbitration is lost after transmission is started in I 2C bus format master mode 4. When the SW bit in DDCSWR changes from 1 to 0 1 Transmit mode [Setting conditions] 1. When 1 is written by software (in cases other than clearing conditions 3 and 4) 2. When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3 and 4) 3. When a 1 is received as the R/W bit of the first frame in I2C bus format slave mode 490 Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the acknowledge bit returned from the receiving device when using the I2C bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0. In the H8S/2169 or H8S/2149, the DTC can be used to perform continuous transfer. The DTC is activated when the IRTR interrupt flag is set to 1 (IRTR is one of two interrupt flags, the other being IRIC). When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of data transmission, regardless of the value of the acknowledge bit. When the ACKE bit is 1, the TDRE, IRIC, and IRTR flags are set on completion of data transmission when the acknowledge bit is 0, and the IRIC flag alone is set on completion of data transmission when the acknowledge bit is 1. When the DTC is activated, the TDRE, IRIC, and IRTR flags are cleared to 0 after the specified number of data transfers have been executed. Consequently, interrupts are not generated during continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the ACKE bit is set to 1, the DTC is not activated and an interrupt is generated, if enabled. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. Bit 3 ACKE Description 0 The value of the acknowledge bit is ignored, and continuous transfer is performed 1 If the acknowledge bit is 1, continuous transfer is interrupted (Initial value) Bit 2—Bus Busy (BBSY): The BBSY flag can be read to check whether the I2C bus (SCL, SDA) is busy or free. In master mode, this bit is also used to issue start and stop conditions. A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition, clearing BBSY to 0. To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, use a MOV instruction to write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode; the I2C bus interface must be set to master transmit mode before issuing a start condition. MST and TRS should both be set to 1 before writing 1 in BBSY and 0 in SCP. 491 Bit 2 BBSY Description 0 Bus is free (Initial value) [Clearing condition] When a stop condition is detected 1 Bus is busy [Setting condition] When a start condition is detected Bit 1—I2C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I2C bus interface has issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is detected. IRIC is set at different times depending on the FS bit in SAR and the WAIT bit in ICMR. See section 16.3.6, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC. When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. 492 Bit 1 IRIC Description 0 Waiting for transfer, or transfer in progress (Initial value) [Clearing conditions] 1. When 0 is written in IRIC after reading IRIC = 1 2. When ICDR is written or read by the DTC (When the TDRE or RDRF flag is cleared to 0) (This is not always a clearing condition; see the description of DTC operation for details) 1 Interrupt requested [Setting conditions] • I 2C bus format master mode 1. When a start condition is detected in the bus line state after a start condition is issued (when the TDRE flag is set to 1 because of first frame transmission) 2. When a wait is inserted between the data and acknowledge bit when WAIT = 1 3. At the end of data transfer (When a wait is not inserted(WAIT=0), at the rise of the 9th transmit/receive clock pulse, or, when a wait is inserted(WAIT=1), at the fall of the 8th transmit/receive clock pulse) 4. When a slave address is received after bus arbitration is lost (when the AL flag is set to 1) 5. When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) • I 2C bus format slave mode 1. When the slave address (SVA, SVAX) matches (when the AAS and AASX flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) 2. When the general call address is detected (when FS = 0 and the ADZ flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) 3. When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) 4. When a stop condition is detected (when the STOP or ESTP flag is set to 1) • Synchronous serial format, and formatless mode 1. At the end of data transfer (when the TDRE or RDRF flag is set to 1) 2. When a start condition is detected with serial format selected 3. When the SW bit is set to 1 in DDCSWR When any other condition arises in which the TDRE or RDRF flag is set to 1. 493 When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (SVA) or general call address match in I 2C bus format slave mode. Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set. The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous transfer using the DTC. The TDRE or RDRF flag is cleared, however, since the specified number of ICDR reads or writes have been completed. Table 16.3 shows the relationship between the flags and the transfer states. Table 16.3 Flags and Transfer States MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State 1/0 1/0 0 0 0 0 0 0 0 0 0 Idle state (flag clearing required) 1 1 0 0 0 0 0 0 0 0 0 Start condition issuance 1 1 1 0 0 1 0 0 0 0 0 Start condition established 1 1/0 1 0 0 0 0 0 0 0 0/1 Master mode wait 1 1/0 1 0 0 1 0 0 0 0 0/1 Master mode transmit/receive end 0 0 1 0 0 0 1/0 1 1/0 1/0 0 Arbitration lost 0 0 1 0 0 0 0 0 1 0 0 SAR match by first frame in slave mode 0 0 1 0 0 0 0 0 1 1 0 General call address match 0 0 1 0 0 0 1 0 0 0 0 SARX match 0 1/0 1 0 0 0 0 0 0 0 0/1 Slave mode transmit/receive end (except after SARX match) 0 1/0 1 0 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 Slave mode transmit/receive end (after SARX match) 0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 494 Stop condition detected Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. Bit 0 SCP Description 0 Writing 0 issues a start or stop condition, in combination with the BBSY flag 1 Reading always returns a value of 1 (Initial value) Writing is ignored 16.2.6 I2C Bus Status Register (ICSR) Bit 7 6 5 4 3 2 1 0 ESTP STOP IRTR AASX AL AAS ADZ ACKB Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W Note: * Only 0 can be written, to clear the flags. ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control. ICSR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been detected during frame transfer in I2C bus format slave mode. 495 Bit 7 ESTP Description 0 No error stop condition (Initial value) [Clearing conditions] 1. When 0 is written in ESTP after reading ESTP = 1 2. When the IRIC flag is cleared to 0 1 • In I 2C bus format slave mode Error stop condition detected [Setting condition] When a stop condition is detected during frame transfer • In other modes No meaning Bit 6—Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been detected after completion of frame transfer in I2C bus format slave mode. Bit 6 STOP Description 0 No normal stop condition (Initial value) [Clearing conditions] 1. When 0 is written in STOP after reading STOP = 1 2. When the IRIC flag is cleared to 0 1 • In I 2C bus format slave mode Normal stop condition detected [Setting condition] When a stop condition is detected after completion of frame transfer • In other modes No meaning Bit 5—I2C Bus Interface Continuous Transmission/Reception Interrupt Request Flag (IRTR): Indicates that the I2C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically when the IRIC flag is cleared to 0. 496 Bit 5 IRTR Description 0 Waiting for transfer, or transfer in progress (Initial value) [Clearing conditions] 1. When 0 is written in IRTR after reading IRTR = 1 2. When the IRIC flag is cleared to 0 1 Continuous transfer state [Setting condition] • In I 2C bus interface slave mode When the TDRE or RDRF flag is set to 1 when AASX = 1 • In other modes When the TDRE or RDRF flag is set to 1 Bit 4—Second Slave Address Recognition Flag (AASX): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is also cleared automatically when a start condition is detected. Bit 4 AASX 0 Description Second slave address not recognized (Initial value) [Clearing conditions] 1. When 0 is written in AASX after reading AASX = 1 2. When a start condition is detected 3. In master mode 1 Second slave address recognized [Setting condition] When the second slave address is detected in slave receive mode while FSX = 0 Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The I2C bus interface monitors the bus. When two or more master devices attempt to seize the bus at nearly the same time, if the I2C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. 497 AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 3 AL Description 0 Bus arbitration won (Initial value) [Clearing conditions] 1. When ICDR data is written (transmit mode) or read (receive mode) 2. When 0 is written in AL after reading AL = 1 1 Arbitration lost [Setting conditions] 1. If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode 2. If the internal SCL line is high at the fall of SCL in master transmit mode Bit 2—Slave Address Recognition Flag (AAS): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 2 AAS Description 0 Slave address or general call address not recognized (Initial value) [Clearing conditions] 1. When ICDR data is written (transmit mode) or read (receive mode) 2. When 0 is written in AAS after reading AAS = 1 3. In master mode 1 Slave address or general call address recognized [Setting condition] When the slave address or general call address is detected in slave receive mode while FS = 0 498 Bit 1—General Call Address Recognition Flag (ADZ): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 1 ADZ Description 0 General call address not recognized (Initial value) [Clearing conditions] 1. When ICDR data is written (transmit mode) or read (receive mode) 2. When 0 is written in ADZ after reading ADZ = 1 3. In master mode 1 General call address recognized [Setting condition] When the general call address is detected in slave receive mode while FSX = 0 or FS = 0 Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line (returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal software is read. When writing to this bit, acknowledge data that is returned after receiving is rewritten regardless of the TRS value. The data loaded from receiving device is retained, therefore pay attention when using bit-manipulation instructions. Bit 0 ACKB Description 0 Receive mode: 0 is output at acknowledge output timing (Initial value) Transmit mode: Indicates that the receiving device has acknowledged the data (signal is 0) 1 Receive mode: 1 is output at acknowledge output timing Transmit mode: Indicates that the receiving device has not acknowledged the data (signal is 1) 499 16.2.7 Serial/Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 IICS IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls register access, the I2C interface operating mode (when the on-chip IIC option is included), and on-chip flash memory, and selects the TCNT input clock source. For details of functions not related to the I2C bus interface, see section 3.2.4, Serial/Timer Control Register (STCR), and the descriptions of the relevant modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit. STCR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—I2C Extra Buffer Select (IICS): Designates bits 7 to 4 of port A as the same kind of output buffer as SCL and SDA. This bit is used when implementing the I2C interface by software only. Bit 7 IICS Description 0 PA7 to PA4 are normal I/O pins 1 PA7 to PA4 are I/O pins with bus driving capability (Initial value) Bit 6—I2C Transfer Select 1 (IICX1): This bit, together with bits CKS2 to CKS0 in ICMR of IIC1, selects the transfer rate in master mode. For details, see section 16.2.4, I2C Bus Mode Register (ICMR). Bit 5—I2C Transfer Select 0 (IICX0): This bit, together with bits CKS2 to CKS0 in ICMR of IIC0, selects the transfer rate in master mode. For details, see section 16.2.4, I2C Bus Mode Register (ICMR). Bit 4—I2C Master Enable (IICE): Controls CPU access to the I2C bus interface data and control registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR). Bit 4 IICE Description 0 CPU access to I 2C bus interface data and control registers is disabled 1 500 2 CPU access to I C bus interface data and control registers is enabled (Initial value) Bit 3—Flash Memory Control Register Enable (FLSHE): Controls the access of CPU to the flash memory control registers, the power-down mode control registers, and the supporting module control registers. See section 3.2.4, Serial/Timer Control Register (STCR). Bit 2—Reserved: Do not write 1 to this bit. Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits, together with bits CKS2 to CKS0 in TCR, select the clock input to the timer counters (TCNT). For details, see section 12.2.4, Timer Control Register (TCR). 16.2.8 DDC Switch Register (DDCSWR) Bit Initial value Read/Write 7 6 5 4 3 2 1 0 SWE SW IE IF CLR3 CLR2 CLR1 CLR0 0 0 0 0 1 1 1 1 R/W R/(W)*1 W*2 W*2 W*2 W*2 R/W R/W Notes: 1. Only 0 can be written, to clear the flag. 2. Always read as 1. DDCSWR is an 8-bit readable/writable register that controls the IIC channel 0 automatic format switching function and IIC internal latch clearance. DDCSWR is initialized to H'0F by a reset and in hardware standby mode. Bit 7—DDC Mode Switch Enable (SWE): Selects the function for automatically switching IIC channel 0 from formatless mode to the I2C bus format. Bit 7 SWE Description 0 Automatic switching of IIC channel 0 from formatless mode to I 2C bus format is disabled 1 Automatic switching of IIC channel 0 from formatless mode to I 2C bus format is enabled (Initial value) Bit 6—DDC Mode Switch (SW): Selects either formatless mode or the I2C bus format for IIC channel 0. 501 Bit 6 SW Description 0 IIC channel 0 is used with the I 2C bus format (Initial value) [Clearing conditions] 1. When 0 is written by software 2. When a falling edge is detected on the SCL pin when SWE = 1 1 IIC channel 0 is used in formatless mode [Setting condition] When 1 is written in SW after reading SW = 0 Bit 5—DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to the CPU when automatic format switching is executed for IIC channel 0. Bit 5 IE Description 0 Interrupt when automatic format switching is executed is disabled 1 Interrupt when automatic format switching is executed is enabled (Initial value) Bit 4—DDC Mode Switch Interrupt Flag (IF): Flag that indicates an interrupt request to the CPU when automatic format switching is executed for IIC channel 0. Bit 4 IF Description 0 No interrupt is requested when automatic format switching is executed (Initial value) [Clearing condition] When 0 is written in IF after reading IF = 1 1 An interrupt is requested when automatic format switching is executed [Setting condition] When a falling edge is detected on the SCL pin when SWE = 1 Bits 3 to 0—IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initialization of the internal state of IIC0 and IIC1. These bits can only be written to; if read they will always return a value of 1. When a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module(s), and the internal state of the IIC module(s) is initialized. 502 The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. When clearing is required again, all the bits must be written to in accordance with the setting. Bit 3 Bit 2 Bit 1 Bit 0 CLR3 CLR2 CLR1 CLR0 Description 0 0 — — Setting prohibited 1 0 0 Setting prohibited 1 IIC0 internal latch cleared 0 IIC1 internal latch cleared 1 IIC0 and IIC1 internal latches cleared — Invalid setting 1 1 — 16.2.9 — Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. When the MSTP4 or MSTP3 bit is set to 1, operation of the corresponding IIC channel is halted at the end of the bus cycle, and a transition is made to module stop mode. For details, see section 24.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. 503 MSTPCRL Bit 4—Module Stop (MSTP4): Specifies IIC channel 0 module stop mode. MSTPCRL Bit 4 MSTP4 Description 0 IIC channel 0 module stop mode is cleared 1 IIC channel 0 module stop mode is set (Initial value) MSTPCRL Bit 3—Module Stop (MSTP3): Specifies IIC channel 1 module stop mode. MSTPCRL Bit 3 MSTP3 Description 0 IIC channel 1 module stop mode is cleared 1 IIC channel 1 module stop mode is set 16.3 Operation 16.3.1 I2C Bus Data Format (Initial value) The I2C bus interface has serial and I2C bus formats. The I2C bus formats are addressing formats with an acknowledge bit. These are shown in figures 16.3 (a) and (b). The first frame following a start condition always consists of 8 bits. IIC channel 0 only is capable of formatless operation, as shown in figure 16.4. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 16.5. Figure 16.6 shows the I2C bus timing. The symbols used in figures 16.3 to 16.6 are explained in table 16.4. 504 (a) I2C bus format (FS = 0 or FSX = 0) S SLA R/W A DATA A A/A P 1 7 1 1 n 1 1 1 1 transfer bit count (n = 1 to 8) transfer frame count (m ≥ 1) m (b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0) S SLA R/W A DATA A/A S SLA R/W A DATA A/A P 1 7 1 1 n1 1 1 7 1 1 n2 1 1 1 m1 1 m2 transfer bit count (n1 and n2 = 1 to 8) transfer frame count (m1 and m2 ≥ 1) Figure 16.3 I2C Bus Data Formats (I2C Bus Formats) IIC0 only, FS = 0 or FSX = 0 DATA A 8 1 DATA n A A/A 1 1 1 transfer bit count (n = 1 to 8) m transfer frame count (m ≥ 1) Note: This mode applies to the DDC (Display Data Channel) which is a PC monitoring system standard. Figure 16.4 Formatless FS = 1 and FSX = 1 S DATA DATA P 1 8 n 1 1 m transfer bit count (n = 1 to 8) transfer frame count (m ≥ 1) Figure 16.5 I2C Bus Data Format (Serial Format) 505 SDA SCL S 1-7 8 9 1-7 SLA R/W A DATA 8 9 A 1-7 DATA 8 9 A/A P Figure 16.6 I2C Bus Timing Table 16.4 I2C Bus Data Format Symbols Legend S Start condition. The master device drives SDA from high to low while SCL is high SLA Slave address, by which the master device selects a slave device R/W Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 A Acknowledge. The receiving device (the slave in master transmit mode, or the master in master receive mode) drives SDA low to acknowledge a transfer DATA Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or LSB-first format is selected by bit MLS in ICMR P Stop condition. The master device drives SDA from low to high while SCL is high 16.3.2 Master Transmit Operation In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The transmission procedure and operations by which data is sequentially transmitted in synchronization with ICDR write operations, are described below. [1] Set the ICE bit in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX in STCR, according to the operation mode. [2] Read the BBSY flag to confirm that the bus is free. [3] Set the MST and TRS bits to 1 in ICCR to select master transmit mode. [4] Write 1 to BBSY and 0 to SCP. This switches SDA from high to low when SCL is high, and generates the start condition. [5] When the start condition is generated, the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. [6] Write data to ICDR (slave address + R/W) 506 With the I 2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first framedata following the start condition indicates the 7-bit slave address and transmit/receive direction. Then clear the IRIC flag to indicate the end of transfer.Writing to ICDR and clearing of the IRIC flag must be executed continuously, so that no interrupt is inserted. If a period of time that is equal to transfer one byte has elapsed by the time the IRIC flag is cleared, the end of transfer cannot be identified. The master device sequentially sends the transmit clock and the data written to ICDR with the timing shown in figure 16.7. The selected slave device (i.e., the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. [7] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. [8] Read the ACKB bit to confirm that ACKB is 0. When the slave device has not returned an acknowledge signal and ACKB remains 1, execute the transmit end processing described in step [12] and perform transmit operation again. [9] Write the next data to be transmitted in ICDR. To identify the end of data transfer, clear the IRIC flag to 0. As described in step [6] above, writing to ICDR and clearing of the IRIC flag must be executed continuously so that no interrupt is inserted. The next frame is transmitted in synchronization with the internal clock. [10] [11] [12] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. Read the ACKB bit of ICSR. Confirm that the slave device has returned an acknowledge signal and ACKB is 0. When more data is to be transmitted, return to step [9] to execute next transmit operation. If the slave device has not returned an acknowledge signal and ACKB is 1, execute the transmit end processing described in step [12]. Clear the IRIC flag to 0. Write BBSY and CSP of ICCR to 0. By doing so, SDA is changed from low to high while SCL is high and the transmit stop condition is generated. 507 Start condition generation SCL (Master output) 1 2 3 4 5 6 7 SDA (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Slave address SDA (Slave output) 8 Bit 0 R/W 1 2 Bit 7 Bit 6 9 [7] Data 1 A [5] IRIC IRTR ICDR Data 1 Address + R/W Precaution: Data set timing to ICDR Incorrect operation (ICDR writing prohibited) Normal operation User processing [4] Write 1 to BBSY [6] ICDR write and 0 to SCP (start condition issuance) [6] IRIC clear [9] ICDR write [9] IRIC clear Figure 16.7 Example of Master Transmit Mode Operating Timing (MLS = WAIT = 0) 16.3.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The receive procedure and operations by which data is sequentially received in synchronization with ICDR read operations, are described below. [1] Clear the TRS bit of ICCR to 0 and switch from transmit mode to receive mode. Set the WAIT bit to 1 and clear the ACKB bit of ICSR to 0 (acknowledge data setting). [2] When ICDR is read (dummy data read), reception is started and the receive clock is output, and data is received, in synchronization with the internal clock. To indicate the wait, clear the IRIC flag to 0. Reading from ICDR and clearing of the IRIC flag must be executed continuously so that no interrupt is inserted. If a period of time that is equal to transfer one byte has elapsed by the time the IRIC flag is cleared, the end of transfer cannot be identified. [3] The IRIC flag is set to 1 at the fall of the 8th clock of a one-frame reception clock. At this point, if the IEIC bit of ICCR is set to 1, an interrupt request is generated to the CPU. 508 SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared. If the first frame is the final reception frame, execute the end processing as described in [10]. [4] Clear the IRIC flag to 0 to release from the wait state. The master device outputs the 9th receive clock pulse, sets SDA to low, and returns an acknowledge signal. [5] When one frame of data has been transmitted, the IRIC and IRTR flags are set to 1 at the rise of the 9th transmit clock pulse. The master device continues to output the receive clock for the next receive data. [6] Read the ICDR receive data. [7] Clear the IRIC flag to indicate the next wait. From clearing of the IRIC flag to completion of data transmission as described in steps [5], [6], and [7], must be performed within the time taken to transfer one byte because releasing of the wait state as described in step [4](or[9]). [8] The IRIC flag is set to 1 at the fall of the 8th receive clock pulse. SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared. If this frame is the final reception frame, execute the end processing as described in [10]. [9] Clear the IRIC flag to 0 to release from the wait state. The master device outputs the 9th reception clock pulse, sets SDA to low, and returns an acknowledge signal. By repeating steps [5] to [9] above, more data can be received. [10] Set the ACKB bit of ICSR to 1 and set the acknowledge data for the final reception. Set the TRS bit of ICCR to 1 to change receive mode to transmit mode. [11] Clear the IRIC flag to release from the wait state. [12] When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th reception clock pulse. [13] Clear the WAIT bit of ICMR to 0 to cancel wait mode. Read the ICDR receive data and clear the IRIC flag to 0. Clear the IRIC flag only when WAIT = 0. (If the stop-condition generation command is executed after clearing the IRIC flag to 0 and then clearing the WAIT bit to 0, the SDA line is fixed low and the stop condition cannot be generated.) [14] Write 0 to BBSY and SCP. This changes SDA from low to high when SCL is high, and generates the stop condition. 509 Master transmit mode Master receive mode SCL (Master output) 9 1 2 3 4 5 6 7 8 SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 [3] Data 1 SDA (Master output) [5] 1 2 3 4 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Data 2 A IRIC IRTR Data 1 ICDR User processing [1] TRS = 0 clear [2] ICDR read WAIT = 1 set (dummy read) ACKB = 0 clear [6] ICDR read (Data 1) [4] IRIC clear [7] IRIC clear [2] IRIC clear Figure 16.8 (1) Example of Master Receive Mode Operating Timing (MLS = ACKB = 0 and WAIT = 1) SCL (Master output) 8 9 SDA Bit 0 (Slave output) Data 2 [8] SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [5] Data 3 A 1 9 Bit 7 [8] [5] 2 Bit 6 Data 4 A IRIC IRTR ICDR User processing Data 1 Data 2 [6] ICDR read (Data 2) [9] IRIC clear Data 3 [6] ICDR read (Data 3) [7] IRIC clear [9] IRIC clear Figure 16.8 (2) Example of Master Receive Mode Operating Timing (MLS = ACKB = 0 and WAIT = 1) 510 [7] IRIC clear 16.3.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. [1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. [2] When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. [3] When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit in ICCR remains cleared to 0, and slave receive operation is performed. [4] At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag has been set to 1, the slave device drives SCL low from the fall of the receive clock until data is read into ICDR. [5] Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. 511 Start condition generation SCL (master output) 1 2 3 4 5 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 9 1 2 Bit 7 Bit 6 SCL (slave output) SDA (master output) Slave address SDA (slave output) Bit 1 Bit 0 R/W Data 1 [4] A RDRF IRIC Interrupt request generation ICDRS Address + R/W ICDRR User processing Address + R/W [5] ICDR read [5] IRIC clearance Figure 16.9 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) 512 SCL (master output) 7 8 Bit 1 Bit 0 9 1 2 3 4 5 6 7 8 9 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCL (slave output) SDA (master output) Data 1 SDA (slave output) Bit 7 [4] Bit 6 Data 2 A [4] A RDRF Interrupt request generation IRIC ICDRS Data 1 ICDRR Data 1 User processing [5] ICDR read Interrupt request generation Data 2 Data 2 [5] IRIC clearance Figure 16.10 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) 16.3.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. [1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. [2] When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. .If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The TDRE internal flag is set to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is written. [3] After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0. The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR 513 flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The slave device sequentially sends the data written into ICDR in accordance with the clock output by the master device at the timing shown in figure 16.10. [4] When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device drives SCL low from the fall of the transmit clock until data is written to ICDR. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed normally. When the TDRE internal flag is 0, the data written into ICDR is transferred to ICDRS, transmission is started, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. [5] To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted into ICDR. The TDRE flag is cleared to 0. Transmit operations can be performed continuously by repeating steps [4] and [5]. To end transmission, write H'FF to ICDR to release SDA on the slave side. When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. 514 Slave receive mode SCL (master output) 8 Slave transmit mode 9 1 2 3 4 5 6 7 8 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 2 SCL (slave output) SDA (slave output) SDA (master output) R/W Bit 7 Data 1 [2] Bit 6 Data 2 A TDRE Interrupt request generation IRIC [3] Interrupt request generation Interrupt request generation Data 1 ICDRT ICDRS Data 2 Data 1 User processing [3] IRIC [3] ICDR write clearance [3] ICDR write Data 2 [5] IRIC clearance [5] ICDR write Figure 16.11 Example of Slave Transmit Mode Operation Timing (MLS = 0) 16.3.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 16.11 shows the IRIC set timing and SCL control. 515 (a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 8 9 1 SDA 7 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) (b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 SDA 8 A 1 IRIC Clear IRIC User processing Clear Write to ICDR (transmit) IRIC or read ICDR (receive) (c) When FS = 1 and FSX = 1 (synchronous serial format) SCL 7 8 1 SDA 7 8 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) Figure 16.12 IRIC Setting Timing and SCL Control 16.3.7 Automatic Switching from Formatless Mode to I2C Bus Format Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC0 operating mode. Switching from formatless mode to the I2C bus format (slave mode) is performed automatically when a falling edge is detected on the SCL pin. The following four preconditions are necessary for this operation: 516 • A common data pin (SDA) for formatless and I2C bus format operation • Separate clock pins for formatless operation (VSYNCI) and I2C bus format operation (SCL) • A fixed 1 level for the SCL pin during formatless operation (the SCL pin does not output a low level) • Settings of bits other than TRS in ICCR that allow I2C bus format operation Automatic switching is performed from formatless mode to the I 2C bus format when the SW bit in DDCSWR is automatically cleared to 0 on detection of a falling edge on the SCL pin. Switching from the I2C bus format to formatless mode is achieved by having software set the SW bit in DDCSWR to 1. In formatless mode, bits (such as MSL and TRS) that control the I 2C bus interface operating mode must not be modified. When switching from the I2C bus format to formatless mode, set the TRS bit to 1 or clear it to 0 according to the transmit data (transmission or reception) in formatless mode, then set the SW bit to 1. After automatic switching from formatless mode to the I2C bus format (slave mode), in order to wait for slave address reception, the TRS bit is automatically cleared to 0. If a falling edge is detected on the SCL pin during formatless operation, I2C bus interface operation is deferred until a stop condition is detected. 517 16.3.8 Operation Using the DTC The I2C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts. Table 16.5 shows some examples of processing using the DTC. These examples assume that the number of transfer data bytes is known in slave mode. Table 16.5 Examples of Operation Using the DTC Master Receive Mode Slave Transmit Mode Slave Receive Mode Slave address + Transmission by DTC (ICDR write) R/W bit transmission/ reception Transmission by CPU (ICDR write) Reception by CPU (ICDR read) Reception by CPU (ICDR read) Dummy data read — Processing by CPU (ICDR read) — — Actual data transmission/ reception Transmission by DTC (ICDR write) Reception by DTC (ICDR read) Transmission by DTC (ICDR write) Reception by DTC (ICDR read) Dummy data (H'FF) write — — Processing by DTC (ICDR write) — Last frame processing Not necessary Reception by CPU (ICDR read) Not necessary Reception by CPU (ICDR read) Transfer request processing after last frame processing 1st time: Clearing by CPU Not necessary 2nd time: End condition issuance by CPU Automatic clearing Not necessary on detection of end condition during transmission of dummy data (H'FF) Setting of number of DTC transfer data frames Reception: Actual Transmission: Actual data count data count + 1 (+1 equivalent to slave address + R/W bits) Reception: Actual Transmission: Actual data count data count + 1 (+1 equivalent to dummy data (H'FF)) Item 518 Master Transmit Mode 16.3.9 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.12 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D C Q Latch D Q Latch Match detector Internal SCL or SDA signal System clock period Sampling clock Figure 16.13 Block Diagram of Noise Canceler 16.3.10 Sample Flowcharts Figures 16.13 to 16.16 show sample flowcharts for using the I2C bus interface in each mode. 519 Start Initialize [1] Initialize [2] Test the status of the SCL and SDA lines. [3] Select master transmit mode. [4] Start condition issuance [5] Wait for a start condition [6] Set transmit data for the first byte (slave address + R/W). (After writing ICDR, clear IRIC immediately) [7] Wait for 1 byte to be transmitted. [8] Test the acknowledge bit, transferred from slave device. Read BBSY in ICCR No BBSY = 0 ? Yes Set MST = 1 and TRS = 1 in ICCR Write BBSY = 1 and SCP = 0 in ICCR Read IRIC in ICCR No IRIC = 1 ? Yes Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1 ? Yes Read ACKB in ICSR ACKB = 0 ? No Yes Transmit mode ? No Master receive mode Yes Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No [9] Set transmit data for the second and subsequent bytes. (After writing ICDR, clear IRIC immediately.) [10] Wait for 1 byte to be transmitted. IRIC = 1 ? Yes Read ACKB in ICSR No [11] Test for end of transfer End of transmission ? or ACKB = 1 ? Yes Clear IRIC in ICCR [12] Stop condition issuance Write BBSY = 0 and SCP = 0 in ICCR End Figure 16.14 Flowchart for Master Transmit Mode (Example) 520 Master receive operation Set TRS = 0 in ICCR [1] Select receive mode. [2] Start receiving. The first read is a dummy read. After reading ICDR, please clear IRIC immediately. [3] Wait for 1 byte to be received (8th clock falling edge) [4] Clear IRIC to trigger the 9th clock. (to end the wait insertion) [5] Wait for 1 byte to be received. (9th clock rising edge) Read ICDR [6] Read the receive data. Clear IRIC in ICCR [7] Clear IRIC. [8] Wait for the next data to be received. (8th clock falling edge) [9] Clear IRIC to trigger the 9th clock. (to end the wait insertion) Set WAIT = 1 in ICMR Set ACKB = 0 in ICSR Read ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1 ? Yes Last receive ? Yes No Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1 ? Yes Read IRIC in ICCR No IRIC = 1 ? Yes Last receive ? Yes No Clear IRIC in ICCR Set ACKB = 1 in ICSR Set TRS = 1 in ICCR Clear IRIC in ICCR [10] Set ACKB = 1 so as to return no acknowledge, or set TRS = 1 so as not to issue extra clock. [11] Clear IRIC to trigger the 9th clock (to end the wait insertion) Read IRIC in ICCR No IRIC = 1 ? [12] Wait for 1 byte to be received. Yes Set WAIT = 0 in ICMR Read ICDR Clear IRIC in ICCR Write BBSY = 0 and SCP = 0 in ICCR [13] Set WAIT = 0. Read ICDR. Clear IRIC. (Note: After setting WAIT = 0, IRIC should be cleared to 0.) [14] Stop condition issuance. End Figure 16.15 Flowchart for Master Receive Mode (Example) 521 Start Initialize Set MST = 0 and TRS = 0 in ICCR [1] Set ACKB = 0 in ICSR Read IRIC in ICCR [2] No IRIC = 1? Yes Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? No General call address processing * Description omitted Yes Read TRS in ICCR No TRS = 0? Slave transmit mode Yes Last receive? No Read ICDR Yes [3] [1] Select slave receive mode. [2] Wait for the first byte to be received (slave address). Clear IRIC in ICCR [3] Start receiving. The first read is a dummy read. Read IRIC in ICCR No [4] Wait for the transfer to end. [4] IRIC = 1? [5] Set acknowledge data for the last receive. [6] Start the last receive. Yes [7] Wait for the transfer to end. Set ACKB = 1 in ICSR [5] Read ICDR [6] [8] Read the last receive data. Clear IRIC in ICCR Read IRIC in ICCR No [7] IRIC = 1? Yes Read ICDR [8] Clear IRIC in ICCR End Figure 16.16 Flowchart for Slave Receive Mode (Example) 522 Slave transmit mode Clear IRIC in ICCR Write transmit data in ICDR [1] [1] Set transmit data for the second and subsequent bytes. [2] Wait for 1 byte to be transmitted. Clear IRIC in ICCR [3] Test for end of transfer. [4] Select slave receive mode. Read IRIC in ICCR No [2] [5] Dummy read (to release the SCL line). IRIC = 1? Yes Read ACKB in ICSR No [3] End of transmission (ACKB = 1)? Yes Set TRS = 0 in ICCR [4] Read ICDR [5] Clear IRIC in ICCR End Figure 16.17 Flowchart for Slave Transmit Mode (Example) 16.3.11 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in the DDCSWR register or clearing ICE bit. For details the setting of bits CLR3 to CLR0, see section 16.2.8, DDC Switch Register (DDCSWR). Scope of Initialization: The initialization executed by this function covers the following items: • TDRE and RDRF internal flags • Transmit/receive sequencer and internal operating clock counter 523 • Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) The following items are not initialized: • Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, STCR) • Internal latches used to retain register read information for setting/clearing flags in the ICMR, ICCR, ICSR, and DDCSWR registers • The value of the ICMR register bit counter (BC2 to BC0) • Generated interrupt sources (interrupt sources transferred to the interrupt controller) Notes on Initialization: • Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. • Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. • When initialization is executed by the DDCSWR register, the write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. Similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. • If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY bit to 0, and wait for two transfer rate clock cycles. 3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 4. Initialize (re-set) the IIC registers. 524 16.4 Usage Notes • In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0. • Either of the following two conditions will start the next transfer. Pay attention to these conditions when reading or writing to ICDR. Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS) Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) • Table 16.6 shows the timing of SCL and SDA output in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. Table 16.6 I2C Bus Timing (SCL and SDA Output) Item Symbol Output Timing Unit Notes SCL output cycle time t SCLO 28t cyc to 256tcyc ns SCL output high pulse width t SCLHO 0.5tSCLO ns Figure 25.27 (reference) SCL output low pulse width t SCLLO 0.5tSCLO ns SDA output bus free time t BUFO 0.5tSCLO – 1t cyc ns Start condition output hold time t STAHO 0.5tSCLO – 1t cyc ns Retransmission start condition output setup time t STASO 1t SCLO ns Stop condition output setup time t STOSO 0.5tSCLO + 2tcyc ns Data output setup time (master) t SDASO 1t SCLLO – 3tcyc ns Data output setup time (slave) Data output hold time 1t SCLL – (6t cyc or 12t cyc *) t SDAHO 3t cyc ns Note: * 6t cyc when IICX is 0, 12tcyc when 1. • SCL and SDA input is sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in I2C bus Timing in section 25, Electrical Characteristics. Note that the I2C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. 525 • The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in the table below. Table 16.7 Permissible SCL Rise Time (tSR) Values Time Indication IICX tcyc Indication 0 7.5tcyc 1 17.5tcyc 2 I C Bus Specification (Max.) ø= 5 MHz ø= 8 MHz ø= 10 MHz 1000 ns 1000 ns 937 ns 750 ns High-speed mode 300 ns 300 ns 300 ns 300 ns Normal mode 1000 ns 1000 ns 1000 ns 300 ns 300 ns 300 ns Normal mode 1000 ns High-speed mode 300 ns Note: The maximum operating frequency for the H8S/2169 and H8S/2149 is 10 MHz. • The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by t cyc, as shown in table 16.6. However, because of the rise and fall times, the I2C bus interface specifications may not be satisfied at the maximum transfer rate. Table 16.8 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. tSCLLO in high-speed mode and t STASO in standard mode fail to satisfy the I 2C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the I 2C bus. 526 Table 16.8 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] Item t SCLHO t SCLLO t BUFO t STAHO t STASO t STOSO t SDASO (master) tcyc Indication tSr/tSf Influence (Max.) I 2C Bus Specification ø = (Min.) 5 MHz ø= ø= 8 MHz 10 MHz –1000 4000 4000 4000 4000 950 950 0.5tSCLO (–tSr) Standard mode High-speed mode –300 600 950 0.5tSCLO (–tSf ) Standard mode 4700 4750 –250 High-speed mode –250 0.5tSCLO – Standard mode –1000 1t cyc ( –tSr ) High-speed mode –300 4750 1 1000* 1 1300 1000* 4700 3800* 1 3875* 1 3900* 1 1300 750* 1 825* 1 850* 1 4000 4550 4625 4650 1000* 0.5tSCLO – 1t cyc (–tSf ) Standard mode High-speed mode –250 600 800 875 900 1t SCLO (–tSr ) Standard mode 4700 9000 9000 9000 High-speed mode –300 600 2200 2200 2200 0.5tSCLO + 2t cyc (–tSr ) Standard mode 4000 4400 4250 4200 High-speed mode –300 600 1350 1200 1150 Standard mode 250 3100 3325 3400 High-speed mode –300 100 400 625 700 250 1300 3 1t SCLLO* – 3t cyc (–tSr ) 3 –250 4750 1 –1000 –1000 –1000 t SDASO (slave) 1t SCLL * – 12t cyc * 2 (–tSr ) Standard mode –1000 2200 High-speed mode –300 100 –1400* –500* t SDAHO 3t cyc Standard mode 0 0 600 375 300 High-speed mode 0 0 600 375 300 1 2500 1 –200* 1 Notes: The maximum operating frequency for the H8S/2169 and H8S/2149 is 10 MHz. 1. Does not meet the I 2C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the I 2C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL – 6t cyc ). 3. Calculated using the I 2C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.). 527 • Note on ICDR Read at End of Master Reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR, and so it will not be possible to read the second byte of data. If it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the bus has been released, then read the ICDR register with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 16.17 (after confirming that the BBSY bit has been cleared to 0 in the ICCR register). Stop condition Start condition (a) SDA Bit 0 A SCL 8 9 Internal clock BBSY bit Master receive mode ICDR reading prohibited Execution of stop condition issuance instruction (0 written to BBSY and SCP) Confirmation of stop condition generation (0 read from BBSY) Start condition issuance Figure 16.18 Points for Attention Concerning Reading of Master Receive Data 528 • Notes on Start Condition Issuance for Retransmission Figure 16.18 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. After start condition issuance is done and determined the start condition, write the transmit data to ICDR, as shown below. IRIC = 1 ? No [1] Yes Clear IRIC in ICSR Start condition issuance ? No Wait for end of 1-byte transfer [2] Determine whether SCL is low [3] Issue restart condition instruction for transmission [4] Detremine whether start condition is generated or not [5] Set transmit data (slave address + R/W) Other processing Yes [2] Read SCL pin SCL = Low ? [1] Note: Program so that processing from [3] to [5] is executed continuously. No Yes Write BBSY = 1, SCP = 0 (ICSR) IRIC = 1 ? [3] No [4] Yes [5] Write transmit data to ICDR start condition (retransmission) 9 SCL SDA ACK bit7 Data output IRIC [3] Start condition instruction issuance [1] IRIC determination [2] Determination of SCL = Low [4] IRIC determination [5] ICDR write (next transmit data) Figure 16.19 Flowchart and Timing of Start Condition Instruction Issuance for Retransmission 529 • Notes on I 2C Bus Interface Stop Condition Instruction Issuance If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, after rising of the 9th SCL clock, issue the stop condition after reading SCL and determining it to below, as shown below. SCL 9th clock VIH High period secured As waveform rise is late, SCL is detected as low SDA Stop condition generation IRIC [1] Determination of SCL = Low [2] Stop condition instruction isuuance Figure 16.20 Timing of Stop Condition Issuance 530 Section 17 Keyboard Buffer Controller 17.1 Overview The H8S/2169 or H8S/2149 has three on-chip keyboard buffer controller channels, designated 0, 1, and 2. The keyboard buffer controller is provided with functions conforming to the PS/2 interface specifications. Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line, providing economical use of connectors, board surface area, etc. Figure 17.1 shows how the keyboard buffer controller is connected. 17.1.1 • • • • Features Conforms to PS/2 interface specifications Direct bus drive (via the KCLK and KD pins) Interrupt sources: on completion of data reception and on detection of clock edge Error detection: parity error and stop bit monitoring Vcc Vcc Keyboard side System side KCLK in KCLK in Clock KCLK out KCLK out KD in KD in Data KD out KD out Keyboard buffer controller (H8S/2169 or H8S/2149 chip) I/F Figure 17.1 Keyboard Buffer Controller Connection 531 17.1.2 Block Diagram Figure 17.2 shows a block diagram of the keyboard buffer controller. Internal data bus KCLK (PS2AC, PS2BC, PS2CC) KDI Control logic KCLKI KBCRH Parity KDO KCLKO KBCRL Register counter value KB interrupt Legend: KD: KCLK: KBBR: KBCRH: KBCRL: KBC data I/O pin KBC clock I/O pin Keyboard data buffer register Keyboard control register H Keyboard control register L Figure 17.2 Block Diagram of Keyboard Buffer Controller 532 Bus interface KD (PS2AD, PS2BD, PS2CD) Module data bus KBBR 17.1.3 Input/Output Pins Table 17.1 lists the input/output pins used by the keyboard buffer controller. Table 17.1 Keyboard Buffer Controller Input/Output Pins Channel Name Abbreviation* I/O Function 0 KBC clock I/O pin (KCLK0) PS2AC I/O KBC clock input/output KBC data I/O pin (KD0) PS2AD I/O KBC data input/output KBC clock I/O pin (KCLK1) PS2BC I/O KBC clock input/output KBC data I/O pin (KD1) PS2BD I/O KBC data input/output KBC clock I/O pin (KCLK2) PS2CC I/O KBC clock input/output KBC data I/O pin (KD2) PS2CD I/O KBC data input/output 1 2 Note: * These are the external I/O pin names. In the text, clock I/O pins are referred to as KCLK and data I/O pins as KD, omitting the channel designations. 17.1.4 Register Configuration Table 17.2 lists the registers of the keyboard buffer controller. Table 17.2 Keyboard Buffer Controller Registers Channel Name Abbreviation R/W Initial Value Address* 1 0 Keyboard control register H KBCRH0 R/(W)*2 H'70 H'FED8 Keyboard control register L KBCRL0 R/W H'70 H'FED9 Keyboard data buffer register KBBR0 R H'00 H'FEDA H'70 H'FEDC H'70 H'FEDD H'00 H'FEDE H'70 H'FEE0 1 2 Common Keyboard control register H KBCRH1 R/(W)* Keyboard control register L KBCRL1 R/W Keyboard data buffer register KBBR1 R 2 2 Keyboard control register H KBCRH2 R/(W)* Keyboard control register L KBCRL2 R/W H'70 H'FEE1 Keyboard data buffer register KBBR2 R H'00 H'FEE2 Module stop control register MSTPCRH R/W H'3F H'FF86 MSTPCRL R/W H'FF H'FF87 Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written in bits 2 and 1, to clear the flags. 533 17.2 Register Descriptions 17.2.1 Keyboard Control Register H (KBCRH) Bit 7 6 5 4 3 2 1 0 KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS Initial value 0 1 1 1 0 0 0 0 Read/Write R/W R R R/W R/W R/(W)* R/(W)* R Note: * Only 0 can be written, to clear the flags. KBCRH is an 8-bit readable/writable register that indicates the operating status of the keyboard buffer controller. KBCRH is initialized to H'70 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bits 6, 5, and 2 to 0 are also initialized when KBIOE is cleared to 0. Bit 7—Keyboard In/Out Enable (KBIOE): Selects whether or not the keyboard buffer controller is used. When KBIOE is set to 1, the keyboard buffer controller is enabled for transmission and reception and the port pins function as KCLK and KD I/O pins. When KBIOE is cleared to 0, the keyboard buffer controller stops functioning and the port pins go to the highimpedance state. Bit 7 KBIOE Description 0 The keyboard buffer controller is non-operational (KCLK and KD signal pins have port functions) (Initial value) 1 The keyboard buffer controller is enabled for transmission and reception (KCLK and KD signal pins are in the bus drive state) Bit 6—Keyboard Clock In (KCLKI): Monitors the KCLK I/O pin. This bit cannot be modified. Bit 6 KCLKI Description 0 KCLK I/O pin is low 1 KCLK I/O pin is high 534 (Initial value) Bit 5—Keyboard Data In (KDI): Monitors the KDI I/O pin. This bit cannot be modified. Bit 5 KDI Description 0 KD I/O pin is low 1 KD I/O pin is high (Initial value) Bit 4—Keyboard Buffer Register Full Select (KBFSEL): Selects whether the KBF bit is used as the keyboard buffer register full flag or as the KCLK fall interrupt flag, When KBFSEL is cleared to 0, the KBE bit in the KBCRL register should be cleared to 0 to disable reception. Bit 4 KBFSEL Description 0 KBF bit is used as KCLK fall interrupt flag 1 KBF bit is used as keyboard buffer register full flag (Initial value) Bit 3—Keyboard Interrupt Enable (KBIE): Enables or disables interrupts from the keyboard buffer controller to the CPU. Bit 3 KBIE Description 0 Interrupt requests are disabled 1 Interrupt requests are enabled (Initial value) Bit 2—Keyboard Buffer Register Full (KBF): Indicates that data reception has been completed and the received data is in the keyboard data buffer register (KBBR). Bit 2 KBF Description 0 [Clearing condition] (Initial value) Read KBF when KBF =1, then write 0 in KBF 1 [Setting condition] • When data has been received normally and has been transferred to KBBR (keyboard buffer register full flag) • When a KCLK falling edge is detected (while KBFSEL = 0) (KCLK interrupt flag) 535 Bit 1—Parity Error (PER): Indicates that an odd parity error has occurred. Bit 1 PER Description 0 [Clearing condition] (Initial value) Read PER when PER =1, then write 0 in PER 1 [Setting condition] When an odd parity error occurs Bit 0—Keyboard Stop (KBS): Indicates the receive data stop bit. Valid only when KBF = 1. Bit 0 KBS Description 0 0 stop bit received 1 1 stop bit received 17.2.2 (Initial value) Keyboard Control Register L (KBCRL) Bit 7 6 5 4 3 2 1 0 KBE KCLKO KDO — RXCR3 RXCR2 Initial value 0 1 1 1 0 0 0 0 Read/Write R/W R/W R/W — R R R R RXCR1 RXCR0 KBCRL is an 8-bit readable/writable register that enables the receive counter count and controls the keyboard buffer controller pin output. KBCRL is initialized to H'70 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7—Keyboard Enable (KBE): Enables or disables loading of receive data into the keyboard data buffer register (KBBR). Bit 7 KBE Description 0 Loading of receive data into KBBR is disabled 1 Loading of receive data into KBBR is enabled 536 (Initial value) Bit 6—Keyboard Clock Out (KCLKO): Controls KBC clock I/O pin output. Bit 6 KCLKO Description 0 Keyboard buffer controller clock I/O pin is low 1 Keyboard buffer controller clock I/O pin is high (Initial value) Bit 5—Keyboard Data Out (KDO): Controls KBC data I/O pin output. Bit 5 KDO Description 0 Keyboard buffer controller data I/O pin is low 1 Keyboard buffer controller data I/O pin is high (Initial value) Bit 4—Reserved: This bit cannot be modified and is always read as 1. Bits 3 to 0—Receive Counter (RXCR3 to RXCR0): These bits indicate the received data bit. Their value is incremented on the fall of KCLK. These bits cannot be modified. The receive counter is initialized to 0000 by a reset and when 0 is written in KBE. Its value returns to 0000 after a stop bit is received. Bit 3 Bit 2 Bit 1 Bit 0 RXCR3 RXCR2 RXCR1 RXCR0 Receive Data Contents 0 0 0 0 — 1 Start bit 0 KB0 1 KB1 0 KB2 1 KB3 0 KB4 1 KB5 0 KB6 1 KB7 0 Parity bit 1 — — — 1 1 0 1 1 0 0 1 1 — (Initial value) 537 17.2.3 Keyboard Data Buffer Register (KBBR) Bit 7 6 5 4 3 2 1 0 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R KBBR is a read-only register that stores receive data. Its value is valid only when KBF = 1. KBBR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode, and when KBIOE is cleared to 0. 17.2.4 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable register, performs module stop mode control. When the MSTP2 bit is set to 1, the keyboard buffer controller halts and enters module stop mode. See section 24.5, Module Stop Mode, for details. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRL Bit 2—Module Stop (MSTP2): Specifies keyboard buffer controller module stop mode. MSTPCRL Bit 2 MSTP2 Description 0 Keyboard buffer controller module stop mode is cleared 1 Keyboard buffer controller module stop mode is set 538 (Initial value) 17.3 Operation 17.3.1 Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on the H8S/2169 or H8S/2149 chip (system) side. KD receives a start bit, 8 data bits (LSBfirst), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. A sample receive processing flowchart is shown in figure 17.3, and the receive timing in figure 17.4. 539 Start [1] Set the KBIOE bit to 1 in KBCRL. Set KBIOE bit [1] Read KBCRH [2] KCLKI and KDI bits both 1? No [2] Read KBCRH, and if the KCLKI and KDI bits are both 1, set the KBE bit (receive enabled state). Keyboard side in data transmission state. [3] Execute receive abort processing. [3] Detect the start bit output on the keyboard side and receive data in synchronization with the fall of KCLK. Yes Set KBE bit Receive enabled state KBF = 1? [4] When a stop bit is received, the keyboard buffer controller drives KCLK low to disable keyboard transmission (automatic I/O inhibit). If the KBIE bit is set to 1 in KBCRH, an interrupt request is sent to the CPU at the same time. No [4] Yes PER = 0? No Yes KBS = 1? No [5] Perform receive data processing. Yes Read KBBR Error handling Receive data processing Clear KBF flag (receive enabled state) [6] [5] [6] Clear the KBF flag to 0 in KBCRL. At the same time, the system automatically drives KCLK high, setting the receive enabled state. The receive operation can be continued by repeating steps [3] to [6]. Figure 17.3 Sample Receive Processing Flowchart 540 Receive processing/ error handling KCLK (pin state) 1 KD (pin state) Start bit 2 0 3 1 9 7 10 Flag cleared 11 Parity bit Stop bit KCLK (input) KCLK (output) Automatic I/O inhibit KB7 to KB0 Previous data KB0 KB1 Receive data PER KBS KBF [1] [2] [3] [4] [5] [6] Figure 17.4 Receive Timing 17.3.2 Transmit Operation In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit processing flowchart is shown in figure 17.5, and the transmit timing in figure 17.6. 541 Start Set KBIOE bit [1] Read KBCRH [2] KCLKI and KDI bits both 1? Yes Set I/O inhibit (KCLKO = 0) [1] Set the KBE bit to 1 in KBCRH, and the KBIOE bit to 1 in KBCRL. [2] Read KBCRH, and if the KCLKI and KDI bits are both 1, write 0 in the KCLKO bit (set I/O inhibit). No 2 [3] Write 0 in the KBE bit (disable KBBR receive operation). KDO remains at 1 [4] Write 0 in the KDO bit (set start bit). KBE = 0 (KBBR reception disabled) [3] [5] Write 1 in the KCLKO bit (clear I/O inhibit). Wait Set start bit (KDO = 0) Set I/O inhibit (KCLKO = 1) [4] KCLKO remains at 0 [5] KDO remains at 0 i=0 [6] Read KBCRH No KCLKI = 0? Yes [6] Read KBCRH, and when KCLKI = 0, set the transmit data in the KDO bit (LSB-first). Next, set the parity bit and stop bit in the KDO bit. [7] After transmitting the stop bit, read KBCRL and confirm that KDI = 0 (receive completed notification from the keyboard). [8] Read KBCRH. Confirm that the KCLKI and KDI bits are both 1. The transmit operation can be continued by repeating steps [2] to [8]. Set transmit data (KDO = D(i)) Read KBCRH KCLKI = 1? No Yes i=i+1 i > 9? No Yes Read KBCRH KCLKI = 1? No i = 0 to 7: Transmit data i = 8: Parity bit i = 9: Stop bit Yes 1 Figure 17.5 Sample Transmit Processing Flowchart 542 1 Read KBCRH No KCLKI = 0? 2 Yes * [7] No KDI = 0? Keyboard side in data transmission state. Execute receive abort processing. Yes [8] Read KBCRH Error handling No KCLK = 1? Yes Transmit end state (KCLK = high, KD = high) To receive operation or transmit operation Note: * To switch to reception after transmission, set KBE to 1 (KBBR receive enable) while KCLKI is low. Figure 17.5 Sample Transmit Processing Flowchart (cont) KCLK (pin state) 1 KD (pin state) KCLK (output) Start bit 2 8 9 10 11 0 1 7 Parity bit Stop bit 0 1 7 Parity bit Stop bit I/O inhibit KD (output) Start bit KCLK (input) Receive completed notification KD (input) [1] [2] [3] [4] [5] [6] [7] [8] Figure 17.6 Transmit Timing 543 17.3.3 Receive Abort The H8S/2169 or H8S/2149 device (system side) can forcibly abort transmission from the device connected to it (keyboard side) in the event of a protocol error, etc. In this case, the system holds the clock low. During reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is an abort request from the system, and data transmission from the keyboard is aborted. Thus the system can abort reception by holding the clock low for a certain period. A sample receive abort processing flowchart is shown in figure 17.7, and the receive abort timing in figure 17.8. 544 [1] Read KBCRL, and if KBF = 1, perform processing 1. Start [2] Read KBCRH, and if the value of bits RXCR3 to RXCR0 is less than B'1001, write 0 in KCLKO to abort reception. If the value of bits RXCR3 to RXCR0 is B'1001 or greater, wait until stop bit reception is completed, then perform receive data processing, and proceed to the next operation. Receive state Read KBCRL No KBF = 0? [1] Yes Read KBCRH Processing 1 No RXCR3 to RXCR0 ≥ B'1001? Yes Disable receive abort requests [3] [2] KCLKO = 0 (receive abort request) Retransmit command transmission (data)? [3] If the value of bits RXCR3 to RXCR0 is B'1001 or greater, the parity bit is being received. With the PS2 interface, a receive abort request following parity bit reception is disabled. Wait until stop bit reception is completed, perform receive data processing and clear the KBF flag, then proceed to the next operation. No Yes KBE = 0 (disable KBBR reception and clear receive counter) KBE = 0 (disable KBBR reception and clear receive counter) Set start bit (KDO = 0) KBE = 1 (enable KB operation) Clear I/O inhibit (KCLKO = 1) Clear I/O inhibit (KCLKO = 1) Transmit data To transmit operation To receive operation Figure 17.7 Sample Receive Abort Processing Flowchart 545 Processing 1 Receive operation ends normally [1] [1] On the system side, drive the KCLK pin low, setting the I/O inhibit state. Receive data processing Clear KBF flag (KCLK = H) Transmit enabled state. If there is transmit data, the data is transmitted. Figure 17.7 Sample Receive Abort Processing Flowchart (cont) Keyboard side monitors clock during receive operation (transmit operation as seen from keyboard), and aborts receive operation during this period. Reception in progress KCLK (pin state) Transmit operation Receive abort request Start bit KD (pin state) KCLK (input) KCLK (output) KD (input) KD (output) Figure 17.8 Receive Abort and Transmit Start (Transmission/Reception Switchover) Timing 546 17.3.4 KCLKI and KDI Read Timing Figure 17.9 shows the KCLKI and KDI read timing. T1 T2 ø* Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note: * The ø clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.9 KCLKI and KDI Read Timing 17.3.5 KCLKO and KDO Write Timing Figure 17.10 shows the KLCKO and KDO write timing and the KCLK and KD pin states. T1 T2 ø* Internal write signal KCLKO, KDO (register) KCLK, KD (pin state) Note: * The ø clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.10 KCLKO and KDO Write Timing 547 17.3.6 KBF Setting Timing and KCLK Control Figure 17.11 shows the KBF setting timing and the KCLK pin states. ø* KCLK (pin) 11th fall Internal KCLK Falling edge signal RXCR3 to RXCR0 H'010 H'000 KBF KCLK (output) Automatic I/O inhibit Note: * The ø clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing 548 17.3.7 Receive Timing Figure 17.12 shows the receive timing. ø* KCLK (pin) KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to RXCR0 Internal KD (KDI) N N+1 ,,, ,,, ,,, ,,, N+2 ,,,, ,,,, ,,,, ,,,, KBBR7 to KBBR0 Note: * The ø clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.12 Receive Counter and KBBR Data Load Timing 549 17.3.8 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRL to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 17.13 shows the setting method and an example of operation. Start Set KBIOE KBE = 0 (KBBR reception disabled) KBFSEL = 0 KBIE = 1 (KCLK falling edge interrupts enabled) KCLK (pin state) KBF bit KCLK pin fall detected? Yes KBF = 1 (interrupt generated) No Interrupt generated Cleared by software Interrupt generated Interrupt handling Clear KBF Note: The KBF setting timing is the same as the timing of KBF setting and KCLK automatic I/O inhibit bit generation in figure 17.11. When the KBF bit is used as the KCLK input fall interrupt flag, the automatic I/O inhibit function does not operate. Figure 17.13 Example of KCLK Input Fall Interrupt Operation 550 17.3.9 Usage Note When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected. If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 17.14 shows the timing of KBIOE setting and KCLK falling edge detection. T1 T2 ø KCLK (pin) Internal KCLK (KCLKI) KBIOE Falling edge signal KBFSEL KBE KBF Figure 17.14 KBIOE Setting and KCLK Falling Edge Detection Timing 551 552 Section 18A Host Interface X-Bus Interface (XBS) 18A.1 Overview The H8S/2169 or H8S/2149 has an on-chip host interface (HIF) that enables connection to the ISA bus (X-BUS) widely used as the internal bus in personal computers. In addition, the H8S/2169 or H8S/2149 has an on-chip LPC interface, a new host interface replacing the ISA bus. In the following text, these two host interfaces (HIFs) are referred to as XBS and LPC, respectively. The HIF:XBS provides a four-channel parallel interface between the chip’s internal CPU and a host processor. The HIF:XBS is available only when bit HI12E is set to 1 in SYSCR2 in single-chip mode. Do not set bit HI12E to 1 when using the HIF:LPC function. 18A.1.1 Features The features of the HIF:XBS are summarized below. The HIF:XBS consists of 8-byte data registers, 4-byte status registers, a 2-byte control register, fast A20 gate logic, and a host interrupt request circuit. Communication is carried out via seven control signals from the host processor (CS1, CS2 or ECS2, CS3, CS4, HA0, IOR, and IOW), six output signals to the host processor (GA20, HIRQ1, HIRQ11, HIRQ12, HIRQ3, and HIRQ4), and an 8-bit bidirectional command/data bus (HDB7 to HDB0). The CS1, CS2 (or ECS2), CS3 and CS4 signals select one of the four interface channels. 553 18A.1.2 Block Diagram Figure 18A.1 shows a block diagram of the HIF:XBS. Internal interrupt signals IBF4 IBF3 IBF2 IBF1 CS1 CS2/ECS2 CS3 CS4 IOR IOW HA0 HDB7 to HDB0 IDR1 ODR1 Control logic STR1 IDR2 ODR2 Fast A20 gate control HICR IDR3 ODR3 STR3 HIRQ1 HIRQ11 HIRQ12 HIRQ3 HIRQ4 GA20 IDR4 ODR4 Port 4, port 8, port B STR4 HIFSD HICR2 Bus interface Internal data bus Legend: IDR1: Input data register 1 IDR2: Input data register 2 ODR1: Output data register 1 ODR2: Output data register 2 STR1: Status register 1 STR2: Status register 2 HICR: Host interface control register 1 IDR3: IDR4: ODR3: ODR4: STR3: STR4: HICR2: Input data register 3 Input data register 4 Output data register 3 Output data register 4 Status register 3 Status register 4 Host interface control register 2 Figure 18A.1 Block Diagram of HIF:XBS 554 Module data bus Host interrupt request Host data bus STR2 18A.1.3 Input and Output Pins Table 18A.1 lists the input and output pins of the HIF:XBS module. Table 18A.1 Host Interface Input/Output Pins Name Abbreviation Port I/O Function I/O read IOR P93 Input Host interface read signal I/O write IOW P94 Input Host interface write signal Chip select 1 CS1 P95 Input Host interface chip select signal for IDR1, ODR1, STR1 Chip select 2* CS2 P81 Input ECS2 P90 Host interface chip select signal for IDR2, ODR2, STR2 Chip select 3 CS3 PB2 Input Host interface chip select signal for IDR3, ODR3, STR3 Chip select 4 CS4 PB3 Input Host interface chip select signal for IDR4, ODR4, STR4 Command/data HA0 P80 Input Host interface address select signal. In host read access, this signal selects the status registers (STR1 to STR4) or data registers (ODR1 to ODR4). In host write access to the data registers (IDR1 to IDR3, and IDTR4), this signal indicates whether the host is writing a command or data. Data bus HDB7 to HDB0 P37 to I/O P30 Host interface data bus Host interrupt 1 HIRQ1 P44 Output Interrupt output 1 to host Host interrupt 11 HIRQ11 P43 Output Interrupt output 11 to host Host interrupt 12 HIRQ12 P45 Output Interrupt output 12 to host Host interrupt 3 HIRQ3 PB0 Output Interrupt output 3 to host Host interrupt 4 HIRQ4 PB1 Output Interrupt output 4 to host Gate A20 GA20 P81 Output A20 gate control signal output HIF shutdown HIFSD P82 Input Host interface shutdown control signal Note: * Selection of CS2 or ECS2 is by means of the CS2E bit in STCR and the FGA20E bit in HICR. HIF:XBS channel 2 and the CS2 pin can be used when CS2E = 1. When CS2E = 1, CS2 is used when FGA20E =0, and ECS2 is used when FGA20E = 1. In this manual, both are referred to as CS2. 555 18A.1.4 Register Configuration Table 18A.2 lists the HIF:XBS registers. HIF:XBS registers HICR, IDR1, IDR2, ODR1, ODR2, STR1, and STR2 can only be accessed when the HIE bit is set to 1 in SYSCR. Table 18A.2 Register Configuration R/W Host Address*4 Host Initial Slave Value Address*3 CS1 CS2 CS3 CS4 HA0 R/W* — H'09 H'FFC4 — — — — — System control register 2 SYSCR2 R/W — H'00 H'FF83 — — — — — Host interface control register 1 HICR R/W — H'F8 H'FFF0 — — — — — Host interface control register 2 HICR2 R/W — H'F8 H'FE80 — — — — — Input data register 1 IDR1 R W — H'FFF4 0 1 1 1 0/1*5 Output data register 1 ODR1 R/W R — H'FFF5 0 1 1 1 0 Name System control register Abbreviation SYSCR Slave 1 2 Status register 1 STR1 R/(W)* R H'00 H'FFF6 0 1 1 1 1 Input data register 2 IDR2 R W — H'FFFC 1 0 1 1 0/1*5 Output data register 2 ODR2 R/W R — H'FFFD 1 0 1 1 0 R H'00 H'FFFE 1 0 1 1 1 W — H'FE84 1 1 0 1 5 0/1* R — H'FE85 1 1 0 1 0 Status register 2 STR2 R/(W)* Input data register 3 IDR3 R Output data register 3 ODR3 R/W 2 2 Status register 3 STR3 R/(W)* R H'00 H'FE86 1 1 0 1 1 Input data register 4 IDR4 R W — H'FE8C 1 1 1 0 5 0/1* Output data register 4 ODR4 R/W R — H'FE8D 1 1 1 0 0 2 Status register 4 STR4 R/(W)* R H'00 H'FE8E 1 1 1 0 1 Module stop control register MSTPCRH R/W — H'3F H'FF86 — — — — — MSTPCRL R/W — H'FF H'FF87 — — — — — Notes: 1. Bits 5 and 3 are read-only bits. 2. The user-defined bits (bits 7 to 4 and 2) are read/write accessible from the slave processor. 3. Address when accessed from the slave processor. The lower 16 bits of the address are shown. 4. Pin inputs used in access from the host processor. 5. The HA0 input discriminates between writing of commands and data. 556 18A.2 Register Descriptions 18A.2.1 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W SYSCR is an 8-bit readable/writable register which controls the chip operations. Of the host interface registers, HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2 can only be accessed when the HIE bit is set to 1. HICR2, IDR3, ODR3, STR3, IDR4, ODR4, and STR4 can be accessed regardless of the setting of the HIE bit. The host interface CS2 and ECS2 pins are controlled by the CS2E bit in SYSCR and the FGA20E bit in HICR. See section 3.2.2, System Control Register (SYSCR), and section 5.2.1, System Control Register (SYSCR), for information on other SYSCR bits. SYSCR is initialized to H'09 by a reset and in hardware standby mode. Bit 7—CS2 Enable Bit (CS2E): Used together with the FGA20E bit in HICR to select the pin that performs the CS2 pin function when the HI12E bit is set to 1. SYSCR Bit 7 HICR Bit 0 CS2E FGA20E Description 0 0 CS2 pin function halted (CS2 fixed high internally) (Initial value) 1 1 0 CS2 pin function selected for P81/CS2 pin 1 CS2 pin function selected for P90/ECS2 pin Bit 1—Host Interface Enable Bit (HIE): Enables or disables CPU access to the host interface registers, keyboard matrix interrupt mask register (KMIMR), keyboard matrix interrupt mask register A (KMIMRA), and port 6 MOS pull-up control register (KMPCR). When enabled, the host interface registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2) can be accessed. Bit 1 HIE Description 0 HIF:XBS register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU access is disabled (Initial value) 1 HIF:XBS register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU access is enabled 557 18A.2.2 System Control Register 2 (SYSCR2) Bit 7 6 5 4 3 2 1 0 KWUL1 KWUL0 P6PUE — SDE CS4E CS3E HI12E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W — R/W R/W R/W R/W SYSCR2 is an 8-bit readable/writable register which controls the chip operations. Host interface functions are enabled or disabled by the HI12E bit in SYSCR2. The number of channels that can be used can be extended to a maximum of four by means of the CS3E bit and CS4E bit. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6—Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level can be set and changed by software. For details see section 8, I/O Ports. Bit 5—Port 6 MOS Input Pull-Up Extra (P6PUE): Controls and selects the current specification for the port 6 MOS input pull-up function connected by means of KMPCR settings. For details see section 8, I/O Ports. Bit 4—Reserved: Do not write 1 to this bit. Bit 3—Shutdown Enable (SDE): Enables or disables the host interface pin shutdown function. When this function is enabled, host interface pin functions can be halted, and the pins placed in the high-impedance state, according to the state of the HIFSD pin. Bit 3 SDE Description 0 Host interface pin shutdown function disabled 1 Host interface pin shutdown function enabled (Initial value) Bit 2—CS4 Enable (CS4E): Enables or disables host interface channel 4 functions in slave mode. When these functions are enabled, channel 4 pins are enabled and processing can be performed for data transfer between the slave and the host processors. Bit 2 CS4E Description 0 Host interface pin channel 4 functions disabled 1 Host interface pin channel 4 functions enabled 558 (Initial value) Bit 1—CS3 Enable (CS3E): Enables or disables host interface channel 3 functions in slave mode. When these functions are enabled, channel 3 pins are enabled and processing can be performed for data transfer between the slave and the host processors. Bit 1 CS3E Description 0 Host interface pin channel 3 functions disabled 1 Host interface pin channel 3 functions enabled (Initial value) Bit 0—Host Interface Enable Bit (HI12E): Enables or disables host interface functions in single-chip mode. When the host interface functions are enabled, processing is performed for data transfer between the slave and the host processors using the pins determined by bits CS2E to CS4E, FGA20E, and SDE. Bit 0 HI12E Description 0 Host interface functions are disabled 1 Host interface functions are enabled (Initial value) 18A.2.3 Host Interface Control Register (HICR) • HICR Bit 7 6 5 4 3 2 — — — — — IBFIE2 Initial value 1 1 1 1 1 0 0 0 Slave Read/Write — — — — — R/W R/W R/W Host Read/Write — — — — — — — — 7 6 5 4 3 2 1 0 1 0 IBFIE1 FGA20E • HICR2 Bit — — — — — IBFIE4 IBFIE3 — Initial value 1 1 1 1 1 0 0 0 Slave Read/Write — — — — — R/W R/W — Host Read/Write — — — — — — — — HICR is an 8-bit readable/writable register which controls host interface channel 1 and 2 interrupts and the fast A20 gate function. HICR2 is an 8-bit readable/writable register which controls host 559 interface channel 3 and 4 interrupts. HICR and HICR2 are initialized to H'F8 by a reset and in hardware standby mode. Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1. HICR Bits 2 and 1—Input Data Register Full Interrupt Enable 2 and 1 (IBFIE2, IBFIE1) HICR2 Bits 2 and 1—Input Data Register Full Interrupt Enable 4 and 3 (IBFIE4, IBFIE3) These bits enable or disable the IBF1, IBF2, IBF3, and IBF4 interrupts to the internal CPU. HICR2 Bit 2 HICR2 Bit 1 HICR Bit 2 HICR Bit 1 IBFIE4 IBFIE3 IBFIE2 IBFIE1 Description — — — 0 Input data register (IDR1) reception completed interrupt request disabled (Initial value) — — — 1 Input data register (IDR1) reception completed interrupt request enabled — — 0 — Input data register (IDR2) reception completed interrupt request disabled (Initial value) — — 1 — Input data register (IDR2) reception completed interrupt request enabled — 0 — — Input data register (IDR3) reception completed interrupt request disabled (Initial value) — 1 — — Input data register (IDR3) reception completed interrupt request enabled 0 — — — Input data register (IDR4) reception completed interrupt request disabled (Initial value) 1 — — — Input data register (IDR4) reception completed interrupt request enabled HICR Bit 0—Fast A20 Gate Function Enable (FGA20E): Enables or disables the fast A20 gate function. When the fast A20 gate is disabled, the normal A20 gate can be implemented byte firmware operation of the P81 output. When the host interface (HIF:XBS) fast A20 gate function is enabled, the DDR bit for P81 must be set to 1. Therefore, the state of the P81/GA20 pin cannot be monitored by reading the DR bit for P81. A fast A20 gate function is also provided in the HIF:LPC. The state of the P81/GA20 pin can be monitored by reading the HIF:LPC’s GA20 bit. 560 HICR Bit 0 P8DDR Bit 1 FGA20E P81DDR Description 0 0 HIF:XBS fast A20 gate function disabled 1 HIF:XBS fast A20 gate function disabled 0 Setting prohibited 1 HIF:XBS fast A20 gate function enabled 1 (Initial value) HICR2 Bit 0—Reserved: Do not set to 1. 18A.2.4 Input Data Register (IDR) Bit 7 6 5 4 3 2 1 0 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 Initial value — — — — — — — — Slave Read/Write R R R R R R R R Host Read/Write W W W W W W W W IDRn (n = 1 to 4) is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the host processor. When CSn (n = 1 to 4) is low, information on the host data bus is written into IDRn at the rising edge of IOW. The HA0 state is also latched into the C/D bit in STRn to indicate whether the written information is a command or data. The initial values of IDR after a reset and in standby mode are undetermined. 18A.2.5 Output Data Register (ODR) Bit 7 6 5 4 3 2 1 0 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 — — — — — — — — Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Host Read/Write R R R R R R R R Initial value ODRn (n = 1 to 4) is an 8-bit readable/writable register to the slave processor, and an 8-bit readonly register to the host processor. The ODRn contents are output on the host data bus when HA0 is low, CSn (n = 1 to 4) is low, and IOR is low. The initial values of ODR after a reset and in standby mode are undetermined. 561 18A.2.6 Status Register (STR) Bit Initial value 7 6 5 4 3 2 1 0 DBU DBU DBU DBU C/D DBU IBF OBF 0 0 0 0 0 0 0 0 Slave Read/Write R/W R/W R/W R/W R R/W R R/(W)* Host Read/Write R R R R R R R R Note: * Only 0 can be written, to clear the flag. STRn (n = 1 to 4) is an 8-bit register that indicates status information during host interface processing. Bits 3, 1, and 0 are read-only bits to both the host and the slave processors. STR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary. Bit 3—Command/Data (C/D): Receives the HA0 input when the host processor writes to IDR, and indicates whether IDR contains data or a command. Bit 3 C/D Description 0 Contents of input data register (IDR) are data 1 Contents of input data register (IDR) are a command (Initial value) Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR. This bit is an internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads IDR. The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 18A.8, Fast A20 Gate Output Signals. Bit 1 IBF Description 0 [Clearing condition] When the slave processor reads IDR 1 [Setting condition] When the host processor writes to IDR 562 (Initial value) Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to 0 when the host processor reads ODR. Bit 0 OBF Description 0 [Clearing condition] When the host processor reads ODR or the slave writes 0 in the OBF bit (Initial value) 1 [Setting condition] When the slave processor writes to ODR Table 18A.3 shows the conditions for setting and clearing the STR flags. Table 18A.3 Set/Clear Timing for STR Flags Flag Setting Condition Clearing Condition C/D Rising edge of host’s write signal (IOW) when HA0 is high Rising edge of host’s write signal (IOW) when HA0 is low IBF* Rising edge of host’s write signal (IOW) when writing to IDR1 Falling edge of slave’s internal read signal (RD) when reading IDR1 OBF Falling edge of slave’s internal write Rising edge of host’s read signal (IOR) when signal (WR) when writing to ODR1 reading ODR1 Note: * The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 18A.8, Fast A20 Gate Output Signals. 563 18A.2.7 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP2 bit is set to 1, the host interface (HIF:XBS) halts and enters module stop mode. See section 24.5, Module Stop Mode, for details. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRL Bit 2—Module Stop (MSTP2): Specifies host interface (HIF:XBS) module stop mode. MSTPCRL Bit 2 MSTP2 Description 0 Host interface (HIF: XBS) module stop mode is cleared 1 Host interface (HIF: XBS) module stop mode is set (Initial value) 18A.3 Operation 18A.3.1 Host Interface Activation The host interface is activated by setting the HI12E bit (bit 0) in SYSCR2 to 1 in single-chip mode. When the host interface is activated, all related I/O ports (data port 3, control ports 8 and 9, and host interrupt request port 4) become dedicated host interface ports. Setting the CS3E bit and CS4E bit to 1 enables the number of host interface channels to be extended to a four, and makes the channel 3 and 4 related I/O port (part of port B for control and host interrupt requests) a dedicated host interface port. Table 18A.4 shows HIF host interface channel selection and pin operation. 564 Table 18A.4 Host Interface Channel Selection and Pin Operation HI12E CS2E CS3E CS4E Operation 0 — — — Host interface functions halted 1 0 0 0 Host interface channel 1 only operating Operation of channels 2 to 4 halted (No operation as CS2 or ECS2, CS3, and CS4 inputs. Pins P43, P81, P90, and PB0 to PB3 operate as I/O ports.) 1 Host interface channel 1 and 4 functions operating Operation of channels 2 and 3 halted (No operation as CS2 or ECS2 and CS3 inputs. Pins P43, P81, P90, PB0, and PB2 operate as I/O ports.) 1 0 Host interface channel 1 and 3 functions operating Operation of channels 2 and 4 halted (No operation as CS2 or ECS2 and CS4 inputs. Pins P43, P81, P90, PB1, and PB3 operate as I/O ports.) 1 Host interface channel 1, 3, and 4 functions operating Operation of channel 2 halted (No operation as CS2 or ECS2 input. Pins P43, P81, and P90 operate as I/O ports.) 1 0 0 Host interface channel 1 and 2 functions operating Operation of channels 3 and 4 halted (No operation as CS3 and CS4 inputs. Pins PB0 to PB3 operate as I/O ports.) 1 Host interface channel 1, 2, and 4 functions operating Operation of channel 3 halted (No operation as CS3 input. Pins PB0 and PB2 operate as I/O ports.) 1 0 Host interface channel 1 to 3 functions operating Operation of channel 4 halted (No operation as CS4 input. Pins PB1 and PB3 operate as I/O ports.) 1 Host interface channel 1 to 4 functions operating For host read/write timing, see section 25.3.4, Timing of On-Chip Supporting Modules. 565 18A.3.2 Control States Table 18A.5 shows host interface operations from the HIF host, and slave operation. Table 18A.5 Host Interface Operations from HIF Host, and Slave Operation Other than CSn CSn IOR IOW HA0 Operation 1 0 0 0 0 Setting prohibited 1 Setting prohibited 0 Data read from output data register n (ODRn) 1 Status read from status register n (STRn) 0 Data written to input data register n (IDRn) 1 Command written to input data register n (IDRn) 0 Idle state 1 Idle state 1 1 0 1 (n = 1 to 4) 18A.3.3 A20 Gate The A20 gate signal can mask address A20 to emulate an addressing mode used by personal computers with an 8086*-family CPU. A regular-speed A20 gate signal can be output under firmware control. Fast A20 gate output is enabled by setting the FGA20E bit (bit 0) to 1 in HICR (H'FFF0). Note: * Intel microprocessor. Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the slave processor receives data, it normally uses an interrupt routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1 command, software copies bit 1 of the data and outputs it at the gate A20 pin. Fast A20 Gate Operation: When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. Bit P81DDR must be set to 1 to assign this pin for output. When the DDR bit for P81 is set to 1, the state of the P81/GA20 pin cannot be monitored by reading the DR bit for P81. The state of the P81/GA20 pin can be monitored by reading the GA20 bit in the HIF:LPC’s HICR2 register. The initial output from this pin will be a logic 1, which is the initial value. Afterward, the host processor can manipulate the output from this pin by sending commands and data. This function is available only when register IDR1 is accessed using CS1. The slave processor decodes the commands input from the host processor. When an H'D1 host command is detected, bit 1 of the data following the host command is output from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the regular processing 566 using interrupts. Table 18A.6 lists the conditions that set and clear GA20 (P81). Figure 18A.2 shows the GA20 output in flowchart form. Table 18A.7 indicates the GA20 output signal values. Table 18A.6 GA20 (P81) Set/Clear Timing Pin Name Setting Condition Clearing Condition GA20 (P81) Rising edge of the host’s write signal (IOW) when bit 1 of the written data is 1 and the data follows an H'D1 host command Rising edge of the host’s write signal (IOW) when bit 1 of the written data is 0 and the data follows an H'D1 host command Also, when bit FGA20E in HICR is cleared to 0 Start Host write No H'D1 command received? Yes Wait for next byte Host write No Data byte? Yes Write bit 1 of data byte to DR bit of P81/GA20 Figure 18A.2 GA20 Output 567 Table 18A.7 Fast A20 Gate Output Signal HA0 Data/Command Internal CPU Interrupt Flag GA20 (P81) 1 0 1 H'D1 command 1 data* 1 H'FF command 0 0 0 Q 1 Q (1) Turn-on sequence 1 0 1 H'D1 command 0 data* 2 H'FF command 0 0 0 Q 0 Q (0) Turn-off sequence 1 0 1/0 H'D1 command 1 data* 1 Command other than H'FF and H'D1 0 0 1 Q 1 Q (1) Turn-on sequence (abbreviated form) 1 0 1/0 H'D1 command 0 data* 2 Command other than H'FF and H'D1 0 0 1 Q 0 Q (0) Turn-off sequence (abbreviated form) 1 1 H'D1 command Command other than H'D1 0 1 Q Q Cancelled sequence 1 1 H'D1 command H'D1 command 0 0 Q Q Retriggered sequence 1 0 1 H'D1 command Any data H'D1 command 0 0 0 Q 1/0 Q(1/0) Consecutively executed sequences Remarks Notes: 1. Arbitrary data with bit 1 set to 1. 2. Arbitrary data with bit 1 cleared to 0. 18A.3.4 Host Interface Pin Shutdown Function Host interface output can be placed in the high-impedance state according to the state of the HIFSD pin. Setting the SDE bit to 1 in the SYSCR2 register when the HI12E bit is set to 1 enables the HIFSD pin. The HIF constantly monitors the HIFSD pin, and when this pin goes low, places the host interface output pins (HIRQ1, HIRQ11, HIRQ12, HIRQ3, HIRQ4, and GA20) in the high-impedance state. At the same time, the host interface input pins (CS1, CS2 or ECS2, CS3, CS4, IOW, IOR, and HA0) are disabled (fixed at the high input state internally) regardless of the pin states, and the signals of the multiplexed functions of these pins (input block) are similarly fixed internally. As a result, the host interface I/O pins (HDB7 to HDB0) also go to the highimpedance state. This state is maintained while the HIFSD pin is low, and when the HIFSD pin returns to the highlevel state, the pins are restored to their normal operation as host interface pins. 568 Table 18A.8 shows the scope of HIF pin shutdown. Table 18A.8 Scope of HIF Pin Shutdown Abbreviation Port Scope of Shutdown in Slave Mode I/O IOR P93 O Input HI12E = 1 IOW P94 O Input HI12E = 1 CS1 P95 O Input HI12E = 1 CS2 P81 ∆ Input HI12E = 1 and CS2E = 1 and FGA20E = 0 ECS2 P90 ∆ Input HI12E = 1 and CS2E = 1 and FGA20E = 1 CS3 PB2 ∆ Input HI12E = 1 and CS3E = 1 CS4 PB3 ∆ Input HI12E = 1 and CS4E = 1 HA0 P80 O Input HI12E = 1 HDB7 to HDB0 P37 to P30 O I/O HI12E = 1 HIRQ11 P43 ∆ Output HI12E = 1 and CS2E = 1 and P43DDR = 1 HIRQ1 P44 ∆ Output HI12E = 1 and P44DDR = 1 HIRQ12 P45 ∆ Output HI12E = 1 and P45DDR = 1 HIRQ3 PB0 ∆ Output HI12E = 1 and CS3E = 1 and PB0DDR = 1 HIRQ4 PB1 ∆ Output HI12E = 1 and CS4E = 1 and PB1DDR = 1 GA20 P81 ∆ Output HI12E = 1 and FGA20E = 1 HIFSD P82 — Input HI12E = 1 and SDE = 1 Selection Conditions Notes: O: Pins shut down by shutdown function The IRQ2/ADTRG input signal is also fixed in the case of P90 shutdown, the TMCI1/HSYNCI signal in the case of P43 shutdown, and the TMRI/CSYNCI in the case of P45 shutdown. ∆: Pins shut down only when the HIF:XBS function is selected by means of a register setting —: Pin not shut down 569 18A.4 Interrupts 18A.4.1 IBF1, IBF2, IBF3, IBF4 The host interface can issue four interrupt requests to the slave processor: IBF1, IBF2, IBF3 and IBF4. They are input buffer full interrupts for input data registers IDR1, IDR2, IDR3 and IDR4 respectively. Each interrupt is enabled when the corresponding enable bit is set. Table 18A.9 Input Buffer Full Interrupts Interrupt Description IBF1 Requested when IBFIE1 is set to 1 and IDR1 is full IBF2 Requested when IBFIE2 is set to 1 and IDR2 is full IBF3 Requested when IBFIE3 is set to 1 and IDR3 is full IBF4 Requested when IBFIE4 is set to 1 and IDR4 is full 18A.4.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 Bits P45DR to P43DR in the port 4 data register (P4DR) and bits PB1ODR and PB0ODR in the port B data register (PBODR) can be used as host interrupt request latches The corresponding bits in P4DR are cleared to 0 by the host processor’s read signal (IOR). If CS1 and HA0 are low, when IOR goes low and the host reads ODR1, HIRQ1 and HIRQ12 are cleared to 0. If CS2 and HA0 are low, when IOR goes low and the host reads ODR2, HIRQ11 is cleared to 0. The corresponding bit in PBODR is cleared to 0 by the host’s read signal (IOR). If CS3 and HA0 are low, when IOR goes low and the host reads ODR3, HIRQ3 is cleared to 0. If CS4 and HA0 are low, when IOR goes low and the host reads ODR4, HIRQ4 is cleared to 0. To generate a host interrupt request, normally on-chip firmware writes 1 in the corresponding bit. In processing the interrupt, the host’s interrupt handling routine reads the output data register (ODR1, ODR2, ODR3, or ODR4) and this clears the host interrupt latch to 0. Table 18A.10 indicates how these bits are set and cleared. Figure 18A.3 shows the processing in flowchart form. 570 Table 18A.10 HIRQ Setting/Clearing Conditions Host Interrupt Signal Setting Condition Clearing Condition HIRQ11 (P43) Internal CPU reads 0 from bit P43DR, then writes 1 Internal CPU writes 0 in bit P43DR, or host reads output data register 2 HIRQ1 (P44) Internal CPU reads 0 from bit P44DR, then writes 1 Internal CPU writes 0 in bit P44DR, or host reads output data register 1 HIRQ12 (P45) Internal CPU reads 0 from bit P45DR, then writes 1 Internal CPU writes 0 in bit P45DR, or host reads output data register 1 HIRQ3 (PB0) Internal CPU reads 0 from bit PB0ODR, then writes 1 Internal CPU writes 0 in bit PB0ODR, or host reads output data register 3 HIRQ4 (PB1) Internal CPU reads 0 from bit PB1ODR, then writes 1 Internal CPU writes 0 in bit PB1ODR, or host reads output data register 4 Slave CPU Master CPU Write to ODR Write 1 to P4DR No HIRQ output high Interrupt initiation HIRQ output low ODR read P4DR = 0? Yes No All bytes transferred? Yes Hardware operations Software operations Figure 18A.3 HIRQ Output Flowchart (Example of Channels 1 and 2) HIRQ Setting/Clearing Contention: If there is contention between a P4DR or PBODR read/write by the CPU and P4DR (HIRQ11, HIRQ1, HIRQ12) or PBODR (HIRQ3, HIRQ4) clearing by the host, clearing by the host is held pending during the P4DR or PBODR read/write by the CPU. P4DR or PBODR clearing is executed after completion of the read/write. 571 18A.5 Usage Note Note the following when using the XBS function. (1) Transmitting/receiving sequence of the transfer between the host and slave processors The host interface provides buffering of asynchronous data from the host and slave processors, but an interface protocol must be followed to implement necessary functions and avoid data contention. For example, if the host and slave processors try to access the same input or output data register simultaneously, the data will be corrupted. Interrupts can be used to design a simple and effective protocol. (2) Data contention on the host interface data bus (HDB) When the HIF function is used and channel 3 or channel 4 is not used, the following condition must be satisfied. (1) The unselected channel pins must be fixed at a high level. (2) Port B must not be read. (3) Through-current at the pins CS1 to CS4 Also, if two or more of pins CS1 to CS4 are driven low simultaneously in attempting IDR or ODR access, signal contention will occur within the chip, and a through-current may result. This usage must therefore be avoided. 572 Section 18B Host Interface LPC Interface (LPC) 18B.1 Overview The H8S/2169 or H8S/2149 has an on-chip host interface (HIF) that can be connected to the ISA bus (X-BUS) widely used as the internal bus in personal computers. In addition, the H8S/2169 or H8S/2149 has an on-chip LPC interface, a new host interface replacing the ISA bus. In the following text, these two host interfaces (HIFs) are referred to as XBS and LPC, respectively. The HIF:LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. Various kinds of cycle are available for the LPC interface, but the chip’s HIF:LPC supports only I/O read cycle and I/O write cycle transfers. The HIF:LPC consists of three register sets comprising data and status registers, plus a control register, fast A20 gate logic, and a host interrupt request circuit. It is also provided with powerdown functions that can control the PCI clock and shut down the host interface. The HIF:LPC ia available only in single-chip mode. 18B.1.1 Features The features of the HIF:LPC are summarized below. • Supports LPC interface I/O read cycles and I/O write cycles Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data. Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME). • Has three register sets comprising data and status registers The basic register set comprises three bytes: an input register (IDR), output register (ODR), and status register (STR). Channels 1 and 2 have fixed I/O addresses of H'60/H'64 and H'62/H'66, respectively, enabling the same functions to be implemented as on HIF:XBS channels 1 and 2. A fast A20 gate function is also provided. The I/O address can be set for channel 3. Sixteen two-way register bytes can be manipulated in addition to the basic register set. • Supports SERIRQ Host interrupt requests are transferred serially on a single signal line (SERIRQ). On channel 1, HIRQ1 and HIRQ12 can be generated. On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated. 573 Operation can be switched between quiet mode and continuous mode. The CLKRUN signal can be manipulated to restart the PCI clock (LCLK). • Power-down functions, interrupts, etc. The LPC module can be shut down by inputting the LPCPD signal. Three pins, PME, LSMI, and LSCI, are provided for general input/output. 18B.1.2 Block Diagram Figure 18B.1 shows a block diagram of the HIF:LPC. Module data bus TWR0MW IDR3 Parallel → serial conversion SERIRQ IDR2 TWR1–15 CLKRUN IDR1 SIRQCR0 SIRQCR1 Cycle detection Serial → parallel conversion LPCPD Control logic LFRAME Address match LAD0– LAD3 LRESET H'0060/64 H'0062/66 Serial ← parallel conversion TWR0SW TWR1–15 PB1 I/O LSCI PB0 I/O LSMI P80 I/O PME LSMIE LSMIB LSMI input LADR3 SYNC output LCLK LSCIE LSCIB LSCI input PMEE PMEB PME input HICR0 ODR3 HICR1 ODR2 HICR2 ODR1 HICR3 GA20 STR3 STR2 STR1 Internal interrupt control Figure 18B.1 Block Diagram of HIF:LPC 574 IBF interrupts (IBFI1, IBFI2, IBFI3) ERR interrupt (ERRI) 18B.1.3 Pin Configuration Table 18B.1 lists the input and output pins of the HIF:LPC module. Table 18B.1 Pin Configuration Name Abbreviation LPC address/ data 3 to 0 LAD3 to LAD0 P33 to P30 Input/ output LPC frame LFRAME P34 Input* 1 Transfer cycle start and forced termination signal LPC reset LRESET P35 Input* 1 LPC interface reset signal LPC clock LCLK P36 Input 33 MHz PCI clock signal P37 Input/ output* 1 Serialized host interrupt request signal, synchronized with LCLK Serialized interrupt SERIRQ request Port I/O Function Serial (4-signal-line) transfer cycle type/address/data signals, synchronized with LCLK (SMI, IRQ1, IRQ6, IRQ9 to IRQ12) 1, 2 General output LSCI general output LSCI PB1 Output* * LSMI general output LSMI PB0 Output* 1, * 2 General output PME general output PME P80 Output* 1, * 2 General output GATE A20 GA20 P81 Output* 1, * 2 A20 gate control signal output LPC clock run CLKRUN P82 Input/ output* 1, * 2 LCLK restart request signal in case of serial host interrupt request LPC power-down LPCPD P83 Input* 1 LPC module shutdown signal Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control input/output function. 2. Only 0 can be output. If 1 is output, the pin goes to the high-impedance state, so an external resistor is necessary to pull the signal up to VCC. 575 18B.1.4 Register Configuration Table 18B.2 lists the HIF:LPC registers. Table 18B.2 Register Configuration R/W Name Abbreviation Slave Host Initial Value Slave Host Address* 3 Address* 4 System control register SYSCR R/W*1 — H'09 H'FFC4 — System control register 2 SYSCR2 R/W — H'00 H'FF83 — Host interface control register 0 HICR0 R/W — H'00 H'FE40 — Host interface control register 1 HICR1 R/W — H'00 H'FE41 — Host interface control register 2 HICR2 R/W — H'00 H'FE42 — Host interface control register 3 HICR3 R — — H'FE43 — LPC channel 3 address register LADR3H R/W — H'00 H'FE34 — LADR3L R/W — H'00 H'FE35 — Input data register 1 IDR1 R W — H'FE38 H'0060 and H'0064 Output data register 1 ODR1 R/W R — H'FE39 H'0060 R H'00 H'FE3A H'0064 W — H'FE3C H'0062 and H'0066 R — H'FE3D H'0062 R H'00 H'FE3E H'0066 Status register 1 STR1 R/(W)* Input data register 2 IDR2 R Output data register 2 ODR2 R/W 2 2 Status register 2 STR2 R/(W)* Input data register 3 IDR3 R W — H'FE30 LADR3* 5 +0 and +4 Output data register 3 ODR3 R/W R — H'FE31 LADR3* 5 +0 Status register 3 STR3 R/(W)*2 R H'00 H'FE32 LADR3* 5 +4 Two-way register 0MW TWR0MW R W — H'FE20 LADR3* 6 +16 /–16 Two-way register 0SW TWR0SW W R — H'FE20 LADR3* 6 +16 /–16 576 Abbreviation Name R/W Slave Host Initial Value Slave Host Address* 3 Address* 4 Two-way registers 1 to 15 TWR1 to TWR15 R/W R/W — H'FE21 to H'FE2F LADR3* 6 +17/–15 to LADR3* 6 +31/–1 SERIRQ control register 0 SIRQCR0 R/W — H'00 H'FE36 — SERIRQ control register 1 SIRQCR1 R/W — H'00 H'FE37 — Module stop control register MSTPCRH R/W — H'3F H'FF86 — MSTPCRL R/W — H'FF H'FF87 — Notes: 1. Bits 5 and 3 are read-only bits. 2. The user-defined bits (channels 1 and 2: bits 7 to 4 and 2; channel 3: bit 2) are read/write accessible from the slave processor. 3. Address when accessed from the slave processor. The lower 16 bits of the address are shown. 4. Address when accessed from the host processor. 5. +0 and +4 address calculation is performed, with bit 0 of LADR3 regarded as B'0. 6. +31 to –16 address calculation is performed, with bits 3 to 0 of LADR3 regarded as B'0000. 18B.2 Register Descriptions 18B.2.1 System Control Registers (SYSCR, SYSCR2) • SYSCR Bit 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W 7 6 5 4 3 2 1 0 KWUL1 KWUL0 P6PUE — SDE CS4E CS3E HI12E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W — R/W R/W R/W R/W • SYSCR2 Bit 577 SYSCR and SYSCR2 are 8-bit readable/writable registers that control the chip operations. The settings of HIF:XBS related bits do not affect the operation of the chip’s HIF:LPC. However, for reasons relating to the configuration of the program development tool (emulator), when the HIF:LPC is used, bit HI12E in SYSCR2 should not be set to 1. For details of the individual bits, see section 18A.2.1, System Control Register (SYSCR), section 18A.2.2, System Control Register 2 (SYSCR2), section 3.2.2, System Control Register (SYSCR), section 5.2.1, System Control Register (SYSCR), and section 8, I/O Ports. SYSCR and SYSCR2 are initialized to H'09 and H'00, respectively, by a reset and in hardware standby mode. 18B.2.2 Host Interface Control Registers 0 and 1 (HICR0, HICR1) • HICR0 Bit 7 6 LPC3E LPC2E 0 0 0 0 Slave Read/Write R/W R/W R/W Host Read/Write — — 7 6 Initial value 5 4 3 2 1 0 PMEE LSMIE LSCIE 0 0 0 0 R/W R/W R/W R/W R/W — — — — — — 5 4 3 2 1 0 PMEB LSMIB LSCIB LPC1E FGA20E SDWNE • HICR1 Bit LPCBSY CLKREQ IRQBSY LRSTB SDWNB Initial value 0 0 0 0 0 0 0 0 Slave Read/Write R R R R/W R/W R/W R/W R/W Host Read/Write — — — — — — — — HICR0 and HICR1 contain control bits that enable or disable host interface functions, control bits that determine pin output and the internal state of the host interface, and status flags that monitor the internal state of the host interface. HICR0 and HICR1 are initialized to H'00 by a reset and in hardware standby mode. 578 HICR0 Bits 7 to 5—LPC Enable 3 to 1 (LPC3E, LPC2E, LPC1E): These bits enable or disable the host interface function in single-chip mode. When the host interface is enabled (at least one of the three bits is set to 1), processing for data transfer between the slave processor and the host processor is performed using pins LAD3 to LAD0, LFRAME, LRESET, LCLK, SERIRQ, CLKRUN, and LPCPD. HICR0 Bit 7 LPC3E Description 0 LPC channel 3 operation is disabled (Initial value) No address (LADR3) matches for IDR3, ODR3, STR3, or TWR0 to TWR15 1 LPC channel 3 operation is enabled HICR0 Bit 6 LPC2E Description 0 LPC channel 2 operation is disabled (Initial value) No address (H'0062, 66) matches for IDR2, ODR2, or STR2 1 LPC channel 2 operation is enabled HICR0 Bit 5 LPC1E Description 0 LPC channel 1 operation is disabled (Initial value) No address (H'0060, 64) matches for IDR1, ODR1, or STR1 1 LPC channel 1 operation is enabled 579 HICR0 Bit 4—Fast A20 Gate Function Enable (FGA20E): Enables or disables the fast A20 gate function. When the fast A20 gate is disabled, the normal A20 gate can be implemented by firmware operation of the P81 output. When the fast A20 gate function is enabled, the DDR bit for P81 must not be set to 1. HICR0 Bit 4 FGA20E Description 0 Fast A20 gate function disabled 1 • Other function of pin P81 is enabled • GA20 output internal state is initialized to 1 (Initial value) Fast A20 gate function enabled • GA20 pin output is open-drain (external V CC pull-up resistor required) HICR0 Bit 2—PME Output Enable (PMEE) HICR1 Bit 2—PME Output Bit (PMEB) These bits control PME output. PME pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC. When the PME output function is used, the DDR bit for P80 must not be set to 1. HICR0 Bit 2 HICR1 Bit 2 PMEE PMEB Description 0 0 PME output disabled, other function of pin P80 is enabled 1 PME output disabled, other function of pin P80 is enabled 0 PME output enabled, PME pin output goes to 0 level 1 PME output enabled, PME pin output is high-impedance 1 580 (Initial value) HICR0 Bit 1—LSMI Output Enable (LSMIE) HICR1 Bit 1—LSMI Output Bit (LSMIB) These bits control LSMI output. LSMI pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC. When the LSMI output function is used, the DDR bit for PB0 must not be set to 1. HICR0 Bit 1 HICR1 Bit 1 LSMIE LSMIB Description 0 0 LSMI output disabled, other function of pin PB0 is enabled 1 LSMI output disabled, other function of pin PB0 is enabled 0 LSMI output enabled, LSMI pin output goes to 0 level 1 LSMI output enabled, LSMI pin output is high-impedance 1 (Initial value) HICR0 Bit 0—LSCI Output Enable (LSCIE) HICR1 Bit 0—LSCI Output Bit (LSCIB) These bits control LSCI output. LSCI pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC. When the LSCI output function is used, the DDR bit for PB1 must not be set to 1. HICR0 Bit 0 HICR1 Bit 0 LSCIE LSCIB Description 0 0 LSCI output disabled, other function of pin PB1 is enabled 1 LSCI output disabled, other function of pin PB1 is enabled 0 LSCI output enabled, LSCI pin output goes to 0 level 1 LSCI output enabled, LSCI pin output is high-impedance 1 (Initial value) 581 HICR1 Bit 7—LPC Busy (LPCBSY): Indicates that the host interface is processing a transfer cycle. HICR1 Bit 7 LPCBSY Description 0 Host interface is in transfer cycle wait state (Initial value) • Bus idle, or transfer cycle not subject to processing is in progress • Cycle type or address indeterminate during transfer cycle [Clearing conditions] 1 • LPC hardware reset or LPC software reset • LPC hardware shutdown or LPC software shutdown • Forced termination (abort) of transfer cycle subject to processing • Normal termination of transfer cycle subject to processing Host interface is performing transfer cycle processing [Setting condition] • Match of cycle type and address HICR1 Bit 6—LCLK Request (CLKREQ): Indicates that the host interface’s SERIRQ output is requesting a restart of LCLK. HICR1 Bit 6 CLKREQ Description 0 No LCLK restart request (Initial value) [Clearing conditions] 1 • LPC hardware reset or LPC software reset • LPC hardware shutdown or LPC software shutdown • SERIRQ is set to continuous mode • There are no further interrupts for transfer to the host in quiet mode LCLK restart request issued [Setting condition] • 582 In quiet mode, SERIRQ interrupt output becomes necessary while LCLK is stopped HICR1 Bit 5—SERIRQ Busy (IRQBSY): Indicates that the host interface’s SERIRQ signal is engaged in transfer processing. HICR1 Bit 5 IRQBSY Description 0 SERIRQ transfer frame wait state (Initial value) [Clearing conditions] 1 • LPC hardware reset or LPC software reset • LPC hardware shutdown or LPC software shutdown • End of SERIRQ transfer frame SERIRQ transfer processing in progress [Setting condition] • Start of SERIRQ transfer frame HICR1 Bit 4—LPC Software Reset Bit (LRSTB): Resets the host interface. For the scope of initialization by an LPC reset, see section 18B.3.4, Host Interface Shutdown Function. HICR1 Bit 4 LRSTB Description 0 Normal state (Initial value) [Clearing conditions] 1 • Writing 0 • LPC hardware reset LPC software reset state [Setting condition] • Writing 1 after reading LRSTB = 0 583 HICR0 Bit 3—LPC Software Shutdown Enable (SDWNE) HICR1 Bit 3—LPC Software Shutdown Bit (SDWNB) These bits control host interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 18B.3.4, Host Interface Shutdown Function. HICR0 Bit 3 SDWNE Description 0 Normal state, LPC software shutdown setting enabled (Initial value) [Clearing conditions] 1 • Writing 0 • LPC hardware reset or LPC software reset • LPC hardware shutdown release (rising edge of LPCPD signal) LPC hardware shutdown state setting enabled • Hardware shutdown state when LPCPD signal is low [Setting condition] • Writing 1 after reading SDWNE = 0 HICR1 Bit 3 SDWNB Description 0 Normal state [Clearing conditions] • Writing 0 • LPC hardware reset or LPC software reset • LPC hardware shutdown (falling edge of LPCPD signal when SDWNE = 1) • LPC hardware shutdown release (rising edge of LPCPD signal when SDWNE = 0) 1 LPC software shutdown state [Setting condition] • 584 Writing 1 after reading SDWNB = 0 (Initial value) 18B.2.3 Host Interface Control Registers 2 and 3 (HICR2, HICR3) • HICR2 Bit 7 6 5 4 3 2 1 0 GA20 LRST SDWN ABRT IBFIE3 IBFIE2 IBFIE1 ERRIE Initial value 0 0 0 0 0 0 0 0 Slave Read/Write R R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W Host Read/Write — — — — — — — — 3 2 1 0 PME LSMI LSCI 0 0 0 Note: * Only 0 can be written to bits 6 to 4, to clear the flags. • HICR3 Bit 7 6 5 4 LFRAME CLKRUN SERIRQ LRESET LPCPD Initial value 0 0 0 0 0 Slave Read/Write R R R R R R R R Host Read/Write — — — — — — — — HICR2 and HICR3 contain flags and bits that control interrupts from the host interface (LPC) module to the slave processor, and bits that monitor host interface pin states. Bits 6 to 0 of HICR2 are initialized to H'00 by a reset and in hardware standby mode. The states of the other bits are determined by the pin states. HICR2 Bit 7—GA20 Pin Monitor (GA20) HICR3 Bit 7—LFRAME Pin Monitor (LFRAME) HICR3 Bit 6—CLKRUN Pin Monitor (CLKRUN) HICR3 Bit 5—SERIRQ Pin Monitor (SERIRQ) HICR3 Bit 4—LRESET Pin Monitor (LRESET) HICR3 Bit 3—LPCPD Pin Monitor (LPCPD) HICR3 Bit 2—PME Pin Monitor (PME) HICR3 Bit 1—LSMI Pin Monitor (LSMI) HICR3 Bit 0—LSCI Pin Monitor (LSCI) These are pin state monitoring bits. The pin states can be monitored regardless of the host interface operating state or the operating state of the functions that use pin multiplexing. 585 HICR2 Bit 6—LPC Reset Interrupt Flag (LRST): Interrupt flag that generates an ERRI interrupt when an LPC hardware reset occurs. HICR2 Bit 6 LRST Description 0 [Clearing condition] • 1 (Initial value) Writing 0 after reading LRST = 1 [Setting condition] • LRESET pin falling edge detection HICR2 Bit 5—LPC Shutdown Interrupt Flag (SDWN): Interrupt flag that generates an ERRI interrupt when an LPC hardware shutdown request is generated. HICR2 Bit 5 SDWN Description 0 [Clearing conditions] 1 • Writing 0 after reading SDWN = 1 • LPC hardware reset (LRESET pin falling edge detection) • LPC software reset (LRSTB = 1) [Setting condition] • 586 LPCPD pin falling edge detection (Initial value) HICR2 Bit 4—LPC Abort Interrupt Flag (ABRT): Interrupt flag that generates an ERRI interrupt when a forced termination (abort) of an LPC transfer cycle occurs. HICR2 Bit 4 ABRT Description 0 [Clearing conditions] (Initial value) • Writing 0 after reading ABRT = 1 • LPC hardware reset (LRESET pin falling edge detection) • LPC software reset (LRSTB = 1) • LPC hardware shutdown (SDWNE = 1 and LPCPD falling edge detection) • 1 LPC software shutdown (SDWNB = 1) [Setting condition] • LFRAME pin falling edge detection during LPC transfer cycle HICR2 Bit 3—IDR3 and TWR receive complete Interrupt Enable (IBFIE3) HICR2 Bit 2—IDR2 receive complete Interrupt Enable (IBFIE2) HICR2 Bit 1—IDR1 receive complete Interrupt Enable (IBFIE1) HICR2 Bit 0—Error Interrupt Enable (ERRIE) These bits enable or disable IBFI1, IBFI2, IBFI3, and ERRI interrupts to the slave processor. HICR2 Bit 3 HICR2 Bit 2 HICR2 Bit 1 HICR2 Bit 0 IBFIE3 IBFIE2 IBFIE1 ERRIE Description — — — 0 Error interrupt requests disabled — — — 1 Error interrupt requests enabled — — 0 — Input data register IDR1 receive completed interrupt request disabled (Initial value) — — 1 — Input data register IDR1 receive completed interrupt request enabled — 0 — — Input data register IDR2 receive completed interrupt request disabled (Initial value) — 1 — — Input data register IDR2 receive completed interrupt request enabled 0 — — — Input data register IDR3 and TWR receive completed interrupt requests disabled (Initial value) 1 — — — Input data register IDR3 and TWR receive completed interrupt requests enabled (Initial value) 587 18B.2.4 LPC Channel 3 Address Register (LADR3) LADR3H Bit 7 6 5 4 3 LADR3L 2 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Initial value Read/Write 0 0 0 0 0 0 7 Bit 8 Bit 7 0 0 6 5 Bit 6 Bit 5 0 0 4 3 Bit 4 Bit 3 0 0 2 — 0 1 0 Bit 1 TWRE 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ↓ IDR3, ODR3, STR3 address 0 0 ↓ ↓ ↓ ↓ ↓ ↓ Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 ↓ ↓ ↓ ↓ ↓ ↓ ↓ TWR0–TWR15 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 address ↓ ↓ Bit 8 Bit 7 ↓ ↓ Bit 8 Bit 7 ↓ ↓ Bit 6 Bit 5 ↓ ↓ Bit 6 Bit 5 ↓ ↓ Bit 4 Bit 3 ↓ 1/0 Bit 1 0 ↓ Bit 4 1/0 1/0 1/0 1/0 LADR3 comprises two 8-bit readable/writable registers that perform LPC channel 3 host address setting and control the operation of the two-way registers. The contents of the address field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1). LADR3 is initialized to H'0000 by a reset and in hardware standby mode. It is not initialized in software standby mode. LADR3H Bits 7 to 0: Channel 3 Address Bits 15 to 8 LADR3L Bits 7 to 3 and 1: Channel 3 Address Bits 7 to 3 and 1 When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 of LADR3 is regarded as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4 of LADR3 is inverted, and the values of bits 3 to 0 are ignored. Register selection according to the bits ignored in address match determination is as shown in the following table. 588 I/O Address Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection Bit 4 Bit 3 0 Bit 1 0 I/O write IDR3 write, C/D3 ← 0 Bit 4 Bit 3 1 Bit 1 0 I/O write IDR3 write, C/D3 ← 1 Bit 4 Bit 3 0 Bit 1 0 I/O read ODR3 read Bit 4 Bit 3 1 Bit 1 0 I/O read STR3 read Bit 4 0 0 0 0 I/O write TWR0MW write Bit 4 0 0 0 1 I/O write TWR1 to TWR15 write • • • 1 1 1 1 Bit 4 0 0 0 0 I/O read TWR0SW read Bit 4 0 0 0 1 I/O read TWR1 to TWR15 read • • • 1 1 1 1 LADR3L Bit 2—Reserved: This is a readable/writable reserved bit. LADR3L Bit 0—Two-Way Register Enable (TWRE): Enables or disables two-way register operation. LADR3L Bit 0 TWRE Description 0 TWR operation is disabled (Initial value) TWR-related I/O address match determination is halted 1 TWR operation is enabled 18B.2.5 Input Data Registers (IDR1, IDR2, IDR3) Bit 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value — — — — — — — — Slave Read/Write R R R R R R R R Host Read/Write W W W W W W W W 589 The IDR registers are 8-bit read-only registers to the slave processor, and 8-bit write-only registers to the host processor. The registers selected from the host according to the I/O address are shown in the following table. For information on IDR3 selection, see section 18B.2.4, LPC Channel 3 Address Register (LADR3). Data transferred in an LPC I/O write cycle is written to the selected register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether the written information is a command or data. The initial values of the IDR registers after a reset and in standby mode are undetermined. I/O Address Bits 15 to 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection 0000 0000 0110 0 0 0 0 I/O write IDR1 write, C/D1 ← 0 0000 0000 0110 0 1 0 0 I/O write IDR1 write, C/D1 ← 1 0000 0000 0110 0 0 1 0 I/O write IDR2 write, C/D2 ← 0 0000 0000 0110 0 1 1 0 I/O write IDR2 write, C/D2 ← 1 18B.2.6 Output Data Registers (ODR1, ODR2, ODR3) Bit 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — — — — — — — Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Host Read/Write R R R R R R R R Initial value The ODR registers are 8-bit readable/writable registers to the slave processor, and 8-bit read-only registers to the host processor. The registers selected from the host according to the I/O address are shown in the following table. For information on ODR3 selection, see section 18B.2.4, LPC Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register is transferred to the host. The initial values of the ODR registers after a reset and in standby mode are undetermined. I/O Address Bits 15 to 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection 0000 0000 0110 0 0 0 0 I/O read ODR1 read 0000 0000 0110 0 0 1 0 I/O read ODR2 read 590 18B.2.7 Two-Way Data Registers (TWR0 to TWR15) • TWR0MW Bit 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value — — — — — — — — Slave Read/Write R R R R R R R R Host Read/Write W W W W W W W W 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value — — — — — — — — Slave Read/Write W W W W W W W W Host Read/Write R R R R R R R R 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 • TWR0SW Bit • TWR1 to TWR15 Bit Initial value — — — — — — — — Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Host Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave processor and the host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the same address for both the host address and the slave address. TWR0MW is a write-only register to the host processor, and a read-only register to the slave processor, while TWR0SW is a write-only register to the slave processor and a read-only register to the host processor. When the host and slave processors begin a write, after the respective TWR0 registers have been written to, access right arbitration for simultaneous access is performed by checking the status flags to see if those writes were valid. For the registers selected from the host according to the I/O address, see section 18B.2.4, LPC Channel 3 Address Register (LADR3). Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read cycle, the data in the selected register is transferred to the host. The initial values of TWR0 to TWR15 after a reset and in standby mode are undetermined. 591 18B.2.8 Status Registers (STR1, STR2, STR3) • STR1 Bit 7 6 5 4 3 2 1 0 DBU17 DBU16 DBU15 DBU14 C/D1 DBU12 IBF1 OBF1 0 0 0 0 0 0 0 0 Slave Read/Write R/W R/W R/W R/W R R/W R R/(W)* Host Read/Write R R R R R R R R Initial value Note: * Only 0 can be written, to clear the flag. • STR2 Bit 7 6 5 4 3 2 1 0 DBU27 DBU26 DBU25 DBU24 C/D2 DBU22 IBF2 OBF2 0 0 0 0 0 0 0 0 Slave Read/Write R/W R/W R/W R/W R R/W R R/(W)* Host Read/Write R R R R R R R R Initial value Note: * Only 0 can be written, to clear the flag. • STR3 Bit 7 6 5 4 3 2 1 0 IBF3B OBF3B MWMF SWMF C/D3 DBU32 IBF3A OBF3 Initial value 0 0 0 0 0 0 0 0 Slave Read/Write R R/(W)* R R/(W)* R R/W R R/(W)* Host Read/Write R R R R R R R R Note: * Only 0 can be written, to clear the flag. The STR registers are 8-bit registers that indicate status information during host interface processing. Bits 3, 1, and 0 of STR1 to STR3, and bits 7 to 4 of STR3, are read-only bits to both the host processor and the slave processor. However, 0 only can be written from the slave processor to bit 0 of STR1 to STR3, and bits 6 and 4 of STR3, in order to clear the flags to 0. The registers selected from the host processor according to the I/O address are shown in the following table. For information on STR3 selection, see section 18B.2.4, LPC Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register is transferred to the host processor. The STR registers are initialized to H'00 by a reset and in standby mode. 592 I/O Address Bits 15 to 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection 0000 0000 0110 0 1 0 0 I/O read STR1 read 0000 0000 0110 0 1 1 0 I/O read STR2 read STR1, STR2 Bits 7 to 4 and 2—Defined by User (DBU17 to DBU14, DBU12; DBU27 to DBU24, DBU22) STR3 Bit 2— Defined by User (DBU32) The user can use these bits as necessary. STR1, STR2, STR3 Bit 3—Command/Data (C/D1, C/D2, C/D3): When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command. Bit 3 C/D Description 0 Contents of data register (IDR) are data 1 Contents of data register (IDR) are a command (Initial value) STR1, STR2, STR3 Bit 1—Input Buffer Full (IBF1, IBF2, IBF3A): Set to 1 when the host processor writes to IDR. This bit is an internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads IDR. The IBF1 flag setting and clearing conditions are diffrent when the fast A20 gate is used. For details see table 18B.4, Fast A20 gate Output Signals. Bit 1 IBF Description 0 [Clearing condition] (Initial value) When the slave processor reads IDR 1 [Setting condition] When the host processor writes to IDR using I/O write cycle 593 STR1, STR2, STR3 Bit 0—Output Buffer Full (OBF1, OBF2, OBF3A): Set to 1 when the slave processor writes to ODR. Cleared to 0 when the host processor reads ODR. Bit 0 OBF Description 0 [Clearing condition] (Initial value) When the host processor reads ODR using I/O read cycle, or the slave processor writes 0 in the OBF bit 1 [Setting condition] When the slave processor writes to ODR STR3 Bit 7—Two-Way Register Input Buffer Full (IBF3B): Set to 1 when the host processor writes to TWR15. This is an internal interrupt source to the slave processor. IBF3B is cleared to 0 when the slave processor reads TWR15. Bit 7 IBF3B Description 0 [Clearing condition] (Initial value) When the slave processor reads TWR15 1 [Setting condition] When the host processor writes to TWR15 using I/O write cycle STR3 Bit 6—Two-Way Register Output Buffer Full (OBF3B): Set to 1 when the slave processor writes to TWR15. OBF3B is cleared to 0 when the host processor reads TWR15. Bit 6 OBF3B Description 0 [Clearing condition] (Initial value) When the host processor reads TWR15 using I/O read cycle, or the slave processor writes 0 in the OBF3B bit 1 [Setting condition] When the slave processor writes to TWR15 594 STR3 Bit 5—Master Write Mode Flag (MWMF): Set to 1 when the host processor writes to TWR0. MWMF is cleared to 0 when the slave processor reads TWR15. Bit 5 MWMF Description 0 [Clearing condition] (Initial value) When the slave processor reads TWR15 1 [Setting condition] When the host processor writes to TWR0 using I/O write cycle when SWMF = 0 STR3 Bit 4—Slave Write Mode Flag (SWMF): Set to 1 when the slave processor writes to TWR0. In the event of simultaneous writes by the master and the slave, the master write has priority. SWMF is cleared to 0 when the host reads TWR15. Bit 4 SWMF Description 0 [Clearing condition] (Initial value) When the host processor reads TWR15 using I/O read cycle, or the slave processor writes 0 in the SWMF bit 1 [Setting condition] When the slave processor writes to TWR0 when MWMF = 0 18B.2.9 SERIRQ Control Registers (SIRQCR0, SIRQCR1) • SIRQCR0 Bit 7 6 5 Q/C — IEDIR 0 0 0 0 0 0 0 0 Slave Read/Write R R/W R/W R/W R/W R/W R/W R/W Host Read/Write — — — — — — — — Initial value 4 3 SMIE3B SMIE3A 2 1 0 SMIE2 IRQ12E1 IRQ1E1 595 • SIRQCR1 Bit 7 6 5 4 3 2 1 0 IRQ11E3 IRQ10E3 IRQ9E3 IRQ6E3 IRQ11E2 IRQ10E2 IRQ9E2 IRQ6E2 Initial value 0 0 0 0 0 0 0 0 Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Host Read/Write — — — — — — — — The SIRQCR registers contain status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. The SIRQCR registers are initialized to H'00 by a reset and in hardware standby mode. SIRQCR0 Bit 7—Quiet/Continuous Mode Flag (Q/C): Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame). Bit 7 Q/C Description 0 Continuous mode (Initial value) [Clearing conditions] 1 • LPC hardware reset, LPC software reset • Specification by SERIRQ transfer cycle stop frame Quiet mode [Setting condition] • Specification by SERIRQ transfer cycle stop frame SIRQCR0 Bit 6—Reserved: This is a readable/writable reserved bit. SIRQCR0 Bit 5—Interrupt Enable Direct Mode (IEDIR): Specifies whether LPC channel 2 and channel 3 SERIRQ interrupt source (SMI, HIRQ6, HIRQ9 to HIRQ11) generation is conditional upon OBF, or is controlled only by the host interrupt enable bit. Bit 5 IEDIR Description 0 Host interrupt is requested when host interrupt enable bit and corresponding OBF are both set to 1 (Initial value) 1 Host interrupt is requested when host interrupt enable bit is set to 1 596 SIRQCR0 Bit 4—SMI Interrupt Enable 3B (SMIE3B): Enables or disables a SMI interrupt request when OBF3B is set by a TWR15 write. Bit 4 SMIE3B Description 0 SMI interrupt request by OBF3B and SMIE3B is disabled (Initial value) [Clearing conditions] 1 • Writing 0 to SMIE3B • LPC hardware reset, LPC software reset • Clearing OBF3B to 0 (when IEDIR = 0) [When IEDIR = 0] SMI interrupt request by setting OBF3B to 1 is enabled [When IEDIR = 1] SMI interrupt is requested [Setting condition] • Writing 1 after reading SMIE3B = 0 SIRQCR0 Bit 3—SMI Interrupt Enable 3A (SMIE3A): Enables or disables a SMI interrupt request when OBF3A is set by an ODR3 write. Bit 3 SMIE3A Description 0 SMI interrupt request by OBF3A and SMIE3A is disabled (Initial value) [Clearing conditions] 1 • Writing 0 to SMIE3A • LPC hardware reset, LPC software reset • Clearing OBF3A to 0 (when IEDIR = 0) [When IEDIR = 0] SMI interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] SMI interrupt is requested [Setting condition] • Writing 1 after reading SMIE3A = 0 597 SIRQCR1 Bit 7—HIRQ11 Interrupt Enable 3 (IRQ11E3): Enables or disables a HIRQ11 interrupt request when OBF3A is set by an ODR3 write. Bit 7 IRQ11E3 Description 0 HIRQ11 interrupt request by OBF3A and IRQ11E3 is disabled (Initial value) [Clearing conditions] 1 • Writing 0 to IRQ11E3 • LPC hardware reset, LPC software reset • Clearing OBF3A to 0 (when IEDIR = 0) [When IEDIR = 0] HIRQ11 interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] HIRQ11 interrupt is requested [Setting condition] • Writing 1 after reading IRQ11E3 = 0 SIRQCR1 Bit 6—HIRQ10 Interrupt Enable 3 (IRQ10E3): Enables or disables a HIRQ10 interrupt request when OBF3A is set by an ODR3 write. Bit 6 IRQ10E3 Description 0 HIRQ10 interrupt request by OBF3A and IRQ10E3 is disabled (Initial value) [Clearing conditions] 1 • Writing 0 to IRQ10E3 • LPC hardware reset, LPC software reset • Clearing OBF3A to 0 (when IEDIR = 0) [When IEDIR = 0] HIRQ10 interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] HIRQ10 interrupt is requested [Setting condition] • 598 Writing 1 after reading IRQ10E3 = 0 SIRQCR1 Bit 5—HIRQ9 Interrupt Enable 3 (IRQ9E3): Enables or disables a HIRQ9 interrupt request when OBF3A is set by an ODR3 write. Bit 5 IRQ9E3 Description 0 HIRQ9 interrupt request by OBF3A and IRQ9E3 is disabled (Initial value) [Clearing conditions] 1 • Writing 0 to IRQ9E3 • LPC hardware reset, LPC software reset • Clearing OBF3A to 0 (when IEDIR = 0) [When IEDIR = 0] HIRQ9 interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] HIRQ9 interrupt is requested [Setting condition] • Writing 1 after reading IRQ9E3 = 0 SIRQCR1 Bit 4—HIRQ6 Interrupt Enable 3 (IRQ6E3): Enables or disables a HIRQ6 interrupt request when OBF3A is set by an ODR3 write. Bit 4 IRQ6E3 Description 0 HIRQ6 interrupt request by OBF3A and IRQ6E3 is disabled (Initial value) [Clearing conditions] 1 • Writing 0 to IRQ6E3 • LPC hardware reset, LPC software reset • Clearing OBF3A to 0 (when IEDIR = 0) [When IEDIR = 0] HIRQ6 interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] HIRQ6 interrupt is requested [Setting condition] • Writing 1 after reading IRQ6E3 = 0 599 SIRQCR0 Bit 2—SMI Interrupt Enable 2 (SMIE2): Enables or disables a SMI interrupt request when OBF2 is set by an ODR2 write. Bit 2 SMIE2 Description 0 SMI interrupt request by OBF2 and SMIE2 is disabled (Initial value) [Clearing conditions] 1 • Writing 0 to SMIE2 • LPC hardware reset, LPC software reset • Clearing OBF2 to 0 (when IEDIR = 0) [When IEDIR = 0] SMI interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] SMI interrupt is requested [Setting condition] • Writing 1 after reading SMIE2 = 0 SIRQCR1 Bit 3—HIRQ11 Interrupt Enable 2 (IRQ11E2): Enables or disables a HIRQ11 interrupt request when OBF2 is set by an ODR2 write. Bit 3 IRQ11E2 Description 0 HIRQ11 interrupt request by OBF2 and IRQ11E2 is disabled [Clearing conditions] 1 • Writing 0 to IRQ11E2 • LPC hardware reset, LPC software reset • Clearing OBF2 to 0 (when IEDIR = 0) [When IEDIR = 0] HIRQ11 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] HIRQ11 interrupt is requested [Setting condition] • 600 Writing 1 after reading IRQ11E2 = 0 (Initial value) SIRQCR1 Bit 2—HIRQ10 Interrupt Enable 2 (IRQ10E2): Enables or disables a HIRQ10 interrupt request when OBF2 is set by an ODR2 write. Bit 2 IRQ10E2 Description 0 HIRQ10 interrupt request by OBF2 and IRQ10E2 is disabled (Initial value) [Clearing conditions] 1 • Writing 0 to IRQ10E2 • LPC hardware reset, LPC software reset • Clearing OBF2 to 0 (when IEDIR = 0) [When IEDIR = 0] HIRQ10 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] HIRQ10 interrupt is requested [Setting condition] • Writing 1 after reading IRQ10E2 = 0 SIRQCR1 Bit 1—HIRQ9 Interrupt Enable 2 (IRQ9E2): Enables or disables a HIRQ9 interrupt request when OBF2 is set by an ODR2 write. Bit 1 IRQ9E2 Description 0 HIRQ9 interrupt request by OBF2 and IRQ9E2 is disabled (Initial value) [Clearing conditions] 1 • Writing 0 to IRQ9E2 • LPC hardware reset, LPC software reset • Clearing OBF2 to 0 (when IEDIR = 0) [When IEDIR = 0] HIRQ9 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] HIRQ9 interrupt is requested [Setting condition] • Writing 1 after reading IRQ9E2 = 0 601 SIRQCR1 Bit 0—HIRQ6 Interrupt Enable 2 (IRQ6E2): Enables or disables a HIRQ6 interrupt request when OBF2 is set by an ODR2 write. Bit 0 IRQ6E2 Description 0 HIRQ6 interrupt request by OBF2 and IRQ6E2 is disabled (Initial value) [Clearing conditions] 1 • Writing 0 to IRQ6E2 • LPC hardware reset, LPC software reset • Clearing OBF2 to 0 (when IEDIR = 0) [When IEDIR = 0] HIRQ6 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] HIRQ6 interrupt is requested [Setting condition] • Writing 1 after reading IRQ6E2 = 0 SIRQCR0 Bit 1—HIRQ12 Interrupt Enable 1 (IRQ12E1): Enables or disables a HIRQ12 interrupt request when OBF1 is set by an ODR1 write. Bit 1 IRQ12E1 Description 0 HIRQ12 interrupt request by OBF1 and IRQ12E1 is disabled [Clearing conditions] 1 • Writing 0 to IRQ12E1 • LPC hardware reset, LPC software reset • Clearing OBF1 to 0 HIRQ12 interrupt request by setting OBF1 to 1 is enabled [Setting condition] • 602 Writing 1 after reading IRQ12E1 = 0 (Initial value) SIRQCR0 Bit 0—HIRQ1 Interrupt Enable 1 (IRQ1E1): Enables or disables a HIRQ1 interrupt request when OBF1 is set by an ODR1 write. Bit 0 IRQ1E1 Description 0 HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled (Initial value) [Clearing conditions] 1 • Writing 0 to IRQ1E1 • LPC hardware reset, LPC software reset • Clearing OBF1 to 0 HIRQ1 interrupt request by setting OBF1 to 1 is enabled [Setting condition] • Writing 1 after reading IRQ1E1 = 0 18B.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP0 bit is set to 1, the host interface (HIF: LPC) halts and enters module stop mode. See section 24.5, Module Stop Mode, for details. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRL Bit 0—Module Stop (MSTP0): Specifies host inteface (HIF:LPC) module stop mode. MSTPCRL Bit 0 MSTP0 Description 0 HIF:LPC module stop mode is cleared 1 HIF:LPC module stop mode is set (Initial value) 603 18B.3 Operation 18B.3.1 Host Interface Activation The host interface is activated by setting at least one of HICR0 bits LPC3E to LPC1E (bits 7 to 5) to 1 in single-chip mode. When the host interface is activated, the related I/O ports (ports 37 to 30, ports 83 and 82) function as dedicated host interface input/output pins. In addition, setting the FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports (ports 81 and 80, ports B0 and B1) to the host interface’s input/output pins. Use the following procedure to activate the host interface after a reset release. 1. Read the signal line status and confirm that the LPC module can be connected. Also check that the LPC module is initialized internally. 2. When using channel 3, set LADR3 to determine the channel 3 I/O address and whether twoway registers are to be used. 3. Set the enable bit (LPC3E to LPC1E) for the channel to be used. 4. Set the enable bits (GA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be used. 5. Set the selection bits for other functions (SDWNE, IEDIR). 6. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, OBF). Read IDR or TWR15 to clear IBF. 7. Set interrupt enable bits (IBFIE3 to IBFIE1, ERRIE) as necessary. 18B.3.2 LPC I/O Cycles There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O read, and bus master I/O write. Of these, the chip's HIF:LPC supports only I/O read and I/O write cycles. An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of the LPC transfer cycle has been requested. In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the following order, in synchronization with LCLK. The host can be made to wait by sending back a value other than 0000 in the slave’s synchronization return cycle, but with the H8S/2149’s HIF:LPC a value of 0000 is always returned. If the received address matches the host address in an HIF:LPC register (IDR, ODR, STR, TWR), the host interface enters the busy state; it returns to the idle state by output of a state #12 turnaround. Register (IDR, etc.) and flag (IBF, etc.) changes are made at this timing, so in the 604 event of a transfer cycle forced termination (abort) before state #12, registers and flags are not changed. I/O Read Cycle I/O Write Cycle State Count Contents Drive Source Value (3 to 0) Contents Drive Source Value (3 to 0) 1 Start Host 0000 Start Host 0000 2 Cycle type/direction Host 0000 Cycle type/direction Host 0010 3 Address 1 Host Bits 15 to 12 Address 1 Host Bits 15 to 12 4 Address 2 Host Bits 11 to 8 Address 2 Host Bits 11 to 8 5 Address 3 Host Bits 7 to 4 Address 3 Host Bits 7 to 4 6 Address 4 Host Bits 3 to 0 Address 4 Host Bits 3 to 0 7 Turnaround (recovery) Host 1111 Data 1 Host Bits 3 to 0 8 Turnaround None ZZZZ Data 2 Host Bits 7 to 4 9 Synchronization Slave 0000 Turnaround (recovery) Host 1111 10 Data 1 Slave Bits 3 to 0 Turnaround None ZZZZ 11 Data 2 Slave Bits 7 to 4 Synchronization Slave 0000 12 Turnaround (recovery) Slave 1111 Turnaround (recovery) Slave 1111 13 Turnaround None ZZZZ Turnaround None ZZZZ The timing of the LFRAME, LCLK, and LAD signals is shown in figures 18B.2 and 18B.3. LCLK LFRAME LAD3–LAD0 Start ADDR TAR Sync Data TAR Start Cycle type, direction, and size Number of clocks 1 1 4 2 1 2 2 1 Figure 18B.2 Typical LFRAME Timing 605 LCLK LFRAME LAD3–LAD0 Start ADDR Cycle type, direction, and size TAR Sync Slave must stop driving Master will drive high Too many Syncs cause timeout Figure 18B.3 Abort Mechanism 18B.3.3 A20 Gate The A20 gate signal can mask address A20 to emulate an addressing mode used by personal computers with an 8086*-family CPU. A regular-speed A20 gate signal can be output under firmware control. Fast A20 gate output is enabled by setting the FGA20E bit (bit 4) to 1 in HICR0 (H'FE40). Note: * An Intel microprocessor Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the slave processor (H8S/2149) receives data, it normally uses an interrupt routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1 command, firmware copies bit 1 of the data and outputs it at the gate A20 pin. Fast A20 Gate Operation: When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. Bit P81DDR must be set to 1 to assign this pin for output. When the DDR bit for P81 is set to 1, the state of the P81/GA20 pin can be monitored by reading the GA20 bit in HICR2. The initial output from this pin will be a logic 1, which is the initial value. Afterward, the host processor can manipulate the output from this pin by sending commands and data. This function is only available via the IDR1 register. The host interface decodes commands input from the host. When an H'D1 host command is detected, bit 1 of the data following the host command is output from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the regular processing using interrupts. Table 18B.3 shows the conditions that set and clear GA20 (P81). Figure 18B.4 shows the GA20 output in flowchart form. Table 18B.4 indicates the GA20 output signal values. 606 Table 18B.3 GA20 (P81) Set/Clear Timing Pin Name Setting Condition Clearing Condition GA20 (P81) When bit 1 of the written data is 1 and data follows an H'D1 host command When bit 1 of the written data is 0 and the data follows an H'D1 host command Start Host write No H'D1 command received? Yes Wait for next byte Host write No Data byte? Yes Write bit 1 of data byte to DR bit of P81/GA20 Figure 18B.4 GA20 Output 607 Table 18B.4 Fast A20 Gate Output Signals HA0 Data/Command Internal CPU Interrupt Flag (IBF) 1 H'D1 command 0 Q 0 1 data* 1 0 1 1 H'FF command 0 Q (1) 1 H'D1 command 0 Q 0 0 data* 2 0 0 1 H'FF command 0 Q (0) 1 H'D1 command 0 Q 0 1 data* 1 0 1 1/0 Command other than H'FF and H'D1 1 Q (1) 1 H'D1 command 0 Q 0 0 data* 2 0 0 1/0 Command other than H'FF and H'D1 1 Q (0) 1 H'D1 command 0 Q 1 Command other than H'D1 1 Q 1 H'D1 command 0 Q 1 H'D1 command 0 Q 1 H'D1 command 0 Q 0 Any data 0 1/0 1 H'D1 command 0 Q (1/0) Notes: 1. Arbitrary data with bit 1 set to 1. 2. Arbitrary data with bit 1 cleard to 0. 608 GA20 (P81) Remarks Turn-on sequence Turn-off sequence Turn-on sequence (abbreviated form) Turn-off sequence (abbreviated form) Cancelled sequence Retriggered sequence Consecutively executed sequences 18B.3.4 Host Interface Shutdown Function (LPCPD) The host interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of host interface shutdown state: LPC hardware shutdown and LPC software shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the software shutdown state is controlled by the SDWNB bit. In both states, the host interface enters the reset state by itself, and is no longer affected by external signals other than the LRESET and LPCPD signals. Placing the slave processor in sleep mode or software standby mode is effective in reducing current dissipation in the shutdown state. If software standby mode is set, some means must be provided for exiting software standby mode before clearing the shutdown state with the LPCPD signal. If the SDWNE bit has been set to 1 beforehand, the LPC hardware shutdown state is entered at the same time as the LPCPD signal falls, and prior preparation is not possible. If the LPC software shutdown state is set by means of the SDWNB bit, on the other hand, the LPC software shutdown state cannot be cleared at the same time as the rise of the LPCPD signal. Taking these points into consideration, the following operating procedure uses a combination of LPC software shutdown and LPC hardware shutdown. 1. Clear the SDWNE bit to 0. 2. Set the ERRIE bit to 1 and wait for an interrupt by the SDWN flag. 3. When an ERRI interrupt is generated by the SDWN flag, check the host interface internal status flags and perform any necessary processing. 4. Set the SDWNB bit to 1 to set LPC software standby mode. 5. Set the SDWNE bit to 1 and make a transition to LPC hardware standby mode. The SDWNB bit is cleared automatically. 6. Check the state of the LPCPD signal to make sure that the LPCPD signal has not risen during steps 3 to 5. If the signal has risen, clear SDWNE to 0 to return to the state in step 1. 7. Place the slave processor in sleep mode or software standby mode as necessary. 8'. If software standby mode has been set, exit software standby mode by some means independent of the LPC. 8. When a rising edge is detected in the LPCPD signal, the SDWNE bit is automatically cleared to 0. If the slave processor has been placed in sleep mode, the mode is exited by means of LRESET signal input, on completion of the LPC transfer cycle, or by some other means. Table 18B.5 shows the scope of HIF pin shutdown 609 Table 18B.5 Scope of HIF Pin Shutdown Abbreviation Port Scope of Shutdown I/O Notes LAD3 to LAD0 P33–P30 O I/O Hi-Z LFRAME P34 O Input Hi-Z LRESET P35 X Input LPC hardware reset function is active LCLK P36 O Input Hi-Z SERIRQ P37 O I/O Hi-Z LSCI PB1 ∆ I/O Hi-Z, only when LSCIE = 1 LSMI PB0 ∆ I/O Hi-Z, only when LSMIE = 1 PME P80 ∆ I/O Hi-Z, only when PMEE = 1 GA20 P81 ∆ I/O Hi-Z, only when FGA20E = 1 CLKRUN P82 O I/O Hi-Z LPCPD P83 X Input Needed to clear shutdown state Note: O: Pins shut down by the shutdown function ∆: Pins shut down only when the HIF (LPC) function is selected by register setting X: Pins not shut down In the LPC shutdown state, the LPC’s internal state and some register bits are initialized. The order of priority of LPC shutdown and reset states is as follows. 1. System reset (reset by STBY or RES pin input, or WDT0 overflow) • All register bits, including bits LPC3E to LPC1E, are initialized. 2. LPC hardware reset (reset by LRESET pin input) • LRSTB, SDWNE, and SDWNB bits are cleared to 0. 3. LPC software reset (reset by LRSTB) • SDWNE and SDWNB bits are cleared to 0. 4. LPC hardware shutdown • SDWNB bit is cleared to 0. 5. LPC software shutdown The scope of the initialization in each mode is shown in table 18B.6. 610 Table 18B.6 Scope of Initialization in Each Host Interface Mode System Reset LPC Reset LPC Shutdown LPC transfer cycle sequencer (internal state), LPCBSY and ABRT flags Initialized Initialized Initialized SERIRQ transfer cycle sequencer (internal state), CLKREQ and IRQBSY flags Initialized Initialized Initialized Host interface flags (IBF1, IBF2, IBF3A, IBF3B, MWMF, C/D1, C/D2, C/D3, OBF1, OBF2, OBF3A, OBF3B, SWMF, DBU), GA20 (internal state) Initialized Initialized Retained Host interrupt enable bits (IRQ1E1, IRQ12E1, SMIE2, IRQ6E2, IRQ9E2 to IRQ11E2, SMIE3B, SMIE3A, IRQ6E3, IRQ9E3 to IRQ11E3), Q/C flag Initialized Initialized Retained LRST flag Initialized (0) Can be set/cleared Can be set/cleared SDWN flag Initialized (0) Initialized (0) Can be set/cleared LRSTB bit Initialized (0) HR: 0 SR: 1 0 (can be set) SDWNB bit Initialized (0) Initialized (0) HS: 0 SS: 1 SDWNE bit Initialized (0) Initialized (0) HS: 1 SS: 0 or 1 Host interface operation control bits (LPC3E to LPC1E, FGA20E, LADR3, IBFIE1 to IBFIE3, PMEE, PMEB, LSMIE, LSMIB, LSCIE, LSCIB) Initialized Retained Retained LRESET signal Input (port function) Input Input Input Input LAD3 to LAD0, LFRAME, LCLK, SERIRQ, CLKRUN signals Input Hi-Z PME, LSMI, LSCI, GA20 signals (when function is selected) Output Hi-Z PME, LSMI, LSCI, GA20 signals (when function is not selected) Port function Port function Items Initialized LPCPD signal Note: System reset: Reset by STBY input, RES input, or WDT overflow LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR) LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS) 611 Figure 18B.5 shows the timing of the LPCPD and LRESET signals. LCLK LPCPD LAD3–LAD0 LFRAME At least 30 µs At least 100 µs At least 60 µs LRESET Figure 18B.5 Power-Down State Termination Timing 18B.3.5 Host Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a supporting function, and a request signal is generated by the frame corresponding to that interrupt. The timing is shown in figure 18B.6. 612 SL or H Start frame H R T IRQ0 frame IRQ1 frame IRQ2 frame S S S R T R T R T LCLK START SERIRQ IRQ1 Drive source Host controller None IRQ1 None H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample IRQ14 frame IRQ15 frame S S R T R T IOCHCK frame S R T Stop frame I H R Next cycle T LCLK STOP SERIRQ Driver None IRQ15 None START Host controller H = Host control, R = Recovery, T = Turnaround, S = Sample, I = Idle Figure 18B.6 SERIRQ Timing The serialized interrupt transfer cycle frame configuration is as follows. Two of the states comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The recover state must be driven by the host or slave processor that was driving the preceding state. 613 Serial Interrupt Transfer Cycle Frame Count Contents Drive Source Number of States 0 Start Slave 6 Host Notes In quiet mode only, slave drive possible in first state, then next 3 states 0-driven by host 1 HIRQ0 Slave 3 2 HIRQ1 Slave 3 Drive possible in LPC channel 1 3 SMI Slave 3 Drive possible in LPC channels 2 and 3 4 HIRQ3 Slave 3 5 HIRQ4 Slave 3 6 HIRQ5 Slave 3 7 HIRQ6 Slave 3 8 HIRQ7 Slave 3 9 HIRQ8 Slave 3 10 HIRQ9 Slave 3 Drive possible in LPC channels 2 and 3 11 HIRQ10 Slave 3 Drive possible in LPC channels 2 and 3 12 HIRQ11 Slave 3 Drive possible in LPC channels 2 and 3 13 HIRQ12 Slave 3 Drive possible in LPC channel 1 14 HIRQ13 Slave 3 15 HIRQ14 Slave 3 16 HIRQ15 Slave 3 17 IOCHCK Slave 3 18 Stop Host Undefined Drive possible in LPC channels 2 and 3 First, 1 or more idle states, then 2 or 3 states 0-driven by host 2 states: Quiet mode next 3 states: Continuous mode next There are two modes—continuous mode and quiet mode—for serialized interrupts. The mode initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer cycle that ended before that cycle. In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet mode, the slave processor with interrupt sources requiring a request can also initiate an interrupt transfer cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate interrupt transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the powerdown state. In order for a slave to transfer an interrupt request in this case, a request to restart the clock must first be issued to the host. For details see section 18B.3.6, Host Interface Clock Start Request (CLKRUN). 614 18B.3.6 Host Interface Clock Start Request (CLKRUN) A request to restart the clock (LCLK) can be sent to the host processor by means of the CLKRUN pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host interrupt request is generated the CLKRUN signal is driven and a clock (LCLK) restart request is sent to the host. The timing for this operation is shown in figure 18B.7. CLK 1 2 3 4 5 6 CLKRUN Pull-up enable Drive by the host processor Drive by the slave processor Figure 18B.7 Clock Start or Speed-Up Cases other than SERIRQ in quiet mode when clock restart is required must be handled with a different protocol, using the PME signal, etc. 615 18B.4 Interrupt Sources 18B.4.1 IBF1, IBF2, IBF3, ERRI The host interface has four interrupt requests for the slave processor: IBF1, IBF2, IBF3, and ERRI. IBF1, IBF2, and IBF3 are IDR receive complete interrupts for IDR1, IDR2, and IDR3 and TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such as an LPC reset, LPC shutdown, or transfer cycle abort. An interrupt request is enable by setting the corresponding enable bit, Table 18B.7 Receive Complete Interrupts and Error Interrupt Interrupt Description IBF1 Requested when IBFIE1 is set to 1 and IDR1 reception is completed IBF2 Requested when IBFIE2 is set to 1 and IDR2 reception is completed IBF3 Requested when IBFIE3 is set to 1 and IDR3 reception is completed, or when TWRE and IBFIE3 are set to 1 and reception is completed up to TWR15 ERRI Requested when ERRIE is set to 1 and LRST, SDWN, or ABRT is set to 1 18B.4.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, HIRQ12 The host interface can request seven kinds of host interrupt by means of SERIRQ. HIRQ1 and HIRQ12 are used on LPC channel 1 only, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can be requested from LPC channel 2 or 3. There are two ways of clearing a host interrupt request. When the IEDIR bit is cleared to 0 in SIRQCR0, host interrupt sources and LPC channels are all linked to the host interrupt request enable bits. When the OBF flag is cleared to 0 by a read by the host of ODR or TWR15 in the corresponding LPC channel, the corresponding host interrupt enable bit is automatically cleared to 0, and the host interrupt request is cleared. When the IEDIR bit is set to 1 in SIRQCR0, LPC channel 2 and 3 interrupt requests are dependent only upon the host interrupt enable bits. The host interrupt enable bit is not cleared when OBF for channel 2 or 3 is cleared. Therefore, SMIE2, SMIE3A and SMIE3B, IRQ6E2 and IRQ6E3, IRQ9E2 and IRQ9E3, IRQ10E2 and IRQ10E3, and IRQ11E2 and IRQ11E3 lose their respective functional differences. In order to clear a host interrupt request, it is necessary to clear the host interrupt enable bit. Table 18B.8 summarizes the methods of setting and clearing these bits, and figure 18B.8 shows the processing flowchart. 616 Table 18B.8 HIRQ Setting and Clearing Conditions Host Interrupt Setting Condition Clearing Condition HIRQ1 (independent from IEDIR) Internal CPU writes to ODR1, then reads Internal CPU writes 0 in bit IRQ1E1, 0 from bit IRQ1E1 and writes 1 or host reads ODR1 HIRQ12 (independent from IEDIR) Internal CPU writes to ODR1, then reads Internal CPU writes 0 in bit IRQ12E1, 0 from bit IRQ12E1 and writes 1 or host reads ODR1 SMI (IEDIR = 0) Internal CPU • writes to ODR2, then reads 0 from bit SMIE2 and writes 1 • Internal CPU writes 0 in bit SMIE2, or host reads ODR2 • writes to ODR3, then reads 0 from bit SMIE3A and writes 1 • Internal CPU writes 0 in bit SMIE3A, or host reads ODR3 • writes to TWR15, then reads 0 from bit • Internal CPU writes 0 in bit SMIE3B and writes 1 SMIE3B, or host reads TWR15 SMI (IEDIR = 1) Internal CPU • reads 0 from bit SMIE2, then writes 1 • Internal CPU writes 0 in bit SMIE2 • reads 0 from bit SMIE3A, then writes 1 • Internal CPU writes 0 in bit SMIE3A • reads 0 from bit SMIE3B, then writes 1 • Internal CPU writes 0 in bit SMIE3B HIRQi (i = 6, 9, 10, 11) (IEDIR = 0) HIRQi (i = 6, 9, 10, 11) (IEDIR = 1) Internal CPU • writes to ODR2, then reads 0 from bit IRQIE2 and writes 1 • Internal CPU writes 0 in bit IRQIE2, or host reads ODR2 • writes to ODR3, then reads 0 from bit IRQIE3 and writes 1 • Internal CPU writes 0 in bit IRQIE3, or host reads ODR3 Internal CPU • reads 0 from bit IRQIE2, then writes 1 • Internal CPU writes 0 in bit IRQIE2 • reads 0 from bit IRQIE3, then writes 1 • Internal CPU writes 0 in bit IRQIE3 617 Slave CPU Master CPU ODR1 write Write 1 to IRQ1E1 No SERIRQ IRQ1 output Interrupt initiation SERIRQ IRQ1 source clearance ODR1 read OBF1 = 0? Yes No All bytes transferred? Hardware operation Yes Software operation Figure 18B.8 HIRQ Flowchart (Example of Channel 1) 18B.5 Usage Note The following points should be noted when using the HIF : LPC. (1) The host interface provides buffering of asynchronous data from the host processor and slave processor, but an interface protocol that uses the flags in STR must be followed to avoid data contention. For example, if the host and slave processor both try to access IDR or ODR at the same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be used to allow access only to data for which writing has finished. (2) Unlike the IDR and ODR registers, the transfer direction is not fixed for the two-way registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing to TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to TWR15 has been obtained. (3) Table 18B.9 shows host address examples for corresponding registers when LADR3 = H'A24F and LADR3 = H'3FD0. 618 Table 18B.9 Host Address Example Register Host Address when LADR3 = H'A24F Host Address when LADR3 = H'3FD0 IDR3 H'A24A and H'A24E H'3FD0 and H'3FD4 ODR3 H'A24A H'3FD0 STR3 H'A24E H'3FD4 TWR0MW H'A250 H'3FC0 TWR0SW H'A250 H'3FC0 TWR1 H'A251 H'3FC1 TWR2 H'A252 H'3FC2 TWR3 H'A253 H'3FC3 TWR4 H'A254 H'3FC4 TWR5 H'A255 H'3FC5 TWR6 H'A256 H'3FC6 TWR7 H'A257 H'3FC7 TWR8 H'A258 H'3FC8 TWR9 H'A259 H'3FC9 TWR10 H'A25A H'3FCA TWR11 H'A25B H'3FCB TWR12 H'A25C H'3FCC TWR13 H'A25D H'3FCD TWR14 H'A25E H'3FCE TWR15 H'A25F H'3FCF 619 620 Section 19 D/A Converter 19.1 Overview The H8S/2169 or H8S/2149 has an on-chip D/A converter module with two channels. 19.1.1 Features Features of the D/A converter module are listed below. • • • • • Eight-bit resolution Two-channel output Maximum conversion time: 10 µs (with 20-pF load capacitance) Output voltage: 0 V to AVref D/A output retention in software standby mode 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the D/A converter. 621 AVref DACR 8-bit D/A DADR1 DA0 DADR0 AVCC DA1 AVSS Control circuit Legend: DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 Figure 19.1 Block Diagram of D/A Converter 622 Bus interface Module data bus Internal data bus 19.1.3 Input and Output Pins Table 19.1 lists the input and output pins used by the D/A converter module. Table 19.1 Input and Output Pins of D/A Converter Module Name Abbreviation I/O Function Analog supply voltage AVCC Input Power supply for analog circuits Analog ground AVSS Input Ground and reference voltage for analog circuits Analog output 0 DA0 Output Analog output channel 0 Analog output 1 DA1 Output Analog output channel 1 Reference voltage pin AVref Input Reference voltage for analog circuits 19.1.4 Register Configuration Table 19.2 lists the registers of the D/A converter module. Table 19.2 D/A Converter Registers Name Abbreviation R/W Initial Value Address* D/A data register 0 DADR0 R/W H'00 H'FFF8 D/A data register 1 DADR1 R/W H'00 H'FFF9 D/A control register DACR R/W H'1F H'FFFA Module stop control register MSTPCRH R/W H'3F H'FF86 MSTPCRL R/W H'FF H'FF87 Note: * Lower 16 bits of the address. 623 19.2 Register Descriptions 19.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W D/A data registers 0 and 1 (DADR0 and DADR1) are 8-bit readable/writable registers that store data to be converted. When analog output is enabled, the value in the D/A data register is converted and output continuously at the analog output pin. The D/A data registers are initialized to H'00 by a reset and in hardware standby mode. 19.2.2 D/A Control Register (DACR) Bit 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE — — — — — Initial value 0 0 0 1 1 1 1 1 Read/Write R/W R/W R/W — — — — — DACR is an 8-bit readable/writable register that controls the operation of the D/A converter module. DACR is initialized to H'1F by a reset and in hardware standby mode. Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 Description 0 Analog output DA1 is disabled 1 D/A conversion is enabled on channel 1. Analog output DA1 is enabled 624 (Initial value) Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description 0 Analog output DA0 is disabled 1 D/A conversion is enabled on channel 0. Analog output DA0 is enabled (Initial value) Bit 5—D/A Enable (DAE): Controls D/A conversion, in combination with bits DAOE0 and DAOE1. D/A conversion is controlled independently on channels 0 and 1 when DAE = 0. Channels 0 and 1 are controlled together when DAE = 1. Output of the converted results is always controlled independently by DAOE0 and DAOE1. Bit 7 Bit 6 Bit 5 DAOE1 DAOE0 DAE D/A conversion 0 0 * Disabled on channels 0 and 1 1 0 Enabled on channel 0 Disabled on channel 1 1 Enabled on channels 0 and 1 0 Disabled on channel 0 Enabled on channel 1 1 Enabled on channels 0 and 1 * Enabled on channels 0 and 1 1 0 1 *: Don’t care If the chip enters software standby mode while D/A conversion is enabled, the D/A output is retained and the analog power supply current is the same as during D/A conversion. If it is necessary to reduce the analog power supply current in software standby mode, disable D/A output by clearing the DAOE0, DAOE1 and DAE bits to 0. Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1. 625 19.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP10 bit is set to 1, the D/A converter halts and enters module stop mode at the end of the bus cycle. See section 24.5, Module Stop Mode, for details. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 2—Module Stop (MSTP10): Specifies D/A converter module stop mode. MSTPCRH Bit 2 MSTP10 Description 0 D/A converter module stop mode is cleared 1 D/A converter module stop mode is set 626 (Initial value) 19.3 Operation The D/A converter module has two built-in D/A converter circuits that can operate independently. D/A conversion is performed continuously whenever enabled by the D/A control register (DACR). When a new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The converted result is output by setting the DAOE0 or DAOE1 bit to 1. An example of conversion on channel 0 is given next. Figure 19.2 shows the timing. • Software writes the data to be converted in DADR0. • D/A conversion begins when the DAOE0 bit in DACR is set to 1. After the elapse of the conversion time, analog output appears at the DA0 pin. The output value is AVref × (DADR value)/256. This output continues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0. • If a new value is written in DADR0, conversion begins immediately. Output of the converted result begins after the conversion time. • When the DAOE0 bit is cleared to 0, DA0 becomes an input pin. DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle Ø Address Conversion data (1) DADR0 Conversion data (2) DAOE0 Conversion result (1) DA0 High-impedance state t DCONV Conversion result (2) t DCONV t DCONV: D/A conversion time Figure 19.2 D/A Conversion (Example) 627 628 Section 20 A/D Converter 20.1 Overview The H8S/2169 or H8S/2149 incorporates a 10-bit successive-approximations A/D converter that allows up to eight analog input channels to be selected. In addition to the eight analog input channels, up to 16 channels of digital input can be selected for A/D conversion. Since the conversion precision falls when digital input is selected, digital input is ideal for use by a comparator identifying multi-valued inputs, for example. 20.1.1 Features A/D converter features are listed below. • 10-bit resolution • Eight (analog) or 16 (digital) input channels • Settable analog conversion voltage range The analog conversion voltage range is set using the reference power supply voltage pin (AVref) as the analog reference voltage • High-speed conversion Minimum conversion time: 13.4 µs per channel (at 10 MHz operation) • Choice of single mode or scan mode Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels • Four data registers Conversion results are held in a 16-bit data register for each channel • Sample and hold function • Three kinds of conversion start Choice of software or timer conversion start trigger (8-bit timer), or ADTRG pin • A/D conversion end interrupt generation An A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion 629 20.1.2 Block Diagram Figure 20.1 shows a block diagram of the A/D converter. Internal data bus AVSS AN3 AN4 AN5 AN6/CIN0 to CIN7 AN7/CIN8 to CIN15 ADCR ADCSR ADDRD ADDRC + – Multiplexer AN0 AN1 AN2 ADDRB 10-bit D/A ADDRA AVref Successive approximations register AVCC Bus interface Module data bus Comparator ø/8 Control circuit Sample-andhold circuit ø/16 ADI interrupt signal ADTRG Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: Conversion start trigger from 8-bit timer A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 20.1 Block Diagram of A/D Converter 630 20.1.3 Pin Configuration Table 20.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. Table 20.1 A/D Converter Pins Pin Name Symbol I/O Function Analog power supply pin AVCC Input Analog block power supply Analog ground pin AVSS Input Analog block ground and A/D conversion reference voltage Reference power supply pin AVref Input A/D conversion reference voltage Analog input pin 0 AN0 Input Analog input channel 0 Analog input pin 1 AN1 Input Analog input channel 1 Analog input pin 2 AN2 Input Analog input channel 2 Analog input pin 3 AN3 Input Analog input channel 3 Analog input pin 4 AN4 Input Analog input channel 4 Analog input pin 5 AN5 Input Analog input channel 5 Analog input pin 6 AN6 Input Analog input channel 6 Analog input pin 7 AN7 Input Analog input channel 7 A/D external trigger input pin ADTRG Input External trigger input for starting A/D conversion Expansion A/D input pins 0 to 15 CIN0 to CIN15 Input Expansion A/D conversion input (digital input pin) channels 0 to 15 631 20.1.4 Register Configuration Table 20.2 summarizes the registers of the A/D converter. Table 20.2 A/D Converter Registers Name Abbreviation R/W Initial Value Address* 1 A/D data register AH ADDRAH R H'00 H'FFE0 A/D data register AL ADDRAL R H'00 H'FFE1 A/D data register BH ADDRBH R H'00 H'FFE2 A/D data register BL ADDRBL R H'00 H'FFE3 A/D data register CH ADDRCH R H'00 H'FFE4 A/D data register CL ADDRCL R H'00 H'FFE5 A/D data register DH ADDRDH R H'00 H'FFE6 A/D data register DL ADDRDL R H'00 H'FFE7 H'00 H'FFE8 2 A/D control/status register ADCSR R/(W)* A/D control register ADCR R/W H'3F H'FFE9 Module stop control register MSTPCRH R/W H'3F H'FF86 MSTPCRL R/W H'FF H'FF87 KBCOMP R/W H'00 H'FEE4 Keyboard comparator control register Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written in bit 7, to clear the flag. 20.2 Register Descriptions 20.2.1 A/D Data Registers A to D (ADDRA to ADDRD) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. 632 The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 20.3. The ADDR registers can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 20.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Table 20.3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Group 0 Group 1 A/D Data Register AN0 AN4 ADDRA AN1 AN5 ADDRB AN2 AN6 or CIN0 to CIN7 ADDRC AN3 AN7 or CIN8 to CIN15 ADDRD 20.2.2 A/D Control/Status Register (ADCSR) 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Bit Note: * Only 0 can be written in bit 7, to clear the flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations. ADCSR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. 633 Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF Description 0 [Clearing conditions] 1 • When 0 is written in the ADF flag after reading ADF = 1 • When the DTC is activated by an ADI interrupt and ADDR is read (Initial value) [Setting conditions] • Single mode: When A/D conversion ends • Scan mode: When A/D conversion ends on all specified channels Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE Description 0 A/D conversion end interrupt (ADI) request is disabled 1 A/D conversion end interrupt (ADI) request is enabled (Initial value) Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST Description 0 A/D conversion stopped 1 Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends (Initial value) Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 20.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped. 634 Bit 4 SCAN Description 0 Single mode 1 Scan mode (Initial value) Bit 3—Clock Select (CKS): Sets the A/D conversion time. Only change the conversion time while ADST = 0. Bit 3 CKS Description 0 Conversion time = 266 states (max.) 1 Conversion time = 134 states (max.) (Initial value) Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channel(s). Two analog input channel can be switched to digital input. Only set the input channel while conversion is stopped. Group Selection Channel Selection Description CH2 CH1 CH0 Single Mode Scan Mode 0 0 0 AN0 AN0 1 AN1 AN0, AN1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 0 AN4 AN4 1 AN5 AN4, AN5 0 AN6 or CIN0 to CIN7 AN4, AN5, AN6 or CIN0 to CIN7 1 AN7 or CIN8 to CIN15 AN4, AN5, AN6 or CIN0 to CIN7 1 1 0 1 (Initial value) AN7 or CIN8 to CIN15 635 20.2.3 A/D Control Register (ADCR) 7 6 5 4 3 2 1 0 TRGS1 TRGS0 — — — — — — 1 1 1 — — Bit Initial value 0 0 1 1 1 Read/Write R/W R/W — — — — ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations. ADCR is initialized to H'3F by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): These bits select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped. Bit 7 Bit 6 TRGS1 TRGS0 Description 0 0 Start of A/D conversion by external trigger is disabled 1 Start of A/D conversion by external trigger is disabled 0 Start of A/D conversion by external trigger (8-bit timer) is enabled 1 Start of A/D conversion by external trigger pin is enabled 1 Bits 5 to 0—Reserved: Should always be written with 1. 636 (Initial value) 20.2.4 Keyboard Comparator Control Register (KBCOMP) Bit 7 6 5 4 3 IrE IrCKS2 IrCKS1 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W IrCKS0 KBADE 2 KBCH2 1 0 KBCH1 KBCH0 KBCOMP is an 8-bit readable/writable register that controls the SCI2 IrDA function and selects the CIN input channels for A/D conversion. KBCOMP is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4—IrDA Control: See the description in section 15.2.11, Keyboard Comparator Control Register (KBCOMP). Bit 3—Keyboard A/D Enable (KBADE): Selects either analog input pins (AN6, AN7) or digital input pins (CIN0 to CIN7, CIN8 to CIN15) for A/D converter channel 6 and channel 7 input. Bits 2 to 0—Keyboard A/D Channel Select 2 to 0 (KBCH2 to KBCH0): These bits select the channels for A/D conversion from among the digital input pins. Only set the input channel while A/D conversion is stopped. Bit 3 Bit 2 Bit 1 Bit 0 KBADE KBCH2 KBCH1 KBCH0 A/D Converter Channel 6 Input A/D Converter Channel 7 Input 0 — — — AN6 AN7 1 0 0 0 CIN0 CIN8 1 CIN1 CIN9 0 CIN2 CIN10 1 CIN3 CIN11 0 CIN4 CIN12 1 CIN5 CIN13 0 CIN6 CIN14 1 CIN7 CIN15 1 1 0 1 637 20.2.5 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 24.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 1—Module Stop (MSTP9): Specifies the A/D converter module stop mode. MSTPCRH Bit 1 MSTP9 Description 0 A/D converter module stop mode is cleared 1 A/D converter module stop mode is set 638 (Initial value) 20.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, but the data bus to the bus master is only 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 20.2 shows the data flow for ADDR access. Upper byte read Bus master (H'AA) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 20.2 ADDR Access Operation (Reading H'AA40) 639 20.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 20.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 20.3 shows a timing diagram for this example. 1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The routine reads ADCSR, then writes 0 to the ADF flag. 6. The routine reads and processes the conversion result (ADDRB). 7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated. 640 Set* ADIE ADST A/D conversion starts Set* Set* Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion 1 Idle A/D conversion 2 Idle ADDRA ADDRB Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 ADDRC ADDRD Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 20.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 641 20.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0; AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 20.4 shows a timing diagram for this example. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). 642 Continuous A/D conversion execution Clear*1 Set*1 ADST Clear*1 ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) Idle Idle A/D conversion 1 Idle Idle A/D conversion 2 Idle Idle A/D conversion 4 A/D conversion 5 *2 Idle A/D conversion 3 State of channel 3 (AN3) Idle Idle Transfer ADDRA A/D conversion result 1 ADDRB A/D conversion result 4 A/D conversion result 2 ADDRC A/D conversion result 3 ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. Figure 20.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) 643 20.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 20.5 shows the A/D conversion timing. Table 20.4 indicates the A/D conversion time. As indicated in figure 20.5, the A/D conversion time includes t D and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 20.4. In scan mode, the values given in table 20.4 apply to the first conversion time. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1. (1) ø Address (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1): ADCSR write cycle (2): ADCSR address A/D conversion start delay tD: tSPL: Input sampling time tCONV: A/D conversion time Figure 20.5 A/D Conversion Timing 644 Table 20.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max A/D conversion start delay tD 10 — 17 6 — 9 Input sampling time t SPL — 63 — — 31 — A/D conversion time t CONV 259 — 266 131 — 134 Note: Values in the table are the number of states. 20.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit is set to 1 by software. Figure 20.6 shows the timing. ø ADTRG Internal trigger signal ADST A/D conversion Figure 20.6 External Trigger Input Timing 20.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 645 20.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: 1. Analog input voltage range The voltage applied to the ANn analog input pins during A/D conversion should be in the range AVSS ≤ ANn ≤ AVref (n = 0 to 7). 2. Digital input voltage range The voltage applied to the CINn digital input pins should be in the range AVSS ≤ CINn ≤ AVref and VSS ≤ CINn ≤ VCC (n = 0 to 15). 3. Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. 4. Setting Range of AVref Pin: The reference voltage supplied via the AVref pin should be in the range AVref ≤ AVCC. If conditions 1 to 4 above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference power supply (AVref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) or analog reference power supply pin (AVref) should be connected between AVCC and AVSS as shown in figure 20.7. Also, the bypass capacitors connected to AVCC, AVref and the filter capacitor connected to AN0 to AN7 must be connected to AVSS. If a filter capacitor is connected as shown in figure 20.7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the 646 sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin ), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC AVref 100 Ω Rin* 2 *1 AN0 to AN7 *1 0.1 µF Notes: AVSS Figures are reference values. 1. 10 µF 0.01 µF 2. Rin: Input impedance Figure 20.7 Example of Analog Input Protection Circuit Table 20.5 Analog Pin Ratings Item Min Max Unit Analog input capacitance — 20 pF Permissible signal source impedance — 5* kΩ Note: * When V CC= 2.7 to 3.6 V and ø ≤ 10 MHz. 10 kΩ AN0 to AN7 To A/D converter 20 pF Note: Numeric values are reference values. Figure 20.8 Analog Input Pin Equivalent Circuit 647 A/D Conversion Precision Definitions: H8S/2169 or H8S/2149 A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 20.10). • Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 20.11). • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 20.9). • Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. • Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. 648 Digital output H'3FF Ideal A/D conversion characteristic H'3FE H'3FD H'004 H'003 H'002 Quantization error H'001 H'000 2 1 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 20.9 A/D Conversion Precision Definitions (1) 649 Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 20.10 A/D Conversion Precision Definitions (2) 650 Permissible Signal Source Impedance: H8S/2169 or H8S/2149 analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance is ignored. But since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µsec or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. The chip A/D converter equivalent circuit Sensor output impedance, up to 5 kΩ 10 kΩ Sensor input Low-pass filter C to 0.1 µF Cin = 15 pF 20 pF Figure 20.11 Example of Analog Input Circuit 651 652 Section 21 RAM 21.1 Overview The H8S/2169 or H8S/2149 has 2 kbytes of on-chip high-speed static RAM. The on-chip RAM is connected to the bus master by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 21.1.1 Block Diagram Figure 21.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFE880 H'FFE881 H'FFE882 H'FFE883 H'FFE884 H'FFE885 H'FFEFFE H'FFEFFF H'FFFF00 H'FFFF01 H'FFFF7E H'FFFF7F Figure 21.1 Block Diagram of RAM 653 21.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 21.1 shows the register configuration. Table 21.1 Register Configuration Name Abbreviation R/W Initial Value Address* System control register SYSCR R/W H'09 H'FFC4 Note: * Lower 16 bits of the address. 21.2 System Control Register (SYSCR) 7 6 5 4 3 2 1 0 CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R R/W R R/W R/W R/W Bit The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip RAM is enabled 654 (Initial value) 21.3 Operation 21.3.1 Expanded Mode (Modes 1, 2, and 3 (EXPE = 1)) When the RAME bit is set to 1, accesses to H8S/2169 or H8S/2149 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the on-chip RAM. When the RAME bit is cleared to 0, accesses to addresses H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the external address space. Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to and read in byte or word units. Each type of access is performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 21.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0)) When the RAME bit is set to 1, accesses to H8S/2169 or H8S/2149 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the on-chip RAM. When the RAME bit is cleared to 0, the on-chip RAM is not accessed. Undefined values are always read from these bits, and writing is invalid. Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to and read in byte or word units. Each type of access is performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 655 656 Section 22 ROM 22.1 Overview The H8S/2169 or H8S/2149 has 64 kbytes of on-chip ROM (flash memory). The ROM is connected to the bus master by a 16-bit data bus. The bus master accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed. The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the on-chip ROM. The chip can be erased and programmed on-board as well as with a general-purpose PROM programmer. 22.1.1 Block Diagram Figure 22.1 shows a block diagram of the ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000001 H'000002 H'000003 H'00FFFE H'00FFFF Figure 22.1 ROM Block Diagram 657 22.1.2 Register Configuration The chip on-chip ROM is controlled by the operating mode and register MDCR. The register configuration is shown in table 22.1. Table 22.1 ROM Register Register Name Abbreviation R/W Initial Value Address* Mode control register MDCR R/W Undefined Depends on the operating mode H'FFC5 Note: * Lower 16 bits of the address. 22.2 Register Descriptions 22.2.1 Mode Control Register (MDCR) Bit 7 6 5 4 3 2 1 0 EXPE — — — — — MDS1 MDS0 Initial value —* 0 0 0 0 0 —* —* Read/Write R/W* — — — — — R R Note: * Determined by the MD1 and MD0 pins. MDCR is an 8-bit read-only register used to set the chip operating mode and monitor the current operating mode. The EXPE bit is initialized in accordance with the mode pin states by a reset and in hardware standby mode. Bit 7—Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, EXPE is fixed at 1 and cannot be modified. In modes 2 and 3, EXPE has an initial value of 0 and can be read or written. Bit 7 EXPE Description 0 Single-chip mode selected 1 Expanded mode selected 658 Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0. Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate values that reflects the input levels of mode pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0 correspond to pins MD1 and MD0, respectively. These are read-only bits, and cannot be modified. When MDCR is read, the input levels of mode pins MD1 and MD0 are latched in these bits. 22.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data is accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the on-chip ROM, as shown in table 22.2. In normal mode, the maximum amount of ROM that can be used is 56 kbytes. Table 22.2 Operating Modes and ROM Operating Mode MCU Operating Mode CPU Operating Mode Mode 1 Mode 2 Mode 3 Mode Pins MDCR Description MD1 MD0 EXPE On-Chip ROM Normal Expanded mode with on-chip ROM disabled 0 1 1 Disabled Advanced Single-chip mode 1 0 0 Advanced Expanded mode with on-chip ROM enabled Enabled (64 kbytes) Normal Single-chip mode Normal Expanded mode with on-chip ROM enabled 1 1 0 1 Enabled (56 kbytes) 659 22.4 Overview of Flash Memory 22.4.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units). When erasing multiple blocks, the individual blocks must be erased sequentially. Block erasing can be performed as required on 1-kbyte, 28-kbyte, 16-kbyte, and 8-kbyte blocks. • Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent to about 80 µs (typ.) per byte, and the erase time is 100 ms (typ.) per block. • Reprogramming capability The flash memory can be reprogrammed up to 100 times. • On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode • Automatic bit rate adjustment With data transfer in boot mode, the bit rate of the chip can be automatically adjusted to match the transfer bit rate of the host. • Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. • Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. 660 22.4.2 Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 Bus interface/controller FLMCR2 Operating mode Mode pins EBR1 EBR2 Flash memory (64 kbytes) Legend: FLMCR1: FLMCR2: EBR1: EBR2: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Figure 22.2 Block Diagram of Flash Memory 661 22.4.3 Flash Memory Operating Modes Mode Transitions: When the mode pins are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 22.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode. Reset state MD1 = 1 RES = 0 User mode with on-chip ROM enabled RES = 0 *2 SWE = 0 RES = 0 *1 RES = 0 SWE = 1 Programmer mode User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. MD0 = MD1 = 0, P92 = P91 = P90 = 1 2. MD0 = MD1 = 0, P92 = 0, P91 = P90 = 1 Figure 22.3 Flash Memory Mode Transitions 662 On-Board Programming Modes • Boot mode 1. Initial state The flash memory is in the erased state when the device is shipped. The description here applies to the case where the old program version or data is being rewritten. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started, an SCI communication check is carried out, and the boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Programming control program New application program New application program "#!" Host Programming control program The chip The chip SCI Boot program Flash memory RAM SCI Boot program Flash memory RAM Boot program area Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. Programming control program 4. Writing new application program The programming control program transferred from the host to RAM by SCI communication is executed, and the new application program in the host is written into the flash memory. Host Host New application program The chip The chip SCI Boot program Flash memory Flash memory RAM Programming control program RAM Boot program area Boot program area Flash memory erase SCI Boot program New application program Programming control program Program execution state Figure 22.4 Boot Mode 663 • User program mode 2. Programming/erase control program transfer The transfer program in the flash memory is executed, and the programming/erase control program is transferred to RAM. , , ! 1. Initial state (1) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. Host Host Programming/ erase control program New application program New application program The chip The chip SCI Boot program Flash memory RAM SCI Boot program Flash memory RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host Host New application program The chip The chip SCI Boot program Flash memory RAM Transfer program Flash memory RAM Transfer program Programming/ erase control program Flash memory erase SCI Boot program Programming/ erase control program New application program Program execution state Figure 22.5 User Program Mode (Example) 664 Differences between Boot Mode and User Program Mode Table 22.3 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Yes Yes Block erase No Yes Programming control program* Program/program-verify Program/program-verify Erase/erase-verify Note: To be provided by the user, in accordance with the recommended algorithm. Block Configuration: The flash memory is divided into two 8-kbyte blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks. Address H'00000 1 kbyte 1 kbyte 1 kbyte 1 kbyte 64 kbytes 28 kbytes 16 kbytes 8 kbytes 8 kbytes Address H'0FFFF Figure 22.6 Flash Memory Block Configuration 665 22.4.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 22.4. Table 22.4 Flash Memory Pins Pin Name Abbreviation I/O Function Reset RES Input Reset Mode 1 MD1 Input Sets MCU operating mode Mode 0 MD0 Input Sets MCU operating mode Port 92 P92 Input Sets MCU operating mode when MD1 = MD0 = 0 Port 91 P91 Input Sets MCU operating mode when MD1 = MD0 = 0 Port 90 P90 Input Sets MCU operating mode when MD1 = MD0 = 0 Transmit data TxD1 Output Serial transmit data output Receive data RxD1 Input Serial receive data input 22.4.5 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 22.5. In order for these registers to be accessed, the FLSHE bit must be set to 1 in STCR. Table 22.5 Flash Memory Registers Register Name Abbreviation R/W Initial Value Address* 1 Flash memory control register 1 FLMCR1* 5 R/W*3 H'80 H'FF80* 2 Flash memory control register 2 FLMCR2* 5 R/W*3 H'00* 4 H'FF81* 2 Erase block register 1 EBR1* 5 —* 3 H'00* 4 H'FF82* 2 Erase block register 2 EBR2* 5 R/W*3 H'00* 4 H'FF83* 2 Serial/timer control register STCR R/W H'00 H'FFC3 Notes: 1. Lower 16 bits of the address. 2. Flash memory registers share addresses with other registers. Register selection is performed by the FLSHE bit in the serial/timer control register (STCR). 3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. 4. When the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. 5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. 666 22.5 Register Descriptions 22.5.1 Flash Memory Control Register 1 (FLMCR1) Bit 7 6 5 4 3 2 1 0 FWE SWE — — EV PV E P Initial value 1 0 0 0 0 0 0 0 Read/Write R R/W — — R/W R/W R/W R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1. Program mode is entered by setting SWE to 1, then setting the PSU bit in FLMCR2, and finally setting the P bit. Erase mode is entered by setting SWE to 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is initialized to H'80 by a reset, and in hardware standby mode, software standby mode, subactive mode, subsleep mode, and watch mode. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to the EV and PV bits in FLMCR1 are enabled only when SWE=1; writes to the E bit only when SWE = 1, and ESU = 1; and writes to the P bit only when SWE = 1, and PSU = 1. Bit 7—Flash Write Enable (FWE): Sets hardware protection against flash memory programming/erasing. This bit cannot be modified and is always read as 1. Bit 6—Software Write Enable (SWE): Enables or disables flash memory programming. SWE should be set before setting bits ESU, PSU, EV, PV, E, P, and EB7 to EB0, and should not be cleared at the same time as these bits. Bit 6 SWE Description 0 Writes disabled 1 Writes enabled (Initial value) Bit 5 and 4—Reserved: These bits cannot be modified and are always read as 0. Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. 667 Bit 3 EV Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When SWE = 1 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV Description 0 Program-verify mode cleared 1 Transition to program-verify mode (Initial value) [Setting condition] When SWE = 1 Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E Description 0 Erase mode cleared 1 (Initial value) Transition to erase mode [Setting condition] When SWE = 1, and ESU = 1 Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P Description 0 Program mode cleared 1 Transition to program mode [Setting condition] When SWE = 1, and PSU = 1 668 (Initial value) 22.5.2 Flash Memory Control Register 2 (FLMCR2) Bit 7 6 5 4 3 2 1 0 FLER — — — — — ESU PSU Initial value 0 0 0 0 0 0 0 0 Read/Write R — — — — — R/W R/W FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, subactive mode, subsleep mode, and watch mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7 FLER Description 0 Flash memory is operating normally (Initial value) Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 22.8.3, Error Protection Bits 6 to 2—Reserved: Should always be written with 0. Bit 1—Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit to 1 in FLMCR1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. 669 Bit 1 ESU Description 0 Erase setup cleared 1 Erase setup (Initial value) [Setting condition] When SWE = 1 Bit 0—Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 0 PSU Description 0 Program setup cleared 1 Program setup (Initial value) [Setting condition] When SWE = 1 22.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) Bit 7 6 5 4 3 2 1 0 EBR1 — — — — — — — — Initial value 0 Read/Write Bit EBR2 —* 0 2 —* 0 2 —* 0 2 —* 0 2 —* 0 2 —* 0 2 —* 0 2 —* 2 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W*1 R/W R/W R/W R/W R/W R/W R/W Notes: 1. In normal mode, these bits cannot be modified and are always read as 0. 2. This bit must not be set to 1. EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 7 to 0 in EBR2 are readable/writable bits. EBR1 and EBR2 are each initialized to H'00 by a reset, in hardware standby mode, software standby mode, subactive mode, subsleep mode, and watch mode, and when the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR2 (more than one bit cannot be set). When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. 670 The flash memory block configuration is shown in table 22.6. Table 22.6 Flash Memory Erase Blocks Block (Size) Address EB0 (1 kbyte) H'(00)0000 to H'(00)03FF EB1 (1 kbyte) H'(00)0400 to H'(00)07FF EB2 (1 kbyte) H'(00)0800 to H'(00)0BFF EB3 (1 kbytes) H'(00)0C00 to H'(00)0FFF EB4 (28 kbytes) H'(00)1000 to H'(00)7FFF EB5 (16 kbytes) H'(00)8000 to H'(00)BFFF EB6 (8 kbytes) H'(00)C000 to H'(00)DFFF EB7 (8 kbytes) H'00E000 to H'00FFFF 22.5.4 Serial/Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 IICS IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode (when the on-chip IIC option is included), and on-chip flash memory, and also selects the TCNT input clock. For details on functions not related to on-chip flash memory, see section 3.2.4, Serial/Timer Control Register (STCR), and descriptions of individual modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit. STCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4—I2C Control (IICS, IICX1, IICX0, IICE): These bits control the operation of the I2C bus interface. For details, see section 16, I2C Bus Interface. 671 Bit 3—Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained. Bit 3 FLSHE Description 0 Flash memory control registers deselected 1 Flash memory control registers selected (Initial value) Bit 2—Reserved: Do not write 1 to this bit. Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits control 8-bit timer operation. See section 12, 8-Bit Timers, for details. 22.6 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 22.7. For a diagram of the transitions to the various flash memory modes, see figure 22.3. Only advanced mode setting is possible for boot mode. In the case of user program mode, established in advanced mode or normal mode, depending on the setting of the MD0 pin. In normal mode, only programming of a 56-kbyte area of flash memory is possible. Table 22.7 Setting On-Board Programming Modes Mode Mode Name CPU Operating Mode MD1 MD0 P92 P91 P90 Boot mode Advanced mode 0 0 1* 1* 1* User program mode Advanced mode 1 0 — — — 1 — — — Normal mode Note: * Can be used as I/O ports after boot mode is initiated. 672 22.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI. In the chip, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 22.7, and the boot program mode execution procedure in figure 22.8. The chip Flash memory Host Write data reception Verify data transmission RxD1 SCI1 On-chip RAM TxD1 Figure 22.7 System Configuration in Boot Mode 673 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate The chip measures low period of H'00 data transmitted by host The chip calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, trransmit one H'AA data byte to host Host transmits number of user program bytes (N), upper byte followed by lower byte The chip transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units The chip transmits received programming control program to host as verify data (echo-back) n+1→n Transfer received programming control program to on-chip RAM n = N? No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks Confirm that all flash memory data has been erased Check ID code at beginning of user program transfer area ID code match? No Yes Transmit one H'AA byte to host Transfer 1-byte of H'FF data as an ID code error indicator and halt other operations. Execute programming control program transferred to on-chip RAM Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 22.8 Boot Mode Execution Procedure 674 Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) Stop bit High period (1 or more bits) Figure 22.9 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the chip’s system clock frequency, there will be a discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the host’s transfer bit rate should be set to (4800, 9600, or 19200) bps. Table 22.8 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the chip’s bit rate is possible. The boot program should be executed within this system clock range. Table 22.8 System Clock Frequencies for which Automatic Adjustment of the Chip’s Bit Rate is Possible Host Bit Rate System Clock Frequency for which Automatic Adjustment of the Chip’s Bit Rate is Possible 19200 bps 8 MHz to 10 MHz 9600 bps 4 MHz to 10 MHz 4800 bps 2 MHz to 10 MHz On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 1920-byte area from H'(FF)E880 to H'(FF) EFFF and the 128-byte area from H'(FF)FF00 to H'(FF)FF7F is reserved for use by the boot program, as shown in figure 22.10. The area to which the programming control program is transferred is H'(FF)E080 to H'(FF)E87F (2048 bytes). However, the 8-byte area from H'(FF)E080 to H'(FF)E087 is reserved for ID codes as shown in figure 22.10. The boot program area can be used when the programming control program transferred into the reserved area enters the execution state. A stack area should be set up as required. 675 H'(FF)E080 ID code area H'(FF)E088 Programming control program area*1 (2040 bytes) H'(FF)E880 Boot program area*2 (1920 bytes) H'(FF)EFFF H'(FF)FF00 Boot program area*2 (128 bytes) H'(FF)FF7F Note: *1 This reserved area is used only for boot mode operation. Do not use this area for other purpose. *2 The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to the reserved area. Note that the boot program remains stored in this area after a branch is made to the programming control program. Figure 22.10 RAM Areas in Boot Mode In boot mode in the chip, the contents of the 8-byte ID code area shown below are checked to determine whether the program is a programming control program compatible with the chip. H'(FF)E080 40 FE 64 66 32 31 34 39 ↑ (Product ID code) H'(FF)E088 ~ Programming control program instruction codes If an original programming control program is used in boot mode, the 8-byte ID code shown above should be added at the beginning of the program. Notes on Use of Boot Mode: • When the chip comes out of reset in boot mode, it measures the low period of the input at the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the RxD1 input. 676 • In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. • Interrupts cannot be used while the flash memory is being programmed or erased. • The RxD1 and TxD1 pins should be pulled up on the board. • Before branching to the programming control program (RAM area H'(FF)E088), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P84DDR = 1, P84DR = 1). The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. The initial values of other on-chip registers are not changed. • Boot mode can be entered by making the pin settings shown in table 22.7 and executing a reset-start. When the chip detects the boot mode setting at reset release*1, P92, P91, and P90 can be used as I/O ports. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the mode pins, and executing reset release* 1. Boot mode can also be cleared by a WDT overflow reset. The mode pin input levels must not be changed in boot mode. • If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode*2. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pins input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. 2. Ports with multiplexed address functions will output a low level as the address signal if mode pin setting is for mode 1 is entered during a reset. In other modes, the port pins go to the high-impedance state. The bus control output signals will output a high level if mode pin setting is for mode 1 is entered during a reset. In other modes, the port pins go to the high-impedance state. 677 22.6.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing an on-board means of supplying programming data, and storing a program/erase control program in part of the program area as necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 2 or 3). In this mode, on-chip supporting modules other than flash memory operate as they normally would in mode 2 and 3. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. Figure 22.11 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the transfer program (and the program/erase control program if necessary) beforehand MD1, MD0 = 10, 11 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area Execute program/erase control program (flash memory rewriting) Branch to flash memory application program Note: The watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Figure 22.11 User Program Mode Execution Procedure 678 22.7 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in FLMCR1, and the ESU and PSU bits in FLMCR2, is executed by a program in flash memory. 2. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. 22.7.1 Program Mode Follow the procedure shown in the program/program-verify flowchart in figure 22.12 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. The wait times (x, y, z1, z2, z3, α, ß, γ, ε, η, θ) after setting/clearing individual bits in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of writes (N) are shown in section 25, Electrical Characteristics, Flash Memory Characteristics. Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the reprogram data area written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z2 + α + β) µs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (z1), (z2) or (z3) µs. 679 22.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared, then the PSU bit in FLMCR2 is cleared at least (α) µs later). The watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to programverify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 22.12) and transferred to the reprogram data area. After 128 bytes of data have been verified, exit program-verify mode, wait for at least (η) µs. If the programming count is less than 6, the 128-byte data in the additional program data area should be written consecutively to the write addresses, and additional programming performed. Next clear the SWE bit in FLMCR1, and wait at least (θ) µs . If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. 680 Write pulse application subroutine Sub-routine write pulse Start of programming Start Enable WDT Set SWE bit in FLMCR1 Set PSU bit in FLMCR2 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. Wait (x) µs Wait (y) µs Store 128-byte program data in program data area and reprogram data area Set P bit in FLMCR1 Wait (z1) µs, (z2) µs or (z3) µs *4 n=1 *5 m=0 Clear P bit in FLMCR1 Wait (α) µs Write 128-byte data in RAM reprogram data *1 area consecutively to flash memory Sub-routine-call Write pulse See Note 7 for pulse width (z1) µs or (z2) µs Clear PSU bit in FLMCR2 Wait (β) µs Disable WDT Set PV bit in FLMCR1 End sub Wait (γ) µs H'FF dummy write to verify address Wait (ε) µs Increment address Read verify data Note 7: Write Pulse Width Number of Writes n Write Time (z) µs z1 1 2 z1 3 z1 4 z1 5 z1 z1 6 7 z2 8 z2 9 z2 10 z2 11 z2 12 z2 13 z2 .. .. . . 998 z2 z2 999 1000 z2 Note: Use a (z3) µs write pulse for additional programming. Program data = verify data? *2 n←n+1 NG m=1 OK 6 ≥ n? NG OK Additional program data computation Transfer additional program data to additional program data area *4 Reprogram data computation *3 Transfer reprogram data to reprogram data area *4 NG End of 128-byte data verification? OK Clear PV bit in FLMCR1 Wait (η) µs 6 ≥ n? RAM NG OK Write 128-byte data in additional program data area in RAM consecutively to flash memory Program data storage area (128 bytes) *1 Additional write pulse (z3) µs Reprogram data storage area (128 bytes) m = 0? Additional program data storage area (128 bytes) NG OK Clear SWE bit in FLMCR1 n ≥ 1000? NG OK Clear SWE bit in FLMCR1 Wait (θ) µs Wait (θ) µs End of programming Programming failure Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the subsequent verify operation. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data must be provided in RAM. The reprogram and additional program data contents are modified as programming proceeds. 5. The write pulse of (z1) µs or (z2) µs is applied according to the progress of the programming operation. See Note 7 for the pulse widths. When writing of additional program data is executed, a (z3) µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. 6. See section 25, Electrical Characteristics, Flash Memory Characteristics, for the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N. Program Data Computation Chart Original Data (D) Verify Data (V) 0 0 1 1 0 1 Reprogram Data (X) 1 0 1 1 Comments Programming completed Programming incomplete; reprogram Still in erased state; no action Additional Program Data Computation Chart Reprogram Data (X') Verify Data (V) Additional Program Data (Y) Comments Additional programming executed 0 0 0 Additional programming not executed 1 1 1 0 1 Additional programming not executed 1 1 Figure 22.12 Program/Program-Verify Flowchart 681 22.7.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 22.13. The wait times (x, y, z, α, β, γ, ε, η, θ) after setting/clearing individual bits in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of erase (N) are shown in section 25, Electrical Characteristics, Flash Memory Characteristics. To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) µs after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + α + β) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR2, and after the elapse of (y) µs or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 22.7.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the ESU bit in FLMCR2 is cleared at least (α) µs later), the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/eraseverify sequence is not repeated more than (N) times. When verification is completed, exit eraseverify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1, and wait (θ) µs. If there are any unerased blocks, make a 1 bit setting in EBR1 or EBR2 for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way. 682 Start *1 Set SWE bit in FLMCR1 Wait (x) µs *5 n=1 Set EBR1, EBR2 *3 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs *5 Start of erase Set E bit in FLMCR1 Wait (z) ms *5 Clear E bit in FLMCR1 n←n+1 Halt erase Wait (α) µs *5 Clear ESU bit in FLMCR2 Wait (β) µs *5 Disable WDT Set EV bit in FLMCR1 Wait (γ) µs *5 Set block start address to verify address H'FF dummy write to verify address Increment address Wait (ε) µs *5 Read verify data *2 Verify data = all 1? NG OK NG Last address of block? OK Clear EV bit in FLMCR1 Clear EV bit in FLMCR1 Wait (η) µs Wait (η) µs *5 *5 NG Notes: 1. 2. 3. 4. 5. *4 End of erasing of all erase blocks? OK *5 n ≥ N? Clear SWE bit in FLMCR1 OK Clear SWE bit in FLMCR1 Wait (θ) µs Wait (θ) µs End of erasing Erase failure NG Preprogramming (setting erase block data to all 0) is not necessary. Verify data is read in 16-bit (W) units. Set only one bit in EBR1or EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. See section 25, Electrical Characteristics, Flash Memory Characteristics, for the values of x, y, z, α, β, γ, ε, η, θ, and N. Figure 22.13 Erase/Erase-Verify Flowchart (Single-Block Erase) 683 22.8 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 22.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). (See table 22.9.) Table 22.9 Hardware Protection Functions Item Description Program Erase Reset/standby protection • In a reset (including a WDT overflow reset) and in hardware standby mode, software standby mode, subactive mode, subsleep mode, and watch mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. Yes Yes • In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 22.8.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1 and erase block registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase mode. (See table 22.10.) 684 Table 22.10 Software Protection Functions Item Description Program Erase SWE bit protection • Yes Yes — Yes Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks. (Execute in on-chip RAM or external memory.) Block specification protection 22.8.3 • Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2). • Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: • When flash memory is read during programming/erasing (including a vector read or instruction fetch) • Immediately after exception handling (excluding a reset) during programming/erasing • When a SLEEP instruction (including software standby, sleep, subactive, subsleep and watch mode) is executed during programming/erasing • When the bus is released during programming/erasing Error protection is released only by a reset and in hardware standby mode. Figure 22.14 shows the flash memory state transition diagram. 685 Normal operation mode Program mode Erase mode RES = 0 or STBY = 0 Reset or hardware standby (hardware protection) RD VF PR ER FLER = 0 RD VF PR ER FLER = 0 Error occurrence*2 RES = 0 or STBY = 0 Error occurrence*1 RES = 0 or STBY = 0 Software standby, sleep, subsleep, and watch mode Error protection mode RD VF*4 PR ER FLER = 1 Software standby, sleep, subsleep, and watch mode release FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode (software standby, sleep, subsleep, and watch ) RD VF PR ER FLER = 1 FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2 initialization state*3 Legend: RD: VF: PR: ER: Memory read possible Verify-read possible Programming possible Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Notes: 1. When an error occurs other than due to a SLEEP instruction, or when a SLEEP instruction is executed for a transition to subactive mode 2. When an error occurs due to a SLEEP instruction (except subactive mode) 3. Except sleep mode 4. VF in subactive mode Figure 22.14 Flash Memory State Transitions 22.9 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. 686 For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All interrupt requests, including NMI input, must therefore be disabled inside and outside the MCU when programming or erasing flash memory. Interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: • If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). • If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 22.10 Flash Memory Programmer Mode 22.10.1 Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Hitachi microcomputer device types with 64-kbyte on-chip flash memory*. For precautions concerning the use of programmer mode, see section 22.10.10, Notes on Memory Programming and section 22.11, Flash Memory Programming and Erasing Precausions. Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with these device types. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. Table 22.11 shows programmer mode pin settings. Note: Set the programming voltage of the PROM programmer to 3.3 V before using the chip. 687 Table 22.11 Programmer Mode Pin Settings Pin Names Setting/External Circuit Connection Mode pins: MD1, MD0 Low-level input to MD1, MD0 STBY pin High-level input (Hardware standby mode not set) RES pin Power-on reset circuit XTAL and EXTAL pins Oscillation circuit Other setting pins: P97, P92, P91, P90, P67 Low-level input to p92, p67, high-level input to P97, P91, P90 22.10.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is mounted on the writer programmer to match the package concerned. Socket adapters are available for each manufacturer supporting Hitachi microcomputer device types with 64-kbyte on-chip flash memory. Figure 22.15 shows the memory map in programmer mode. For pin names in programmer mode, see section 1.3.2, Pin Functions in Each Operating Mode. MCU mode The chip H'000000 Programmer mode H'00000 On-chip ROM area H'00FFFF H'0FFFF Undefined value output H'1FFFF Figure 22.15 Memory Map in Programmer Mode 22.10.3 Programmer Mode Operation Table 22.12 shows how the different operating modes are set when using programmer mode, and table 22.13 lists the commands used in programmer mode. Details of each mode are given below. • Memory Read Mode Memory read mode supports byte reads. • Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. 688 • Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. • Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the FO6 signal. In status read mode, error information is output if an error occurs. Table 22.12 Settings for Each Operating Mode in Programmer Mode Pin Names Mode CE OE WE FO0 to FO7 FA0 to FA17 Read L L H Data output Ain Output disable L H H Hi-z X Command write L H L Data input Ain* 2 Chip disable* 1 H X X Hi-z X Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. Table 22.13 Programmer Mode Commands 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read mode 1+n Write X H'00 Read RA Dout Auto-program mode 129 Write X H'40 Write WA Din Auto-erase mode 2 Write X H'20 Write X H'20 Status read mode 2 Write X H'71 Write X H'71 Notes: 1. In auto-program mode. 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 689 22.10.4 Memory Read Mode • After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. • Command writes can be performed in memory read mode, just as in the command wait state. • Once memory read mode has been entered, consecutive reads can be performed. • After power-on, memory read mode is entered. Table 22.14 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns WE rise time tr — 30 ns WE fall time tf — 30 ns Memory read mode Command write FA17 to FA0 Address stable CE OE WE FO7 to FO0 twep tceh tnxtc tces tf tr Data Data tdh tds Note: Data is latched on the rising edge of WE. Figure 22.16 Memory Read Mode Timing Waveforms after Command Write 690 Table 22.15 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns WE rise time tr — 30 ns WE fall time tf — 30 ns Memory read mode FA17 to FA0 Other mode command write Address stable CE twep tnxtc OE tces WE FO7 to FO0 tceh tf Data tr H'XX tdh Note: Do not enable WE and OE at the same time. tds Figure 22.17 Timing Waveforms when Entering Another Mode from Memory Read Mode 691 Table 22.16 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Access time t acc — 20 µs CE output delay time t ce — 150 ns OE output delay time t oe — 150 ns Output disable delay time t df — 100 ns Data output hold time t oh 5 — ns FA17 to FA0 Address stable Address stable CE VIL OE VIL tacc WE VIH tacc toh toh Data FO7 to FO0 Data Figure 22.18 Timing Waveforms for CE/OE Enable State Read FA17 to FA0 Address stable Address stable tacc CE tce tce OE toe toe WE FO7 to FO0 Data Data toh Figure 22.19 Timing Waveforms for CE/OE Clocked Read 692 tdf tdf tacc toh VIH 22.10.5 Auto-Program Mode AC Characteristics Table 22.17 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns Status polling start time t wsts 1 — ms Status polling access time t spa — 150 ns Address setup time t as 0 — ns Address hold time t ah 60 — ns Memory write time t write 1 3000 ms WE rise time tr — 30 ns WE fall time tf — 30 ns Address stable FA17 to FA0 tceh tas CE tah tnxtc OE tnxtc twep WE FO7 Data transfer 1 byte to 128 bytes tces twsts tspa twrite (1 to 3000 ms) Programming operation end identification signal tr tf tds tdh Programming normal end identification signal FO6 Programming wait FO7 to FO0 H'40 Data Data FO0 to 5 = 0 Figure 22.20 Auto-Program Mode Timing Waveforms 693 Notes on Use of Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. • A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. • The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. • Memory address transfer is performed in the second cycle (figure 22.20). Do not perform transfer after the second cycle. • Do not perform a command write during a programming operation. • Perform one auto-programming operation for a 128-byte block for each address. Characteristics are not guaranteed for two or more programming operations. • Confirm normal end of auto-programming by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-program operation end identification pin). • The status polling FO6 and FO7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling CE and OE. 22.10.6 Auto-Erase Mode AC Characteristics Table 22.18 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns Status polling start time t ests 1 — ms Status polling access time t spa — 150 ns Memory erase time t erase 100 40000 ms WE rise time tr — 30 ns WE fall time tf — 30 ns 694 FA17 to FA0 tceh tces CE tspa OE WE tnxtc twep tf tests tr terase (100 to 40000 ms) tds FO7 tdh Erase normal end confirmation signal FO6 FO7 to FO0 tnxtc Erase end identification signal CLin DLin H'20 H'20 FO0 to FO5 = 0 Figure 22.21 Auto-Erase Mode Timing Waveforms Notes on Use of Auto-Erase-Program Mode • Auto-erase mode supports only entire memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-erase operation end identification pin). • The status polling FO6 and FO7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling CE and OE. 695 22.10.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. • The return code is retained until a command write for other than status read mode is performed. Table 22.19 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle t nxtc 20 — µs CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns OE output delay time t oe — 150 ns Disable delay time t df — 100 ns CE output delay time t ce — 150 ns WE rise time tr — 30 ns WE fall time tf — 30 ns FA17 to FA0 CE tnxtc tce OE tnxtc twep WE tceh tces tf tr tceh tces tf toe tdf tr tds tds FO7 to FO0 tnxtc twep tdh tdh H'71 H'71 Data Note: FO2 and FO3 are undefined. Figure 22.22 Status Read Mode Timing Waveforms 696 Table 22.20 Status Read Mode Return Commands Pin Name FO7 Attribute FO6 Normal Command end error identification Initial value 0 0 Indications Normal end: 0 Command error: 1 Abnormal end: 1 FO5 FO4 FO3 FO2 FO1 Programming error Erase error — — ProgramEffective ming or address error erase count exceeded 0 0 0 0 0 — Count Effective exceeded: 1 address Otherwise: 0 error: 1 ProgramErase — ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 FO0 0 Otherwise: 0 Note: FO2 and FO3 are undefined. 22.10.8 Status Polling • The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode. • The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 22.21 Status Polling Output Truth Table Pin Names Internal Operation in Progress Abnormal End — Normal End FO7 0 1 0 1 FO6 0 0 1 1 FO0 to FO5 0 0 0 0 22.10.9 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 22.22 Command Wait State Transition Time Specifications Item Symbol Min Max Unit Standby release (oscillation stabilization time) t osc1 20 — ms Programmer mode setup time t bmv 10 — ms VCC hold time t dwn 0 — ms 697 VCC RES tosc1 tbmv tdwn Memory read Auto-program mode mode Auto-erase mode Command wait state Command Don't care wait state Normal/ abnormal end identification Command acceptance Figure 22.23 Oscillation Stabilization Time, Programmer Mode Setup Time, and Power Supply Fall Sequence 22.10.10 Notes On Memory Programming • When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. • When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. 22.11 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode and programmer mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports 3.3 V programming voltage for Hitachi microcomputer device types with 64-kbyte on-chip flash memory. Do not select the HN28F101 setting for the PROM programmer or 5.0 V setting for the programming voltage, and only use the specified socket adapter. Incorrect use will result in damaging the device. Powering on and off: When applying or disconnecting VCC, fix the RES pin low and place the flash memory in the hardware protection state. 698 The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Do not set or clear the SWE bit during program execution in flash memory. Wait for at least 100 µs after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but when SWE = 1 the flash memory can only be read in program-verify or erase-verify mode. Flash memory should only be accessed for verify operations (verification during programming/erasing). Do not clear the SWE bit during a program, erase, or verify operation. Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled when programming and erasing flash memory to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming. In onboard programming, perform only one programming operation on a 128-byte programming unit block. In writer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. 699 700 Section 23 Clock Pulse Generator 23.1 Overview The H8S/2169 and H8S/2149 have a built-in clock pulse generator (CPG) that generates the system clock (ø), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty-cycle adjustment circuit, clock selection circuit, medium-speed clock divider, bus-master clock selection circuit, subclock input circuit, and waveform shaping circuit. 23.1.1 Block Diagram Figure 23.1 is a block diagram of the clock pulse generator. EXTAL Oscillator XTAL Duty-cycle adjustment circuit Medium-speed clock divider Clock selection circuit øSUB EXCL Subclock input circuit Waveform shaping circuit ø/2 to ø/32 Bus-master clock selection circuit ø System clock To ø pin Internal clock To supporting modules Bus master clock To CPU, DTC WDT1 count clock Figure 23.1 Block Diagram of Clock Pulse Generator 23.1.2 Register Configuration The clock pulse generator is controlled by the standby control register (SBYCR) and low-power control register (LPWRCR). Table 23.1 shows the register configuration. 701 Table 23.1 CPG Registers Name Abbreviation R/W Initial Value Address* Standby control register SBYCR R/W H'00 H'FF84 Low-power control register LPWRCR R/W H'00 H'FF85 Note: * Lower 16 bits of the address. 23.2 Register Descriptions 23.2.1 Standby Control Register (SBYCR) Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 — SCK2 SCK1 SCK0 0 0 0 R/W R/W Initial value 0 0 0 0 0 Read/Write R/W R/W R/W R/W — R/W SBYCR is an 8-bit readable/writable register that performs power-down mode control. Only bits 0 to 2 are described here. For a description of the other bits, see section 24.2.1, Standby Control Register (SBYCR). SBYCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock for high-speed mode and medium-speed mode. When operating the device after a transition to subactive mode or watch mode bits SCK2 to SCK0 should all be cleared to 0. Bit 2 Bit 1 Bit 0 SCK2 SCK1 SCK0 Description 0 0 0 Bus master is in high-speed mode 1 Medium-speed clock is ø/2 0 Medium-speed clock is ø/4 1 Medium-speed clock is ø/8 0 Medium-speed clock is ø/16 1 Medium-speed clock is ø/32 — — 1 1 0 1 702 (Initial value) 23.2.2 Low-Power Control Register (LPWRCR) Bit 7 6 5 4 3 2 1 0 DTON LSON NESEL EXCLE — — — — 0 0 0 Initial value 0 0 0 0 0 Read/Write (H8S/2169) R/W R/W R/W R/W R/W — — — Read/Write (H8S/2149) R/W R/W R/W R/W — — — — LPWRCR is an 8-bit readable/writable register that performs power-down mode control. Only bit 4 is described here. For a description of the other bits, see section 24.2.2, Low-Power Control Register (LPWRCR). LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 4—Subclock Input Enable (EXCLE): Controls subclock input from the EXCL pin. Bit 4 EXCLE Description 0 Subclock input from EXCL pin is disabled 1 Subclock input from EXCL pin is enabled 23.3 (Initial value) Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 23.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 23.2. Select the damping resistance Rd according to table 23.2. An AT-cut parallel-resonance crystal should be used. 703 CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22pF Figure 23.2 Connection of Crystal Resonator (Example) Table 23.2 Damping Resistance Value Frequency (MHz) 2 4 8 10 Rd (Ω) 1k 500 200 0 Crystal resonator: Figure 23.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 23.3 and the same frequency as the system clock (ø). CL L Rs XTAL EXTAL AT-cut parallel-resonance type C0 Figure 23.3 Crystal Resonator Equivalent Circuit Table 23.3 Crystal Resonator Parameters Frequency (MHz) 2 4 8 10 RS max (Ω) 500 120 80 70 C0 max (pF) 7 7 7 7 Note on Board Design: When a crystal resonator is connected, the following points should be noted. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 23.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. 704 Avoid Signal A Signal B The chip CL2 XTAL EXTAL CL1 Figure 23.4 Example of Incorrect Board Design 23.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 23.5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode. EXTAL XTAL External clock input Open (a) XTAL pin left open EXTAL External clock input XTAL (b) Complementary clock input at XTAL pin Figure 23.5 External Clock Input (Examples) External Clock: The external clock signal should have the same frequency as the system clock (ø). 705 Table 23.4 and figure 23.6 show the input conditions for the external clock. Table 23.4 External Clock Input Conditions VCC = 2.7 to 3.6 V Item Symbol Min Max Unit Test Conditions External clock input low pulse width t EXL 40 — ns Figure 23.6 External clock input high pulse width t EXH 40 — ns External clock rise time t EXr — 10 ns External clock fall time t EXf — 10 ns Clock low pulse width t CL 0.4 0.6 t cyc ø ≥ 5 MHz Figure 25.4 80 — ns ø < 5 MHz 0.4 0.6 t cyc ø ≥ 5 MHz 80 — ns ø < 5 MHz Clock high pulse width t CH tEXH tEXL VCC × 0.5 EXTAL tEXr tEXf Figure 23.6 External Clock Input Timing Table 23.5 shows the external clock output settling delay time, and figure 23.7 shows the external clock output settling delay timing. The oscillator and duty adjustment circuit have a function for adjusting the waveform of the external clock input at the EXTAL pin. When the prescribed clock signal is input at the EXTAL pin, internal clock signal output is fixed after the elapse of the external clock output settling delay time (tDEXT). As the clock signal output is not fixed during the tDEXT period, the reset signal should be driven low to maintain the reset state. 706 Table 23.5 External Clock Output Settling Delay Time Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0 V Item Symbol Min Max Unit Notes External clock output settling delay time t DEXT* 500 — µs Figure 23.7 Note: * t DEXT includes RES pulse width (t RESW). VCC 2.7V STBY VIH EXTAL ø (internal or external) RES tDEXT* Note: * tDEXT includes RES pulse width (tRESW). Figure 23.7 External Clock Output Settling Delay Timing 707 23.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (ø). 23.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32 clocks. 23.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed clocks (ø/2, ø/4, ø/8, ø/16, or ø/32) to be supplied to the bus master, according to the settings of bits SCK2 to SCK0 in SBYCR. 23.7 Subclock Input Circuit The subclock input circuit controls the subclock input from the EXCL pin. Inputting the Subclock: When a subclock is used, a 32.768 kHz external clock should be input from the EXCL pin. In this case, clear bit P96DDR to 0 in P9DDR and set bit EXCLE to 1 in LPWRCR. The subclock input conditions are shown in table 23.6 and figure 23.8. Table 23.6 Subclock Input Conditions VCC = 2.7 to 3.6 V Item Min Typ Max Unit Test Conditions Subclock input low pulse t EXCLL width — 15.26 — µs Figure 23.8 Subclock input high pulse t EXCLH width — 15.26 — µs Subclock input rise time t EXCLr — — 10 ns Subclock input fall time t EXCLf — — 10 ns 708 Symbol tEXCLH tEXCLL VCC × 0.5 EXCL tEXCLr tEXCLf Figure 23.8 Subclock Input Timing When Subclock is not Needed: Do not enable subclock input when the subclock is not needed 23.8 Subclock Waveform Shaping Circuit To eliminate noise in the subclock input from the EXCL pin, this circuit samples the clock using a clock obtained by dividing the ø clock. The sampling frequency is set with the NESEL bit in LPWRCR. For details, see section 24.2.2, Low-Power Control Register (LPWRCR). The clock is not sampled in subactive mode, subsleep mode, or watch mode. 23.9 Clock Selection Circuit This circuit selects the system clock used in the MCU. The clock signal generated in the EXTAL/XTAL oscillator is selected as a system clock, when the MCU is returned from high-speed mode, medium-speed mode, sleep mode, reset state, standby mode. In sub-active mode, sub-sleep mode and watch mode, the sub-clock signal input from or EXCL pin is selected as a sytem clock. In these modes, modules, such as CPU, TMR0, TMR1, WDT0, WDT1, and I/O ports, operate on ø SUB clock. In addition, the count clock and sampling clock are derived by frequency division from ø SUB. Note: See figure 23.1. 709 23.10 X1 and X2 Pins Leave the X1 and X2 pins open, as shown in figure 23.9. X1 Open X2 Open Figure 23.9 X1 and X2 Pins 710 Section 24 Power-Down State 24.1 Overview In addition to the normal program execution state, the H8S/2169 or H8S/2149 has a power-down state in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2169 or H8S/2149 operating modes are as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. High-speed mode Medium-speed mode Subactive mode Sleep mode Subsleep mode Watch mode Module stop mode Software standby mode Hardware standby mode Of these, 2 to 9 are power-down modes. Sleep mode and subsleep mode are CPU modes, mediumspeed mode is a CPU and bus master mode, subactive mode is a CPU, bus master, and on-chip supporting module mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the CPU). Certain combinations of these modes can be set. After a reset, the MCU is in high-speed mode and module stop mode (excluding the DTC). Table 24.1 shows the internal chip states in each mode, and table 24.2 shows the conditions for transition to the various modes. Figure 24.1 shows a mode transition diagram. 711 Table 24.1 The Chip’s Internal States in Each Mode Function HighSpeed MediumSpeed System clock oscillator Functioning Function- Functioning ing Function- Halted ing Halted Subclock input Functioning Function- Functioning ing Function- Functioning ing CPU operation Functioning Mediumspeed Function- Halted ing Retained Retained Retained Functioning Function- Functioning ing Function- Functioning ing Function- Functioning ing Function- Halted ing Functioning Mediumspeed Functioning Function- Halted ing/halted (retained) (retained) Halted Halted (retained) (retained) Halted Halted (retained) (reset) Functioning Function- Functioning ing Function- Subclock ing operation Subclock Subclock operation operation Halted Halted (retained) (reset) Instructions Registers External interrupts NMI Sleep Halted Module Stop Watch Software Hardware Subactive Subsleep Standby Standby Halted Halted Halted Function- Functioning ing Halted Halted Subclock Halted operation Halted Halted Retained Undefined IRQ0 IRQ1 IRQ2 On-chip DTC supporting module operation WDT1 WDT0 TMR0, 1 Functioning/halted (retained) FRT Halted (retained) TMRX, Y Halted Halted (retained) (retained) Timer connection IIC0 IIC1 HIF:LPC SCI0 Function- Halted ing/halted (reset) (reset) SCI1 Halted (reset) Halted (reset) Halted (reset) SCI2 PWM PWMX HIF:XBS, PS2 D/A A/D RAM Functioning Function- Function- Function- Retained ing ing (DTC) ing Function- Retained ing Retained Retained I/O Functioning Function- Functioning ing Function- Functioning ing Retained High impedance Function- Retained ing Note: “Halted (retained)” means that internal register values are retained. The internal state is “operation suspended.” “Halted (reset)” means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 712 Program-halted state STBY pin = low Reset state STBY pin = high RES pin = low Hardware standby mode RES pin = high Program execution state SSBY = 0, LSON = 0 High-speed mode (main clock) SCK2 to SCK0 = 0 SCK2 to SCK0 ≠ 0 Medium-speed mode (main clock) SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 0 Clock switching exception handling after oscillation setting time (STS2 to STS0) SLEEP instruction Any interrupt*3 SLEEP instruction External interrupt*4 SSBY = 1 PSS = 0, LSON = 0 Software standby mode SLEEP instruction Interrupt*1, SLEEP instruction SSBY = 1, PSS = 1, LSON bit = 0 DTON = 1, LSON = 1 Clock switching SLEEP exception handling instruction Interrupt*1, LSON bit = 1 Subactive mode (subclock) Sleep mode (main clock) SLEEP instruction Interrupt*2 : Transition after exception handling SSBY = 1 PSS = 1, DTON = 0 Watch mode (subclock) SSBY = 0 PSS = 1, LSON = 1 Subsleep mode (subclock) : Power-down mode Notes: • When a transition is made between modes by means of an interrupt, transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. • From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. • From any state, a transition to hardware standby mode occurs when STBY goes low. • When a transition is made to watch mode or subactive mode, high-speed mode must be set. *1 *2 *3 *4 NMI, IRQ0 to IRQ2, IRQ6, IRQ7, and WDT1 interrupts NMI, IRQ0 to IRQ7, and WDT0 interrupts, WDT1 interrupt, TMR0 interrupt, TMR1 interrupt All interrupts NMI, IRQ0 to IRQ2, IRQ6, IRQ7 Figure 24.1 Mode Transitions 713 Table 24.2 Power-Down Mode Transition Conditions Control Bit States at Time of Transition State before Transition PSS LSON DTON State after Transition State after Return by SLEEP Instruction by Interrupt High-speed/ 0 medium-speed * 0 * Sleep High-speed/ medium-speed 0 * 1 * — — 1 0 0 * Software standby High-speed/ medium-speed 1 0 1 * — — 1 1 0 0 Watch High-speed 1 1 1 0 Watch Subactive 1 1 0 1 — — 1 1 1 1 Subactive — 0 0 * * — — 0 1 0 * — — 0 1 1 * Subsleep Subactive 1 0 * * — — 1 1 0 0 Watch High-speed 1 1 1 0 Watch Subactive 1 1 0 1 High-speed — 1 1 1 1 — — Subactive *: Don’t care —: Do not set. 714 SSBY 24.1.1 Register Configuration The power-down state is controlled by the SBYCR, LPWRCR, TCSR (WDT1), and MSTPCR registers. Table 24.3 summarizes these registers. Table 24.3 Power-Down State Registers Name Abbreviation R/W Initial Value Address* 1 Standby control register SBYCR R/W H'00 H'FF84* 2 Low-power control register LPWRCR R/W H'00 H'FF85* 2 Timer control/status register (WDT1) TCSR R/W H'00 H'FFEA Module stop control register MSTPCRH R/W H'3F H'FF86* 2 MSTPCRL R/W H'FF H'FF87* 2 Notes: 1. Lower 16 bits of the address. 2. A CPU access to some of the control registers in the power-down state is controlled by the FLSHE bit of the serial/timer control register (STCR). 24.2 Register Descriptions 24.2.1 Standby Control Register (SBYCR) Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 — SCK2 SCK1 SCK0 0 0 0 R/W R/W Initial value 0 0 0 0 0 Read/Write R/W R/W R/W R/W — R/W SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Software Standby (SSBY): Determines the operating mode, in combination with other control bits, when a power-down mode transition is made by executing a SLEEP instruction. The SSBY setting is not changed by a mode transition due to an interrupt, etc. 715 Bit 7 SSBY Description 0 Transition to sleep mode after execution of SLEEP instruction in high-speed mode or medium-speed mode (Initial value) Transition to subsleep mode after execution of SLEEP instruction in subactive mode 1 Transition to software standby mode, subactive mode, or watch mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to watch mode or high-speed mode after execution of SLEEP instruction in subactive mode Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when software standby mode, watch mode, or subactive mode is cleared and a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt or instruction. With crystal oscillation, refer to table 24.4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation settling time). With an external clock, any selection can be made. Bit 6 Bit 5 Bit 4 STS2 STS1 STS0 Description 0 0 0 Standby time = 8192 states 1 Standby time = 16384 states 0 Standby time = 32768 states 1 Standby time = 65536 states 0 Standby time = 131072 states 1 Standby time = 262144 states 0 Reserved 1 Standby time = 16 states* 1 1 0 1 Note: * This setting must not be used in the flash memory version. Bit 3—Reserved: This bit cannot be modified and is always read as 0. 716 (Initial value) Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master in high-speed mode and medium-speed mode. When operating the device after a transition to subactive mode or watch mode, bits SCK2 to SCK0 should all be cleared to 0. Bit 2 Bit 1 Bit 0 SCK2 SCK1 SCK0 Description 0 0 0 Bus master is in high-speed mode 1 Medium-speed clock is ø/2 0 Medium-speed clock is ø/4 1 Medium-speed clock is ø/8 0 Medium-speed clock is ø/16 1 Medium-speed clock is ø/32 — — 1 1 0 1 24.2.2 (Initial value) Low-Power Control Register (LPWRCR) 7 6 5 4 3 2 1 0 DTON LSON NESEL EXCLE — — — — Initial value 0 0 0 0 0 0 0 0 Read/Write (H8S/2169) R/W R/W R/W R/W R/W — — — Read/Write (H8S/2149) R/W R/W R/W R/W — — — — Bit LPWRCR is an 8-bit readable/writable register that performs power-down mode control. LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Direct-Transfer On Flag (DTON): Specifies whether a direct transition is made between high-speed mode, medium-speed mode, and subactive mode when making a power-down transition by executing a SLEEP instruction. The operating mode to which the transition is made after SLEEP instruction execution is determined by a combination of other control bits. 717 Bit 7 DTON Description 0 When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode (Initial value) 1 When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode*, or a transition is made to sleep mode or software standby mode When a SLEEP instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be set. Bit 6—Low-Speed On Flag (LSON): Determines the operating mode in combination with other control bits when making a power-down transition by executing a SLEEP instruction. Also controls whether a transition is made to high-speed mode or to subactive mode when watch mode is cleared. Bit 6 LSON Description 0 When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode After watch mode is cleared, a transition is made to high-speed mode 1 (Initial value) When a SLEEP instruction is executed in high-speed mode a transition is made to watch mode or subactive mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode After watch mode is cleared, a transition is made to subactive mode Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be set. Bit 5—Noise Elimination Sampling Frequency Select (NESEL): Selects the frequency at which the subclock (øSUB) input from the EXCL pin is sampled with the clock (ø) generated by the system clock oscillator. When ø = 5 MHz or higher, clear this bit to 0. 718 Bit 5 NESEL Description 0 Sampling at ø divided by 32 1 Sampling at ø divided by 4 (Initial value) Bit 4—Subclock Input Enable (EXCLE): Controls subclock input from the EXCL pin. Bit 4 EXCLE Description 0 Subclock input from EXCL pin is disabled 1 Subclock input from EXCL pin is enabled (Initial value) Bit 3 (H8S/2149)—Reserved: These bits cannot be modified and are always read as 0. Bit 3 (H8S/2169)—Reserved: Do not write 1 to this bit. Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0. 24.2.3 Timer Control/Status Register (TCSR) TCSR1 7 6 5 4 3 2 1 0 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Bit Note: * Only 0 can be written in bit 7, to clear the flag. TCSR1 is an 8-bit readable/writable register that performs selection of the WDT1 TCNT input clock, mode, etc. Only bit 4 is described here. For details of the other bits, see section 14.2.2, Timer Control/Status Register (TCSR). TCSR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. 719 Bit 4—Prescaler Select (PSS): Selects the WDT1 TCNT input clock. This bit also controls the operation in a power-down mode transition. The operating mode to which a transition is made after execution of a SLEEP instruction is determined in combination with other control bits. For details, see the description of Clock Select 2 to 0 in section 14.2.2, Timer Control/Status Register (TCSR). Bit 4 PSS Description 0 TCNT counts ø-based prescaler (PSM) divided clock pulses When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode or software standby mode (Initial value) 1 TCNT counts øSUB-based prescaler (PSS) divided clock pulses When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, watch mode*, or subactive mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode, watch mode, or high-speed mode Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be set. 24.2.4 Module Stop Control Register (MSTPCR) MSTPCRH Bit 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value Read/Write 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. 720 MSTPCRH and MSTPCRL Bits 7 to 0—Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See table 24.4 for the method of selecting on-chip supporting modules. MSTPCRH, MSTPCRL Bits 7 to 0 MSTP15 to MSTP0 Description 0 Module stop mode is cleared (Initial value of MSTP15, MSTP14) 1 Module stop mode is set (Initial value of MSTP13 to MSTP0) 24.3 Medium-Speed Mode When the SCK2 to SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0 bits. The bus master other than the CPU (the DTC) also operates in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (ø). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if ø/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, and the LSON bit in LPWRCR and the PSS bit in TCSR (WDT1) are both cleared to 0, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 24.2 shows the timing for transition to and clearance of medium-speed mode. 721 Medium-speed mode ø, supporting module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 24.2 Medium-Speed Mode Transition and Clearance Timing 24.4 Sleep Mode 24.4.1 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained. Other supporting modules do not stop. 24.4.2 Clearing Sleep Mode Sleep mode is cleared by any interrupt, or with the RES pin or STBY pin. Clearing with an Interrupt: When an interrupt request signal is input, sleep mode is cleared and interrupt exception handling is started. Sleep mode will not be cleared if interrupts are disabled, or if interrupts other than NMI have been masked by the CPU. Clearing with the RES Pin: When the RES pin is driven low, the reset state is entered. When the RES pin is driven high after the prescribed reset input period, the CPU begins reset exception handling. Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware standby mode. 722 24.5 Module Stop Mode 24.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 24.4 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, A/D converter, 8-bit PWM module, and 14-bit PWM module, are retained. After reset release, all modules other than the DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. 723 Table 24.4 MSTP Bits and Corresponding On-Chip Supporting Modules Register Bit MSTPCRH MSTPCRL Module MSTP15* — MSTP14 Data transfer controller (DTC) MSTP13 16-bit free-running timer (FRT) MSTP12 8-bit timers (TMR0, TMR1) MSTP11 8-bit PWM timer (PWM), 14-bit PWM timer (PWMX) MSTP10 D/A converter MSTP9 A/D converter MSTP8 8-bit timers (TMRX, TMRY), timer connection MSTP7 Serial communication interface 0 (SCI0) MSTP6 Serial communication interface 1 (SCI1) MSTP5 Serial communication interface 2 (SCI2) MSTP4 I 2C bus interface (IIC) channel 0 MSTP3 I 2C bus interface (IIC) channel 1 MSTP2 Host interface (HIF:XBS), keyboard matrix interrupt mask register (KMIMR), keyboard matrix interrupt mask register A (KMIMRA), port 6 MOS pull-up control register (KMPCR), keyboard buffer controller (PS2) MSTP1 — MSTP0 Host interface (HIF: LPC), keyboard buffer controller (PS2) Note: Bit 1 can be read or written to, but do not affect operation. * Bit 15 must not be set to 1. 24.5.2 Usage Note If there is conflict between DTC module stop mode setting and a DTC bus request, the bus request has priority and the MSTP bit will not be set to 1. Write 1 to the MSTP bit again after the DTC bus cycle. 724 24.6 Software Standby Mode 24.6.1 Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is cleared to 0, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI, PWM, and PWMX, and of the I/O ports, are retained. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 24.6.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pin IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7), or by means of the RES pin or STBY pin. Clearing with an Interrupt: When an NMI, IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. Software standby mode cannot be cleared with an IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt if the corresponding enable bit has been cleared to 0 or has been masked by the CPU. Clearing with the RES Pin: When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware standby mode. 725 24.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation settling time). Table 24.5 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 24.5 Oscillation Settling Time Settings STS2 STS1 STS0 Standby Time 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz Unit 0 0 0 8192 states 0.8 1.0 1.3 2.0 4.1 ms 1 16384 states 1.6 2.0 2.7 4.1 0 32768 states 3.3 4.1 5.5 1 65536 states 6.6 0 131072 states 1 262144 states 0 1 1 1 0 1 13.1 8.2 10.9 8.2 8.2 16.4 16.4 32.8 16.4 21.8 32.8 65.5 26.2 32.8 43.6 65.6 131.2 Reserved — — — — — 16 states* 1.6 2.0 2.7 4.0 8.0 µs : Recommended time setting Notes: * The maximum operating frequency for the H8S/2169 and H8S/2149 is 10 MHz. This setting must not be used in the flash memory version. Using an External Clock: Any value can be set. Normally, use of the minimum time is recommended. 24.6.4 Software Standby Mode Application Example Figure 24.3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. 726 Oscillator ø NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down state) Oscillation settling time tOSC2 NMI exception handling SLEEP instruction Figure 24.3 Software Standby Mode Application Example 24.6.5 Usage Note In software standby mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current dissipation increases while waiting for oscillation to settle. 727 24.7 Hardware Standby Mode 24.7.1 Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD1 and MD0) while the chip is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillation settles (at least 8 ms—the oscillation settling time—when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 728 24.7.2 Hardware Standby Mode Timing Figure 24.4 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation settling time, then changing the RES pin from low to high. Oscillator RES STBY Oscillation settling time Reset exception handling Figure 24.4 Hardware Standby Mode Timing 729 24.8 Watch Mode 24.8.1 Watch Mode If a SLEEP instruction is executed in high-speed mode or subactive mode when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is set to 1, the CPU makes a transition to watch mode. In this mode, the CPU and all on-chip supporting modules except WDT1 stop. As long as the prescribed voltage is supplied, the contents of some of the CPU’s internal registers and on-chip RAM are retained, and I/O ports retain their states prior to the transition. 24.8.2 Clearing Watch Mode Watch mode is cleared by an interrupt (WOVI1 interrupt, NMI pin, or pin IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7), or by means of the RES pin or STBY pin. Clearing with an Interrupt: When an interrupt request signal is input, watch mode is cleared and a transition is made to high-speed mode or medium-speed mode if the LSON bit in LPWRCR is cleared to 0, or to subactive mode if the LSON bit is set to 1. When making a transition to highspeed mode, after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire chip, and interrupt exception handling is started. Watch mode cannot be cleared with an IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the CPU. See section 24.6.3, Setting Oscillation Settling Time after Clearing Software Standby Mode, for the oscillation settling time setting when making a transition from watch mode to high-speed mode. Clearing with the RES Pin: See “Clearing with the RES Pin” in section 24.6.2, Clearing Software Standby Mode. Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware standby mode. 730 24.9 Subsleep Mode 24.9.1 Subsleep Mode If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the PSS bit in TCSR (WDT1) is set to 1, the CPU makes a transition to subsleep mode. In this mode, the CPU and all on-chip supporting modules except TMR0, TMR1, WDT0, and WDT1 stop. As long as the prescribed voltage is supplied, the contents of some of the CPU’s internal registers and on-chip RAM are retained, and I/O ports retain their states prior to the transition. 24.9.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (on-chip supporting module interrupt, NMI pin, or pin IRQ0 to IRQ7), or by means of the RES pin or STBY pin. Clearing with an Interrupt: When an interrupt request signal is input, subsleep mode is cleared and interrupt exception handling is started. Subsleep mode cannot be cleared with an IRQ0 to IRQ7 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the CPU. Clearing with the RES Pin: See “Clearing with the RES Pin” in section 24.6.2, Clearing Software Standby Mode. Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware standby mode 731 24.10 Subactive Mode 24.10.1 Subactive Mode If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON bit in LPWRCR, and the PSS bit in TCSR (WDT1) are all set to 1, the CPU makes a transition to subactive mode. When an interrupt is generated in watch mode, if the LSON bit in LPWRCR is set to 1, a transition is made to subactive mode. When an interrupt is generated in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU performs sequential program execution at low speed on the subclock. In this mode, all on-chip supporting modules except TMR0, TMR1, WDT0, and WDT1 stop. When operating the device in subactive mode, bits SCK2 to SCK0 in SBYCR must all be cleared to 0. 24.10.2 Clearing Subactive Mode Subsleep mode is cleared by a SLEEP instruction, or by means of the RES pin or STBY pin. Clearing with a SLEEP Instruction: When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is set to 1, subactive mode is cleared and a transition is made to watch mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the PSS bit in TCSR (WDT1) is set to 1, a transition is made to subsleep mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit is set to 1 and the LSON bit is cleared to 0 in LPWRCR, and the PSS bit in TCSR (WDT1) is set to 1, a transition is made directly to high-speed mode. Fort details of direct transition, see section 24.11, Direct Transition. Clearing with the RES Pin: See “Clearing with the RES Pin” in section 24.6.2, Clearing Software Standby Mode. Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware standby mode 732 24.11 Direct Transition 24.11.1 Overview of Direct Transition There are three operating modes in which the CPU executes programs: high-speed mode, mediumspeed mode, and subactive mode. A transition between high-speed mode and subactive mode without halting the program is called a direct transition. A direct transition can be carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction. After the transition, direct transition interrupt exception handling is started. Direct Transition from High-Speed Mode to Subactive Mode: If a SLEEP instruction is executed in high-speed mode while the SSBY bit in SBYCR, the LSON bit and DTON bit in LPWRCR, and the PSS bit in TSCR (WDT1) are all set to 1, a transition is made to subactive mode. Direct Transition from Subactive Mode to High-Speed Mode: If a SLEEP instruction is executed in subactive mode while the SSBY bit in SBYCR is set to 1, the LSON bit is cleared to 0 and the DTON bit is set to 1 in LPWRCR, and the PSS bit in TSCR (WDT1) is set to 1, after the elapse of the time set in bits STS2 to STS0 in SBYCR, a transition is made to directly to highspeed mode. 733 734 Section 25 Electrical Characteristics 25.1 Absolute Maximum Ratings Table 25.1 lists the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC, VCL –0.3 to +4.3 V I/O buffer power supply voltage VCCB –0.3 to +7.0 V Input voltage (except ports 6, 7, and A) (include ports C and D for H8S/2169) Vin –0.3 to VCC +0.3 V Input voltage (CIN input not selected for port 6) Vin –0.3 to VCC +0.3 V Input voltage (CIN input not selected for port A) (include ports E, F, and G for H8S/2169) Vin –0.3 to VCCB +0.3 V Input voltage (CIN input selected for port 6) Vin –0.3 V to lower of voltages VCC + 0.3 and AVCC + 0.3 V Input voltage (CIN input selected for port A) Vin –0.3 V to lower of voltages VCCB + 0.3 and AVCC + 0.3 V Input voltage (port 7) Vin –0.3 to AVCC + 0.3 V Reference supply voltage AVref –0.3 to AVCC + 0.3 V Analog power supply voltage AVCC –0.3 to +4.3 V Analog input voltage VAN –0.3 to AVCC +0.3 V Operating temperature Topr –20 to +75 °C Operating temperature (flash memory programming/erasing) Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Ensure so that the impressed voltage does not exceed 4.3 V for pins for which the maximum rating is determined by the voltage on the VCC, AVCC, and VCL pins, or 7.0 V for pins for which the maximum rating is determined by V CCB. 735 25.2 DC Characteristics Table 25.2 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 25.3 and 25.4, respectively. Table 25.2 DC Characteristics Conditions: VCC = 2.7 V to 3.6 V*11, VCCB = 2.7 V to 5.5 V, AVCC*1 = 2.7 V to 3.6 V, AVref*1 = 2.7 V to AVCC, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C Item Symbol Schmitt P67 to P60* 2, * 6, (1)* 8 VT– trigger input KIN15 to KIN8* 7, voltage IRQ2 to IRQ0* 3, VT+ IRQ5 to IRQ3 Min Typ Max Unit VCC × 0.2 — VCCB × 0.2 — V — VCC × 0.7 V VCCB × 0.7 — VT+ – VT– VCC × 0.05 — VCCB × 0.05 Schmitt P67 to P60 trigger input (KWUL = 00) voltage (in level switching)* 6 — — VT+ — — VCC × 0.7 – VT + VT – VT – VT – VT + VT EXTAL 7 PA7 to PA0* (include ports E, F, and G for H8S/2169) 736 — — — — VCC × 0.7 VCC × 0.05 — — VCC × 0.4 — — — — VCC × 0.8 VCC × 0.45 — — — — VCC × 0.9 VT – VT 0.05 — — VIH VCC × 0.9 — VCC +0.3 V VCC × 0.7 — VCC +0.3 V – VT + VT + RES, STBY, (2) NMI, MD1, MD0 VCC × 0.3 — – VT – VT Input high voltage — VCC × 0.03 — + P67 to P60 (KWUL = 11) V VCC × 0.2 + P67 to P60 (KWUL = 10) V VT– VT+ – VT– VCC × 0.05 — P67 to P60 (KWUL = 01) — – VCCB × 0.7 — VCCB + 0.3 V Test Conditions Item Input high voltage Min Typ Max VIH VCC × 0.7 — AVCC +0.3 V VCC × 0.7 — VCC +0.3 V –0.3 — VCC × 0.1 V PA7 to PA0 (include ports E, F, and G for H8S/2169) –0.3 — VCCB × 0.2 V VCCB = 2.7 V to 4.0 V –0.3 — 0.8 V VCCB = 4.0 V to 5.5 V NMI, EXTAL, input pins except (1) and (3) above (include ports C and D for H8S/2169) –0.3 — VCC × 0.2 V VCC = 2.7 V to 3.6 V VCC – 0.5 — VCCB – 0.5 — V I OH = –200 µA VCC – 1.0 — VCCB – 1.0 — V I OH = –1 mA, (VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 4.5 V) 0.5 — — V I OH = –200 µA — — 0.4 V I OL = 1.6 mA Ports 1 to 3 — — 1.0 V I OL = 5 mA RESO — — 0.4 V I OL = 1.6 mA — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 µA Vin = 0.5 to VCC – 0.5 V Port 7 — — 1.0 µA Port 7 (2) Input pins except (1) and (2) above (include ports C and D for H8S/2169) Input low voltage RES, STBY, MD1, MD0 Output high All output pins voltage (except P97, and P52* 4)* 5, * 8 (include ports C to G* 8 for H8S/2169) (3) VIL VOH P97, P52* 4 Output low voltage Input leakage current All output pins (except RESO)* 5 (include ports C to G* 8 for H8S/2169) RES VOL Iin Unit Test Conditions Symbol Vin = 0.5 to AVCC – 0.5 V 737 Item Symbol Min Typ Max Unit Test Conditions Three-state leakage current (off state) Ports 1 to 6 Ports 8, 9, A* 8, B (include ports C to G* 8 for H8S/2169) ITSI — — 1.0 µA Vin = 0.5 to VCC – 0.5 V, Vin = 0.5 to VCCB – 0.5 V Input pull-up MOS current Ports 1 to 3 –I P 5 — 150 µA Vin = 0 V, VCC = 2.7 V to 3.6 V Ports 6 (P6PUE = 0), B 30 — 300 µA VCCB = 2.7 V to 5.5 V Ports A* 8 (include ports C to G* 8 for H8S/2169). 30 — 600 µA Port 6 (P6PUE = 1) 3 — 100 µA — — 80 pF NMI — — 50 pF P52, P97, P42, P86, PA7 to PA2 — — 20 pF Input pins except (4) above (include ports C to G for H8S/2169) — — 15 pF — 30 40 mA f = 10 MHz — 20 32 mA f = 10 MHz — 1 5.0 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta — 1.2 2.0 mA — 0.01 5.0 µA Input RES capacitance (4) Current Normal dissipation* 9 operation Cin I CC Sleep mode Standby mode* Analog power supply current 738 10 During A/D, D/A conversion Idle AlCC Vin = 0 V, f = 1 MHz, Ta = 25°C AVCC = 2.0 V to 3.6 V Item Reference power supply current Test Conditions Symbol Min Typ Max Unit Alref — 0.5 1.0 mA During A/D, D/A conversion — 2.0 5.0 mA Idle — 0.01 5.0 µA AVref = 2.0 V to AVCC 2.7 — 3.6 V Operating 2.0 — 3.6 V Idle/not used 2.0 — — V During A/D conversion Analog power supply voltage* 1 RAM standby voltage AVCC VRAM Notes: 1. Do not leave the AVCC, AVref, and AV SS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 3.6 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AV ref ≤ AV CC. 2. P67 to P60 include supporting module inputs multiplexed on those pins. 3. IRQ2 includes the ADTRG signal multiplexed on that pin. 4. P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs. An external pull-up resistor is necessary to provide high-level output from SCL0 and SDA0 (ICE = 1). P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS. When the SCK0 pin is used as an output, external pull-up register must be connected in order to output high level. 5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function is selected is determined separately. 6. The upper limit of the port 6 applied voltage is V CC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. The upper limit of the port A applied voltage is V CCB + 0.3 V when CIN input is not selected, and the lower of VCCB + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 8. The port A characteristics depend on V CCB, and the other pins characteristics depend on V CC. On the H8S/2169, the characteristics of ports E, F, and G depend on VCCB, and the characteristics of ports C and D depend on VCC. 9. Current dissipation values are for V IH min = VCC – 0.2 V, VCCB – 0.2 V, and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 10. The values are for VRAM ≤ V CC < 2.7 V, VIH min = VCC– 0.2 V, VCCB – 0.2 V, and VIL max = 0.2 V. 11. For flash memory programming/erasure, the applicable range is VCC = 3.0 V to 3.6 V. 739 Table 25.3 Permissible Output Currents Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C Item Symbol Min Typ Max Unit Permissible output low current (per pin) I OL — — 10 mA Ports 1, 2, 3 — — 2 mA RESO — — 1 mA Other output pins — — 1 mA — — 40 mA — — 60 mA Permissible output low current (total) SCL1, SCL0, SDA1, SDA0, PS2AC to PS2CC, PS2AD to PS2CD, PA7 to PA4 (bus drive function selected) Total of ports 1, 2, and 3 ∑ IOL Total of all output pins, including the above Permissible output high current (per pin) All output pins –I OH — — 2 mA Permissible output high current (total) Total of all output pins ∑ –IOH — — 30 mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 25.3. 2. When driving a Darlington pair or LED, always insert a current-limiting resistor in the output line, as show in figures 25.1 and 25.2. 740 Table 25.4 Bus Drive Characteristics Conditions: VCC = 2.7 V to 3.6 V, VSS = 0 V, Ta = –20 to +75°C Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Symbol Min Typ Max Unit Test Conditions VCC × 0.3 — — V VCC = 2.7 V to 3.6 V — — VCC × 0.7 VCC = 2.7 V to 3.6 V VT – VT VCC × 0.05 — — VCC = 2.7 V to 3.6 V Input high voltage VIH VCC × 0.7 — VCC + 0.5 Input low voltage VIL –0.5 — VCC × 0.3 Output low voltage VOL — — 0.5 — — 0.4 — — 20 pF Vin = 0 V, f = 1 MHz, Ta = 25°C Three-state leakage | ITSI | current (off state) — — 1.0 µA Vin = 0.5 to VCC – 0.5 V SCL, SDA output fall time 20 + 0.1Cb — 250 ns VCC = 2.7 V to 3.6 V – Schmitt trigger input voltage VT VT+ + Input capacitance Conditions: – Cin t Of V VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V V I OL = 8 mA I OL = 3 mA VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C Applicable Pins: PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD, PA7 to PA4 (bus drive function selected) Item Symbol Min Typ Max Unit Test Conditions Output low voltage VOL — — 0.8 I OL = 16 mA, VCCB = 4.5 V to 5.5 V — — 0.5 I OL = 8 mA — — 0.4 I OL = 3 mA 741 The chip 2 kΩ Port Darlington pair Figure 25.1 Darlington Pair Drive Circuit (Example) The chip 600 Ω Ports 1 to 3 LED Figure 25.2 LED Drive Circuit (Example) 25.3 AC Characteristics Figure 25.3 shows the test conditions for the AC characteristics. VCC RL C = 30 pF: All output ports RL = 2.4 kΩ RH = 12 kΩ Chip output pin C RH I/O timing test levels • Low level: 0.8 V • High level: 2.0 V Figure 25.3 Output Load Circuit 742 25.3.1 Clock Timing Table 25.5 shows the clock timing. The clock timing specified here covers clock (ø) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 23, Clock Pulse Generator. Table 25.5 Clock Timing Condition: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Symbol Min Max Unit Test Conditions Clock cycle time t cyc 100 500 ns Figure 25.4 Clock high pulse width t CH 30 — ns Figure 25.4 Clock low pulse width t CL 30 — ns Clock rise time t Cr — 20 ns Clock fall time t Cf — 20 ns Oscillation settling time at reset (crystal) t OSC1 20 — ms Figure 25.5 Oscillation settling time in software standby (crystal) t OSC2 8 — ms Figure 25.6 External clock output stabilization delay time t DEXT 500 — µs tcyc tCH tCf ø tCL tCr Figure 25.4 System Clock Timing 743 EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES ø Figure 25.5 Oscillation Settling Timing ø NMI IRQi (i = 0, 1, 2, 6, 7) tOSC2 Figure 25.6 Oscillation Setting Timing (Exiting Software Standby Mode) 744 25.3.2 Control Signal Timing Table 25.6 shows the control signal timing. The only external interrupts that can operate on the subclock (ø = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 25.6 Control Signal Timing Condition: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, ø = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Symbol Min Max Unit Test Conditions RES setup time t RESS 300 — ns Figure 25.7 RES pulse width t RESW 20 — t cyc NMI setup time (NMI) t NMIS 250 — ns NMI hold time (NMI) t NMIH 10 — ns NMI pulse width (exiting software standby t NMIW mode) 200 — ns IRQ setup time (IRQ7 to IRQ0) t IRQS 250 — ns IRQ hold time(IRQ7 to IRQ0) t IRQH 10 — ns IRQ pulse width (IRQ7, IRQ6, IRQ2 to IRQ0) (exiting software standby mode) t IRQW 200 — ns Figure 25.8 745 ø tRESS tRESS RES tRESW Figure 25.7 Reset Input Timing ø tNMIH tNMIS NMI tNMIW IRQi (i = 7 to 0) tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 25.8 Interrupt Input Timing 746 25.3.3 Bus Timing Table 25.7 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (ø = 32.768 kHz). Table 25.7 Bus Timing (1) (Normal Mode) Condition: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Symbol Min Max Unit Test Conditions Address delay time t AD — 40 ns Address setup time t AS 0.5 × t cyc – 30 — ns Figure 25.9 to figure 25.13 Address hold time t AH 0.5 × t cyc – 20 — ns CS delay time (IOS) t CSD — 40 ns AS delay time t ASD — 60 ns RD delay time 1 t RSD1 — 60 ns RD delay time 2 t RSD2 — 60 ns Read data setup time t RDS 35 — ns Read data hold time t RDH 0 — ns Read data access time 1 t ACC1 — 1.0 × t cyc – 60 ns Read data access time 2 t ACC2 — 1.5 × t cyc – 50 ns Read data access time 3 t ACC3 — 2.0 × t cyc – 60 ns Read data access time 4 t ACC4 — 2.5 × t cyc – 50 ns Read data access time 5 t ACC5 — 3.0 × t cyc – 60 ns WR delay time 1 t WRD1 — 60 ns WR delay time 2 t WRD2 — 60 ns WR pulse width 1 t WSW1 1.0 × t cyc – 40 — ns WR pulse width 2 t WSW2 1.5 × t cyc – 40 — ns Write data delay time t WDD — 60 ns Write data setup time t WDS 0 — ns Write data hold time t WDH 20 — ns WAIT setup time t WTS 60 — ns WAIT hold time t WTH 10 — ns 747 Table 25.7 Bus Timing (2) (Advanced Mode) Condition: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition C 10 MHz Item Symbol Min Max Unit Test Conditions Address delay time t AD — 60 ns Address setup time t AS 0.5 × t cyc – 30 — ns Figure 25.9 to figure 25.13 Address hold time t AH 0.5 × t cyc – 20 — ns CS delay time (IOS) t CSD — 60 ns AS delay time t ASD — 60 ns RD delay time 1 t RSD1 — 60 ns RD delay time 2 t RSD2 — 60 ns Read data setup time t RDS 35 — ns Read data hold time t RDH 0 — ns Read data access time 1 t ACC1 — 1.0 × t cyc – 80 ns Read data access time 2 t ACC2 — 1.5 × t cyc – 50 ns Read data access time 3 t ACC3 — 2.0 × t cyc – 80 ns Read data access time 4 t ACC4 — 2.5 × t cyc – 50 ns Read data access time 5 t ACC5 — 3.0 × t cyc – 80 ns WR delay time 1 t WRD1 — 60 ns WR delay time 2 t WRD2 — 60 ns WR pulse width 1 t WSW1 1.0 × t cyc – 40 — ns WR pulse width 2 t WSW2 1.5 × t cyc – 40 — ns Write data delay time t WDD — 60 ns Write data setup time t WDS 0 — ns Write data hold time t WDH 20 — ns WAIT setup time t WTS 60 — ns WAIT hold time t WTH 10 — ns 748 T1 T2 ø tAD A23 to A0, IOS* tCSD tAS tAH tASD tASD AS* tRSD1 RD (read) tACC2 tRSD2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D15 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 25.9 Basic Bus Timing (Two-State Access) 749 T1 T2 T3 ø tAD A23 to A0, IOS* tCSD tAS tASD tAH tASD AS* tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tACC5 tRDH D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 25.10 Basic Bus Timing (Three-State Access) 750 T1 T2 TW T3 ø A23 to A0, IOS* AS* RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 25.11 Basic Bus Timing (Three-State Access with One Wait State) 751 T1 T2 or T3 T1 T2 ø tAD A23 to A0, IOS* tAS tASD tAH tASD AS* tRSD2 RD (read) tACC3 tRDS D15 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 25.12 Burst ROM Access Timing (Two-State Access) 752 tRDH T1 T2 or T3 T1 ø tAD A23 to A0, IOS* AS* tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 25.13 Burst ROM Access Timing (One-State Access) 753 25.3.4 Timing of On-Chip Supporting Modules Tables 25.8 to 25.10 show the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (ø = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 25.8 Timing of On-Chip Supporting Modules (1) Condition: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, ø = 32.768 kHz *, 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Symbol Min Max Unit Test Conditions I/O ports Output data delay time t PWD — 100 ns Figure 25.14 Input data setup time t PRS 50 — Input data hold time t PRH 50 — Timer output delay time t FTOD — 100 ns Figure 25.15 Timer input setup time t FTIS 50 — Timer clock input setup time t FTCS 50 — Single edge t FTCWH 1.5 — Both edges t FTCWL 2.5 — Timer output delay time t TMOD — 100 Timer reset input setup time t TMRS 50 — Figure 25.19 Timer clock input setup time t TMCS 50 — Figure 25.18 Single edge t TMCWH 1.5 — Both edges t TMCWL 2.5 — FRT Timer clock pulse width TMR Timer clock pulse width Figure 25.16 t cyc ns Figure 25.17 t cyc PWM, PWMX Pulse output delay time t PWOD — 100 ns Figure 25.20 SCI Input clock cycle t Scyc 4 — t cyc Figure 25.21 6 — 754 Asynchronous Synchronous Input clock pulse width t SCKW 0.4 0.6 t Scyc Input clock rise time t SCKr — 1.5 t cyc Input clock fall time t SCKf — 1.5 Transmit data delay time (synchronous) t TXD — 100 ns Figure 25.22 Condition 10 MHz Item Symbol Min Max Unit Test Conditions Receive data setup time (synchronous) t RXS 100 — ns Figure 25.22 Receive data hold time (synchronous) t RXH 100 — ns A/D Trigger input setup time converter t TRGS 50 — ns Figure 25.23 RESO output delay time t RESD — 200 ns Figure 25.24 RESO output pulse width t RESOW 132 — t cyc SCI WDT Note: * Only supporting modules that can be used in subclock operation T1 T2 ø tPRS tPRH Ports 1 to 9, A to G (read) tPWD Ports 1 to 6, 8, 9, A to G (write) Figure 25.14 I/O Port Input/Output Timing ø tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 25.15 FRT Input/Output Timing 755 ø tFTCS FTCI tFTCWL tFTCWH Figure 25.16 FRT Clock Input Timing ø tTMOD TMO0, TMO1 TMOX Figure 25.17 8-Bit Timer Output Timing ø tTMCS tTMCS TMCI0, TMCI1 TMIX, TMIY tTMCWL tTMCWH Figure 25.18 8-Bit Timer Clock Input Timing ø tTMRS TMRI0, TMRI1 TMIX, TMIY Figure 25.19 8-Bit Timer Reset Input Timing 756 ø tPWOD PW15 to PW0, PWX1, PWX0 Figure 25.20 PWM, PWMX Output Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 25.21 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 25.22 SCI Input/Output Timing (Synchronous Mode) ø tTRGS ADTRG Figure 25.23 A/D Converter External Trigger Input Timing 757 ø tRESD tRESD RESO tRESOW Figure 25.24 WDT Output Timing (RESO) Table 25.8 Timing of On-Chip Supporting Modules (2) Condition: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Symbol Min Max Unit Test Conditions XBS read CS/HA0 setup time cycle CS/HA0 hold time t HAR 10 — ns Figure 25.25 t HRA 10 — ns IOR pulse width t HRPW 220 — ns HDB delay time t HRD — 200 ns HDB hold time t HRF 0 40 ns HIRQ delay time t HIRQ — 200 ns t HAW 10 — ns t HWA 10 — ns t HWPW 100 — ns 50 — ns 85 — ns XBS write CS/HA0 setup time cycle CS/HA0 hold time IOW pulse width HDB setup Fast A20 gate not t HDW time used Fast A20 gate used 758 HDB hold time t HWD 25 — ns GA20 delay time t HGA — 180 ns Host interface (XBS) read timing CS/HA0 tHAR tHRPW tHRA IOR tHRD HDB7 to HDB0 tHRF Valid data tHIRQ HIRQi* (i = 1, 11, 12, 3, 4) Note: * The rising edge timing is the same as the port 4 and port B output timing. See figure 25.14. Host interface (XBS) write timing CS/HA0 tHAW tHWPW tHWA IOW tHDW tHWD HDB7 to HDB0 tHGA GA20 Figure 25.25 Host Interface (XBS) Timing 759 Table 25.9 Keyboard Buffer Controller Timing Conditions: VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Ratings Item Symbol Min KCLK, KD output fall time t KBF KCLK, KD input data hold time Typ Max Unit Notes 20 + 0.1Cb — 250 ns Figure 25.26 t KBIH 150 — — ns KCLK, KD input data setup time t KBIS 150 — — ns KCLK, KD output delay time t KBOD — — 450 ns KCLK, KD capacitive load Cb — — 400 pF 1. Reception ø tKBIS tKBIH KCLK/ KD* 2. Transmission (a) T1 T2 ø tKBOD KCLK/ KD* Transmission (b) KCLK/ KD* tKBF Note: ø shown here is the clock scaled by 1/N when the operating mode is active medium-speed mode. * KCLK: PS2AC to PS2CC KD: PS2AD to PS2CD Figure 25.26 Keyboard Buffer Controller Timing 760 Table 25.10 I2C Bus Timing Conditions: VCC = 2.7 V to 3.6 V, VSS = 0 V, ø = 5 MHz to maximum operating frequency, Ta = –20 to +75°C Ratings Item Symbol Min Typ Max Unit Notes SCL input cycle time t SCL 12 — — t cyc Figure 25.27 SCL input high pulse width t SCLH 3 — — t cyc SCL input low pulse width t SCLL 5 — — t cyc SCL, SDA input rise time t Sr — — 7.5* t cyc SCL, SDA input fall time t Sf — — 300 ns SCL, SDA input spike pulse elimination time t SP — — 1 t cyc SDA input bus free time t BUF 5 — — t cyc Start condition input hold time t STAH 3 — — t cyc Retransmission start condition input setup time t STAS 3 — — t cyc Stop condition input setup time t STOS 3 — — t cyc Data input setup time t SDAS 0.5 — — t cyc Data input hold time t SDAH 0 — — ns SCL, SDA capacitive load Cb — — 400 pF 2 Note: * 17.5tcyc can be set according to the clock selected for use by the I C module. For details, see section 16.4, Usage Notes. 761 VIH SDA0, SDA1 VIL tBUF tSCLH tSTAH tSP tSTOS tSTAS SCL0, SCL1 P* S* tSf Sr* tSCLL P* tSDAS tSr tSCL tSDAH Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition Figure 25.27 I2C Bus Interface Input/Output Timing Table 25.11 LPC Module Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Item LPC 762 Symbol Min Max Unit Notes Input clock cycle t Lcyc 30 — ns Figure 25.28 Input clock pulse width t LCKW 0.4 0.6 t Lcyc Transmit signal delay time t TXD — 18 ns Receive signal setup time t RXS 8 — Receive signal hold time t RXH 8 — tLCKW LCLK tLcyc LCLK tTXD LAD3 to LAD0, SERIRQ (transmit signal) tRXS tRXH LAD3 to LAD0, SERIRQ, LFRAME, LRESET (receive signal) Figure 25.28 Host Interface (LPC) Timing 763 25.4 A/D Conversion Characteristics Tables 25.12 and 25.13 list the A/D conversion characteristics. Table 25.12 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC, VCCB = 2.7 V to 5.5 V, VSS = AVSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Min Typ Max Unit Resolution 10 10 10 Bits Conversion time — — 13.4 µs Analog input capacitance — — 20 pF Permissible signal-source impedance — — 5 kΩ Nonlinearity error — — ±7.0 LSB Offset error — — ±7.5 LSB Full-scale error — — ±7.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±8.0 LSB 764 Table 25.13 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VCCB = 3.0 V to 5.5 V, VSS = AVSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Min Typ Max Unit Resolution 10 10 10 Bits Conversion time — — 13.4 µs Analog input capacitance — — 20 pF Permissible signal-source impedance — — 5 kΩ Nonlinearity error — — ±11.0 LSB Offset error — — ±11.5 LSB Full-scale error — — ±11.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±12.0 LSB 25.5 D/A Conversion Characteristics Table 25.14 lists the D/A conversion characteristics. Table 25.14 D/A Conversion Characteristics Condition: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC, VCCB = 2.7 V to 5.5 V, VSS = AVSS = 0 V, ø = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Min Typ Max Unit Resolution 8 8 8 Bits Conversion time With 20 pF load capacitance — — 10 µs Absolute accuracy With 2 MΩ load resistance — ±2.0 ±3.0 LSB With 4 MΩ load resistance — — ±2.0 765 25.6 Flash Memory Characteristics Table 25.15 shows the flash memory characteristics. Table 25.15 Flash Memory Characteristics Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = –20 to +75°C Test Condition Item Symbol Min Typ Max Unit Programming time*1,* 2,* 4 tP — 10 200 ms/ 128 bytes Erase time* 1,* 3,* 6 tE — 100 1200 ms/ block Reprogramming count NWEC — — 100 Times Programming Wait time after SWE-bit setting* 1 x 1 — — µs Wait time after PSU-bit setting* 1 y 50 — — µs Wait time after z1 28 30 32 µs 1≤n≤6 z2 198 200 202 µs 7 ≤ n ≤ 1000 z3 8 10 12 µs additional write Wait time after P-bit clear*1 α 5 — — µs Wait time after PSU-bit clear* 1 β 5 — — µs Wait time after PV-bit setting* 1 γ 4 — — µs Wait time after dummy write* 1 ε 2 — — µs Wait time after PV-bit clear* 1 η 2 — — µs Wait time after SWE-bit clear* 1 θ 100 — — µs Maximum programming count* 1,* 4,* 5 N — — 1000 Times 1, P-bit setting* * 766 4 Item Erase Symbol Min Typ Max Unit Wait time after SWE-bit setting* 1 x 1 — — µs Wait time after ESU-bit setting* 1 y 100 — — µs Wait time after E-bit setting* 1,* 6 z 10 — 100 ms Wait time after E-bit clear*1 α 10 — — µs Wait time after ESU-bit clear* 1 β 10 — — µs Wait time after EV-bit setting* 1 γ 20 — — µs Wait time after dummy write* 1 ε 2 — — µs Wait time after EV-bit clear* 1 η 4 — — µs Wait time after SWE-bit clear *1 θ 100 — — µs Maximum erase count* 1,* 6,* 7 N — — 120 Times Test Condition Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in FLMCR1 is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max)) tP (max) = (wait time after P-bit setting (z1) + (z3)) × 6 + wait time after P-bit setting (z2) × ((N) – 6) 5. The maximun number of writes (N) should be set according to the actual set value of z1, z2 and z3 to allow programming within the maximum programming time (tP (max)). The wait time after P-bit setting (z1,z2, and z3) should be alternated according to the number of writes (n) as follows: 1 ≤ n≤ 6 z1 = 30µs, z3 = 10µs 7 ≤ n ≤ 1000 z2 = 200µs 6. Maximum erase time (tE (max)) tE (max) = Wait time after E-bit setting (z) × maximum erase count (N) 7. The maximum number of erases (N) should be set according to the actual set value of z to allow erasing within the maximum erase time (tE (max)). 767 25.7 Usage Note The method of connecting an external capacitor is shown in figure 25.29. Connect the system power supply to the VCL pin together with the VCC pins. Vcc power supply VCL Bypass capacitor 10 µF H8S/2169, H8S/2149 0.01 µF VSS < Vcc = 2.7 V to 3.6 V > Connect the Vcc power supply to the chip's VCL pin in the same way as the VCC pins. It is recommended that a bypass capacitor be connected to the power supply pins. (Values are reference values.) Figure 25.29 Connection of VCL Capacitor 768 Appendix A Instruction Set A.1 Instruction Operation Notation Rd General register (destination )* 1 Rs General register (source)* 1 Rn General register* 1 ERn General register (32-bit register) MAC Multiply-and-accumulate register (32-bit register)*2 (EAd) Destination operand (EAs) Source operand EXR Extend register CCR Condition code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction × Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Exclusive logical OR → Transfer from left-hand operand to right-hand operand, or transition from lefthand state to right-hand state ¬ NOT (logical complement) ( ) < > Operand contents :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 2. MAC instructions cannot be used in the H8S/2149. 769 Condition Code Notation Symbol Meaning Changes according operation result. * Indeterminate (value not guaranteed). 0 Always cleared to 0. 1 Always set to 1. — Not affected by operation result. 770 Table A.1 Instruction Set 1. Data Transfer Instructions B MOV.B @ERs+,Rd B MOV.B @aa:8,Rd B MOV.B @aa:16,Rd H N Z V C Advanced MOV.B @(d:32,ERs),Rd No. of States*1 Normal B I — MOV.B @(d:16,ERs),Rd @@aa B @(d,PC) MOV.B @ERs,Rd Condition Code Operation @aa 2 B @-ERn/@ERn+ B MOV.B Rs,Rd @ERn MOV.B #xx:8,Rd Rn #xx MOV Size Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) #xx:8→Rd8 — — 0 — 1 Rs8→Rd8 — — 0 — 1 @ERs→Rd8 — — 0 — 2 4 @(d:16,ERs)→Rd8 — — 0 — 3 8 @(d:32,ERs)→Rd8 — — 0 — 5 @ERs→Rd8,ERs32+1→ERs32 — — 0 — 3 2 @aa:8→Rd8 — — 0 — 2 B 4 @aa:16→Rd8 — — 0 — 3 MOV.B @aa:32,Rd B 6 @aa:32→Rd8 — — 0 — 4 MOV.B Rs,@ERd B Rs8→@ERd — — 0 — 2 MOV.B Rs,@(d:16,ERd) B 4 Rs8→@(d:16,ERd) — — 0 — 3 MOV.B Rs,@(d:32,ERd) B 8 Rs8→@(d:32,ERd) — — 0 — 5 MOV.B Rs,@-ERd B ERd32-1→ERd32,Rs8→@ERd — — 0 — 3 MOV.B Rs,@aa:8 B 2 Rs8→@aa:8 — — 0 — 2 MOV.B Rs,@aa:16 B 4 Rs8→@aa:16 — — 0 — 3 MOV.B Rs,@aa:32 B 6 Rs8→@aa:32 — — 0 — 4 MOV.W #xx:16,Rd W #xx:16→Rd16 — — 0 — 2 MOV.W Rs,Rd W Rs16→Rd16 — — 0 — 1 MOV.W @ERs,Rd W @ERs→Rd16 — — 0 — 2 MOV.W @(d:16,ERs),Rd W 4 @(d:16,ERs)→Rd16 — — 0 — 3 MOV.W @(d:32,ERs),Rd W 8 @(d:32,ERs)→Rd16 — — 0 — 5 MOV.W @ERs+,Rd W @ERs→Rd16,ERs32+2→ERs32 — — 0 — 3 MOV.W @aa:16,Rd W 4 @aa:16→Rd16 — — 0 — 3 MOV.W @aa:32,Rd W 6 @aa:32→Rd16 — — 0 — 4 MOV.W Rs,@ERd W Rs16→@ERd — — 0 — 2 MOV.W Rs,@(d:16,ERd) W 4 Rs16→@(d:16,ERd) — — 0 — 3 MOV.W Rs,@(d:32,ERd) W 8 Rs16→@(d:32,ERd) — — 0 — 5 MOV.W Rs,@-ERd W ERd32-2→ERd32,Rs16→@ERd — — 0 — 3 MOV.W Rs,@aa:16 W 4 Rs16→@aa:16 — — 0 — 3 MOV.W Rs,@aa:32 W 6 Rs16→@aa:32 — — 0 — 4 2 2 2 2 2 4 2 2 2 2 2 771 L MOV.L @ERs+,ERd L MOV.L @aa:16,ER