Intersil HA9P5320-5 1 microsecond precision sample and hold amplifier Datasheet

HA-5320
Data Sheet
1 Microsecond Precision Sample and
Hold Amplifier
The HA-5320 was designed for use in precision, high speed
data acquisition systems.
The circuit consists of an input transconductance amplifier
capable of providing large amounts of charging current, a low
leakage analog switch, and an output integrating amplifier. The
analog switch sees virtual ground as its load; therefore, charge
injection on the hold capacitor is constant over the entire
input/output voltage range. The pedestal voltage resulting from
this charge injection can be adjusted to zero by use of the offset
adjust inputs. The device includes a hold capacitor. However, if
improved droop rate is required at the expense of acquisition
time, additional hold capacitance may be added externally.
This monolithic device is manufactured using the Intersil
Dielectric Isolation Process, minimizing stray capacitance
and eliminating SCRs. This allows higher speed and latchfree operation. For further information, please see
Application Note AN538.
April 1999
File Number
2857.4
Features
• Gain, DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 x 106 V/V
• Acquisition Time . . . . . . . . . . . . . . . . . . . . . 1.0µs (0.01%)
• Droop Rate . . . . . . . . . . . . . . . . . . . . . . 0.08µV/µs (25oC)
17µV/µs (Full Temperature)
• Aperture Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns
• Hold Step Error (See Glossary) . . . . . . . . . . . . . . . . . 5mV
• Internal Hold Capacitor
• Fully Differential Input
• TTL Compatible
Applications
• Precision Data Acquisition Systems
• Digital to Analog Converter Deglitcher
• Auto Zero Circuits
• Peak Detector
Pinouts
Ordering Information
HA-5320
(PDIP, CERDIP)
TOP VIEW
-INPUT 1
14 S/H CONTROL
+INPUT 2
13 SUPPLY GND
OFFSET ADJUST 3
12 NC
OFFSET ADJUST 4
11 CEXT
V- 5
10 NC
SIG. GND 6
9 V+
-55 to 25
14 Ld CERDIP
F14.3
HA1-5320-5
0 to 75
14 Ld CERDIP
F14.3
HA3-5320-5
0 to 75
14 Ld PDIP
E14.3
HA9P5320-5
0 to 75
16 Ld SOIC
M16.3
HA9P5320-9
-40 to 85
16 Ld SOIC
M16.3
Functional Diagram
OFFSET
ADJUST
3
V+
9
4
HA-5320
(SOIC)
TOP VIEW
100pF
HA-5320
-INPUT 1
-INPUT 1
16 S/H CONTROL
+INPUT 2
15 SUPPLY GND
OFFSET ADJUST 3
14 NC
OFFSET ADJUST 4
13 CEXT
V- 5
11 V+
INTEGRATOR
10 BANDWIDTH
OUTPUT 7
9 NC
NC 8
-
+INPUT 2
7
+
OUTPUT
S/H
CONTROL 14
12 NC
SIG. GND 6
PKG.
NO.
PACKAGE
HA1-5320-2
INTEGRATOR
8 BANDWIDTH
OUTPUT 7
TEMP.
RANGE (oC)
PART NUMBER
13
5
SUPPLY
GND
V-
6
8
INTEGRATOR
BANDWIDTH
SIG.
GND
11 CEXT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
HA-5320
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8V, -15V
Output Current, Continuous (Note 1) . . . . . . . . . . . . . . . . . . . ±20mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W) θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . .
70
18
PDIP Package . . . . . . . . . . . . . . . . . . .
75
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
90
N/A
Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range
HA-5320-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HA-5320-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
HA-5320-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Supply Voltage Range (Typical, Note 2) . . . . . . . . . ±13.5V to ±20V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Internal Power Dissipation may limit Output Current below 20mA.
2. Specification based on a one time characterization. This parameter is not guaranteed.
3. θJA is measured with the component mounted on an evaluation PC board in free air.
VSUPPLY = ±5.0V; CH = Internal; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold),
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified
Electrical Specifications
TEST
CONDITIONS
HA-5320-2/-9
HA-5320-5
TEMP.
(oC)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Input Voltage Range
Full
±10
-
-
±10
-
-
V
Input Resistance
25
1
5
-
1
5
-
MΩ
Input Capacitance
25
-
-
5
-
-
5
pF
Offset Voltage
25
-
0.2
-
-
0.5
-
mV
Full
-
-
2.0
-
-
1.5
mV
25
-
70
200
-
100
300
nA
Full
-
-
200
-
-
300
nA
25
-
30
100
-
30
300
nA
Full
-
-
100
-
-
300
nA
Full
±10
-
-
±10
-
-
V
PARAMETER
INPUT CHARACTERISTICS
Bias Current
Offset Current
Common Mode Range
VCM = ±5V
CMRR
Offset Voltage Temperature Coefficient
25
80
90
-
72
90
-
dB
Full
-
5
15
-
5
20
µV/ oC
TRANSFER CHARACTERISTICS
Gain
DC, (Note 12)
25
106
2 x 106
-
3 x 105
2 x 106
-
V/V
Gain Bandwidth Product
(AV = +1, Note 5)
CH = 100pF
25
-
2.0
-
-
2.0
-
MHz
CH = 1000pF
25
-
0.18
-
-
0.18
-
MHz
Output Voltage
Full
±10
-
-
±10
-
-
V
Output Current
25
±10
-
-
±10
-
-
mA
OUTPUT CHARACTERISTICS
Full Power Bandwidth
Note 4
25
-
600
-
-
600
-
kHz
Output Resistance
Hold Mode
25
-
1.0
-
-
1.0
-
Ω
Total Output Noise (DC to 10MHz)
Sample
25
-
125
200
-
125
200
µVRMS
Hold
25
-
125
200
-
125
200
µVRMS
2
HA-5320
VSUPPLY = ±5.0V; CH = Internal; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold),
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified (Continued)
Electrical Specifications
TEST
CONDITIONS
PARAMETER
HA-5320-2/-9
HA-5320-5
TEMP.
(oC)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
TRANSIENT RESPONSE
Rise Time
Note 5
25
-
100
-
-
100
-
ns
Overshoot
Note 5
25
-
15
-
-
15
-
%
Slew Rate
Note 6
25
-
45
-
-
45
-
V/µs
VIH
Full
2.0
-
-
2.0
-
-
V
VIL
Full
-
-
0.8
-
-
0.8
V
VIL = 0V
25
-
-
4
-
-
4
µA
Full
-
-
10
-
-
10
µA
Full
-
-
0.1
-
-
0.1
µA
To 0.1%
25
-
0.8
1.2
-
0.8
1.2
µs
To 0.01%
25
-
1.0
1.5
-
1.0
1.5
µs
Aperture Time (Note 8)
25
-
25
-
-
25
-
ns
Effective Aperture Delay Time
25
-50
-25
0
-50
-25
0
ns
Aperture Uncertainty
25
-
0.3
-
-
0.3
-
ns
Droop Rate
25
-
0.08
0.5
-
0.08
0.5
µV/µs
Full
-
17
100
-
1.2
100
µV/µs
25
-
8
50
-
8
50
pA
DIGITAL INPUT CHARACTERISTICS
Input Voltage
Input Current
VIH = +5V
SAMPLE AND HOLD CHARACTERISTICS
Acquisition Time (Note 7)
Drift Current
Note 9
Full
-
1.7
10
-
0.12
10
nA
Charge Transfer
Note 9
25
-
0.5
1.1
-
0.5
1.1
pC
Hold Step Error
Note 9
25
-
5
11
-
5
11
mV
Hold Mode Settling Time
To 0.01%
Full
-
165
350
-
165
350
ns
Hold Mode Feedthrough
10VP-P , 100kHz
Full
-
2
-
-
2
-
mV
Positive Supply Current
Note 10
25
-
11
13
-
11
13
mA
Negative Supply Current
Note 10
25
-
-11
-13
-
-11
-13
mA
Supply Voltage Range
Note 2
±13.5
−
±20
±13.5
-
±20
V
Power Supply Rejection
V+, Note 11
Full
80
-
-
80
-
-
dB
V-, Note 11
Full
65
-
-
65
-
-
dB
POWER SUPPLY CHARACTERISTICS
NOTES:
4. VO = 20VP-P; RL = 2kΩ; CL = 50pF; unattenuated output.
5. VO = 200mVP-P; RL = 2kΩ; CL = 50pF.
6. VO = 20V Step; RL = 2kΩ; CL = 50pF.
7. VO = 10V Step; RL = 2kΩ; CL = 50pF.
8. Derived from computer simulation only; not tested.
9. VIN = 0V, VIH = +3.5V, tR < 20ns (VIL to VIH).
10. Specified for a zero differential input voltage between +IN and -IN. Supply current will increase with differential input (as may occur in the Hold
mode) to approximately ±46mA at 20V.
11. Based on a 1V delta in each supply, i.e. 15V ±0.5VDC.
12. RL = 1kΩ, CL = 30pF.
3
HA-5320
Test Circuits and Waveforms
1
2
S/H
CONTROL
INPUT
14
-INPUT
OUTPUT
7
8
+INPUT
11
S/H CONTROL
VO
NC
NC
HA-5320
(CH = 100pF)
FIGURE 1. CHARGE TRANSFER AND DRIFT CURRENT
HOLD (+3.5V)
SAMPLE (0V)
S/H CONTROL
HOLD (+3.5V)
SAMPLE (0V)
S/H CONTROL
VO
∆VO
VO
∆t
VP
NOTES:
NOTES:
13. Observe the “hold step” voltage VP .
15. Observe the voltage “droop”, ∆VO/∆t.
16. Measure the slope of the output during hold, ∆VO/∆t, and
compute drift current: ID = CH ∆VO/∆t.
14. Compute charge transfer: Q = VPCH.
FIGURE 2. CHARGE TRANSFER TEST
FIGURE 3. DRIFT CURRENT TEST
V+
V IN
10VP-P
100kHz
SINE WAVE
VHA-5320
ANALOG
MUX OR
SWITCH
9
1
-IN
2
+IN
VOUT
OUT
14 S/H CONTROL
SUPPLY
CEXT
GND
AIN
S/H CONTROL
INPUT
13
TO
SUPPLY
COMMON
NOTE:
5
11
NC
REF
COM
6
TO
SIGNAL
GND
7
INT.
COMP.
Feedthrough in
V OUT
dB = 20 log --------------V IN
where:
VOUT = VP-P, Hold Mode, VIN = VP-P.
8
NC
FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION
Application Information
Hold Capacitor
The HA-5320 has the uncommitted differential inputs of an
op amp, allowing the Sample and Hold function to be
combined with many conventional op amp circuits. See the
Intersil Application Note AN517 for a collection of circuit
ideas.
The HA-5320 includes a 100pF MOS hold capacitor,
sufficient for most high speed applications (the Electrical
Specifications section is based on this internal capacitor).
Layout
A printed circuit board with ground plane is recommended
for best performance. Bypass capacitors (0.01µF to 0.1µF,
ceramic) should be provided from each power supply
terminal to the Supply Ground terminal on pin 13.
The ideal ground connections are pin 6 (SIG. Ground)
directly to the system Signal Ground, and pin 13 (Supply
Ground) directly to the system Supply Common.
4
Additional capacitance may be added between pins 7 and
11. This external hold capacitance will reduce droop rate at
the expense of acquisition time, and provide other trade-offs
as shown in the Performance Curves.
If an external hold capacitor CEXT is used, then a noise
bandwidth capacitor of value 0.1CEXT should be connected
from pin 8 to ground. Exact value and type are not critical.
The hold capacitor CEXT should have high insulation
resistance and low dielectric absorption, to minimize droop
errors. Polystyrene dielectric is a good choice for operating
temperatures up to 85oC. Teflon® and glass dielectrics offer
good performance to 125oC and above.
®Teflon is a registered Trademark of Dupont Corporation.
HA-5320
The hold capacitor terminal (pin 11) remains at virtual
ground potential. Any PC connection to this terminal should
be kept short and “guarded” by the ground plane, since
nearby signal lines or power supply voltages will introduce
errors due to drift current.
Aperture Time
Typical Application
Hold Step Error
Figure 5 shows the HA-5320 connected as a unity gain
noninverting amplifier - its most widely used configuration.
As an input device for a fast successive - approximation A/D
converter, it offers very high throughput rate for a monolithic
IC sample/hold amplifier. Also, the HA-5320’s hold step error
is adjustable to zero using the Offset Adjust potentiometer,
to deliver a 12-bit accurate output from the converter.
Hold Step Error is the output error due to Charge Transfer (see
above). It may be calculated from the specified parameter,
Charge Transfer, using the following relationship:
The application may call for an external hold capacitor CEXT as
shown. As mentioned earlier, 0.1CEXT is then recommended at
pin 8 to reduce output noise in the Hold mode.
Effective Aperture Delay Time (EADT)
The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is the interval
between the conditions of 10% open and 90% open.
Charge Transfer (pC)
Hold Step (V) = -----------------------------------------------------------Hold Capacitance (pF)
See Performance Curves.
The difference between the digital delay time from the Hold
command to the opening of the S/H switch, and the
propagation time from the analog input to the switch.
The HA-5320 output circuit does not include short circuit
protection, and consequently its output impedance remains
low at high frequencies. Thus, the step changes in load
current which occur during an A/D conversion are absorbed
at the S/H output with minimum voltage error. A momentary
short circuit to ground is permissible, but the output is not
designed to tolerate a short of indefinite duration.
EADT may be positive, negative or zero. If zero, the S/H
amplifier will output a voltage equal to VIN at the instant the
Hold command was received. For negative EADT, the output in
Hold (exclusive of pedestal and droop errors) will correspond to
a value of VIN that occurred before the Hold command.
Aperture Uncertainty
Glossary of Terms
The range of variation in Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Delay Uncertainty,
Aperture Time Jitter, etc.) sets a limit on the accuracy with
which a waveform can be reconstructed from sample data.
Acquisition Time
The time required following a “sample” command, for the
output to reach its final value within ±0.1% or ±0.01%. This is
the minimum sample time required to obtain a given accuracy,
and includes switch delay time, slewing time and settling time.
Drift Current
The net leakage current from the hold capacitor during the
hold mode. Drift current can be calculated from the droop
rate using the formula:
Charge Transfer
The small charge transferred to the holding capacitor from
the inter-electrode capacitance of the switch when the unit is
switched to the HOLD mode. Charge transfer is directly
proportional to sample-to-hold offset pedestal error, where:
Charge Transfer (pC) = CH (pF) x Hold Step Error (V)
OFFSET
ADJUST
±15mV
10kΩ
-15V +15V
HI-574A
3
4
5
9
11
CEXT
1
100pF
+
VIN
-
2
13
7
INPUT
-
DIGITAL
OUTPUT
+
14
S/H CONTROL
CONVERT
HA-5320
H
S
∆V
I D (pA) = C H ( pF ) × -------- (V/s)
∆t
6
13
5
8
R/C
0.1CEXT
SYSTEM POWER
GROUND
SYSTEM SIGNAL
GROUND
9
ANALOG
COMMON
NOTE: Pin Numbers Refer to
DIP Package Only.
FIGURE 5. TYPICAL HA-5320 CONNECTIONS; NONINVERTING UNITY GAIN MODE
5
HA-5320
Typical Performance Curves
CH = 100pF, INTERNAL
10
ACQUISITION TIME FOR
10V STEP TO +0.01% (µs)
5
1000
IDRIFT (pA)
VOLTAGE DROOP DURING
HOLD MODE, (mV/100ms)
1.0
0.5
0.1
SAMPLE-TO-HOLD OFFSET
(HOLD STEP) ERROR, (mV)
0.05
0.01
100
100
10
1
1000
10K
0
100K
-25
0
CH VALUE (pF)
FIGURE 6. TYPICAL SAMPLE AND HOLD PERFORMANCE
AS A FUNCTION OF HOLD CAPACITOR
25
50
75
TEMPERATURE (oC)
100
FIGURE 7. DRIFT CURRENT vs TEMPERATURE
100
0
80
45
PHASE
90
60
(CH = 100pF)
GAIN
GAIN
(CH = 1100pF)
40
135
180
20
0
PHASE (DEGREES)
GAIN (dB)
120
0
10
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 8. OPEN LOOP GAIN AND PHASE RESPONSE
CH = 100pF
TA = 25oC
-10
-8
-6
-4
5.0
CH = 100pF
0.5
CH = 1000pF
0.05
CH = 0.01µF
-2
2
4
6
75oC
HOLD STEP VOLTAGE
HOLD STEP VOLTAGE (mV)
8
DC INPUT (V)
FIGURE 9A. HOLD STEP vs INPUT VOLTAGE
10
25oC
2
3
4
LOGIC LEVEL HIGH (V)
FIGURE 9B. HOLD STEP vs LOGIC (VIH) VOLTAGE
FIGURE 9. TYPICAL SAMPLE-TO-HOLD OFFSET (HOLD STEP) ERROR
6
5
125
HA-5320
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos)
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
92 mils x 152 mils x 19 mils
METALLIZATION:
Type: Al, 1% Cu
Thickness: 16kÅ ±2kÅ
TRANSISTOR COUNT:
184
SUBSTRATE POTENTIAL:
V-
Metallization Mask Layout
HA-5320
CEXT
(11)
SUPPLY GND
(13)
V+
(9)
S/H CTRL (14)
-INPUT (1)
(8) INT BW
(7) OUTPUT
+INPUT (2)
(6) SIG GND
(3)
(4)
(5)
VIO ADJ
VIO ADJ
V-
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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