HB52RD168GB-F EO 128 MB Unbuffered SDRAM Micro DIMM 16-Mword × 64-bit, 100 MHz Memory Bus, 1-Bank Module (16 pcs of 16 M × 4 components) PC100 SDRAM L Description E0009H10 (1st edition) (Previous ADE-203-1153A (Z)) Jan. 19, 2001 Pr The HB52RD168GB is a 16M × 64 × 1 bank Synchronous Dynamic RAM Micro Dual In-line Memory Module (Micro DIMM), mounted 16 pieces of 64-Mbit SDRAM (HM5264405FTB) sealed in TCP package and 1 piece of ser ia l EEP RO M (2- kbit EEP RO M) for P rese nce De te ct (P D). An outline of the produc t is 144-pin Zig Za g Dua l tabs socke t type compa ct and thin pac kage . The ref ore, it make s high density mounting possible without surf ace mount tec hnology. It provide s common data inputs and outputs. De coupling ca pac itor s ar e mounted beside TCP on the module board. Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. uc od Features • 144-pin Zig Zag Dual tabs socket type Outline: 38.00 mm (Length) × 30.00 mm (Height) × 3.80 mm (Thickness) Lead pitch: 0.50 mm • 3.3 V power supply • Clock frequency: 100 MHz (max) • LVTTL interface • Data bus width: × 64 Non parity • Single pulsed RAS • 4 Banks can operates simultaneously and independently • Burst read/write operation and burst read/single write operation capability • Programmable burst length : 1/2/4/8/full page t This Product became EOL in October, 2005. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. HB52RD168GB-F L EO • 2 variations of burst sequence Sequential (BL = 1/2/4/8/full page) Interleave (BL = 1/2/4/8) • Programmable CE latency : 2/3 (HB52RD168GB-A6F/A6FL) : 3 (HB52RD168GB-B6F/B6FL) • Byte control by DQMB • Refresh cycles: 4096 refresh cycles/64 ms • 2 variations of refresh Auto refresh Self refresh • Low self refresh current: HB52RD168GB-A6FL/B6FL (L-version) • Full page burst length capability Sequential burst Burst stop capability Ordering Information Pr Type No. Frequency CE latency Package Contact pad HB52RD168GB-A6F HB52RD168GB-B6F HB52RD168GB-A6FL HB52RD168GB-B6FL 100 100 100 100 2/3 3 2/3 3 Micro DIMM (144-pin) Gold MHz MHz MHz MHz uc od Pin Arrangement Front Side 1pin 2pin 143pin 144pin Back Side t Data Sheet E0009H10 2 HB52RD168GB-F Pin Arrangement (cont.) EO Front side Back side Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name 1 VSS 73 NC 2 VSS 74 CK1 3 DQ0 75 VSS 4 DQ32 76 VSS 5 DQ1 77 NC 6 DQ33 78 NC 7 DQ2 79 NC 8 DQ34 80 NC 9 DQ3 81 VCC 10 DQ35 82 VCC 11 VCC 83 DQ16 12 VCC 84 DQ48 13 DQ4 85 DQ17 14 DQ36 86 DQ49 15 DQ5 87 DQ18 16 DQ37 88 DQ50 17 DQ6 89 DQ19 18 DQ38 90 DQ51 19 DQ7 91 VSS 20 DQ39 92 VSS 21 VSS 93 DQ20 22 VSS 94 DQ52 23 DQMB0 95 DQ21 24 DQMB4 96 DQ53 25 DQMB1 97 DQ22 26 DQMB5 98 DQ54 27 VCC 99 DQ23 28 VCC 100 DQ55 29 A0 101 VCC 30 A3 102 VCC 31 A1 103 A6 32 A4 104 A7 33 A2 105 A8 34 A5 106 A13 (BA0) 35 VSS 107 VSS 36 VSS 108 VSS 37 DQ8 109 A9 38 DQ40 110 A12 (BA1) 39 DQ9 111 A10 (AP) 40 DQ41 112 A11 41 DQ10 113 VCC 42 DQ42 114 VCC 43 DQ11 115 DQMB2 44 DQ43 116 DQMB6 45 VCC 117 DQMB3 46 VCC 118 DQMB7 47 DQ12 119 VSS 48 DQ44 120 VSS 49 DQ13 121 DQ24 50 DQ45 122 DQ56 51 DQ14 123 DQ25 52 DQ46 124 DQ57 53 DQ15 125 DQ26 54 DQ47 126 DQ58 55 VSS 127 DQ27 56 VSS 128 DQ59 57 NC 129 VCC 58 NC 130 VCC 59 NC 131 DQ28 60 NC 132 DQ60 61 CK0 133 DQ29 62 CKE0 134 DQ61 63 VCC 135 DQ30 64 VCC 136 DQ62 65 RE 137 DQ31 66 CE 138 L Pin No. t uc od Pr DQ63 Data Sheet E0009H10 3 HB52RD168GB-F Front side Back side Signal name Pin No. Signal name Pin No. 67 W 139 VSS 69 S0 141 71 NC 143 EO Pin No. Signal name Pin No. Signal name 68 NC 140 VSS SDA 70 NC 142 SCL VCC 72 NC 144 VCC Pin Description Function A0 to A11 Address input A12/A13 DQ0 to DQ63 S0 CE W DQMB0 to DQMB7 CK0/CK1 CKE0 Row address A0 to A11 Column address A0 to A9 Bank select address BA1, BA0 Data-input/output Chip select Pr RE L Pin name Row address asserted bank enable Column address asserted Write enable Byte input/output mask Clock input Clock enable uc od SDA Data-input/output for serial PD SCL Clock input for serial PD VCC Power supply VSS Ground NC No connection t Data Sheet E0009H10 4 HB52RD168GB-F Serial PD Matrix*1 EO Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 Number of bytes used by module manufacturer 1 0 0 0 0 0 0 0 80 128 1 Total SPD memory size 0 0 0 0 1 0 0 0 08 256 byte 2 Memory type 0 0 0 0 0 1 0 0 04 SDRAM 3 Number of row addresses bits 0 0 0 0 1 1 0 0 0C 12 4 Number of c olumn address es bit s 0 0 0 0 1 0 1 0 0A 10 5 Number of banks 0 0 0 0 0 0 0 1 01 1 6 Module data width 0 1 0 0 0 0 0 0 40 64 7 Module data width (continued) 0 0 0 0 0 0 0 0 00 0 (+) 8 Module interface signal levels 0 0 0 0 0 0 0 1 01 LVTTL 9 SDRAM cycle time (highest CE latency) 10 ns 1 0 1 0 0 0 0 0 A0 CL = 3 10 SDRAM access from Clock (highest CE latency) 6 ns 0 1 1 0 0 0 0 0 60 CL = 3 11 Module configuration type 0 0 0 0 0 0 0 0 00 Non parity 12 Refresh rate/type 1 0 0 0 0 0 0 0 80 Normal (15.625 µs) Self refresh 13 SDRAM width 0 0 0 0 0 1 0 0 04 16M × 4 14 Error checking SDRAM width 0 0 0 15 0 SDRAM device attributes: minimum clock delay for backto-back random column addresses 0 0 16 SDRAM device attributes: Burst lengths supported 1 0 0 17 SDRAM device attributes: number of banks on SDRAM device 0 0 0 18 SDRAM device attributes: CE latency 0 0 0 19 SDRAM device attributes: S latency 0 0 0 20 SDRAM device attributes: W latency 0 0 0 21 SDRAM module attributes 0 0 0 22 SDRAM device attributes: General 0 0 0 L Byte No. Function described uc od Pr 0 0 0 0 00 — 0 0 0 0 1 01 1 CLK 0 1 1 1 1 8F 1, 2, 4, 8, full page 0 0 1 0 0 04 4 0 0 1 1 0 06 2, 3 0 0 0 0 1 01 0 0 0 0 0 1 01 0 0 0 0 0 0 00 Unbuffer 0 1 1 1 0 0E t 0 VCC ± 10% Data Sheet E0009H10 5 HB52RD168GB-F Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 23 1 0 1 0 0 0 0 0 A0 1 1 1 1 0 0 0 0 F0 0 1 1 0 0 0 0 0 60 1 0 0 0 0 0 0 0 80 0 0 0 0 0 0 0 0 00 EO SDRAM cycle time (2nd highest CE latency) (-A6F/A6FL) 10 ns (-B6F/B6FL) 15 ns 24 SDRAM access from Clock (2nd highest CE latency) (-A6F/A6FL) 6 ns (-B6F/B6FL) 8 ns CL=2 CL=2 SDRAM cycle time (3rd highest CE latency) Undefined 26 SDRAM access from Clock (3rd 0 highest CE latency) Undefined 0 0 0 0 0 0 0 00 27 Minimum row precharge time 0 0 0 1 0 1 0 0 14 20 ns 28 Row active to row active min 0 0 0 1 0 1 0 0 14 20 ns 29 RE to CE delay min 0 0 0 1 0 1 0 0 14 20 ns 30 Minimum RE pulse width 0 0 1 1 0 0 1 0 32 50 ns 31 Density of each bank on module 0 0 1 0 0 0 0 0 20 128M byte 32 Address and command signal 0 input setup time 0 1 0 0 0 0 0 20 2 ns 33 Address and command signal 0 input hold time 0 0 1 0 0 0 0 10 1 ns 34 Data signal input setup time 0 0 1 35 Data signal input hold time 0 0 0 36 to 61 Superset information 0 0 0 62 SPD data revision code 0 0 0 63 Checksum for bytes 0 to 62 (-A6F/A6FL) 0 0 0 1 0 0 Manuf ac turer’s J EDEC I D c ode 0 0 0 65 to 71 Manuf ac turer’s J EDEC I D c ode 0 0 0 72 Manufacturing location × × × 73 Manufacturer’s part number 0 1 0 74 Manufacturer’s part number 0 1 0 75 Manufacturer’s part number 0 0 1 76 Manufacturer’s part number 0 0 1 77 Manufacturer’s part number 0 1 0 L 25 64 uc od Pr (-B6F/B6FL) 0 0 0 0 20 2 ns 1 0 0 0 0 10 1 ns 0 0 0 0 0 00 Future use 1 0 0 1 0 12 Rev. 1.2A 1 0 0 1 0 12 18 0 0 0 1 0 82 130 0 0 1 1 1 07 HITACHI 0 0 0 0 0 00 × × × × × ×× * 3 (ASCII-8bit code) 0 1 0 0 0 48 H 0 0 0 1 0 42 B 1 0 1 0 1 35 5 1 0 0 1 0 32 2 1 0 0 1 0 52 Data Sheet E0009H10 6 t 0 R HB52RD168GB-F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 78 Manufacturer’s part number 0 1 0 0 0 1 0 0 44 D 79 Manufacturer’s part number 0 0 1 1 0 0 0 1 31 1 80 Manufacturer’s part number 0 0 1 1 0 1 1 0 36 6 81 Manufacturer’s part number 0 0 1 1 1 0 0 0 38 8 82 Manufacturer’s part number 0 1 0 0 0 1 1 1 47 G 83 Manufacturer’s part number 0 1 0 0 0 0 1 0 42 B 84 Manufacturer’s part number 0 0 1 0 1 1 0 1 2D — 85 Manufacturer’s part number (-A6F/A6FL) 0 1 0 0 0 0 0 1 41 A 0 1 0 0 0 0 1 0 42 B EO Byte No. Function described L (-B6F/B6FL) 86 Manufacturer’s part number 0 0 1 1 0 1 1 0 36 6 87 Manufacturer’s part number 0 1 0 0 0 1 1 0 46 F 88 Manufacturer’s part number (L-version) 0 1 0 0 1 1 0 0 4C L Manufacturer’s part number 0 0 1 0 0 0 0 0 20 (Space) Pr Manufacturer’s part number 0 0 1 0 0 0 0 0 20 (Space) 90 Manufacturer’s part number 0 0 1 0 0 0 0 0 20 (Space) 91 Revision code 0 0 1 1 0 0 0 0 30 Initial 92 Revision code 0 0 1 0 0 0 0 0 20 (Space) 93 Manufacturing date × × × × × × × × ×× Year code (BCD)*4 94 Manufacturing date × × × × × × × × ×× Week code (BCD)*4 — — — — — — *5 0 0 1 0 0 64 100 MHz 0 0 1 1 1 C7 CL = 2, 3 0 0 1 0 1 C5 CL = 3 95 to 98 Assembly serial number *6 99 t o 125 Manufacturer specific data — — — 126 Intel specification frequency 0 1 1 127 Intel specification CE# latency 1 support (-A6F/A6FL) 1 0 1 0 (-B6F/B6FL) 1 uc od 89 t Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High” These SPD are based on Intel specification (Rev.1.2A). 2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119. 3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on ASCII code.) 4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary Coded Decimal”. 5. All bits of 99 through 125 are not defined (“1” or “0”). 6. Bytes 95 through 98 are assembly serial number. Data Sheet E0009H10 7 HB52RD168GB-F Block Diagram EO W S0 WE DQM DQMB0 8 N0 to N3 DQ0 to DQ7 I/O0 to I/O3 WE DQM I/O0 to I/O3 WE DQM 8 N4 to N7 DQ8 to DQ15 I/O0 to I/O3 WE DQM I/O0 to I/O3 WE DQ32 to DQ39 8 DQ16 to DQ23 N8 to N11 I/O0 to I/O3 WE DQM I/O0 to I/O3 WE DQMB3 D1 I/O0 to I/O3 CS WE DQMB5 D2 DQ40 to DQ47 I/O0 to I/O3 I/O0 to I/O3 CS WE DQ48 to DQ55 CS D7 RAS (D0 to D15) BA0 BA1 CKE0 A13 (D0 to D15) A12 (D0 to D15) CAS (D0 to D15) A0 to A11(D0 to D15) CKE (D0 to D15) CLK (D0, D1, D8, D9) CLK (D2, D3, D10, D11) CLK (D4, D5, D12, D13) CLK (D6, D7, D14, D15) VCC VCC (D0 to D15, U0) C0-C15 VSS (D0 to D15, U0) CS WE DQM I/O0 to I/O3 CS DQ56 to DQ63 D11 D12 8 N24 to N27 I/O0 to I/O3 D5 DQMB7 CS DQM CS RE CE A0 to A11 CK1 D10 8 N20 to N23 I/O0 to I/O3 D3 D4 D9 CS WE DQM DQMB6 CS DQM CS D6 8 N12 to N15 I/O0 to I/O3 WE DQM VSS WE DQM CS DQM CK0 D8 8 N16 to N19 I/O0 to I/O3 WE CS D13 CS DQM D14 8 N28 to N31 I/O0 to I/O3 uc od DQ24 to DQ31 CS DQM Pr DQM DQMB2 DQMB4 D0 L DQMB1 WE CS WE DQM I/O0 to I/O3 CS D15 Serial PD SCL SDA SCL A0 A1 A2 SDA U0 VSS Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D15: HM5264405 U0: 2-kbit EEPROM C0 to C15: 0.1 µF N0 to N31: Network resistors (10 Ω) t Data Sheet E0009H10 8 HB52RD168GB-F Absolute Maximum Ratings EO Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT –0.5 to VCC + 0.5 (≤ 4.6 (max)) V 1 Supply voltage relative to VSS VCC –0.5 to +4.6 V 1 Short circuit output current Iout 50 mA Power dissipation PT 16 W Operating temperature Topr 0 to +65 °C Storage temperature Tstg –55 to +125 °C Note: L 1. Respect to VSS . DC Operating Conditions (Ta = 0 to +65°C) Parameter Symbol Min Max Unit Notes Supply voltage VCC 3.0 3.6 V 1, 2 Input low voltage 0 0 V 3 VIH 2.0 VCC + 0.3 V 1, 4, 5 VIL –0.3 0.8 V 1, 6 All voltage referred to VSS The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. CK, CKE, S, DQMB, DQ pins: VIH (max) = VCC + 0.5 V for pulse width ≤ 5 ns at VCC. Others: VIH (max) = 4.6 V for pulse width ≤ 5 ns at VCC. VIL (min) = –1.0 V for pulse width ≤ 5 ns at VSS . t uc od Notes: 1. 2. 3. 4. 5. 6. Pr Input high voltage VSS Data Sheet E0009H10 9 HB52RD168GB-F VIL/VIH Clamp (Component characteristic) EO This SDRAM component has VIL and VIH clamp for CK, CKE, S, DQMB and DQ pins. Minimum VIL Clamp Current I (mA) –2 –32 –1.8 –25 –1.6 –19 –1.4 –13 L VIL (V) –1.2 –1 –0.9 –8 –4 –2 –0.8 –0.6 –0.6 0 Pr –0.4 0 –0.2 0 0 0 0 I (mA) –10 –15 –20 –25 –30 –35 –2 –1.5 –1 –0.5 0 uc od –5 VIL (V) t Data Sheet E0009H10 10 HB52RD168GB-F Minimum VIH Clamp Current EO VIH (V) I (mA) VCC + 2 10 VCC + 1.8 8 VCC + 1.6 5.5 VCC + 1.4 3.5 VCC + 1.2 1.5 VCC + 1 0.3 VCC + 0.8 0 L VCC + 0.6 VCC + 0.4 VCC + 0.2 VCC + 0 I (mA) 8 6 4 2 0 0 VCC + 0.5 uc od 0 VCC + 0 0 Pr 10 0 VCC + 1 VCC + 1.5 VCC + 2 VIH (V) t Data Sheet E0009H10 11 HB52RD168GB-F IOL/IOH Characteristics (Component characteristic) EO Output Low Current (I OL) I OL I OL Vout (V) Min (mA) Max (mA) 0 0 0 0.4 27 71 0.65 41 108 0.85 51 134 58 70 188 72 194 1.65 L 151 75 203 1.8 77 209 1.95 77 212 3 80 220 3.45 81 223 1 1.4 1.5 IOL (mA) 200 150 uc od Pr 250 min max 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 Vout (V) t Data Sheet E0009H10 12 HB52RD168GB-F Output High Current (I OH ) (Ta = 0 to 65˚C, VCC = 3.0 V to 3.45 V, VSS = 0 V) EO I OH I OH Vout (V) Min (mA) Max (mA) 3.45 — –3 3.3 — –28 3 0 –75 2.6 –21 –130 2.4 –34 –154 2 –59 –197 L 1.8 –227 –73 –248 –78 –270 –81 –285 1 –89 –345 0 –93 1.65 1.5 1.4 0 –200 0.5 1 –503 1.5 2 2.5 3 3.5 uc od IOH (mA) –100 0 Pr –67 min –300 –400 –500 –600 max Vout (V) t Data Sheet E0009H10 13 HB52RD168GB-F DC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) EO HB52RD168GB -A6F/B6F/A6FL/B6FL Parameter Symbol Min Max Unit Test conditions Notes Operating current I CC1 — 960 mA Burst length = 1 t RC = min 1, 2, 3 Standby current in power down I CC2P — 24 mA CKE0 = VIL, t CK = 12 ns 6 Standby current in power down I CC2PS (input signal stable) — 16 mA CKE0 = VIL, t CK = ∞ 7 Standby current in non power down — 160 mA CKE0, S = VIH, t CK = 12 ns 4 I CC2N L — 64 mA CKE0, S = VIH, t CK = 12 ns 1, 2, 6 Active standby current in non power down I CC3N — 288 mA CKE0, S = VIH, t CK = 12 ns 1, 2, 4 Burst operating current I CC4 — 880 mA t CK = min, BL = 4 1, 2, 5 Refresh current I CC5 Self refresh current I CC6 Self refresh current (L-version) I CC6 Input leakage current I LI Output leakage current I LO Output high voltage Output low voltage Pr Active standby current in power I CC3P down 1760 mA t RC = min 3 — 16 mA VIH ≥ VCC – 0.2 V VIL ≤ 0.2 V 8 — 9 mA –10 10 µA 0 ≤ Vin ≤ VCC –10 10 µA 0 ≤ Vout ≤ VCC DQ = disable VOH 2.4 — V I OH = –4 mA VOL — 0.4 V I OL = 4 mA uc od — Notes: 1. I CC depends on output load condition when the device is selected. I CC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK0/CK1 operating current. 7. After power down mode, no CK0/CK1 operating current. 8. After self refresh mode set, self refresh current. t Data Sheet E0009H10 14 HB52RD168GB-F Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) EO Parameter Symbol Max Unit Notes Input capacitance (Address) CIN 90 pF 1, 2, 4 Input capacitance (RE, CE, W, S0, CKE0) CIN 90 pF 1, 2, 4 Input capacitance (CK0/CK1) CIN 60 pF 1, 2, 4 Input capacitance (DQMB0 to DQMB7) CIN 20 pF 1, 2, 4 Input/Output capacitance (DQ0 to DQ63) CI/O 20 pF 1, 2, 3, 4 Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested. L Notes: 1. 2. 3. 4. t uc od Pr Data Sheet E0009H10 15 HB52RD168GB-F AC Characteristics (Ta = 0 to 65˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) EO HB52RD168GB -A6F/A6FL -B6F/B6FL PC100 Symbol Symbol Min Max Min Max Unit Notes System clock cycle time (CE latency = 2) t CK Tclk 10 — 15 — ns 1 (CE latency = 3) t CK Tclk 10 — 10 — ns CK high pulse width t CKH Tch 3 — 3 — ns 1 CK low pulse width t CKL Tcl 3 — 3 — ns 1 1, 2 Access time from CK (CE latency = 2) L Parameter Tac — 6 — 8 ns t AC Tac — 6 — 6 ns t OH Toh 3 — 3 — ns 1, 2 CK to Data-out low impedance t LZ 2 — 2 — ns 1, 2, 3 CK to Data-out high impedance t HZ — 6 — 6 ns 1, 4 Tsi 2 — 2 — ns 1, 5, 6 Tpde 2 — 2 — ns 1 (CE latency = 3) Data-out hold time Data-in setup time Pr t AC t AS , t CS, t DS, t CES CKE setup time for power down t CESP exit t AH, t CH, t DH, t CEH Thi 1 — 1 — ns 1, 5 Ref/Active to Ref/Active command period t RC Trc 70 — 70 — ns 1 Active to Precharge command period t RAS Tras 50 120000 50 120000 ns 1 Active command to column command (same bank) t RCD Trcd 20 — 20 — ns 1 Precharge to active command period t RP Trp 20 — 20 — ns 1 Write recovery or data-in to precharge lead time t DPL Tdpl 10 — 10 — ns 1 Active (a) to Active (b) command period t RRD Trrd 20 — 20 — ns 1 Transition time (rise and fall) tT 1 5 1 5 ns Refresh period t REF — 64 — 64 ms t uc od Data-in hold time Data Sheet E0009H10 16 HB52RD168GB-F AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is CL = 50 pF. t LZ (min) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES define CKE setup time to CK rising edge except power down exit command. t AS /tAH: Address, t CS/tCH: S, RE, CE, W, DQMB t DS/tDH: Data-in, t CES/tCEH : CKE EO Notes: 1. 2. 3. 4. 5. 6. Test Conditions • Input and output timing reference levels: 1.5 V L • Input waveform and output load: See following figures 2.4 V input 0.4 V I/O 2.0 V 0.8 V Pr t T CL tT t uc od Data Sheet E0009H10 17 HB52RD168GB-F Relationship Between Frequency and Minimum Latency EO HB52RD168GB Parameter -A6F/A6FL/B6F/B6FL Frequency (MHz) 100 tCK (ns) Symbol Active command to column command (same bank) PC100 Symbol Notes lRCD 2 1 Active command to active command (same bank) lRC 7 = [lRAS+ lRP] 1 Active command to precharge command (same bank) lRAS 5 1 Precharge command to active command (same bank) lRP 2 1 Write recovery or data-in to precharge command (same bank) lDPL 1 1 Active command to active command (different bank) lRRD 2 1 L 10 Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Pr Self refresh exit time Tdpl lSREX Tsrx 1 2 lAPW Tdal 3 = [lDPL + lRP] 7 = [lRC] 3 lSEC (CE latency = 3) lHZP lHZP Last data out to active command (auto precharge) (same bank) lAPR Last data out to precharge (early precharge) (CE latency = 2) (CE latency = 3) lEP lEP Column command to column command lCCD Write command to data in latency lWCD DQMB to data in lDID DQMB to data out lDOD CKE to CK disable lCLE Register set to active command lRSA uc od Precharge command to high impedance (CE latency = 2) Troh 2 Troh 3 1 –1 –2 Tccd 1 Tdwd 0 Tdqm 0 Tdqz 2 Tcke 1 Tmrd 1 t Data Sheet E0009H10 18 HB52RD168GB-F HB52RD168GB -A6F/A6FL/B6F/B6FL Frequency (MHz) 100 EO Parameter PC100 Symbol tCK (ns) Symbol S to command disable lCDD 0 Power down exit to command input lPEC 1 Burst stop to output valid data hold (CE latency = 2) lBSR 1 lBSR 2 (CE latency = 3) (CE latency = 3) L Burst stop to output high impedance (CE latency = 2) Burst stop to write data ignore 10 lBSH 2 lBSH 3 lBSW 0 Notes t uc od Pr Notes: 1. lRCD to lRRD are recommended value. 2. Be valid [DSEL] or [NOP] at next command of self refresh exit. 3. Except [DSEL] and [NOP]. Data Sheet E0009H10 19 HB52RD168GB-F Pin Functions EO CK0/CK1 (in pu t p in ): C K is the master cloc k input to this pin. The other input signals ar e re fe rre d at C K rising edge. S 0 (in pu t p in ): Whe n S is Low, the command input cyc le bec omes valid. Whe n S is High, all inputs ar e ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM modules, they func tion in a diffe re nt wa y. The se pins def ine oper ation commands (r ea d, wr ite , etc .) depe nding on the combination of their voltage levels. For details, refer to the command operation section. L A0 to A11 (in pu t p in s): R ow addr ess (A X0 to AX11) is dete rmined by A0 to A11 leve l at the bank ac tive command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or wr ite command cyc le C K rising edge . And this column addr ess bec omes burst ac ce ss start addr ess. A10 def ines the pre cha rge mode. Whe n A10 = High at the pre cha rge command cyc le, both banks ar e pre cha rged. B ut whe n A10 = Low at the pre cha rge command cyc le, only the bank that is sele cted by A12/A13 (B A) is precharged. Pr A12/A13 (input pin): A12/A13 is a bank select signal (BA). The memory array is divided into bank0, bank1, bank2 and bank3. If A12 is Low and A13 is Low, bank0 is selected. If A12 is High and A13 is Low, bank1 is selected. If A12 is Low and A13 is High, bank2 is selected. If A12 is High and A13 is HIgh, bank3 is selected. CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next C K rising edge is valid. If C KE is Low, the next C K rising edge is invalid. This pin is used for powe r-dow n and clock suspend modes. uc od DQMB 0 to DQMB 7 (in pu t p in s): R ea d oper ation: If DQMB is High, the output buff er bec omes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Wr ite oper ation: If DQMB is High, the pre vious data is held (the new data is not wr itten) . If DQMB is Low, the data is written. DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. VCC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected. Detailed Operation Part Refer to the HM5264165F/HM5264805F/HM5264405F-75/A60/B60 datasheet. t Data Sheet E0009H10 20 HB52RD168GB-F Physical Outline EO Unit: mm (38.0) 1 A 17.625 3.80 Max B ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; 3.5 Min 3.5 Min 1.0 Min 2.5 Min ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;; (front) ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; L 15.0 30.0 1.0 Min 42.0 Max 0.80 ± 0.08 35.50 0.875 Pr 37.0 ± 0.08 35.50 17.875 ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;; (back) ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; 2 1.0 Min uc od 4-R1.0 ± 0.1 0.625 4.0 ± 0.1 R1.0 ± 0.1 1.0 Min Detail B Detail A 0.37 ± 0.03 t 1.0 ± 0.08 0.25 Max 5.0 ± 0.1 2.00 Min 0.50 Data Sheet E0009H10 21 HB52RD168GB-F Cautions EO L 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. t uc od Pr Data Sheet E0009H10 22