AVAGO HCPL-3140-500E 0.4 amp output current igbt gate drive optocoupler Datasheet

HCPL-3140, HCPL-0314
0.4 Amp Output Current IGBT Gate Drive Optocoupler
Data Sheet
Description
The HCPL-3140/HCPL-0314 family of devices consists
of a GaAsP LED optically coupled to an integrated
circuit with a power output stage. These optocouplers are ideally suited for driving power IGBTs
and MOSFETs used in motor control inverter
applications. The high operating voltage range of the
output stage provides the drive voltages required by
gate controlled devices. The voltage and current
supplied by this optocoupler makes it ideally suited for
directly driving small or medium power IGBTs. For
IGBTs with higher ratings, the HCPL-3150 (0.5 A) or
HCPL-3120 (2.0 A) opto-couplers can be used.
Functional Diagram
N/C
1
8
VCC
ANODE
2
7
N.C.
CATHODE
3
6
VO
N/C
4
5
VEE
SHIELD
Features
• 0.4 A minimum peak output current
• High speed response:
0.7 µs maximum propagation delay over temperature
range
• Ultra high CMR: minimum 25 kV/µs at VCM = 1 kV
• Bootstrappable supply current: maximum 3 mA
• Wide operating temperature range: –40°C to 100°C
• Wide VCC operating range: 10 V to 30 V over temp.
range
• Available in DIP8 and SO8 package
• Safety approvals: UL approval, 3750 Vrms for 1 minute.
CSA approval. IEC/EN/DIN EN 60747-5-2 approval
VIORM = 630 Vpeak (HCPL-3140)
Applications
• Isolated IGBT/Power MOSFET gate drive
• AC and brushless DC motor drives
• Inverters for home appliances
• Industrial inverters
• Switch Mode Power Supplies (SMPS)
HCPL-3140/HCPL-0314
Truth Table
LED
VO
OFF
LOW
ON
HIGH
A 0.1 µF bypass capacitor must be
connected between pins VCC and VEE.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage
and/or degradation which may be induced by ESD.
Ordering Information
HCPL-3140 and HCPL-0314 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part
Number
RoHS
Compliant
Non RoHS
Compliant
HCPL-3140
-000E
No option
-300E
#300
-500E
#500
-060E
#060
-360E
#360
X
X
-560E
#560
X
X
-000E
No option
X
-500E
#500
-060E
#060
-560E
#560
HCPL-3140
HCPL-0314
HCPL-0314
Package
Surface
Mount
Gull
Wing
Tape
& Reel
IEC/EN/DIN
EN 60747-5-2
Quantity
50 per tube
300 mil
DIP-8
X
X
X
X
X
SO-8
50 per tube
X
X
50 per tube
X
50 per tube
X
1000 per reel
100 per tube
X
X
X
1000 per reel
X
X
1500 per reel
X
100 per tube
X
1500 per reel
To order, choose a part number from the part number column and combine with the desired option from
the option column to form an order entry.
Example 1:
HCPL-3140-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel
packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-3140 to order product of 300 mil DIP package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for
information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th
July 2001 and RoHS compliant option will use ‘-XXXE’.
Package Outline Drawings
HCPL-3140 Standard DIP Package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
TYPE NUMBER
8
7
6
5
OPTION CODE*
6.35 ± 0.25
(0.250 ± 0.010)
DATE CODE
A XXXXZ
YYWW RU
1
1.19 (0.047) MAX.
2
3
4
UL
RECOGNITION
1.78 (0.070) MAX.
5° TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
2
HCPL-3140 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
6
7
8
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
1
3
2
10.9 (0.430)
4
2.0 (0.080)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
HCPL-0314 Small Outline SO-8 Package
LAND PATTERN RECOMMENDATION
8
7
6
5
5.994 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
7.49 (0.295)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
PIN ONE 1
2
3
0.406 ± 0.076
(0.016 ± 0.003)
4
1.9 (0.075)
1.270 BSC
(0.050)
0.64 (0.025)
* 5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
7°
45° X
0.432
(0.017)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
0.305 MIN.
(0.012)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
3
Solder Reflow Temperature Profile
Regulatory Information
The HCPL-3140/HCPL-0314 have
been approved by the following
organizations:
300
TEMPERATURE (°C)
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
2.5°C ± 0.5°C/SEC.
30
SEC.
160°C
150°C
140°C
SOLDERING
TIME
200°C
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01
(Option 060 only)
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
50
0
100
150
200
250
TIME (SECONDS)
UL
Approval under UL 1577,
component recognition program
up to VISO = 2500 Vrms. File
E55361.
Note: Non-halide flux should be used.
Recommended Pb-Free IR Profile
tp
Tp
TEMPERATURE
TL
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
260 +0/-5 °C
217 °C
RAMP-UP
3 °C/SEC. MAX.
Tsmax 150 - 200 °C
CSA
Approval under CSA Component
Acceptance Notice #5, File CA
88324.
RAMP-DOWN
6 °C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
tL
60 to 150 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
Note: Non-halide flux should be used.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics (HCPL-3140 Option 060)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875=VPR, 100% Production Test with
tm=1 sec, Partial discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec,
Partial discharge < 5 pC
Highest Allowable Overvoltage
(Transient Overvoltage tini = 10 sec)
Safety-limiting values - maximum values allowed in the
event of a failure.
Case Temperature
Input Current**
Output Power**
Insulation Resistance at TS, VIO = 500 V
Symbol
Characteristic
Unit
VIORM
I - IV
I - III
I-II
55/100/21
2
630
Vpeak
VPR
1181
Vpeak
VPR
945
Vpeak
VIOTM
6000
Vpeak
TS
IS,INPUT
PS, OUTPUT
RS
175
230
600
>10 9
°C
mA
mW
Ω
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/
DIN EN 60747-5-2 for a detailed description of Method a and Method b partial discharge test profiles.
** Refer to the following figure for dependence of PS and IS on ambient temperature.
4
OUTPUT POWER – PS, INPUT CURRENT – IS
800
PS (mW)
IS (mA)
700
600
500
400
300
200
100
0
0
25
50
75 100 125 150 175 200
TS – CASE TEMPERATURE – °C
Insulation and Safety Related Specifications
Parameter
Symbol
HCPL-3140
HCPL-0314
Units
Conditions
Minimum External Air Gap
(Clearance)
L(101)
7.1
4.9
mm
Measured from input terminals
to output terminals, shortest
distance through air.
Minimum External Tracking
(Creepage)
L(102)
7.4
4.8
mm
Measured from input terminals
to output terminals, shortest
distance path along body.
0.08
0.08
mm
Through insulation distance
conductor to conductor, usually
the straight line distance
thickness between the emitter
and detector.
>175
>175
V
DIN IEC 112/VDE 0303 Part 1
IIIa
IIIa
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
Material Group (DIN VDE
0110, 1/89, Table 1)
Absolute Maximum Ratings
5
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Note
Operating Temperature
TA
-40
100
°C
Average Input Current
IF(AVG)
25
mA
Peak Transient Input Current (<1 µs pulse
width, 300pps)
IF(TRAN)
1.0
A
Reverse Input Voltage
VR
5
V
“High” Peak Output Current
IOH(PEAK)
0.6
A
2
“Low” Peak Output Current
IOL(PEAK)
0.6
A
2
Supply Voltage
VCC-VEE
-0.5
35
V
Output Voltage
VO(PEAK)
-0.5
VCC
V
Output Power Dissipation
PO
250
mW
3
Input Power Dissipation
PI
45
mW
4
Lead Solder Temperature
260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile
See Package Outline Drawings section
1
Recommended Operating Conditions
Parameter
Power Supply
Input Current (ON)
Input Voltage (OFF)
Operating Temperature
Symbol
VCC -VEE
IF(ON)
VF(OFF)
TA
Min.
10
8
- 3.6
- 40
Max.
30
12
0.8
100
Units
V
mA
V
°C
Note
Electrical Specifications (DC)
Over recommended operating conditions unless otherwise specified.
Parameter
High Level Output Current
6
Symbol
IOH
Low Level Output Current
IOL
High Level Output Voltage
Low Level Output Voltage
High Level Supply Current
Low Level Supply Current
Threshold Input Current
Low to High
Threshold Input Voltage
High to Low
Input Forward Voltage
Temperature Coefficient of
Input Forward Voltage
Input Reverse Breakdown
Voltage
Input Capacitance
VOH
VOL
ICCH
ICCL
IFLH
Min.
0.2
0.4
0.2
0.4
VCC-4
VFHL
0.8
VF
DVF/DTA
1.2
BVR
5
CIN
Typ.
0.5
0.4
0.5
VCC-1.8
0.4
0.7
1.2
Max.
Units
A
A
1
3
3
7
V
V
mA
mA
mA
Test
Conditions
Vo = VCC- 4
Vo = VCC-10
Vo = VEE+2.5
Vo = VEE+10
Io = -100 mA
Io = 100 mA
Io = 0 mA
Io = 0 mA
Io = 0 mA,
Vo>5 V
Fig.
2
3
5
6
1
4
7,8
9,15
V
1.5
–1.6
60
1.8
V
mV/°C
IF = 10 mA
V
IR = 10 µA
pF
f = 1 MHz,
VF = 0 V
16
Note
5
2
5
2
6,7
14
Switching Specifications (AC)
Over recommended operating conditions unless otherwise specified.
Parameter
Propagation Delay Time to
High Output Level
Symbol
tPLH
Min.
0.1
Typ.
0.2
Max.
0.7
Units
µs
Propagation Delay Time to
Low Output Level
Propagation Delay
Difference Between Any
Two Parts or Channels
Rise Time
Fall Time
Output High Level Common
Mode Transient Immunity
Output Low Level Common
Mode Transient Immunity
tPHL
0.1
0.3
0.7
µs
PDD
-0.5
0.5
µs
tR
tF
|CMH|
25
50
50
35
ns
ns
kV/µs
|CML|
25
35
kV/µs
Symbol
VISO
Min.
3750
Test
Conditions
Rg = 47 Ω,
Cg = 3 nF,
f = 10 kHz,
Duty Cycle =
50%,
IF = 8 mA,
VCC = 30 V
TA = 25°C,
VCM = 1 kV
Fig.
10,11,
12,13,
Note
14
14,17
10
18
11
18
12
Fig.
Note
8,9
Package Characteristics
Parameter
Input-Output Momentary
Withstand Voltage
Input-Output Resistance
Input-Output Capacitance
RI-O
CI-O
Typ.
1012
0.6
Max.
Units
Vrms
Ω
pF
Test
Conditions
TA=25°C,
RH<50% for
VI-O=500 V
Freq=1 MHz
9
Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak
minimum = 0.4 A. See Application section for additional details on limiting IOL peak.
3. Derate linearly above 85°C, free air temperature at the rate of 4.0 mW/°C.
4. Input power dissipation does not require derating.
5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
6. In this test, VOH is measured with a DC load current. When driving capacitive load VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detection
current limit II-O ≤ 5 µA). This test is performed before 100% production test for partial discharge (method B) shown in the IEC/EN/DIN EN
60747-5-2 Insulation Characteristics Table, if applicable.
9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.
10. PDD is the difference between tPHL and tPLH between any two parts or channels under the same test conditions.
11. Common mode transient immunity in the high state is the maximum tolerable |dVcm/dt| of the common mode pulse VCM to assure that the output
will remain in the high state (i.e. Vo > 6.0 V).
12. Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e. Vo < 1.0 V).
13. This load condition approximates the gate load of a 1200 V/25 A IGBT.
14. The power supply current increases when operating frequency and Qg of the driven IGBT increases.
7
-0.5
-1.0
-1.5
-2.0
-25
0
25
50
75
100 125
0.34
0.32
0.30
-50
TA – TEMPERATURE – °C
Figure 1. VOH vs. temperature.
75
100 125
0.40
-25
0
25
50
75
0.455
0.450
0.445
-25
0
25
50
75
100 125
1.4
0.6
0.4
ICCL
0.2
ICCH
-25
0
25
50
75
100 125
TA – TEMPERATURE – °C
Figure 7. ICC vs. temperature.
ICC – SUPPLY CURRENT – mA
0.8
-3
-4
-5
-6
0.2
0.4
0.6
IOH – OUTPUT HIGH CURRENT – A
20
15
10
5
0
0
0.8
0.6
0.4
ICCL
ICCH
0.2
15
20
25
VCC – SUPPLY VOLTAGE – V
Figure 8. ICC vs. VCC.
100 200 300 400 500 600 700
Figure 6. VOL vs. IOL.
1.0
0
10
0
IOL – OUTPUT LOW CURRENT – mA
1.2
1.0
-2
TA – TEMPERATURE – °C
Figure 5. IOL vs. temperature.
1.2
VOH
-1
25
0.460
0.440
-50
100 125
0
Figure 3. VOH vs. IOH.
VOL – OUTPUT LOW VOLTAGE – V
IOL – OUTPUT LOW CURRENT – A
0.41
Figure 4. VOL vs. temperature.
ICC – SUPPLY CURRENT – mA
50
0.465
TA – TEMPERATURE – °C
8
25
0.470
0.42
0
-50
0
Figure 2. IOH vs. temperature.
0.43
0.39
-50
-25
TA – TEMPERATURE – °C
0.44
VOL – OUTPUT LOW VOLTAGE – V
0.36
30
IFLH – LOW TO HIGH CURRENT THRESHOLD – mA
-2.5
-50
0.38
(VOH-VCC) – OUTPUT HIGH VOLTAGE DROP – V
IOH – OUTPUT HIGH CURRENT – A
(VOH-VCC) – HIGH OUTPUT VOLTAGE DROP – V
0.40
0
3.5
3.0
2.5
2.0
1.5
-50
-25
0
25
50
75
100 125
TA – TEMPERATURE – °C
Figure 9. IFLH vs. temperature.
400
300
200
100
TPLH
TPHL
0
10
15
20
25
300
200
100
0
30
500
TP – PROPAGATION DELAY – ns
TP – PROPAGATION DELAY – ns
6
Figure 10. Propagation delay vs. VCC.
TP – PROPAGATION DELAY – ns
TP – PROPAGATION DELAY – ns
350
TPLH
300
TPHL
250
0
50
100
150
200
Figure 13. Propagation delay vs. Rg.
20
15
10
5
1.4
1.6
200
100
1.8
VF – FORWARD VOLTAGE – V
Figure 16. Input current vs. forward voltage.
-25
0
25
50
75
100 125
TA – TEMPERATURE – °C
Figure 12. Propagation delay vs. temperature.
300
200
100
TPLH
TPHL
0
TPLH
TPHL
35
30
25
20
15
10
5
0
-5
0
20
40
60
80
Cg – LOAD CAPACITANCE – nF
Figure 14. Propagation delay vs. Cg.
25
0
1.2
300
0
-50
18
400
Rg – SERIES LOAD RESISTANCE – Ω
IF – FORWARD CURRENT – mA
15
Figure 11. Propagation delay vs. IF.
400
9
12
400
IF – FORWARD LED CURRENT – mA
VCC – SUPPLY VOLTAGE – V
200
9
VO – OUTPUT VOLTAGE – V
TP – PROPAGATION DELAY – ns
400
100
0
1
2
3
4
5
IF – FORWARD LED CURRENT – mA
Figure 15. Transfer characteristics.
6
8
1
0.1 µF
IF = 7 to 16 mA
+
10 KHz –
500 Ω
2
+
–
7
IF
VCC = 15
to 30 V
tr
tf
VO
50% DUTY
CYCLE
6
3
90%
47 Ω
50%
VOUT
3 nF
4
10%
5
tPLH
tPHL
Figure 17. Propagation delay test circuit and waveforms.
VCM
5V
δt
0.1 µF
A
B
δV
8
1
IF
2
VO
3
6
4
5
VCC = 30 V
VO
–
Figure 18. CMR test circuit and waveforms.
10
VOH
SWITCH AT A: IF = 10 mA
SWITCH AT B: IF = 0 mA
+
∆t
∆t
+
–
VO
VCM = 1500 V
VCM
0V
7
+
–
=
VOL
Applications Information
Eliminating Negative IGBT Gate
Drive
To keep the IGBT firmly off,
the HCPL-3140/HCPL-0314 has a
very low maximum VOL
specification of 1.0 V. Minimizing
Rg and the lead inductance from
the HCPL-3140/HCPL-0314 to
the IGBT gate and emitter
(possibly by mounting the
HCPL-3140/HCPL-0314 on a
small PC board directly above the
IGBT) can eliminate the need for
negative IGBT gate drive in many
applications as shown in
Figure 19. Care should be taken
with such a PC board design to
avoid routing the IGBT collector
or emitter traces close to the
HCPL-3140/HCPL-0314 input as
this can result in unwanted
coupling of transient signals into
the input of HCPL-3140/
HCPL-0314 and degrade
performance. (If the IGBT
drain must be routed near the
HCPL-3140/HCPL-0314 input,
then the LED should be reverse
biased when in the off state, to
prevent the transient signals
coupled from the IGBT drain
from turning on the HCPL-3140/
HCPL-0314.)
HCPL-3140/HCPL-0314
+5 V
1
270 Ω
8
0.1 µF
2
+
–
VCC = 15 V
+ HVDC
7
Rg
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
3
6
4
5
Figure 19. Recommended LED drive and application circuit for HCPL-3140/HCPL-0314.
11
Q1
3-PHASE
AC
Q2
- HVDC
Rg ≥
=
VCC – VOL
IOLPEAK
24 V – 5 V
0.6A
= 32 Ω
The VOL value of 5 V in the previous equation is the VOL at the peak
current of 0.6A. (See Figure 6).
Step 2: Check the HCPL-3140/HCPL-0314 power dissipation and
increase Rg if necessary. The HCPL-3140/HCPL-0314 total power
dissipation (PT) is equal to the sum of the emitter power (PE) and the
output power (PO).
PT = PE + PO
PE = IF • VF • Duty Cycle
PO = PO(BIAS) + PO(SWITCHING) = ICC • VCC + ESW (Rg,Qg)• f
= (ICCBIAS + KICC • Qg • f) • VCC + ESW (Rg,Qg) • f
where KICC • Qg • f is the increase in ICC due to switching and KICC is a
constant of 0.001 mA/(nC*kHz). For the circuit in Figure 19 with IF
(worst case) = 10 mA, Rg = 32 Ω, Max Duty Cycle = 80%,
Qg = 100 nC, f = 20 kHz and TAMAX = 85°C:
PE = 10 mA • 1.8 V • 0.8 = 14 mW
PO = (3 mA + (0.001 mA/(nC • kHz)) • 20 kHz • 100 nC) • 24 V +
0.4 µJ • 20 kHz = 128 mW
< 250 mW (PO(MAX) @ 85°C)
The value of 3 mA for ICC in the previous equation is the max. ICC over
entire operating temperature range.
Since PO for this case is less than PO(MAX), Rg = 32 Ω is alright for the
power dissipation.
Esw – ENERGY PER SWITCHING CYCLE – µJ
Selecting the Gate Resistor (Rg)
Step 1: Calculate Rg minimum from the IOL peak specification. The IGBT
and Rg in Figure 19 can be analyzed as a simple RC circuit with a
voltage supplied by the HCPL-3140/HCPL-0314.
4.0
Qg = 50 nC
3.5
Qg = 100 nC
Qg = 200 nC
3.0
Qg = 400 nC
2.5
2.0
1.5
1.0
0.5
0
0
20
40
60
80
100
Rg – GATE RESISTANCE – Ω
Figure 20. Energy dissipated in the
HCPL-0314 and for each IGBT switching
cycle.
LED Drive Circuit Considerations for
Ultra High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC
as shown in Figure 21. The
HCPL-3140/HCPL-0314 improves
CMR performance by using a
detector IC with an optically
transparent Faraday shield, which
diverts the capacitively coupled
current away from the sensitive
IC circuitry. However, this shield
does not eliminate the capacitive
coupling between the LED and
opto-coupler pins 5-8 as shown in
Figure 22. This capacitive
coupling causes perturbations in
the LED current during common
mode transients and becomes the
major source of CMR failures for
a shielded optocoupler. The main
design objective of a high CMR
LED drive circuit becomes
keeping the LED in the proper
state (on or off ) during common
mode transients. For example,
the recommended application
circuit (Figure 19), can achieve
10 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in
the proper state are discussed in
the next two sections.
12
1
8
1
7
2
CLEDO1
CLEDP
8
CLEDP
2
7
CLEDO2
3
CLEDN
4
6
3
5
4
Figure 21. Optocoupler input to output capacitance model
for unshielded optocouplers.
+5 V
5
SHIELD
Figure 22. Optocoupler input to output capacitance model
for shielded optocouplers.
8
1
0.1
µF
CLEDP
2
+
VSAT
–
6
CLEDN
7
+
–
VCC = 18 V
ILEDP
3
4
•••
6
CLEDN
Rg
5
SHIELD
•••
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dVCM/dt.
+ –
VCM
Figure 23. Equivalent circuit for Figure 17 during common mode transient.
8
1
+5 V
8
1
+5 V
CLEDP
2
3
Q1
CLEDN
CLEDP
7
2
6
3
5
4
7
CLEDN
6
ILEDN
4
SHIELD
Figure 24. Not recommended open collector drive circuit.
13
SHIELD
5
Figure 25. Recommended LED drive circuit for ultra-high CMR IPM
dead time and propagation delay specifications.
CMR with the LED On (CMRH)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED
current of 8 mA provides
adequate margin over the
maximum IFLH of 5 mA to
achieve 10 kV/µs CMR.
CMR with the LED Off (CMRL)
A high CMR LED drive
circuit must keep the LED off
(VF ≤ VF(OFF)) during common
mode transients. For example,
during a -dVCM/dt transient in
Figure 23, the current flowing
through CLEDP also flows
through the RSAT and VSAT of the
logic gate. As long as the low
state voltage developed across
the logic gate is less than VF(OFF)
the LED will remain off and no
common mode failure will occur.
The open collector drive circuit,
shown in Figure 24, can not keep
the LED off during a +dVCM/dt
transient, since all the current
flowing through CLEDN must be
14
supplied by the LED, and it is
not recommended for
applications requiring ultra high
CMR1 performance. The
alternative drive circuit which
like the recommended
application circuit (Figure 19),
does achieve ultra high CMR
performance by shunting the
LED in the off state.
IPM Dead Time and Propagation
Delay Specifications
The HCPL-3140/HCPL-0314
includes a Propagation Delay
Difference (PDD) specification
intended to help designers
minimize “dead time” in their
power inverter designs. Dead
time is the time high and low
side power transistors are off.
Any overlap in Ql and Q2
conduction will result in large
currents flowing through the
power devices from the highvoltage to the low-voltage motor
rails. To minimize dead time in a
given design, the turn on of
LED2 should be delayed (relative
to the turn off of LED1) so that
under worst-case conditions,
transistor Q1 has just turned off
when transistor Q2 turns on, as
shown in Figure 26. The amount
of delay necessary to achieve this
condition is equal to the
maximum value of the
propagation delay difference
specification, PDD max, which is
specified to be 500 ns over the
operating temperature range of
-40° to 100°C.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but it
does not tell a designer what the
maximum dead time will be. The
maximum dead time is equivalent
to the difference between the
maximum and minimum
propagation delay difference
specification as shown in
Figure 27. The maximum dead
time for the HCPL-3140/HCPL0314 is 1 µs (= 0.5 µs - (-0.5 µs))
over the operating temperature
range of –40°C to 100°C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal
temperatures and test conditions
since the optocouplers under
consideration are typically
mounted in close proximity to
each other and are switching
identical IGBTs.
ILED1
VOUT1
Q1 ON
Q1 OFF
Q2 ON
VOUT2
ILED2
Q2 OFF
tPHL MAX
tPLH MIN
PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 26. Minimum LED skew for zero dead time.
ILED1
VOUT1
Q1 ON
Q1 OFF
Q2 ON
VOUT2
Q2 OFF
ILED2
tPHL MIN
tPHL MAX
tPLH
MIN
tPLH MAX
(tPHL-tPLH) MAX
PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN)
= (tPHL MAX - tPLH MIN) – (tPHL MIN - tPLH MAX)
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 27. Waveforms for dead time.
15
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0366EN
AV02-0162EN April 26, 2007