AVAGO HCPL-6531 Hermetically sealed, tansistor output optocouplers for analog and digital application Datasheet

4N55*, 5962-87679, HCPL-553X, HCPL-653X,
HCPL-257K, HCPL-655X, 5962-90854, HCPL-550X
Hermetically Sealed, Transistor Output Optocouplers
for Analog and Digital Applications
Data Sheet
*See matrix for available extensions.
Description
Features
These units are single, dual and quad channel, hermetically
sealed optocouplers. The products are capable of operation
and storage over the full military temperature range and
can be purchased as either standard product or with full
MIL-PRF-38534 Class Level H or K testing or from the appropriate DLA Drawing. All devices are manufactured and
tested on a MIL-PRF-38534 certified line and are included
in the DLA Qualified Manufacturers List QML-38534 for
Hybrid Microcircuits.
 Dual Marked with Device Part Number and DLA
Applications
 High Speed: Typically 400 kBit/s
 Military and Space
 9 MHz Bandwidth
 High Reliability Systems
 Open Collector Output
 Vehicle Command, Control, Life Critical Systems
 2-18 Volt VCC Range
 Line Receivers
 1500 Vdc Withstand Test Voltage
 Switching Power Supply
 High Radiation Immunity
 Voltage Level Shifting
 6N135, 6N136, HCPL-2530/2531,
 Analog Signal Ground Isolation
(see Figures 7, 8, and 13)
 Isolated Input Line Receiver
Drawing Number
 Manufactured and Tested on a MIL-PRF-38534 Certified
Line
 QML-38534, Class H and K
 Five Hermetically Sealed Package Configurations
 Performance Guaranteed over Full Military
Temperature Range: -55°C to +125°C
Function Compatibility
 Reliability Data
 Isolated Output Line Driver
 Logic Ground Isolation
 Harsh Industrial Environments
 Isolation for Test Equipment Systems
The connection of a 0.1 μF bypass capacitor between VCC and GND is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Each channel contains a GaAsP light emitting diode which
is optically coupled to an integrated photon detector.
Separate connections for the photodiodes and output
transistor collectors improve the speed up to a hundred
times that of a conventional phototransistor optocoupler
by reducing the base-collector capacitance.
Truth Table
These devices are suitable for wide bandwidth analog
applications, as well as for interfacing TTL to LSTTL or
CMOS. Current Transfer Ratio (CTR) is 9% minimum at IF
= 16 mA. The 18 V VCC capability will enable the designer
to interface any TTL family to CMOS. The availability of
the base lead allows optimized gain/ bandwidth adjustment in analog applications. The shallow depth of the
IC photodiode provides better radiation immunity than
conventional phototransistor couplers.
These products are also available with the transistor base
node not connected to improve common mode noise
immunity and ESD susceptibility. In addition, higher CTR
minimums are available by special request.
Package styles for these parts are 8 and 16 pin DIP through
hole (case outlines P and E respectively), 16 pin DIP flat
pack (case outline F), and leadless ceramic chip carrier
(case outline 2). Devices may be purchased with a variety
of lead bend and plating options, see Selection Guide Table
for details. Standard Microcircuit Drawing (SMD) parts are
available for each package and lead style.
Because the same functional die (emitters and detectors)
are used for each channel of each device listed in this
data sheet, absolute maximum ratings, recommended
operating conditions, electrical specifications, and performance characteristics shown in the figures are identical
for all parts. Occasional exceptions exist due to package
variations and limitations and are as noted. Additionally,
the same package assembly processes and materials are
used in all devices. These similarities give justification for
the use of data obtained from one part to represent other
part’s performance for die related reliability and certain
limited radiation test results.
2
(Positive Logic)
Input
Output
On (H)
L
Off (L)
H
Functional Diagram
Multiple Channel Devices Available
V CC
VB
VO
GND
Selection Guide–Package Styles and Lead Configuration Options
Package
16 Pin DIP
8 Pin DIP
8 Pin DIP
16 Pin Flat Pack
20 Pad LCCC
Lead Style
Through Hole
Through Hole
Through Hole
Unformed Leads Surface Mount
Channels
2
1
2
4
2
Common Channel Wiring
None
None
VCC GND
VCC GND
None
Commercial
4N55(1)
HCPL-5500
HCPL-5530
HCPL-6550
HCPL-6530
MIL-PRF-38534 Class H
4N55/883B
HCPL-5501
HCPL-5531
HCPL-6551
HCPL-6531
MIL-PRF-38534 Class K
HCPL-257K
HCPL-550K
HCPL-553K
HCPL-655K
HCPL-653K
Standard Lead Finish
Gold Plate
Gold Plate
Gold Plate
Gold Plate
Solder Pads *
Solder Dipped *
Option 200
Option 200
Option 200
Butt Joint/Gold Plate
Option 100
Option 100
Option 100
Gull Wing/Soldered*
Option 300
Option 300
Option 300
Prescript for all below
5962-
5962-
5962-
5962-
5962-
Gold Plate
8767901EC
9085401HPC
8767902PC
8767904FC
Solder Dipped*
8767901EA
9085401HPA
8767902PA
Butt Joint/Gold Plate
8767901UC
9085401HYC
8767902YC
Butt Joint/Soldered*
8767901UA
9085401HYA
8767902YA
Gull Wing/Soldered*
8767901TA
9085401HXA
8767902XA
Prescript for all below
5962-
5962-
5962-
5962-
Gold Plate
8767905KEC
9085401KPC
8767906KPC
8767908KFC
Solder Dipped *
8767905KEA
9085401KPA
8767906KPA
Butt Joint/Gold Plate
8767905KUC
9085401KYC
8767906KYC
Butt Joint/Soldered*
8767905KUA
9085401KYA
8767906KYA
Gull Wing/Soldered*
8767905KTA
9085401KXA
8767906KXA
Avago Part No. and Options
Class H SMD Part #
87679032A
Class K SMD Part #
1. JEDEC registered part.
* Solder contains lead
3
5962-
8767907K2A
8 Pin Ceramic DIP Single Channel Schematic
2
ANODE
IF
8
IB
7
IO
6
V CC
+
VB
VF
CATHODE
ICC
-
VO
3
5
GND
Note, base is pin 7.
Functional Diagrams
16 Pin DIP
Through Hole
2 Channels
8 Pin DIP
Through Hole
1 Channel
8 Pin DIP
Through Hole
2 Channels
16 Pin Flat Pack
Unformed Leads
4 Channels
20 Pad LCCC
Surface Mount
2 Channels
15 14
1
V B1
16
2
V CC1
V CC
1
V CC
VB
V O1
14
GND
13
V OUT
4
GND
7
6
5
V O1
2
V O2
3
4
GND
V CC2
8
V CC
2
3
4
8
15
2
3
16
1
1
15
V O2
20
7
3
V O1
14
4
V O2
13
5
V O3
12
6
GND 2
2
5
V B2
19
V O1
V CC1
3
V B1
13
12
10
9
GND 1
5
V B2
12
6
V CC2
11
6
V O4
11
7
GND
10
7
GND
10
8
V O2
9
8
7
8
9
Note: 8 pin DIP and flat pack devices have common VCC and ground. 16 pin DIP and LCCC (leadless ceramic chip carrier) packages have isolated
channels with separate VCC and ground connections.
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
0.89 (0.035)
1.65 (0.065)
4.45 (0.175)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
4
0.20 (0.008)
0.33 (0.013)
Leaded Device Marking
Avago DESIGNATOR
Avago P/N
DLA SMD*
DLA SMD*
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
Leadless Device Marking
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
Avago CAGE CODE*
Avago DESIGNATOR
Avago P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
A QYYWWZ
XXXXXX
XXXX
XXXXXX
XXX 50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DLA SMD*
DLA SMD*
Avago CAGE CODE*
* QUALIFIED PARTS ONLY
* QUALIFIED PARTS ONLY
Outline Drawings
16 Pin Flat Pack, 4 Channels
7.24 (0.285)
6.99 (0.275)
2.29 (0.090)
MAX.
1.27 (0.050)
REF.
11.13 (0.438)
10.72 (0.422)
0.46 (0.018)
0.36 (0.014)
8.13 (0.320)
MAX.
2.85 (0.112)
MAX.
0.88 (0.0345)
MIN.
0.89 (0.035)
0.69 (0.027)
5.23
(0.206)
MAX.
0.31 (0.012)
0.23 (0.009)
9.02 (0.355)
8.76 (0.345)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
20 Terminal LCCC Surface Mount, 2 Channels
8 Pin DIP Through Hole, 1 and 2 Channel
8.70 (0.342)
9.10 (0.358)
9.40 (0.370)
9.91 (0.390)
0.76 (0.030)
1.27 (0.050)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
2.03 (0.080)
1.02 (0.040) (3 PLCS)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
0.64
(0.025)
(20 PLCS)
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
METALIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
8.13 (0.320)
MAX.
3.81 (0.150)
MIN.
0.51 (0.020)
1.52 (0.060)
2.03 (0.080)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
5
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
Hermetic Optocoupler Options
Option
Description
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for
details).
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
100
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
Lead finish is solder dipped rather than gold plated. This option is available on commercial and
hi-rel product in 8 and 16 pin DIP. DLA drawing part numbers contain provisions for lead finish.
All leadless chip carrier devices are delivered with solder dipped terminals as a standard feature.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This
option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for
details). This option has solder dipped leads.
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
1.40 (0.055)
1.65 (0.065)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
300
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
1.40 (0.055)
1.65 (0.065)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: Solder contains lead.
6
4.57 (0.180)
MAX.
5° MAX.
0.20 (0.008)
0.33 (0.013)
9.65 (0.380)
9.91 (0.390)
1.07 (0.042)
1.32 (0.052)
Absolute Maximum Ratings
No derating required up to +125° C.
Parameter
Symbol
Min.
Max.
Units
Storage Temperature Range
TS
-65°
+150°
C
Operating Ambient Temperature
TA
-55°
+125°
C
Junction Temperature
TJ
+175°
C
Case Temperature
TC
+170°
C
260° for 10 s
C
Lead Solder Temperature (1.6 mm below seating plane)
Average Input Forward Current
IF AVG
20
mA
Peak Forward Input Current
(each channel,  1 ms duration)
IFPK
40
mA
Reverse Input Voltage
BVR
See Electrical Characteristics
Average Output Current, each channel
IO
8
mA
Peak Output Current, each channel
IO
16
mA
Supply Voltage
VCC
-0.5
20
V
Output Voltage
VO
-0.5
20
V
Input Power Dissipation, each channel
36
mW
Output Power Dissipation, each channel
50
mW
200
mW
Max.
Units
Package Power Dissipation, each channel
PD
Single Channel 8 Pin, Dual Channel 16 Pin, and LCCC Only
Parameter
Symbol
Min.
Emitter Base Reverse Voltage
VEBO
3
V
Base Current, each channel
IB
5
mA
ESD Classification
(MIL-STD-883, Method 3015)

4N55, 4N55/883B, HCPL-257K, HCPL-5500/01/0K, and HCPL-6530/31/3K
( ), Class 1
HCPL-5530/31/3K, HCPL-6550/51/5K
(Dot), Class 3
Recommended Operating Conditions
7
Parameter
Symbol
Input Current, Low Level
IFL
Input Current, High Level
IFH
Supply Voltage, Output
VCC
Min.
Max.
Units
250
μA
12
20
mA
2
18
V
Electrical Characteristics
TA = -55° C to +125° C, unless otherwise specified. See Note 12.
Parameter
Symbol
Group A,
Subgroup
Current Transfer Ratio
CTR
1, 2, 3
VO = 0.4V, IF = 16 mA,
VCC = 4.5V
Logic High Output
Current
IOH
1, 2, 3
IF = 0,
IF (other channels) =
20 mA
VO = VCC = 18 V
5
Output Leakage Current IOLeak
1, 2, 3
IF = 250 A,
IF (other channels) =
20 mA,
VO = VCC = 18 V
30
Input-Output Insulation
Leakage Current
II-O
1
VI-O = 1500 Vdc,
RH ≤ 65%,
TA = 25°C, t = 5 s
Input Forward Voltage
VF
1, 2, 3
IF = 20 mA
Limits
Test Conditions
Min.
Typ.*
9
20
1.55
Max.
Units
Fig.
Notes
%
2, 3
1, 2, 10
100
A
4
1
250
A
4
1
1.0
A
1.8
V
3, 9
1
1.9
Reverse Breakdown
Voltage
BVR
Logic High
Supply
Current
ICCH
Logic Low
Supply
Current
Single
Channel
1, 2, 3
5
1, 13
V
1, 14
3
1, 13
A
VCC = 18 V, IF = 0 mA
0.1
10
Dual
Channel
VCC = 18 V, IF = 0 mA
(all channels)
0.2
20
1,4
Quad
Channel
VCC = 18 V, IF = 0 mA
(all channels)
0.4
40
1
VCC = 18 V, IF = 20 mA
35
200
Dual
Channel
VCC = 18 V, IF1 = IF2 =
20 mA
70
400
1, 4
Quad
Channel
VCC = 18 V, IF1 = IF2 =
IF3 = IF4 = 20 mA
140
800
1
RL = 8.2 k,
CL = 50 pF,
IF = 16 mA,
VCC = 5 V
1.0
6.0
0.4
2.0
Single
Channel
ICCL
Propagation Delay
Time to Logic High at
Output
tPLH
Propagation Delay
Time to Logic Low at
Output
tPHL
1, 2, 3
1, 2, 3
*All typical values are at VCC = 5 V, TA = 25°C.
8
IR = 10 A
1, 14
9, 10, 11
1
A
s
1
6, 9
1, 6
Typical Characteristics
All typical values are at TA = 25°C, VCC = 5 V, unless otherwise specified.
Parameter
Symbol
Test Conditions
Typ.
Units
Fig.
Notes
Input Capacitance
CIN
VF = 0 V, f = 1 MHz
60
pF
1
Input Diode Temperature
Coefficient
VF/TA
IF = 20 mA
-1.5
mV/°C
1
Resistance (Input-Output)
RI-O
VI-O = 500 V
1012

3
Capacitance (Input-Output)
CI-O
f = 1 MHz
1.0
pF
1, 11
Transistor DC Current Gain
hFE
VO = 5 V, IO = 3 mA
250
-
1
Small Signal Current Transfer Ratio
IO/IF
VCC = 5 V, VO = 2 V
21
%
7
1
Common Mode Transient Immunity
at Logic High Level Output
|CMH|
IF = 0 mA, RL = 8.2 k,
VO (min) = 2.0 V,
VCM = 10 VP-P
1000
V/s
10
1, 7
Common Mode Transient Immunity
at Logic Low Level Output
|CML|
IF = 16 mA, RL = 8.2 k,
VO (max) = 0.8 V,
VCM = 10 VP-P
-1000
V/s
10
1, 7
Bandwidth
BW
9
MHz
8
8
Multi-Channel Product Only
Parameter
Symbol
Test Conditions
Typ.
Units
Notes
Input-Input Insulation Leakage
Current
II-I
RH ≤ 65%, VI-I = 500 V, t = 5 s
1
pA
5, 9
Resistance (Input-Input)
RI-I
VI-I = 500 V
1012

5
Capacitance (Input-Input)
CI-I
f=1 MHz
0.8
pF
5
Notes:
1. Each channel of a multi-channel device.
2. Current Transfer Ratio is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100%. CTR is known to
degrade slightly over the unit’s lifetime as a function of input current, temperature, signal duty cycle, and system on time. Refer to Application
Note 1002 for more detail. ln short, it is recommended that designers allow at least 20-25% guardband for CTR degradation.
3. All devices are considered two-terminal devices; measured between all input leads or terminals shorted together and all output leads or terminals
shorted together.
4. The 4N55, 4N55/883B, HCPL-257K, HCPL-6530, HCPL-6531, and HCPL-653K dual channel parts function as two independent single channel units.
Use the single channel parameter limits. IF = 0 mA for channel under test and IF = 20 mA for other channels.
5. Measured between adjacent input pairs shorted together for each multichannel device.
6. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading edge of the
output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point on the trailing edge of the output pulse.
7. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO < 0.8 V).
CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (VO > 2.0
V).
8. Bandwidth is the frequency at which the ac output voltage is 3 dB below the low frequency asymptote. For the HCPL-5530 the typical bandwidth
is 2 MHz.
9. This is a momentary withstand test, not an operating condition.
10. Higher CTR minimums are available to support special applications.
11. Measured between each input pair shorted together and all output connections for that channel shorted together.
12. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and -55°C (Subgroups 1
and 9, 2 and 10, 3 and 11, respectively).
13. Not required for 4N55, 4N55/883B, HCPL-257K, 5962-8767901, and 5962-8767905 types.
14. Required for 4N55, 4N55/883B, HCPL-257K, 5962-8767901, and 5962-8767905 types only.
9
IOH - LOGIC HIGH OUTPUT CURRENT - μA
Figure 1. Input Diode Forward Current vs. Forward Voltage.
Figure 2. DC and Pulsed Transfer Characteristic.
Figure 3. Normalized Current Transfer Ratio vs.
Input Diode Forward Current.
Figure 5. Logic Low Supply Current vs. Input
Diode Forward Current.
Figure 6. Propagation Delay vs. Temperature.
100
IF = 250 μA,
IF (OTHER CHANNELS) = 20 mA
10
1
IF = 0 μA,
IF (OTHER CHANNELS) = 20 mA
IF = IF (OTHER CHANNELS)
= 0 mA
0.1
VCC = VO = 18 V
0.01
0.001
-60 -40 -20 0
20 40 60 80 100 120 140
TA - TEMPERATURE - ˚C
Figure 4. Logic High Output Current vs. Temperature.
Figure 7. Normalized Small Signal Current Transfer Ratio vs. Quiescent Input Current.
10
+12 V
D.U.T.
+12 V
0.1 μF
0.1 μF
V CC
2.1 k Ω
Q1
VB
100 Ω
51 Ω
9.1 k Ω
VO
47 μF
V IN
1.2 k Ω
15 k Ω
RF
1kΩ
Q3
0.01 μF
Q2
100 Ω
0.01 μF
VO
(1 M Ω, 12 pF
TEST INPUT)
470
Ω
GND
22 Ω
SINGLE CHANNEL TESTING,
INDEPENDENT VCC DEVICES
1N4150
TRIM FOR UNITY GAIN
Q 1 , Q 2 , Q 3 : 2N3904
TYPICAL LINEARITY = +3 % AT V IN = 1 V P-P
TYPICAL SNR = 50 dB
TYPICAL R F = 375 Ω
TYPICAL V O dc = 3.8 V
TYPICAL IF = 9 mA
D.U.T.
20 k Ω
SET I F
0.1 μF
560 Ω
100 Ω
VO
2N3053
1.6 Vdc
0.25 V P-P ac
AC INPUT
100 Ω
+15
+15 V
V CC
GND
COMMON
V CC DEVICES
NORMALIZED RESPONSE - dB
+5 V
+10
PULSE GEN.
Z O = 50 Ω
t r = 5 ns
IF
D.U.T.
+5 V
V CC
RL
VO
IF MONITOR
100 Ω
C L * = 50 pF
GND
SINGLE CHANNEL
OR COMMON V CC DEVICES
10 % DUTY CYCLE
1/f < 100 μs
NOTES:
* C L INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
BASE LEAD NOT CONNECTED.
Figure 9. Switching Test Circuit.*
*JEDEC Registered Data.
11
INDEPENDENT
V CC DEVICES
+5
0
-5
-10
COMMON V CC
DEVICES
-15
-20
0.1
Figure 8. Frequency Response.
T A = 25 ˚C
1.0
10
f - FREQUENCY - MHz
100
IF
B
D.U.T.
+5 V
V CC
RM
RL
A
VO
V FF
GND
SINGLE CHANNEL OR
COMMON V CC DEVICES
V CM
+
PULSE GEN.
NOTE: BASE LEAD NOT CONNECTED.
Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.
V CC
5V
220 Ω
RL
D.U.T.
V CC
0.01 μF
GND
Device No.
54LS14
CD40106BM
5V
5V
15 V
18 k *
8.2 k
22 k
*The equivalent output load resistance is affected by the LSTTL input
current and is approximately 8.2 kΩ. This is a worst case design
which takes into account 25% degradation of CTR. See App. Note
1002 to assess actual degradation and lifetime.
EACH CHANNEL
Figure 11. Recommended Logic Interface.
V CC
VOC
D.U.T.*
VCC
(EACH INPUT)
0.1 μF
VO
V IN
GND
(EACH OUTPUT)
NOMINAL CONDITIONS
PER CHANNEL: IF = 20 mA
IO = 4 mA
ICC = 30 μA
NOTE: BASE LEAD NOT CONNECTED.
T A = +125 ˚C
Figure 12. Operating Circuit for Burn-In and Steady State Life Tests. All
Channels Tested Simultaneously.
12
CMOS
RL 5% Tolerance
LOGIC GATE
-
LSTTL
VCC
TTL
+
Logic Family
U1
+
+
R3
2
HCPL-5530
IF 1
V IN
1
8
2
7
3
6
OFFSET ADJUST
5kΩ
220 Ω
IC
1
IC
2
U3
+
IF 2
2
U2
+
-
4
R1
2.7 k Ω
R2
2.7 k Ω
R 4 1 kΩ
5 k Ω GAIN ADJUST
5
-15 V
U4
+
U 1 , U 2 , U 3 , U 4 , LM307
IC
IC
1
2
=K1
IF
IF
=K2
IF
IF
50 k Ω
V OUT
2
n1
1
R5
I CC
6 mA
´
1
n2
2
-15 V
´
2
Figure 13. Isolation Amplifier Application Circuit.
Description
MIL-PRF-38534 Class H, Class K, and DLA SMD Test Program
The schematic uses a dualchannel, high-speed optocoupler (HCPL-5530) to function as a servo type dc isolation
amplifier. This circuit operates on the principle that two
optocouplers will track each other if their gain changes
by the same amount over a specific operating region.
Avago Technologies’s Hi-Rel Optocouplers are in compliance with MIL-PRF-38534 Classes H and K. Class H and Class
K devices are also in compliance with DLA drawings 596287679, and 5962-90854. Testing consists of 100% screening
and quality conformance inspection to MIL-PRF-38534.
Performance of Circuit
 1% linearity for 10 V peak-to-peak dynamic range
 Gain drift: -0.03%/°C
 Offset Drift: ± 1 mV/°C
 25 kHz bandwidth (limited by Op-Amps U1, U2)
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies Limited. All rights reserved. Obsoletes 5989-1659EN
AV02-3846EN - October 2, 2012
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