HP HCPL0454 High cmr, high speed optocoupler Datasheet

H
High CMR, High Speed
Optocouplers
Technical Data
HCPL-4504
HCPL-0454
HCNW4504
Features
Applications
Description
• Short Propagation Delays
for TTL and IPM
Applications
• 15 kV/µs Minimum Common
Mode Transient Immunity at
VCM = 1500 V for TTL/Load
Drive
• High CTR at TA = 25°C
>25% for HCPL-4504/0454
>23% for HCNW4504
• Electrical Specifications for
Common IPM Applications
• TTL Compatible
• Guaranteed Performance
from 0°C to 70°C
• Open Collector Output
• Safety Approval
UL Recognized - 2500 V rms
for 1 minute (5000 V rms for
1 minute for
HCPL-4504#020 and
HCNW4504)per UL1577
CSA Approved
VDE 0884 Approved
-VIORM = 630 V peak for
HCPL-4504#060
-VIORM = 1414 V peak for
HCNW4504
BSI Certified (HCNW4504)
• Available in 8-Pin DIP, SO-8,
Widebody Packages
• Inverter Circuits and
Intelligent Power Module
(IPM) interfacing High Common Mode Transient
Immunity (> 10 kV/µs for an
IPM load/drive) and (tPLH - tPHL)
Specified (See Power Inverter
Dead Time section)
• Line Receivers Short Propagation Delays and
Low Input-Output Capacitance
• High Speed Logic Ground
Isolation - TTL/TTL, TTL/
CMOS, TTL/LSTTL
• Replaces Pulse
Transformers Save Board Space and Weight
• Analog Signal Ground
Isolation Integrated Photodetector
Provides Improved Linearity
over Phototransistors
These optocouplers are similar to
HP’s other high speed transistor
optocouplers but with shorter
propagation delays and higher
CTR. The HCPL-4504/0454 and
HCNW4504 also have a guaranteed propagation delay difference
(tPLH - tPHL). These features make
these optocouplers an excellent
solution to IPM inverter dead time
and other switching problems.
Functional Diagram
NC 1
8 VCC
ANODE 2
7 NC
CATHODE 3
6 VO
NC 4
TRUTH TABLE
LED
VO
ON
LOW
OFF
HIGH
5 GND
A 0.1 µF bypass capacitor between pins 5 and 8 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
5965-3604E
1-33
The HCPL-4504/0454 and
HCNW4504 CTR, propagation
delay, and CMR are specified for
both TTL and IPM load/drive
conditions. Specifications and
typical performance plots for both
TTL and IPM conditions are
provided for ease of application.
These single channel, diodetransistor optocouplers are
available in 8-Pin DIP, SO-8, and
Widebody package configurations. An insulating layer between
a LED and an integrated
photodetector provide electrical
insulation between input and
output. Separate connections for
the photodiode bias and outputtransistor collector increase the
speed up to a hundred times that
of a conventional phototransistor
coupler by reducing the base
collector capacitance.
Selection Guide
Single Channel Packages
8-Pin DIP
(300 Mil)
Small Outline
SO-8
Widebody
(400 Mil)
HCPL-4504
HCPL-0454
HCNW4504
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-4504#XXX
020 = UL 5000 V rms/1 Minute Option*
060 = VDE 0884 VIORM = 630 V peak Option*
300 = Gull Wing Surface Mount Option†
500 = Tape and Reel Packaging Option
Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for
information.
*For HCPL-4504 only. Combination of Option 020 and Option 060 is not available.
†Gull wing surface mount option applies to through hole parts only.
Schematic
ICC
8
VCC
IF
+
ANODE
2
VF
CATHODE
–
IO
6
VO
3
SHIELD
1-34
5
GND
Package Outline Drawings
8-Pin DIP Package (HCPL-4504)
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
TYPE NUMBER
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
OPTION CODE*
DATE CODE
HP XXXXZ
YYWW RU
1
2
3
4
UL
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
5° TYP.
4.70 (0.185) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
0.51 (0.020) MIN.
2.92 (0.115) MIN.
0.65 (0.025) MAX.
1.080 ± 0.320
(0.043 ± 0.013)
2.54 ± 0.25
(0.100 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS.
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
8-Pin DIP Package with Gull Wing Surface Mount Option 300 (HCPL-4504)
PAD LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
1.016 (0.040)
1.194 (0.047)
5
4.826 TYP.
(0.190)
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
9.398 (0.370)
9.906 (0.390)
4
1.194 (0.047)
1.778 (0.070)
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
4.19 MAX.
(0.165)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.381 (0.015)
0.635 (0.025)
0.635 ± 0.25
(0.025 ± 0.010)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12° NOM.
1-35
Small Outline SO-8 Package (HCPL-0454)
8
7
6
5
5.842 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
1
2
3
4
0.381 ± 0.076
(0.016 ± 0.003)
1.270 BSG
(0.050)
7°
5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
45° X
0.432
(0.017)
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.152 ± 0.051
(0.006 ± 0.002)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.305 MIN.
(0.012)
8-Pin Widebody DIP Package (HCNW4504)
11.00 MAX.
(0.433)
11.15 ± 0.15
(0.442 ± 0.006)
8
7
6
9.00 ± 0.15
(0.354 ± 0.006)
5
TYPE NUMBER
HP
HCNWXXXX
DATE CODE
YYWW
1
2
3
4
10.16 (0.400)
TYP.
1.55
(0.061)
MAX.
7° TYP.
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
5.10 MAX.
(0.201)
3.10 (0.122)
3.90 (0.154)
0.51 (0.021) MIN.
2.54 (0.100)
TYP.
1.78 ± 0.15
(0.070 ± 0.006)
1-36
0.40 (0.016)
0.56 (0.022)
DIMENSIONS IN MILLIMETERS (INCHES).
8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300 (HCNW4504)
11.15 ± 0.15
(0.442 ± 0.006)
6
7
8
PAD LOCATION (FOR REFERENCE ONLY)
5
6.15
(0.242)TYP.
9.00 ± 0.15
(0.354 ± 0.006)
12.30 ± 0.30
(0.484 ± 0.012)
1
3
2
4
1.3
(0.051)
0.9
(0.035)
12.30 ± 0.30
(0.484 ± 0.012)
1.55
(0.061)
MAX.
11.00 MAX.
(0.433)
4.00 MAX.
(0.158)
1.78 ± 0.15
(0.070 ± 0.006)
1.00 ± 0.15
(0.039 ± 0.006)
0.75 ± 0.25
(0.030 ± 0.010)
2.54
(0.100)
BSC
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
DIMENSIONS IN MILLIMETERS (INCHES).
7° NOM.
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
TEMPERATURE – °C
Solder Reflow Temperature Profile
(HCPL-0454 and Gull Wing Surface Mount Option Parts)
260
240
220
200
180
160
140
120
100
80
60
40
20
0
∆T = 145°C, 1°C/SEC
∆T = 115°C, 0.3°C/SEC
∆T = 100°C, 1.5°C/SEC
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
Note: Use of nonchlorine activated fluxes is highly recommended.
1-37
Regulatory Information
The devices contained in this data
sheet have been approved by the
following organizations:
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
UL
Recognized under UL 1577,
Component Recognition
Program, File E55361.
VDE
Approved according to VDE
0884/06.92 (HCNW4504 and
HCPL-4504#060 only).
BSI
Certification according to
BS451:1994,
(BS EN60065:1994);
BS EN60950:1992
(BS7002:1992) and
EN41003:1993 for Class II
applications (HCNW4504 only).
Insulation and Safety Related Specifications
Symbol
8-Pin DIP
(300 Mil)
Value
SO-8
Value
Minimum External
Air Gap (External
Clearance)
L(101)
7.1
4.9
9.6
mm
Measured from input terminals
to output terminals, shortest
distance through air.
Minimum External
Tracking (External
Creepage)
L(102)
7.4
4.8
10.0
mm
Measured from input terminals
to output terminals, shortest
distance path along body.
0.08
0.08
1.0
mm
Through insulation distance,
conductor to conductor, usually
the direct distance between the
photoemitter and photodetector
inside the optocoupler cavity.
NA
NA
4.0
mm
Measured from input terminals
to output terminals, along
internal cavity.
200
200
200
Volts
DIN IEC 112/VDE 0303 Part 1
IIIa
IIIa
IIIa
Parameter
Minimum Internal
Plastic Gap
(Internal Clearance)
Minimum Internal
Tracking (Internal
Creepage)
Tracking Resistance
(Comparative
Tracking Index)
Isolation Group
CTI
Widebody
(400 Mil)
Value
Units
Conditions
Material Group
(DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
1-38
VDE 0884 Insulation Related Characteristics
(HCPL-4504 OPTION 060 ONLY)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 450 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test,
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 15, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
Symbol
Characteristic
Units
VIORM
I-IV
I-III
55/100/21
2
630
V peak
VPR
1181
V peak
VPR
945
V peak
VIOTM
6000
V peak
TS
IS,INPUT
PS,OUTPUT
RS
175
230
600
≥ 109
°C
mA
mW
Ω
VDE 0884 Insulation Related Characteristics (HCNW4504 ONLY)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 600 V rms
for rated mains voltage ≤ 1000 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test,
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 15, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
Symbol
Characteristic
Units
VIORM
I-IV
I-III
55/85/21
2
1414
V
peak
VPR
2652
V
peak
VPR
2121
V
peak
VIOTM
8000
V
peak
TS
IS,INPUT
PS,OUTPUT
RS
150
400
700
≥ 109
°C
mA
mW
Ω
*Refer to the front of the optocoupler section of the current catalog under Product Safety Regulations section (VDE 0884), for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
1-39
Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Average Forward Input Current
Peak Forward Input Current
(50% duty cycle, 1 ms pulse width)
(50% duty cycle, 1 ms pulse width)
Peak Transient Input Current
(≤ 1 µs pulse width, 300 pps)
Symbol
TS
TA
IF(AVG)
IF(PEAK)
IF(TRANS)
Reverse LED Input Voltage (Pin 3-2)
VR
Input Power Dissipation
PIN
Average Output Current (Pin 6)
Peak Output Current
Supply Voltage (Pin 8-5)
Output Voltage (Pin 6-5)
Output Power Dissipation
Lead Solder Temperature
(Through-Hole Parts Only)
1.6 mm below seating plane,
10 seconds up to seating plane, 10 seconds
Reflow Temperature Profile
1-40
Device
Min.
-55
HCPL-4504 -55
HCPL-0454
HCNW4504 -55
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
IO(AVG)
IO(PEAK)
VCC
VO
PO
TLS
TRP
Units
°C
°C
Note
85
25
mA
1
mA
2
50
40
1
-0.5
-0.5
HCPL-4504
HCNW4504
HCPL-0454
and
Option 300
Max.
125
100
A
0.1
5
V
3
45
mW
3
40
8
16
30
20
100
mA
mA
V
V
mW
4
260
°C
260
°C
See Package Outline
Drawings section
Electrical Specifications (DC)
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified. See note 12.
Parameter
Current
Transfer Ratio
Current
Transfer Ratio
Logic Low
Output Voltage
Symbol
CTR
CTR
VOL
Device
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
Min.
25
21
23
19
26
22
25
21
HCPL-4504
HCPL-0454
HCNW4504
Typ.*
32
34
29
31
35
37
33
35
0.2
0.2
Logic High
Output Current
IOH
0.003
0.01
Logic Low
Supply Current
Logic High
Supply Current
Input Forward
Voltage
ICCL
50
ICCH
0.02
Input Reverse
Breakdown
Voltage
Temperature
Coefficient of
Forward Voltage
Input
Capacitance
VF
BVR
∆VF
∆TA
CIN
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
1.5
1.45
1.35
5
1.59
Max.
60
60
63
65
65
68
0.4
0.5
0.4
0.5
0.5
1
50
200
1
2
1.7
1.8
1.85
1.95
Units
Test Conditions
%
TA = 25°C VO = 0.4 V
IF = 16 mA,
VO = 0.5 V
VCC = 4.5 V
TA = 25°C VO = 0.4 V
VO = 0.5 V
%
TA = 25°C VO = 0.4 V
IF = 12 mA,
VO = 0.5 V
VCC = 4.5 V
TA = 25°C VO = 0.4 V
VO = 0.5 V
V
TA = 25°C IO = 4.0 mA
IF = 16 mA,
VCC = 4.5 V
IO = 3.3 mA
TA = 25°C IO = 3.6 mA
IO = 3.0 mA
µA
TA = 25°C VO = VCC = 5.5 V IF = 0 mA
TA = 25°C VO = VCC = 15 V
-1.6
-1.4
60
Note
5
1, 2,
4
5
5
µA
IF = 16 mA, VO = Open, VCC = 15 V
12
µA
TA = 25°C IF = 0 mA, VO = Open,
VCC = 15 V
TA = 25°C IF = 16 mA
12
V
3
TA = 25°C IF = 16 mA
V
3
Fig.
1, 2,
4
IR = 10 µA
IR = 100 µA, TA = 25°C
mV/°C IF = 16 mA
pF
f = 1 MHz, VF = 0 V
70
*All typicals at TA = 25°C.
1-41
AC Switching Specifications
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified.
Parameter
Propagation
Delay Time
to Logic Low
at Output
Propagation
Delay Time
to Logic
High at
Output
Propagation
Delay
Difference
Between
Any 2 Parts
Common
Mode
Transient
Immunity at
Logic High
Level Output
Common
Mode
Transient
Immunity at
Logic Low
Level Output
Symbol
Min. Typ.
0.2
0.3
µs
tPHL
0.2
0.5
0.2
0.5
0.7
0.1
0.5
1.0
0.3
0.5
0.3
0.7
0.3
0.8
1.1
0.2
0.8
1.4
-0.4
0.3
0.9
-0.7
0.3
15
30
|CMH|
TA = 25°C
1.3
kV/µs
15
TA = 25°C
TA = 25°C
µs
tPLH-tPHL
TA = 25°C
TA = 25°C
µs
tPLH
15
30
30
|CML|
kV/µs
10
*All typicals at TA = 25°C.
Fig.
Note
Pulse: f = 20 kHz,
Duty Cycle = 10%,
IF = 16 mA, VCC = 5.0 V,
RL = 1.9 kΩ, CL = 15 pF,
VTHHL = 1.5 V
6,
8, 9
9
Pulse: f = 10 kHz,
Duty Cycle = 50%,
IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
VTHHL = 1.5 V
6,
10-14
10
Pulse: f = 20 kHz,
Duty Cycle = 10%,
IF = 16 mA, VCC = 5.0 V,
RL = 1.9 kΩ, CL = 15 pF,
VTHLH = 1.5 V
6,
8, 9
9
Pulse: f = 10 kHz,
Duty Cycle = 50%,
IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
VTHLH = 2.0 V
6,
10-14
10
Pulse: f = 10 kHz,
6,
Duty Cycle = 50%,
10-14
IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
VTHHL = 1.5 V, VTHLH = 2.0 V
15
VCC = 5.0 V, RL = 1.9 kΩ,
CL = 15 pF, IF = 0 mA
7
7, 9
VCC = 15.0 V, RL = 20 kΩ,
CL = 100 pF, IF = 0 mA
7
8, 10
VCC = 5.0 V, RL = 1.9 kΩ,
CL = 15 pF, IF = 16 mA
7
7, 9
VCC = 15.0 V, RL = 20 kΩ,
CL = 100 pF, IF = 12 mA
7
8, 10
TA = 25°C
30
VCM =
1500 VP-P
30
Test Conditions
TA = 25°C
VCM =
1500 VP-P
15
1-42
Max. Units
VCC = 15.0 V, RL = 20 kΩ,
CL = 100 pF, IF = 16 mA
7
7
8, 10
8, 10
Package Characteristics
Over recommended temperature (TA = 0°C to 25°C) unless otherwise specified.
Parameter
Input-Output
Momentary
Withstand
Voltage†
Sym.
VISO
Input-Output
Resistance
RI-O
Input-Output
Capacitance
CI-O
Device
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
(Option 020)
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
Min.
2500
Typ.*
Max.
Units
V rms
5000
Test Conditions
RH ≤ 50%,
t = 1 min.,
TA = 25°C
5000
1012
1012
1011
Ω
VI-O = 500 Vdc
pF
TA = 25°C
TA = 100°C
f = 1 MHz
1013
0.6
0.5
Fig.
Note
6, 13
6, 14
6, 11,
14
6
6
0.6
*All typicals at TA = 25°C..
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if
applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance
Voltage.”
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 0.5 mA/°C (SO-8).
2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.0 mA/°C (SO-8).
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.1 mW/°C (SO-8).
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 2.3 mW/°C (SO-8).
5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current, IO, to the forward LED input current,
IF, times 100.
6. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive)
dVCM /dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state
(i.e., VO > 2.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM /dt on the
trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V).
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is
the maximum tolerable dVCM /dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a
Logic High state (i.e., VO > 3.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM /dt on
the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state
(i.e., VO < 1.0 V).
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
10. The RL = 20 kΩ, CL = 100 pF load represents an IPM (Intelligent Power Module) load.
11. See Option 020 data sheet for more information.
12. Use of a 0.1 µF bypass capacitor connected between pins 5 and 8 is recommended.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second
(leakage detection current limit, Ii-o ≤ 5 µA). This test is performed before the 100% Production test shown in the VDE 0884
Insulation Related Characteristics Table, if applicable.
14. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second
(leakage detection current limit, Ii-o ≤ 5 µA). This test is performed before the 100% Production test shown in the VDE 0884
Insulation Related Characteristics Table, if applicable.
15. The difference between tPLH and tPHL between any two devices (same part number) under the same test condition. (See Power
Inverter Dead Time and Propagation Delay Specifications section.)
1-43
HCNW4504
HCPL-4504/0454
40 mA
35 mA
IO – OUTPUT CURRENT – mA
IO – OUTPUT CURRENT – mA
TA = 25°C
10 VCC = 5.0 V
30 mA
25 mA
5
20 mA
15 mA
10 mA
IF = 5 mA
0
0
20
10
TA = 25°C
20 VCC = 5.0 V
18
12
40 mA
35 mA
30 mA
25 mA
10
20 mA
8
15 mA
16
14
6
10 mA
4
2
0
IF = 5 mA
0
20
10
VO – OUTPUT VOLTAGE – V
VO – OUTPUT VOLTAGE – V
HCPL-4504/0454
1.5
1.0
0.5
0.0
NORMALIZED
IF = 16 mA
VO = 0.4 V
VCC = 5.0 V
TA = 25°C
0 2 4 6 8 10 12 14 16 18 20 22 24 26
NORMALIZED CURRENT TRANSFER RATIO
NORMALIZED CURRENT TRANSFER RATIO
Figure 1. DC and Pulsed Transfer Characteristics.
HCNW4504
NORMALIZED
IF = 16 mA
VO = 0.4 V
VCC = 5.0 V
TA = 25°C
2.0
1.6
1.2
0.8
0.4
0
0
5
10
15
20
25
IF – INPUT CURRENT – mA
IF – INPUT CURRENT – mA
Figure 2. Current Transfer Ratio vs. Input Current.
HCNW4504
HCPL-4504/0454
1000
100
IF
TA = 25°C
+
VF
–
10
IF – FORWARD CURRENT – mA
IF – FORWARD CURRENT – mA
1000
1.0
0.1
0.01
0.001
1.1
1.2
1.3
1.4
1.5
1.6
VF – FORWARD VOLTAGE – VOLTS
Figure 3. Input Current vs. Forward Voltage.
1-44
TA = 25°C
100
IF
+
VF
–
10
1.0
0.1
0.01
0.001
1.2
1.3
1.4
1.5
1.6
VF – FORWARD VOLTAGE – VOLTS
1.7
0.9
NORMALIZED
I F = 16 mA
VO = 0.4 V
VCC = 5.0 V
TA = 25°C
0.8
0.7
0.6
-60 -40 -20 0
20 40 60 80 100 120
HCNW4504
1.05
IOH – LOGIC HIGH OUTPUT CURRENT – nA
1.0
NORMALIZED CURRENT TRANSFER RATIO
NORMALIZED CURRENT TRANSFER RATIO
HCPL-4504/0454
1.1
NORMALIZED
I F = 16 mA
VO = 0.4 V
VCC = 5.0 V
TA = 25°C
1.0
0.95
0.9
0.85
-60 -40 -20 0
20 40 60 80 100 120
IF
0
VCC
10 1
10 0
10-1
10-2
-60 -40 -20
VOL
0
20 40 60 80 100 120
Figure 5. Logic High Output Current
vs. Temperature.
PULSE
GEN.
ZO = 50 Ω
t r = 5 ns
IF
VTHLH
1
8
2
7
3
6
VCC
RL
VO
0.1µF
I F MONITOR
4
5
CL
RM
t PLH
t PHL
IF = 0 mA
VO = VCC = 5.0 V
10 2
TA – TEMPERATURE – °C
Figure 4. Current Transfer Ratio vs. Temperature.
VTHHL
10 3
TA – TEMPERATURE – °C
TA – TEMPERATURE – °C
VO
10 4
Figure 6. Switching Test Circuit.
VCM
90%
0V
90%
10%
1
8
2
7
3
6
VCC
IF
10%
tr
A
tf
B
VO
VO
0.1µF
VCC
4
SWITCH AT A: IF = 0 mA
5
CL
VFF
VO
RL
VOL
SWITCH AT B: IF = 12 mA, 16 mA
VCM
+
–
PULSE GEN.
Figure 7. Test Circuit for Transient Immunity and Typical Waveforms.
1-45
HCPL-4504/0454
HCNW4504
IF = 10 mA
IF = 16 mA
0.10
-60 -40 -20 0
0.30
t PHL
0.25
0.20
IF = 10 mA
IF = 16 mA
0.15
0.10
-60 -40 -20 0
20 40 60 80 100 120
tPLH
TA – TEMPERATURE – °C
t PHL
0
2
4
6
IF = 10 mA
IF = 16 mA
VCC = 15.0 V
1.0 RL = 20 kΩ
CL = 100 pF
0.9 VTHHL = 1.5 V
VTHLH = 2.0 V
0.8
0.7
0.6
0.5
tPHL
0.4
1.2
t PLH
t PHL
1.5
1.0
IF = 10 mA
IF = 16 mA
0.5
0.0
0 100 200 300 400 500 600 700 800 900 1000
RL – LOAD CAPACITANCE – pF
Figure 13. Propagation Delay Time vs.
Load Capacitance.
1-46
0
20 40 60 80 100 120
Figure 11. Propagation Delay Time vs.
Temperature.
tp – PROPAGATION DELAY – µs
tp – PROPAGATION DELAY – µs
VCC = 15.0 V
3.0 TA = 25° C
RL = 20 kΩ
2.5 VTHHL = 1.5 V
VTHLH = 2.0 V
2.0 50% DUTY CYCLE
t PLH
TA – TEMPERATURE – °C
3.5
TA = 25° C
RL = 20 kΩ
CL = 100 pF
VTHHL = 1.5 V
VTHLH = 2.0 V
50% DUTY CYCLE
1.1
1.0
0.9
0.8
0.7
t PLH
0.6
0.5
0.4
0.3
IF = 10 mA
IF = 16 mA
0.2
0
2
4
6
8 10 12 14 16 18 20
RL – LOAD RESISTANCE – kΩ
1.8
IF = 10 mA
IF = 16 mA
50% DUTY CYCLE
RL– LOAD RESISTANCE – kΩ
Figure 10. Propagation Delay Time vs.
Load Resistance.
t PHL
0.4
Figure 9. Propagation Delay Time vs.
Load Resistance.
0.3
-60 -40 -20
8 10 12 14 16 18 20
tPLH
0.6
TA – TEMPERATURE – °C
tp – PROPAGATION DELAY – µs
tp – PROPAGATION DELAY – µs
t PLH
0.8
0.0
1.1
VCC = 5.0 V
TA = 25° C
CL = 100 pF
VTHHL = 1.5 V
VTHLH = 2.0 V
50% DUTY CYCLE
VCC = 5.0 V
TA = 25° C
CL = 15 pF
1.0 VTHHL = VTHLH = 1.5 V
10% DUTY CYCLE
1.2
20 40 60 80 100 120
Figure 8. Propagation Delay Time vs. Temperature.
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
tp – PROPAGATION DELAY – µs
0.20
VCC = 5.0 V
0.45 RL = 1.9 kΩ
CL = 15 pF
0.40 V
THHL = VTHLH = 1.5 V
10% DUTY CYCLE
0.35
t PHL
IF = 10 mA
IF = 16 mA
0.2
10 11 12 13 14 15 16 17 18 19 20
VCC – SUPPLY VOLTAGE – V
Figure 14. Propagation Delay Time vs.
Supply Voltage.
tp – PROPAGATION DELAY – µs
tPLH
0.25
0.15
1.4
0.50
VCC = 5.0 V
0.45 RL = 1.9 kΩ
CL = 15 pF
0.40 V
THHL = VTHLH = 1.5 V
10% DUTY CYCLE
0.35
t PHL
0.30
tp – PROPAGATION DELAY – µs
tp – PROPAGATION DELAY – µs
0.50
VCC = 15.0 V
1.6 TA = 25° C
CL = 100 pF
1.4
VTHHL = 1.5 V
1.2 VTHLH = 2.0 V
50% DUTY CYCLE
1.0
0.8
t PLH
t PHL
0.6
0.4
IF = 10 mA
IF = 16 mA
0.2
0.0
0
5 10 15 20 25 30 35 40 45 50
RL – LOAD RESISTANCE – kΩ
Figure 12. Propagation Delay Time vs.
Load Resistance.
OUTPUT POWER – PS, INPUT CURRENT – IS
HCPL-4504 OPTION 060
800
+HV
PS (mW)
700
+
IS (mA)
HCPL-4504/0454
HCNW4504
600
500
LED 1
2
7
400
6
3
300
(230)
200
OUT 1
BASE/GATE
DRIVE CIRCUIT
Q1
BASE/GATE
DRIVE CIRCUIT
Q2
5
100
0
0
25
75 100 125 150 175 200
50
+
HCPL-4504/0454
HCNW4504
TS – CASE TEMPERATURE – °C
OUTPUT POWER – PS, INPUT CURRENT – IS
8
HCNW4504
1000
LED 2
2
7
PS (mW)
900
6
IS (mA)
800
8
3
OUT 2
700
5
600
500
400
300
Figure 16. Typical Power Inverter.
200
–HV
100
0
0
25
50
75
100 125 150 175
TS – CASE TEMPERATURE – °C
Figure 15. Thermal Derating Curve,
Dependence of Safety Limiting Valve
with Case Temperature per VDE 0884.
Power Inverter Dead
Time and Propagation
Delay Specifications
The HCPL-4504/0454 and
HCNW4504 include a specification intended to help designers
minimize “dead time” in their
power inverter designs. The new
“propagation delay difference”
specification (tPLH - tPHL) is useful
for determining not only how
much optocoupler switching delay
is needed to prevent “shootthrough” current, but also for
determining the best achievable
worst-case dead time for a given
design.
When inverter power transistors
switch (Q1 and Q2 in Figure 17),
it is essential that they never
LED 1
OUT 1
tPLH min
(tPLH max–tPLH min)
tPLH max
TURN-ON DELAY
(tPLH max–tPLH min )
LED 2
OUT 2
tPHL min
(tPHL max–tPHL min)
tPHL max
MAXIMUM DEAD TIME
Figure 17. LED Delay and Dead Time Diagram.
1-47
conduct at the same time.
Extremely large currents will flow
if there is any overlap in their
conduction during switching
transitions, potentially damaging
the transistors and even the surrounding circuitry. This “shootthrough” current is eliminated by
delaying the turn-on of one
transistor (Q2) long enough to
ensure that the opposing
transistor (Q1) has completely
turned off. This delay introduces a
small amount of “dead time” at
the output of the inverter during
which both transistors are off
during switching transitions.
Minimizing this dead time is an
important design goal for an
inverter designer.
The amount of turn-on delay
needed depends on the propagation delay characteristics of the
optocoupler, as well as the
characteristics of the transistor
base/gate drive circuit. Considering only the delay characteristics
of the optocoupler (the characteristics of the base/gate drive
circuit can be analyzed in the
same way), it is important to
know the minimum and maximum
turn-on (tPHL) and turn-off (tPLH)
propagation delay specifications,
preferably over the desired
operating temperature range. The
importance of these specifications
is illustrated in Figure 17. The
waveforms labeled “LED1”,
“LED2”, “OUT1”, and “OUT2” are
the input and output voltages of
the optocoupler circuits driving
Q1 and Q2 respectively. Most
inverters are designed such that
the power transistor turns on
when the optocoupler LED turns
on; this ensures that both power
transistors will be off in the event
of a power loss in the control
circuit. Inverters can also be
designed such that the power
1-48
transistor turns off when the
optocoupler LED turns on; this
type of design, however, requires
additional fail-safe circuitry to
turn off the power transistor if an
over-current condition is
detected. The timing illustrated in
Figure 17 assumes that the power
transistor turns on when the
optocoupler LED turns on.
time is the sum of the maximum
difference in turn-on delay plus
the maximum difference in turnoff delay,
[(tPLHmax-tPLHmin)+(tPHLmax-tPHLmin)].
This expression can be
rearranged to obtain
[(tPLHmax-tPHLmin)-(tPHLmin-tPHLmax)],
The LED signal to turn on Q2
should be delayed enough so that
an optocoupler with the very
fastest turn-on propagation delay
(tPHLmin) will never turn on before
an optocoupler with the very
slowest turn-off propagation delay
(tPLHmax) turns off. To ensure this,
the turn-on of the optocoupler
should be delayed by an amount
no less than (tPLHmax - tPHLmin),
which also happens to be the
maximum data sheet value for the
propagation delay difference
specification, (tPLH - tPHL). The
HCPL-4504/0454 and
HCNW4504 specify a maximum
(tPLH - tPHL) of 1.3 µs over an
operating temperature range
of 0-70°C.
Although (tPLH-tPHL)max tells the
designer how much delay is
needed to prevent shoot-through
current, it is insufficient to tell the
designer how much dead time a
design will have. Assuming that
the optocoupler turn-on delay is
exactly equal to (tPLH - tPHL)max,
the minimum dead time is zero
(i.e., there is zero time between
the turn-off of the very slowest
optocoupler and the turn-on of
the very fastest optocoupler).
Calculating the maximum dead
time is slightly more complicated.
Assuming that the LED turn-on
delay is still exactly equal to
(tPLH - tPHL)max, it can be seen in
Figure 17 that the maximum dead
and further rearranged to obtain
[(tPLH-tPHL)max-(tPLH-tPHL)min],
which is the maximum minus the
minimum data sheet values of
(tPLH-tPHL). The difference
between the maximum and
minimum values depends directly
on the total spread in propagation
delays and sets the limit on how
good the worst-case dead time
can be for a given design.
Therefore, optocouplers with tight
propagation delay specifications
(and not just shorter delays or
lower pulse-width distortion) can
achieve short dead times in power
inverters. The HCPL-4504/0454
and HCNW4504 specify a
minimum (tPLH - tPHL) of -0.7 µs
over an operating temperature
range of 0-70°C, resulting in a
maximum dead time of 2.0 µs
when the LED turn-on delay is
equal to (tPLH-tPHL)max, or 1.3 µs.
It is important to maintain
accurate LED turn-on delays
because delays shorter than
(tPLH - tPHL)max may allow shootthrough currents, while longer
delays will increase the worst-case
dead time.