INTERSIL HCTS08HMSR

HCTS08MS
Radiation Hardened
Quad 2-Input AND Gate
August 1995
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
• Total Dose 200K RAD(Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
A1 1
14 VCC
B1 2
13 B4
Y1 3
12 A4
A2 4
11 Y4
• Latch-Up Free Under Any Conditions
B2 5
10 B3
• Military Temperature Range: -55oC to +125oC
Y2 6
9 A3
GND 7
8 Y3
• Dose Rate Survivability: >1 x
10
• Dose Rate Upset >10
1012
Rads (Si)/Sec
RAD(Si)/s 20ns Pulse
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
• LSTTL Input Compatibility
- VIL = 0.8V
- VIH = VCC/2
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS08MS is a Radiation Hardened Quad 2-Input
AND Gate. A high on both inputs force the output to a High state.
The HCTS08MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
A1
1
14
VCC
B1
2
13
B4
Y1
3
12
A4
A2
4
11
Y4
B2
5
10
B3
Y2
6
9
A3
GND
7
8
Y3
TRUTH TABLE
The HCTS08MS is supplied in a 14 lead Ceramic Flatpack
Package (K suffix) or a 14 lead SBDIP Package (D suffix).
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
SCREENING
LEVEL
HCTS08DMSR
-55oC to +125oC
Intersil Class
S Equivalent
14 Lead SBDIP
HCTS08KMSR
-55oC
Intersil Class
S Equivalent
14 Lead Ceramic
Flatpack
to
+125oC
PACKAGE
INPUTS
OUTPUTS
An
Bn
Yn
L
L
L
L
H
L
H
L
L
H
H
H
NOTE: L = Logic Level Low, H = Logic level High
HCTS08D/
Sample
+25oC
Sample
14 Lead SBDIP
HCTS08K/
Sample
+25oC
Sample
14 Lead Ceramic
Flatpack
HCTS08HMSR
+25oC
Die
Die
Functional Diagram
(1, 4, 9, 12)
An
(3, 6, 8, 11)
Yn
DB NA
(2, 5, 10, 13)
Bn
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number
File Number
518842
2136.2
Specifications HCTS08MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
SBDIP Package . . . . . . . . . . . . . . . . . . . .
74oC/W
24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 116oC/W 30oC/W
Maximum Package Power Dissipation at +125oC
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.66W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.43W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.6mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . 100ns/V Max
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETERS
Quiescent Current
Output Current
(Sink)
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage
Current
Noise Immunity
Functional Test
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
10
µA
2, 3
+125oC, -55oC
-
200
µA
1
+25oC
4.8
-
mA
2, 3
+125oC, -55oC
4.0
-
mA
1
+25oC
-4.8
-
mA
2, 3
+125oC, -55oC
-4.0
-
mA
VCC = 4.5V, VIH = 2.25V,
IOL = 50µA, VIL = 0.8V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 5.5V, VIH = 2.75V,
IOL = 50µA, VIL = 0.8V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 4.5V, VIH = 2.25V,
IOH = -50µA, VIL = 0.8V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIH = 2.75V,
IOH = -50µA, VIL = 0.8V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIN = VCC or
GND
1
+25oC
-0.5
+0.5
µA
2, 3
+125oC, -55oC
-5.0
+5.0
µA
7, 8A, 8B
+25oC, +125oC, -55oC
4.0
0.5
-
(NOTE 1)
CONDITIONS
SYMBOL
ICC
IOL
IOH
VOL
VOH
IIN
FN
VCC = 5.5V,
VIN = VCC or GND
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V
VCC = 4.5V,
VIH = 2.25V,
VIL = 0.8V, (Note 2)
LIMITS
NOTES:
1. All voltages reference to device GND.
2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number
2
518842
Specifications HCTS08MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
(NOTES 1, 2)
CONDITIONS
SYMBOL
Input to Output
TPHL
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
9
+25oC
2
18
ns
10, 11
+125oC, -55oC
2
20
ns
9
+25oC
2
20
ns
10, 11
+125oC, -55oC
2
22
ns
VCC = 4.5V
TPLH
VCC = 4.5V
LIMITS
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Capacitance Power
Dissipation
CPD
Input Capacitance
CIN
Output Transition
Time
CONDITIONS
VCC = 5.0V, f = 1MHz
VCC = 5.0V, f = 1MHz
TTHL
TTLH
VCC = 4.5V
NOTES
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
45
pF
1
+125oC, -55oC
-
80
pF
1
+25oC
-
10
pF
1
+125oC
-
10
pF
1
+25oC
-
15
ns
1
+125oC
-
22
ns
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD LIMITS
PARAMETERS
SYMBOL
(NOTES 1, 2)
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
Quiescent Current
ICC
VCC = 5.5V, VIN = VCC or GND
+25oC
-
0.2
mA
Output Current (Sink)
IOL
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
+25oC
4.0
-
mA
Output Current (Source)
IOH
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
+25oC
-4.0
-
mA
Output Voltage Low
VOL
VCC = 4.5V and 5.5V, VIH = VCC/2,
VIL = 0.8V at 200K RAD,
IOL = 50µA
+25oC
-
0.1
V
Output Voltage High
VOH
VCC = 4.5V and 5.5V, VIH = VCC/2,
VIL = 0.8V at 200K RAD,
IOH = -50µA
+25oC
VCC
-0.1
-
V
VCC = 5.5V, VIN = VCC or GND
+25oC
-5.0
+5.0
µA
Input Leakage Current
IIN
Spec Number
3
518842
Specifications HCTS08MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
200K RAD LIMITS
PARAMETERS
(NOTES 1, 2)
CONDITIONS
SYMBOL
TEMPERATURE
MIN
MAX
UNITS
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V at 200K RAD, (Note 3)
+25oC
-
-
-
Noise Immunity
Functional Test
FN
Input to Output
TPHL
VCC = 4.5V
+25oC
2
20
ns
TPLH
VCC = 4.5V
+25oC
2
22
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)
GROUP B
SUBGROUP
DELTA LIMIT
ICC
5
3µA
IOL/IOH
5
-15% of 0 Hour
PARAMETER
TABLE 6. APPLICABLE SUBGROUPS
GROUP A SUBGROUPS
COMFORMANCE GROUP
MIL-STD-883 METHOD
TESTED
RECORDED
Initial Test
100% 5004
1, 7, 9
1 (Note 2)
Interim Test
100% 5004
1, 7, 9, ∆
1, ∆ (Note 2)
PDA
100% 5004
1, 7, ∆
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A (Note 1)
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, ∆
Subgroup B6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 7, 9
1, 2, 3, ∆ (Note 2)
NOTES:
1. Alternate Group A testing in accordance with MIL-STD-883 Method 5005 may be exercised.
2. Table 5 parameters only.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
CONFORMANCE
GROUPS
Group E Subgroup 2
READ AND RECORD
METHOD
PRE RAD
POST RAD
PRE RAD
POST RAD
5005
1, 7, 9
Table 4
1, 9
Table 4 (Note 1)
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
Spec Number
4
518842
Specifications HCTS08MS
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V
VCC = 6V ± 0.5V
50kHz
25kHz
-
14
-
-
-
1, 2, 4, 5, 9, 10, 12,
13, 14
-
-
3, 6, 8, 11
14
1, 2, 4, 5, 9, 10,
12, 13
-
STATIC BURN-IN I TEST CONDITIONS (Note 1)
3, 6, 8, 11
1, 2, 4, 5, 7, 9, 10, 12,
13
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
3, 6, 8, 11
7
DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)
-
7
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in.
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
3, 6, 8, 11
7
1, 2, 4, 5, 9, 10, 12, 13, 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number
5
518842
HCTS08MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
100% Interim Electrical Test 2 (T2)
Sample - Wire Bond Pull Monitor, Method 2011
100% Delta Calculation (T0-T2)
Sample - Die Shear Monitor, Method 2019 or 2027
100% PDA 1, Method 5004 (Notes 1and 2)
100% Internal Visual Inspection, Method 2010, Condition A
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
Equivalent, Method 1015
100% Delta Calculation (T0-T1)
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Interim Electrical Test 3 (T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% PIND, Method 2020, Condition A
100% Final Electrical Test
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Serialization
100% Radiographic, Method 2012 (Note 3)
100% Initial Electrical Test (T0)
100% External Visual, Method 2009
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number
6
518842
HCTS08MS
AC Timing Diagrams
AC Load Circuit
DUT
TEST
POINT
VIH
INPUT
VS
CL
VIL
RL
TPLH
TPHL
VOH
CL = 50pF
VS
OUTPUT
RL = 500Ω
VOL
FIGURE 2
VOH
TTLH
TTHL
80%
VOL
20%
80%
20%
OUTPUT
FIGURE 1
AC VOLTAGE LEVELS
PARAMETER
HCTS
UNITS
VCC
4.50
V
VIH
3.00
V
VS
1.30
V
VIL
0
V
GND
0
V
Spec Number
7
518842
HCTS08MS
Die Characteristics
DIE DIMENSIONS:
87 x 88 mils
2.20 x 2.24mm
METALLIZATION:
Type: SiAl
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 mils x 4 mils
Metallization Mask Layout
HCTS08MS
A1
(1)
VCC
(14)
B4
(13)
B1 (2)
(12) A4
(11) Y4
Y1 (3)
(10) B3
A2 (4)
B2 (5)
(9) A3
(6)
Y2
(7)
GND
(8)
Y3
Spec Number
8
518842
HCTS08MS
Packaging
-A-
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
LEAD FINISH
c1
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-DBASE
METAL
E
b1
M
(b)
M
-Bbbb S C A - B S
INCHES
(c)
SECTION A-A
D S
D
BASE
PLANE
S2
Q
-C-
SEATING
PLANE
A
L
S1
eA
A A
b2
b
e
eA/2
c
aaa M C A - B S D S
ccc M C A - B S D S
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
-
E
0.220
0.310
5.59
7.87
-
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
MILLIMETERS
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
5
S1
0.005
-
0.13
-
6
S2
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
M
-
0.0015
-
0.038
2
N
14
14
8
Rev. 0 4/94
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Spec Number
9
518842
HCTS08MS
Packaging (Continued)
e
A
K14.B
A
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
PIN NO. 1
ID AREA
INCHES
-A-
D
-B-
S1
b
E1
0.004 M
H A-B S
D S
0.036 M
H A-B S
D S
C
Q
E
-D-
A
-C-
-HL
E2
E3
L
E3
MIN
MAX
MIN
MAX
NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.003
0.009
0.08
0.23
-
c1
0.003
0.007
0.08
0.18
-
D
-
0.390
-
9.91
3
E
0.235
0.260
5.97
6.60
-
E1
-
0.290
-
7.11
3
E2
0.125
-
3.18
-
-
E3
0.030
-
0.76
-
7
0.38
2
e
SEATING AND
BASE PLANE
c1
LEAD FINISH
BASE
METAL
k
(c)
b1
M
M
(b)
MILLIMETERS
SYMBOL
0.050 BSC
0.008
0.015
1.27 BSC
0.20
-
L
0.270
0.370
6.86
9.40
-
Q
0.010
0.020
0.25
0.51
8
S1
0.005
-
0.13
-
6
M
-
0.0015
-
0.04
-
N
14
14
-
SECTION A-A
Rev. 0 6/14/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
Spec Number
10
518842