Renesas HD407A4369H Microcomputer has an a/d converter Datasheet

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HD404369 Series
Rev. 6.0
Sept. 1998
Description
The HD404369 Series is a 4-bit HMCS400-Series microcomputer designed to increase program
productivity and also incorporate large-capacity memory. Each microcomputer has an A/D converter, input
capture timer, 32-kHz oscillator for clock, and four low-power dissipation modes.
The HD404369 Series includes nine chips: the HD404364, HD40A4364 with 4-kword ROM; the
HD404368, HD40A4368 with 8-kword ROM; the HD4043612, HD40A43612 with 12-kword ROM; the
HD404369, HD40A4369 with 16-kword ROM; the HD407A4369 with 16-kword PROM.
The HD40A4364, HD40A4368, HD40A43612, HD40A4369, and HD407A4369 are high speed versions
(minimum instruction cycle time: 0.47 µs).
The HD407A4369 is a PROM version (ZTAT microcomputer). A program can be written to the PROM
by a PROM writer, which can dramatically shorten system development periods and smooth the process
from debugging to mass production. (The ZTAT version is 27256-compatible.)
Features
• 512-digit × 4-bit RAM
• 54 I/O pins
 One input-only pin
 53 input/output pins: 8 pins are intermediate-voltage NMOS open drain with high-current pins (15
mA, max.)
• On-chip A/D converter (8-bit × 12-channel)
 Low power voltage 2.7 V to 6.0 V
• Three timers
 One event counter input
 One timer output
 One input capture timer
• Eight-bit clock-synchronous serial interface (1 channel)
• Alarm output
HD404369 Series
• Built-in oscillators
 Ceramic oscillator or crystal
 External clock drive is also possible
 Subclock: 32.768-kHz crystal oscillator
• Seven interrupt sources
 Two by external sources
 Three by timers
 One by A/D converter
 One by serial interface
• Four low-power dissipation modes
 Standby mode
 Stop mode
 Watch mode
 Subactive mode
• Instruction cycle time
 0.47 µs (fOSC = 8.5 MHz, 1/4 division ratio):
HD40A4364, HD40A4368, HD40A43612, HD40A4369, HD407A4369
 0.8 µs (fOSC = 5 MHz, 1/4 division ratio):
HD404364, HD404368, HD4043612, HD404369
 1/4, 1/8, 1/16, 1/32 system clock division ratio can be selecte
2
HD404369 Series
Ordering Information
Type
Instruction Cycle Time
Mask ROM Standard version (fOSC= 5 MHz)
Product Name
Model Name
ROM (Words) Package
HD404364
HD404364S
4,096
HD404368
HD4043612
HD404369
High speed versions
HD40A4364
(fOSC = 8.5 MHz)
HD40A4368
HD40A43612
HD40A4369
ZTAT
(fOSC = 8.5 MHz)
HD407A4369
DP-64S
HD404364F
FP-64B
HD404364H
FP-64A
HD404368S
8,192
DP-64S
HD404368F
FP-64B
HD404368H
FP-64A
HD4043612S
12,288
DP-64S
HD4043612F
FP-64B
HD4043612H
FP-64A
HD404369S
16,384
DP-64S
HD404369F
FP-64B
HD404369H
FP-64A
HD40A4364S
4,096
DP-64S
HD40A4364F
FP-64B
HD40A4364H
FP-64A
HD40A4368S
8,192
DP-64S
HD40A4368F
FP-64B
HD40A4368H
FP-64A
HD40A43612S
12,288
DP-64S
HD40A43612F
FP-64B
HD40A43612H
FP-64A
HD40A4369S
16,384
DP-64S
HD40A4369F
FP-64B
HD40A4369H
FP-64A
HD407A4369S
16,384
DP-64S
HD407A4369F
FP-64B
HD407A4369H
FP-64A
3
HD404369 Series
52
53
54
55
56
57
58
59
60
61
62
1
51
2
50
3
49
4
48
5
47
6
46
7
45
8
44
9
43
FP-64B
10
42
35
18
34
19
32
17
31
36
30
16
29
37
28
15
27
38
26
14
25
39
24
13
23
40
22
12
21
41
20
11
33
R11
R10
R93
R92
R91
R90
R83
R82
R81
R80
D13
D12
D11
D10
D9
D8
D7
D6
D5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
R00/SCK
R72
R71
R70
R63
R62
R61
R60
RA1
R23
R22
R21
R20
R13
R12
R11
R42/AN6
R43/AN7
R50/AN8
R51/AN9
R52/AN10
R53/AN11
AVCC
VCC
D0/INT0
D1/INT1
D2/EVNB
D3/BUZZ
D4/STOPC
R72
R00/SCK
R01/SI
R02/SO
R03/TOC
TEST
RESET
OSC1
OSC2
GND
X1
X2
AVSS
R30/AN0
R31/AN1
R32/AN2
R33/AN3
R40/AN4
R41/AN5
63
64
R71
R70
R63
R62
R61
R60
RA1
R23
R22
R21
R20
R13
R12
Pin Arrangement
FP-64A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R41/AN5
R42/AN6
R43/AN7
R50/AN8
R51/AN9
R52/AN10
R53/AN11
AVCC
VCC
D0/INT0
D1/INT1
D2/EVNB
D3/BUZZ
D4/STOPC
D5
D6
R01/SI
R02/SO
R03/TOC
TEST
RESET
OSC1
OSC2
GND
X1
X2
AVSS
R30/AN0
R31/AN1
R32/AN2
R33/AN3
R40/AN4
4
R10
R93
R92
R91
R90
R83
R82
R81
R80
D13
D12
D11
D10
D9
D8
D7
R60
R61
R62
R63
R70
R71
R72
R00/SCK
R01/SI
R02/SO
R03/TOC
TEST
RESET
OSC1
OSC2
GND
X1
X2
AVSS
R30/AN0
R31/AN1
R32/AN2
R33/AN3
R40/AN4
R41/AN5
R42/AN6
R43/AN7
R50/AN8
R51/AN9
R52/AN10
R53/AN11
AV CC
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
15
16
51
DP-64S
50
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
RA1
R23
R22
R21
R20
R13
R12
R11
R10
R93
R92
R91
R90
R83
R82
R81
R80
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4/STOPC
D3/BUZZ
D2/EVNB
D1/INT1
D0/INT0
VCC
HD404369 Series
Pin Description
Pin Number
Item
Symbol
DP-64S FP-64B FP-64A I/O
Function
Power
VCC
33
27
25
Applies power voltage
Supply
GND
16
10
8
Connected to ground
Test
TEST
12
6
4
I
Cannot be used in user applications. Connect this
pin to GND.
Reset
RESET
13
7
5
I
Resets the MCU
Oscillator OSC 1
14
8
6
I
Input/output pin for the internal oscillator. Connect
these pins to the ceramic oscillator or crystal
oscillator, or OSC1 to an external oscillator circuit.
OSC 2
15
9
7
O
X1
17
11
9
I
X2
18
12
10
O
D0–D 13
34–47
28–41
26–39
I/O
Input/output pins consisting of standard voltage
pins addressed individually by bits
RA 1
64
58
56
I
One-bit standard-voltage input port pin
R0 0–R0 3,
1–11,
1–5,
1–3,
I/O
R3 0–R9 3
20–31,
14–25, 12–23,
Four-bit input/output pins consisting of standard
voltage pins
48–55
42–49, 40–47,
Port
Interrupt
56–63
50–57
48–55
I/O
Four-bit input/output pins consisting of
intermediate voltage pins
INT0, INT1
34, 35
28, 29
26, 27
I
Input pins for external interrupts
38
32
30
I
Input pin for transition from stop mode to active
mode
8
2
64
I/O
Serial interface clock input/output pin
9
3
1
I
Serial interface receive data input pin
SO
10
4
2
O
Serial interface transmit data output pin
TOC
11
5
3
O
Timer output pin
EVNB
36
30
28
I
Event count input pin
BUZZ
37
31
29
O
Square waveform output pin
SCK
Interface SI
Timer
Alarm
57–64
R1 0–R2 3
Stop clear STOPC
Serial
59–64
Used with a 32.768-kHz crystal ocillator for clock
purposes
5
HD404369 Series
Pin Description (cont)
Pin Number
Item
DP-64S FP-64B FP-64A I/O
Function
A/D
AVCC
converter
32
26
24
Power supply for the A/D converter. Connect this
pin as close as possible to the V CC pin and at the
same voltage as VCC. If the power supply voltage
to be used for the A/D converter is not equal to
VCC, connect a 0.1-µF bypass capacitor between
the AVCC and AV SS pins. (However, this is not
necessary when the AV CC pin is directly connected
to the VCC pin.)
AVSS
19
13
11
Ground for the A/D converter. Connect this pin as
close as possible to GND at the same voltage as
GND.
AN 0–AN 11
20–31
14–25
12–23
6
Symbol
I
Analog input pins for the A/D converter
HD404369 Series
GND
VCC
X2
X1
OSC2
OSC1
STOPC
TEST
RESET
Block Diagram
D0
INT0
D1
System control
Interrupt
control
D2
INT1
D3
RAM
(512 × 4 bits)
D4
D port
D5
W
(2 bits)
Timer A
D6
D7
D8
D9
X
(4 bits)
D10
D11
D12
D13
R0 port
SPX
(4 bits)
R1 port
SCK
ALU
AVSS
R2 port
SPY
(4 bits)
R3 port
Serial
interface
SO
Internal data bus
SI
Internal data bus
Timer C
TOC
Internal address bus
Y
(4 bits)
R4 port
Timer B
EVNB
CA
(1 bit)
R6 port
A
(4 bits)
AVCC
B
(4 bits)
BUZZ
Buzzer
SP
(10 bits)
Data bus
Intermediate
voltage pin
Directional
signal line
Instruction
decoder
PC
(14 bits)
ROM
(16,384 × 10 bits) (12,288 × 10 bits)
(8,192 × 10 bits) (4,096 × 10 bits)
R7 port
ST
(1 bit)
R8 port
A/D
converter
R9 port
•
•
•
RA port
•
•
•
AN11
R5 port
AN0
R00
R01
R02
R03
R10
R11
R12
R13
R20
R21
R22
R23
R30
R31
R32
R33
R40
R41
R42
R43
R50
R51
R52
R53
R60
R61
R62
R63
R70
R71
R72
R80
R81
R82
R83
R90
R91
R92
R93
RA1
7
HD404369 Series
Memory Map
ROM Memory Map
The ROM memory map is shown in figure 1 and described below.
Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.
Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.
Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.
Program Area ($0000-$0FFF (HD404364, HD40A4364), $0000–$1FFF (HD404368, HD40A4368),
$0000–$2FFF (HD4043612, HD40A43612), $0000–$3FFF (HD404369, HD40A4369, HD407A4369)):
The entire ROM area can be used for program coding.
$0000
$000F
Vector address
(16 words)
$0010
Zero-page subroutine
(64 words)
$003F
$0040
$0FFF
$1000
$1FFF
Program
(4,096 words)
For HD404364, HD40A4364
Program
(8,192 words)
For HD404368, HD40A4368
$2000
Program
(12,288 words)
$2FFF
$0000
JMPL instruction
$0001 (jump to RESET, STOPC routine)
JMPL instruction
$0002
(jump to INT 0 routine)
$0003
JMPL instruction
$0004
(jump to INT 1 routine)
$0005
$0006
$0007
$0008
$0009
JMPL instruction
(jump to timer A routine)
$000A
$000B
$000C
$000D
$000E
$000F
JMPL instruction
(jump to timer C routine)
JMPL instruction
(jump to timer B routine)
JMPL instruction
(jump to A/D converter routine)
JMPL instruction
(jump to serial routine)
For HD4043612, HD40A43612
$3000
Program
(16,384 words)
$3FFF
Note:
For HD404369, HD40A4369,
HD407A4369
Since the ROM address areas between $0000–$0FFF overlap, the user can determine how these
areas are to be used.
Figure 1 ROM Memory Map
RAM Memory Map
The MCU contains 512-digit × 4 bit RAM areas. These RAM areas consist of a memory register area, a
data area, and a stack area. In addition, an interrupt control bits area, special function register area, and
register flag area are mapped onto the same RAM memory space labeled as a RAM-mapped register area.
The RAM memory map is shown in figure 2 and described below.
8
HD404369 Series
RAM Memory Map
Initial values
after reset
$000
$000
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
RAM-mapped registers
$040
Memory registers (MR)
$050
Data (432 digits)
$200
Not used
Interrupt control bits area
Port mode register A
(PMRA)
Serial mode register
(SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A
(TMA)
Timer mode register B1 (TMB1)
Timer B
(TRBL/TWBL)
(TRBU/TWBU)
Miscellaneous register
(MIS)
Timer mode register C
(TMC)
Timer C
(TRCL/TWCL)
(TRCU/TWCU)
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
0000
0000
Undefined
Undefined
0000
0000
*2/0000
*1
Undefined
0000
0000
*2/0000
Undefined
Not used
$3C0
Stack (64 digits)
(ACR)
(ADRL)
(ADRU)
(AMR1)
(AMR2)
W
R
R
W
W
0000
0000
1000
0000
-000
$020
Register flag area
$023
$024 Port mode register B
(PMRB)
$025 Port mode register C
(PMRC)
$026 Timer mode register B2
(TMB2)
$027 System clock selection register 1 (SSR1)
$028 System clock selection register 2 (SSR2)
W
W
W
W
W
0000
00-0
-000
000--00
Not used
Port D0–D3 DCR
(DCD0)
W
$016
$017
$018
$019
$01A
$3FF
A/D channel register
A/D data register lower
A/D data register upper
A/D mode register 1
A/D mode register 2
Not used
$02C
$02D
Notes: 1. Two registers are mapped
on the same area ($00A,
$00B, $00E, $00F).
2. Undefined.
R: Read only
W: Write only
R/W: Read/write
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03F
Port D4–D7 DCR
Port D8–D11 DCR
Port D12, D13 DCR
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR
Port R8 DCR
Port R9 DCR
Not used
(DCD1)
(DCD2)
W
W
0000
0000
0000
(DCD3)
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
(DCR9)
W
W
W
W
W
W
W
W
W
W
W
--00
0000
0000
0000
0000
0000
0000
0000
-000
0000
0000
$00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W
$00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W
$00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W
$00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W
Figure 2 RAM Memory Map
9
HD404369 Series
RAM-Mapped Register Area ($000–$03F):
• Interrupt Control Bits Area ($000–$003)
This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.
• Special Function Register Area ($004–$01F, $024–$03F)
This area is used as mode registers and data registers for external interrupts, serial interface,
timer/counters, A/D converter, and as data control registers for I/O ports. The structure is shown in
figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and
read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.
• Register Flag Area ($020–$023)
This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).
These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and
TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the
instructions are shown in figure 4.
Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.
Data Area ($050–$1FF)
Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.
The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.
10
HD404369 Series
Bit 3
Bit 2
Bit 1
Bit 0
$000
IM0
(IM of INT0)
IF0
(IF of INT0)
RSP
(Reset SP bit)
IE
(Interrupt
enable flag)
$001
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT1)
IF1
(IF of INT1)
$002
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
$003
IMS
(IM of serial)
IFS
(IF of serial)
IMAD
(IM of A/D)
IFAD
(IF of A/D)
Interrupt control bits area
Bit 2
Bit 1
Bit 0
$020
DTON
(Direct transfer
on flag)
Bit 3
ADSF
(A/D start flag)
WDON
(Watchdog
on flag)
LSON
(Low speed
on flag)
$021
RAME
(RAM enable
flag)
IAOF
(IAD off flag)
ICEF
(Input capture
error flag)
ICSF
(Input capture
status flag)
$022
IF:
IM:
IE:
SP:
Not used
$023
Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer
Register flag area
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IE
IM
LSON
IAOF
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
DTON
Not used
SEM/SEMD
REM/REMD
TM/TMD
Allowed
Allowed
Allowed
Not executed
Allowed
Allowed
Not executed
Allowed
Allowed
Not executed in active mode
Used in subactive mode
Not executed
Allowed
Not executed
Inhibited
Inhibited
Inhibited
Allowed
Allowed
Allowed
Not executed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
11
HD404369 Series
Bit 3
Bit 2
Bit 1
Bit 0
$000
Interrupt control bits area
$003
PMRA $004
D3 /BUZZ
SMR $005
R00 /SCK
R03/TOC
R01/SI
SRL $006
Serial data register (lower digit)
SRU $007
Serial data register (upper digit)
TMA $008
*1
TMB1 $009
*2
R02 /SO
Serial transmit clock speed selection
Clock source selection (timer A)
Clock source selection (timer B)
Timer B register (lower digit)
TRBL/TWBL $00A
Timer B register (upper digit)
TRBU/TWBU $00B
MIS $00C
*3
TMC $00D
*2
SO PMOS control Interrupt frame period selection
Clock source selection (timer C)
TRCL/TWCL $00E
Timer C register (lower digit)
TRCU/TWCU $00F
Timer C register (upper digit)
Not used
ACR $016
Analog channel selection
ADRL $017
A/D data register (lower digit)
A/D data register (upper digit)
ADRU $018
AMR1$019
R33/AN3
AMR2 $01A
Not used
R32/AN2
R31/AN1
R5/AN8–AN11 R4/AN4–AN7
R30/AN0
*4
Not used
$020
Register flag area
$023
PMRB $024
PMRC $025
D4/STOPC
D2/EVNB
TMB2 $026
Not used
*7
SSR1 $027
*8
*9
SSR2 $028
D1/INT1
D0/INT0
*5
*6
Buzzer output
EVNB detection edge selection
Clock select
Not used
Clock division ratio selection
Not used
Not used
DCD0 $02C
Port D3 DCD Port D2 DCD
Port D1 DCD Port D0 DCD
DCD1 $02D
Port D7 DCD Port D6 DCD
Port D5 DCD Port D4 DCD
DCD2 $02E
Port D11 DCD Port D10 DCD Port D9 DCD Port D8 DCD
DCD3 $02F
DCR0 $030
DCR1 $031
DCR2 $032
DCR3 $033
Not used
Port D13 DCD Port D12 DCD
Port R03 DCR Port R02 DCR Port R01 DCR Port R00 DCR
Port R13 DCR Port R12 DCR Port R11 DCR Port R10 DCR
Port R23 DCR Port R22 DCR Port R21 DCR Port R20 DCR
Port R33 DCR Port R32 DCR Port R31 DCR Port R30 DCR
DCR4 $034
Port R43 DCR Port R42 DCR Port R41 DCR Port R40 DCR
DCR5 $035
Port R53 DCR Port R52 DCR Port R51 DCR Port R50 DCR
DCR6 $036
Port R63 DCR Port R62 DCR Port R61 DCR Port R60 DCR
DCR7 $037
Not used
Port R72 DCR Port R71 DCR Port R70 DCR
DCR8 $038
Port R83 DCR Port R82 DCR Port R81 DCR Port R80 DCR
DCR9 $039
Port R93 DCR Port R92 DCR Port R91 DCR Port R90 DCR
Not used
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
9.
Timer-A/time-base
Auto-reload on/off
Pull-up MOS control
A/D conversion time
SO output level control in idle states
Serial clock source selection
Input capture selection
32-kHz oscillation stop
32-kHz oscillation division ratio
$03F
Figure 5 Special Function Register Area
12
HD404369 Series
Memory registers
$040 MR(0)
$041 MR(1)
$042 MR(2)
$043 MR(3)
$044 MR(4)
$045 MR(5)
$046 MR(6)
$047 MR(7)
$048 MR(8)
$049 MR(9)
$04A MR(10)
$04B MR(11)
$04C MR(12)
$04D MR(13)
$04E MR(14)
$04F MR(15)
Stack area
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
$3FF Level 1
$3C0
Bit 3
Bit 2
Bit 1
Bit 0
$3FC
ST
PC13
PC 12
PC11
$3FD
PC 10
PC9
PC 8
PC7
$3FE
CA
PC6
PC 5
PC4
$3FF
PC 3
PC2
PC 1
PC0
PC13 –PC0 : Program counter
ST: Status flag
CA: Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
13
HD404369 Series
Functional Description
Registers and Flags
The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described
below.
3
Accumulator
0
(A)
Initial value: Undefined, R/W
3
B register
Initial value: Undefined, R/W
W register
Initial value: Undefined, R/W
0
(B)
1
0
(W)
3
X register
Initial value: Undefined, R/W
0
(X)
3
Y register
0
(Y)
Initial value: Undefined, R/W
3
SPX register
Initial value: Undefined, R/W
SPY register
Initial value: Undefined, R/W
Carry
Initial value: Undefined, R/W
Status
Initial value: 1, no R/W
0
(SPX)
3
0
(SPY)
0
(CA)
0
(ST)
13
Program counter
Initial value: 0,
no R/W
0
(PC)
9
Stack pointer
Initial value: $3FF, no R/W
1
5
1
1
1
0
(SP)
Figure 7 Registers and Flags
Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.
W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.
14
HD404369 Series
SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.
Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an
interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.
Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction,
not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL,
CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or
bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read,
regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack
during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.
Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being
executed.
Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and
incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a
stack can be used up to 16 levels.
The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.
Reset
The MCU is reset by inputting a low-level voltage to the RESET pin. At power-on or when stop mode is
cancelled, RESET must be low for at least one tRC to enable the oscillator to stabilize. During operation,
RESET must be low for at least two instruction cycles.
Initial values after MCU reset are listed in table 1.
Interrupts
The MCU has 7 interrupt sources: two external signals (INT 0 and INT1), three timer/counters (timers A, B,
and C), serial interface, and A/D converter.
An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.
Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 in RAM are reserved for the
interrupt control bits which can be accessed by RAM bit manipulation instructions.
The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE)
and the IF to 0 and the interrupt mask (IM) to 1.
A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 7 interrupt sources are listed in
table 3.
15
HD404369 Series
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.
The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in
figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.
Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.
16
HD404369 Series
Table 1
Initial Values After MCU Reset
Item
Abbr.
Initial Value Contents
Program counter
(PC)
$0000
Indicates program execution point from start
address of ROM area
Status flag
(ST)
1
Enables conditional branching
Stack pointer
(SP)
$3FF
Stack level 0
Interrupt
Interrupt enable flag
flags/mask
(IE)
0
Inhibits all interrupts
Interrupt request flag
(IF)
0
Indicates there is no interrupt request
Interrupt mask
(IM)
1
Prevents (masks) interrupt requests
Port data register
(PDR)
All bits 1
Enables output at level 1
Data control register
(DCD0DCD2)
All bits 0
Turns output buffer off (to high impedance)
(DCD3)
- - 00
(DCR0–
DCR6,
DCR8,
DCR9)
All bits 0
(DCR7)
- 000
Port mode register A
(PMRA)
0000
Port mode register B
bits 2–0
(PMRB2– 000
PMRB0)
Refer to description of port mode register B
Port mode register C
(PMRC)
00 - 0
Refer to description of port mode register C
(TMA)
0000
Refer to description of timer mode register A
Timer mode register B1 (TMB1)
0000
Refer to description of timer mode register B1
Timer mode register B2 (TMB2)
- 000
Refer to description of timer mode register B2
Timer mode register C
(TMC)
0000
Refer to description of timer mode register C
Serial mode register
(SMR)
0000
Refer to description of serial mode register
Prescaler S
(PSS)
$000
—
Prescaler W
(PSW)
$00
—
Timer counter A
(TCA)
$00
—
Timer counter B
(TCB)
$00
—
Timer counter C
(TCC)
$00
—
Timer write register B
(TWBU,
TWBL)
$X0
—
Timer write register C
(TWCU,
TWCL)
$X0
—
000
—
I/O
Timer/count- Timer mode register A
ers, serial
interface
Octal counter
Refer to description of port mode register A
17
HD404369 Series
Item
A/D
Abbr.
Initial Value Contents
A/D mode register 1
(AMR1)
0000
A/D mode register 2
(AMR2)
- 000
A/D channel register
(ACR)
0000
Refer to description of A/D channel register
A/D data register
(ADRL)
0000
Refer to description of A/D data register
(ADRU)
1000
(LSON)
0
Bit registers Low speed on flag
Others
Refer to description of A/D mode register
Refer to description of operating modes
Watchdog timer on flag (WDON) 0
Refer to description of timer C
A/D start flag
(ADSF)
0
Refer to description of A/D converter
I AD off flag
(IAOF)
0
Refer to the description of A/D converter
Direct transfer on flag
(DTON)
0
Refer to description of operating modes
Input capture status
flag
(ICSF)
0
Refer to description of timer B
Input capture error flag (ICEF)
0
Refer to description of timer B
Miscellaneous register
(MIS)
0000
Refer to description of operating modes, I/O,
and serial interface
System clock select
register 1
(SSR1)
000 -
Refer to description of operating modes, and
oscillation circuits
System clock select
register 2
(SSR2)
- - 00
Refer to description of oscillation circuits
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.
2. X indicates invalid value. – indicates that the bit does not exist.
18
HD404369 Series
Item
Abbr.
Carry flag
(CA)
Accumulator
(A)
B register
(B)
W register
(W)
X/SPX register
(X/SPX)
Y/SPY register
(Y/SPY)
Serial data register
(SRL, SRU)
Status After Cancellation of Stop Status After all Other Types of
Mode by STOPC Input
Reset
Pre-stop-mode values are not
guaranteed; values must be
initialized by program
RAM
Pre-mcu-reset values are not
guaranteed; values must be
initialized by program
Pre-stop-mode values are retained
RAM enable flag
(RAME)
1
0
Port mode register B
bit 3
(PMRB3)
Pre-stop-mode values are retained
0
System clock select
register 1 bit 3
(SSR13)
Table 2
Vector Addresses and Interrupt Priorities
Reset/Interrupt
Priority
Vector Address
RESET, STOPC*
—
$0000
INT0
1
$0002
INT1
2
$0004
Timer A
3
$0006
Timer B
4
$0008
Timer C
5
$000A
A/D
6
$000C
Serial
7
$000E
Note: * The STOPC interrupt request is valid only in stop mode.
19
HD404369 Series
$ 000,0
IE
INT0 interrupt
Sequence control
• Push PC/CA/ST
• Reset IE
• Jump to vector
address
$ 000,2
IFO
$ 000,3
IMO
Vector
address
Priority control logic
INT1 interrupt
$ 001,0
IF1
$ 001,1
IM1
Timer A interrupt
$ 001,2
IFTA
$ 001,3
IMTA
Timer B interrupt
$ 002,0
IFTB
$ 002,1
IMTB
Timer C interrupt
$ 002,2
IFTC
$ 002,3
IMTC
A/D interrupt
$ 003,0
IFAD
$ 003,1
IMAD
Serial interrupt
$ 003,2
IFS
$ 003,3
IMS
Note: $m,n is RAM address $m, bit number n.
Figure 8 Interrupt Control Circuit
20
HD404369 Series
Table 3
Interrupt Processing and Activation Conditions
Interrupt Source
INT0
INT1
Timer A
Timer B
Timer C
A/D
Serial
IE
1
1
1
1
1
1
1
IF0 IM0
1
0
0
0
0
0
0
IF1 IM1
*
1
0
0
0
0
0
IFTA IMTA
*
*
1
0
0
0
0
IFTB IMTB
*
*
*
1
0
0
0
IFTC IMTC
*
*
*
*
1
0
0
IFAD IMAD
*
*
*
*
*
1
0
IFS IMS
*
*
*
*
*
*
1
Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Execution of
instruction at
start address
of interrupt
routine
Figure 9 Interrupt Processing Sequence
21
HD404369 Series
Power on
RESET = 0?
Yes
No
Interrupt
request?
No
Yes
No
IE = 1?
Yes
Reset MCU
Accept interrupt
Execute instruction
IE ← 0
Stack ← (PC)
Stack ← (CA)
Stack ← (ST)
PC ←(PC) + 1
PC← $0002
Yes
INT0
interrupt?
No
PC← $0004
Yes
INT1
interrupt?
No
PC← $0006
Yes
Timer-A
interrupt?
No
PC← $0008
Yes
Timer-B
interrupt?
No
PC ← $000A
Yes
Timer-C
interrupt?
No
PC ← $000C
Yes
A/D
interrupt?
No
PC ← $000E
(serial interrupt)
Figure 10 Interrupt Processing Flowchart
22
HD404369 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.
Table 4
Interrupt Enable Flag (IE: $000, Bit 0)
IE
Interrupt Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (INT0, INT1): Two external interrupt signals.
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): IF0 and IF1 are set at the rising
edge of signals input to INT 0 and INT1, as listed in table 5.
Table 5
External Interrupt Request Flags (IF0: $000, Bit2; IF1: $001, Bit 0)
IF0, IF1
Interrupt Request
0
No
1
Yes
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as listed in table 6.
Table 6
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1)
IM0, IM1
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.
Table 7
Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
IFTA
Interrupt Request
0
No
1
Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer
A interrupt request flag, as listed in table 8.
23
HD404369 Series
Table 8
Timer A Interrupt Mask (IMTA: 001, Bit 3)
IMTA
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in
table 9.
Table 9
Timer B Interrupt Request Flag (IFTB: $002, Bit 0)
IFTB
Interrupt Request
0
No
1
Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer
B interrupt request flag, as listed in table 10.
Table 10
Timer B Interrupt Mask (IMTB: $002, Bit 1)
IMTB
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 11.
Table 11
Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
IFTC
Interrupt Request
0
No
1
Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer
C interrupt request flag, as listed in table 12.
Table 12
Timer C Interrupt Mask (IMTC: $002, Bit 3)
IMTC
Interrupt Request
0
Enabled
1
Disabled (masked)
24
HD404369 Series
Serial Interrupt Request Flag (IFS: $003, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 13.
Table 13
Serial Interrupt Request Flag (IFS: $003, Bit 2)
IFS
Interrupt Request
0
No
1
Yes
Serial Interrupt Mask (IMS: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial
interrupt request flag, as listed in table 14.
Table 14
Serial Interrupt Mask (IMS: $003, Bit 3)
Mask IMS
Interrupt Request
0
Enabled
1
Disabled (masked)
A/D Interrupt Request Flag (IFAD: $003, Bit 0): Set at the completion of A/D conversion, as listed in
table 15.
Table 15
A/D Interrupt Request Flag (IFAD: $003, Bit 0)
IFAD
Interrupt Request
0
No
1
Yes
A/D Interrupt Mask (IMAD: $003, Bit 1): Prevents (masks) an interrupt request caused by the A/D
interrupt request flag, as listed in table 16.
Table 16
A/D Interrupt Mask (IMAD: $003, Bit 1)
IMAD
Interrupt Request
0
Enabled
1
Disabled (masked)
25
HD404369 Series
Operating Modes
The MCU has five operating modes as shown in table 17. The operations in each mode are listed in tables
18 and 19. Transitions between operating modes are shown in figure 11.
Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC 1
and OSC2.
Table 17
Operating Modes and Clock Status
Mode Name
Active
Standby
Stop
Watch
Subactive*2
Activation method RESET cancellation, SBY
instruction
interrupt STOPC
cancellation in stop
mode, STOP/SBY
instruction in
subactive mode
(when direct transfer
is selected)
STOP
STOP
INT0 or timer A
instruction when instruction when interrupt request
TMA3 = 0
TMA3 = 1
from watch
mode
Status System
oscillator
OP
OP
Stopped
Stopped
Stopped
Subsystem OP
oscillator
OP
*1 OP
OP
OP
Cancellation
method
RESET input,
RESET
STOP/SBY instruction input,
interrupt
request
RESET input,
RESET input,
RESET input,
STOPC input in INT0 or timer A STOP/SBY
stop mode
interrupt request instruction
Notes: OP implies in operation
1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select
register 1 (SSR1: $027).
2. Subactive mode is an optional function; specify it on the function option list.
26
HD404369 Series
Table 18
Operations in Low-Power Dissipation Modes
Function
Stop Mode
Watch Mode
Standby Mode
Subactive Mode
CPU
Reset
Retained
Retained
OP
RAM
Retained
Retained
Retained
OP
Timer A
Reset
OP
OP
OP
Timer B
Reset
Stopped
OP
OP
Timer C
Reset
Stopped
OP
OP
Serial
Reset
Stopped
OP
OP
A/D
Reset
Stopped
OP
Stopped
I/O
Reset
Retained
Retained
OP
Note: OP implies in operation
Table 19
I/O Status in Low-Power Dissipation Modes
Output
Input
Standby Mode,
Watch mode
Stop Mode
Active Mode,
Subactive mode
RA 1
—
—
Input enabled
D0–D 13 , R0–R9
Retained or output of
peripheral functions
High impedance
Input enabled
27
HD404369 Series
Reset by
RESET input or
by watchdog timer
Stop mode
(TMA3 = 0, SSR13 = 0)
RAME = 0
RESET1
RAME = 1
RESET2
STOPC
STOPC
STOP
Oscillate
Oscillate
Stop
fcyc
fcyc
Stop
Oscillate
Stop
Stop
Stop
Active
mode
Standby mode
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
SBY
Interrupt
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
Oscillate
Oscillate
fcyc
fcyc
fcyc
(TMA3 = 0, SSR13 = 1)
STOP
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
Stop
Stop
Stop
Stop
Stop
(TMA3 = 0)
Watch mode
(TMA3 = 1)
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
Oscillate
Oscillate
Stop
fW
fcyc
SBY
Interrupt
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
Oscillate
Oscillate
fcyc
fW
fcyc
(TMA3 = 1, LSON = 0)
STOP
INT0,
timer A*1
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
Stop
Oscillate
Stop
fW
Stop
*3
fOSC:
fX:
*2
Main oscillation frequency
Subactive
Suboscillation frequency
STOP
mode
(TMA3 = 1, LSON = 1)
for time-base
Stop
f
:
fOSC: Stop
OSC
*4
fOSC/4, fOSC/8, fOSC/16, fOSC/32
fcyc:
Oscillate
Oscillate
f
fX:
:
X
(software selectable)
INT0,
ø CPU: fSUB
ø CPU: Stop
*1
fSUB: fX/8 or fX/4
timer A
ø CLK: fW
ø CLK: fW
(software selectable)
ø
ø PER: Stop
:
f
SUB
PER
fW:
fX/8
ø CPU: System clock
ø CLK: Clock for time-base
Notes: 1. Interrupt source
ø PER: Clock for other
2. STOP/SBY (DTON = 1, LSON = 0)
peripheral functions
3. STOP/SBY (DTON = 0, LSON = 0)
LSON: Low speed on flag
4. STOP/SBY (DTON = Don’t care, LSON = 1)
DTON: Direct transfer on flag
Figure 11 MCU Status Transitions
28
HD404369 Series
Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.
The MCU enters standby mode when the SBY instruction is executed in active mode.
Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation
in standby mode is shown in figure 12.
29
HD404369 Series
Stop
Standby
Watch
Oscillator: Stop
Suboscillator: Active/Stop
Peripheral clocks: Stop
All other clocks: Stop
Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop
Oscillator: Stop
Suboscillator: Active
Peripheral clocks: Stop
All other clocks: Stop
No
RESET = 0?
Yes
No
RESET = 0?
Yes
IF0 • IM0 = 1?
No
No
STOPC = 0?
Yes
IF1 • IM1 = 1?
No
Yes
Yes
IFTA • IMTA
= 1?
Yes
RAME = 1
No
IFTB •
IMTB = 1?
RAME = 0
No
Yes
IFTC •
IMTC = 1?
Yes
No
IFAD •
IMAD = 1?
Yes
(SBY
only)
Restart
processor clocks
(SBY
only)
(SBY
only)
(SBY
only)
No
IFS •
IMS = 1?
(SBY
only)
No
Yes
Restart
processor clocks
Execute
next instruction
No
Reset MCU
IF = 1,
IM = 0, and
IE = 1?
Execute
next instruction
Yes
Accept interrupt
Figure 12 MCU Operation Flowchart
Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops. For the X1 and X2
oscillator to operate or stop can be selected by setting bit 3 of the system clock select register 1 (SSR1:
$027; operating: SSR13 = 0, stop: SSR13 = 1) (figure 23). The MCU enters stop mode if the STOP
instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3
= 0) (figure 37).
Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC
must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When
the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,
30
,
HD404369 Series
but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.
Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator operates, but
other function operations stop. Therefore, the power dissipation in this mode is the second least to stop
mode, and this mode is convenient when only clock display is used. In this mode, the OSC 1 and OSC2
oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP
instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in
subactive mode.
Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET
input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU
enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated,
the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC)
for an INT0 interrupt, as shown in figures 14 and 15.
Operation during mode transition is the same as that at standby mode cancellation (figure 12).
Stop mode
Oscillator
Internal
clock
RESET
or STOPC
tres
STOP instruction execution
tres ≥ tRC (stabilization period)
Figure 13 Timing of Stop Mode Cancellation
Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by
the X1 and X2 oscillator. In this mode, functions except the A/D conversion operate. However, because the
operating clock is slow, the power dissipation becomes low, next to watch mode.
The CPU instruction execution speed can be selected as 244 µs or 122 µs by setting bit 2 (SSR12) of the
system clock select register 1 (SSR1: $027). Note that the SSR12 value must be changed in active mode. If
the value is changed in subactive mode, the MCU may malfunction.
When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active
mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on
flag (DTON: $020, bit 3).
Interrupt Frame: In watch and subactive modes, øCLK is applied to timer A and the INT0 circuit. Prescaler
W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three
interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 15).
In watch and subactive modes, the timer-A/INT0 interrupt is generated synchronously with the interrupt
frame. The interrupt request is generated synchronously with the interrupt strobe timing except during
transition to active mode. The falling edge of the INT0 signal is input asynchronously with the interrupt
31
HD404369 Series
frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the
falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt
strobe timing.
Oscillation
stabilization period
Active mode
Watch mode
Active mode
Interrupt strobe
INT0
Interrupt request
generation
T
(During the transition
from watch mode to
active mode only)
T
tRC
TX
T: Interrupt frame length
t RC : Oscillation stabilization period
T + tRC ≤ TX ≤ 2T + tRC
Figure 14 Interrupt Frame
Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on
flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described
below:
• Set LSON to 0 and DTON to 1 in subactive mode.
• Execute the STOP or SBY instruction.
• The MCU automatically enters active mode from subactive mode after waiting for the MCU internal
processing time and oscillation stabilization time (figure 16).
Notes: 1. The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active
mode.
2. The transition time (TD) from subactive mode to active mode:
tRC < TD < T + tRC
32
HD404369 Series
Miscellaneous register (MIS: $00C)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
MIS3
MIS2
MIS1
MIS0
Bit name
MIS3
MIS2
Buffer control.
Refer to figure 34.
MIS1
MIS0
0
0
T*1
tRC * 1
Oscillation Circuit Conditions
0.24414 ms 0.12207 ms
0.24414
External clock input
ms* 2
0
1
15.625 ms
7.8125 ms
Ceramic oscillator
1
0
125 ms
62.5 ms
Crystal oscillator
1
1
Not used
—
Notes: 1. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used.
2. The value is applied only when direct transfer operation is used.
Figure 15 Miscellaneous Register (MIS)
STOP/SBY instruction execution
Subactive mode
MCU internal
processing period
Oscillation
stabilization
time
Active mode
(Set LSON = 0, DTON = 1)
Interrupt strobe
Direct transfer
completion timing
t RC
T
TD
T:
tRC:
tD:
Interrupt frame length
Oscillation stabilization period
Transition time
Figure 16 Direct Transition Timing
Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by inputting STOPC
as well as by R ESET. In either case, the MCU starts instruction execution from the starting address
(address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs
between cancellation by STOPC and by R ESET. When stop mode is cancelled by R ESET, RAME = 0;
when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop
mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop
mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is
33
HD404369 Series
used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the
beginning of the program.
MCU Operation Sequence: The MCU operates in the sequence shown in figures 17 to 19. It is reset by an
asynchronous RESET input, regardless of its status.
The low-power mode operation sequence is shown in figure 19. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a
STOP/SBYinstruction, make sure all interrupt flags are cleared or all interrupts are masked.
Power on
RESET = 0 ?
No
Yes
RAME = 0
MCU
operation
cycle
Reset MCU
Figure 17 MCU Operating Sequence (Power On)
34
HD404369 Series
MCU operation
cycle
IF = 1?
No
Instruction
execution
Yes
SBY/STOP
instruction?
Yes
No
IM = 0 and
IE = 1?
Yes
IE ← 0
Stack ← (PC),
(CA),
(ST)
No
Low-power mode
operation cycle
IF:
IM:
IE:
PC:
CA:
ST:
PC ← Next
location
PC ← Vector
address
Interrupt request flag
Interrupt mask
Interrupt enable flag
Program counter
Carry flag
Status flag
Figure 18 MCU Operating Sequence (MCU Operation Cycle)
35
HD404369 Series
Low-power mode
operation cycle
IF = 1 and
IM = 0?
No
Yes
Standby/watch
mode
No
IF = 1 and
IM = 0?
Yes
Stop mode
No
STOPC = 0?
Yes
Hardware NOP
execution
Hardware NOP
execution
RAME = 1
PC ← Next
Iocation
PC ← Next
Iocation
Reset MCU
Instruction
execution
MCU operation
cycle
For IF and IM operation, refer to figure 12.
Figure 19 MCU Operating Sequence (Low-Power Mode Operation)
Note: When the MCU is in watch mode or subactive mode, if the high level period before the falling edge
of INT0 is shorter than the interrupt frame, INT0 is not detected. Also, if the low level period after
the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Edge detection is
shown in figure 20. The level of the INT0 signal is sampled by a sampling clock. When this
sampled value changes to low from high, a falling edge is detected. In figure 21, the level of the
INT0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also
low at point B. Therefore, a falling edge is not detected. In (b), the sampled value is high at point
A, and also high at point B. A falling edge is not detected in this case either. When the MCU is in
watch mode or subactive mode, keep the high level and low level period of INT0 longer than the
interrupt frame
36
HD404369 Series
INT0
Sampling
High
Low
Low
Figure 20 Edge Detection
INT0
INT0
Interrupt
frame
Interrupt
frame
A: Low
B: Low
(a) High level period
A: High
B: High
(b) Low level period
Figure 21 Sampling Example
37
HD404369 Series
Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 22. As shown in table 20, a ceramic
oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be
connected to X1 and X2. The system oscillator can also be operated by an external clock.
Registers for Oscillator Circuit Operation
System Clock Selection Register 1 (SSR1: $027): Four bit write-only register which sets the subsystem
clock frequency (fSUB) division ratio, and sets the subsystem clock oscillation in stop mode. Bit 1 (SSR11)
of system clock select register 1 must be set according to the frequency of the oscillator connected to OSC1
and OSC2 (figure 23).
Bit 1 (SSR11) and bit 2 (SSR12) are initialized to 0 on reset and in stop mode. Bit 3 (SSR13) is initialized
to 0 only on reset.
LSON
OSC2
OSC1
System fOSC 1/4, 1/8,
1/16 or
oscillator
1/32
division
circuit*1
fX
X1
Subsystem
oscillator
fcyc
tcyc
Timing
generator
circuit
øCPU
CPU with ROM,
RAM, registers,
flags, and I/O
øPER
Peripheral
function
interrupt
System
clock
selection
fSUB
1/8 or 1/4
Timing
division t subcyc generator
circuit*2
circuit
TMA3
X2
1/8
division
circuit
fW
tWcyc
Timing
generator
circuit
Time-base
clock øCLK
selection
Time-base
interrupt
Notes: 1. 1/4, 1/8, 1/16 or 1/32 division ratio can be selected by setting bits 0 and 1 of system clock
select register 2 (SSR2: $028).
2. 1/8 or 1/4 division ratio can be selected by setting bit 2 of system clock select register 1
(SSR1: $027).
Figure 22 Clock Generation Circuit
38
HD404369 Series
System clock selection register 1 (SSR1: $027)
Bit
3
2
1
0
Initial value
0
0
0
—
Read/Write
W
W
W
Bit name
*1
SSR13
SSR12
—
*2
SSR11 Not used
SSR11
System Clock Selection
0
0.4 to 1.0 MHz
1
1.6 to 5.0 MHz (HD404369 Series)
1.6 to 8.5 MHz (HD40A4369 Series)
SSR12
0
fSUB = fX/8
1
fSUB = fX/4
SSR13
Notes:
1.
2.
32-kHz Oscillation Division
Ratio Selection
32-kHz Oscillation Stop
0
Oscillation operates in stop mode
1
Oscillation stops in stop mode
SSR13 will only be cleared to 0 by a RESET input. A STOPC input during stop mode will
not clear SSR13. Also note that SSR13 will not be cleared upon transition to stop mode.
If fOSC = 0.4 to 1.0 MHz, SSR11 must be set 0; if fOSC = 1.6 to 8.5 MHz, SSR11 must be set to
1. Do not use f OSC = 1.0 to 1.6 MHz with 32-kHz oscillation.
Figure 23 System Clock Selection Register 1 (SSR1)
System Clock Selection Register 2 (SSR2: $028): Four bit write-only register which is used to select the
system clock divisor (figure 24).
The division ratio of the system clock can be selected as 1/4, 1/8, 1/16, or 1/32 by setting bits 0 and 1
(SSR20, SSR21) of system clock select register 2 (SSR2).
The values of SSR20 and SSR21 are valid after the MCU enters watch mode. The system clock must be
stopped when the division ratio is to be changed.
There are two methods for changing the system clock divisor, as follows.
• In active mode, set the divisor by writing to SSR20 and SSR21. At this point, the prior divisor setting
will remain in effect. Now, switch to watch mode, and then return to active mode. When active mode
resumes, the system clock divisor will have switched to the new value.
• In subactive mode, set the divisor by writing to SSR20 and SSR21. Then return to active mode through
watch mode. When active mode resumes, the system clock divisor will have switched to the new value.
(The change will also take effect for direct transition to active mode.)
39
HD404369 Series
SSR2 is initialized to $0 on reset or in stop mode.
Notes on Usage
If the system clock select register 1 (SSR1: $027) setting does not match the oscillator frequency, the
subsystem using the 32.768-kHz oscillation will malfunction.
System clock selection register 2 (SSR2: $028)
Bit
3
2
1
0
Initial value
—
—
0
0
Read/Write
—
—
W
W
Bit name
Not used Not used SSR21
SSR20
SSR21
SSR20
0
0
1/4 division
0
1
1/8 division
1
0
1/16 division
1
1
1/32 division
System Clock Division Ratio
Figure 24 System Clock Selection Register 2 (SSR2)
40
HD404369 Series
Table 20
Oscillator Circuit Examples
Circut Configuration
External clock
operation
Ceramic oscillator
(OSC1, OSC 2)
Circut Constants
External
oscillator
OSC 1
Open
OSC 2
Ceramic oscillator: CSA4.00MG (Murata)
C1
Rf = 1 MΩ ±20%
OSC1
Ceramic
C1 = C2 = 30 pF ±20%
Rf
OSC2
C2
GND
Crystal oscillator
(OSC1, OSC 2)
Rf = 1 MΩ ±20%
C1
C1 = C2 = 10 to 22 pF ±20%
OSC1
Crystal
Crystal: Equivalent to circuit shown below
Rf
C0 = 7 pF max.
OSC2
RS = 100 Ω max.
C2
GND
L
CS
RS
OSC1
OSC2
C0
C1
Crystal oscillator
(X1, X2)
Crystal: 32.768 kHz: MX38T
X1
(Nippon Denpa)
C1 = C2 = 20 pF ±20%
Crystal
RS = 14 kΩ
X2
C0 = 1.5 pF
C2
GND
L
CS RS
X1
X2
C0
Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray
capacitance of the board, the user should consult with the crystal or ceramic oscillator
manufacturer to determine the circuit parameters.
2. Wiring among OSC1, OSC 2, X1, X2 and elements should be as short as possible, and must not
cross other wiring (see figure 25).
3. When a 32.768-kHz crystal oscillator is not used, fix pin X1 to GND and leave pin X2 open.
41
HD404369 Series
GND
RESET
OSC1
OSC2
GND
X1
X2
AVSS
Figure 25 Typical Layout of Crystal and Ceramic Oscillators
42
HD404369 Series
Input/Output
The MCU has 53 input/output pins (D0–D13, R0–R9) and an input pin (RA 1). The features are described
below.
• Eight pins (R1–R2) are high-current (15 mA max) input/output with intermediate voltage NMOS open
drain pins.
• The D0–D4, R0, R3–R5 input/output pins are multiplexed with peripheral function pins such as for the
timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port
setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output
selection are automatically switched according to the setting.
• Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.
• Peripheral function output pins are CMOS output pins. Only the R02/SO pin can be set to NMOS opendrain output by software.
• In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output
pins are in high-impedance state.
• Each input/output pin except for R1 and R2 has a built-in pull-up MOS, which can be individually
turned on or off by software.
I/O buffer configuration is shown in figure 26, programmable I/O circuits are listed in table 21, and I/O pin
circuit types are shown in table 22.
43
HD404369 Series
Table 21
Programmable I/O Circuits
MIS3 (bit 3 of MIS)
0
DCD, DCR
0
PDR
0
1
0
1
0
1
0
1
PMOS
—
—
—
On
—
—
—
On
NMOS
—
—
On
—
—
—
On
—
—
—
—
—
—
On
—
On
CMOS buffer
Pull-up MOS
1
1
0
1
Note: — indicates off status.
HLT
Pull-up control signal
VCC
Pull-up
MOS
MIS3
VCC
Buffer control signal
DCD, DCR
Output data
PDR
Input data
Input control signal
Figure 26 I/O Buffer Configuration
44
HD404369 Series
Table 22
Circuit Configuration of I/O Pins
I/O Pin Type
Circuit
Input/output pins
Pins
VCC
Pull-up control signal
Buffer control
signal
VCC
HLT
D0–D 13 ,
MIS3
R0 0, R0 1, R0 3
DCD, DCR
Output data
R3 0–R9 3
PDR
Input data
Input control signal
VCC
HLT
VCC
Pull-up control signal
Buffer control
signal
Output data
R0 2
MIS3
DCR
MIS2
PDR
Input data
Input control signal
HLT
R1 0–R2 3
DCR
Output data
PDR
Input data
Input control signal
Input pins
Input data
RA 1
Input control signal
Notes on next page.
45
HD404369 Series
I/O Pin Type
Circuit
Pins
Peripheral
Input/output
function pins pins
VCC
HLT
VCC
Pull-up control signal
MIS3
Output data
Input data
Output pins
VCC
SCK
SCK
HLT
VCC
Pull-up control signal
Output data
MIS2
SO
HLT
VCC
Pull-up control signal
Output data
Input pins
VCC
Input data
TOC, BUZZ
MIS3
TOC, BUZZ
HLT
SI,
MIS3
PDR
INT0, INT1,
SI, INT0, INT1,
EVNB, STOPC
STOPC
HLT
VCC
SO
MIS3
PMOS control
signal
VCC
SCK
EVNB,
AN 0–AN 11
MIS3
PDR
A/D input
Input control signal
Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT
signal goes low, and input/output pins enter the high-impedance state.
2. The HLT signal is 1 in active, standby, watch, and subactive modes.
46
HD404369 Series
Evaluation Chip Set and ZTAT/Mask ROM Product Differences
As shown in figure 27, the NMOS intermediate-voltage open drain pin circuit in the evaluation chip set
differs from that used in the ZTAT microcomputer and built-in mask ROM microcomputer products.
Please note that although these outputs in the ZTAT microcomputer and built-in mask ROM
microcomputer products can be set to high impedance by the combinations shown in table 23, these outputs
cannot be set to high impedance in the evaluation chip set.
Table 23
Program Control of High Impedance States
Register
Set Value
DCR
0
1
PDR
*
1
Notes: * An asterisk indicates that the value may be either 0 or 1 and has no influence on circuit operation.
This applies to the ZTAT and built-in mask ROM microcomputer NMOS open drain pins.
HLT
VCC
MIS3
VCC
DCR
PDR
CPU input
Input control signal
(a) Evaluation Chip Set Circuit Structure
HLT
DCR
PDR
CPU input
Input control signal
(b) ZTAT and Built-In Mask ROM Microcomputer Circuit Structure
Figure 27 NMOS Intermediate-Voltage Open Drain Pin Circuits
47
HD404369 Series
D Port (D 0–D13): Consist of 14 input/output pins addressed by one bit.
Pins D0–D 13 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.
Output data is stored in the port data register (PDR) for each pin. All pins D0–D13 are tested by the TD and
TDD instructions.
The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0–DCD3:
$02C–$02F) that are mapped to memory addresses (figure 28).
Pins D0–D2, D4 are multiplexed with peripheral function pins INT0, INT 1, EVNB, and STOPC, respectively.
The peripheral function modes of these pins are selected by bits 0–3 (PMRB0– PMRB3) of port mode
register B (PMRB: $024) (figure 29).
Pin D3 is multiplexed with peripheral function pin BUZZ. The peripheral function mode of this pin is
selected by bit 3 (PMRA3) of port mode register A (PMRA: $004) (figure 30).
R Ports (R0 0–R93): 39 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR
and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the
port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled
by R-port data control registers (DCR0–DCR9: $030–$039) that are mapped to memory addresses (figure
28).
Pin R0 0 is multiplexed with peripheral function pin SCK. The peripheral function mode of this pin is
selected by bit 3 (SMR3) of serial mode register (SMR: $005) (figure 31).
Pins R01–R0 3 are multiplexed with peripheral pins SI, SO and TOC, respectively. The peripheral function
modes of these pins are selected by bits 0–2 (PMRA0–PMRA2) of port mode register A (PMRA: $004), as
shown in figure 30.
Port R3 is multiplexed with peripheral function pins AN 0–AN 3, respectively. The peripheral function
modes of these pins can be selected by individual pins, by setting A/D mode register 1 (AMR1: $019)
(figure 32).
Ports R4 and R5 are multiplexed with peripheral function pins AN4–AN 11, respectively. The peripheral
function modes of these pins can be selected in 4-pin units by setting bits 1 and 2 (AMR21, AMR22) of
A/D mode register 2 (AMR2: $01A) (figure 33).
Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each
input/output pin. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous
register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data
register (PDR) of the corresponding pin—enabling on/off control of that pin alone (table 21 and figure 34).
The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to V CC by
their pull-up MOS transistors or by resistors of about 100 kΩ.
48
HD404369 Series
Data control register
(DCD0 to 3: $02C to $02F)
(DCR0 to 9: $030 to $039)
DCD0 to DCD3, DCR0 to DCR9
Bit
3
2
0
1
Initial value
0
0
0
0
Read/Write
W
W
W
W
DCD03–
DCD23,
DCR03–
DCR63,
DCR83–
DCR93
DCD02–
DCD22,
DCR02–
DCR92
DCD01–
DCD31,
DCR01–
DCR91
DCD00–
DCD30,
DCR00–
DCR90
Bit name
Bits 0 to 3
CMOS Buffer On/Off Selection
0
Off (high-impedance)
1
On
Correspondence between ports and DCD/DCR bits
Register Name
Bit 3
Bit 2
Bit 1
Bit 0
DCD0
D3
D2
D1
D0
DCD1
D7
D6
D5
D4
DCD2
D11
D10
D9
D8
DCD3
Not used
Not used
D13
D12
DCR0
R03
R02
R01
R00
DCR1
R13
R12
R11
R10
DCR2
R23
R22
R21
R20
DCR3
R33
R32
R31
R30
DCR4
R43
R42
R41
R40
DCR5
R53
R52
R51
R50
DCR6
R63
R62
R61
R60
DCR7
Not used
R72
R71
R70
DCR8
R83
R82
R81
R80
DCR9
R93
R92
R91
R90
Figure 28 Data Control Registers (DCD, DCR)
49
HD404369 Series
Port mode register B (PMRB: $024)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
PMRB3* PMRB2 PMRB1 PMRB0
PMRB0
PMRB2 D2/EVNB Mode Selection
0
D2
1
EVNB
0
D4
1
STOPC
0
D0
1
INT0
PMRB1
PMRB3 D4/STOPC Mode Selection
D0/INT0 Mode Selection
D1/INT1 Mode Selection
0
D1
1
INT1
Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not
reset but retains its value.
Figure 29 Port Mode Register B (PMRB)
Port mode register A (PMRA: $004)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
PMRA3
PMRA2 PMRA1 PMRA0
PMRA0
PMRA2
R03/TOC Mode Selection
0
R03
1
TOC
PMRA3
0
D3
1
BUZZ
0
R02
1
SO
PMRA1
D3/BUZZ Mode Selection
R01/SI Mode Selection
0
R01
1
SI
Figure 30 Port Mode Register A (PMRA)
50
R02/SO Mode Selection
HD404369 Series
Serial mode register (SMR: $005)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
SMR3
SMR2
SMR1
SMR0
Bit name
R00/SCK
Mode Selection
SMR3
0
R00
1
SCK
SMR2
SMR1
SMR0
Transmit clock selection.
Refer to figure 62 in the
serial interface section.
Figure 31 Serial Mode Register (SMR)
A/D mode register 1 (AMR1: $019)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
AMR13
AMR12
AMR11
AMR10
Bit name
AMR10
AMR12
R32/AN2 Mode Selection
0
R32
1
AN2
AMR13
0
R33
1
AN3
0
R30
1
AN0
AMR11
R33/AN3 Mode Selection
R30/AN0 Mode Selection
R31/AN1 Mode Selection
0
R31
1
AN1
Figure 32 A/D Mode Register 1 (AMR1)
51
HD404369 Series
A/D mode register 2 (AMR2: $01A)
Bit
3
Initial value
—
0
0
0
Read/Write
—
W
W
W
AMR21
AMR20
Bit name
2
0
1
Not used AMR22
AMR20
AMR22
R5/AN8–AN11 Pin Selection
Conversion Time
0
34tcyc
1
67tcyc
AMR21
R4/AN4–AN7 Pin Selection
0
R5
0
R4
1
AN8–AN11
1
AN4–AN7
Figure 33 A/D Mode Register 2 (AMR2)
Miscellaneous register (MIS: $00C)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
W
W
W
W
MIS3
MIS2
MIS1
MIS0
MIS3
Pull-Up MOS
On/Off Selection
0
Pull-up MOS off
1
Pull-up MOS on
(refer to table 21)
MIS2
CMOS Buffer
On/Off Selection
for Pin R02/SO
0
PMOS active
1
PMOS off
MIS1
tRC selection.
Refer to figure 15 in the
operation modes section.
Figure 34 Miscellaneous Register (MIS)
52
MIS0
HD404369 Series
Prescalers
The MCU has the following two prescalers, S and W.
The prescaler operating conditions are listed in table 24, and the prescaler output supply is shown in figure
35. The timer A–C input clocks except external events and the serial transmit clock except the external
clock are selected from the prescaler outputs, depending on corresponding mode registers.
Prescaler Operation
Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset,
prescaler S divides the system clock. Prescaler S keeps counting, except in watch and subactive modes and
at MCU reset.
Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by
eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset
by software.
Table 24
Prescaler Operating Conditions
Prescaler
Input Clock
Reset Conditions
Stop Conditions
Prescaler S
System clock
(in active and standby
mode), subsystem clock
(in subactive mode)
MCU reset
MCU reset, stop mode,
watch mode
Prescaler W
32-kHz crystal oscillation
MCU reset, software
MCU reset, stop mode
Subsystem
clock
fX/8
Prescaler W
Timer A
Timer B
fX/4 or fX/8
Timer C
System
clock
Clock
selector
Prescaler S
Serial
Alarm output
circuit
Figure 35 Prescaler Output Supply
53
HD404369 Series
Timers
The MCU has four timer/counters (A to C).
• Timer A: Free-running timer
• Timer B: Multifunction timer
• Timer C: Multifunction timer
Timer A is an 8-bit free-running timer. Timers B and C are 8-bit multifunction timers, whose functions are
listed in table 25. The operating modes are selected by software.
Timer A
Timer A Functions: Timer A has the following functions.
• Free-running timer
• Clock time-base
The block diagram of timer A is shown in figure 36.
Timer A Operations:
• Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:
$008).
Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied
to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow
sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after
reset to $00, and therefore it generates regular interrupts every 256 clocks.
• Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode
register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A generates
interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and
timer A can be reset to $00 by software.
Registers for Timer A Operation: Timer A operating modes are set by the following registers.
• Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode
and input clock source as shown in figure 37.
54
HD404369 Series
Table 25
Timer Functions
Functions
Clock source
Timer functions
Timer output
Timer A
Timer B
Timer C
Prescaler S
Available
Available
Available
Prescaler W
Available
—
—
External event
—
Available
—
Free-running
Available
Available
Available
Time-base
Available
—
—
Event counter
—
Available
—
Reload
—
Available
Available
Watchdog
—
—
Available
Input capture
—
Available
—
PWM
—
—
Available
Note: — implies not available.
1/4
fW
1/2
tWcyc
2 fW
Timer A interrupt
request flag
(IFTA)
Prescaler W
(PSW)
÷2
÷8
÷ 16
÷ 32
32.768-kHz
oscillator
1/2 tWcyc
Clock
Timer
counter A
(TCA) Overflow
System
clock
ø PER
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
÷ 2048
Selector
Internal data bus
Selector
Selector
Prescaler S (PSS)
3
Timer mode
register A
(TMA)
Figure 36 Timer A Block Diagram
55
HD404369 Series
Timer mode register A (TMA: $008)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TMA3
TMA2
TMA1
TMA0
TMA3
TMA2
TMA1
TMA0
0
0
0
0
PSS
2048tcyc
1
PSS
1024tcyc
0
PSS
512tcyc
1
PSS
128tcyc
0
PSS
32tcyc
1
PSS
8tcyc
0
PSS
4tcyc
1
PSS
2tcyc
0
PSW
32tWcyc
1
PSW
16tWcyc
0
PSW
8tWcyc
1
PSW
2tWcyc
0
PSW
1/2tWcyc
1
Inhibited
Bit name
1
1
0
1
1
0
0
1
1
0
1
Don't
care
Source
Input Clock
Prescaler Frequency Operating Mode
Timer A mode
Time-base
mode
PSW and TCA reset
Notes: 1. tWcyc = 244.14 µs (when a 32.768-kHz crystal oscillator is used)
2. Timer counter overflow output period (seconds) = input clock period (seconds) × 256.
3. The division ratio must not be modified during time-base mode operation, otherwise an overflow
cycle error will occur.
Figure 37 Timer Mode Register A (TMA)
56
HD404369 Series
Timer B
Timer B Functions: Timer B has the following functions.
• Free-running/reload timer
• External event counter
• Input capture timer
The block diagram for each operation mode of timer B is shown in figures 38 and 39.
Timer B Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register B1 (TMB1: $009).
Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by
software and incremented by one at each clock input. If an input clock is applied to timer B after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is
initialized to its initial value set in timer write register B; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• External event counter operation: Timer B is used as an external event counter by selecting the external
event input as an input clock source. In this case, pin D2/EVNB must be set to EVNB by port mode
register B (PMRB: $024).
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by timer mode register 2 (TMB2: $026). When both rising and falling
edges detection is selected, the time between the falling edge and rising edge of input signals must be
2tcyc or longer.
Timer B is incremented by one at each detection edge selected by timer mode register 2 (TMB2: $026).
The other operation is basically the same as the free-running/reload timer operation.
• Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVNB.
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by timer mode register 2 (TMB2: $026).
When a trigger edge is input to EVNB, the count of timer B is written to timer read register B (TRBL:
$00A, TRBU: $00B), and the timer B interrupt request flag (IFTB: $002, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer B is reset to $00, and then incremented again. While ICSF
is set, if a trigger input edge is applied to timer B, or if timer B generates an overflow, the input capture
error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0.
57
HD404369 Series
Interrupt request
flag of timer B
(IFTB)
Timer read
register B upper
(TRBU)
Timer read
register B lower
(TRBL)
Free-running
timer control
signal
Timer write
register B lower
(TWBL)
÷2
÷4
÷8
÷32
÷128
÷512
÷2048
Edge
detector
øPER
2
Overflow
Timer write
register B upper
(TWBU)
Selector
EVNB
System
clock
Timer counter B
(TCB)
3
Prescaler S (PSS)
Timer mode
register B1
(TMB1)
Edge detection control signal
Timer mode
register B2
(TMB2)
Figure 38 Timer B Free-Running and Reload Operation Block Diagram
58
Internal data bus
Clock
HD404369 Series
Input capture
status flag
(ICSF)
Interrupt request
flag of timer B
(IFTB)
Input capture
error flag
(ICEF)
Error
controller
Timer read
register B upper
(TRBU)
Timer read
register B lower
(TRBL)
Read
signal
Edge
detector
Clock
Timer counter B
(TCB)
Overflow
Input capture
timer control
signal
Selector
3
÷2
÷4
÷8
÷32
÷128
÷512
÷2048
System
clock
øPER
2
Internal data bus
EVNB
Timer mode
register B1
(TMB1)
Prescaler S (PSS)
Edge detection control signal
Timer mode
register B2
(TMB2)
Figure 39 Timer B Input Capture Operation Block Diagram
Registers for Timer B Operation: By using the following registers, timer B operation modes are selected
and the timer B count is read and written.





Timer mode register B1 (TMB1: $009)
Timer mode register B2 (TMB2: $026)
Timer write register B (TWBL: $00A, TWBU: $00B)
Timer read register B (TRBL: $00A, TRBU: $00B)
Port mode register B (PMRB: $024)
59
HD404369 Series
• Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in figure 40. It is reset to $0
by MCU reset.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register B1 write instruction. Setting timer B’s initialization by writing to timer
write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.
When selecting the input capture timer operation, select the internal clock as the input clock source.
Timer mode register B1 (TMB1: $009)
Bit
3
2
0
1
Initial value
0
0
0
0
Read/Write
W
W
W
W
TMB13
TMB12
TMB11
TMB10
Bit name
TMB13
Free-Running/Reload
Timer Selection
0
Free-running timer
1
Reload timer
Input Clock Period and Input
Clock Source
TMB12
TMB11
TMB10
0
0
0
2048tcyc
1
512tcyc
0
128tcyc
1
32tcyc
0
8tcyc
1
4tcyc
0
2tcyc
1
D2/EVNB (external event input)
1
1
0
1
Figure 40 Timer Mode Register B1 (TMB1)
• Timer mode register B2 (TMB2: $026): Three-bit write-only register that selects the detection edge of
signals input to pin EVNB and input capture operation as shown in figure 41. It is reset to $0 by MCU
reset.
• Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit
(TWBL) and the upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit
value is invalid (figures 42 and 43).
Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case,
the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the
timer B value. Timer B is initialized to the value in timer write register B at the same time the upper
digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value
needs no change, writing only to the upper digit initializes timer B.
60
HD404369 Series
• Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit
(TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 44 and 45).
The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained,
and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading
TRBL, the count of timer B when TRBU is read can be obtained.
When the input capture timer operation is selected and if the count of timer B is read after a trigger is
input, either the lower or upper digit can be read first.
• Port mode register B (PMRB: $024): Write-only register that selects D2/EVNB pin function as shown in
figure 46. It is reset to $0 by MCU reset.
Timer mode register B2 (TMB2: $026)
Bit
3
2
1
0
Initial value
—
0
0
0
—
W
Read/Write
Bit name
Not used TMB22
W
W
TMB21
TMB20
TMB21
TMB20
0
0
No detection
1
Falling edge detection
0
Rising edge detection
1
Rising and falling edge detection
1
EVNB Edge Detection Selection
Free-Running/Reload and Input Capture Selection
TMB22
0
Free-running/reload
1
Input capture
Figure 41 Timer Mode Register B2 (TMB2)
Timer write register B (lower digit) (TWBL: $00A)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TWBL3
TWBL2
TWBL1
TWBL0
Bit name
Figure 42 Timer Write Register B Lower Digit (TWBL)
61
HD404369 Series
Timer write register B (upper digit) (TWBU: $00B)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
W
W
W
W
TWBU3
TWBU2
TWBU1
TWBU0
Figure 43 Timer Write Register B Upper Digit (TWBU)
Timer read register B (lower digit) (TRBL: $00A)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRBL3
TRBL2
TRBL1
TRBL0
Figure 44 Timer Read Register B Lower Digit (TRBL)
Timer read register B (upper digit) (TRBU: $00B)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRBU3
TRBU2
TRBU1
TRBU0
Figure 45 Timer Read Register B Upper Digit (TRBU)
62
HD404369 Series
Port mode register B (PMRB: $024)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
PMRB3* PMRB2 PMRB1 PMRB0
PMRB0
PMRB2 D2/EVNB Mode Selection
0
D2
1
EVNB
0
D4
1
STOPC
0
D0
1
INT0
PMRB1
PMRB3 D4/STOPC Mode Selection
D0/INT0 Mode Selection
D1/INT1 Mode Selection
0
D1
1
INT1
Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not
reset but retains its value.
Figure 46 Port Mode Register B (PMRB)
63
HD404369 Series
Timer C
Timer C Functions: Timer C has the following functions.
• Free-running/reload timer
• Watchdog timer
• Timer output operation (PWM output)
The block diagram of timer C is shown in figure 47.
System reset signal
Watchdog on
flag (WDON)
Interrupt request
flag of timer C
(IFTC)
Watchdog timer
controller
Timer read register C upper (TRCU)
TOC
Timer output
control logic
Timer read
register C lower
(TRCL)
Clock
Timer
output
control
signal
÷2
÷4
÷8
÷32
÷128
÷512
÷1024
÷2048
Selector
System
clock
øPER
Overflow
Internal data bus
Timer counter C
(TCC)
Timer write
register C upper
(TWCU)
Free-running
timer control
signal
Timer write
register C lower
(TWCL)
3
Prescaler S (PSS)
Timer mode
register C (TMC)
Port mode
register A (PMRA)
Figure 47 Timer C Block Diagram
64
HD404369 Series
Timer C Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C (TMC: $00D).
Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. The watchdog timer operation flowchart is
shown in figure 48. Program run can be controlled by initializing timer C by software before it reaches
$FF.
• Timer output operation: The PWM output modes can be selected for timer C by setting port mode
register A (PMRA: $004).
By selecting the timer output mode, pin R03/TOC is set to TOC. The output from TOC is reset low by
MCU reset.
PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output
function. The output waveform differs depending on the contents of timer mode register C (TMC:
$00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in
figure 49.
$FF + 1
Overflow
Timer C
count value
$00
CPU
operation
Time
Normal
operation
Timer C
clear
Normal
operation
Timer C
clear
Program
runaway
Reset
Normal
operation
Figure 48 Watchdog Timer Operation Flowchart
65
HD404369 Series
T × (N + 1)
TMC3 = 0
(free-running
timer)
T
T × 256
TMC3 = 1
(reload timer)
T × (256 – N)
Notes: T: Input clock period supplied to counter. (The clock source and system clock division ratio are
determined by timer mode register C.)
N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.)
Figure 49 PWM Output Waveform
Registers for Timer C Operation: By using the following registers, timer C operation modes are selected
and the timer C count is read and written.




Timer mode register C (TMC: $00D)
Port mode register A (PMRA: $004)
Timer write register C (TWCL: $00E, TWCU: $00F)
Timer read register C (TRCL: $00E, TRCU: $00F)
• Timer mode register C (TMC: $00D): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in figure 50. It is reset to $0
by MCU reset.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C write instruction. Setting timer C’s initialization by writing to timer
write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.
66
HD404369 Series
Timer mode register C (TMC: $00D)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TMC3
TMC2
TMC1
TMC0
Bit name
TMC3
Free-Running/Reload
Timer Selection
0
Free-running timer
1
Reload timer
TMC2
TMC1
TMC0
0
0
0
2048tcyc
1
1024tcyc
0
512tcyc
1
128tcyc
0
32tcyc
1
8tcyc
0
4tcyc
1
2tcyc
1
1
0
1
Input Clock Period
Figure 50 Timer Mode Register C (TMC)
• Port mode register A (PMRA: $004): Write-only register that selects R03/TOC pin function as shown in
figure 51. It is reset to $0 by MCU reset.
• Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of the lower digit
(TWCL) and the upper digit (TWCU) as shown in figures 52 and 53. The operation of timer write
register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).
• Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of the lower digit
(TRCL) and the upper digit (TRCU) that holds the count of the timer C upper digit (figures 54 and 55).
The operation of timer read register C is basically the same as that of timer read register B (TRBL:
$00A, TRBU: $00B).
67
HD404369 Series
Port mode register A (PMRA: $004)
Bit
3
2
0
1
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
PMRA3
PMRA2 PMRA1 PMRA0
PMRA0
PMRA2
R03/TOC Mode Selection
0
R03
1
TOC
PMRA3
D3
1
BUZZ
0
R02
1
SO
PMRA1
D3/BUZZ Mode Selection
0
R02/SO Mode Selection
R01/SI Mode Selection
0
R01
1
SI
Figure 51 Port Mode Register A (PMRA)
Timer write register C (lower digit) (TWCL: $00E)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TWCL3
TWCL2
TWCL1
TWCL0
Bit name
Figure 52 Timer Write Register C Lower Digit (TWCL)
Timer write register C (upper digit) (TWCU: $00F)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
W
W
W
W
TWCU3
TWCU2
TWCU1
TWCU0
Figure 53 Timer Write Register C Upper Digit (TWCU)
68
HD404369 Series
Timer read register C (lower digit) (TRCL: $00E)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRCL3
TRCL2
TRCL1
TRCL0
Figure 54 Timer Read Register C Lower Digit (TRCL)
Timer read register C (upper digit) (TRCU: $00F)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRCU3
TRCU2
TRCU1
TRCU0
Figure 55 Timer Read Register C Upper Digit (TRCU)
Notes on Use
When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 26. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.
In this case, the lower digit (TWCL) must be written to first, bit writing only to the lower digit does not
change the timer C value. Timer C is changed to the value in timer write register B at the same time the
upper digit (TWCU) is written to.
69
HD404369 Series
Table 26
PWM Output Following Update of Timer Write Register
PWM Output
Mode
Timer Write Register is Updated during High Timer Write Register is Updated during Low
PWM Output
PWM Output
Timer write
register
updated to
value N
Reload
T
Interrupt
request
T × (255 – N)
T
Timer write
register
updated to
value N
T
T × (255 – N)
70
Interrupt
request
T
HD404369 Series
Alarm Output Function
The MCU has a built-in pulse output function called BUZZ. The pulse frequency can be selected from the
prescaler S’s outputs, and the output frequency depends on the state of port mode register C (PMRC: $025).
The duty cycle of the pulse output is fixed at 50%.
Port Mode Register C (PMRC: $025): Four-bit write-only register that selects the alarm frequencies as
shown in figure 57. It is reset to $0 by MCU reset.
BUZZ
Alarm output
control signal
Alarm output
controller
System
clock
øPER
2
÷2048
÷1024
÷512
÷256
Selector
Port mode
register A
(PMRA)
Port mode
register C
(PMRC)
Internal data bus
Port Mode Register A (PMRA: $004): Four-bit write-only register that selects D3/BUZZ pin function as
shown in figure 51. It is reset to $0 by MCU reset.
Prescaler S (PSS)
Figure 56 Alarm Output Function Block Diagram
71
HD404369 Series
Port mode register C (PMRC: $025)
Bit
3
2
1
0
Initial value
0
0
Undefined
0
Read/Write
W
W
W
W
PMRC2
PMRC1
PMRC0
Bit name
PMRC3
0
1
PMRC2
PMRC3
System Clock Divisor
PMRC0
Serial Clock Division Ratio
0
÷2048
0
Prescaler output divided by 2
1
÷1024
1
Prescaler output divided by 4
0
÷512
1
÷256
PMRC1
Output Level Control in Idle States
0
Low level
1
High level
Figure 57 Port Mode Register C (PMRC)
72
HD404369 Series
Serial Interface
The serial interface serially transfers and receives 8-bit data, and includes the following features.
• Multiple transmit clock sources
 External clock
 Internal prescaler output clock
 System clock
• Output level control in idle states
Four registers, an octal counter, and a selector are also configured for the serial interface as follows.







Serial data register (SRL: $006, SRU: $007)
Serial mode register (SMR: $005)
Port mode register A (PMRA: $004)
Port mode register C (PMRC: $025)
Miscellaneous register (MIS: $00C)
Octal counter (OC)
Selector
The block diagram of the serial interface is shown in figure 58.
73
HD404369 Series
Octal
counter (OC)
SO
Serial interrupt
request flag
(IFS)
Idle
controller
SCK
I/O
controller
SI
Clock
1/2
Selector
1/2
Transfer
control
signal
Internal data bus
Serial data
register (SR)
Selector
÷2
÷8
÷32
÷128
÷512
÷2048
3
System
clock
øPER
Prescaler S (PSS)
Serial mode
register
(SMR)
Port mode
register C
(PMRC)
Figure 58 Serial Interface Block Diagram
Serial Interface Operation
Selecting and Changing the Operating Mode: Table 27 lists the serial interface’s operating modes. To
select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and the
serial mode register (SMR: $005) settings; to change the operating mode, always initialize the serial
interface internally by writing data to the serial mode register. Note that the serial interface is initialized by
writing data to the serial mode register. Refer to the following Serial Mode Register section for details.
Pin Setting: The R00/SCK pin is controlled by writing data to the serial mode register (SMR: $005). The
R0 1/SI and R0 2/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the
following Registers for Serial Interface section for details.
Transmit Clock Source Setting: The transmit clock source is set by writing data to the serial mode
register (SMR: $005) and port mode register C (PMRC: $025). Refer to the following Registers for Serial
Interface section for details.
Data Setting: Transmit data is set by writing data to the serial data register (SRL: $006, SRU, $007).
Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the
transmit clock and is input from or output to an external system.
74
HD404369 Series
The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output
level control in idle states is performed.
Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000
by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit
clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000,
the serial interrupt request flag (IFS: $003, bit 2) is set, and the transfer stops.
When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4tcyc
to 8192tcyc by setting bits 0 to 2 (SMR0– SMR2) of serial mode register (SMR: $005) and bit 0 (PMRC0)
of port mode register C (PMRC: $025) as listed in table 28.
Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 59.




STS wait state
Transmit clock wait state
Transfer state
Continuous clock output state (only in internal clock mode)
• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 59). In STS
wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is
then executed (01, 11), the serial interface enters transmit clock wait state.
• Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the
falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12)
increments the octal counter, shifts the serial data register, and puts the serial interface in transfer state.
However, note that if continuous clock output mode is selected in internal clock mode, the serial
interface does not enter transfer state but enters continuous clock output state (17).
The serial interface enters STS wait state by writing data to the serial mode register (SMR: $005) (04,
14) in transmit clock wait state.
• Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge
of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction
sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is
executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait
state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.
In transfer state, writing data to the serial mode register (SMR: $005) (06, 16) initializes the serial
interface, and STS wait state is entered.
If the state changes from transfer to another state, the serial interrupt request flag (IFS: $003, bit 2) is set
by the octal counter that is reset to 000.
• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the SCK pin.
75
HD404369 Series
When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If the serial mode register (SMR: $005) is written to in continuous clock output mode (18), STS wait
state is entered.
Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state,
the output level of the SO pin can be controlled by setting bit 1 (PMRC1) of port mode register C (PMRC:
$025) to 0 or 1. The output level control example is shown in figure 60. Note that the output level cannot be
controlled in transfer state.
Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 61.
Table 27
Serial Interface Operating Modes
SMR
PMRA
Bit 3
Bit 1
Bit 0
Operating Mode
1
0
0
Continuous clock output mode
1
Transmit mode
0
Receive mode
1
Transmit/receive mode
1
Table 28
Serial Transmit Clock (Prescaler Output)
PMRC
SMR
Bit 0
Bit 2
Bit 1
Bit 0
Prescaler Division Ratio
Transmit Clock Frequency
0
0
0
0
÷ 2048
4096t cyc
1
÷ 512
1024t cyc
0
÷ 128
256t cyc
1
÷ 32
64t cyc
0
÷8
16t cyc
1
÷2
4t cyc
0
÷ 4096
8192t cyc
1
÷ 1024
2048t cyc
0
÷ 256
512t cyc
1
÷ 64
128t cyc
0
÷ 16
32t cyc
1
÷4
8t cyc
1
1
1
0
0
0
1
1
76
0
HD404369 Series
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer completion processing is performed and IFS is reset, writing to the serial mode
register (SMR: $005) changes the state from transfer to STS wait. At this time IFS is set again, and
therefore the error can be detected.
Notes on Use:
• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to the serial mode
register (SMR: $005) again.
• Serial interrupt request flag (IFS: $003, bit 2) set: If the state is changed from transfer to another by
writing to the serial mode register (SMR: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request
flag, serial mode register write or STS instruction execution must be programmed to be executed after
confirming that the SCK pin is at 1, that is, after executing the input instruction to port R0.
External clock mode
STS wait state
(octal counter = 000,
transmit clock disabled)
SMR write
04
00
06
01
MCU reset
SMR write (IFS ← 1)
STS instruction
02 Transmit clock
Transmit clock wait state
(octal counter = 000)
03
8 transmit clocks
Transfer state
(octal counter ≠ 000)
05
STS instruction (IFS ← 1)
Internal clock mode
STS wait state
(octal counter = 000,
transmit clock disabled)
SMR write
18
Continuous clock output state
(PMRA 0, 1 = 0, 0)
10
13
SMR write
14
11
STS instruction
MCU reset
8 transmit clocks
16 SMR write (IFS← 1)
Transmit clock 17
12 Transmit clock
Transmit clock wait state
(octal counter = 000)
Transfer state
(octal counter ≠ 000)
15
STS instruction (IFS ← 1)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 59 Serial Interface State Transitions
77
,
HD404369 Series
Transmit clock
wait state
State
STS wait state
Transmit clock
wait state
Transfer state
STS wait state
MCU reset
Port selection
PMRA write
External clock selection
SMR write
Output level control in
idle states
Dummy write for
state transition
Output level control in
idle states
PMRC write
Data write for transmission
SRL, SRU write
STS instruction
SCK pin (input)
SO pin
Undefined
LSB
MSB
IFS
External clock mode
Flag reset at transfer completion
Transmit clock
wait state
State
STS wait state
Transfer state
STS wait state
MCU reset
Port selection
PMRA write
Internal clock selection
SMR write
Output level control in
idle states
PMRC write
Output level control in
idle states
Data write for transmission
SRL, SRU write
STS instruction
SCK pin (output)
SO pin
Undefined
LSB
MSB
IFS
Internal clock mode
Flag reset at transfer completion
Figure 60 Example of Serial Interface Operation Sequence
78
HD404369 Series
Transfer completion
(IFS ← 1)
Interrupts inhibited
IFS ← 0
SMR write
IFS = 1
Yes
Transmit clock
error processing
No
Normal
termination
Transmit clock error detection flowchart
Transmit clock
wait state
Transmit clock wait state
Transfer state
State
Transfer state
SCK pin (input)
Noise
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit clock
error. When SMR is written,
IFS is set.
SMR write
IFS
Flag set because octal
counter reaches 000
Flag reset at
transfer completion
Transmit clock error detection procedure
Figure 61 Transmit Clock Error Detection
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written by the following registers.





Serial Mode Register (SMR: $005)
Serial Data Register (SRL: $006, SRU: $007)
Port Mode Register A (PMRA: $004)
Port Mode Register C (PMRC: $025)
Miscellaneous Register (MIS: $00C)
79
HD404369 Series
Serial Mode Register (SMR: $005): This register has the following functions (figure 62).
•
•
•
•
R0 0/SCK pin function selection
Transmit clock selection
Prescaler division ratio selection
Serial interface initialization
Serial mode register (SMR: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.
A write signal input to serial mode register (SMR: $005) discontinues the input of the transmit clock to the
serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed
during data transfer, the serial interrupt request flag (IFS: $003, bit 2) is set.
Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.
Serial mode register (SMR: $005)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
SMR3
W
W
W
W
SMR3
SMR2
SMR1
SMR0
R00/SCK
Mode Selection
0
R00
1
SCK
Clock Source
Output
Prescaler
Refer to
table 28
0
Output
System clock
—
1
Input
External clock
—
SMR1
SMR0
0
0
0
1
1
Prescaler
Division Ratio
SCK
SMR2
0
1
1
0
0
1
1
Figure 62 Serial Mode Register (SMR)
80
HD404369 Series
Port Mode Register C (PMRC: $025): This register has the following functions (figure 63).
• Prescaler division ratio selection
• Output level control in idle states
Port mode register C (PMRC: $025) is a 4-bit write-only register. It cannot be written during data transfer.
By setting bit 0 (PMRC0) of this register, the prescaler division ratio is selected. Bit 0 (PMRC0) can be
reset to 0 by MCU reset. By setting bit 1 (PMRC1), the output level of the SO pin is controlled in idle
states. The output level changes at the same time that PMRC1 is written to.
Port mode register C (PMRC: $025)
Bit
3
2
1
0
Initial value
0
0
Undefined
0
Read/Write
Bit name
W
W
W
W
PMRC3
PMRC2
PMRC1
PMRC0
PMRC0
Alarm output function.
Refer to figure 57.
Serial Clock Division Ratio
0
Prescaler output divided by 2
1
Prescaler output divided by 4
PMRC1
Output Level Control in Idle States
0
Low level
1
High level
Figure 63 Port Mode Register C (PMRC)
81
HD404369 Series
Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 64 and
65).
• Transmission data write and shift
• Receive data shift and read
Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the
transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 66.
Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.
Serial data register (lower digit) (SRL: $006)
Bit
Initial value
1
2
3
0
Undefined Undefined Undefined Undefined
Read/Write
R/W
R/W
R/W
R/W
Bit name
SR3
SR2
SR1
SR0
Figure 64 Serial Data Register (SRL)
Serial data register (upper digit) (SRU: $007)
Bit
1
2
3
Initial value
0
Undefined Undefined Undefined Undefined
Read/Write
R/W
R/W
R/W
R/W
Bit name
SR7
SR6
SR5
SR4
Figure 65 Serial Data Register (SRU)
Transmit clock
1
Serial output
data
2
3
4
5
6
LSB
Serial input data
latch timing
Figure 66 Serial Interface Output Timing
82
7
8
MSB
HD404369 Series
Port Mode Register A (PMRA: $004): This register has the following functions (figure 67).
• R0 1/SI pin function selection
• R0 2/SO pin function selection
Port mode register A (PMRA: $004) is a 4-bit write-only register, and is reset to $0 by MCU reset.
Port mode register A (PMRA: $004)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
PMRA3
PMRA2 PMRA1 PMRA0
PMRA0
PMRA2
R03/TOC Mode Selection
0
R03
1
TOC
PMRA3
0
D3
1
BUZZ
0
R02
1
SO
PMRA1
D3/BUZZ Mode Selection
R02/SO Mode Selection
R01/SI Mode Selection
0
R01
1
SI
Figure 67 Port Mode Register A (PMRA)
83
HD404369 Series
Miscellaneous Register (MIS: $00C): This register has the following functions (figure 68).
• R0 2/SO pin PMOS control
Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.
Miscellaneous register (MIS: $00C)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
MIS3
MIS2
MIS1
MIS0
MIS3
Pull-Up MOS
On/Off Selection
MIS2
CMOS Buffer
On/Off Selection
for Pin R02/SO
0
Pull-up MOS off
0
PMOS active
1
Pull-up MOS on
(refer to table 21)
1
PMOS off
Bit name
MIS1
tRC selection.
Refer to figure 15 in the
operation modes section.
Figure 68 Miscellaneous Register (MIS)
84
MIS0
HD404369 Series
A/D Converter
The MCU has a built-in A/D converter that uses a sequential comparison method with a resistor ladder. It
can measure twelve analog inputs with 8-bit resolution. The block diagram of the A/D converter is shown
in figure 69.
4
A/D mode
register 1
(AMR1)
A/D interrupt
request flag
(IFAD)
2
Selector
Encoder
+
Comp
–
AVCC
AVSS
D/A
A/D
controller
Control signal
for conversion
time
A/D start flag
(ADSF)
A/D mode
register 2
(AMR2)
A/D data
register
(ADRU, L)
Internal data bus
4
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
A/D channel
register (ACR)
IAD off flag
(IAOF)
Operating mode signal (1 in
stop, watch, and subactive modes)
Figure 69 A/D Converter Block Diagram
85
HD404369 Series
Registers for A/D Converter Operation
A/D Mode Register 1 (AMR1: $019): Four-bit write-only register which selects digital or analog ports, as
shown in figure 70.
A/D mode register 1 (AMR1: $019)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
AMR13
AMR12
AMR11
AMR10
Bit name
AMR10
AMR12
R32/AN2 Mode Selection
0
R32
1
AN2
AMR13
0
R33
1
AN3
0
R30
1
AN0
AMR11
R33/AN3 Mode Selection
R30/AN0 Mode Selection
R31/AN1 Mode Selection
0
R31
1
AN1
Figure 70 A/D Mode Register 1 (AMR1)
A/D Mode register 2 (AMR2: $01A): Three-bit write-only register which is used to set the A/D
conversion period and to select digital or analog ports. Bit 0 of the A/D mode register selects the A/D
conversion period, and bits 1 and 2 select ports R4–R5 as pins AN4–AN11 in 4-pin units (figure 71).
A/D mode register 2 (AMR2: $01A)
Bit
3
2
1
0
Initial value
—
0
0
0
—
W
Read/Write
Bit name
Not used AMR22
W
W
AMR21
AMR20
AMR20
AMR22
R5/AN8–AN11 Pin Selection
Conversion Time
0
34tcyc
1
67tcyc
AMR21
R4/AN4–AN7 Pin Selection
0
R5
0
R4
1
AN8–AN11
1
AN4–AN7
Figure 71 A/D Mode Register 2 (AMR2)
86
HD404369 Series
A/D Channel Register (ACR: $016): Four-bit write-only register which indicates analog input pin
information, as shown in figure 72.
A/D channel register (ACR: $016)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
ACR3
ACR2
ACR1
ACR0
Bit name
ACR3 ACR2 ACR1 ACR0
0
0
0
AN0
1
AN1
0
AN2
1
AN3
0
AN4
1
AN5
0
AN6
1
AN7
0
AN8
1
AN9
1
0
AN10
1
AN11
Don’t
care.
Don’t
care.
0
1
1
0
1
1
0
1
Analog Input Selection
0
Not used
Figure 72 A/D Channel Register (ACR)
87
HD404369 Series
A/D Start Flag (ADSF: $02C, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the
completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is
cleared. Refer to figure 73.
A/D start flag (ADSF: $020, bit 2)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
R/W
R/W
W
R/W
DTON
ADSF
WDON
LSON
LSON
A/D Start Flag (ADSF)
0
A/D conversion completed
1
A/D conversion started
Refer to the description of operating
modes
DTON
WDON
Refer to the description of operating
modes
Refer to the description of timers
Figure 73 A/D Start Flag (ADSF)
IAD Off Flag (IAOF: $021, Bit 2): By setting the IA D off flag to 1, the current flowing through the
resistance ladder can be cut off even while operating in standby or active mode, as shown in figure 74.
IAD off flag (IAOF: $021, bit 2)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
RAME
IAOF
ICEF
ICSF
Bit name
ICSF
IAD Off Flag (IAOF)
0
IAD current flows
1
IAD current is cut off
Refer to the description of timers
ICEF
RAME
Refer to the description of timers
Refer to the description of operating
modes
Figure 74 IAD Off Flag (IAOF)
88
HD404369 Series
A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower
digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion, the
resultant eight-bit data is held in this register until the start of the next conversion (figures 75, 76, and 77).
ADRU: $018
3
2
1
ADRL: $017
0
3
2
1
0
MSB
LSB
Bit 7
Bit 0
Figure 75 A/D Data Registers (ADRU, ADRL)
A/D data register (lower digit) (ADRL: $017)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
R
R
R
R
ADRL3
ADRL2
ADRL1
ADRL0
Bit name
Figure 76 A/D Data Register Lower Digit (ADRL)
A/D data register (upper digit) (ADRU: $018)
Bit
3
2
1
0
Initial value
1
0
0
0
Read/Write
R
R
R
R
ADRU3
ADRU2
Bit name
ADRU1 ADRU0
Figure 77 A/D Data Register Upper Digit (ADRU)
89
HD404369 Series
Notes on Usage
• Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF)
• Do not write to the A/D start flag during A/D conversion
• Data in the A/D data register during A/D conversion is undefined
• Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop, watch, or subactive mode. In addition, to save power while in these
modes, all current flowing through the converter’s resistance ladder is cut off.
• If the power supply for the A/D converter is to be different from VCC, connect a 0.1-µF bypass capacitor
between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly
connected to the VCC pin.)
• The contents of the A/D data register are not guaranteed during A/D conversion. To ensure that the A/D
converter operates stably, do not execute port output instructions during A/D conversion.
• The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a
shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by A/D mode register 1 or 2 (AMR1 or AMR2) as an analog
pin will remain pulled up (figure 78).
HLT
VCC
MIS3
VCC
AMR
A/D mode register value
DCR
PDR
CPU input
Input control signal
A/D input
ACR
A/D channel register value
Figure 78 R Port/Analog Multiplexed Pin Circuit
90
HD404369 Series
Pin Description in PROM Mode
The HD407A4369 is a PROM version of a ZTAT microcomputer. In PROM mode, the MCU stops
operating, thus allowing the user to program the on-chip PROM.
Pin Number
MCU Mode
PROM Mode
DP-64S
FP-64B
FP-64A
Pin
I/O
Pin
I/O
1
59
57
R6 0
I/O
2
60
58
R6 1
I/O
3
61
59
R6 2
I/O
4
62
60
R6 3
I/O
5
63
61
R7 0
I/O
6
64
62
R7 1
I/O
7
1
63
R7 2
I/O
8
2
64
R0 0/SCK
I/O
VCC
9
3
1
R0 1/SI
I/O
VCC
10
4
2
R0 2/SO
I/O
O1
I/O
11
5
3
R0 3/TOC
I/O
O2
I/O
12
6
4
TEST
I
VPP
13
7
5
RESET
I
RESET
14
8
6
OSC 1
I
VCC
15
9
7
OSC 2
O
16
10
8
GND
—
GND
17
11
9
X1
I
GND
18
12
10
X2
O
19
13
11
AVSS
—
GND
20
14
12
R3 0/AN0
I/O
O0
I/O
21
15
13
R3 1/AN1
I/O
O1
I/O
22
16
14
R3 2/AN2
I/O
O2
I/O
23
17
15
R3 3/AN3
I/O
O3
I/O
24
18
16
R4 0/AN4
I/O
O4
I/O
25
19
17
R4 1/AN5
I/O
M0
I
26
20
18
R4 2/AN6
I/O
M1
I
27
21
19
R4 3/AN7
I/O
28
22
20
R5 0/AN8
I/O
29
23
21
R5 1/AN9
I/O
30
24
22
R5 2/AN10
I/O
I
91
HD404369 Series
Pin Number
MCU Mode
PROM Mode
DP-64S
FP-64B
FP-64A
Pin
I/O
Pin
31
25
23
R5 3/AN11
I/O
32
26
24
AVCC
—
VCC
33
27
25
VCC
—
VCC
34
28
26
D0/INT0
I/O
O3
I/O
35
29
27
D1/INT1
I/O
O4
I/O
36
30
28
D2/EVNB
I/O
A1
I
37
31
29
D3/BUZZ
I/O
A2
I
38
32
30
D4/STOPC
I/O
39
33
31
D5
I/O
A3
I
40
34
32
D6
I/O
A4
I
41
35
33
D7
I/O
A9
I
42
36
34
D8
I/O
VCC
43
37
35
D9
I/O
44
38
36
D10
I/O
45
39
37
D11
I/O
46
40
38
D12
I/O
47
41
39
D13
I/O
48
42
40
R8 0
I/O
CE
49
43
41
R8 1
I/O
OE
I
50
44
42
R8 2
I/O
A13
I
51
45
43
R8 3
I/O
A14
I
52
46
44
R9 0
I/O
53
47
45
R9 1
I/O
54
48
46
R9 2
I/O
55
49
47
R9 3
I/O
56
50
48
R1 0
I/O
A5
I
57
51
49
R1 1
I/O
A6
I
58
52
50
R1 2
I/O
A7
I
59
53
51
R1 3
I/O
A8
I
60
54
52
R2 0
I/O
A0
I
61
55
53
R2 1
I/O
A10
I
62
56
54
R2 2
I/O
A11
I
63
57
55
R2 3
I/O
A12
I
64
58
56
RA 1
I
O0
I/O
Notes: 1. I/O: Input/output pin; I: Input pin; O: Output pin
2. O0 to O 4 consist of two pins each. Tie each pair together before using them.
92
I/O
I
HD404369 Series
Programming the Built-In PROM
The MCU’s built-in PROM is programmed in PROM mode. PROM mode is set by pulling RESET, M0,
and M1 low, as shown in figure 79. In PROM mode, the MCU does not operate, but it can be programmed
in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and a
100-to-28-pin socket adapter. Recommended PROM programmers and socket adapters are listed in table
29.
Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into
five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if,
for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer,
a 32-kbyte address space ($0000–$7FFF) must be specified.
CE, OE
Control signals
A14–A0
Address bus
O7
O6
O4–O0
O5
O4–O0
O7–O0
Data bus
M0
M1
RESET
VCC
GND
VPP
HD407A4369
PROM mode pins
VCC
GND
VPP
Socket adapter
PROM programmer
Figure 79 PROM Mode Connections
93
HD404369 Series
Table 29
Recommended PROM Programmers and Socket Adapters
PROM Programmer
Socket Adapter
Manufacture
Model Name
Package
Manufacture
Model Name
DATA I/O corp
121 B
DP-64S
Hitachi
HS4369ESS01H
AVAL corp
PKW-1000
FP-64B
HS4369ESF01H
FP-64A
HS4369ESH01H
DP-64S
Hitachi
HS4369ESS01H
FP-64B
HS4369ESF01H
FP-64A
HS4369ESH01H
Warnings
1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address
$8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.
Note that the plastic-package version cannot be erased and reprogrammed.
2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1
positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure
that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.
3. PROM programmers have two voltages (VPP ): 12.5 V and 21 V. Remember that ZTAT devices
require a VPP of 12.5 V—the 21-V setting will damage them. 12.5 V is the Intel 27256 setting.
Programming and Verification
The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage
to data reliability.
Programming and verification modes are selected as listed in table 30.
For details of PROM programming, refer to the following Notes on PROM Programming section.
Table 30
PROM Mode Selection
Pin
Mode
CE
OE
VPP
O0–O4
Programming
Low
High
VPP
Data input
Verification
High
Low
VPP
Data output
Programming inhibited
High
High
VPP
High impedance
94
HD404369 Series
Addressing Modes
RAM Addressing Modes
The MCU has three RAM addressing modes, as shown in figure 80 and described below.
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from
$040 to $04F, are accessed with the LAMR and XMRA instructions.
W register
W1 W0
RAM address
X register
X3
X2
X1
Y register
X0
Y3
Y2
Y1
Y0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register Direct Addressing
1st word of Instruction
Opcode
2nd word of Instruction
d
RAM address
9
d8
d7
d6
d5
d4
d3
d2
d1
d0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct Addressing
Instruction
Opcode
0
RAM address
0
0
1
m3 m2
0
m1
m0
0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory Register Addressing
Figure 80 RAM Addressing Modes
95
HD404369 Series
ROM Addressing Modes and the P Instruction
The MCU has four ROM addressing modes, as shown in figure 81 and described below.
Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC 13–PC0) with 14-bit immediate data.
Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction
is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 83. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.
Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.
Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000–
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight highorder bits (PC13–PC6).
Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.
P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 82. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If
both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.
The P instruction has no effect on the program counter.
96
HD404369 Series
1st word of instruction
[JMPL]
[BRL]
[CALL]
Opcode
p3
Program counter
2nd word of instruction
p2
p1
p0
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Direct Addressing
Instruction
[BR]
Program counter
Opcode
b7
b6
b5
b4
b3
b2
b1
b0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Current Page Addressing
Instruction
[CAL]
0
Program counter
0
0
0
d5
Opcode
0
0
0
d4
d3
d2
d1
d0
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Zero Page Addressing
Instruction
[TBR]
Opcode
p3
p2
p1
p0
B register
B3
0
Program counter
B2 B1
Accumulator
B0
A3
A2
A1
A0
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table Data Addressing
Figure 81 ROM Addressing Modes
97
HD404369 Series
Instruction
[P]
Opcode
p3
p2
p1
p0
B register
B3
0
B2 B1
Accumulator
B0
A3
A2
A1
A0
0
Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0
Address Designation
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
ROM data
B3
B2
B1
B0
A3 A
A1
A
0
If RO 8 = 1
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
R23 R22 R21 R20 R13 R12 R11 R10
Pattern Output
Figure 82 P Instruction
98
2
If RO 9 = 1
HD404369 Series
256 (n – 1) + 255
BR
AAA
256n
AAA
BBB
256n + 254
256n + 255
256 (n + 1)
NOP
BR
BR
BBB
AAA
NOP
Figure 83 Branching when the Branch Destination is on a Page Boundary
99
HD404369 Series
Instruction Set
The HD404369 Series has 101 instructions, classified into the following 10 groups:
• Immediate instructions
• Register-to-register instructions
• RAM address instructions
• RAM register instructions
• Arithmetic instructions
• Compare instructions
• RAM bit manipulation instructions
• ROM address instructions
• Input/output instructions
• Control instructions
100
HD404369 Series
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Notes
Supply voltage
VCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +14.0
V
1
Pin voltage
VT
–0.3 to VCC + 0.3 V
2
–0.3 to +15.0
V
3
Total permissible input current
∑IO
105
mA
4
Total permissible output current
–∑IO
50
mA
5
Maximum input current
IO
4
mA
6, 7
30
mA
6, 8
7, 9
Maximum output current
–I O
4
mA
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.
1. Applies to pin TEST (VPP ) of HD407A4369.
2. Applies to all standard voltage pins.
3. Applies to intermediate-voltage pins.
4. The total permissible input current is the total of input currents simultaneously flowing in from all
the I/O pins to GND.
5. The total permissible output current is the total of output currents simultaneously flowing out from
VCC to all I/O pins.
6. The maximum input current is the maximum current flowing from each I/O pin to GND.
7. Applies to ports D0 to D13 , R0, R3 to R9.
8. Applies to ports R1 and R2.
9. The maximum output current is the maximum current flowing from VCC to each I/O pin
101
HD404369 Series
Electrical Characteristics
DC Characteristics (HD407A4369: VC C = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C;
HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/HD40A4369:V
CC = 2.7 to 6.0 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item
Symbol
Pins
Min
Typ
Max
Unit
Input high
voltage
VIH
RESET, SCK,
0.8V CC
—
VCC + 0.3
V
SI
0.7 VCC
—
VCC + 0.3
V
OSC 1
VCC – 0.5 —
VCC + 0.3
V
RESET, SCK,
–0.3
—
0.2V CC
V
SI
–0.3
—
0.3V CC
V
OSC 1
–0.3
—
0.5
V
Test Condition Notes
INT0, INT1,
STOPC, EVNB
Input low voltage VIL
INT0, INT1,
STOPC, EVNB
Output high
voltage
VOH
SCK, SO, TOC
VCC – 0.5 —
—
V
–I OH = 0.5 mA
Output low
voltage
VOL
SCK, SO, TOC
—
—
0.4
V
I OL = 0.4 mA
I/O leakage
current
|IIL|
RESET, SCK,
—
—
1
µA
Vin = 0 V to VCC
1
—
—
5.0
mA
VCC = 5 V,
2
SI, SO, TOC,
OSC 1, INT0,
INT1, STOPC,
EVNB
Current
dissipation in
active mode
I CC
Current
dissipation in
standby mode
I SBY
Current
dissipation in
subactive mode
I SUB
Current
dissipation in
watch mode
I WTC
102
VCC
f OSC = 4 MHz
VCC
—
—
2.0
mA
VCC = 5 V,
3
f OSC = 4 MHz
VCC
—
—
100
µA
VCC = 5 V,
4
32 kHz oscillator
VCC
—
—
20
µA
VCC = 5 V,
32 kHz oscillator
4
HD404369 Series
Item
Symbol
Pins
Min
Typ
Max
Unit
Test Condition Notes
Current
dissipation in
stop mode
I STOP
VCC
—
—
10
µA
VCC = 5V,
Stop mode
VSTOP
retaining voltage
4
X1 = GND,
X2 = Open
VCC
2
—
—
V
Notes: 1. Excludes current flowing through pull-up MOS and output buffers.
2. I CC is the source current when no I/O current is flowing while the MCU is in reset state.
Test conditions:
MCU: Reset
Pins:
RESET, TEST at GND
3. I SBY is the source current when no I/O current is flowing while the MCU timer is operating.
Test conditions:
MCU: I/O reset
Standby mode
Pins:
RESET at V CC
TEST at GND
D0–D 13 , R0–R9, RA 1 at V CC
4. This is the source current when no I/O current is flowing.
Test conditions:
Pins:
RESET at V CC
TEST at GND
D0–D 13 , R0–R9, RA 1 at V CC
103
HD404369 Series
I/O Characteristics for Standard Pins (HD407A4369: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to
+75°C; HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/HD40A
4369: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item
Symbol
Pins
Min
Typ
Max
Unit
Test Condition Note
Input high voltage
VIH
D0–D 13 ,
0.7V CC
—
VCC + 0.3 V
–0.3
—
0.3V CC
V
VCC –
0.5
—
—
V
–I OH = 0.5 mA
R0, R3–R9
D0–D 13 ,
—
—
0.4
V
I OL = 1.6 mA
—
—
1
µA
Vin = 0 V to VCC
30
150
300
µA
VCC = 5 V,
R0, R3–R9, RA1
Input low voltage
VIL
D0–D 13 ,
R0, R3–R9, RA1
Output high voltage VOH
Output low voltage
VOL
D0–D 13 ,
R0, R3–R9
Input leakage
current
|IIL|
D0–D 13 ,
R0, R3–R9, RA1
Pull-up MOS current –I PU
D0–D 13 ,
Vin = 0 V
R0, R3–R9
Note:
1
1. Output buffer current is excluded.
I/O Characteristics for Intermediate-Voltage Pins (HD407A4369: V CC = 2.7 to 5.5 V, GND = 0 V, Ta =
–20 to +75°C; HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/
HD40A4369: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item
Symbol
Pins
Min
Typ
Max
Unit
Input high voltage
VIH
R1, R2
0.7V CC
—
12
V
Input low voltage
VIL
R1, R2
–0.3
—
0.3V CC
V
Output high voltage VOH
R1, R2
11.5
—
—
V
500 kΩ at 12 V
Output low voltage
R1, R2
—
—
0.4
V
I OL = 0.4 mA
—
—
2.0
V
I OL = 15 mA,
VOL
Test Condition
Note
VCC = 4.5 to 5.5 V
I/O leakage current
Note:
104
|IIL|
R1, R2
1. Excludes output buffer current.
—
—
20
µA
Vin = 0 V to 12 V
1
HD404369 Series
A/D Converter Characteristics (HD407A4369: VCC = 2.7 to 5.5 V, GND = 0 V, T a = –20 to
+75°C;HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/HD40A
4369: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item
Symbol
Pins
Min
Typ
Max
Analog supply
voltage
AVCC
AVCC
VCC –
0.3
VCC
VCC + 0.3 V
AN 0–AN 11
AVSS
—
AVCC
V
—
—
200
µA
—
—
30
pF
Resolution
8
8
8
Bit
Number of input
channels
0
—
12
Chan
nel
Absolute accuracy
—
—
±2.0
LSB
Conversion time
34
—
67
t cyc
1
—
—
MΩ
Analog input voltage AVin
Current flowing
between AV CC and
AVSS
I AD
Analog input
capacitance
CA in
Input impedance
Note:
AN 0–AN 11
AN 0–AN 11
Unit
Test Condition
Notes
1
VCC = AVCC = 5.0 V
1. Connect this to V CC if the A/D converter is not used.
105
HD404369 Series
Standard fOSC = 5 MHz Version AC Characteristics (HD404364/HD404368/HD4043612/HD404369:
VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20 to +75°C)
Item
Symbol
Pins
Min
Typ
Max
Unit
Test Condition
Notes
Clock oscillation
frequency
f OSC
OSC 1, OSC 2
0.4
4
5.0
MHz
1/4 system clock
division ratio
1
X1, X2
—
32.768 —
kHz
t cyc
0.8
1
10
µs
t subcyc
—
244.14 —
µs
32-kHz oscillator,
1/8 system clock
division ratio
—
122.07 —
µs
32-kHz oscillator,
1/4 system clock
division ratio
Instruction cycle
time
1
Oscillation
t RC
stabilization time
(ceramic oscillator)
OSC 1, OSC 2
—
—
7.5
ms
2
Oscillation
stabilization time
(crystal oscillator)
OSC 1, OSC 2
—
—
40
ms
2
X1, X2
—
—
2
s
2
External clock high t CPH
width
OSC 1
80
—
—
ns
3
External clock low t CPL
width
OSC 1
80
—
—
ns
3
External clock rise t CPr
time
OSC 1
—
—
20
ns
3
External clock fall
time
t CPf
OSC 1
—
—
20
ns
3
INT0, INT1, EVNB
high widths
t IH
INT0, INT1, EVNB
2
—
—
t cyc /
4
INT0, INT1, EVNB
low widths
t IL
RESET low width
t RSTL
RESET
2
—
—
t cyc
5
STOPC low width
t STPL
STOPC
1
—
—
t RC
6
RESET rise time
t RSTr
RESET
—
—
20
ms
5
STOPC rise time
t STPr
STOPC
—
—
20
ms
6
Input capacitance
Cin
All input pins
—
except R1 and R2
—
15
pF
R1, R2
—
t RC
t subcyc
INT0, INT1, EVNB
2
—
—
t cyc /
4
t subcyc
—
f = 1 MHz,
Vin = 0 V
30
pF
f = 1 MHz,
Vin = 0 V
106
HD404369 Series
Notes: 1. When using the subsystem oscillator (32.768 kHz), one of the following relationships for f OSC
must be applied.
0.4 MHz ≤ fOSC ≤ 1.0 MHz or 1.6 MHz ≤ fOSC ≤ 5.0 MHz
The operating range for fOSC can be set with bit 1 of system clock selection register 1 (SSR1:
$027).
2. The oscillation stabilization time is the period required for the oscillator to stabilize in the
following situations:
a. After V CC reaches 2.7 V at power-on.
b. After RESET input goes low when stop mode is cancelled.
c. After STOPC input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET
or STOPC must be input for at least a duration of t RC.
When using a crystal or ceramic oscillator, consult with the manufacturer to determine what
stabilization time is required, since it will depend on the circuit constants and stray capacitance.
3. Refer to figure 84.
4. Refer to figure 85.
5. Refer to figure 86.
6. Refer to figure 87.
107
HD404369 Series
High-Speed f OSC = 8.5 MHz Version AC Characteristics (HD407A4369: VCC = 2.7 to 5.5 V, GND = 0
V, Ta = –20 to +75°C; HD40A4364/HD40A4368/HD40A43612/HD40A4369: V CC = 2.7 to 6.0 V, GND
= 0 V, T a = –20 to +75°C)
Item
Symbol
Pins
Min
Typ
Max
Unit
Test Condition
Notes
Clock oscillation
frequency
f OSC
OSC 1, OSC 2
0.4
4
5.0
MHz
1/4 system clock
division ratio
1
0.4
4
8.5
MHz
—
32.768 —
kHz
0.8
1
10
µs
1
0.47
1
10
µs
2, 3
—
244.14 —
µs
32-kHz oscillator,
1/8 system clock
division ratio
—
122.07 —
µs
32-kHz oscillator,
1/4 system clock
division ratio
X1, X2
Instruction cycle
time
t cyc
t subcyc
2, 3
Oscillation
t RC
stabilization time
(ceramic oscillator)
OSC 1, OSC 2
—
—
7.5
ms
4
Oscillation
t RC
stabilization time
(ceramic oscillator)
OSC 1, OSC 2
—
—
40
ms
4
X1, X2
—
—
2
s
4
OSC 1
80
—
—
ns
5
47
—
—
ns
3, 5
80
—
—
ns
5
47
—
—
ns
3, 5
—
—
20
ns
5
—
—
15
ns
3, 5
—
—
20
ns
5
—
—
15
ns
3, 5
2
—
—
t cyc /
6
External clock high t CPH
width
External clock low t CPL
width
External clock rise t CPr
time
External clock fall
time
t CPf
INT0, INT1, EVNB
high widths
t IH
INT0, INT1, EVNB
low widths
t IL
108
OSC 1
OSC 1
OSC 1
INT0, INT1,
EVNB
INT0, INT1,
EVNB
t subcyc
2
—
—
t cyc /
t subcyc
6
HD404369 Series
Item
Symbol
Pins
Min
Typ
Max
Unit
Test Condition
Notes
RESET low width
t RSTL
RESET
2
—
—
t cyc
7
STOPC low width
t STPL
STOPC
1
—
—
t RC
8
RESET rise time
t RSTr
RESET
—
—
20
ms
7
STOPC rise time
t STPr
STOPC
—
—
20
ms
8
Input capacitance
Cin
All input pins except —
TEST, R1 and R2
—
15
pF
f = 1 MHz, Vin = 0 V
TEST
—
—
15
pF
f = 1 MHz, Vin = 0 V 9
TEST
—
—
180
pF
f = 1 MHz, Vin = 0 V 10
R1, R2
—
—
30
pF
f = 1 MHz, Vin = 0 V
Notes: 1. When using the subsystem oscillator (32.768 kHz), one of the following relationships for f OSC
must be applied.
0.4 MHz ≤ fOSC ≤ 1.0 MHz or 1.6 MHz ≤ fOSC ≤ 5.0 MHz
The operating range for fOSC can be set with bit 1 of system clock selection register 1 (SSR1:
$027).
2. When using the subsystem oscillator (32.768 kHz), one of the following relationships for f OSC
must be applied.
0.4 MHz ≤ f OSC ≤ 1.0 MHz or 1.6 MHz ≤ f OSC ≤ 8.5 MHz
The operating range for fOSC can be set with bit 1 of system clock selection register 1 (SSR1:
$027).
3. VCC = 4.5 to 5.5V
4. The oscillation stabilization time is the period required for the oscillator to stabilize in the
following situations:
a. After V CC reaches 2.7 V at power-on.
b. After RESET input goes low when stop mode is cancelled.
c. After STOPC input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET
or STOPC must be input for at least a duration of t RC.
When using a crystal or ceramic oscillator, consult with the manufacturer to determine what
stabilization time is required, since it will depend on the circuit constants and stray capacitance.
5. Refer to figure 84.
6. Refer to figure 85.
7. Refer to figure 86.
8. Refer to figure 87.
9. Applies to the HD40A4364, HD40A4368, HD40A43612, and HD40A4369.
10. Applies to the HD407A4369.
109
HD404369 Series
Serial Interface Timing Characteristics (HD407A4369: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to
+75°C; HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/HD40A
4369: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
During Transmit Clock Output
Item
Symbol
Pins
Min
Typ
Max
Unit
Test Condition
Note
Transmit clock cycle
time
t Scyc
SCK
1
—
—
t cyc
Load shown in figure 89
1
Transmit clock high
width
t SCKH
SCK
0.4
—
—
t Scyc
Load shown in figure 89
1
Transmit clock low
width
t SCKL
SCK
0.4
—
—
t Scyc
Load shown in figure 89
1
Transmit clock rise
time
t SCKr
SCK
—
—
80
ns
Load shown in figure 89
1
Transmit clock fall
time
t SCKf
SCK
—
—
80
ns
Load shown in figure 89
1
Serial output data
delay time
t DSO
SO
—
—
300
ns
Load shown in figure 89
1
Serial input data setup t SSI
time
SI
100
—
—
ns
1
Serial input data hold
time
SI
200
—
—
ns
1
t HSI
During Transmit Clock Input
Item
Symbol
Pins
Min
Typ
Max
Unit
Transmit clock cycle
time
t Scyc
SCK
1
—
—
t cyc
1
Transmit clock high
width
t SCKH
SCK
0.4
—
—
t Scyc
1
Transmit clock low
width
t SCKL
SCK
0.4
—
—
t Scyc
1
Transmit clock rise
time
t SCKr
SCK
—
—
80
ns
1
Transmit clock fall
time
t SCKf
SCK
—
—
80
ns
1
Serial output data
delay time
t DSO
SO
—
—
300
ns
Serial input data setup t SSI
time
SI
100
—
—
ns
1
Serial input data hold
time
SI
200
—
—
ns
1
Note:
110
t HSI
1. Refer to figure 88.
Test Condition
Load shown in figure 89
Note
1
HD404369 Series
OSC1
1/fCP
VCC – 0.5 V
tCPL
tCPH
0.5 V
tCPr
tCPf
Figure 84 External Clock Timing
INT0, INT1, EVNB
0.8VCC
tIL
tIH
0.2VCC
Figure 85 Interrupt Timing
RESET
0.8VCC
tRSTL
0.2VCC
tRSTr
Figure 86 RESET Timing
STOPC
0.8VCC
tSTPL
0.2VCC
tSTPr
Figure 87 STOPC Timing
111
HD404369 Series
t Scyc
t SCKf
SCK
VCC – 0.5 V (0.8VCC )*
0.4 V (0.2VCC)*
t SCKr
t SCKL
t SCKH
t DSO
VCC – 0.5 V
0.4 V
SO
t SSI
t HSI
0.7V CC
0.3VCC
SI
Note: * VCC – 0.5 V and 0.4 V are the threshold voltages for transmit clock output, and
0.8VCC and 0.2VCC are the threshold voltages for transmit clock input.
Figure 88 Serial Interface Timing
VCC
RL = 2.6 kΩ
Test
point
C=
30 pF
R=
12 kΩ
Hitachi
1S2074
or equivalent
Figure 89 Timing Load Circuit
112
HD404369 Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out.
On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404364,
HD40A4364, HD404368, HD40A4368, HD4043612 and HD40A43612 as a 16-kword version
(HD404369, HD40A4369). The 16-kword data sizes are required to change ROM data to mask
manufacturing data since the program used is for a 16-kword version.
This limitation applies when using an EPROM or a data base.
ROM 4-kword version:
HD404364, HD40A4364
$0000
ROM 8-kword version:
HD404368, HD40A4368
$000F
$0010
Zero-page
subroutine
(64 words)
$003F
$0040
$000F
$0010
Zero-page
subroutine
(64 words)
$000F
$0010
Zero-page
subroutine
(64 words)
$003F
$0040
$003F
$0040
$0FFF
$1000
Vector address
Vector address
Pattern & program
(4,096 words)
Pattern & program
(12,288 words)
Pattern & program
(8,192 words)
$2FFF
$3000
$1FFF
$2000
Not used
$3FFF
$0000
$0000
Vector address
ROM 12-kword version:
HD4043612, HD40A43612
Not used
$3FFF
Not used
$3FFF
Fill this area with 1s
113
HD404369 Series
HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/
HD40A43612/HD40A4369 Option List
Please check off the appropriate applications and enter the necessary information.
1. ROM size
5 MHz operation
HD404364
4-kword
8.5 MHz operation HD40A4364
5 MHz operation
HD404368
Customer
8-kword
8.5 MHz operation HD40A4368
5 MHz operation
HD4043612
Department
Name
12-kword
8.5 MHz operation HD40A43612
5 MHz operation
Date of order
ROM code name
LSI number
16-kword
HD404369
8.5 MHz operation HD40A4369
2. Optional Functions
*
With 32-kHz CPU operation, with time base for clock
*
Without 32-kHz CPU operation, with time base for clock
Without 32-kHz CPU operation, without time base
Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2).
3. ROM Code Media
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
4. System Oscillator (OSC1, OSC2)
Ceramic oscillator
f=
MHz
Crystal oscillator
f=
MHz
External clock
f=
MHz
5. Stop mode
6. Package
Used
DP-64S
Not used
FP-64B
FP-64A
114
HD404369 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
115
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