REJ09B0254-0500
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32
SH7727 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH RISC engine Family/SH7700 Series
SH7727
Rev. 5.00
Revision Date: Dec 12, 2005
HD6417727
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
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diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
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Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
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7. If these products or technologies are subject to the Japanese export control restrictions, they must
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
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contained therein.
Rev. 5.00 Dec 12, 2005 page ii of lxxii
General Precautions on the Handling of Products
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are not connected to any of the internal circuitry; they are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined. The states of internal
circuits are undefined until full power is supplied throughout the chip and a low level is
input on the reset pin. During the period where the states are undefined, the register
settings and the output state of each pin are also undefined. Design your system so that it
does not malfunction because of processing while it is in this undefined state. For those
products which have a reset function, reset the LSI immediately after the power supply has
been turned on.
4. Prohibition of access to undefined or reserved address
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these address. Do not access these registers: the system’s
operation is not guaranteed if they are accessed.
Rev. 5.00 Dec 12, 2005 page iii of lxxii
Rev. 5.00 Dec 12, 2005 page iv of lxxii
Preface
The SH7727 microprocessor incorporates the 32-bit SH-3 CPU and is also equipped with
peripheral functions necessary for configuring a user system.
The SH7727 is built in with a variety of peripheral functions such as cache memory, memory
management unit (MMU), interrupt controller, timers, three serial communication interfaces (SCI,
SCIF, SIOF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and
AFE interface. The SH7727 can be used in a variety of applications that demand a high-speed
microcomputer with low power consumption.
The descriptions in this manual are based on the SH7727C. For details on using versions previous
to the SH7727B please refer to Using Versions Previous to the SH7727B at the end of the manual.
Note that the version is the SH7727C if “C” is engraved on the chip and the version is the
SH7727B if “B” is engraved. If there is no such indication the product is a version previous to the
SH7727B. (See Appendix E.)
Target Readers: This manual is designed for use by people who design application systems using
the SH7727.
To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is
required.
Purpose: This manual provides the information of the hardware functions and electrical
characteristics of the SH7727.
The SH-3, SH-3E, SH3-DSP Programming Manual contains detailed information of executable
instructions. Please read the Programming Manual together with this manual.
How to Use the Book:
• To understand general functions
→ Read the manual from the beginning.
The manual explains the CPU, system control functions, peripheral functions and electrical
characteristics in that order.
• To understanding CPU functions
→ Refer to the separate SH-3, SH-3E, SH3-DSP Programming Manual.
Explanatory Note: Bit sequence: upper bit at left, and lower bit at right
List of Related Documents: The latest documents are available on our Web site. Please make
sure that you have the latest version. (http://www.renesas.com/)
Rev. 5.00 Dec 12, 2005 page v of lxxii
• User manuals for SH7727
Name of Document
Document No.
SH7727 Hardware Manual
This manual
SH-3, SH-3E, SH3-DSP Programming Manual
ADE-602-096B
• User manuals for development tools
Name of Document
Document No.
SuperH™ RISC engine C/C++ Compiler, Assembler, Optimizing
Linkage Editor Compiler Package V.9.00 User’s Manual
REJ10B0152-0101
SuperH™ RISC engine High-Performance Embedded Workshop 3
User’s Manual
REJ10B0025-0200H
SuperH RISC engine High-Performance Embedded Workshop 3
Tutorial
REJ10B0023-0200H
• Application Note
Name of Document
Document No.
SuperH RISC engine C/C++ Compiler Package Application Note
REJ05B0463-0200
Rev. 5.00 Dec 12, 2005 page vi of lxxii
Revisions and Additions
Page
Previous Version
Revised Version
5 to 7 Table 1.1 SH7727 Features
Item
Features
Item
Timer
(TMU, CMT)
• 3-channel auto-reload-type 32-bit timer
Timer (TMU)
• 1-channel 16-bit compare match timer
• Choice of six counter input clocks
Features
• Choice of six counter input clocks
• Maximum resolution: 2 MHz
• 3-channel auto-reload-type 32-bit timer
• Maximum resolution: 2 MHz
Item
Features
Item
Features
Serial communication interface
(SCIF)
• 16-byte FIFO for transmission/reception
Serial communication interface
(SCIF)
• 16-byte FIFO for transmission/reception
• DMA can be transferred
• Hardware flow control
• DMA can be transferred
• On-chip modem control function
Direct memory
• 4 channels
access controller • Burst mode and cycle-steal mode
(DMAC)
• External request operating mode
Direct memory
• 4 channels
access controller • Burst mode and cycle-steal mode
(DMAC)
• External request operating mode
Item
Features
Item
Features
LCD controller
(LCDC)
• From 16 x 1 to 1024 x 1024 pixels can be supported
LCD controller
(LCDC)
• From 16 x 1 to 1024 x 1024 pixels can be supported
• 1-channel 16-bit compare match timer
• 1/2/4/6/8/16 bpp (bit per pixel) with 18bit color pallet
• 1/2/4/6 bpp (bit per pixel) gray scale
• 8-bit Frame rate controller
• 8-bit Frame rate controller
• TFT/DSTN/STN
• TFT/DSTN/STN
• Signal polarity setting function
• Signal polarity setting function
• Hardware panel rotation
• Hardware panel rotation
• Power control function
• Power control function
• Selectable clock source (LCLK or Bclk or Pclk)
A/D converter
(ADC)
• 4/8/15/16 bpp (bit per pixel) color modes
• 1/2/4 bpp (bit per pixel) gray scale
• Selectable clock source (LCLK, bus clock (Bφ), or peripheral clock (Pφ))
• 10 bits ± 4 LSB, 6 channels
A/D converter
(ADC)
• Conversion time: 10 µs
• Input range: 0–Vcc (max. 3.6 V)
Product lineup
Power Supply
Voltage
Abb.
I/O
Internal
SH7727
3.3 ±
0.3 V
1.7 to
2.05 V
• 10 bits ± 4 LSB, 6 channels
• Conversion time: 15 µs
• Input range: 0–Vcc (max. 3.6 V)
Product lineup
Power Supply
Voltage
Operating
Frequency
Model Name
Package
SH7727
I/O
160 MHz
HD6417727F160B
240-pin plastic HQFP
(FP-240B)
160 MHz
products
3.0 V to 1.70 V to 160 MHz
3.6 V
2.05 V
Internal
Operating
Frequency
HD6417727BP160B 240-pin CSP
(BP-240A)
3.1 ±
0.5 V
1.6 to
2.05 V
100 MHz
HD6417727F100B
240-pin plastic HQFP
(FP-240B)
HD6417727BP100B 240-pin CSP
(BP-240A)
11 to
19
Table 1.2 SH7727 Pin Function
167
7.1.4 Register Configuration
Pin No.
(FP-240B)
Pin No.
(BP-240A)
The INTC has 12 registers listed in table
7.2.
Model Name
Package
HD6417727F160C
240-pin plastic HQFP
(PRQP0240KC-B)
HD6417727BP160C 240-pin CSP
(PLBG0240JA-A)
100 MHz
products
2.6 V to 1.60 V to 100 MHz
3.6 V
2.05 V
HD6417727F100C
240-pin plastic HQFP
(PRQP0240KC-B)
HD6417727BP100C 240-pin CSP
(PLBG0240JA-A)
Pin No.
Pin No.
(PRQP0240KC-B) (PLBG0240JA-A)
The INTC has 17 registers listed in table
7.2.
Rev. 5.00 Dec 12, 2005 page vii of lxxii
Page
169
Previous Version
Revised Version
7.2.2 IRQ Interrupt
IRQ interrupts are input by priority from pins
IRQ0 to IRQ5 with a level or an edge. The
priority level can be set by priority setting
registers C, D (IPRC, IPRD) in a range from
levels 0 to 15.
IRQ interrupts are input by priority from pins
IRQ0 to IRQ5 with a level or an edge. The
priority level can be set by priority setting
registers C, D (IPRC, IPRD) in a range from
levels 0 to 15.
When using edge-sensing for IRQ
interrupts, clear the interrupt source by
having software read 1 from the
corresponding bit in IRR0, then write 0 to
the bit.
When using edge sensing for IRQ
interrupts, do the following to clear IR0.
To clear bits IRQ5R to IRQ0R to 0, read
from IRR0 before writing. After confirming
that the bits to be cleared to 0 are set to 1,
write 0 to them. In this case write 0 only to
the bits to be cleared; write 1 to the other
bits. The values of the bits to which 1 is
written do not change.
When level sensing is used for IRQ
interrupts, bits IRQ5R to IRQ0R indicate
whether or not an interrupt request has
been input. They can be set and cleared by
the values input to pins IRQ5R to IRQ0R
alone.
175
Table 7.4 Interrupt Exception Handling
Sources and Priority (IRQ Mode)
Interrupt Source
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
IPR (Bit
(Initial Value) Numbers)
Priority
within IPR
Setting
Default
Priority
Unit
TMU1
TUNI1
H'420 (H'420)
0–15 (0)
IPRA (11–8)
—
TMU2
TUNI2
H'440 (H'440)
0–15 (0)
IPRA (7–4)
High
TICPI2
H'460 (H'460)
Low
RTC
SCI0
177
ATI
H'480 (H'480)
PRI
H'4A0 (H'4A0)
CUI
H'4C0 (H'4C0)
ERI
H'4E0 (H'4E0)
RXI
H'500 (H'500)
TXI
H'520 (H'520)
TEI
H'540 (H'540)
0–15 (0)
IPRA (3–0)
High
0–15 (0)
IPRB (3–0)
0–15 (0)
IPRA (11–8)
—
0–15 (0)
IPRA (7–4)
—
0–15 (0)
IPRA (3–0)
High
0–15 (0)
IPRB (7–4)
Interrupt Source
TMU1
TUNI1
H'420 (H'420)
TMU2
TUNI2
H'440 (H'440)
RTC
ATI
H'480 (H'480)
CUI
H'4C0 (H'4C0)
SCI0
ERI
H'4E0 (H'4E0)
RXI
H'500 (H'500)
TXI
H'520 (H'520)
TEI
H'540 (H'540)
PRI
High
Low
Priority
within IPR
Setting
Default
Unit
Priority
Interrupt
Priority
(Initial Value)
High
Low
IPR (Bit
Numbers)
INTEVT Code
(INTEVT2 Code)
High
H'4A0 (H'4A0)
Low
High
Low
Low
Low
Table 7.5 Interrupt Exception Handling
Sources and Priority (IRL Mode)
Interrupt Source
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
(Initial
IPR (Bit
Numbers)
Value)
IPRE (3–0)
—
ADC
ADI
H'200–3C0* (H'980)
LCDC
LCDCI
H'200–3C0* (H'9A0)
0–15 (0)
IPRF (11–8)
—
TMU1
TUNI1
H'420 (H'420)
0–15 (0)
IPRA (11–8)
—
TUNI2
H'440 (H'440)
0–15 (0)
IPRA (7–4)
High
TICPI2
H'460 (H'460)
TMU2
0–15 (0)
Priority
within IPR
Setting
Default
Priority
Unit
Rev. 5.00 Dec 12, 2005 page viii of lxxii
Low
High
Low
Interrupt Source
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
(Initial
IPR (Bit
Value)
Numbers)
IPRE (3–0)
Priority
within IPR
Setting
Default
Unit
Priority
—
ADC
ADI
H'200–3C0* (H'980)
0–15 (0)
LCDC
LCDCI
H'200–3C0* (H'9A0)
0–15 (0)
IPRF (11–8)
—
TMU1
TUNI1
H'420 (H'420)
0–15 (0)
IPRA (11–8)
—
TMU2
TUNI2
H'440 (H'440)
0–15 (0)
IPRA (7–4)
—
High
Low
Page
Previous Version
188
7.3.7 Interrupt Request Register 0 (IRR0)
The IRR0 is an 8-bit register that indicates
interrupt requests from external input pins
IRQ0 to IRQ5 and PINT0 to PINT15. This
register is initialized to H'00 at power-on
reset or manual reset, but is not initialized
in standby mode.
Revised Version
When using edge sensing for IRQ
interrupts, do the following to clear IR0.
To clear bits IRQ5R to IRQ0R to 0, read
from IRR0 before writing. After confirming
that the bits to be cleared to 0 are set to 1,
write 0 to them. In this case write 0 only to
the bits to be cleared; write 1 to the other
bits. The values of the bits to which 1 is
written do not change.
When level sensing is used for IRQ
interrupts, bits IRQ5R to IRQ0R indicate
whether or not an interrupt request has
been input. They can be set and cleared by
the values input to pins IRQ5R to IRQ0R
alone.
198
Figure 7.3 Interrupt Operation Flowchart
Yes
No
Yes
NMI?
No
Yes
NMI?
Yes
Yes
Yes
IRQOUT = low
Set interrupt cause in
INTEVT, INTEVT2
199
Set interrupt cause in
INTEVT, INTEVT2
7.4.2 Multiple Interrupts
When these procedures are followed in
order, an interrupt of higher priority than the
one being handled can be accepted after
clearing BL in step 4. Figure 7.3 shows a
sample interrupt operation flowchart.
When these procedures are followed in
order, an interrupt of higher priority than the
one being handled can be accepted after
clearing BL in step 4.
Rev. 5.00 Dec 12, 2005 page ix of lxxii
Page
234
Previous Version
Revised Version
Table 9.1 Power-Down Modes
Mode
Transition
Conditions
Mode
Transition
Conditions
Sleep
mode
Execute
SLEEP
instruction
with STBY bit
cleared to 0
in STBCR
Sleep
mode
Execute
SLEEP
instruction
with STBY bit
cleared to 0
in STBCR *7
Module
standby
function
Set MSTP bit
of STBCR
to 1
Module
standby
function
Set MSTP bit
of STBCR
to 1*6
Note 6, 7, added
Section 10.1.2 “Clock Abbreviation” deleted
259
Figure 10.1 Block Diagram of Clock Pulse
Generator
Clock pulse generator
Clock pulse generator
CAP1
CKIO2
PLL circuit 1
(× 1, 2, 3, 4, 6)
CKIO
Cycle = Bcyc
CAP2
XTAL
Crystal
oscillator
PLL circuit 2
(× 1, 4)
Divider 1
×1
× 1/2
× 1/3
×1/4
Divider 2
×1
× 1/2
× 1/3
× 1/4
× 1/6
CAP1
CKIO2
Internal
clock (Iφ)
Cycle = Icyc
CKIO
Cycle = Bcyc
Peripheral
clock (Pφ)
Cycle = Pcyc
EXTAL
CAP2
XTAL
Crystal
oscillator
PLL circuit 2
(× 1, 4)
Divider 1
×1
× 1/2
× 1/3
×1/4
Divider 2
×1
× 1/2
× 1/3
× 1/4
× 1/6
Internal
clock (Iφ)
Cycle = Icyc
Peripheral
clock (Pφ)
Cycle = Pcyc
EXTAL
Bus clock (Pφ)
Cycle = Bcyc
260
PLL circuit 1
(× 1, 2, 3, 4, 6)
Bus clock (Pφ)
Cycle = Bcyc
10.2.1 CPG Block Diagram
1. PLL Circuit 1
PLL circuit 1 doubles, triples, quadruples,
sextuples, or leaves unchanged the input
clock frequency from the CKIO terminal. ...
Rev. 5.00 Dec 12, 2005 page x of lxxii
PLL circuit 1 doubles, triples, quadruples
sextuples, or leaves unchanged the input
clock frequency from the CKIO pin or PLL
circuit 2. …
Page
Previous Version
265,
266
Table 10.4 Available Combination of Clock
Mode and FRQCR Values
Revised Version
Cautions:
Cautions:
1. The frequency ranges of the input clock and crystal
oscillator should be set within the specified frequency
range based on the clock rate in table 10.4, and section
32.3, AC Characteristics.
1. The frequency ranges of the input clock and crystal
oscillator should be set within the specified frequency
range based on the clock rate in table 10.4, and section
32.3, AC Characteristics.
2. The input to divider 1 becomes the output of:
2. The input to divider 1 becomes the output of PLL
circuit 1 when PLL circuit 1 is on.
• PLL circuit 1 when PLL circuit 1 is on.
• PLL circuit 2 when PLL circuit 1 is off and PLL circuit 2
is on.
3. The input of divider 2 becomes the output of:
3. The input of divider 2 becomes the output of:
4. The frequency of the internal clock (Iφ) becomes:
• PLL circuit 1
• The product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1, and the
division ratio of divider 1 when PLL circuit 1 is on.
4. The frequency of the internal clock (Iφ) becomes:
• The product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1, and the
division ratio of divider 1 when PLL circuit 1 is on.
• Equal to the frequency of CKIO pin when PLL circuit 1
is off.
• Do not set the internal clock frequency lower than the
CKIO pin frequency.
5. The frequency of the peripheral clock (Pφ) becomes:
• The product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1, and the
division ratio of divider 2 when the clock operating mode
is 0 to 2 or 7.
• The peripheral clock frequency should not be set
higher than the maximum frequency specified in the AC
Characteristics, higher than the frequency of the CKIO
pin, higher than 40 MHz, or lower than 1/8 the internal
clock (Iφ).
6. The output frequency of PLL circuit 1 is the product of
the CKIO frequency and the multiplication ratio of PLL
circuit 1. This frequency should be equal to or lower
than the maximum frequency specified in the AC
Characteristics.
7. × 1, × 2, × 3, × 4, or × 6 can be used as the
multiplication ratio of PLL circuit 1. × 1, × 1/2, × 1/3, and
× 1/4 can be selected as the division ratio of divider 1.
× 1, × 1/2, × 1/3, × 1/4, and × 1/6 can be selected as the
division ratio of divider 2. Set the rate in the frequency
control register. The on/off state of PLL circuit 2 is
determined by the mode.
• PLL circuit 1
• Do not set the internal clock frequency lower than the
CKIO pin frequency.
• Depending on the product, the clock ratio should be
set to produce a frequency within one of the ranges
indicated below.
100 MHz products: 24 MHz to 100 MHz
160 MHz products: 24 MHz to 160 MHz
5. Bus clock (Bφ) frequency:
• Depending on the product, the clock ratio should be
set to produce a frequency within one of the ranges
indicated below.
100 MHz products: 24 MHz to 50 MHz
160 MHz products: 24 MHz to 66.64 MHz
6. The frequency of the peripheral clock (Pφ) becomes:
• The product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1, and the
division ratio of divider 2.
• For all products, the peripheral clock frequency (Pφ)
should be set within the frequency range 6 MHz to
33.34 MHz and no higher than the frequency of the
CKIO pin.
• The peripheral clock frequency (Pφ) should be set to
13 MHz or higher if the USB function module is used.
7. The output frequency of PLL circuit 1 is the product of
the CKIO frequency and the multiplication ratio of PLL
circuit 1.
8. ×1, ×2, ×3, ×4, or ×6 can be used as the multiplication
ratio of PLL circuit 1. ×1, ×1/2, ×1/3, and ×1/4 can be
selected as the division ratio of divider 1. ×1, ×1/2, ×1/3,
×1/4, and ×1/6 can be selected as the division ratio of
divider 2. Set the rate in the frequency control register.
The on/off state of PLL circuit 2 is determined by the
mode.
Rev. 5.00 Dec 12, 2005 page xi of lxxii
Page
279
Previous Version
Revised Version
11.1.1 EXCPG
The extend clock pulse generator (EXCPG)
generates a divided clock from the CPU
clock (Iφ), the bus clock (Bφ), or the
external clock (UCLK).
The extend clock pulse generator (EXCPG)
generates a divided clock from the internal
clock (Iφ), the bus clock (Bφ), or the
external clock (UCLK).
Figure 11.1 Block Diagram of EXCPG
USB clock
(48 MHz)
P clock
USB
host
USB clock
(48 MHz)
Peripheral clock (Pφ)
USB
host
Select
281
I clock
1/1
Bus clock
1/2
UCLK
1/3
Select
USB
function
Internal clock (Iφ)
1/1
Bus clock (Bφ)
1/2
External clock (UCLK)
1/3
USB
function
11.3.1 EXCPG Control Register
(EXCPGCR)
Bits 5 to 3—Clock Select (USBCKSEL2 to
USBCKSEL0):
Bits 5 to 3
Function (Clock Selection)
110
External clock
Bits 5 to 3
Function (Clock Selection)
110
External clock (UCLK)
Bits 2 to 0 Function (Dividing Ratio
Selection):
Bits 2 to 0
Function (Dividing Ratio Selection)
1**
Iφ, CKIO, UCLK halted
Note: To reduce power consumption, set USBDIVSEL2 to 1 and halts Iø, CKIO, or UCLK input.
281
Bits 2 to 0
Function (Dividing Ratio Selection)
1**
Internal clock (Iφ), bus clock (Bφ), external clock (UCLK) halted
Note: To reduce power consumption, set USBDIVSEL2 to 1 and halts internal clock (Iφ), bus clock
(Bφ), or external clock (UCLK) input.
11.4 Usage Notes
Newly added
Rev. 5.00 Dec 12, 2005 page xii of lxxii
Page
Previous Version
303
12.2.5 Individual Memory Control Register
(MCR)
Bit:
15
14
13
12
11
10
9
8
7
6
5
Revised Version
4
3
2
1
TPC1 TPC0 RCD1 RCD0 TRWL TRWL TRAS TRAS RASD AMX3 AMX2 AMX1 AMX0 RFSH RMO
1
0
1
0
DE
Initial value:
R/W:
Bit:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
TPC1 TPC0 RCD1 RCD0 TRWL TRWL TRAS TRAS
1
0
1
0
—
Initial value:
R/W:
7
—
6
5
4
3
2
1
AMX3 AMX2 AMX1 AMX0 RFSH RMO
DE
0
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 and 14RAS Precharge Time
(TPC1, TPC0):
304
309
… However, the number of cycles inserted
immediately after the precharge all banks
(PALL) command is issued when
performing auto-refresh or the precharge
(PRE) command is issued in bank-active
mode is one fewer than the number of
cycles during normal operation. Do not set
TPC1 to 0 and TPC0 to 0 when in bankactive mode.
… However, the number of cycles inserted
immediately after the precharge all banks
(PALL) command is issued when
performing auto-refresh is one fewer than
the number of cycles during normal
operation.
Note: * Immediately after the precharge all
banks (PALL) command is issued when
performing auto-refresh or the precharge
(PRE) command is issued in bank-active
mode.
Note: * Immediately after the precharge all
banks (PALL) command is issued when
performing auto-refresh.
Bit 7—SDRAM Bank Active (RASD):
Specifies whether SDRAM is put into bankactive mode or auto-precharge mode. The
auto-precharge mode should be used if
both area 2 and area 3 are set in SDRAM
space and the bus width is 16 bits.
Bit 7Reserved:
Bit 7: RASD
Description
0
Auto-precharge mode
1
Bank-active mode
(Initial value)
This bit is always read as 0. The write
value should always be 0.
Table deleted
12.2.6 PCMCIA Control Register (PCR)
Bits 8, 1, and 0Area6 OE/WE Negate
Address Delay (A6TEH2, A6TEH1, and
A6TEH0):
Bit 8:
A6TEH2
Bit 1:
A6TEH1
Bit 0:
A6TEH0
Description
Bit 8:
A6TEH2
Bit 1:
A6TEH1
Bit 0:
A6TEH0
Description
1
0
0
4.5-cycle delay
1
0
0
4.5-cycle delay
1
Reserved
1
5.5-cycle delay
0
Reserved
0
6.5-cycle delay
1
Reserved
1
7.5-cycle delay
1
1
Rev. 5.00 Dec 12, 2005 page xiii of lxxii
Page
385
Previous Version
14.2.2 DMA Destination Address
Registers 0 to 3 (DAR0 to DAR3)
To transfer data in 16 bits or in 32 bits,
specify the address on the 16-bit or 32-bit
boundary. If any other address is specified,
correct operation is not guaranteed.
433
Revised Version
To transfer data in 16 bits or in 32 bits,
specify the address on the 16-bit or 32-bit
boundary. When transferring data in 16byte units, always set a value at a 16-byte
boundary (16n address) as the destination
address. If any other address is specified,
correct operation is not guaranteed.
14.4.2 Register Descriptions
Compare-Match Timer Control/Status
Register 0 (CMCSR0)
The compare-match timer control/status
register 0 (CMCSR0) is a 16-bit register
that indicates a compare-match
occurrence, sets enable/disable of
interrupts, and sets the incrementation
clock. …
434
The compare-match timer control/status
register 0 (CMCSR0) is a 16-bit register
that indicates a compare-match occurrence
and sets the incrementation clock. …
Bits 1 and 0clock Select 1, 0 (CKS1,
CKS0):
These bits select the clock input to CMCNT
from four internal clocks which are divided
from the system clock (Pφ). When the STR
bit in CMSTR is set to 1, …
These bits select the clock input to CMCNT
from four clocks which are divided from the
peripheral clock (Pφ). When the STR0 bit in
CMSTR is set to 1, …
Compare-Match Counter 0 (CMCNT0)
When the internal clock is selected with the
CKS1 and CKS0 bits in CMCSR0 and the
STR bit in CMSTR is set to 1, …
435
When the clock is selected with the CKS1
and CKS0 bits in CMCSR0 and the STR0
bit in CMSTR is set to 1, …
14.4.3 Operation
Period Count Operation
When the internal clock is selected with the
CKS1, CKS0 bits in CMCSR0 and the STR
bit of the CMSTR is set to 1,
Rev. 5.00 Dec 12, 2005 page xiv of lxxii
When the clock is selected with the CKS1
and CKS0 bits in CMCSR0 and the STR0
bit in CMSTR is set to 1, …
Page
436
Previous Version
Revised Version
CMCNT0 Count Timing
One of four clocks (Pφ/4, Pφ/8, Pφ/16,
Pφ/64) which are divided from the clock
(Pφ) can be selected with the CKS1 and
CKS0 bits in CMCSR0. …
One of four peripheral clocks (Pφ/4, Pφ/8,
Pφ/16, Pφ/64) which are divided from the
clock (Pφ) can be selected with the CKS1
and CKS0 bits in CMCSR0. …
Figure 14.28 Count Timing
437
CK
Peripheral clock (Pφ)
Internal clock
CMT clock
Figure 14.29 Timing of CMF Setting
CK
Peripheral clock (Pφ)
Figure 14.30 Timing of CMF Clear by the
CPU
CK
442
Peripheral clock (Pφ)
14.6 Usage Notes
Item 14, 15, added
443
15.1.1 Features
• Selection of six counter input clocks for
each channel:
On-chip RTC output clock (16 kHz), Pφ/4,
Pφ/16, Pφ/64, and Pφ/256
• Selection of six counter input clocks for
each channel:
On-chip RTC output clock (16 kHz), Pφ/4,
Pφ/16, Pφ/64, and Pφ/256
Note: Pφ is the internal clock for peripheral
Note deleted
modules and can be selected as 1/4, 1/2, or
the same frequency as that of the CPU
operating clock φ.) See section 10, On-Chip
Oscillation Circuits, for more information on
the clock pulse generator.
• The maximum 2 MHz operating frequency
for the 32-bit counter in each channel:
Operate the SH7727 so that the clock input
to each channel timer counter does not
exceed the maximum operating frequency,
by dividing the external clock and internal
clock with the prescaler)
Operate the SH7727 so that the clock input
to each channel timer counter does not
exceed the maximum operating frequency,
by dividing the external clock and
peripheral clock (Pφ) with the prescaler.
Rev. 5.00 Dec 12, 2005 page xv of lxxii
Page
469
Previous Version
Revised Version
16.2.15 RTC Control Register 1 (RCR1)
RCR1 is initialized to H'00 by a power-on
reset. By a manual reset, bits except the
CF flag are all initialized to 0, but the CF
flag is undefined. When using the CF flag, it
must be initialized beforehand. This register
is not initialized in standby mode.
Bit:
7
CF
Initial value:
R/W:
RCR1 is an 8-bit read/write register. The
CIE, AIE, and AF bits are initialized by a
power-on reset or manual reset. However,
the value of the CF flag is undefined after a
power-on reset or manual reset. It must
therefore be initialized without fail before
use. This register is not initialized in
standby mode.
Bit:
6
—
0
0
Initial value:
R/W
R
R/W:
7
6
CF
—
—
0
R/W
R
Bit 7—Carry Flag (CF):
Bit 7: CF
Description
Bit 7: CF
Description
0
No carry in R64CNT or RSECCNT.
0
No carry in R64CNT or RSECCNT.
Clearing condition: When 0 is written to CF
Rev. 5.00 Dec 12, 2005 page xvi of lxxii
(Initial value)
Clearing condition: When 0 is written to CF
Page
472,
473
Previous Version
Revised Version
16.3.2 Setting the Time
Figure 16.2 shows how to set the time after stopping the clock. This procedure is available to set
the entire calendar and clock function. This procedure can be programmed easily.
Figures 16.2 (a) and 16.2 (b) show how to set the time after stopping the clock. This procedure can
be used to set the entire calendar and clock function. It can be programmed easily.
Usage Notes
Stop clock,
reset divider circuit
Set seconds, minutes,
hour, day, day of the
week, month and year
Start clock
Write 1 to RESET and 0 to
START in the RCR2 register
1. Initialization Timing for 64 Hz Counter (R64CNT)
If it is necessary, after initializing the counter by means of the RESET bit in the RTC’s RCR2
register, to confirm that the change has taken effect by reading the R64CNT value, wait at least
107 µs after setting the RESET bit to 1 before reading the R64CNT counter. Note that the
divider circuit (RTC prescaler) is also initialized when the RESET bit is set to 1.
Order is irrelevant
2. Incrementing RSECCNT by Initializing R64CNT
Write 1 to START in the
RCR2 register
Either method (a) or method (b) below may be used.
(a) After setting the RESET bit to 1 and confirming that R64CNT has been initialized, set the
START bit to 1. This process is shown in figure 16.2 (a).
Reset the divider circuits (RTC prescaler and R64CNT) and set the counter.
(b) Set the START bit to 1 and the RESET bit to 1 at the same time. This process is shown in
figure 16.2 (b). Note that the processing indicated by the asterisk (*) in figure 16.2 (b) may
be omitted if nothing is written to the RCR2 register during an interval of approximately
107 µs after the START bit is set to 1.
Figure 16.2 Setting the Time
Confirm R64CNT is not 0
Stop clock
Reset divider circuit
Write 1 to RESET and
0 to START in the RCR2 register
Set seconds, minutes,
hour, day, day of the
week, month and year
Order is irrelevant
Confirm R64CNT is 0
No
Yes
Start clock
Write 1 to START in the RCR2 register
Figure 16.2(a) Setting the Time
*
Confirm R64CNT is not 0
Stop clock
Reset divider circuit
Write 1 to RESET and
0 to START in the RCR2 register
Set seconds, minutes,
hour, day, day of the
week, month and year
Order is irrelevant
Write 1 to RESET and
Start clock
Reset divider circuit
*
Confirm R64CNT is 0
*
Write to RCR2
1 to START in the RCR2 register
No
Yes
Figure 16.2(b) Setting the Time
481
17.1.2 Block Diagram
SCI pin I/O and data control is performed
by bits 11 to 8 of SCPCR and bits 5 and 4
of SCPDR. …
484
Table 17.2 Registers
497
17.2.8 Port SC Control Register
(SCPCR)/Port SC Date Register (SCPDR)
SCI pin I/O and data control is performed
by bits 3 to 0 of SCPCR and bits 1 and 0 of
SCPDR. …
H'8008
H'A888
SCPCR
SCPCR
Bit:
15
14
13
12
11
10
9
8
7
6
Bit:
SCP7 SCP7 SCP6 SCP6 SCP5 SCP5 SCP4 SCP4 SCP3 SCP3
MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0
Initial value:
R/W:
1
0
1
0
1
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
SCP7 SCP7 SCP6 SCP6 SCP5 SCP5 SCP4 SCP4 SCP3 SCP3
MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0
Initial value:
R/W:
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Dec 12, 2005 page xvii of lxxii
Page
Revised Version
19.1.1 Features
• On-chip modem control functions (RTS
and CTS)
Figure 19.1 SCIF Block Diagram
Bus interface
564
Module data bus
RxD2
SCFRDR2
(16stages)
SCFTDR2
(16stages)
SCRSR2
SCTSR2
TxD2
SCPCR2
SCFDR2
SCFDR2
SCFCR2
SCSSR2
SCSCR2
SCSMR2
Transmit/
receive
control
Internal
data bus
Baud rate
generator
SCFRDR2
(16stages)
SCFTDR2
(16stages)
SCRSR2
SCTSR2
Pφ
Pφ/4
RxD2
Pφ/16
Pφ/64
TxD2
SCPCR2
SCFDR2
SCFDR2
SCFCR2
SCSSR2
SCSCR2
SCSMR2
Transmit/
receive
control
Internal
data bus
SCBRR2
Baud rate
generator
Pφ
Pφ/4
Pφ/16
Pφ/64
Clock
Parity generation
Clock
Parity generation
Parity check
RTS2
ERI
TXI
BRI
BRI
SCIF
ERI
TXI
BRI
BRI
CTS2
SCIF
19.1.2 Block Diagram
Figures 19.2 and 19.3 show SCIF I/O ports.
Bits 11 to 8 of SCPCR and bits 5 and 4 of
SCPDR control an input/output and data of
the SCIF pins. …
603
Module data bus
SCBRR2
Parity check
565
• On-chip modem control functions (RTS2
and CTS2)
Bus interface
563
Previous Version
Figure 19.2 and 19.3 show SCIF I/O ports.
Bits 15, 14, 9, 8 of SCPCR and bits 7 and 4
of SCPDR control an input/output and data
of the SCIF pins. …
20.1.1 Features
• Serial clock
External clock or internal clock (P_CLK)
are able to be used as clock source.
604
External clock or peripheral clock (Pφ)
are able to be used as clock source.
20.1.2 Block Diagram
Peripheral
clock (Pφ)
PP-BUS
32
TXI
RXI
ERI
CCI
32
TXI
RXI
ERI
CCI
P_CLK
Figure 20.1 SIOF Block Diagram
Peripheral bus
Bus I/F
Bus I/F
32
32
16
32
32
32
32
16
Control register
Tx control data
Baud rate 1/n MCLK
generator
Rx_FIFO
32 bits ×
16 stages
Tx_FIFO
32 bits ×
16 stages
Control register
Rx control data
32
32
Tx_FIFO
32 bits ×
16 stages
Tx control data
Baud rate 1/n MCLK
generator
Timing control
P/S
S/P
TXD_SIO
RXD_SIO
32
32
Rx_FIFO
32 bits ×
16 stages
Rx control data
Timing control
P/S
S/P
TXD_SIO
RXD_SIO
SIOF
SIOMCLK
SCK_SIO SIOFSYNC
Rev. 5.00 Dec 12, 2005 page xviii of lxxii
SIOMCLK
SCK_SIO SIOFSYNC
Page
608
Previous Version
Revised Version
20.2.2 Clock Select Register (SISCR)
• Bit 15Master Clock Source Choice
(MSSEL):
Use PCLK as master clock
628
Use Peripheral clock (Pφ) as master clock
Figure 20.2 Serial Clock Supply System
BRG
BRG
E
SIOMCLK
E
P_CLK
SIOMCLK
Peripheral clock
(Pφ)
635
20.3.5 Control Data Interface
(1) Control by Slot Positions (Master Mode
1)
Note: When using this method, PCLK
Note: When using this method, Peripheral
should be used as the master clock (Master clock should be used as master clock
(Master Clock Select (MSSEL) = 1).
Clock Select (MSSEL) = 1).
651
20.4 Usage Notes
Item 7, 8, added
679
22.1.2 Pin Configuration
Table 22.1 Pin Configuration (Digital
Transceiver Signal)
709
Name
Symbol
I/O
Description
Name
Symbol
I/O
Description
TXDPLS pin
USB1d_TXDPLS
Output
D+ transmit output pin
TXDPLS pin
USB1d_TXDPLS
Output
D+ transmit output pin
TXDMNS pin
USB1d_TXDMNS
Output
D− transmit output pin
TXENL pin
USB1d_TXENL
Output
Driver output enable pin
TXENL pin
USB1d_TXENL
Output
Driver output enable pin
23.6.3 Control Transfer
Figure 23.8 Status Stage Operation
(Control-In)
Replaced
720
23.9 Usage Notes
Newly added
758
24.7 Notes on Using USB Host with
Versions Previous to the SH7727C
Newly added
Rev. 5.00 Dec 12, 2005 page xix of lxxii
Page
759
760
762
Previous Version
Revised Version
25.1.1 Features
• Supports 1/2/4/8/15/16-bpp (bit per pixel)
color modes
• Supports 4/8/15/16-bpp (bit per pixel)
color modes
• Supports 1/2/4-bpp grayscale modes
• Supports 1/2/4/6-bpp grayscale modes
Figure 25.1 Block Diagram
CKIO
Bus clock (Bφ)
P clock
Peripheral clock (Pφ)
Table 25.2 Register Configuration
H'F606
763
H'F60F
25.2.1 LCDC Input Clock Register
(LDICKR)
This LCDC can select the bus clock (Bφ),
the peripheral clock (Pφ), or the external
clock as its operation clock source. …
This LCDC can select CKIO (bus clock),
the P clock, or the external clock as its
operation clock source. …
Bits 13, and 12Input Clock Select
(ICKSEL1 and ICKSEL0):
766
CKIO is selected
Bus clock (Bφ) is selected
P clock is selected
Peripheral clock (Pφ) is selected
25.2.2 LCDC Module Type Register
(LDMTR)
Bits 5 to 0—Module Interface Type Select
(MIFTYP5 to MIFTYP0):
If an STN or DSTN panel is selected,
display control is performed using a 24-bit
space-modulation FRC consisting of the 8bit R, G, and B included in the LCDC, …
783
If an STN or DSTN panel is selected,
display control is performed using a 24-bit
space-modulation FRC (Frame Rate
Controller) consisting of the 8-bit R, G, and
B included in the LCDC, …
25.2.17 LCDC Power Management Mode
Register (LDPMMR)
Bit 4DON Pin Enable (DONE):
784
Bit 4
DONE
Description
0
Disabled: DON pin is masked and fixed low
(Initial value)
0
Disabled: DON pin is masked and fixed low
1
Enabled: DON pin output is asserted and negated according to the power-on or poweroff sequence
1
Enabled: DON pin output is asserted and negated according to the power-on or power(Initial value)
off sequence
Bit 4
DONE
Description
25.2.18 LCDC Power-Supply Sequence
Period Register (LDPSPR)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
ONA3
ONA2
ONA1
ONA0
ONB3
ONB2
ONB1
0
0
0
0
0
0
0
8
0
7
0
6
0
5
0
4
1
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
ONB0 OFFE3 OFFE2 OFFE1 OFFE0 OFFF3 OFFF2 OFFF1 OFFF0
Rev. 5.00 Dec 12, 2005 page xx of lxxii
Initial value:
R/W:
15
14
13
12
11
10
9
ONA3
ONA2
ONA1
ONA0
ONB3
ONB2
ONB1
1
1
1
1
0
1
1
8
0
7
0
6
0
5
0
0
4
1
3
1
2
1
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ONB0 OFFE3 OFFE2 OFFE1 OFFE0 OFFF3 OFFF2 OFFF1 OFFF0
Page
786
Previous Version
Revised Version
25.3.1 LCD Module Sizes which can be
Displayed in this LCDC
The overhead coefficient depends on the
The overhead coefficient is 1.375 if the
SDRAM in CL2 uses a 32-bit bus and 1.188 bus used by the SDRAM in CL2, as
indicated below.
if it uses a 16-bit bus.
If the hardware rotation function is not used
(ROT = 0), the overhead coefficient is 1.375
if a 32-bit bus is used and 1.188 if a 16-bit
bus is used.
If the hardware rotation function is used
(ROT = 1), the overhead coefficient is
determined by the access unit select (AU)
setting and the bus width, as follows.
Table added
787
to
793
Access Unit Select (AU) Setting
32-Bit Bus
16-Bit Bus
4-burst operation
2.500
1.750
8-burst operation
1.750
1.375
16-burst operation
1.375
1.188
32-burst operation
1.188
1.094
25.3.2 Limits on the Resolution of Rotated
Displays, Burst Length, and Connected
Memory (SDRAM)
Replaced
816
25.5 Usage Notes
Newly added
820,
821
Table 26.1 List of Multiplexed Pins
Port
Port Function
(Related Module)
Other Function 1
(Related Module)
K
PTK2 in/out (port)
CS4 out (BSC)
Port
Port Function
(Related Module)
Other Function 1
(Related Module)
K
PTK1 in/out (port)
AFE_RLYCNT out (AFE)
USB1d_DMNS0 in (USB)*2
K
PTK2 in/out (port)
CS4 out (BSC)
K
PTK0 in/out (port)
AFE_HC1 out (AFE)
USB1d_DPLS0 in (USB)*2
K
PTK1 in/out (port)
AFE_RLYCNT out (AFE)
USB1d_DMNS in (USB)*
L
PTL7 in (port)
AN7 in (ADC)/DA0 out (DAC)
K
PTK0 in/out (port)
AFE_HC1 out (AFE)
USB1d_DPLS in (USB)*
L
PTL2 in (port)
AN2 in (ADC)
M
PTM7 in (port)/PINT7 in (INTC)
AFE_FS in (AFE)
USB1d_RCV0 in (USB)*2
L
PTL2 in (port)
AN2 in (ADC)
M
PTM6 in (port)/PINT6 in (INTC)
AFE_RXIN in (AFE)
USB1d_SPEED0 out (USB)*2
M
PTM7 in (port)/PINT7 in (INTC)
AFE_FS in (AFE)
USB1d_RCV in (USB)*
M
PTM5 in (port)/PINT5 in (INTC)
AFE_TXOUT out (AFE)
USB1d_TXSE0 out (USB)*2
M
PTM6 in (port)/PINT6 in (INTC)
AFE_RXIN in (AFE)
USB1d_SPEED out (USB)*
M
PTM4 in (port)/PINT4 in (INTC)
AFE_RDET in (AFE)
USB1d_TXMNS0 out (USB)*2
M
PTM5 in (port)/PINT5 in (INTC)
AFE_TXOUT out (AFE)
USB1d_TXSE0 out (USB)*
M
PTM3 in (port)/ PINT10 in (INTC)
LCD15 out (LCDC)
M
PTM4 in (port)/PINT4 in (INTC)
AFE_RDET in (AFE)
M
PTM3 in (port)/ PINT10 in (INTC)
LCD15 out (LCDC)
Port
Port Function
(Related Module)
Other Function 1
(Related Module)
SCPT
SCPT4 in (port)*1
RxD2 in (SCIF)
SCPT4 out (port)*1
TxD2 out (SCIF)
SCPT
SCPT1 in/out (port)
Port
Port Function
(Related Module)
Other Function 1
(Related Module)
SCPT
SCPT4 in (port)*1
RxD2 in (UART ch 3)
SCPT4 out (port)*1
TxD2 out (UART ch 3)
SCPT
SCPT1 in/out (port)
SCK0 in/out (UART ch 1)
SCPT
*1
SCPT0 in (port)
RxD0 in (UART ch 1)
SCPT0 out (port)*1
TxD0 out (UART ch 1)
Other Function 2
(Related Module)
L
Other Function 2
(Related Module)
SCPT
PTL7 in (port)
Other Function 2
(Related Module)
2
2
AN7 in (ADC)/DA0 out (DAC)
*1
2
2
2
Other Function 2
(Related Module)
SCK0 in/out (SCI)
SCPT0 in (port)
RxD0 in (SCI)
SCPT0 out (port)*1
TxD0 out (SCI)
Rev. 5.00 Dec 12, 2005 page xxi of lxxii
Page
826
Previous Version
26.3.4 Port D Control Register (PDCR)
Bit (2n + 1)
Bit 2n
PDnMD1
PDnMD0
Pin Function
PDnMD1
PDnMD0
Pin Function
0
0
Other function (see table 26.1)
0
0
Other function (see table 26.1)
0
1
Port output (n = value other than 4 or 6), reserved (n = 4 or 6)
0
1
Port output (n = value other than 4 or 6), reserved (n = 4 or 6)
1
0
Port input (Pullup MOS: on)
1
0
Port input (Pullup MOS: on)
1
1
Port input (Pullup MOS: off)
1
1
Port input (Pullup MOS: off)
Bit (2n + 1)
838
Revised Version
Bit 2n
(Initial value)
26.3.13 SC Port Control Register
(SCPCR)
Bits 5, 4—SCP2 Mode 1, 0 (SCP2MD1,
SCP2MD0):
Bit 5
909
Bit 5
Bit 4
Bit 4
SCP2MD1
SCP2MD0
Pin Function
SCP2MD1
SCP2MD0
Pin Function
0
0
Transmit data output 1 (TxD1)
Receive data input 1 (RxD1)
0
0
Transmit data output 1 (TxD_SiO)
Receive data input 1 (RxD_SiO)
(Initial value)
0
1
General output (SCPT[2] output pin)
Receive data input 1 (RxD1)
0
1
General output (SCPT[2] output pin)
Receive data input 1 (RxD_SiO)
1
0
SCPT[2] input pin pullup (input pin)
Transmit data output 1 (TxD1)
1
0
SCPT[2] input pin pullup (input pin)
Transmit data output 1 (TxD_SiO)
1
1
General input (SCPT[2] input pin)
Transmit data output 1 (TxD1)
1
1
General input (SCPT[2] input pin)
Transmit data output 1 (TxD_SiO)
(Initial value)
Note: There is no combination of simultaneous I/O of SCPT[2] because one bit (SCP2DT) is
accessed using two pins of TxD1 and RxD1.
Note: There is no combination of simultaneous I/O of SCPT[2] because one bit (SCP2DT) is
accessed using two pins of TxD_SiO and RxD_SiO.
When the port input is set (bit SCPnMD1 is set to 1) and when the TE bit in SCSCR is set to 1, the
TxD1 pin is in the output state. When the TE bit is cleared to 0, the TxD1 pin is in the highimpedance state.
When the port input is set (bit SCPnMD1 is set to 1) and when the TE bit in SCSCR is set to 1, the
TxD_SiO pin is in the output state. When the TE bit is cleared to 0, the TxD_SiO pin is in the
high-impedance state.
30.3.3 Usage Notes
Setting procedure when Using PC Card
Controller:
1. Set bit 0 (A6PCM) in bus control register
1 (BCR1) in the bus state controller to 1.
2. Set bit 4 (P0USE) in the area 6 general
control register in the PC card controller to
1.
3. Set the pin function controller to custom
PC card pin functions (“other functions”).
Rev. 5.00 Dec 12, 2005 page xxii of lxxii
1. Drive pin ASEMD0 high.
2. Set bit 0 (A6PCM) in bus control register
1 (BCR1) in the bus state controller to 1.
3. Set bit 4 (P0USE) in the area 6 general
control register in the PC card controller to
1.
4. Set the pin function controller to custom
PC card pin functions (“other functions”).
Page
Previous Version
918,
919
Table 31.3 Correspondence between
SH7727 Pins and Boundary-Scan Register
Bit
Pin Name
I/O
170
PTM5/PINT5/AFE_TXOUT/
USB1d_TXSE0
Control
169
PTM4/PINT4/AFE_RDET/
USB1d_TXDMNS
IN
168
Reserved/USB1d_SUSPEND0
IN
137
MD0
IN
136
925
Revised Version
PTM4/PINT4/AFE_RDET/
USB1d_TXDMNS
OUT
Bit
Pin Name
I/O
170
PTM5/PINT5/AFE_TXOUT/
USB1d_TXSE0
Control
169
PTM4/PINT4/AFE_RDET
IN
168
Reserved/USB1d_SUSPEND0
IN
137
MD0
IN
136
PTM4/PINT4/AFE_RDET
OUT
135
Reserved/USB1d_SUSPEND0
OUT
OUT
135
Reserved/USB1d_SUSPEND0
OUT
110
PTF0/PCC0VS2/Reserved
110
PTF0/PCC0VS2/Reserved
OUT
109
PTM4/PINT4/AFE_RDET
Control
109
PTM4/PINT4/AFE_RDET/
USB1d_TXDMNS
Control
108
Reserved/USB1d_SUSPEND0
Control
108
Reserved/USB1d_SUSPEND0
Control
32.1 Absolute Maximum Ratings
Caution:
Item 3 added
927,
928
Table 32.2 DC Characteristics (1)
Item
Symbol
Min
Typ
Max
Unit
Power supply voltage
VCCQ
3.0
—
3.6
V
2.6
—
3.6
Measurement
Conditions
HD6417727F160,
HD6417727BP160V
Item
Symbol
Min
Typ
Max
Unit
Measurement
Conditions
Power supply voltage
VCCQ
3.0
—
3.6
V
160 MHz products
2.6
—
3.6
100 MHz products
VCC,
1.70
—
2.05
160 MHz products
VCC-PLL1,
1.60
—
2.05
100 MHz products
—
0.8
2
mA
—
2.4
6
mA
—
0.01
5.0
mA
HD6417727F100,
HD6417727BP100V
See note *4 for applied
voltage when mounted.
VCC,
1.70
—
2.05
HD6417727F160,
HD6417727BP160V
VCC-PLL1,
VCC-PLL2,
VCC-RTC*1
See note *4 for applied
voltage when mounted.
1.60
—
2.05
—
0.8
2
—
2.4
6
mA
—
0.01
5.0
mA
HD6417727F100,
HD6417727BP100V
See note *4 for applied
voltage when mounted.
Analog (A/D, During A/D
D/A) power- conversion
supply
During A/D
current
and D/A
conversion
Idle
AICC
VCC-PLL2,
VCC-RTC*1
Analog (A/D, During A/D
D/A) power- conversion
supply
During A/D
current
and D/A
conversion
Idle
AICC
Ta = 25°C
mA
Notes:
*3 Current dissipation values shown are
for VIHmin = VccQ – 0.5 V and VILmax =
0.5 V with 5 pF load.
3. Current dissipation values are for VIH
min = VccQ – 0.5 V and VIL max = 0.5 V
with all output pins in the no-load state.
*4 The voltage range that can be applied
depends on the operating frequency
setting. Be sure check the operating
frequency range of the AC characteristics.
4. There is no stipulation regarding the
power supply in standby mode when there
is no RTC clock input.
*5 There is no stipulation regarding the
power supply in standby mode when there
is no RTC clock input.
Rev. 5.00 Dec 12, 2005 page xxiii of lxxii
Page
930
Previous Version
Revised Version
32.3 AC Characteristics
In general, inputting for this LSI should be
clock synchronous. Keep the setup and
hold times for each input signal unless
otherwise specified. Regarding the power
supply and frequency specifications of the
individual products, refer to tables 32.2 and
32.4. When the measuring condition range
in the timing chart is wider than that in table
32.2 or 32.4, the conditions listed in table
32.2 or 32.4 apply.
In general, inputting for this LSI should be
clock synchronous. Keep the setup and
hold times for each input signal unless
otherwise specified. Regarding the power
supply and frequency specifications of the
individual products, refer to figure 32.2,
tables 32.2 and 32.4.
AC specifications vary depending on the
product, so should be checked before the
chip is used.
931
Figure 32.2 Power Supply Voltage and
Operating Frequency
Newly added
932
Table 32.4 Maximum Operating
Frequencies (1)
Item
Symbol
Min
Max
Unit
CPU, cache,
TLB (Iφ)
f
24
100
MHz
External bus
(Bφ) or CKIO I/O
frequency
Peripheral
modules (Pφ)
932
Power Supply
Voltage Conditions
Products
VCC = 1.60 to 2.05 V,
VCCQ = 2.6 to 3.6 V
HD6417727F100,
HD6417727BP100V
24
33.4
VCC = 1.60 to 2.05 V,
VCCQ= 2.6 to 3.6 V
24
50
VCC = 1.70 to 2.05 V,
VCCQ= 3.0 to 3.6 V
6
33.4
VCC = 1.60 to 2.05 V,
VCCQ = 2.6 to 3.6 V
Item
Symbol
Min
Max
Unit
Power Supply
Voltage Conditions
Reference Products
CPU, cache,
TLB (Iφ)
f
24
100
MHz
VCC = 1.60 to 2.05 V
—
VCCQ = 2.6 to 3.6 V
External bus
(Bφ) or CKIO
I/O frequency
24
33.34
VCC = 1.60 to 2.05 V
24
50
VCC = 1.70 to 2.05 V
100 MHz
products
Table 32.5
VCCQ = 2.6 to 3.6 V
Table 32.6
VCCQ= 3.0 to 3.6 V
Peripheral
modules (Pφ)
6
33.34
VCC = 1.60 to 2.05 V
—
VCCQ = 2.6 to 3.6 V
Table 32.4 Maximum Operating
Frequencies (2)
Item
Symbol
Min
Max
Unit
CPU, cache,
TLB (Iφ)
f
24
144
MHz
External bus
(Bφ) or CKIO I/O
frequency
Peripheral
modules (Pφ)
Power Supply
Voltage Conditions
Products
VCC = 1.70 to 2.05 V,
VCCQ = 3.0 to 3.6 V
HD6417727F160,
HD6417727BP160V
24
160
VCC = 1.75 to 2.05 V,
VCCQ = 3.0 to 3.6 V
24
48
VCC = 1.70 to 2.05 V,
VCCQ = 3.0 to 3.6 V
24
66.67
VCC = 1.75 to 2.05 V,
VCCQ = 3.0 to 3.6 V
6
33.4
VCC = 1.70 to 2.05 V,
VCCQ = 3.0 to 3.6 V
Rev. 5.00 Dec 12, 2005 page xxiv of lxxii
Item
Symbol
Min
Max
Unit
Power Supply
Voltage Conditions
Reference Products
CPU, cache,
TLB (Iφ)
f
24
144
MHz
VCC = 1.70 to 2.05 V
—
VCCQ= 3.0 to 3.6 V
24
160
VCC = 1.75 to 2.05 V
24
50
VCC = 1.70 to 2.05 V
—
VCCQ= 3.0 to 3.6 V
External bus
(Bφ) or CKIO
I/O frequency
Table 32.7
VCCQ= 3.0 to 3.6 V
24
66.67
VCC = 1.75 to 2.05 V
6
33.34
VCC = 1.70 to 2.05 V
Table 32.8
VCCQ= 3.0 to 3.6 V
Peripheral
modules (Pφ)
VCCQ= 3.0 to 3.6 V
—
160 MHz
products
Page
933
Previous Version
Table 32.5 Clock Timing (1)
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.6 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C,
external bus maximum operating frequency = 33 MHz
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C,
100 MHz products
Item
Symbol
Min
EXTAL clock input frequency
fEX
EXTAL clock input cycle time
tEXcyc
tEXL
EXTAL clock input low pulse width
Max
Unit
Figure
Item
Symbol
Min
Max
Unit
Figure
6
33
MHz
32.1
EXTAL clock input frequency
33.34
MHz
32.3
167
ns
EXTAL clock input cycle time
30
166.7
ns
7
—
ns
EXTAL clock input low pulse width
fEX
tEXcyc
tEXL
tEXH
6
30.3
9
—
ns
ns
tEXH
7
—
ns
EXTAL clock input high pulse width
9
—
EXTAL clock input rise time
tEXR
—
6
ns
EXTAL clock input rise time
tEXR
—
6
EXTAL clock input fall time
tEXF
fCKI
—
6
ns
EXTAL clock input fall time
tEXF
—
6
ns
24
33
MHz
CKIO clock input frequency
24
33.34
MHz
tCKIcyc
tCKIL
30.3
40
ns
CKIO clock input cycle time
30
41.7
ns
7
—
ns
CKIO clock input low pulse width
fCKI
tCKIcyc
tCKIL
9
—
ns
CKIO clock input high pulse width
tCKIH
7
—
ns
CKIO clock input high pulse width
tCKIH
9
—
ns
CKIO clock input rise time
tCKIR
—
6
ns
CKIO clock input rise time
tCKIR
—
6
CKIO clock input fall time
—
6
ns
CKIO clock input fall time
6
ns
24
33
MHz
CKIO clock output frequency
tCKIF
fOP
—
CKIO clock output frequency
tCKIF
fOP
24
33.34
MHz
CKIO clock output cycle time
tcyc
30.3
40
ns
CKIO clock output cycle time
tcyc
30
41.7
ns
EXTAL clock input high pulse width
CKIO clock input frequency
CKIO clock input cycle time
CKIO clock input low pulse width
934
Revised Version
32.2
32.3
Table 32.5 Clock Timing (2)
ns
32.4
ns
32.5
Table 32.6 Clock Timing (2)
Conditions: VccQ = 3.0 to 3.6 V, Vcc = 1.75 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C,
external bus maximum operating frequency = 66.67 MHz
Conditions: VccQ = 3.0 to 3.6 V, Vcc = 1.70 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C,
100 MHz products
Item
Symbol
Min
Max
Unit
Figure
Item
Symbol
Min
Max
Unit
Figure
EXTAL clock input frequency
f EX
6
66.67
MHz
32.1
EXTAL clock input frequency
f EX
6
50
MHz
32.3
EXTAL clock input cycle time
tEXcyc
15.2
167
ns
EXTAL clock input cycle time
tEXcyc
20
166.7
ns
EXTAL clock input low pulse width
t EXL
1.5
—
ns
EXTAL clock input low pulse width
t EXL
4
—
ns
EXTAL clock input high pulse width
t EXH
1.5
—
ns
EXTAL clock input high pulse width
t EXH
4
—
CKIO clock input frequency
f CKI
24
66.67
MHz
CKIO clock input frequency
f CKI
24
50
MHz
CKIO clock input cycle time
tCKIcyc
15.2
40
ns
CKIO clock input cycle time
tCKIcyc
20
41.7
ns
CKIO clock input low pulse width
t CKIL
1.5
—
ns
CKIO clock input low pulse width
t CKIL
4
—
ns
CKIO clock input high pulse width
tCKIH
1.5
—
ns
CKIO clock input high pulse width
tCKIH
4
—
CKIO clock output frequency
f OP
24
66.67
MHz
CKIO clock output frequency
f OP
24
50
MHz
CKIO clock output cycle time
tcyc
15.2
—
ns
CKIO clock output cycle time
tcyc
20
41.7
ns
Power-on oscillation settling time
tOSC1
10
—
ns
Power-on oscillation settling time
tOSC1
10
—
ms
32.2
32.3
32.4
935
ns
32.4
ns
32.5
32.6
Table 32.7 Clock Timing (3)
Newly added
936
Table 32.8 Clock Timing (4)
Newly added
938
Figure 32.3 CKIO Clock Output Timing
tCK2D
CKIO2
(output)
Figure 32.5 CKIO Clock Output Timing
tCK2D
tCK2D
CKIO2
(output)
VIH
tCK2OF
tCK2OR
VOH
tCK2D
VOH
VOH
VOL
tCK2OF
VOL
tCK2OR
Rev. 5.00 Dec 12, 2005 page xxv of lxxii
Page
942
Previous Version
Revised Version
Table 32.6 Control Signal Timing
2
Table 32.9 Control Signal Timing
3
33 MHz*
66.67 MHz*
Min
Max
Min
RESETP pulse width
1
RESETP setup time*
tRESPW
20
—
20*
—
tRESPS
23
—
23
—
RESETP hold time
tRESPH
2
—
2
—
—
4
Max
Min
20*
—
tRESPS
23
—
RESETP hold time
tRESPH
2
RESETM pulse width
tRESMW
12*
—
RESETM setup time
tRESMS
3
—
RESETM hold time
tRESMH
34
—
BREQ setup time
tBREQS
10
—
tBREQH
3
—
tNMIS
10
—
tNMIH
4
—
tIRQS
10
—
RESETM pulse width
tRESMW
12
—
RESETM setup time
tRESMS
3
—
3
—
RESETM hold time
tRESMH
34
—
34
—
BREQ setup time
tBREQS
10
—
10
—
BREQ hold time
1
NMI setup time *
tBREQH
3
—
3
—
tNMIS
10
—
10
—
NMI hold time
tNMIH
4
—
4
—
BREQ hold time
1
NMI setup time *
tIRQS
10
—
10
—
NMI hold time
1
Max
tRESPW
5
12*
IRQ5–IRQ0 setup time *
2
RESETP pulse width
1
RESETP setup time*
*1
—
3
IRQ5–IRQ0 hold time
tIRQH
4
—
4
—
IRQ5–IRQ0 setup time
BACK delay time
tBACKD
—
10
—
10
IRQ5–IRQ0 hold time
tIRQH
4
—
STATUS1, STATUS0 delay
time
tSTD
—
16
—
16
BACK delay time
tBACKD
—
10
STATUS1, STATUS0 delay time
tSTD
—
16
Bus tri-state delay time 1
tBOFF1
0
15
0
15
Bus tri-state delay time 2
tBOFF2
0
15
0
15
Bus tri-state delay time 1
tBOFF1
0
15
Bus buffer-on time 1
tBON1
0
15
0
15
Bus tri-state delay time 2
tBOFF2
0
15
Bus buffer-on time 2
tBON2
0
15
0
15
Bus buffer-on time 1
tBON1
0
15
Bus buffer-on time 2
tBON2
0
15
Notes:
*1 RESETP, NMI and IRQ5 to IRQ0 are
asynchronous. Changes are detected at
the clock fall when the setup shown is
used. When the setup cannot be used,
detection can be delayed until the next
clock falls. When using as IRL, please
observe the setup time.
1. RESETP, NMI and IRQ5 to IRQ0 are
asynchronous. Changes are detected at
the clock fall when the setup shown is
used. When the setup cannot be used,
detection can be delayed until the next
clock falls. When using as IRL, please
observe the setup time.
*2 When Vcc = 1.6 to 2.05 V and VccQ =
2.6 to 3.6 V, the upper limit of the external
bus clock is 33 MHz.
2. In the standby mode, tRESPW = tOSC2 (10
ms). In the sleep mode, tRESPW = tPLL1 (100
µs). When the clock multiplication ratio is
changed, tRESPW = tPLL1 (100 µs).
*3 When Vcc = 1.75 to 2.05 V and VccQ =
3.0 to 3.6 V, the upper limit of the external
bus clock is 66.67 MHz.
*4 In the standby mode, tRESPW = tOSC2 (10
ms). In the sleep mode, tRESPW = tPLL1 (100
µs). When the clock multiplication ratio is
changed, tRESPW = tPLL1 (100 µs).
Rev. 5.00 Dec 12, 2005 page xxvi of lxxii
Page
945,
946
Previous Version
Revised Version
Table 32.7 Bus Timing
Table 32.10 Bus Timing
1
2
33 MHz*
66.67 MHz*
Item
Symbol
Min
Max
Min
Max
Unit
Item
Symbol Min
Max
Unit
Conditions
Address delay time
tAD
1.5
16
1.5
13
ns
Address delay time
tAD
1.5
13
ns
Vcc = 1.70 to 2.05 V
Address setup time
tAS
0
—
0
—
ns
tAH*
1.5
16
Address hold time
7
—
7
—
ns
BS delay time
tBSD
—
12
—
12
ns
CS delay time 1
tCSD1
1.5
12
1.5
12
ns
CS delay time 2
tCSD2
1
12
1
12
ns
Read/write delay time
tRWD
1.5
10
1.5
10
ns
Read/write hold time
tRWH
0
—
0
—
ns
Read strobe delay time tRSD
—
10
—
10
ns
Read data setup time 1 tRDS1
6
—
6
—
ns
VccQ = 3.0 to 3.6 V
3
7
—
7
—
ns
Read data hold time 1
tRDH1*
0
—
0
—
ns
Read data hold time 2
tRDH2
2
—
2
—
ns
Write enable delay time tWED
1
10
1
10
ns
Write data delay time 1 tWDD1
—
14
—
14
ns
Read data setup time 2 tRDS2
4
Write data delay time 2 tWDD2
—
—
13
33 MHz
*1
13
66.67 MHz
Other than the above
Address setup time
tAS
0
—
ns
Address hold time
1
tAH*
7
—
ns
BS delay time
tBSD
—
12
ns
CS delay time 1
tCSD1
1.5
12
ns
CS delay time 2
tCSD2
1
12
ns
Read/write delay time
tRWD
1.5
10
ns
Read/write hold time
tRWH
0
—
ns
Read strobe delay time tRSD
—
10
ns
Read data setup time 1 tRDS1
6
—
ns
Read data setup time 2 tRDS2
7
—
ns
2
Read data hold time 1
tRDH1*
0
—
ns
Read data hold time 2
tRDH2
2
—
ns
Write enable delay time tWED
1
10
ns
Write data delay time 1 tWDD1
—
14
ns
Write data delay time 2 tWDD2
—
13
ns
ns
*2
Item
Symbol
Min
Max
Min
Max
Unit
Item
Symbol Min
Max
Unit
Write data hold time 1
tWDH1
1.5
—
1.5
—
ns
Write data hold time 1
tWDH1
1.5
—
ns
Write data hold time 2
tWDH2
1.5
—
1.5
—
ns
Write data hold time 2
tWDH2
1.5
—
ns
Write data hold time 3
tWDH3
2
—
2
—
ns
Write data hold time 3
tWDH3
2
—
ns
Write data hold time 4
tWDH4
2
—
2
—
ns
Write data hold time 4
tWDH4
2
—
ns
ns
WAIT setup time
tWTS
5
—
ns
6
—
WAIT setup time
tWTS
6
—
5
—
Conditions
Vcc = 1.70 to 2.05 V
VccQ = 3.0 to 3.6 V
WAIT hold time
tWTH
0
—
0
—
ns
RAS delay time 2
tRASD2
1.5
12
1.5
12
ns
CAS delay time 2
tCASD2
1.5
12
1.5
12
ns
DQM delay time
tDQMD
1.5
10
1.5
10
ns
CKE delay time
tCKED
1.5
12
1.5
12
ns
ICIORD delay time
tICRSD
—
12
—
12
ns
ICIOWR delay time
tICWSD
—
12
—
12
ns
IOIS16 setup time
tIO16S
12
—
12
—
ns
IOIS16 hold time
tIO16H
4
—
4
—
ns
DACK delay time 1
tDAKD1
—
10
—
10
ns
Other than the above
WAIT hold time
tWTH
0
—
ns
RAS delay time 2
tRASD2
1.5
12
ns
CAS delay time 2
tCASD2
1.5
12
ns
DQM delay time
tDQMD
1.5
10
ns
CKE delay time
tCKED
1.5
12
ns
ICIORD delay time
tICRSD
—
12
ns
ICIOWR delay time
tICWSD
—
12
ns
IOIS16 setup time
tIO16S
12
—
ns
IOIS16 hold time
tIO16H
4
—
ns
DACK delay time 1
tDAKD1
—
10
ns
Notes:
*1 When Vcc = 1.6 to 2.05 V and VccQ =2.6 to 3.6 V,
the upper limit of the external bus clock is 33 MHz.
1. tAH: This is to deal with the latest negate timing of
CSn, RD, or WEn.
*2 When Vcc = 1.75 to 2.05 V and VccQ = 3.0 to 3.6 V,
the upper limit of the external bus clock is 66.67 MHz.
2. tRDH1: This is to deal with the earliest negate timing of
CSn or RD.
*3 tAH: This is to deal with the latest negate timing of
CSn, RD, or WEn.
*4 tRDH1: This is to deal with the earliest negate timing of
CSn or RD.
Rev. 5.00 Dec 12, 2005 page xxvii of lxxii
Page
949
Previous Version
Revised Version
Figure 32.17 Basic Bus Cycle (External
Wait, WAITSEL = 1)
Figure 32.19 Basic Bus Cycle (External
Wait, WAITSEL = 1)
tRDS1
tRDS1
D31 to D0
(read)
D31 to D0
(read)
Note added
Notes: tRDH1: Specified based on the earliest negate timing of CSn or RD.
tAH: Specified based on the latest negate timing of CSn, RD, or WEn.
971
Table 32.8 Peripheral Module Signal
Timing
Table 32.11 Peripheral Module Signal
Timing
–66.67
Min
973
974
Max
Min
Max
Note: * Pcyc stands for “P clock cycle.”
Note: * Pcyc stands for “peripheral clock
(Pφ) cycle.”
Figure 32.42 I/O Port Timing
Figure 32.44 I/O Port Timing
PORT 7 to 0
(read)
(B:P clock ratio = 1:1)
PORT A to H,
J to M, SC (read)
(bus clock:peripheral
clock ratio = 1:1)
PORT 7 to 0
(read)
(B:P clock ratio = 1:2)
PORT A to H,
J to M, SC (read)
(bus clock:peripheral
clock ratio = 1:1/2)
PORT 7 to 0
(read)
(B:P clock ratio = 1:4)
PORT A to H,
J to M, SC (read)
(bus clock:peripheral
clock ratio = 1:1/4)
PORT 7 to 0
(write)
PORT A to H,
J to M, SC (write)
Figure 32.45 TCK Input Timing
Figure 32.47 TCK Input Timing
tTCKcyc
tTCKH
tTCKcyc
tTCKL
tTCKH
VIH VIH
1/2VccQ
tTCKL
TCK (input)
TCK (input)
VIL VIL
tTCKf
VIL
1/2VccQ
tTCKf
Note: When clock is input from TCK pin
Rev. 5.00 Dec 12, 2005 page xxviii of lxxii
VIH VIH
1/2 VccQ
VIL VIL
tTCKf
VIH
1/2 VccQ
tTCKf
Page
981
983
985
Previous Version
Revised Version
Table 32.12 USB Module Signal Timing
Table 32.15 USB Module Signal Timing
Item
Symbol
Min
Max
Unit
Figure
Item
Symbol
Min
Max
Unit
Figure
UCLK external input clock
frequency (48 MHz)
tFREQ
47.9
48.1
MHz
32.56
UCLK external input clock
frequency (48 MHz)
tFREQ
47.9
48.1
MHz
32.58
Clock rise time
tR48
—
2
ns
Clock rise time
tR48
—
6
ns
Clock fall time
tF48
—
2
ns
Clock fall time
tF48
—
6
ns
Duty (tHIGH/tLOW)
tDUTY
90
110
%
Table 32.15 AFEIF Module Signal Timing
Table 32.18 AFEIF Module Signal Timing
Note: tPCYC is the cycle time (ns) of the
peripheral clock (P clock).
Note: tPCYC is the cycle time (ns) of the
peripheral clock (Pφ).
32.3.14 AC Characteristics Measurement
Conditions
• Input pulse level: VssQ to 3.0 V (where
RESETP, RESETM, ASEMD0, IRL3 to
IRL0, ADTRG, PINT[15] to PINT[0], CA,
NMI, IRQ5 to IRQ0, CKIO, and MD5 to
MD0 are within VssQ to VccQ)
• Input pulse level: Vss to 3.0 V (where
RESETP, RESETM, ASEMD0, IRL3 to
IRL0, ADTRG, PINT[15] to PINT[0], CA,
NMI, IRQ5 to IRQ0, CKIO, and MD5 to
MD0 are within VssQ to VccQ)
991,
992
Table A.1 Pin Functions (cont)
Type
AFE/USB
digital/port
related
Serial
related
997
Signal Name
(Initial Status: Bold)
Standby
Release/
Open Bus
Privileges
I/I/I/O
V
I/I/I/O
Z(V)/I/Z/O
I/I/I/O
Pin No.
(HQFP)
118, 119,
PTM[7]/PINT[7]/
AFE_FS/USB1d_RCV,
120
PTM[6]/PINT[6]/
AFE_RXIN/USB1d_SPEED,
PTM[5]/PINT[5]/
AFE_TXOUT/
USB1d_TXSE0
I/O
PowerManual
On
Reset
Reset
PTM[4]/PINT[4]/
AFE_RDET/
USB1d_TXDMNS
121
I/I/I/O
V
I/I/I/O
Z(V)/I/Z/O
I/I/I/O
USB1d_SUSPEND
122
O
O
O
O
O
SIOMCLK/SCPT[3]
194
I/IO
I
Z/P
Z/K
I/P
SCK_SIO/SCPT[5],
SIOFSYNC/SCPT[6]
196, 197
IO/IO
I
Z/P
Z/K
IO/P
RxD0/SCPT[0],
RxD2/SCPT[4]
198, 201
I/I
Z
Z/I
Z/Z
I/Z
Type
AFE/USB
digital/port
related
Serial
related
Signal Name
(Initial Status: Bold)
I/O
PowerOn
Reset
Manual
Reset
Standby
Release/
Open Bus
Privileges
I/I/I/O
V
I/I/I/O
Z(V)/I/Z/O
I/I/I/O
I/I/I
Pin No.
(HQFP)
118, 119,
PTM[7]/PINT[7]/
120
AFE_FS/USB1d_RCV,
PTM[6]/PINT[6]/
AFE_RXIN/USB1d_SPEED,
PTM[5]/PINT[5]/
AFE_TXOUT/
USB1d_TXSE0
PTM[4]/PINT[4]/
AFE_RDET
121
I/I/I
V
I/I/I
Z(V)/I/Z
USB1d_SUSPEND
122
O
O
O
O
SIOMCLK/SCPT[3]
194
I/IO
I
Z/P
Z/K
I/P
SCK_SIO/SCPT[5]
196
IO/IO
I
Z/P
Z/K
IO/P
SIOFSYNC/SCPT[6]
197
IO/IO
I
Z/P
K/K
IO/P
RxD0/SCPT[0],
RxD2/SCPT[4]
198, 201
I/I
Z
Z/I
Z/Z
I/Z
O
Table A.2 Treatment of Unused Pins
(cont)
Type
AFE/USB
digital/port
related
Signal Name (Initial Status:
Bold)
Pin No (HQFP)
PTM[7]/PINT[7]/AFE_FS/
118, 119, 120
USB1d_RCV,
PTM[6]/PINT[6]/AFE_RXIN/
USB1d_SPEED,
PTM[5]/PINT[5]/AFE_TXOUT/
USB1d_TXSE0
Pin No (CSP)
I/O
Treatment
when Not Used
V19, T18, V18
I/I/I/O Open
I/I/I/O Open
PTM[4]/PINT[4]/AFE_RDET/
USB1d_TXDMNS
121
W19
USB1d_SUSPEND
122
V16
O
Type
AFE/USB
digital/port
related
Signal Name
(Initial Status: Bold)
Pin No (HQFP)
118, 119, 120
PTM[7]/PINT[7]/AFE_FS/
USB1d_RCV,
PTM[6]/PINT[6]/AFE_RXIN/
USB1d_SPEED,
PTM[5]/PINT[5]/AFE_TXOUT/
USB1d_TXSE0
Pin No (CSP)
V19, T18, V18
I/O
Treatment
when Not Used
I/I/I/O Open
121
W19
I/I/I
Open
Reserved/USB1d_SUSPEND 122
V16
O
Open
PTM[4]/PINT[4]/AFE_RDET
Open
Rev. 5.00 Dec 12, 2005 page xxix of lxxii
Page
1001
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Revised Version
Table A.3 Pin Status (Normal
Memory/Little Endian) (cont)
Note: 2. Unused pins can be switched to
port function, pull-up, or pull-down.
1003
Table A.4 Pin Status (Normal Memory/Big
Endian) (cont)
Note: 2. Unused pins can be switched to
port function, pull-up, or pull-down.
1005
Note: 2. Unused pins can be switched to
port function, pull-up.
Table A.9 Pin Status (PCMCIA/Little
Endian) (cont)
Note: 2. Unused pins can be switched to
port function, pull-up, or pull-down.
1013
Note: 2. Unused pins can be switched to
port function, pull-up.
Table A.6 Pin Status (Burst ROM/Big
Endian) (cont)
Note: 2. Unused pins can be switched to
port function, pull-up, or pull-down.
1011
Note: 2. Unused pins can be switched to
port function, pull-up.
Table A.5 Pin Status (Burst ROM/Little
Endian) (cont)
Note: 2. Unused pins can be switched to
port function, pull-up, or pull-down.
1007
Note: 2. Unused pins can be switched to
port function, pull-up.
Note: 2. Unused pins can be switched to
port function, pull-up.
Table A.10 Pin Status (PCMCIA/Big
Endian) (cont)
Note: 2. Unused pins can be switched to
port function, pull-up, or pull-down.
1018, Table B.1 Memory-Mapped Control
1019, Registers (Address Map)
1021
Note: 2. Unused pins can be switched to
port function, pull-up.
Control Register
Module*1
Bus*2
Address*4
Access Size (Bits)*3
Control Register
SIRCR
SIOF
P2
H'040000EC
32
32
SIRCR
SIOF
P2
H'040000EC
32
32
SITMR
SIOF
P2
H'040000FC
16
16
PACR
PORT
P
H'04000100
16
16
P
H'04000102
16
Size (Bits)
Module*1
Bus*2
Address*4
Size (Bits)
Access Size (Bits)*3
SIFPR
SIOF
P2
H'040000FE
16
16
PBCR
PORT
PACR
PORT
P
H'04000100
16
16
SDIR
H-UDI
I2
H'04000200
16
16
PBCR
PORT
P
H'04000102
16
16
IPRF
PPCNT
P2
H'04000220
16
16
16
16
SDIR
UDI
I2
H'04000200
16
16
IPRG
PPCNT
P2
H'04000222
16
SDDR/SDDRH
UDI
I2
H'04000208
16/32
16/32
P2
H'04000458
32
32
UDI
I2
H'0400020A
16
16
HcRhPortStatus2
(USBHRPS2)
USBH
SDDRL
IPRF
PPCNT
P2
H'04000220
16
16
LDPR00 to LDPRFF
LCDC
P2
H'04000800 to
H'04000BFC
32
32
LDICKR
LCDC
P2
H'04000C00
16
16
IPRG
PPCNT
P2
H'04000222
16
16
HcRhPortStatus2
(USBHRPS2)
USBH
P2
H'04000458
32
32
LDPR00
LCDC
P2
H'04000800
32
32
LDICKR
LCDC
P2
H'04000C00
16
16
Rev. 5.00 Dec 12, 2005 page xxx of lxxii
Page
1024
1025
Previous Version
Revised Version
Appendix C Product Lineup
Model Name
Package
Model Name
Package
HD6417727F160B
240-pin plastic HQFP
(FP-240B)
HD6417727F160C
240-pin plastic HQFP
(PRQP0240KC-B)
HD6417727BP160B
240-pin CSP
(BP-240A)
HD6417727BP160C
240-pin CSP
(PLBG0240JA-A)
HD6417727F100B
240-pin plastic HQFP
(FP-240B)
HD6417727F100C
240-pin plastic HQFP
(PRQP0240KC-B)
HD6417727BP100B
240-pin CSP
(BP-240A)
HD6417727BP100C
240-pin CSP
(PLBG0240JA-A)
Figure D.1 Package Dimensions
(FP-240B)
Figure D.1 Package Dimensions
(PRQP0240KC-B)
Replaced
1026
Figure D.2 Package Dimensions
(BP-240A)
Figure D.2 Package Dimensions
(PLBG0240JA-A)
Replaced
1027
E.1 Determining the Version Number
Based on the Markings on the Chip
(1) HQFP-240 Package
(1) HQPF-240 Package
Version Previous to SH7727B
Version Previous
to SH7727B
SH7727B
6417727
SH3-DSP
100
HITACHI
0124
BF80128 JAPAN
6417727
SH3-DSP
100
HITACHI B
0124
BF80128 JAPAN
6417727F
SH3-DSP
100
HITACHI
0124
BF80128 JAPAN
SH7727C
SH7727B
"B" indication
6417727F
SH3-DSP
100
HITACHI B
0124
BF80128 JAPAN
"B"
indication
6417727F
SH3-DSP
C
BF80128
"C"
indication
100
0124
Note: Once stocks bearing Hitachi markings are exhausted, chips bearing Renesas markings may begin
to appear.
(2) CSP-240 Package
Version Previous to SH7727B
(2) CSP-240 Package
SH7727B
Version Previous
to SH7727B
SH7727B
"B" indication
6417727BP
100
BF80128
0124 JAPAN
6417727BP
100
B
BF80128
0124 JAPAN
6417727BP
100
BF80128
0124 JAPAN
6417727BP
100
B
BF80128
0124 JAPAN
SH7727C
"B"
indication
6417727BP
100
C
BF80128
0124 JAPAN
"C"
indication
Rev. 5.00 Dec 12, 2005 page xxxi of lxxii
Rev. 5.00 Dec 12, 2005 page xxxii of lxxii
Contents
Section 1 Overview and Pin Functions .........................................................................
1.1
1.2
1.3
1
Features ............................................................................................................................. 1
Block Diagram .................................................................................................................. 8
Pin Description.................................................................................................................. 9
1.3.1 Pin Arrangement .................................................................................................. 9
1.3.2 Pin Functions ....................................................................................................... 11
Section 2 CPU ...................................................................................................................... 21
2.1
2.2
2.3
2.4
2.5
2.6
Registers............................................................................................................................
2.1.1 General Purpose Registers ...................................................................................
2.1.2 Control Registers .................................................................................................
2.1.3 System Registers..................................................................................................
2.1.4 DSP Registers ......................................................................................................
Data Format ......................................................................................................................
2.2.1 Data Format in Registers (Non-DSP Type) .........................................................
2.2.2 DSP-Type Data Format........................................................................................
2.2.3 Data Format in Memory.......................................................................................
Features of CPU Core Instructions....................................................................................
Instruction Formats ...........................................................................................................
2.4.1 CPU Instruction Addressing Modes.....................................................................
2.4.2 DSP Data Addressing ..........................................................................................
2.4.3 CPU Instruction Formats .....................................................................................
2.4.4 DSP Instruction Formats......................................................................................
Instruction Set ...................................................................................................................
2.5.1 CPU Instruction Set .............................................................................................
DSP Extended-Function Instructions ................................................................................
2.6.1 Introduction..........................................................................................................
2.6.2 Added CPU System Control Instructions.............................................................
2.6.3 Single and Double Data Transfer for DSP Data Instructions...............................
2.6.4 DSP Operation Instruction Set .............................................................................
21
25
27
31
31
38
38
38
40
40
44
44
48
54
58
64
64
79
79
80
82
85
Section 3 Memory Management Unit (MMU) ........................................................... 97
3.1
3.2
Overview...........................................................................................................................
3.1.1 Features................................................................................................................
3.1.2 Role of MMU.......................................................................................................
3.1.3 SH7727 MMU .....................................................................................................
3.1.4 Register Configuration.........................................................................................
Register Description..........................................................................................................
97
97
97
99
103
103
Rev. 5.00 Dec 12, 2005 page xxxiii of lxxii
3.3
3.4
3.5
3.6
3.7
TLB Functions ..................................................................................................................
3.3.1 Configuration of the TLB ....................................................................................
3.3.2 TLB Indexing.......................................................................................................
3.3.3 TLB Address Comparison ...................................................................................
3.3.4 Page Management Information ............................................................................
MMU Functions................................................................................................................
3.4.1 MMU Hardware Management .............................................................................
3.4.2 MMU Software Management ..............................................................................
3.4.3 MMU Instruction (LDTLB).................................................................................
3.4.4 Avoiding Synonym Problems ..............................................................................
MMU Exceptions..............................................................................................................
3.5.1 TLB Miss Exception ............................................................................................
3.5.2 TLB Protection Violation Exception ...................................................................
3.5.3 TLB Invalid Exception.........................................................................................
3.5.4 Initial Page Write Exception ................................................................................
3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow
for Address Error) ................................................................................................
3.5.6 MMU Exception in Repeat Loop.........................................................................
Memory-Mapped TLB......................................................................................................
3.6.1 Address Array ......................................................................................................
3.6.2 Data Array............................................................................................................
3.6.3 Usage Examples...................................................................................................
Usage Notes ......................................................................................................................
105
105
107
108
110
111
111
111
112
113
116
116
117
118
119
121
123
124
125
125
127
128
Section 4 Exception Handling ......................................................................................... 131
4.1
4.2
4.3
4.4
4.5
Overview...........................................................................................................................
4.1.1 Features................................................................................................................
4.1.2 Register Configuration.........................................................................................
Exception Handling Function ...........................................................................................
4.2.1 Exception Handling Flow ....................................................................................
4.2.2 Exception Handling Vector Addresses ................................................................
4.2.3 Acceptance of Exceptions....................................................................................
4.2.4 Exception Codes ..................................................................................................
4.2.5 Exception Request Masks ....................................................................................
4.2.6 Returning from Exception Handling....................................................................
Register Description..........................................................................................................
Exception Handling Operation..........................................................................................
4.4.1 Reset.....................................................................................................................
4.4.2 Interrupts..............................................................................................................
4.4.3 General Exceptions ..............................................................................................
Individual Exception Operations.......................................................................................
Rev. 5.00 Dec 12, 2005 page xxxiv of lxxii
131
131
131
131
131
132
134
136
137
138
138
139
139
139
140
140
4.6
4.5.1 Resets ...................................................................................................................
4.5.2 General Exceptions ..............................................................................................
4.5.3 Interrupts..............................................................................................................
Usage Notes ......................................................................................................................
140
141
146
147
Section 5 Cache .................................................................................................................... 149
5.1
5.2
5.3
5.4
5.5
Overview...........................................................................................................................
5.1.1 Features................................................................................................................
5.1.2 Cache Structure....................................................................................................
5.1.3 Register Configuration.........................................................................................
Register Description..........................................................................................................
5.2.1 Cache Control Register (CCR) ............................................................................
5.2.2 Cache Control Register 2 (CCR2)........................................................................
Cache Operation................................................................................................................
5.3.1 Searching the Cache.............................................................................................
5.3.2 Read Access .........................................................................................................
5.3.3 Prefetch Operations..............................................................................................
5.3.4 Write Access ........................................................................................................
5.3.5 Write-Back Buffer ...............................................................................................
5.3.6 Coherency of Cache and External Memory .........................................................
Memory-Mapped Cache....................................................................................................
5.4.1 Address Array ......................................................................................................
5.4.2 Data Array............................................................................................................
Usage Examples................................................................................................................
5.5.1 Invalidating Specific Entries ................................................................................
5.5.2 Reading the Data of a Specific Entry...................................................................
149
149
149
151
151
151
152
154
154
156
156
156
157
157
157
157
158
160
160
160
Section 6 X/Y Memory ...................................................................................................... 161
6.1
6.2
6.3
6.4
Overview...........................................................................................................................
6.1.1 Features................................................................................................................
X/Y Memory Access from the CPU .................................................................................
X/Y Memory Access from the DSP..................................................................................
X/Y Memory Access from the DMAC .............................................................................
161
161
162
164
164
Section 7 Interrupt Controller (INTC) ........................................................................... 165
7.1
7.2
Overview...........................................................................................................................
7.1.1 Features................................................................................................................
7.1.2 Block Diagram .....................................................................................................
7.1.3 Pin Configuration.................................................................................................
7.1.4 Register Configuration.........................................................................................
Interrupt Sources ...............................................................................................................
165
165
166
167
167
169
Rev. 5.00 Dec 12, 2005 page xxxv of lxxii
7.3
7.4
7.5
7.2.1 NMI Interrupts .....................................................................................................
7.2.2 IRQ Interrupt........................................................................................................
7.2.3 IRL Interrupts.......................................................................................................
7.2.4 PINT Interrupt......................................................................................................
7.2.5 On-Chip Supporting Module Interrupts ...............................................................
7.2.6 Interrupt Exception Handling and Priority...........................................................
INTC Registers .................................................................................................................
7.3.1 Interrupt Priority Registers A to G (IPRA to IPRG) ............................................
7.3.2 Interrupt Control Register 0 (ICR0).....................................................................
7.3.3 Interrupt Control Register 1 (ICR1).....................................................................
7.3.4 Interrupt Control Register 2 (ICR2).....................................................................
7.3.5 Interrupt Control Register 3 (ICR3).....................................................................
7.3.6 PINT Interrupt Enable Register (PINTER)..........................................................
7.3.7 Interrupt Request Register 0 (IRR0) ....................................................................
7.3.8 Interrupt Request Register 1 (IRR1) ....................................................................
7.3.9 Interrupt Request Register 2 (IRR2) ....................................................................
7.3.10 Interrupt Request Register 3 (IRR3) ....................................................................
7.3.11 Interrupt Request Register 4 (IRR4) ....................................................................
INTC Operation ................................................................................................................
7.4.1 Interrupt Sequence ...............................................................................................
7.4.2 Multiple Interrupts ...............................................................................................
Interrupt Response Time ...................................................................................................
169
169
170
172
172
173
179
179
180
181
184
185
187
187
190
191
192
195
197
197
199
199
Section 8 User Break Controller ..................................................................................... 203
8.1
8.2
Overview...........................................................................................................................
8.1.1 Features................................................................................................................
8.1.2 Block Diagram .....................................................................................................
8.1.3 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
8.2.1 Break Address Register A (BARA) .....................................................................
8.2.2 Break Address Mask Register A (BAMRA)........................................................
8.2.3 Break Bus Cycle Register A (BBRA) ..................................................................
8.2.4 Break Address Register B (BARB)......................................................................
8.2.5 Break Address Mask Register B (BAMRB) ........................................................
8.2.6 Break Data Register B (BDRB) ...........................................................................
8.2.7 Break Data Mask Register B (BDMRB)..............................................................
8.2.8 Break Bus Cycle Register B (BBRB) ..................................................................
8.2.9 Break Control Register (BRCR) ..........................................................................
8.2.10 Execution Times Break Register (BETR)............................................................
8.2.11 Branch Source Register (BRSR)..........................................................................
8.2.12 Branch Destination Register (BRDR) ..................................................................
Rev. 5.00 Dec 12, 2005 page xxxvi of lxxii
203
203
204
205
206
206
206
207
209
210
211
212
213
215
218
219
220
8.3
8.2.13 Break ASID Register A (BASRA).......................................................................
8.2.14 Break ASID Register B (BASRB) .......................................................................
Operation Description .......................................................................................................
8.3.1 Flow of the User Break Operation .......................................................................
8.3.2 Break on Instruction Fetch Cycle.........................................................................
8.3.3 Break by Data Access Cycle ................................................................................
8.3.4 Break on X/Y-Memory Bus Cycle.......................................................................
8.3.5 Sequential Break ..................................................................................................
8.3.6 Value of Saved Program Counter ........................................................................
8.3.7 PC Trace ..............................................................................................................
8.3.8 Usage Examples...................................................................................................
8.3.9 Usage Notes .........................................................................................................
221
221
222
222
222
223
224
224
224
225
227
231
Section 9 Power-Down Modes and Software Reset .................................................. 233
9.1
9.2
9.3
9.4
9.5
9.6
9.7
Overview...........................................................................................................................
9.1.1 Power-Down Modes ............................................................................................
9.1.2 Pin Configuration.................................................................................................
9.1.3 Register Configuration.........................................................................................
Register Description..........................................................................................................
9.2.1 Standby Control Register (STBCR).....................................................................
9.2.2 Standby Control Register 2 (STBCR2)................................................................
9.2.3 Standby Control Register 3 (STBCR3)................................................................
9.2.4 Module Software Reset Register (SRSTR)..........................................................
Sleep Mode .......................................................................................................................
9.3.1 Transition to Sleep Mode.....................................................................................
9.3.2 Canceling Sleep Mode .........................................................................................
Standby Mode ...................................................................................................................
9.4.1 Transition to Standby Mode.................................................................................
9.4.2 Canceling Standby Mode .....................................................................................
9.4.3 Clock Pause Function ..........................................................................................
Module Standby Function .................................................................................................
9.5.1 Transition to Module Standby Function...............................................................
9.5.2 Clearing the Module Standby Function ...............................................................
Timing of STATUS Pin Changes......................................................................................
9.6.1 Timing for Resets.................................................................................................
9.6.2 Timing for Canceling Standbys ...........................................................................
9.6.3 Timing for Canceling Sleep Mode.......................................................................
Hardware Standby Mode ..................................................................................................
9.7.1 Transition to Hardware Standby Mode ................................................................
9.7.2 Clearing the Hardware Standby Mode.................................................................
9.7.3 Timing of Hardware Standby Mode ....................................................................
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Section 10 On-Chip Oscillation Circuits ...................................................................... 257
10.1 Overview...........................................................................................................................
10.1.1 Features................................................................................................................
10.2 Overview of the CPG........................................................................................................
10.2.1 CPG Block Diagram ............................................................................................
10.2.2 CPG Pin Configuration ........................................................................................
10.2.3 CPG Register Configuration ................................................................................
10.3 Clock Operating Modes ....................................................................................................
10.4 Register Descriptions ........................................................................................................
10.4.1 Frequency Control Register (FRQCR).................................................................
10.4.2 CKIO2 Control Register (CKIO2CR)..................................................................
10.5 Changing the Frequency ...................................................................................................
10.5.1 Changing the Multiplication Rate ........................................................................
10.5.2 Changing the Division Ratio................................................................................
10.6 Overview of the WDT.......................................................................................................
10.6.1 Block Diagram of the WDT.................................................................................
10.6.2 Register Configurations .......................................................................................
10.7 WDT Registers..................................................................................................................
10.7.1 Watchdog Timer Counter (WTCNT)...................................................................
10.7.2 Watchdog Timer Control/Status Register (WTCSR)...........................................
10.7.3 Notes on Register Access.....................................................................................
10.8 Using the WDT .................................................................................................................
10.8.1 Canceling Standby Mode .....................................................................................
10.8.2 Changing the Frequency ......................................................................................
10.8.3 Using Watchdog Timer Mode..............................................................................
10.8.4 Using Interval Timer Mode..................................................................................
10.9 Notes on Board Design .....................................................................................................
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Section 11 Extend Clock Pulse Generator for USB (EXCPG) .............................. 279
11.1 Overview...........................................................................................................................
11.1.1 EXCPG ................................................................................................................
11.2 Functions...........................................................................................................................
11.2.1 Block Diagram .....................................................................................................
11.2.2 Pin Configuration.................................................................................................
11.2.3 Register Configuration.........................................................................................
11.3 Register Descriptions ........................................................................................................
11.3.1 EXCPG Control Register (EXCPGCR) ...............................................................
11.4 Usage Notes ......................................................................................................................
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Section 12 Bus State Controller (BSC) .........................................................................
12.1 Overview...........................................................................................................................
12.1.1 Features................................................................................................................
12.1.2 Block Diagram .....................................................................................................
12.1.3 Pin Configuration.................................................................................................
12.1.4 Register Configuration.........................................................................................
12.1.5 Area Overview .....................................................................................................
12.1.6 PC Card Support ..................................................................................................
12.2 BSC Registers ...................................................................................................................
12.2.1 Bus Control Register 1 (BCR1) ...........................................................................
12.2.2 Bus Control Register 2 (BCR2) ...........................................................................
12.2.3 Wait State Control Register 1 (WCR1)................................................................
12.2.4 Wait State Control Register 2 (WCR2)................................................................
12.2.5 Individual Memory Control Register (MCR).......................................................
12.2.6 PCMCIA Control Register (PCR)........................................................................
12.2.7 Synchronous DRAM Mode Register (SDMR) ....................................................
12.2.8 Refresh Timer Control/Status Register (RTCSR) ................................................
12.2.9 Refresh Timer Counter (RTCNT)........................................................................
12.2.10 Refresh Time Constant Register (RTCOR) .........................................................
12.2.11 Refresh Count Register (RFCR) ..........................................................................
12.2.12 Cautions on Accessing Refresh Control Related Registers..................................
12.3 BSC Operation ..................................................................................................................
12.3.1 Endian/Access Size and Data Alignment.............................................................
12.3.2 Description of Areas ............................................................................................
12.3.3 Basic Interface .....................................................................................................
12.3.4 Synchronous DRAM Interface.............................................................................
12.3.5 Burst ROM Interface............................................................................................
12.3.6 PCMCIA Interface ...............................................................................................
12.3.7 Waits between Access Cycles..............................................................................
12.3.8 Bus Arbitration.....................................................................................................
12.3.9 Bus Pull-Up..........................................................................................................
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Section 13 Li Bus State Controller (LBSC) .................................................................
13.1 Overview...........................................................................................................................
13.1.1 Features................................................................................................................
13.1.2 Register Configuration.........................................................................................
13.1.3 Bus Control Register 1 (BCR1) ...........................................................................
13.1.4 Bus Control Register 2 (BCR2) ...........................................................................
13.1.5 Wait State Control Register 1 (WCR1)................................................................
13.1.6 Wait State Control Register 2 (WCR2)................................................................
13.1.7 Individual Memory Control Register (MCR).......................................................
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13.2 LBSC Operation................................................................................................................
13.2.1 Bus Sharing Architecture .....................................................................................
13.2.2 Usable System Memory .......................................................................................
13.2.3 Bus Arbitration.....................................................................................................
13.2.4 LCDC Li Bus Access...........................................................................................
13.2.5 USBH Li Bus Access...........................................................................................
13.2.6 Setting of DMA Transfer with Bus Arbitration of Other Module........................
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Section 14 Direct Memory Access Controller (DMAC) ..........................................
14.1 Overview...........................................................................................................................
14.1.1 Features................................................................................................................
14.1.2 Block Diagram .....................................................................................................
14.1.3 Pin Configuration.................................................................................................
14.1.4 Register Configuration.........................................................................................
14.2 Register Descriptions ........................................................................................................
14.2.1 DMA Source Address Registers 0 to 3 (SAR0 to SAR3) ....................................
14.2.2 DMA Destination Address Registers 0 to 3 (DAR0 to DAR3)............................
14.2.3 DMA Transfer Count Registers 0 to 3 (DMATCR0 to DMATCR3) ..................
14.2.4 DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3).............................
14.2.5 DMA Channel Request Assign Register (CHRAR )............................................
14.2.6 DMA Operation Register (DMAOR)...................................................................
14.3 Operation...........................................................................................................................
14.3.1 DMA Transfer Flow.............................................................................................
14.3.2 DMA Transfer Requests ......................................................................................
14.3.3 Channel Priority ...................................................................................................
14.3.4 DMA Transfer Types ...........................................................................................
14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ..........................
14.3.6 Source Address Reload Function .........................................................................
14.3.7 DMA Transfer Ending .........................................................................................
14.4 Compare-Match Timer (CMT) .........................................................................................
14.4.1 Overview..............................................................................................................
14.4.2 Register Descriptions ...........................................................................................
14.4.3 Operation .............................................................................................................
14.4.4 Compare-Match ...................................................................................................
14.5 Examples for Use ..............................................................................................................
14.5.1 Example of DMA Transfer between A/D Converter and External Memory
(Address Reload on) ............................................................................................
14.5.2 Example of DMA Transfer between External Memory and SCIF Transmitter
(Indirect Address on) ...........................................................................................
14.6 Usage Notes ......................................................................................................................
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Section 15 Timer (TMU) ...................................................................................................
15.1 Overview...........................................................................................................................
15.1.1 Features................................................................................................................
15.1.2 Block Diagram .....................................................................................................
15.1.3 Register Configuration.........................................................................................
15.2 TMU Registers..................................................................................................................
15.2.1 Timer Start Register (TSTR)................................................................................
15.2.2 Timer Control Register (TCR) .............................................................................
15.2.3 Timer Constant Register (TCOR) ........................................................................
15.2.4 Timer Counters (TCNT) ......................................................................................
15.3 TMU Operation.................................................................................................................
15.3.1 Overview..............................................................................................................
15.3.2 Basic Functions....................................................................................................
15.4 Interrupts ...........................................................................................................................
15.4.1 Status Flag Set Timing.........................................................................................
15.4.2 Status Flag Clear Timing .....................................................................................
15.4.3 Interrupt Sources and Priorities............................................................................
15.5 Usage Notes ......................................................................................................................
15.5.1 Writing to Registers .............................................................................................
15.5.2 Reading Registers ................................................................................................
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453
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Section 16 Realtime Clock (RTC) .................................................................................. 457
16.1 Overview...........................................................................................................................
16.1.1 Features................................................................................................................
16.1.2 Block Diagram .....................................................................................................
16.1.3 Pin Configuration.................................................................................................
16.1.4 RTC Register Configuration ................................................................................
16.2 Register Descriptions ........................................................................................................
16.2.1 64-Hz Counter (R64CNT) ...................................................................................
16.2.2 Second Counter (RSECCNT) ..............................................................................
16.2.3 Minute Counter (RMINCNT) ..............................................................................
16.2.4 Hour Counter (RHRCNT)....................................................................................
16.2.5 Day of the Week Counter (RWKCNT)................................................................
16.2.6 Date Counter (RDAYCNT) .................................................................................
16.2.7 Month Counter (RMONCNT) .............................................................................
16.2.8 Year Counter (RYRCNT) ....................................................................................
16.2.9 Second Alarm Register (RSECAR) .....................................................................
16.2.10 Minute Alarm Register (RMINAR) .....................................................................
16.2.11 Hour Alarm Register (RHRAR)...........................................................................
16.2.12 Day of the Week Alarm Register (RWKAR).......................................................
16.2.13 Date Alarm Register (RDAYAR) ........................................................................
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16.2.14 Month Alarm Register (RMONAR) ....................................................................
16.2.15 RTC Control Register 1 (RCR1)..........................................................................
16.2.16 RTC Control Register 2 (RCR2)..........................................................................
16.3 RTC Operation..................................................................................................................
16.3.1 Initial Settings of Registers after Power-On ........................................................
16.3.2 Setting the Time...................................................................................................
16.3.3 Reading the Time.................................................................................................
16.3.4 Alarm Function ....................................................................................................
16.3.5 Crystal Oscillator Circuit .....................................................................................
16.4 Usage Notes ......................................................................................................................
16.4.1 Writing Registers During RTC Count Operation.................................................
16.4.2 RTC Periodic Interrupts .......................................................................................
16.4.3 Using the ADJ Bit in the Real Time Clock (RTC) ..............................................
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478
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479
Section 17 Serial Communication Interface (SCI) .................................................... 481
17.1 Overview...........................................................................................................................
17.1.1 Features................................................................................................................
17.1.2 Block Diagram .....................................................................................................
17.1.3 Pin Configuration.................................................................................................
17.1.4 Register Configuration.........................................................................................
17.2 Register Descriptions ........................................................................................................
17.2.1 Receive Shift Register (SCRSR)..........................................................................
17.2.2 Receive Data Register (SCRDR) .........................................................................
17.2.3 Transmit Shift Register (SCTSR) ........................................................................
17.2.4 Transmit Data Register (SCTDR)........................................................................
17.2.5 Serial Mode Register (SCSMR)...........................................................................
17.2.6 Serial Control Register (SCSCR).........................................................................
17.2.7 Serial Status Register (SCSSR)............................................................................
17.2.8 Port SC Control Register (SCPCR)/Port SC Data Register (SCPDR) .................
17.2.9 Bit Rate Register (SCBRR)..................................................................................
17.3 Operation...........................................................................................................................
17.3.1 Overview..............................................................................................................
17.3.2 Operation in Asynchronous Mode .......................................................................
17.3.3 Multiprocessor Communication...........................................................................
17.3.4 Clock Synchronous Operation .............................................................................
17.4 SCI Interrupt Sources........................................................................................................
17.5 Usage Notes ......................................................................................................................
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511
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538
539
Section 18 Smart Card Interface ..................................................................................... 543
18.1 Overview........................................................................................................................... 543
18.1.1 Features................................................................................................................ 543
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18.1.2 Block Diagram .....................................................................................................
18.1.3 Pin Configuration.................................................................................................
18.1.4 Register Configuration.........................................................................................
18.2 Register Descriptions ........................................................................................................
18.2.1 Smart Card Mode Register (SCSCMR) ...............................................................
18.2.2 Serial Status Register (SCSSR)............................................................................
18.3 Operation...........................................................................................................................
18.3.1 Overview..............................................................................................................
18.3.2 Pin Connections ...................................................................................................
18.3.3 Data Format .........................................................................................................
18.3.4 Register Settings ..................................................................................................
18.3.5 Clock....................................................................................................................
18.3.6 Data Transmission and Reception........................................................................
18.4 Usage Notes ......................................................................................................................
18.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode ....................
18.4.2 Retransmission (Receive and Transmit Modes)...................................................
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Section 19 Serial Communication Interface with FIFO (SCIF)............................. 565
19.1 Overview...........................................................................................................................
19.1.1 Features................................................................................................................
19.1.2 Block Diagram .....................................................................................................
19.1.3 Pin Configuration.................................................................................................
19.1.4 Register Configuration.........................................................................................
19.2 Register Descriptions ........................................................................................................
19.2.1 Receive Shift Register 2 (SCRSR2).....................................................................
19.2.2 Receive FIFO Data Register 2 (SCFRDR2) ........................................................
19.2.3 Transmit Shift Register 2 (SCTSR2) ...................................................................
19.2.4 Transmit FIFO Data Register 2 (SCFTDR2) .......................................................
19.2.5 Serial Mode Register 2 (SCSMR2)......................................................................
19.2.6 Serial Control Register 2 (SCSCR2)....................................................................
19.2.7 Serial Status Register 2 (SCSSR2).......................................................................
19.2.8 Bit Rate Register 2 (SCBRR2).............................................................................
19.2.9 FIFO Control Register 2 (SCFCR2) ....................................................................
19.2.10 FIFO Data Count Set Register 2 (SCFDR2) ........................................................
19.3 Operation...........................................................................................................................
19.3.1 Overview..............................................................................................................
19.3.2 Serial Operation ...................................................................................................
19.4 SCIF Interrupts..................................................................................................................
19.5 Usage Notes ......................................................................................................................
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Section 20 Serial IO (SIOF) ............................................................................................. 605
20.1 Overview...........................................................................................................................
20.1.1 Features................................................................................................................
20.1.2 Block Diagram .....................................................................................................
20.1.3 Terminal...............................................................................................................
20.1.4 Register Configuration.........................................................................................
20.2 Register Description..........................................................................................................
20.2.1 Mode Register (SIMDR)......................................................................................
20.2.2 Clock Select Register (SISCR) ............................................................................
20.2.3 Transmit Data Assign Register (SITDAR) ..........................................................
20.2.4 Receive Data Assign Register (SIRDAR)............................................................
20.2.5 Control Command Assign Register (SICDAR) ...................................................
20.2.6 Serial Control Register (SICTR)..........................................................................
20.2.7 FIFO Control Register (SIFCTR) ........................................................................
20.2.8 Status Register (SISTR) .......................................................................................
20.2.9 Interrupt Enable Register (SIIER)........................................................................
20.2.10 Transmit Data Register (SITDR) .........................................................................
20.2.11 Receive Data Register (SIRDR)...........................................................................
20.2.12 Transmit Control Data Register (SITCR) ............................................................
20.2.13 Receive Control Data Register (SIRCR)..............................................................
20.3 Operation...........................................................................................................................
20.3.1 Serial Clock..........................................................................................................
20.3.2 Serial Timing .......................................................................................................
20.3.3 Transmit Data Format ..........................................................................................
20.3.4 Register Assignment for Transfer Data................................................................
20.3.5 Control Data Interface..........................................................................................
20.3.6 FIFO.....................................................................................................................
20.3.7 Procedures for Transmit or Receive.....................................................................
20.3.8 Interrupt ...............................................................................................................
20.3.9 Transmit or Receive Timing ................................................................................
20.4 Usage Notes ......................................................................................................................
20.4.1 Notes on Using the SIOF with Versions Previous to the SH7727B.....................
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Section 21 Analog Front End Interface (AFEIF) ....................................................... 657
21.1 Overview...........................................................................................................................
21.1.1 Features................................................................................................................
21.1.2 Block Diagram .....................................................................................................
21.1.3 Pin Configuration.................................................................................................
21.1.4 Register Configuration.........................................................................................
21.2 Register Description..........................................................................................................
Rev. 5.00 Dec 12, 2005 page xliv of lxxii
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21.2.1 AFEIF Control Register 1 and 2 (ACTR1, ACTR2) ...........................................
21.2.2 Make Ratio Count Register (MRCR)...................................................................
21.2.3 Minimum Pause Count Register (MPCR)............................................................
21.2.4 AFEIF Status Register 1 and 2 (ASTR1, ASTR2)...............................................
21.2.5 Dial Pulse Number Queue (DPNQ) .....................................................................
21.2.6 Ringing Pulse Counter (RCNT) ...........................................................................
21.2.7 AFE Control Data Register (ACDR) ...................................................................
21.2.8 AFE Status Data Register (ASDR) ......................................................................
21.2.9 Transmit Data FIFO Port (TDFP) ........................................................................
21.2.10 Receive Data FIFO Port (RDFP) .........................................................................
21.3 Operation...........................................................................................................................
21.3.1 Interrupt Timing...................................................................................................
21.3.2 AFE Interface.......................................................................................................
21.3.3 DAA Interface......................................................................................................
21.3.4 Wake up Ringing Interrupt ..................................................................................
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Section 22 USB Pin Multiplex Controller ....................................................................
22.1 Feature...............................................................................................................................
22.1.1 Block Diagram .....................................................................................................
22.1.2 Pin Configuration.................................................................................................
22.1.3 Register Configuration.........................................................................................
22.2 Register Description..........................................................................................................
22.2.1 Extra Pin Function Controller (EXPFC) ..............................................................
22.3 Examples of External Circuit ............................................................................................
22.3.1 Example of the Connection between USB Function Controller and Transceiver
22.3.2 Example of the Connection between USB Host Controller and Transceiver.......
22.3.3 Usage Notes .........................................................................................................
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690
Section 23 USB Function Controller ............................................................................. 691
23.1
23.2
23.3
23.4
23.5
Features .............................................................................................................................
Block Diagram ..................................................................................................................
Pin Configuration..............................................................................................................
Register Configuration ......................................................................................................
Register Descriptions ........................................................................................................
23.5.1 USBEP0i Data Register (USBEPDR0I) ..............................................................
23.5.2 USBEP0o Data Register (USBEPDR0O) ............................................................
23.5.3 USBEP0s Data Register (USBEPDR0S) .............................................................
23.5.4 USBEP1 Data Register (USBEPDR1).................................................................
23.5.5 USBEP2 Data Register (USBEPDR2).................................................................
23.5.6 USBEP3 Data Register (USBEPDR3).................................................................
23.5.7 USB Interrupt Flag Register 0 (USBIFR0) ..........................................................
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23.6
23.7
23.8
23.9
23.5.8 USB Interrupt Flag Register 1 (USBIFR1) ..........................................................
23.5.9 USB Trigger Register (USBTRG) .......................................................................
23.5.10 USBFIFO Clear Register (USBFCLR) ................................................................
23.5.11 USBEP0o Receive Data Size Register (USBEPSZ0O) .......................................
23.5.12 USB Data Status Register (USBDASTS) ............................................................
23.5.13 USB Endpoint Stall Register (USBEPSTL) ........................................................
23.5.14 USB Interrupt Enable Register 0 (USBIER0)......................................................
23.5.15 USB Interrupt Enable Register 1 (USBIER1)......................................................
23.5.16 USBEP1 Receive Data Size Register (USBEPSZ1) ............................................
23.5.17 USB Interrupt Select Register 0 (USBISR0) .......................................................
23.5.18 USB Interrupt Select Register 1 (USBISR1) .......................................................
23.5.19 USBDMA Setting Register (USBDMAR)...........................................................
Operation...........................................................................................................................
23.6.1 Cable Connection.................................................................................................
23.6.2 Cable Disconnection ............................................................................................
23.6.3 Control Transfer...................................................................................................
23.6.4 EP1 Bulk-Out Transfer (Dual FIFOs)..................................................................
23.6.5 EP2 Bulk-In Transfer (Dual FIFOs) ....................................................................
23.6.6 EP3 Interrupt-In Transfer.....................................................................................
Processing of USB Standard Commands and Class/Vendor Commands..........................
23.7.1 Processing of Commands Transmitted by Control Transfer ................................
Stall Operations.................................................................................................................
23.8.1 Overview..............................................................................................................
23.8.2 Forcible Stall by Application ...............................................................................
23.8.3 Automatic Stall by USB Function Module ..........................................................
Usage Notes ......................................................................................................................
23.9.1 Receiving Setup Data...........................................................................................
23.9.2 Clearing the FIFO ................................................................................................
23.9.3 Overreading and Overwriting the Data Registers ................................................
23.9.4 Assigning Interrupt Sources to EP0 .....................................................................
23.9.5 Clearing the FIFO when DMA Transfer Is Enabled ............................................
23.9.6 Notes on TR Interrupt ..........................................................................................
23.9.7 Peripheral Clock (Pφ) Operation Frequency ........................................................
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Section 24 USB HOST Module ...................................................................................... 725
24.1 General Description ..........................................................................................................
24.1.1 Features................................................................................................................
24.1.2 Pin Configuration.................................................................................................
24.1.3 Register Configuration.........................................................................................
24.2 Register Description..........................................................................................................
24.2.1 HcRevision...........................................................................................................
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24.3
24.4
24.5
24.6
24.7
24.2.2 HcControl.............................................................................................................
24.2.3 HcCommandStatus ..............................................................................................
24.2.4 HcInterruptStatus .................................................................................................
24.2.5 HcInterruptEnable................................................................................................
24.2.6 HcInterruptDisable...............................................................................................
24.2.7 HcHCCA..............................................................................................................
24.2.8 HcPeriodCurrentED.............................................................................................
24.2.9 HcControlHeadED...............................................................................................
24.2.10 HcControlCurrentED ...........................................................................................
24.2.11 HcBulkHeadED ...................................................................................................
24.2.12 HcBulkCurrentED................................................................................................
24.2.13 HcDoneHead........................................................................................................
24.2.14 HcFmInterval .......................................................................................................
24.2.15 HcFmRemaining ..................................................................................................
24.2.16 HcFmNumber ......................................................................................................
24.2.17 HcPeriodicStart....................................................................................................
24.2.18 HcLSThreshold ....................................................................................................
24.2.19 HcRhDescriptorA ................................................................................................
24.2.20 HcRhDescriptorB.................................................................................................
24.2.21 HcRhStatus ..........................................................................................................
24.2.22 HcRhPortStatus[1:2] ............................................................................................
Data Storage Format which Required by USB Host Controller........................................
24.3.1 Storage Format of the Transferred Data...............................................................
24.3.2 Storage Format of the Descriptor.........................................................................
Data Alignment Restriction of USB Host Controller........................................................
24.4.1 Restriction on the Line Boundary of the Synchronous DRAM ...........................
24.4.2 Restriction on the Memory Access Address ........................................................
Restrictions on the Data Transfer of USB Controller .......................................................
24.5.1 Restriction of the Data Size in IN Transfer..........................................................
24.5.2 Restrictions on the Hub Connection on NAK/STALL Reception .......................
24.5.3 Restrictions when a Low-Speed Device is Disconnected ....................................
Restrictions on the Software Reset and USB Reset ..........................................................
Notes on Using USB Host with Versions Previous to the SH7727C................................
729
732
735
737
739
740
740
741
741
741
742
742
743
744
745
746
746
747
749
750
751
757
757
758
758
758
759
759
759
759
760
760
760
Section 25 LCD Controller ............................................................................................... 763
25.1 Overview...........................................................................................................................
25.1.1 Features................................................................................................................
25.1.2 Block Diagram .....................................................................................................
25.1.3 Pin Configuration.................................................................................................
25.1.4 Register Configuration.........................................................................................
25.2 Register Descriptions ........................................................................................................
763
763
764
765
765
767
Rev. 5.00 Dec 12, 2005 page xlvii of lxxii
25.2.1 LCDC Input Clock Register (LDICKR) ..............................................................
25.2.2 LCDC Module Type Register (LDMTR) ............................................................
25.2.3 LCDC Data Format Register (LDDFR) ...............................................................
25.2.4 LCDC Scan Mode Register (LDSMR) ................................................................
25.2.5 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ..........
25.2.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) ..........
25.2.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ..........
25.2.8 LCDC Palette Control Register (LDPALCR) ......................................................
25.2.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ......................................
25.2.10 LCDC Horizontal Character Number Register (LDHCNR) ................................
25.2.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ........................................
25.2.12 LCDC Vertical Display Line Number Register (LDVDLNR).............................
25.2.13 LCDC Vertical Total Line Number Register (LDVTLNR) .................................
25.2.14 LCDC Vertical Sync Signal Register (LDVSYNR) ............................................
25.2.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ......
25.2.16 LCDC Interrupt Control Register (LDINTR) ......................................................
25.2.17 LCDC Power Management Mode Register (LDPMMR).....................................
25.2.18 LCDC Power-Supply Sequence Period Register (LDPSPR) ...............................
25.2.19 LCDC Control Register (LDCNTR)....................................................................
25.3 Operation...........................................................................................................................
25.3.1 LCD Module Sizes which can be Displayed in this LCDC .................................
25.3.2 Limits on the Resolution of Rotated Displays, Burst Length, and Connected
Memory (SDRAM) ..............................................................................................
25.3.3 Color Palette Specification...................................................................................
25.3.4 Data Format .........................................................................................................
25.3.5 Timing Controller Register ..................................................................................
25.3.6 Power Management Registers..............................................................................
25.3.7 Operation for Hardware Rotation.........................................................................
25.4 Clock and LCD Data Signal Examples .............................................................................
25.5 Usage Notes ......................................................................................................................
767
768
771
773
774
775
776
777
778
779
780
781
782
783
784
784
786
788
789
790
790
791
797
799
802
802
807
809
820
Section 26 Pin Function Controller (PFC) ................................................................... 821
26.1 Overview........................................................................................................................... 821
26.2 Register Configuration ...................................................................................................... 826
26.3 Register Descriptions ........................................................................................................ 827
26.3.1 Port A Control Register (PACR).......................................................................... 827
26.3.2 Port B Control Register (PBCR) .......................................................................... 828
26.3.3 Port C Control Register (PCCR) .......................................................................... 829
26.3.4 Port D Control Register (PDCR).......................................................................... 830
26.3.5 Port E Control Register (PECR) .......................................................................... 831
26.3.6 Port F Control Register (PFCR)........................................................................... 832
Rev. 5.00 Dec 12, 2005 page xlviii of lxxii
26.3.7 Port G Control Register (PGCR)..........................................................................
26.3.8 Port H Control Register (PHCR)..........................................................................
26.3.9 Port J Control Register (PJCR) ............................................................................
26.3.10 Port K Control Register (PKCR)..........................................................................
26.3.11 Port L Control Register (PLCR) ..........................................................................
26.3.12 Port M Control Register (PMCR) ........................................................................
26.3.13 SC Port Control Register (SCPCR)......................................................................
833
835
836
837
838
839
840
Section 27 I/O Ports ............................................................................................................ 845
27.1 Overview........................................................................................................................... 845
27.2 Register Configuration ...................................................................................................... 846
27.3 Ports A to C, E, J, K.......................................................................................................... 847
27.3.1 Ports A to C, E, J, K Data Rgister
(PADR, PBDR, PCDR, PEDR, PJDR, PKDR) ................................................... 847
27.4 Port D................................................................................................................................ 848
27.4.1 Port D Data Register (PDDR) .............................................................................. 848
27.5 Ports F, M ......................................................................................................................... 850
27.5.1 Ports F, M Data Register (PFDR, PMDR) ........................................................... 850
27.6 Port G................................................................................................................................ 851
27.6.1 Port G Data Register (PGDR) .............................................................................. 851
27.7 Port H................................................................................................................................ 852
27.7.1 Port H Data Register (PHDR) .............................................................................. 852
27.8 Port L ................................................................................................................................ 854
27.8.1 Port L Data Register (PLDR)............................................................................... 854
27.9 SC Port.............................................................................................................................. 855
27.9.1 Port SC Data Register (SCPDR) .......................................................................... 855
Section 28 A/D Converter ................................................................................................. 857
28.1 Overview...........................................................................................................................
28.1.1 Features................................................................................................................
28.1.2 Block Diagram .....................................................................................................
28.1.3 Input Pins .............................................................................................................
28.1.4 Register Configuration.........................................................................................
28.2 Register Descriptions ........................................................................................................
28.2.1 A/D Data Registers A to D (ADDRA to ADDRD)..............................................
28.2.2 A/D Control/Status Register (ADCSR) ...............................................................
28.2.3 A/D Control Register (ADCR) ............................................................................
28.3 Bus Master Interface .........................................................................................................
28.4 Operation...........................................................................................................................
28.4.1 Single Mode (MULTI = 0) ..................................................................................
28.4.2 Multi Mode (MULTI = 1, SCN = 0)....................................................................
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858
859
860
861
861
862
864
865
867
867
869
Rev. 5.00 Dec 12, 2005 page xlix of lxxii
28.4.3 Scan Mode (MULTI = 1, SCN = 1) .....................................................................
28.4.4 Input Sampling and A/D Conversion Time..........................................................
28.4.5 External Trigger Input Timing .............................................................................
28.5 Interrupts ...........................................................................................................................
28.6 Definitions of A/D Conversion Accuracy .........................................................................
28.7 Usage Notes ......................................................................................................................
28.7.1 Setting Analog Input Voltage ..............................................................................
28.7.2 Processing of Analog Input Pins ..........................................................................
28.7.3 Access Size and Read Data..................................................................................
871
873
874
875
875
876
876
876
877
Section 29 D/A Converter ................................................................................................. 879
29.1 Overview...........................................................................................................................
29.1.1 Features................................................................................................................
29.1.2 Block Diagram .....................................................................................................
29.1.3 I/O Pins ................................................................................................................
29.1.4 Register Configuration.........................................................................................
29.2 Register Descriptions ........................................................................................................
29.2.1 D/A Data Registers 0 and 1 (DADR0/1)..............................................................
29.2.2 D/A Control Register (DACR) ............................................................................
29.3 Operation...........................................................................................................................
879
879
879
880
880
881
881
881
883
Section 30 PC Card Controller (PCC) ........................................................................... 885
30.1 Overview...........................................................................................................................
30.1.1 Features................................................................................................................
30.1.2 Block Diagram .....................................................................................................
30.1.3 Register Configuration.........................................................................................
30.1.4 PCMCIA Support.................................................................................................
30.2 Register Descriptions ........................................................................................................
30.2.1 Area 6 Interface Status Register (PCC0ISR) .......................................................
30.2.2 Area 6 General Control Register (PCC0GCR) ....................................................
30.2.3 Area 6 Card Status Change Register (PCC0CSCR).............................................
30.2.4 Area 6 Card Status Change Interrupt Enable Register (PCC0CSCIER) ..............
30.3 Operation...........................................................................................................................
30.3.1 PC card Connection Specification (Interface Diagram, Pin Correspondence).....
30.3.2 PC Card Interface Timing ....................................................................................
30.3.3 Usage Notes .........................................................................................................
885
885
886
887
888
891
891
894
896
900
903
903
907
912
Section 31 User-Debugging Interface (H-UDI).......................................................... 915
31.1 Overview........................................................................................................................... 915
31.2 User Debugging Interface (H-UDI) .................................................................................. 915
31.2.1 Pin Description..................................................................................................... 915
Rev. 5.00 Dec 12, 2005 page l of lxxii
31.2.2 Block Diagram .....................................................................................................
31.3 Register Descriptions ........................................................................................................
31.3.1 Bypass Register (SDBPR) ...................................................................................
31.3.2 Instruction Register (SDIR) .................................................................................
31.3.3 Boundary-Scan Register (SDBSR) ......................................................................
31.4 H-UDI Operations.............................................................................................................
31.4.1 TAP Controller ....................................................................................................
31.4.2 Reset Configuration .............................................................................................
31.4.3 H-UDI Reset ........................................................................................................
31.4.4 H-UDI Interrupt ...................................................................................................
31.4.5 Bypass..................................................................................................................
31.4.6 Using H-UDI to Recover from Sleep Mode........................................................
31.5 Usage Notes ......................................................................................................................
31.6 Advanced User Debugger (AUD) .....................................................................................
916
916
917
917
918
925
925
926
927
927
927
927
928
928
Section 32 Electrical Characteristics.............................................................................. 929
32.1 Absolute Maximum Ratings .............................................................................................
32.2 DC Characteristics ............................................................................................................
32.3 AC Characteristics ............................................................................................................
32.3.1 Clock Timing .......................................................................................................
32.3.2 Control Signal Timing .........................................................................................
32.3.3 AC Bus Timing ....................................................................................................
32.3.4 Basic Timing........................................................................................................
32.3.5 Burst ROM Timing ..............................................................................................
32.3.6 Synchronous DRAM Timing ...............................................................................
32.3.7 PCMCIA Timing .................................................................................................
32.3.8 Peripheral Module Signal Timing........................................................................
32.3.9 H-UDI-Related Pin Timing..................................................................................
32.3.10 LCDC Timing ......................................................................................................
32.3.11 SIOF Module Signal Timing................................................................................
32.3.12 USB Module Signal Timing ................................................................................
32.3.13 AFEIF Module Signal Timing .............................................................................
32.3.14 AC Characteristics Measurement Conditions ......................................................
32.3.15 Delay Time Variation Due to Load Capacitance .................................................
32.4 A/D Converter Characteristics ..........................................................................................
32.5 D/A Converter Characteristics ..........................................................................................
929
931
934
937
946
949
951
954
957
968
975
978
980
982
985
987
989
990
991
991
Appendix A Pin Functions ................................................................................................ 993
A.1
A.2
A.3
Pin Functions .................................................................................................................... 993
Treatment of Unused Pins................................................................................................. 999
Pin Status when Accessing Address Spaces.................................................................... 1004
Rev. 5.00 Dec 12, 2005 page li of lxxii
Appendix B Control Registers ....................................................................................... 1018
B.1
Register Address Map ..................................................................................................... 1018
Appendix C Product Lineup ........................................................................................... 1028
Appendix D Package Dimensions ................................................................................ 1029
Appendix E Using Versions Previous to the SH7727C ......................................... 1031
E.1
Determining the Version Number Based on the Markings on the Chip.......................... 1031
Appendix F Using Port G Control Register (PGCR) with Versions Previous
to the SH7727B.......................................................................................... 1032
Rev. 5.00 Dec 12, 2005 page lii of lxxii
Figures
Section 1 Overview and Pin Functions
Figure 1.1 Block Diagram ....................................................................................................... 8
Figure 1.2 Pin Arrangement (PRQP0240KC-B) ..................................................................... 9
Figure 1.3 Pin Arrangement (PLBG0240JA-A) ...................................................................... 10
Section 2 CPU
Figure 2.1 Register Configuration in Each Processing Mode (1) ............................................
Figure 2.2 Register Configuration in Each Processing Mode (2) ............................................
Figure 2.3 General Purpose Register (Not in DSP Mode) .......................................................
Figure 2.4 General Purpose Register (DSP Mode) ..................................................................
Figure 2.5 Control Registers (1) ..............................................................................................
Figure 2.5 Control Registers (2) ..............................................................................................
Figure 2.6 System Registers ....................................................................................................
Figure 2.7 DSP Registers.........................................................................................................
Figure 2.8 Connections of DSP Registers and Buses ..............................................................
Figure 2.9 Longword Operand ................................................................................................
Figure 2.10 Data Format............................................................................................................
Figure 2.11 Byte, Word, and Longword Alignment ..................................................................
Figure 2.12 X and Y Data Transfer Addressing ........................................................................
Figure 2.13 Single Data Transfer Addressing............................................................................
Figure 2.14 Modulo Addressing ................................................................................................
Figure 2.15 DSP Instruction Formats ........................................................................................
Figure 2.16 Sample Parallel Instruction Program......................................................................
Figure 2.17 Examples of Conditional Operations and Data Transfer Instructions ....................
23
24
25
26
29
30
31
35
37
38
39
40
49
50
52
58
87
95
Section 3 Memory Management Unit (MMU)
Figure 3.1 MMU Functions .....................................................................................................
Figure 3.2 Logical Address Space Mapping............................................................................
Figure 3.3 MMU Register Contents ........................................................................................
Figure 3.4 Overall Configuration of the TLB ..........................................................................
Figure 3.5 Logical Address and TLB Structure.......................................................................
Figure 3.6 TLB Indexing (IX = 1) ...........................................................................................
Figure 3.7 TLB Indexing (IX = 0) ...........................................................................................
Figure 3.8 Objects of Address Comparison.............................................................................
Figure 3.9 Operation of LDTLB Instruction............................................................................
Figure 3.10 Synonym Problem ..................................................................................................
Figure 3.11 MMU Exception Generation Flowchart .................................................................
Figure 3.12 MMU Exception Signals in Instruction Fetch ........................................................
99
101
104
105
106
107
108
109
113
115
120
121
Rev. 5.00 Dec 12, 2005 page liii of lxxii
Figure 3.13 MMU Exception Signals in Data Access ............................................................... 122
Figure 3.14 MMU Exception in Repeat Loop ........................................................................... 123
Figure 3.15 Specifying Address and Data for Memory-Mapped TLB Access .......................... 126
Section 4 Exception Handling
Figure 4.1 Vector Table........................................................................................................... 132
Figure 4.2 Example of Acceptance Order of General Exceptions ........................................... 135
Figure 4.3 Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers........... 139
Section 5 Cache
Figure 5.1 Cache Structure ......................................................................................................
Figure 5.2 CCR Register Configuration ..................................................................................
Figure 5.3 CCR2 Register Configuration ................................................................................
Figure 5.4 Cache Search Scheme ............................................................................................
Figure 5.5 Write-Back Buffer Configuration...........................................................................
Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access........................
150
152
153
155
157
159
Section 6 X/Y Memory
Figure 6.1 X/Y Memory Logical Address Mapping................................................................ 163
Figure 6.2 X/Y Memory Physical Address Mapping .............................................................. 164
Section 7 Interrupt Controller (INTC)
Figure 7.1 INTC Block Diagram .............................................................................................
Figure 7.2 Example of IRL Interrupt Connection....................................................................
Figure 7.3 Interrupt Operation Flowchart................................................................................
Figure 7.4 Example of Pipeline Operations when IRL Interrupt is Accepted .........................
166
171
198
202
Section 8 User Break Controller
Figure 8.1 Block Diagram of User Break Controller............................................................... 204
Section 9 Power-Down Modes and Software Reset
Figure 9.1 Canceling Standby Mode with STBCR.STBY.......................................................
Figure 9.2 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output ...........................
Figure 9.3 Manual Reset STATUS Output..............................................................................
Figure 9.4 Standby to Interrupt STATUS Output....................................................................
Figure 9.5 Standby to Power-On Reset STATUS Output........................................................
Figure 9.6 Standby to Manual Reset STATUS Output............................................................
Figure 9.7 Sleep to Interrupt STATUS Output ........................................................................
Figure 9.8 Sleep to Power-On Reset STATUS Output............................................................
Figure 9.9 Sleep to Manual Reset STATUS Output................................................................
Figure 9.10 Hardware Standby Mode Timing (CA = Low in Normal Operation) ....................
Rev. 5.00 Dec 12, 2005 page liv of lxxii
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249
250
250
251
251
252
252
253
255
Figure 9.11 Hardware Standby Mode Timing (CA = Low during WDT Operation
while Standby Mode is Cleared) ............................................................................ 256
Section 10
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
On-Chip Oscillation Circuits
Block Diagram of Clock Pulse Generator ..............................................................
Block Diagram of the WDT ...................................................................................
Writing to WTCNT and WTCSR...........................................................................
Points for Attention when Using Crystal Resonator...............................................
Points for Attention when Using PLL Oscillator Circuit .......................................
259
271
275
277
278
Section 11 Extend Clock Pulse Generator for USB (EXCPG)
Figure 11.1 Block Diagram of EXCPG ..................................................................................... 279
Section 12 Bus State Controller (BSC)
Figure 12.1 Corresponding to Logical Address Space and Physical Address Space.................
Figure 12.2 Corresponding to Logical Address Space and Physical Address Space.................
Figure 12.3 Physical Space Allocation ......................................................................................
Figure 12.4 Writing to RFCR, RTCSR, RTCNT, and RTCOR.................................................
Figure 12.5 Basic Timing of Basic Interface .............................................................................
Figure 12.6 Example of 32-Bit Data-Width Static RAM Connection .......................................
Figure 12.7 Example of 16-Bit Data-Width Static RAM Connection .......................................
Figure 12.8 Example of 8-Bit Data-Width Static RAM Connection .........................................
Figure 12.9 Basic Interface Wait Timing (Software Wait Only)...............................................
Figure 12.10 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal
WAITSEL = 1).......................................................................................................
Figure 12.11 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width)..........
Figure 12.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width).............................
Figure 12.13 Basic Timing for Synchronous DRAM Burst Read ...............................................
Figure 12.14 Synchronous DRAM Burst Read Wait Specification Timing ................................
Figure 12.15 Basic Timing for Synchronous DRAM Single Read..............................................
Figure 12.16 Basic Timing for Synchronous DRAM Burst Write ..............................................
Figure 12.17 Basic Timing for Synchronous DRAM Single Write.............................................
Figure 12.18 Auto-Refresh Operation .........................................................................................
Figure 12.19 Synchronous DRAM Auto-Refresh Timing...........................................................
Figure 12.20 Synchronous DRAM Self-Refresh Timing ............................................................
Figure 12.21 Synchronous DRAM Mode Write Timing .............................................................
Figure 12.22 Burst ROM Wait Access Timing ...........................................................................
Figure 12.23 Burst ROM Basic Access Timing ..........................................................................
Figure 12.24 Example of PCMCIA Interface (If Internal PC Card Controller is not used.)........
Figure 12.25 Basic Timing for PCMCIA Memory Card Interface ..............................................
Figure 12.26 Wait Timing for PCMCIA Memory Card Interface ...............................................
285
289
291
315
326
327
328
328
329
330
332
333
336
337
338
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341
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343
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348
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Rev. 5.00 Dec 12, 2005 page lv of lxxii
Figure 12.27 Basic Timing for PCMCIA Memory Card Interface Burst Access ........................
Figure 12.28 Wait Timing for PCMCIA Memory Card Interface Burst Access .........................
Figure 12.29 PCMCIA Space Assignment ..................................................................................
Figure 12.30 Basic Timing for PCMCIA I/O Card Interface ......................................................
Figure 12.31 Wait Timing for PCMCIA I/O Card Interface .......................................................
Figure 12.32 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ..............................
Figure 12.33 Waits between Access Cycles ................................................................................
Figure 12.34 Pins A25 to A0 Pull-Up Timing.............................................................................
Figure 12.35 Pins D31 to D0 Pull-Up Timing (Read Cycle).......................................................
Figure 12.36 Pins D31 to D0 Pull-Up Timing (Write Cycle) ......................................................
355
356
357
359
360
361
363
364
364
365
Section 13 Li Bus State Controller (LBSC)
Figure 13.1 Block Diagram of Li Bus Architecture................................................................... 377
Section 14
Figure 14.1
Figure 14.2
Figure 14.3
Figure 14.4
Figure 14.5
Figure 14.6
Direct Memory Access Controller (DMAC)
DMAC Block Diagram ..........................................................................................
DMAC Transfer Flowchart ....................................................................................
Operation in Round-Robin Mode...........................................................................
Channel Priority Order in Round-Robin Mode ......................................................
Operation in Direct Address Mode.........................................................................
Example of DMA Transfer Timing in the Direct Address Mode
(Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)...
Figure 14.7 Example of DMA Transfer Timing in the Direct Address Mode
(16-byte Transfer, Transfer Source: Ordinary Memory, Transfer Destination:
Ordinary Memory) .................................................................................................
Figure 14.8 Example of DMA Transfer Timing in the Direct Address Mode
(16-byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination:
Ordinary Memory) .................................................................................................
Figure 14.9 Operation in Indirect Address Mode (When the External Memory Space
is Set to 16-bit Width) ............................................................................................
Figure 14.10 Example of Transfer Timing in Indirect Address Mode
(Transfer between External Memories, External Memory with 16-bit Width) ......
Figure 14.11 Data Flow in Single Address Mode........................................................................
Figure 14.12 Example of DMA Transfer Timing in Single Address Mode ................................
Figure 14.13 Example of DMA Transfer Timing in Single Address Mode
(External Memory Space (Ordinary Memory) → External Device with DACK) ..
Figure 14.14 Transfer Example in Cycle-Steal Mode .................................................................
Figure 14.15 Example of Transfer in Burst Mode.......................................................................
Figure 14.16 Bus State in Multiple Channel Operation...............................................................
Figure 14.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) .......................................
Figure 14.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles) .......................................
Rev. 5.00 Dec 12, 2005 page lvi of lxxii
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399
403
404
406
407
408
408
410
411
412
413
414
415
415
417
420
421
Figure 14.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access:
4 Cycles).................................................................................................................
Figure 14.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) ...
Figure 14.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) ........................................
Figure 14.22 Burst Mode, Level Input ........................................................................................
Figure 14.23 Burst Mode, Edge Input .........................................................................................
Figure 14.24 Source Address Reload Function Diagram.............................................................
Figure 14.25 Timing Chart of Source Address Reload Function.................................................
Figure 14.26 CMT Block Diagram..............................................................................................
Figure 14.27 Counter Operation ..................................................................................................
Figure 14.28 Count Timing .........................................................................................................
Figure 14.29 Timing of CMF Setting ..........................................................................................
Figure 14.30 Timing of CMF Clear by the CPU .........................................................................
422
423
424
425
426
427
428
431
435
436
437
437
Section 15
Figure 15.1
Figure 15.2
Figure 15.3
Figure 15.4
Figure 15.5
Figure 15.6
Figure 15.7
Timer (TMU)
TMU Block Diagram..............................................................................................
Setting the Count Operation ...................................................................................
Auto-Reload Counter Operation.............................................................................
Count Timing when Internal Clock is Operating ...................................................
Count Timing when On-Chip RTC Clock is Operating .........................................
UNF Set Timing .....................................................................................................
Status Flag Clear Timing........................................................................................
444
451
452
452
453
453
454
Section 16 Realtime Clock (RTC)
Figure 16.1 RTC Block Diagram...............................................................................................
Figure 16.2(a) Setting the Time .................................................................................................
Figure 16.2(b) Setting the Time.................................................................................................
Figure 16.3 Reading the Time ...................................................................................................
Figure 16.4 Using the Alarm Function ......................................................................................
Figure 16.5 Example of Crystal Oscillator Circuit Connection.................................................
Figure 16.6 Periodic Interrupt Function Setting ........................................................................
458
474
474
475
476
477
478
Section 17
Figure 17.1
Figure 17.2
Figure 17.3
Figure 17.4
Figure 17.5
Serial Communication Interface (SCI)
SCI Block Diagram ................................................................................................
SCPT[1]/SCK0 Pin ................................................................................................
SCPT[0]/TxD0 Pin.................................................................................................
SCPT[0]/RxD0 Pin.................................................................................................
Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits).................................................
Figure 17.6 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)............................................................................................
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485
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513
Rev. 5.00 Dec 12, 2005 page lvii of lxxii
Figure 17.7 Sample SCI Initialization Flowchart ......................................................................
Figure 17.8 Sample Serial Transmission Flowchart ..................................................................
Figure 17.9 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) ...................................................
Figure 17.10 Sample Serial Reception Data Flowchart (1) .........................................................
Figure 17.10 Sample Serial Reception Data Flowchart (2) .........................................................
Figure 17.11 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit) ...................................................
Figure 17.12 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) ...........................................
Figure 17.13 Sample Multiprocessor Serial Transmission Flowchart .........................................
Figure 17.14 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)...............................
Figure 17.15 Sample Multiprocessor Serial Reception Flowchart (1).........................................
Figure 17.15 Sample Multiprocessor Serial Reception Flowchart (2).........................................
Figure 17.16 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)...............................
Figure 17.17 Data Format in Clock Synchronous Communication .............................................
Figure 17.18 Sample SCI Initialization Flowchart ......................................................................
Figure 17.19 Sample Serial Transmission Flowchart ..................................................................
Figure 17.20 Sample SCI Transmission Operation in Clocked Synchronous Mode ...................
Figure 17.21 Sample Serial Reception Flowchart (1)..................................................................
Figure 17.21 Sample Serial Reception Flowchart (2)..................................................................
Figure 17.22 Example of SCI Operation in Reception ................................................................
Figure 17.23 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations .......
Figure 17.24 Receive Data Sampling Timing in Asynchronous Mode .......................................
Section 18
Smart Card Interface
Figure 18.1 Smart Card Interface Block Diagram .....................................................................
Figure 18.2 Pin Connection Diagram for the Smart Card Interface...........................................
Figure 18.3 Data Format for Smart Card Interface....................................................................
Figure 18.4 Waveform of Start Character..................................................................................
Figure 18.5 Initialization Flowchart (Example).........................................................................
Figure 18.6 Transmission Flowchart (Example) .......................................................................
Figure 18.7 Reception Flowchart (Example).............................................................................
Figure 18.8 Receive Data Sampling Timing in Smart Card Mode ............................................
Figure 18.9 Retransmission in SCI Receive Mode ....................................................................
Figure 18.10 Retransmission in SCI Transmit Mode ..................................................................
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Section 19 Serial Communication Interface with FIFO (SCIF)
Figure 19.1 SCIF Block Diagram .............................................................................................. 566
Rev. 5.00 Dec 12, 2005 page lviii of lxxii
Figure 19.2 SCPT[4]/TxD2 Pin.................................................................................................
Figure 19.3 SCPT[4]/RxD2 Pin.................................................................................................
Figure 19.4 Sample SCIF Initialization Flowchart ....................................................................
Figure 19.5 Sample Serial Transmission Flowchart ..................................................................
Figure 19.6 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit)
Figure 19.7 Example of Operation Using Modem Control (CTS).............................................
Figure 19.8 Sample Serial Reception Flowchart (1)..................................................................
Figure 19.9 Sample Serial Reception Flowchart (2)..................................................................
Figure 19.10 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit) ...................................................
Figure 19.11 Example of Operation Using Modem Control (RTS).............................................
Figure 19.12 Receive Data Sampling Timing in Asynchronous Mode .......................................
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Section 20 Serial IO (SIOF)
Figure 20.1 SIOF Block Diagram..............................................................................................
Figure 20.2 Serial Clock Supply System ...................................................................................
Figure 20.3 SIOF Serial Data Synchronized Timing.................................................................
Figure 20.4 SIOF Transmit or Receive Timing .........................................................................
Figure 20.5 Transmit or Receive Data Bit Alignment ...............................................................
Figure 20.6 Control Data Bit Alignment ...................................................................................
Figure 20.7 Control Data Interface (Slot Position) ....................................................................
Figure 20.8 Control Data Interface (Secondary FS) ..................................................................
Figure 20.9 Example of Transmit Operation in Master .............................................................
Figure 20.10 Example of Receive Operation in Master...............................................................
Figure 20.11 Example of Transmit Operation in Slave ...............................................................
Figure 20.12 Example of Receive Operation in Slave.................................................................
Figure 20.13 Transmit or Receive Timing (8 bits monaural—1) ................................................
Figure 20.14 Transmit or Receive Timing (8 bits monaural—2) ................................................
Figure 20.15 Transmit or Receive Timing (16 bits monaural—1) ..............................................
Figure 20.16 Transmit or Receive Timing (16 bits stereo—1)....................................................
Figure 20.17 Transmit or Receive Timing (16 bits stereo—2)....................................................
Figure 20.18 Transmit or Receive Timing (16 bits stereo—3)....................................................
Figure 20.19 Transmit or Receive Timing (16 bits monaural—2) ..............................................
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Section 21
Figure 21.1
Figure 21.2
Figure 21.3
Figure 21.4
Figure 21.5
Figure 21.6
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Analog Front End Interface (AFEIF)
Block Diagram of AFE Interface ...........................................................................
FIFO Interrupt Timing............................................................................................
Ringing Interrupt Occurrence Timing ....................................................................
Interrupt Generator .................................................................................................
AFE Serial Interface...............................................................................................
AFE Control Sequence...........................................................................................
Rev. 5.00 Dec 12, 2005 page lix of lxxii
Figure 21.7 DAA Block Diagram.............................................................................................. 675
Figure 21.8 Ringing Detect Sequence ....................................................................................... 676
Section 22 USB Pin Multiplex Controller
Figure 22.1 Block Diagram of USB PIN Multiplexer ...............................................................
Figure 22.2 Example 1 of Transceiver Connection for USB function Controller
(On-chip transceiver is used)..................................................................................
Figure 22.3 Example 2 of Transceiver Connection for USB function Controller
(On-chip transceiver is used)..................................................................................
Figure 22.4 Example 3 of Transceiver Connection for USB function Controller
(On-chip transceiver is not used)............................................................................
Figure 22.5 Example 4 of Transceiver Connection for USB function Controller
(On-chip transceiver is not used)............................................................................
Figure 22.6 Example 1 of Transceiver Connection for USB Host Controller
(On-chip transceiver is used)..................................................................................
Figure 22.7 Example 2 of Transceiver Connection for USB Host Controller
(On-chip transceiver is not used)............................................................................
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Section 23 USB Function Controller
Figure 23.1 Block Diagram of UBC..........................................................................................
Figure 23.2 Cable Connection Operation ..................................................................................
Figure 23.3 Cable Disconnection Operation..............................................................................
Figure 23.4 Transfer Stage for Control Transfer .......................................................................
Figure 23.5 Setup Stage Operation ............................................................................................
Figure 23.6 Data Stage Operation (Control-In) .........................................................................
Figure 23.7 Data Stage Operation (Control-Out).......................................................................
Figure 23.8 Status Stage Operation (Control-In) .......................................................................
Figure 23.9 Status Stage Operation (Control-Out) ....................................................................
Figure 23.10 EP1 Bulk-Out Transfer Operation..........................................................................
Figure 23.11 EP2 Bulk-In Transfer Operation ............................................................................
Figure 23.12 EP2 Interrupt-In Transfer Operation ......................................................................
Figure 23.13 Forcible Stall by Application..................................................................................
Figure 23.14 Automatic Stall by USB Function Module.............................................................
Figure 23.15 TR Interrupt Flag Set Timing .................................................................................
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Section 25
Figure 25.1
Figure 25.2
Figure 25.3
Figure 25.4
Figure 25.5
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LCD Controller
Block Diagram .......................................................................................................
Valid Display and Retrace Period ..........................................................................
Color-Palette Data Format......................................................................................
Power-Supply Control Sequence and States of the LCD Module ..........................
Power-Supply Control Sequence and States of the LCD Module ..........................
Rev. 5.00 Dec 12, 2005 page lx of lxxii
Figure 25.6 Power-Supply Control Sequence and States of the LCD Module ..........................
Figure 25.7 Power-Supply Control Sequence and States of the LCD Module ..........................
Figure 25.8 Clock and LCD Data Signal Example....................................................................
Figure 25.9 Clock and LCD Data Signal Example....................................................................
Figure 25.10 Clock and LCD Data Signal Example....................................................................
Figure 25.11 Clock and LCD Data Signal Example....................................................................
Figure 25.12 Clock and LCD Data Signal Example....................................................................
Figure 25.13 Clock and LCD Data Signal Example....................................................................
Figure 25.14 Clock and LCD Data Signal Example....................................................................
Figure 25.15 Clock and LCD Data Signal Example....................................................................
Figure 25.16 Clock and LCD Data Signal Example....................................................................
Figure 25.17 Clock and LCD Data Signal Example....................................................................
Figure 25.18 Clock and LCD Data Signal Example....................................................................
Figure 25.19 Clock and LCD Data Signal Example....................................................................
Figure 25.20 Clock and LCD Data Signal Example....................................................................
Figure 25.21 Clock and LCD Data Signal Example....................................................................
Figure 25.22 Clock and LCD Data Signal Example....................................................................
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Section 26 Pin Function Controller (PFC)
Figure 26.1 Overview of the Pin Selection Function................................................................. 821
Section 28
Figure 28.1
Figure 28.2
Figure 28.3
Figure 28.4
A/D Converter
A/D Converter Block Diagram...............................................................................
A/D Data Register Access Operation (Reading H'AA40) ......................................
Example of A/D Converter Operation (Single Mode, Channel 2 Selected) ...........
Example of A/D Converter Operation
(Multi Mode, Channels AN4 to AN6 Selected) ....................................................
Figure 28.5 Example of A/D Converter Operation
(Scan Mode, Channels AN4 to AN6 Selected) ......................................................
Figure 28.6 A/D Conversion Timing.........................................................................................
Figure 28.7 External Trigger Input Timing ...............................................................................
Figure 28.8 Definitions of A/D Conversion Accuracy ..............................................................
Figure 28.9 Example of Analog Input Protection Circuit ..........................................................
Figure 28.10 Analog Input Pin Equivalent Circuit ......................................................................
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Section 29 D/A Converter
Figure 29.1 D/A Converter Block Diagram............................................................................... 879
Figure 29.2 Example of D/A Converter Operation.................................................................... 883
Section 30 PC Card Controller (PCC)
Figure 30.1 PC Card Controller Block Diagram........................................................................ 886
Rev. 5.00 Dec 12, 2005 page lxi of lxxii
Figure 30.2
Figure 30.3
Figure 30.4
Figure 30.5
Figure 30.6
Figure 30.7
Figure 30.8
Figure 30.9
Continuous 32-MB Area Mode ..............................................................................
Continuous 16-MB Area Mode (Area 6)................................................................
SH7727 Interface....................................................................................................
PCMCIA Memory Card Interface Basic Timing....................................................
PCMCIA Memory Card Interface Wait Timing.....................................................
PCMCIA I/O Card Interface Basic Timing ............................................................
PCMCIA I/O Card Interface Wait Timing .............................................................
Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ..............................
Section 31
Figure 31.1
Figure 31.2
Figure 31.3
User-Debugging Interface (H-UDI)
H-UDI Block Diagram ........................................................................................... 916
TAP Controller State Transitions ........................................................................... 925
H-UDI Reset........................................................................................................... 927
Section 32 Electrical Characteristics
Figure 32.1 Power-On Sequence ...............................................................................................
Figure 32.2 Power Supply Voltage and Operating Frequency ..................................................
Figure 32.3 EXTAL Clock Input Timing ..................................................................................
Figure 32.4 CKIO Clock Input Timing .....................................................................................
Figure 32.5 CKIO Clock Output Timing...................................................................................
Figure 32.6 Power-on Oscillation Settling Time .......................................................................
Figure 32.7 Oscillation Settling Time at Standby Return (Return by Reset).............................
Figure 32.8 Oscillation Settling Time at Standby Return (Return by NMI)..............................
Figure 32.9 Oscillation Settling Time at Standby Return (Return by IRQ4 to IRQ0)..............
Figure 32.10 PLL Synchronization Settling Time by Reset or NMI Interrupt ............................
Figure 32.11 PLL Synchronization Settling Time by IRQ/IRL and PINT0/1 Interrupt ..............
Figure 32.12 PLL Sync Stabilization Time at Frequency Multiplier Factor Change ..................
Figure 32.13 Reset Input Timing.................................................................................................
Figure 32.14 Interrupt signal Input Timing .................................................................................
Figure 32.15 Bus Release Timing................................................................................................
Figure 32.16 Pin Drive Timing at Standby..................................................................................
Figure 32.17 Basic Bus Cycle (No Wait) ....................................................................................
Figure 32.18 Basic Bus Cycle (One Wait)...................................................................................
Figure 32.19 Basic Bus Cycle (External Wait, WAITSEL = 1) ..................................................
Figure 32.20 Burst ROM Bus Cycle (No Wait) ..........................................................................
Figure 32.21 Burst ROM Bus Cycle (Two Waits) ......................................................................
Figure 32.22 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) ........................................
Figure 32.23 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0) ....
Figure 32.24 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1) ....
Figure 32.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4),
RCD = 0, CAS Latency = 1, TPC = 1) ...................................................................
Rev. 5.00 Dec 12, 2005 page lxii of lxxii
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Figure 32.26 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4),
RCD = 1, CAS Latency = 3, TPC = 0) ...................................................................
Figure 32.27 Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0)..............
Figure 32.28 Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1)..............
Figure 32.29 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write × 4),
RCD = 0, TPC = 1, TRWL = 0) .............................................................................
Figure 32.30 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write × 4),
RCD = 1, TPC = 0, TRWL = 0) .............................................................................
Figure 32.31 Synchronous DRAM Auto-Refresh Cycle (TRAS = 1, TPC = 1)..........................
Figure 32.32 Synchronous DRAM Self-Refresh Cycle (TPC = 0)..............................................
Figure 32.33 Synchronous DRAM Mode Register Write Cycle .................................................
Figure 32.34 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) ...............................
Figure 32.35 PCMCIA Memory Bus Cycle
(TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1) ............................
Figure 32.36 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait)...........
Figure 32.37 PCMCIA Memory Bus Cycle
(Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3, WAITSEL = 1) ....
Figure 32.38 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)........................................
Figure 32.39 PCMCIA I/O Bus Cycle
(TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1) ............................
Figure 32.40 PCMCIA I/O Bus Cycle
(TED = 1, TEH = 1, One Wait, Bus Sizing, WAITSEL = 1) .................................
Figure 32.41 Oscillation Settling Time at RTC Crystal Oscillator Power-on..............................
Figure 32.42 SCK Input Clock Timing .......................................................................................
Figure 32.43 SCI I/O Timing in Clock Synchronous Mode ........................................................
Figure 32.44 I/O Port Timing ......................................................................................................
Figure 32.45 DREQ Input Timing...............................................................................................
Figure 32.46 DRAK Output Timing............................................................................................
Figure 32.47 TCK Input Timing..................................................................................................
Figure 32.48 TRST Input Timing (Reset Hold)...........................................................................
Figure 32.49 H-UDI Data Transfer Timing.................................................................................
Figure 32.50 ASEMD0 Input Timing..........................................................................................
Figure 32.51 LCDC AC Specification.........................................................................................
Figure 32.52 SIOMCLK Input Timing........................................................................................
Figure 32.53 SIOF Transmit/Receive Timing (Master Mode 1: Fall Sampling Time) ...............
Figure 32.54 SIOF Transmit/Receive Timing (Master Mode 1: Rise Sampling Time)...............
Figure 32.55 SIOF Transmit/Receive Timing (Master Mode 2: Fall Sampling Time) ...............
Figure 32.56 SIOF Transmit/Receive Timing (Master Mode 2: Rise Sampling Time)...............
Figure 32.57 SIOF Transmit/Receive Timing (Slave Mode 1 and Slave Mode 2)......................
Figure 32.58 USB Clock Timing.................................................................................................
Figure 32.59 AFEIF Module AC Timing ....................................................................................
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Rev. 5.00 Dec 12, 2005 page lxiii of lxxii
Figure 32.60 Output Load Circuit................................................................................................ 989
Figure 32.61 Load Capacitance vs. Delay Time.......................................................................... 990
Appendix D Package Dimensions
Figure D.1 Package Dimensions (PRQP0240KC-B).............................................................. 1029
Figure D.2 Package Dimensions (PLBG0240JA-A) .............................................................. 1030
Rev. 5.00 Dec 12, 2005 page lxiv of lxxii
Tables
Section 1 Overview and Pin Functions
Table 1.1
SH7727 Features .................................................................................................... 2
Table 1.2
SH7727 Pin Function ............................................................................................. 11
Section 2 CPU
Table 2.1
Initial Register Values ............................................................................................ 24
Table 2.2
Detail Behavior Under Each SH3-DSP Mode........................................................ 33
Table 2.3
Destination Register of DSP Instructions............................................................... 34
Table 2.4
Source Register of DSP Operations ....................................................................... 35
Table 2.5
DSR Register Bits .................................................................................................. 36
Table 2.6
Word Data Sign Extension ..................................................................................... 41
Table 2.7
Delayed Branch Instructions .................................................................................. 41
Table 2.8
T Bit ....................................................................................................................... 42
Table 2.9
Immediate Data Referencing.................................................................................. 42
Table 2.10 Absolute Address Referencing ............................................................................... 43
Table 2.11 Displacement Referencing...................................................................................... 43
Table 2.12 Addressing Modes and Effective Addresses for CPU Instructions ........................ 44
Table 2.13 Overview of Data Transfer Instructions ................................................................. 48
Table 2.14 CPU Instruction Formats........................................................................................ 55
Table 2.15 Double Data Transfer Instruction Formats ............................................................. 59
Table 2.16 Single Data Transfer Instruction Formats .............................................................. 60
Table 2.17 A-Field Parallel Data Transfer Instructions............................................................ 61
Table 2.18 B-Field ALU Operation Instructions and Multiply Instructions............................. 62
Table 2.19 CPU Instruction Types ........................................................................................... 65
Table 2.20 Data Transfer Instructions ...................................................................................... 69
Table 2.21 Arithmetic Operation Instructions .......................................................................... 71
Table 2.22 Logic Operation Instructions.................................................................................. 73
Table 2.23 Shift Instructions .................................................................................................... 74
Table 2.24 Branch Instructions................................................................................................. 75
Table 2.25 System Control Instructions ................................................................................... 76
Table 2.26 Added CPU System Control Instructions............................................................... 81
Table 2.27 Double Data Transfer Instructions ......................................................................... 83
Table 2.28 Single Data Transfer Instructions........................................................................... 84
Table 2.29 Correspondence between DSP Data Transfer Operands and Registers.................. 85
Table 2.30 DSP Operation Instruction Formats ....................................................................... 86
Table 2.31 Correspondence between DSP Instruction Operands and Registers....................... 87
Table 2.32 DSP Operation Instructions.................................................................................... 88
Table 2.33 DC Bit Update Definitions ..................................................................................... 94
Rev. 5.00 Dec 12, 2005 page lxv of lxxii
Table 2.34
Examples of NOPX and NOPY Instruction Codes ................................................ 96
Section 3 Memory Management Unit (MMU)
Table 3.1
Register Configuration ........................................................................................... 103
Table 3.2
Access States Designated by D, C, and PR Bits..................................................... 110
Section 4 Exception Handling
Table 4.1
Register Configuration ........................................................................................... 131
Table 4.2
Exception Event Vectors ........................................................................................ 133
Table 4.3
Exception Codes..................................................................................................... 136
Table 4.4
Types of Reset........................................................................................................ 141
Section 5 Cache
Table 5.1
Cache Specifications .............................................................................................. 149
Table 5.2
LRU and Way Replacement................................................................................... 151
Table 5.3
Register Configuration ........................................................................................... 151
Table 5.4
LRU and Way Replacement (when W2LOCK=1)................................................. 153
Table 5.5
LRU and Way Replacement (when W3LOCK=1)................................................. 153
Table 5.6
LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1) .................... 154
Section 6 X/Y Memory
Table 6.1
X/Y Memory Specifications................................................................................... 161
Section 7 Interrupt Controller (INTC)
Table 7.1
Pin Configuration ...................................................................................................
Table 7.2
Register Configuration ...........................................................................................
Table 7.3
IRL3 to IRL0 Pins and Interrupt Levels.................................................................
Table 7.4
Interrupt Exception Handling Sources and Priority (IRQ Mode)...........................
Table 7.5
Interrupt Exception Handling Sources and Priority (IRL Mode) ...........................
Table 7.6
Interrupt Level and INTEVT Code ........................................................................
Table 7.7
Interrupt Request Sources and IPRA to IPRG........................................................
Table 7.8
Interrupt Response Time ........................................................................................
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Section 8 User Break Controller
Table 8.1
Register Configuration ........................................................................................... 205
Table 8.2
Data Access Cycle Addresses and Operand Size Comparison Conditions ............ 223
Section 9 Power-Down Modes and Software Reset
Table 9.1
Power-Down Modes............................................................................................... 234
Table 9.2
Pin Configuration ................................................................................................... 235
Table 9.3
Register Configuration ........................................................................................... 235
Rev. 5.00 Dec 12, 2005 page lxvi of lxxii
Table 9.4
Register States in Standby Mode............................................................................ 244
Section 10 On-Chip Oscillation Circuits
Table 10.1 Clock Pulse Generator Pins and Functions.............................................................
Table 10.2 Register Configuration ...........................................................................................
Table 10.3 Clock Operating Modes..........................................................................................
Table 10.4 Available Combination of Clock Mode and FRQCR Values.................................
Table 10.5 Register Configuration ...........................................................................................
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Section 11 Extend Clock Pulse Generator for USB (EXCPG)
Table 11.1 Pin Configuration ................................................................................................... 280
Table 11.2 Register Configuration ........................................................................................... 280
Section 12 Bus State Controller (BSC)
Table 12.1 Pin Configuration ...................................................................................................
Table 12.2 Register Configuration ...........................................................................................
Table 12.3 Physical Address Space Map .................................................................................
Table 12.4 Correspondence between External Pins (MD4 and MD3)
and Memory bus width in area0 .............................................................................
Table 12.5 SH7727 and PCMCIA Pins ....................................................................................
Table 12.6 32-Bit External Device/Big Endian Access and Data Alignment ..........................
Table 12.7 16-Bit External Device/Big Endian Access and Data Alignment ..........................
Table 12.8 8-Bit External Device/Big Endian Access and Data Alignment ............................
Table 12.9 32-Bit External Device/Little Endian Access and Data Alignment........................
Table 12.10 16-Bit External Device/Little Endian Access and Data Alignment........................
Table 12.11 8-Bit External Device/Little Endian Access and Data Alignment..........................
Table 12.12 Relationship between Synchronous DRAM type, bus width and AMX ................
Table 12.13 Relationship between LSI Address Pins and Synchronous DRAM Address Pins .
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Section 13 Li Bus State Controller (LBSC)
Table 13.1 Register Configuration ........................................................................................... 367
Section 14 Direct Memory Access Controller (DMAC)
Table 14.1 Pin Configuration ...................................................................................................
Table 14.2 DMAC Registers ....................................................................................................
Table 14.3 Selecting External Request Modes with the RS Bits..............................................
Table 14.4 Selection of On-Chip Module Request Modes Using RS3 to RS0 Bits .................
Table 14.5 DMA Transfers ......................................................................................................
Table 14.6 Relationship of Request Modes and Bus Modes ....................................................
Table 14.7 Register Configuration ...........................................................................................
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Rev. 5.00 Dec 12, 2005 page lxvii of lxxii
Table 14.8
Transfer Conditions and Register Settings for Transfer between On-Chip A/D
Converter and External Memory ............................................................................ 438
Table 14.9 DMAC Sate after the Fourth Transfer Ends ........................................................... 439
Table 14.10 Transfer Conditions and Register Settings for Transfer between External
Memory and SCIF Transmitter .............................................................................. 440
Section 15 Timer (TMU)
Table 15.1 TMU Register Configuration ................................................................................. 445
Table 15.2 TMU Interrupt Sources .......................................................................................... 454
Section 16 Realtime Clock (RTC)
Table 16.1 RTC Pin Configuration ..........................................................................................
Table 16.2 RTC Registers ........................................................................................................
Table 16.3 Day-of-Week Codes (RWKCNT) ..........................................................................
Table 16.4 Day-of-Week Codes (RWKAR).............................................................................
Table 16.5 Recommended Oscillator Circuit Constants (Recommended Values) ...................
Section 17 Serial Communication Interface (SCI)
Table 17.1 SCI Pins 485
Table 17.2 Registers 486
Table 17.3 SCSMR Settings.....................................................................................................
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1)...................................
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (2)...................................
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (3)...................................
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (4)...................................
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (5)...................................
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (6)...................................
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (7)...................................
Table 17.5 Bit Rates and SCBRR Settings in Clock Synchronous Mode ................................
Table 17.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)............................................................................................
Table 17.7 Maximum Bit Rates during External Clock Input (Asynchronous Mode) .............
Table 17.8 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode).....
Table 17.9 Serial Mode Register Settings and SCI Communication Formats..........................
Table 17.10 SCSMR and SCSCR Settings and SCI Clock Source Selection.............................
Table 17.11 Serial Communication Formats (Asynchronous Mode) .........................................
Table 17.12 Receive Error Conditions and SCI Operation ........................................................
Table 17.13 SCI Interrupt Sources .............................................................................................
Table 17.14 SCSSR Status Flags and Transfer of Receive Data................................................
Rev. 5.00 Dec 12, 2005 page lxviii of lxxii
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Section 18 Smart Card Interface
Table 18.1 SCI Pins 545
Table 18.2 Registers 545
Table 18.3 Register Settings for the Smart Card Interface .......................................................
Table 18.4 Relationship of n to CKS1 and CKS0 ....................................................................
Table 18.5 Examples of Bit Rate B (Bit/s) for SCBRR Settings (n = 0)..................................
Table 18.6 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0)..................................
Table 18.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode).......................
Table 18.8 Register Set Values and SCK Pin...........................................................................
Table 18.9 Smart Card Mode Operating State and Interrupt Sources ......................................
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Section 19 Serial Communication Interface with FIFO (SCIF)
Table 19.1 SCIF Pins................................................................................................................ 568
Table 19.2 Registers 569
Table 19.3 SCSMR2 Settings................................................................................................... 581
Table 19.4 Bit Rates and SCBRR2 Settings............................................................................. 581
Table 19.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)............................................................................................ 585
Table 19.6 SCSMR2 Settings and SCIF Transmit/Receive ..................................................... 589
Table 19.7 Settings for SCSMR2 and SCSCR2 and Selection of Clock Source of SCIF ........ 590
Table 19.8 Serial Transmit/Receive Formats ........................................................................... 590
Table 19.9 SCIF Interrupt Sources........................................................................................... 600
Section 20
Table 20.1
Table 20.2
Table 20.3
Table 20.4
Table 20.5
Table 20.6
Table 20.7
Table 20.8
Table 20.9
Table 20.10
Table 20.11
Table 20.12
Table 20.13
Serial IO (SIOF)
SIOF Pin List..........................................................................................................
SIOF Register Configuration..................................................................................
Examples of SIOF Clock Frequency ......................................................................
Serial Transmit Mode.............................................................................................
Frame Length .........................................................................................................
Transmit Data Sound Mode ...................................................................................
Receive Data Sound Mode .....................................................................................
Control Data Channel Number Establishment .......................................................
Transmit Request Submit Condition ......................................................................
Receive Request Submit Condition........................................................................
Transmit or Receive Reset......................................................................................
SIOF Interrupt Factors............................................................................................
Setting Conditions for the Transmit or Receive Interrupt Flag ..............................
607
607
630
632
633
635
635
636
639
640
645
646
647
Section 21 Analog Front End Interface (AFEIF)
Table 21.1 Pins for AFE Interface............................................................................................ 659
Rev. 5.00 Dec 12, 2005 page lxix of lxxii
Table 21.2
Table 21.3
AFEIF Registers..................................................................................................... 659
Telephone Number and Data.................................................................................. 669
Section 22 USB Pin Multiplex Controller
Table 22.1 Pin Configuration (Digital Transceiver Signal)......................................................
Table 22.2 Pin Configuration (Analog Transceiver Signal) .....................................................
Table 22.3 Pin Configuration (Power Control signal)..............................................................
Table 22.4 Register Configuration ...........................................................................................
681
681
682
682
Section 23 USB Function Controller
Table 23.1 Pin Configuration and Functions............................................................................ 692
Table 23.2 USB Function Module Registers............................................................................ 693
Table 23.3 Command Decoding on Application Side .............................................................. 717
Section 24 USB HOST Module
Table 24.1 Pin Configuration ................................................................................................... 726
Table 24.2 Register Configuration ........................................................................................... 727
Section 25 LCD Controller
Table 25.1 Pin Configuration ...................................................................................................
Table 25.2 Register Configuration ...........................................................................................
Table 25.3 Limits on the Resolution of Rotated Displays, Burst Length,
and Connected Memory (32-bit Bus SDRAM) ......................................................
Table 25.4 Limits on the Resolution of Rotated Displays, Burst Length,
and Connected Memory (16-bit Bus SDRAM) ......................................................
Table 25.5 Available Power-Supply Control-Sequence Periods at Typical Frame Rates ........
Table 25.6 LCDC Operating Modes ........................................................................................
Table 25.7 LCD Module Power-Supply States ........................................................................
765
765
792
795
805
806
806
Section 26 Pin Function Controller (PFC)
Table 26.1 List of Multiplexed Pins ......................................................................................... 821
Table 26.2 Pin Function Controller Registers .......................................................................... 826
Section 27 I/O Ports
Table 27.1 Pin Function Controller Registers ..........................................................................
Table 27.2 Read/Write Operation of the Ports A to C, E, J, K Data Register ..........................
Table 27.3 Read/Write Operation of the Port D Data Register (PDDR) .................................
Table 27.4 Read/Write Operation of the Ports F, M Data Register (PFDR, PMDR) ...............
Table 27.5 Read/Write Operation of the Port G Data Register (PGDR) ..................................
Table 27.6 Read/Write Operation of the Port H Data Register (PHDR) .................................
Table 27.7 Read/Write Operation of the Port L Data Register (PLDR) ...................................
Rev. 5.00 Dec 12, 2005 page lxx of lxxii
846
847
849
850
851
853
854
Table 27.8
Read/Write Operation of the SC Port Data Register (SCPDR) .............................. 856
Section 28 A/D Converter
Table 28.1 A/D Converter Pins.................................................................................................. 859
Table 28.2 A/D Converter Registers ........................................................................................ 860
Table 28.3 Analog Input Channels and A/D Data Registers .................................................... 861
Table 28.4 A/D Conversion Time (Single Mode) .................................................................... 874
Table 28.5 Analog Input Pin Ratings ....................................................................................... 878
Table 28.6 Relationship between Access Size and Read Data ................................................. 878
Section 29 D/A Converter
Table 29.1 D/A Converter Pins ................................................................................................ 880
Table 29.2 D/A Converter Registers ........................................................................................ 880
Section 30 PC Card Controller (PCC)
Table 30.1 PC Card Controller Registers ................................................................................. 887
Table 30.2 Features of the PCMCIA Interface......................................................................... 888
Table 30.3 PCMCIA Support Interface.................................................................................... 904
Section 31 User-Debugging Interface (H-UDI)
Table 31.1 H-UDI Registers.....................................................................................................
Table 31.2 H-UDI Commands .................................................................................................
Table 31.3 Correspondence between SH7727 Pins and Boundary-Scan Register ...................
Table 31.4 Reset Configuration................................................................................................
917
918
919
926
Section 32
Table 32.1
Table 32.2
Table 32.2
Table 32.3
Table 32.4
Table 32.4
Table 32.5
Table 32.6
Table 32.7
Table 32.8
Table 32.9
Table 32.10
Table 32.11
Table 32.12
Table 32.13
929
931
933
934
936
936
937
938
939
940
946
949
975
978
980
Electrical Characteristics
Absolute Maximum Ratings...................................................................................
DC Characteristics (1) ............................................................................................
DC Characteristics (2) ............................................................................................
Permitted Output Current Values ...........................................................................
Maximum Operating Frequencies (1) ....................................................................
Maximum Operating Frequencies (2) ....................................................................
Clock Timing (1) ....................................................................................................
Clock Timing (2) ....................................................................................................
Clock Timing (3) ....................................................................................................
Clock Timing (4) ....................................................................................................
Control Signal Timing............................................................................................
Bus Timing.............................................................................................................
Peripheral Module Signal Timing ..........................................................................
H-UDI-Related Pin Timing ....................................................................................
LCDC Timing ........................................................................................................
Rev. 5.00 Dec 12, 2005 page lxxi of lxxii
Table 32.14
Table 32.15
Table 32.16
Table 32.17
Table 32.18
Table 32.19
Table 32.20
SIOF Module Signal Timing ..................................................................................
USB Module Signal Timing...................................................................................
USB Electrical Characteristics (Full-Speed) ..........................................................
USB Electrical Characteristics (Low-Speed) .........................................................
AFEIF Module Signal Timing................................................................................
A/D Converter Characteristics ...............................................................................
D/A Converter Characteristics ...............................................................................
982
985
986
986
987
991
991
Appendix A Pin Functions
Table A.1 Pin Functions.......................................................................................................... 993
Table A.2 Treatment of Unused Pins ...................................................................................... 999
Table A.3 Pin Status (Normal Memory/Little Endian) ......................................................... 1004
Table A.4 Pin Status (Normal Memory/Big Endian) ............................................................ 1006
Table A.5 Pin Status (Burst ROM/Little Endian).................................................................. 1008
Table A.6 Pin Status (Burst ROM/Big Endian) .................................................................... 1010
Table A.7 Pin Status (Synchronous DRAM/Little Endian)................................................... 1012
Table A.8 Pin Status (Synchronous DRAM/Big Endian) ..................................................... 1013
Table A.9 Pin Status (PCMCIA/Little Endian) ..................................................................... 1014
Table A.10 Pin Status (PCMCIA/Big Endian)........................................................................ 1016
Appendix B Control Registers
Table B.1 Memory-Mapped Control Registers (Address Map) ............................................ 1018
Rev. 5.00 Dec 12, 2005 page lxxii of lxxii
Section 1 Overview and Pin Functions
Section 1 Overview and Pin Functions
1.1
Features
The SH7727 is a single-chip RISC microprocessor that integrates a 32-bit RISC-type SuperH
RISC engine architecture CPU with digital signal processing (DSP) extension as its core that has a
cache memory, an on-chip X/Y memory, and a memory management unit (MMU) as well as
peripheral functions required for system configuration. The SH7727 includes data protection,
virtual memory, and other functions provided by incorporating an MMU into a SuperH Series
microprocessor (SH-1 or SH-2).
The SH7727 chip has the on-chip X/Y memory with large capacitance, on-chip DSP module, and
emulator support. The provision of on-chip DSP functions enables applications that previously
required the use of two chips—a microprocessor and a DSP—to be implemented with a single
chip.
High-speed data transfers with a direct memory access controller (DMAC) and an external
memory access support function enables direct connection to each memory. The SH7727
microprocessor also supports an infrared communication function, a stereo audio recording and
playback function, a USB host controller, a function controller, an LCD controller, a PCMCIA
interface, an A/D converter, and a D/A converter.
The USB host controller and LCD controller have bus master functions, so that data supplied from
an external memory (area 3) can be freely processed. Because the USB host controller, in
particular, conforms to Open HCI standards, it is extremely easy to transfer data from the PC of a
device driver or other devices. Also, low-power operation suitable for battery operation is possible
because the LCD controller continues to display even in sleep mode.
An internal USB transceiver is also provided, eliminating the need for attachments.
A powerful built-in power management function keeps power consumption low, even during highspeed operation. In particular, power consumption can be significantly reduced by halting the X/Y
memory. Because the LSI operates at a maximum speed eight times of the speed at which the
system operates, it is ideal for electronic devices, which require both high speed and low power
consumption.
The features of this LSI are listed in table 1.1. The specifications of this LSI are listed in table 1.2.
Rev. 5.00 Dec 12, 2005 page 1 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Table 1.1
SH7727 Features
Item
Features
CPU
•
Original Renesas SuperH architecture
•
Object code level compatible with SH-1, SH-2 and SH-3
•
32-bit internal data bus
•
General-register
Sixteen 32-bit general registers (eight 32-bit shadow registers)
Eight 32-bit control registers
Four 32-bit system registers
•
RISC-type instruction set
Instruction length: 16-bit fixed length to improve code efficiency
Load-store architecture
Delayed branch instructions
Instruction set based on C language
•
Instruction execution time: one instruction/cycle for basic instructions
•
Logical address space: 4 Gbytes
•
Space identifier ASID: 8 bits, 256 logical address space
•
Five-stage pipeline
Rev. 5.00 Dec 12, 2005 page 2 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Item
Features
DSP
•
Mixture of 16-bit and 32-bit instructions
•
32-/40-bit internal data bus
•
Multiplier, ALU, barrel shifter and DSP register
•
16 bits x 16 bits → 32-bit one cycle multiplier
•
Large DSP data register
Six 32-bit data registers
Two 40-bit data registers
•
Extended Harvard Architecture for DSP data bus
Two data buses
One instruction bus
Clock pulse
generator (CPG)
•
Max. four parallel operations: ALU, multiply and two load or store
•
Two addressing units to generate addresses for two memory access
•
DSP data addressing modes: increment, indexing (with or without modulo
addressing)
•
Zero overhead repeat loop control
•
Conditional execution instructions
•
User-DSP mode and privileged-DSP mode
•
Clock mode: An input clock can be selected from the external input (EXTAL
or CKIO) or crystal oscillator.
•
Three types of clocks generated:
CPU clock: 1–16 times the input clock
Bus clock: 1–4 times the input clock
Peripheral clock: 1/4–4 times the input clock
•
Power-down modes:
Sleep mode
Standby mode
Module standby mode (X/Y memory standby enabled)
•
One-channel watchdog timer
Rev. 5.00 Dec 12, 2005 page 3 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Item
Features
Memory
management
unit (MMU)
•
4 Gbytes of address space, 256 address spaces (ASID 8 bits)
•
Page unit sharing
•
Supports multiple page sizes: 1 kbytes or 4 kbytes
•
128-entry, 4-way set associative TLB
•
Supports software selection of replacement method and randomreplacement algorithms
•
Contents of TLB can directly be accessed according to the address mapping
•
16-kbyte cache, mixed instruction/data
•
256 entries, 4-way set associative, 16-byte block length
•
Write-back, write-through, least recently used (LRU) replacement algorithm
•
1-stage write-back buffer
•
Maximum 2 ways of the cache can be locked
Cache memory
X/Y memory
•
User-selectable mapping mechanism
Fixed mapping for mission-critical realtime applications
Automatic mapping through TLB for easy to use
•
3 independent read/write ports
8-/16-/32-bit access from the CPU
Maximum two 16-bit accesses from the DSP
8-/16-/32-bit access from the DMAC
•
8-kbyte RAM for X and Y memory individually
Interrupt
controller (INTC)
•
7 external interrupt pins (NMI, IRQ5–IRQ0)
•
On-chip peripheral interrupts: set priority levels for each module
User break
controller (UBC)
•
2 break channels
•
Addresses, data values, type of access, and data size can all be set as
break conditions
•
Supports a sequential break function
Rev. 5.00 Dec 12, 2005 page 4 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Item
Features
Bus state
controller (BSC)
•
Physical address space divided into six areas (area 0, areas 2 to 6), each of
up to 64 Mbytes, with the following features settable for each area:
Bus size (8, 16, or 32 bits)
Number of wait cycles (hardware wait function also waited)
Direct connection of SRAM, synchronous DRAM, and burst ROM
possible by designating memory to be connected to each area
Supports PCMCIA interface (2 channels)
Chip select signals (CS0, CS2–CS6) for relevant area
•
Synchronous DRAM refresh function
Programmable refresh interval
Supports CAS-before-RAS refresh and self-refresh modes
Supports power-down DRAM
•
Synchronous DRAM burst access function
•
Big endian or little endian can be specified
Li bus state
•
controller (LBSC)
•
•
User debug
•
Interface (H-UDI)
•
Bus State Controller for LCDC or USB Host
Supports synchronous DRAM
Synchronous DRAM access function (area 3)
E10A emulator support
Pin arrangement conforming to JTAG specification
•
Realtime branch trace
•
3-channel auto-reload-type 32-bit timer
•
Choice of six counter input clocks
•
Maximum resolution: 2 MHz
Realtime clock
(RTC)
•
Built-in clock, calendar functions, and alarm functions
•
On-chip 32-kHz crystal oscillator circuit with a maximum resolution (cycle
interrupt) of 1/256 second
Serial communication interface
(SCI)
•
Asynchronous mode or clock synchronous mode can be selected
•
Full-duplex communication
•
Supports smart card interface
Timer (TMU)
Rev. 5.00 Dec 12, 2005 page 5 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Item
Features
Serial I/O (SIOF) •
•
Serial communication interface
(SCIF)
Supports 8-bit/16-bit mono/stereo sound playback or recording
•
DMA can be transferred
•
Supports frame sync signal
•
16-byte FIFO for transmission/reception
•
DMA can be transferred
•
On-chip modem control function
Direct memory
•
access controller
•
(DMAC)
•
PC card
controller
Synchronous 16 step, 8/16/32 bit word FIFO for transmission/reception
4 channels
Burst mode and cycle-steal mode
External request operating mode
•
1-channel 16-bit compare match timer
•
Supports control signals for one slot
•
Interchangeable with SH7709 when not in use (2 slots)
USB Host
•
controller (USBH)
•
Conforms to OHCI Rev. 1.0
USB Rev. 1.1 compatible
•
Up to 127 endpoints
•
Supports INT/BULK/CONTROL/ISO modes
•
Bus master controller (can access area 3 synchronous DRAM)
•
2 ports with analog transceiver (1of 2 is common with USB function)
•
External clock input function
USB Function
•
controller (USBF)
•
•
USB Rev. 1.1 compatible
Up to 4 endpoints
Supports INT/BULK/CONTROL modes (ISO mode not supported)
•
1 port with analog transceiver (common with Host), 12 Mbps only
•
External clock input function
Rev. 5.00 Dec 12, 2005 page 6 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Item
Features
LCD controller
(LCDC)
•
From 16 x 1 to 1024 x 1024 pixels can be supported
•
4/8/15/16 bpp (bit per pixel) color modes
•
1/2/4/6 bpp (bit per pixel) gray scale
•
8-bit Frame rate controller
•
TFT/DSTN/STN
•
Signal polarity setting function
•
Hardware panel rotation
•
Power control function
•
Selectable clock source (LCLK, bus clock (Bφ), or peripheral clock (Pφ))
•
ST7550 direct interface
•
Telephone line control
•
128-word FIFO for transfer
•
128-word FIFO for receive
I/O port
•
Thirteen 8-bit I/O ports
A/D converter
(ADC)
•
10 bits ± 4 LSB, 6 channels
•
Conversion time: 15 µs
•
Input range: 0–Vcc (max. 3.6 V)
•
8 bits ± 4 LSB, 2 channels
•
Conversion time: 10 µs
•
Output range: 0–Vcc (max. 3.6 V)
AFE I/F
D/A converter
(DAC)
Product lineup
Power Supply
Voltage
Internal
As of June 1, 2005
Operating
Frequency
SH7727
I/O
160 MHz
products
3.0 V to 1.70 V to 160 MHz
3.6 V
2.05 V
Model Name
Package
HD6417727F160C
240-pin plastic HQFP
(PRQP0240KC-B)
HD6417727BP160C 240-pin CSP
(PLBG0240JA-A)
100 MHz
products
2.6 V to 1.60 V to 100 MHz
3.6 V
2.05 V
HD6417727F100C
240-pin plastic HQFP
(PRQP0240KC-B)
HD6417727BP100C 240-pin CSP
(PLBG0240JA-A)
Rev. 5.00 Dec 12, 2005 page 7 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
1.2
Block Diagram
Internal SRAM
(XY RAM)
instruction/data
for CPU/DSP
16 kbytes
SuperH
CPU core
DSP core
Memory
management
unit
(MMU)
Cache memory
16 kbytes
CPU bus (L bus)
Bus state
controller
(BSC)
Direct
memory access
controller
(DMAC)
User
break
controller
(UBC)
Internal bus (I bus)
Real time
clock
(RTC)
Interrupt
controller
(INTC)
Bridge
Cache access
controller
(CCN)
Serial/
smart card
(SCI)
User
debug
interface
(H-UDI)
Clock
pulse
generator
(CPG)
Internal bus 2 (I2 bus)
Serial
communication
interface
(SCIF)
Timer
(TMU)
A/D
converter
(ADC)
D/A
converter
(DAC)
Peripheral bus
controller
Peripheral bus (P bus)
Peripheral bus 1 (P1 bus)
Arbitration
Peripheral bus 2 (P2 bus)
512-byte
SRAM
Li bus
state
controller
(LBSC)
Analog
front end
interface
(AFEIF)
128-byte
SRAM
Audio
CODEC
interface
(SIOF)
PC card
controller
(PCC)
USB
function
controller
(USBF)
288-byte
SRAM
LI bus
2.4-kbyte
line buffer
SRAM
LCD display
controller
(LCDC)
512-byte
pallet SRAM
Figure 1.1 Block Diagram
Rev. 5.00 Dec 12, 2005 page 8 of 1034
REJ09B0254-0500
USB host controller
(USBH)
Section 1 Overview and Pin Functions
Pin Description
1.3.1
Pin Arrangement
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
EXTAL
XTAL
Vcc
Vss
PCC0WAIT/PTH[6]/AUDCK
Vcc-PLL2
CAP2
Vss-PLL2
Vss-PLL1
CAP1
Vcc-PLL1
MD0
PCC0VS2/PTF[0]/Reserved
PCC0VS1/PTF[1]/Reserved
PCCREG/PTF[2]/Reserved
PTF[3]/PINT[11]/Reserved
PTF[4]/ PINT[12]/TCK
PTF[5]/PINT[13]/TDI
PTF[6]/PINT[14]/TMS
VccQ
PTF[7]/PINT[15]/TRST
VssQ
PCC0CD1/PTG[0]/AUDATA[0]
Vcc
PCC0CD2/PTG[1]/AUDATA[1]
Vss
PCC0BVD1/PTG[2]/AUDATA[2]
PCC0BVD2/PTG[3]/AUDATA[3]
PTG[4]
PTG[5]/ASEBRKAK
ASEMD0
IOIS16/PTG[7]
ADTRG/PTH[5]
RESETM
WAIT
PCC0DRV/DACK0
PCC0RESET/DRAK0
PTE[0]/TDO
PTE[3]/FLM
PTE[6]/M_DISP
PTD[7]/DON
Vcc
PTD[5]/CL1
Vss
Reserved/PTJ[5]
Reserved/PTJ[4]
VccQ
Reserved/PTJ[3]
VssQ
Reserved/CAS/PTJ[2]
Reserved/PTJ[1]
RAS3/PTJ[0]
CKE/PTK[5]
PTE[1]/USB2_pwr_en
PTE[2]/USB1_pwr_en
RTS2/USB1d_TXENL
USB2_ovr_cr nt
USB1_ovr_cr nt/USBF_VBUS
Reserved/USB1d_SUSPEND
PTM[4]/PINT[4]/
AFE_RDET
1.3
Vcc = 1.9 V, Vss = GND for CPU core
VccQ = 3.3 V, VssQ = GND for I/O buffer
Digital and PLL GND must be separated and isolated from the other signals
The order of pin name and default pin name has no relation. Please refer to
pin table.
SH-7727
PRQP0240KC-B
(Top View)
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PTM[5]/PINT[5]/AFE_TXOUT/USB1d_TXSE0
PTM[6]/PINT[6]/AFE_RXIN/USB1d_SPEED
PTM[7]/PINT[7]/AFE_FS/USB1d_RCV
VccQ
AFE_SCLK/USB1d_TXDPLS
VssQ
AFE_RLYCNT/USB1d_DMNS/PTK[1]
AFE_HC1/USB1d_DPLS/PTK[0]
CE2B/PTE[5]
CE2A/PTE[4]
CS6/CE1B
CS5/CE1A/PTK[3]
CS4/PTK[2]
CS3
CS2
CS0
PTE[7]/PCC0RDY/AUDSYNC
RD/WR
VccQ
WE3/DQMUU/ICIOWR/PTK[7]
VssQ
WE2/DQMUL/ICIORD/PTK[6]
WE1/DQMLU/WE
WE0/DQMLL
RD
BS/PTK[4]
A25
Vcc
A24
Vss
A23
A22
VccQ
A21
VssQ
A20
A19
A18
A17
A16
A15
A14
A13
VccQ
A12
VssQ
A11
A10
A9
A8
A7
A6
A5
A4
VccQ
A3
VssQ
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Vcc-RTC
XTAL2
EXTAL2
Vss-RTC
MD1
MD2
NMI
IRQ0/IRL0/PTH[0]
IRQ1/IRL1/PTH[1]
IRQ2/IRL2/PTH[2]
IRQ3/IRL3/PTH[3]
IRQ4/PTH[4]
VEPWC
VCPWC
MD5
BREQ
BACK
VssQ
CKIO2
VccQ
D31/PTB[7]
D30/PTB[6]
D29/PTB[5]
D28/PTB[4]
D27/PTB[3]
D26/PTB[2]
D25/PTB[1]
D24/PTB[0]
VssQ
D23/PTA[7]
VccQ
D22/PTA[6]
D21/PTA[5]
D20/PTA[4]
Vss
D19/PTA[3]
Vcc
D18/PTA[2]
D17/PTA[1]
D16/PTA[0]
D15
VssQ
D14
VccQ
D13
D12
D11
D10
D9
D8
D7
D6
VssQ
D5
VccQ
D4
D3
D2
D1
D0
LCD15/PTM[3]/PINT[10]
LCD14/PTM[2]/PINT[9]
LCD13/PTM[1]/PINT[8]
LCD12/PTM[0]
STATUS0/PTJ[6]
STATUS1/PTJ[7]
CL2/PTH[7]
VssQ
CKIO
VccQ
TxD0/SCPT[0]
SCK0/SCPT[1]
TxD_SIO/SCPT[2]
SIOMCLK/SCPT[3]
TxD2/SCPT[4]
SCK_SIO/SCPT[5]
SIOFSYNC/SCPT[6]
RxD0/SCPT[0]
RxD_SIO/SCPT[2]
Vss
RxD2/SCPT[4]
Vcc
SCPT[7]/CTS2/IRQ5
LCD11/PTC[7]/PINT[3]
LCD10/PTC[6]/PINT[2]
LCD9/PTC[5]/PINT[1]
VssQ
LCD8/PTC[4]/PINT[0]
VccQ
LCD7/PTD[3]
LCD6/PTD[2]
LCD5/PTC[3]
LCD4/PTC[2]
LCD3/PTC[1]
LCD2/PTC[0]
LCD1/PTD[1]
LCD0/PTD[0]
DREQ0/PTD[4]
LCLK/UCLK/PTD[6]
RESETP
CA
MD3
MD4
Scan_testen
AVcc_USB
USB1_P(analog)
USB1_M(analog)
AVss_USB
USB2_P(analog)
USB2_M(analog)
AVcc-USB
AVss
AN[2]/PTL[2]
AN[3]/PTL[3]
AN[4]/PTL[4]
AN[5]/PTL[5]
AVcc
AN[6]/PTL[6]/DA[1]
AN[7]/PTL[7]/DA[0]
AVss
Figure 1.2 Pin Arrangement (PRQP0240KC-B)
Rev. 5.00 Dec 12, 2005 page 9 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
1
2
3
4
5
6
7
8
VEP
NMI IRQ1
BACK D31
WC
A
Vcc- EXT MD1
RTC AL2
B
VCP
AN6 AVss Vss- XTAL2 MD2
VssQ D30
WC
RTC
C
AN5 AVcc
D
AN3
E
AVcc_
IRQ0 IRQ3 MD5 CKIO2 D29
USB
9
10
14
15
16
17
18
19
D27 VssQ D19
D16 VccQ D10
D6
D5
D4
D2
A0
D26
D17
D1
D3
D0
A2
D22
11
Vss
12
13
D14
D11 VccQ
D24 VccQ D21
D18 VssQ D12
D8
VssQ
D7
VssQ
A3
D25
Vcc
D9
A7
A5
A1
A4
AVss AN4 USB USB
2_M 2_P
A9
A8
VccQ
A6
F
AVss_ USB USB AVcc_
USB 1_M 1_P USB
A12 VssQ A11
G
Scan_ MD4 MD3
testen
A15
A14
A13 VccQ
A19
A18
A17
AN7
AN2 IRQ2 IRQ4 BREQ VccQ D28
D23
D20
CA
H
RES LCLK DRE LCD0
Q0
ETP
J
LCD1 LCD2 LCD4 LCD3
K
VccQ LCD5 LCD6 LCD7
L
SH7727
PLBG0240JA-A
(Top View)
D15
D13
A10
A16
A21 VccQ VssQ A20
A23
Vss
A24
A22
LCD10 LCD9 LCD8 VssQ
A25
Vcc
BS
RD
M
RxD2 Vcc SCPT7 LCD11
WE0 WE1 WE2 VssQ
N
RxD_
SIOF
RxD0
Vss
SIO
SYNC
WE3 VccQ RD/WR PTE7
P
TxD_ SIOM TxD2 SCK_
SIO CLK
SIO
CS0
CS2
R
CKIO
STA
TxD0 SCK0
TUS1
CS5
CS6 VssQ CE2B
CS3
CS4
T
AFE_
AFE_
CL2 LCD14 VssQ VccQ MD0 PTF3 VccQ Vcc PCC0 ASEM RESE PCC0 PTD7 PTJ5 VssQ PTJ1
PTM6
RLYCNT
HC1
BVD1 D0
TM RESET
U
STA LCD12 CAP1 Vss- Vcc- PCC PTF6 PCC0 PCC0 PTG5 ADT PTE0 Vcc PTJ4 CAS CKE CE2A VccQ AFE_
SCLK
PLL2 PLL1 REG
TUS0
CD1 BVD2
RG
V
LCD13 EXTAL Vss XTAL
W
USB1d_ USB2
Vcc- PCC0
PTF5 VssQ Vss PTG4 WAIT PTE3 PTD5 VccQ PTE2
PTM5 PTM7
SUSPEND ovr_crnt
PLL2 VS1
Vss- PCC0
LCD15 Vcc PCC0 CAP2
PTF4 PTF7 PCC0 IOIS16 PCC0 PTE6 Vss PTJ3 RAS3 PTE1 RTS2 USB1 PTM4
PLL1 VS2
WAIT
CD2
DRV
ovr_crnt
Figure 1.3 Pin Arrangement (PLBG0240JA-A)
Rev. 5.00 Dec 12, 2005 page 10 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
1.3.2
Table 1.2
Pin Functions
SH7727 Pin Function
Pin No.
Pin No.
(PRQP0240KC-B) (PLBG0240JA-A) Name
I/O
Function
1
A1
Vcc-RTC*1
—
RTC power supply (1.9 V)
2
B4
XTAL2
O
On-chip RTC crystal oscillator pin
3
A2
EXTAL2
I
On-chip RTC crystal oscillator pin
4
B3
Vss-RTC*1
—
RTC power supply (0 V)
5
A3
MD1
I
Clock mode setting
6
B5
MD2
I
Clock mode setting
7
A4
NMI
I
Nonmaskable interrupt request
8
C4
IRQ0/IRL0/PTH[0]
I/I/I
External interrupt / external interrupt /
input port H
9
A5
IRQ1/IRL1/PTH[1]
I/I/I
External interrupt / external interrupt /
input port H
10
D4
IRQ2/IRL2/PTH[2]
I/I/I
External interrupt / external interrupt /
input port H
11
C5
IRQ3/IRL3/PTH[3]
I/I/I
External interrupt / external interrupt /
input port H
12
D5
IRQ4/PTH[4]
I/I
External interrupt request / input port H
13
A6
VEPWC
O
LCD panel VEE control
14
B6
VCPWC
O
LCD panel VCC control
15
C6
MD5
I
Endian setting
16
D6
BREQ
I
Bus request
17
A7
BACK
O
Bus acknowledge
18
B7
VssQ
—
Input/output power supply (0 V)
19
C7
CKIO2
O
System clock output
20
D7
VccQ
—
Input/output power supply (3.3 V)
21
A8
D31/PTB[7]
IO/IO
Data bus / I/O port B
22
B8
D30/PTB[6]
IO/IO
Data bus / I/O port B
23
C8
D29/PTB[5]
IO/IO
Data bus / I/O port B
24
D8
D28/PTB[4]
IO/IO
Data bus / I/O port B
25
A9
D27/PTB[3]
IO/IO
Data bus / I/O port B
26
B9
D26/PTB[2]
IO/IO
Data bus / I/O port B
27
D9
D25/PTB[1]
IO/IO
Data bus / I/O port B
Rev. 5.00 Dec 12, 2005 page 11 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Pin No.
Pin No.
(PRQP0240KC-B) (PLBG0240JA-A) Name
I/O
Function
28
C9
D24/PTB[0]
IO/IO
Data bus / I/O port B
29
A10
VssQ
—
Input/output power supply (0 V)
30
D10
D23/PTA[7]
IO/IO
Data bus / I/O port A
31
C10
VccQ
—
Input/output power supply (3.3 V)
32
B10
D22/PTA[6]
IO/IO
Data bus / I/O port A
33
C11
D21/PTA[5]
IO/IO
Data bus / I/O port A
34
D11
D20/PTA[4]
IO/IO
Data bus / I/O port A
35
B11
Vss
—
Power supply (0 V)
36
A11
D19/PTA[3]
IO/IO
Data bus / I/O port A
37
D12
Vcc
—
Power supply (1.9 V)
38
C12
D18/PTA[2]
IO/IO
Data bus / I/O port A
39
B12
D17/PTA[1]
IO/IO
Data bus / I/O port A
40
A12
D16/PTA[0]
IO/IO
Data bus / I/O port A
41
D13
D15
IO
Data bus
42
C13
VssQ
—
Input/output power supply (0 V)
43
B13
D14
IO
Data bus
44
A13
VccQ
—
Input/output power supply (3.3 V)
45
D14
D13
IO
Data bus
46
C14
D12
IO
Data bus
47
B14
D11
IO
Data bus
48
A14
D10
IO
Data bus
49
D15
D9
IO
Data bus
50
C15
D8
IO
Data bus
51
C17
D7
IO
Data bus
52
A15
D6
IO
Data bus
53
C16
VssQ
—
Input/output power supply (0 V)
54
A16
D5
IO
Data bus
55
B15
VccQ
—
Input/output power supply (3.3 V)
56
A17
D4
IO
Data bus
57
B17
D3
IO
Data bus
58
A18
D2
IO
Data bus
59
B16
D1
IO
Data bus
60
B18
D0
IO
Data bus
Rev. 5.00 Dec 12, 2005 page 12 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Pin No.
Pin No.
(PRQP0240KC-B) (PLBG0240JA-A) Name
I/O
Function
61
A19
O
Address bus
62
D18
A1
O
Address bus
63
B19
A2
O
Address bus
64
C18
VssQ
—
Input/output power supply (0 V)
65
C19
A3
O
Address bus
66
E18
VccQ
—
Input/output power supply (3.3 V)
67
D19
A4
O
Address bus
68
D17
A5
O
Address bus
69
E19
A6
O
Address bus
70
D16
A7
O
Address bus
71
E17
A8
O
Address bus
72
E16
A9
O
Address bus
73
F19
A10
O
Address bus
74
F18
A11
O
Address bus
75
F17
VssQ
—
Input/output power supply (0 V)
76
F16
A12
O
Address bus
77
G19
VccQ
—
Input/output power supply (3.3 V)
78
G18
A13
O
Address bus
79
G17
A14
O
Address bus
80
G16
A15
O
Address bus
81
H19
A16
O
Address bus
82
H18
A17
O
Address bus
83
H17
A18
O
Address bus
84
H16
A19
O
Address bus
A0
85
J19
A20
O
Address bus
86
J18
VssQ
—
Input/output power supply (0 V)
87
J16
A21
O
Address bus
88
J17
VccQ
—
Input/output power supply (3.3 V)
89
K19
A22
O
Address bus
90
K16
A23
O
Address bus
91
K17
Vss
—
Power supply (0 V)
92
K18
A24
O
Address bus
93
L17
Vcc
—
Power supply (1.9 V)
Rev. 5.00 Dec 12, 2005 page 13 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Pin No.
Pin No.
(PRQP0240KC-B) (PLBG0240JA-A) Name
I/O
Function
94
L16
A25
O
Address bus
95
L18
BS/PTK[4]
O/IO
Bus cycle start signal / I/O port K
96
L19
RD
O
Read strobe
97
M16
WE0/DQMLL
O/O
D7–D0 select signal / DQM (SDRAM)
98
M17
WE1/DQMLU/WE
O/O/O
D15–D8 select signal /
DQM (SDRAM) / PCMCIA WE
99
M18
WE2/DQMUL/
ICIORD/PTK[6]
O/O/
O/IO
D23–D16 select signal /
DQM (SDRAM) / PCMCIA I/O read /
I/O port K
100
M19
VssQ
—
Input/output power supply (0 V)
101
N16
WE3/DQMUU/
ICIOWR/PTK[7]
O/O/
O/IO
D31–D24 select signal /
DQM (SDRAM) / PCMCIA I/O write /
I/O port K
102
N17
VccQ
—
Input/output power supply (3.3 V)
103
N18
RD/WR
O
Read/write
104
N19
PTE[7]/PCC0RDY/
AUDSYNC
IO/I/O
I/O port E / PCMCIA0 ready / AUD
synchronization
105
P16
CS0
O
Chip select 0
106
P17
CS2
O
Chip select 2
107
P18
CS3
O
Chip select 3
108
P19
CS4/PTK[2]
O/IO
Chip select 4 / I/O port K
109
R16
CS5/CE1A/PTK[3]
O/O/IO
Chip select 5 / CE1 (area 5 PCMCIA) /
I/O port K
110
R17
CS6/CE1B
O/O
Chip select 6 / CE1 (area 6 PCMCIA)
111
U17
CE2A/PTE[4]
O/IO
Area 5 PCMCIA card enable /
I/O port E
112
R19
CE2B/PTE[5]
O/IO
Area 6 PCMCIA card enable /
I/O port E
113
T17
AFE_HC1/
USB1d_DPLS/
PTK[0]
O/I/IO
AFE hardware control signal /
D+ signal input / I/O port K
114
T19
AFE_RLYCNT/
USB1d _DMNS/
PTK[1]
O/I/IO
AFE relay control signal / D- signal
input / I/O port K
115
R18
VssQ
—
Input/output power supply (0 V)
116
U19
AFE_SCLK/
USB1d _TXDPLS
I/O
AFE clock / D+ transmit output
117
U18
VccQ
—
Input/output power supply (3.3 V)
Rev. 5.00 Dec 12, 2005 page 14 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Pin No.
Pin No.
(PRQP0240KC-B) (PLBG0240JA-A) Name
I/O
Function
118
V19
PTM[7]/PINT[7]/
AFE_FS/
USB1d_RCV
I/I/I/I
Input port M / port interrupt / AFE frame
synchronization / receive data input
119
T18
PTM[6]/PINT[6]/
AFE_RXIN/
USB1d_SPEED
I/I/I/O
Input port M / port interrupt / AFE
receive data / transceiver speed control
120
V18
PTM[5]/PINT[5]/
AFE_TXOUT/
USB1d_TXSE0
I/I/O/O
Input port M / port interrupt / AFE
transmit data / SE0 output
121
W19
PTM[4]/PINT[4]/
AFE_RDET
I/I/I
Input port M / port interrupt / AFE
ringing detection
122
V16
Reserved/
USB1d_SUSPEND
O/O
Reserved/Transceiver suspend state
output
123
W18
USB1_ovr_crnt/
USBF_VBUS
I/I
USB host 1 overcurrent detection /
USB function VBUS
124
V17
USB2_ovr_crnt
I
USB host 2 overcurrent detection
125
W17
RTS2/
USB1d_TXENL
O/O
SCIF RTS pin / USB output enable pin
126
V15
PTE[2]/
USB1_pwr_en
IO/O
I/O port E / USB1 voltage control
127
W16
PTE[1]/
USB2_pwr_en
IO/O
I/O port E / USB2 voltage control
128
U16
CKE/PTK[5]
O/IO
CK enable (SDRAM) / I/O port K
129
W15
RAS3/PTJ[0]
O/IO
RAS for SDRAM / I/O port J
130
T16
Reserved/PTJ[1]
O/IO
Reserved / I/O port J
131
U15
Reserved/CAS/
PTJ[2]
O/O/IO
Reserved / CAS for SDRAM / I/O port J
132
T15
VssQ
—
Input/output power supply (0 V)
133
W14
Reserved/PTJ[3]
O/IO
Reserved / I/O port J
134
V14
VccQ
—
Input/output power supply (3.3 V)
135
U14
Reserved/PTJ[4]
O/IO
Reserved / I/O port J
136
T14
Reserved/PTJ[5]
O/IO
Reserved / I/O port J
137
W13
Vss
—
Power supply (0 V)
138
V13
PTD[5]/CL1
IO/O
I/O port D / LCD line clock
139
U13
Vcc
—
Power supply (1.9 V)
140
T13
PTD[7]/DON
IO/O
I/O port D / LCD DISPLAY on
141
W12
PTE[6]/M_DISP
IO/O
I/O port E / LCD alternating signal /
DISP signal
Rev. 5.00 Dec 12, 2005 page 15 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Pin No.
Pin No.
(PRQP0240KC-B) (PLBG0240JA-A) Name
I/O
Function
142
PTE[3]/FLM
IO/O
I/O port E / LCD frame line marker
V12
143
U12
PTE[0]/TDO
IO/O
I/O port E / test data output
144
T12
PCC0RESET/
DRAK0
O/O
PCC reset / DMA request receive
145
W11
PCC0DRV/DACK0
O/O
PCC buffer control / DMA acknowledge
0
146
V11
WAIT
I
Hardware wait request
147
T11
RESETM
I
Manual reset request
148
U11
ADTRG/PTH[5]
I/I
Analog trigger / input port H
149
W10
IOIS16/PTG[7]
I/I
IOIS16 (PCMCIA) / input port G
150
T10
ASEMD0
I
ASE mode
151
U10
PTG[5]/ASEBRKAK
I/O
Input port G / ASE break acknowledge
I
Input port G
152
V10
PTG[4]
153
U9
PCC0BVD2/PTG[3]/ I/I/O
AUDATA[3]
PCC BVD2 pin / input port G /
AUD data
154
T9
PCC0BVD1/PTG[2]/ I/I/O
AUDATA[2]
PCC BVD1 pin / input port G /
AUD data
155
V9
Vss
—
Power supply (0 V)
156
W9
PCC0CD2/PTG[1]/
AUDATA[1]
I/I/O
PCMCIA0 CD2 pin / input port G /
AUD data
157
T8
Vcc
—
Power supply (1.9 V)
158
U8
PCC0CD1/PTG[0]/
AUDATA[0]
I/I/O
PCC CD1 pin / input port G / AUD data
159
V8
VssQ
—
Input/output power supply (0 V)
160
W8
PTF[7]/PINT[15]/
TRST
I/I/I
Input port F / port interrupt / test reset
161
T7
VccQ
—
Input/output power supply (3.3 V)
162
U7
PTF[6]/PINT[14]/
TMS
I/I/I
Input port F / port interrupt /
test mode switch
163
V7
PTF[5]/PINT[13]/
TDI
I/I/I
Input port F / port interrupt /
test data input
164
W7
PTF[4]/PINT[12]/
TCK
I/I/I
Input port F / port interrupt /
test clock
165
T6
PTF[3]/PINT[11]/
Reserved
I/I/O
Input port F / port interrupt / Reserved
166
U6
PCCREG/PTF[2]/
Reserved
O/I/O
PCC REG pin / input port F/ Reserved
Rev. 5.00 Dec 12, 2005 page 16 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Pin No.
Pin No.
(PRQP0240KC-B) (PLBG0240JA-A) Name
I/O
Function
167
V6
PCC0VS1/PTF[1]/
Reserved
I/I/O
PCC VS1 pin / input port F/ Reserved
168
W6
PCC0VS2/PTF[0]/
Reserved
I/I/IO
PCC VS2 pin / input port F/ Reserved
169
T5
MD0
I
Clock mode setting
170
U5
Vcc-PLL1*2
—
PLL1 power supply (1.9 V)
171
U3
CAP1
—
PLL1 external capacitance pin
172
W5
Vss-PLL1*2
—
PLL1 power supply (0 V)
173
U4
Vss-PLL2*2
—
PLL2 power supply (0 V)
174
W4
CAP2
—
PLL2 external capacitance pin
175
V5
Vcc-PLL2*2
—
PLL2 power supply (1.9V)
176
W3
PCC0WAIT/PTH[6]/
AUDCK
I/I/I
PCC hardware wait request /
input port H / AUD clock
177
V3
Vss
—
Power supply (0 V)
178
W2
Vcc
—
Power supply (1.9 V)
179
V4
XTAL
O
Clock oscillator
180
V2
EXTAL
I
External clock / crystal oscillator
181
W1
LCD15/PTM[3]/
PINT[10]
O/I/I
LCD data output / input port M /
port interrupt
182
T2
LCD14/PTM[2]/
PINT[9]
O/I/I
LCD data output / input port M /
port interrupt
183
V1
LCD13/PTM[1]/
PINT[8]
O/I/I
LCD data output / input port M /
port interrupt
184
U2
LCD12/PTM[0]
O/I
LCD data output / input port M
185
U1
STATUS0/PTJ[6]
O/IO
Processor status / I/O port J
186
R2
STATUS1/PTJ[7]
O/IO
Processor status / I/O port J
187
T1
CL2/PTH[7]
O/IO
LCD clock output / I/O port H
188
T3
VssQ
—
Input/output power supply (0 V)
189
R1
CKIO
IO
System clock input/output
190
T4
VccQ
—
Input/output power supply (3.3 V)
191
R3
TxD0/SCPT[0]
O/O
Transmit data 0 / SCI output port
192
R4
SCK0/SCPT[1]
IO/IO
Serial clock 0 / SCI I/O port
193
P1
TxD_SIO/SCPT[2]
O/O
SIOF transmit data / SCI output port
194
P2
SIOMCLK/SCPT[3]
I/IO
SIOF clock input / SCI I/O port
195
P3
TxD2/SCPT[4]
O/O
Transmit data 2 / SCI output port
Rev. 5.00 Dec 12, 2005 page 17 of 1034
REJ09B0254-0500
Section 1 Overview and Pin Functions
Pin No.
Pin No.
(PRQP0240KC-B) (PLBG0240JA-A) Name
I/O
Function
196
P4
SCK_SIO/SCPT[5]
IO/IO
SIOF communication clock /
SCI I/O port
197
N1
SIOFSYNC/SCPT[6] IO/IO
SIOF frame synch. / SCI I/O port
198
N2
RxD0/SCPT[0]
I/I
Receive data 0 / SCI input port
199
N3
RxD_SIO/SCPT[2]
I/I
SIOF receive data / SCI input port
200
N4
Vss
—
Power supply (0 V)
201
M1
RxD2/SCPT[4]
I/I
Receive data 2 / SCI input port
202
M2
Vcc
—
Power supply (1.9 V)
203
M3
SCPT[7]/CTS2/IRQ5 I/I/I
SCI input port / SCIF clear to send /
external interrupt request
204
M4
LCD11/PTC[7]/
PINT[3]
O/IO/I
LCD data out / I/O port C /
port interrupt
205
L1
LCD10/PTC[6]/
PINT[2]
O/IO/I
LCD data out / I/O port C / port
interrupt
206
L2
LCD9/PTC[5]/
PINT[1]
O/IO/I
LCD data out / I/O port C / port
interrupt
207
L4
VssQ
—
Input/output power supply (0 V)
208
L3
LCD8/PTC[4]/
PINT[0]
O/IO/I
LCD data out / I/O port C / port
interrupt
209
K1
VccQ
—
Input/output power supply (3.3 V)
210
K4
LCD7/PTD[3]
O/IO
LCD data out / I/O port D
211
K3
LCD6/PTD[2]
O/IO
LCD data out / I/O port D
212
K2
LCD5/PTC[3]
O/IO
LCD data out / I/O port C
213
J3
LCD4/PTC[2]
O/IO
LCD data out / I/O port C
214
J4
LCD3/PTC[1]
O/IO
LCD data out / I/O port C
215
J2
LCD2/PTC[0]
O/IO
LCD data out / I/O port C
216
J1
LCD1/PTD[1]
O/IO
LCD data out / I/O port D
217
H4
LCD0/PTD[0]
O/IO
LCD data out / I/O port D
218
H3
DREQ0/PTD[4]
I/I
DMA request / input port D
219
H2
LCLK/UCLK/PTD[6]
I/I/I
LCD clock / USB clock / input port D
220
H1
RESETP
I
Power-on reset request
221
G4
CA
I
Hardware standby request
222
G3
MD3
I
Area 0 bus width setting
223
G2
MD4
I
Area 0 bus width setting
224
G1
Scan_testen
I
Test pin (fixed to 3.3 V)
225
F4
AVcc_USB
—
USB analog power supply (3.3 V)
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Section 1 Overview and Pin Functions
Pin No.
Pin No.
(PRQP0240KC-B) (PLBG0240JA-A) Name
I/O
Function
226
IO
USB1 data I/O (plus)
F3
USB1_P(analog)
227
F2
USB1_M(analog)
IO
USB1 data I/O (minus)
228
F1
AVss_USB
—
USB analog power supply (0 V)
229
E4
USB2_P(analog)
IO
USB2 data I/O (plus)
230
E3
USB2_M(analog)
IO
USB2 data I/O (minus)
231
C3
AVcc_USB
—
USB analog power supply (3.3 V)
232
E1
AVss
—
Analog power supply (0 V)
233
D3
AN[2]/PTL[2]
I/I
A/D converter input / input port L
234
D1
AN[3]/PTL[3]
I/I
A/D converter input / input port L
235
E2
AN[4]/PTL[4]
I/I
A/D converter input / input port L
236
C1
AN[5]/PTL[5]
I/I
A/D converter input / input port L
237
C2
AVcc
—
Analog power supply (3.3 V)
238
B1
AN[6]/PTL[6]/DA[1]
I/I/O
A/D converter input / input port L /
D/A converter output
239
D2
AN[7]/PTL[7]/DA[0]
I/I/O
A/D converter input / input port L /
D/A converter output
240
B2
AVss
—
Analog power supply (0 V)
Notes: All Vcc/Vss should be connected to the all system power supply (so that power is supplied
at all times).
1. Always supply power to the Vcc-RTC, even if RTC is not being used.
2. Always supply power to the Vcc-PLL, even if the internal PLL is not being used.
3. Drive high when using the user system alone, and not using an emulator or the H-UDI.
When this pin is low or open, RESETP may be masked.
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Section 2 CPU
2.1
Registers
The SH7727 has the same registers as in SH-3. In addition, the SH7727 also support the same
DSP-related registers seen in SH-DSP. The basic software-accessible registers are divided into
four distinct groups:
• General-purpose registers
• Control registers
• System registers
• DSP registers
With the exception of a number of DSP registers, all of these registers are 32-bit width. The
general-purpose registers are accessible from the user mode, with R0 to R7 banked to provide each
processor mode access to a separate set of the R0 to R7 registers (i.e. R0 to R7_BANK0, and R0
to R7_BANK1). In the privileged mode, the register bank (RB) bit in the status register (SR)
defines which set of banked registers (R0 to R7_BANK0 or R0 to R7_BANK1) is accessed as
general-purpose registers, and which are accessed only by the LDC/STC instructions.
The control registers can be accessed by the LDC/STC instructions. The GBR, RS, RE, and MOD
registers can also be accessed in user mode. Control registers are:
• SR: Status register
• SSR: Saved status register
• SPC: Saved program counter
• GBR: Global base register
• VBR: Vector base register
• RS: Repeat start register (DSP mode only)
• RE: Repeat end register (DSP mode only)
• MOD: Modulo register (DSP mode only)
The system registers are accessed by the LDS/STS instructions (the PC cannot be accessed by
software, but is included here because its contents are saved in, and restored from, SPC). The
system registers are:
• MACH: Multiply and accumulate high register
• MACL: Multiply and accumulate low register
• PR: Procedure register
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Section 2 CPU
• PC: Program counter
This section explains the usage of these registers in different modes.
Figures 2.1 and 2.2 show the register configuration in each processing mode.
Switching between user mode and privileged mode is carried out by means of the processing
operation mode bit (MD) in the status register.
The DSP mode is switched by means of the DSP bit in the status register.
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Section 2 CPU
31
0
31
0
31
0
R0_BANK0*1 *2
R1_BANK0*2
R2_BANK0*2
R3_BANK0*2
R4_BANK0*2
R5_BANK0*2
R6_BANK0*2
R7_BANK0*2
R8
R9
R10
R11
R12
R13
R14
R15
R0_BANK1*1 *3
R1_BANK1*3
R2_BANK1*3
R3_BANK1*3
R4_BANK1*3
R5_BANK1*3
R6_BANK1*3
R7_BANK1*3
R8
R9
R10
R11
R12
R13
R14
R15
R0_BANK0*1 *4
R1_BANK0*4
R2_BANK0*4
R3_BANK0*4
R4_BANK0*4
R5_BANK0*4
R6_BANK0*4
R7_BANK0*4
R8
R9
R10
R11
R12
R13
R14
R15
SR
SR
SSR
SR
SSR
GBR
MACH
MACL
PR
GBR
MACH
MACL
PR
VBR
GBR
MACH
MACL
PR
PC
SPC
PC
SPC
R0_BANK0*1 *4
R1_BANK0*4
R2_BANK0*4
R3_BANK0*4
R4_BANK0*4
R5_BANK0*4
R6_BANK0*4
R7_BANK0*4
R0_BANK1*1 *3
R1_BANK1*3
R2_BANK1*3
R3_BANK1*3
R4_BANK1*3
R5_BANK1*3
R6_BANK1*3
R7_BANK1*3
PC
(a) User mode register
configuration
VBR
(b) Privileged mode register
configuration (RB = 1)
(c) Privileged mode register
configuration (RB = 0)
Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode and
indexed GBR indirect addressing mode.
2. Bank register
3. Bank register
Accessed as a general register when the RB bit is set to 1 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is cleared to 0.
4. Bank register
Accessed as a general register when the RB bit is cleared to 0 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is set to 1.
Figure 2.1 Register Configuration in Each Processing Mode (1)
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Section 2 CPU
0
32 31
A0G
A1G
A0
A1
M0
M1
X0
X1
Y0
Y1
DSR
MS
ME
MOD
(d) DSP mode register configuration (DSP = 1)
Figure 2.2 Register Configuration in Each Processing Mode (2)
Register values after a reset are shown in table 2.1.
Table 2.1
Initial Register Values
Type
Registers
Initial Value*
General registers
R0 to R15
Undefined
Control registers
SR
MD bit = 1, RB bit = 1, BL bit = 1, I3 to
I0 = 1111 (H'F), reserved bits = 0,
others undefined
GBR, SSR, SPC
Undefined
VBR
H'00000000
System registers
DSP registers
RS, RE
Undefined
MOD
Undefined
MACH, MACL, PR
Undefined
PC
H'A0000000
A0, A0G, A1, A1G, M0, M1,
X0, X1, Y0, Y1
Undefined
DSR
H'00000000
Note: * Initialized by a power-on or manual reset.
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Section 2 CPU
2.1.1
General Purpose Registers
There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are
used for data processing and address calculation.
With SuperH microcomputer type instructions, R0 is used as an index register. With a number of
instructions, R0 is the only register that can be used. R15 is used as the stack pointer (SP). In
exception handling, R15 is used to reference the stack when saving and restoring the status register
(SR) and program counter (PC).
With DSP type instructions, eight of the sixteen general registers are used for addressing of X and
Y data memory and data memory (single data) that uses the L-bus.
To access X memory, R4 and R5 are used as X address register [Ax] and R8 is used as X index
register [Ix]. To access Y memory, R6 and R7 are used as Y address register [Ay] and R9 is used
as Y index register [Iy]. To access single data that uses the L-bus, R2, R3, R4, and R5 are used as
single data address register [As] and R8 is used as single data index register [Is].
Figure 2.3 shows the general purpose registers, which are identical to SH-3’s, when DSP
extension is disabled.
0
31
R0*1 *2
General Registers (when not in DSP mode)
R1*2
R2*2
R3*2
R4*2
R5*2
R6*2
R7*2
R8
R9
Notes: 1. R0 functions as an index register in the
indexed register-indirect addressing mode
and indexed GBR-indirect addressing mode.
In some instructions, only R0 can be used as
the source register or destination register.
2. R0 to R7 are banked registers. In user mode,
BANK0 is used. In privileged mode, SR.RB
specifies BANK.
SR.RB = 0; BANK0 is used
SR.RB = 1; BANK1 is used
R10
R11
R12
R13
R14
R15
Figure 2.3 General Purpose Register (Not in DSP Mode)
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On the other hand, R2 to R9 registers are also used for the DSP data address calculations, see
figure 2.4, when DSP extension is enabled. Another symbol that represents the purpose of the
registers in DSP type instruction is [ ].
31
0
General Registers (DSP mode enabled)
R0
R1
R2 [As]
R3 [As]
R4 [As, Ax]
X or Y data transfer operation
R4, R5 [Ax]: Address register set for X data memory.
R8 [x]:
Index register for address register set Ax.
R5 [As, Ax]
R6, R7 [Ay]:
R9 [Iy]:
R6 [Ay]
Address register set for Y data memory.
Index register for address register set Ay.
R7 [Ay]
R8 [Ix, Is]
R9 [Iy]
Single data transfer operation
R2 to R5 [As]: Address register set for memory.
R8 [Is]:
Index register for address register set As.
R10
R11
R12
R13
R14
R15
Figure 2.4 General Purpose Register (DSP Mode)
DSP type instructions can access X and Y data memory simultaneously. To specify addresses for
X and Y data memory, two address pointer sets are prepared. These are:
R8[Ix], R4, R5[Ax] for X memory access, and R9[Iy], R6, R7[Ay] for Y memory access.
The names (symbol) R2 to R9 are used in the Assembler, but users can use other register names
that represent the purpose of the register in the DSP instruction explicitly. In the assembly
program, user can use an alias for the register. The coding in assembler is as follows.
Ix: .REG (R8)
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Section 2 CPU
The name Ix is the alias for R8. Other aliases are as follows.
Ax0:
.REG
(R4)
Ax1:
.REG
(R5)
Ix:
.REG
(R8)
Ay0:
.REG
(R6)
Ay1:
.REG
(R7)
Iy:
.REG
(R9)
As0:
.REG
(R4) ; This is optional. If you need another alias for single data transfer.
As1:
.REG
(R5) ; This is optional. If you need another alias for single data transfer.
As2:
.REG
(R2)
As3:
.REG
(R3)
Is:
.REG
(R8) ; This is optional. If you need another alias for single data transfer.
2.1.2
Control Registers
SH7727 has eight control registers: SR, SSR, SPC, GBR, VBR, RS, RE, and MOD (figure 2.5).
SSR, SPC, GBR and VBR are the same as the SH-3 registers. The DSP mode is activated only
when SR.DSP = 1.
Repeat start register RS, repeat end register RE, and repeat counter RC (12-bit part of the SR) and
repeat control bits RF0 and RF1 are new registers and control bits which are used for repeat
control. Modulo register MOD and modulo control bits DMX and DMY in the SR are also new
register and control bits.
In the SR, there are six additional control bits: RC[11:0], RF0, RF1, DMX, DMY and DSP. Bits
DMX, DMY, RC[11:0], and RF[1:0] can be modified in supervisor mode, DSP supervisor mode,
and DSP user mode. The DMX and DMY are used for modulo addressing control. If the DMX is
1 then the modulo addressing mode is effective for the X memory address pointer, Ax (R4 or R5).
If the DMY is 1 then it is effective for the Y memory address pointer, Ay (R6 or R7). However,
both X and Y address pointer cannot be operated under the modulo addressing mode even though
both DMX and DMY bits are set. The case of DMX = DMY = 1 is reserved for future expansion.
When both DMX and DMY are set simultaneously, the hardware will preliminary treat only
address pointer as the modulo addressing mode. Modulo addressing is available for X and Y data
transfer operation (MOVX and MOVY), but not for single data transfer operation (MOVS).
The RF1 and RF0 hold information of the number of repeat steps and they are set when a SETRC
instruction is executed. When RF[1:0] shows 00, the current repeat module consists of one-step
instruction. When RF[1:0] = 01, it means two-step instructions. When RF[1:0] = 11, it means
Rev. 5.00 Dec 12, 2005 page 27 of 1034
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Section 2 CPU
three-step instruction. When RF[1:0] = 10, it means the current repeat module consists of four or
more instructions.
Although RC[11:0] and RF[1:0] can be changed by a store/load to SR, use of the dedicated
manipulation instruction SETRC is recommended.
The SR also has a 12-bit repeat counter RC which is used for efficient loop control. Repeat start
register (RS) and repeat end register (RE) are also introduced for the loop control. They keep the
start and end addresses of a loop (the contents of the registers, RS and RE are slightly different
from the actual loop start and end address).
Modulo register, MOD is introduced to realize modulo addressing for circular data buffering.
MOD keeps the modulo start address (MS) and the modulo end address (ME).
In order to access RS, RE and MOD, load/store (control register) instructions for them are
introduced. An example for RS is as follows:
LDC Rm,RS;
Rm → RS
LDC.L @Rm+,RS;
(Rm) → RS, Rm+4 → Rm
STC RS,Rn;
RS → Rn
STC.L RS,@-Rn;
Rn-4 → Rn, RS → (Rn)
Address set instructions for the RS and RE are also prepared.
LDRS @(disp,PC); disp × 2 + PC → RS
LDRE @(disp,PC); disp × 2 + PC → RE
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31
28 27
0 MD RB BL
16 15 13 12
RC
0-0
11
10
9
8
7
6
5
4
3
2
1
0
DSP DMY DMX M Q
I3
I2 I1 I0 RF1 RF0 S
T
SR (Status register)
MD bit:
Processor operation mode
MD = 1: Privileged mode
MD = 0: User mode
RB bit:
Register bank bit; used to define the general registers in privileged mode.
RB = 1: R0_BANK1 to R7_BANK1 are used as general registers.
R0_BANK0 to R7_BANK0 accessed by LDC/STC instructions.
RB = 0: R0_BANK0 to R7_BANK0 are used as general registers.
R0_BANK1 to R7_BANK1 accessed by LDC/STC instructions.
BL bit:
Block bit; used to mask exception in privileged mode.
BL = 1: Interrupts are masked (not accepted)
BL = 0: Interrupts are accepted
RC [11:0]: 12-bit repeat counter
DSP bit:
DSP operation mode
DSP = 1: DSP instructions (LDS Rm, DSR/A0/X0/X1/Y0/Y1,
LDS.L @Rm+, DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1, Rn,
STS.L DSR/A0/X0/X1/Y0/Y1, @−Rn, LDC Rm, RS/RE/MOD,
LDC.L @Rm+, RS/RE/MOD, STC RS/RE/MOD,Rn, STC.L RS/RE/MOD, @−Rn,
LDRS, LDRE, SETRC, MOVS, MOVX, MOVY, Pxxx) are enabled.
DSP = 0: All DSP instructions are treated as illegal instructions; only SH3 instructions are
supported.
DMY bit:
Modulo addressing enable for Y side
DMX bit:
Modulo addressing enable for X side
Q, M bit:
Used by DIV0U/S and DIV1 instructions.
I [3:0]:
4-bit field indicating the interrupt request mask level.
RF [1:0]:
Used for repeat control
S bit:
Used by the MAC instructions and DSP data.
T bit:
The MOVT, CMP/cond, TAS, TST, BT, BF, SETT, CLRT and DT instructions use the T bit to
indicate true (logic one) or false (logic zero). The ADDV/C, SUBV/C, DIV0U/S, DIV1,
NEGC, SHAR/L, SHLR/L, ROTR/L and ROTCR/L instructions also use the T bit to indicate
a carry, borrow, overflow, or underflow.
Reserved bits: Always read as 0, and should always be written with 0 (bit 31, bits 15 to 13).
Figure 2.5 Control Registers (1)
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31
0
Saved status register (SSR)
SSR
31
0
Saved program counter (SPC)
SPC
31
0
GBR
Global base register
31
0
VBR
Vector base register
31
0
RS
Repeat start register
31
0
RE
31
MOD
Repeat end register
16 15
ME
0
MS
Modulo register
ME: Modulo end address, MS: Modulo start address
Saved status register (SSR)
Stores current SR value at time of exception to indicate processor status when returning to instruction
stream from exception handler.
Saved program counter (SPC)
Stores current PC value at time of exception to indicate return address on completion of exception
handling.
Global base register (GBR)
Stores base address of GBR-indirect addressing mode. The GBR-indirect addressing mode is used for
data transfer and logical operations on the on-chip peripheral module register area.
Vector base register (VBR)
Stores base address of exception vector area.
Repeat start register (RS)
Used in DSP mode only. Indicates start address of repeat loop.
Repeat end register (RE)
Used in DSP mode only. Indicates address of repeat loop end.
Modulo register (MOD)
Used in DSP mode only.
MOD[31:16]: ME: Modulo end address, MOD[15:0]: MS: Modulo start address.
In X/Y operand address generation, the CPU compares the address with ME, and if it is the same,
loads MS in either the X or Y operand address register (depending on bits DMX and DMY in the SR
register).
Figure 2.5 Control Registers (2)
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Section 2 CPU
2.1.3
System Registers
The SH7727 has four system registers, MACL, MACH, PR and PC (figure 2.6).
31
0
Multiply and accumulate high and low registers
(MACH/L)
Store the results of multiplicationand accumulation
operations.
MACH
MACL
31
0
Procedure register (PR)
Stores the subroutine procedure return address.
PR
31
0
PC
Program counter (PC)
Indicates the starting address that is four addresses ahead.
Figure 2.6 System Registers
DSR, A0, X0, X1, Y0 and Y1 registers are also treated as system registers. So, data transfer
instructions between general registers and system registers are supported for them.
2.1.4
DSP Registers
The SH7727 has eight data registers and one control register (figure 2.7). The data registers are
32-bit width with the exception of registers A0 and A1. Registers A0 and A1 include 8 guard bits
(fields A0G and A1G), giving them a total width of 40 bits.
Three types of operations access the DSP data registers. First one is the DSP data. When a DSP
fixed-point data operation uses A0 or A1 for source register, it uses the guard bits (bits 39 to 32).
When it uses A0 or A1 for destination register, bits 39 to 32 in the guard bit are valid. When a
DSP fixed-point data operation uses the DSP registers other than A0 and A1 for source register, it
sign-extends the source value to bits 39 to 32. When it uses them for destination register, the bits
39 to 32 of the result is discard.
Second one is X and Y data transfer operation, “MOVX.W MOVY.W”. This operation accesses
the X and Y memories through 16-bit X and Y data buses (figure 2.8). Registers to be loaded or
stored by this operation are always upper 16 bits (bits 31 to 16). X0 and X1 can be destination of
the X memory load and Y0 and Y1 can be destination of Y memory load, but other register cannot
be destination register of this operation.
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When data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the
register (bits 15 to 0) are automatically cleared. A0 and A1 can be stored to the X or Y memory by
this operation, but other registers cannot be stored.
There are some rules to access SR by STC/LDC instruction.
1. When DSP is disabled, same as SH-3 behavior
2. When SDP supervisor mode, same as supervisor mode
3. In User DSP mode, SR can be read by STC instruction
4. In User DSP mode, LDC to SR is allowed but no DSP related bits are protected from write.
Table 2.2 shows detail behavior under each SH3-DSP mode.
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Table 2.2
Detail Behavior Under Each SH3-DSP Mode
User Mode
DSP
Supervisor
Mode
DSP User
Mode
MD = 1 &
DSP = 0
MD = 0 &
DSP = 0
MD = 1 &
DSP = 1
MD = 0 &
DSP = 1
MD
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
1
RB
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
1
BL
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
1
RC [11:0]
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: OK
DSP
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
0
DMX
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: OK
0
DMY
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: OK
0
Q
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
X
M
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
X
I [3:0]
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
1111
RF [1:0]
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: OK
S
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
X
T
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
X
Fields
Supervisor
Mode
Access to
DSP Related
Bits by
Dedicated
Instruction
SETRC
instruction
SETRC
instruction
Initial Value after
Reset
0b000000000000
X
(S) STC:
Store SR to Rn, SR → Rn
(L) LDC:
Load Rn to SR, Rn → SR
OK:
Allowed to STC/LSC operation
Illegal instruction: Treated as illegal instruction, exception should be occurred
NG:
Keep previous value, nothing changed
Third one is single-data transfer instruction, “MOVS.W” and “MOVS.L”. This instruction
accesses any memory location through LDB (figure 2.8). All DSP registers connect to the LDB
and be able to be source and destination register of the data transfer. It has word and longword
access modes. In the word mode, registers to be loaded or stored by this instruction are upper 16
bits (bits 31 to 16) for the DSP registers except A0G and A1G. When data is loaded into a register
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Section 2 CPU
other than A0G and A1G in the word mode, lower half of the register is cleared. When it is A0 or
A1, the data is sign-extended to bits 39 to 32 and lower half of it is cleared. When A0G or A1G is
a destination register in the word mode, data is loaded into 8-bit register, but A0 or A1 is not
cleared. In the longword mode, when a destination register is A0 or A1, it is sign-extended to bits
39 to 32.
Tables 2.3 and 2.4 show the data type of registers used in the DSP instructions. Some instructions
cannot use some registers shown in the tables because of instruction code limitation. For example,
PMULS can use A1 for source registers, but cannot use A0. These tables ignore details of the
register selectability.
Table 2.3
Destination Register of DSP Instructions
Guard Bits
Registers
A0, A1
Instructions
DSP
Data
transfer
39
Register Bits
32 31
16 15
Fixed-point, PSHA,
PMULS
Sign-extended 40-bit result
Integer, PDMSB
Sign-extended 24-bit result
Cleared
Logical, PSHL
Cleared
Cleared
MOVS.W
Sign-extended 16-bit data
MOVS.L
Sign-extended 32-bit data
16-bit result
Cleared
A0G, A1G
Data
transfer
MOVS.W
Data
No update
MOVS.L
Data
No update
X0, X1
Y0, Y1
M0, M1
DSP
Fixed-point, PSHA,
PMULS
32-bit result
Integer, logical,
PDMSB, PSHL
16-bit result
Cleared
MOVX/Y.W, MOVS.W
16-bit result
Cleared
MOVS.L
32-bit data
Data
transfer
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0
Section 2 CPU
Table 2.4
Source Register of DSP Operations
Guard Bits
Registers
A0, A1
Instructions
DSP
39
Register Bits
32 31
Fixed-point, PDMSB,
PSHA
16
0
40-bit data
Integer
24-bit data
Logical, PSHL, PMULS
16-bit data
Data
transfer
MOVX/Y.W, MOVS.W
16-bit data
MOVS.L
32-bit data
A0G, A1G
Data
transfer
MOVS.W
MOVS.L
Data
X0, X1
Y0, Y1
M0, M1
DSP
Fixed-point, PDMSB,
PSHA
Sign*
32-bit data
Integer
Sign*
16-bit data
Data
transfer
15
Data
Logical, PSHL, PMULS
16-bit data
MOVS.W
16-bit data
MOVS.L
32-bit data
Note: * Sign-extend the data and feed to the ALU
39
32 31
0
A0G
A1G
A0
A1
M0
M1
X0
X1
Y0
Y1
(a) DSP Data Registers
31
8 7 6 5 4 3 2 1 0
GT Z N V CS [2:0] DC
(b) DSP Status Register (DSR)
Reset status
DSR: All zeros
Others: Undefined
Figure 2.7 DSP Registers
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Section 2 CPU
Table 2.5
DSR Register Bits
Bit
Name (Abbreviation)
Function
31–8
Reserved bits
0: Always read out; always use 0 as a write value
7
Signed greater than bit
(GT)
Indicates that the operation result is positive
(excepting 0), or that operand 1 is greater than
operand 2
1: Operation result is positive, or operand 1 is greater
6
Zero bit (Z)
5
Negative bit (N)
Indicates that the operation result is zero (0), or that
operand 1 is equal to operand 2
1: Operation result is zero (0), or equivalence
Indicates that the operation result is negative, or that
operand 1 is smaller than operand 2
1: Operation result is negative, or operand 1 is
smaller
4
Overflow bit (V)
Indicates that the operation result has overflowed
1: Operation result has overflowed
3–1
Status selection bits (CS) Designate the mode for selecting the operation result
status set in the DC bit
Do not set either 110 or 111
000: Carry/borrow mode
001: Negative value mode
010: Zero mode
011: Overflow mode
100: Signed greater mode
101: Signed above mode
0
DSP status bit (DC)
Sets the status of the operation result in the mode
designated by the CS bits
0: Designated mode status not realized (unrealized)
1: Designated mode status realized
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Section 2 CPU
LDB
16 bit
XDB
16 bit
8 bit
MOVX.W MOVY.W
MOVS.W,
MOVS.L
31
39
32
A0G
A1G
DSR
7
0
YDB
32 bit
16
MOVS.W,
MOVS.L
0
A0
A1
M0
M1
X0
X1
Y0
Y1
Figure 2.8 Connections of DSP Registers and Buses
The DSP unit has DSP status register (DSR). The DSR has conditions of the DSP data operation
result (zero, negative, and so on) and a DC bit which is similar to the T bit in the CPU. The DC bit
indicates the one of the conditional flags. A conditional DSP data processing instruction controls
its execution based on the DC bit. This control affects only the operations in the DSP unit; it
controls the update of DSP registers only. It cannot control operations in CPU, such as address
register updating and load/store operations. The control bit CS[2:0] specifies the condition to be
reflect to the DC bit.
The unconditional DSP type data operations, except PMULS, MOVX, MOVY and MOVS, update
the conditional flags and DC bit, but no CPU instructions, including MAC instructions, update the
DC bit. The conditional DSP type instructions do not update the DSR either.
DSR is assigned as a system register and load/store instructions are prepared as follows:
STS DSR,Rn;
STS.L DSR,@-Rn;
LDS Rn,DSR;
LDS.L @Rn+,DSR;
When DSR is read by the STS instructions, the upper bits (bit 31 to bit 8) are all 0.
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2.2
Data Format
2.2.1
Data Format in Registers (Non-DSP Type)
Register operands are always longwords (32 bits) (figure 2.9). When the memory operand is only
a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
31
0
Longword
Figure 2.9 Longword Operand
2.2.2
DSP-Type Data Format
The SH7727 has several different data formats that depend on operations. This section explains
the data formats for DSP type instructions.
Figure 2.10 shows three DSP-type data formats with different binary point positions. A CPU-type
data format with the binary point to the right of bit 0 is also shown for reference.
The DSP-type fixed point data format has the binary point between bit 31 and bit 30. The DSPtype integer format has the binary point between bit 16 and bit 15. The DSP-type logical format
does not have a binary point. The valid data lengths of the data formats depend on the operations
and the DSP registers.
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Section 2 CPU
DSP type fixed point
39
With guard bits
31 30
0
−28 to +28 − 2−31
S
31 30
Without guard bits
0
−1 to +1 − 2−31
S
39
31 30
16 15
0
−1 to +1 − 2−15
S
Multiplier input
DSP type integer
39
With guard bits
32 31
16 15
0
−223 to +223 − 1
S
31
Without guard bits
S
Shift amount for
arithmetic shift (PSHA)
31
Shift amount for
logical shift (PSHL)
39
16 15
0
−215 to +215 − 1
22
16 15
0
−32 to +32
S
31
21 16 15
0
−16 to +16
S
31
16 15
0
DSP type logical
CPU type integer
31
Longword
S: Sign bit
0
−231 to +231 − 1
S
: Binary point
: Does not affect the operations
Figure 2.10 Data Format
Shift amount for arithmetic shift (PSHA) instruction has 7 bits filed that could represent –64 to
+63, however –32 to +32 is the valid number for the operation. Also the shift amount for logical
shift operation has 6-bits field, however –16 to +16 is the valid number for the instruction.
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2.2.3
Data Format in Memory
Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed
from any address, but an address error will occur if the word data starting from an address other
than 2n or longword data starting from an address other than 4n is accessed. In such cases, the data
accessed cannot be guaranteed (figure 2.11).
Address A + 1
Address A
23
31
Address A
Address A + 4
Address A + 8
Byte 0
Address A + 3
Address A + 10
7
15
Byte 1
Byte 2
Word 0
Address A + 9
Address A + 11
Address A + 2
0
Byte 3
23
31
Byte 3
Word 1
Address A + 8
7
15
Byte 2
Byte 1
Word 1
0
Byte 0
Word 0
Longword
Longword
Big-endian mode
Little-endian mode
Address A + 8
Address A + 4
Address A
Figure 2.11 Byte, Word, and Longword Alignment
As the data format, either big endian or little endian byte order can be selected, according to the
MD5 pin at reset. When MD5 is low at reset, the processor operates in big endian. When MD5 is
high at reset, the processor operates in little endian.
2.3
Features of CPU Core Instructions
The CPU core instructions are RISC-type instructions with the following features:
Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code
efficiency.
One Instruction per State: Pipelining is used, and basic instructions can be executed in one state.
At 160-MHz operation, one state is 6.25 ns.
Data Size: The basic data size for operations is longword. Byte, word, or longword can be
selected as the memory access size. Memory byte or word data is sign-extended and operated on
as longword data. Immediate data is sign-extended to longword size for arithmetic operations or
zero-extended to longword size for logical operations.
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Section 2 CPU
Table 2.6
Word Data Sign Extension
SH7727 CPU
Description
Example of Other CPU
MOV.W
@(disp,PC),R1
ADD.W
ADD
R1,R0
Sign-extended to 32 bits, R1
becomes H'00001234, and is
then operated on by the ADD
instruction.
........
#H'1234,R0
.DATA.W H'1234
Note: Immediate data is referenced by @(disp,PC).
Load/Store Architecture: Basic operations are executed between registers. In operations
involving memory, data is first loaded into a register (load/store architecture). However, bit
manipulation instructions such as AND are executed directly on memory.
Delayed Branching: Unconditional branch instructions, etc., are executed as delayed branches.
With a delayed branch instruction, the branch is made after execution of the instruction (called the
slot instruction) immediately following the delayed branch instruction. This minimizes disruption
of the pipeline when a branch is made.
With a delayed branch, the actual branch operation occurs after execution of the slot instruction.
However, instruction execution for register updating, etc., excluding the branch operation, is
performed in delayed branch instruction → delay slot instruction order. For example, even though
the contents of the register holding the branch destination address are changed in the delay slot,
the branch destination address remains as the register contents prior to the change.
Table 2.7
Delayed Branch Instructions
SH7727 CPU
Description
Example of Other CPU
BRA
TRGET
ADD.W R1,R0
ADD
R1,R0
ADD is executed before branch to
TRGET.
BRA
TRGET
Multiply/Multiply-and-Accumulate Operations: A 16 × 16 → 32 multiply operation is
executed in 1 to 3 states, and a 16 × 16 + 64 → 64 multiply-and-accumulate operation in 2 to 3
states. A 32 × 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-and-accumulate
operation are each executed in 2 to 5 states.
T Bit: The result of a comparison is indicated by the T bit in the status register (SR), and a
conditional branch is performed according to whether the result is True or False. Processing speed
has been improved by keeping the number of instructions that modify the T bit to a minimum.
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Section 2 CPU
Table 2.8
T Bit
SH7727 CPU
Description
Example of Other CPU
CMP/GE
R1,R0
If R0 ≥ R1, the T bit is set.
CMP.W R1,R0
BT
TRGET0
BGE
TRGET0
BF
TRGET1
A branch is made to TRGET0
if R0 ≥ R1, or to TRGET1 if R0 < R1.
BLT
TRGET1
ADD
#–1,R0
The T bit is not set by ADD.
SUB.W #1,R0
CMP/EQ
#0,R0
If R0 = 0, the T bit is set.
BEQ
BT
TRGET
A branch is made if R0 = 0.
TRGET
Immediate Data: Byte immediate data is placed inside the instruction code. Word and longword
immediate data is not placed inside the instruction code, but in a table in memory. The table in
memory is referenced with an immediate data transfer instruction (MOV) using PC-relative
addressing mode with displacement.
Table 2.9
Immediate Data Referencing
Type
SH7727 CPU
Example of Other CPU
8-bit immediate
MOV
#H'12,R0
MOV.B
#H'12,R0
16-bit immediate
MOV.W
@(disp,PC),R0
MOV.W
#H'1234,R0
MOV.L
#H'12345678,R0
........
.DATA.W H'1234
32-bit immediate
MOV.L
@(disp,PC),R0
........
.DATA.L H'12345678
Note: Immediate data is referenced by @(disp,PC).
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Absolute Addresses: When data is referenced by absolute address, the absolute address value is
placed in a table in memory beforehand. Using the method whereby immediate data is loaded
when an instruction is executed, this value is transferred to a register and the data is referenced
using register indirect addressing mode.
Table 2.10 Absolute Address Referencing
Type
SH7727 CPU
Example of Other CPU
Absolute address
MOV.L
@(disp,PC),R1
MOV.B @H'12345678,R0
MOV.B
@R1,R0
........
.DATA.L H'12345678
16-Bit/32-Bit Displacement: When data is referenced with a 16- or 32-bit displacement, the
displacement value is placed in a table in memory beforehand. Using the method whereby
immediate data is loaded when an instruction is executed, this value is transferred to a register and
the data is referenced using indexed register indirect addressing mode.
Table 2.11 Displacement Referencing
Type
SH7727 CPU
Example of Other CPU
16-bit displacement
MOV.W
@(disp,PC),R0
MOV.W
MOV.W
@(R0,R1),R2
@(H'1234,R1),R2
........
.DATA.W H'1234
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2.4
Instruction Formats
2.4.1
CPU Instruction Addressing Modes
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.12 Addressing Modes and Effective Addresses for CPU Instructions
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation
Formula
Register
direct
Rn
Effective address is register Rn.
—
Register
indirect
@Rn
Register
indirect with
postincrement
@Rn+
(Operand is register Rn contents.)
Effective address is register Rn contents.
Rn
Rn
Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn
Rn + 1/2/4
@–Rn
Rn
1/2/4
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After instruction
execution
Byte:
Rn + 1 → Rn
Longword:
Rn + 4 → Rn
Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
Rn − 1/2/4
Rn
Word:
Rn + 2 → Rn
+
1/2/4
Register
indirect with
predecrement
Rn
−
Rn − 1/2/4
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction
executed with Rn
after calculation)
Section 2 CPU
Addressing
Mode
Instruction
Format
Register
@(disp:4, Rn)
indirect with
displacement
Effective Address Calculation Method
Effective address is register Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
Rn
disp
(zero-extended)
+
Calculation
Formula
Byte:
Rn + disp
Word:
Rn + disp × 2
Longword:
Rn + disp × 4
Rn
+ disp × 1/2/4
×
1/2/4
Indexed
register
indirect
@(R0, Rn)
Effective address is sum of register Rn and R0
contents.
Rn + R0
Rn
+
Rn + R0
R0
GBR indirect @(disp:8,
with
GBR)
displacement
Effective address is register GBR contents with
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
GBR
disp
(zero-extended)
+
Byte:
GBR + disp
Word:
GBR + disp × 2
Longword:
GBR + disp × 4
GBR
+ disp × 1/2/4
×
1/2/4
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Section 2 CPU
Addressing
Mode
Instruction
Format
Indexed GBR @(R0, GBR)
indirect
Effective Address Calculation Method
Effective address is sum of register GBR and
R0 contents.
Calculation
Formula
GBR + R0
GBR
+
GBR + R0
R0
PC-relative
@(disp:8, PC) Effective address is PC with 8-bit displacement
with
disp added. After disp is zero-extended, it is
displacement
multiplied by 2 (word) or 4 (longword), according
to the operand size. With a longword operand,
the lower 2 bits of PC are masked.
PC
&
*
H'FFFFFFFC
+
disp
(zero-extended)
PC + disp × 2
or
PC&H'FFFFFFFC
+ disp × 4
x
2/4
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*: With longword operand
Word:
PC + disp × 2
Longword:
PC&H'FFFFFFFC
+ disp × 4
Section 2 CPU
Addressing
Mode
Instruction
Format
PC-relative
disp:8
Effective Address Calculation Method
Effective address is PC with 8-bit displacement
disp added after being sign-extended and
multiplied by 2.
Calculation
Formula
PC + disp × 2
PC
disp
(sign-extended)
+
PC + disp × 2
×
2
disp:12
Effective address is PC with 12-bit displacement PC + disp × 2
disp added after being sign-extended and
multiplied by 2.
PC
disp
(sign-extended)
+
PC + disp × 2
×
2
Rn
Effective address is sum of PC and Rn.
PC + Rn
PC
+
PC + Rn
Rn
Immediate
#imm:8
8-bit immediate data imm of TST, AND, OR,
or XOR instruction is zero-extended.
—
#imm:8
8-bit immediate data imm of MOV, ADD, or
CMP/EQ instruction is sign-extended.
—
#imm:8
8-bit immediate data imm of TRAPA instruction
is zero-extended and multiplied by 4.
—
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Section 2 CPU
2.4.2
DSP Data Addressing
Two different memory accesses are made with DSP instructions. The two kinds of instructions are
X and Y data transfer instructions (MOVX.W, MOVY.W) and single data transfer instructions
(MOVS.W, MOVSL). The data addressing is different for these two kinds of instruction. An
overview of the data transfer instructions is given in table 2.13.
Table 2.13 Overview of Data Transfer Instructions
X/Y Data Transfer Processing
(MOVX.W, MOVY.W)
Single Data Transfer Processing
(MOVS.W, MOVS.L)
Address register
Ax: R4, R5, Ay: R6, R7
As: R2, R3, R4, R5
Index register
Ix: R8, Iy: R9
Is: R8
Addressing
Nop/Inc (+2)/index addition:
post-increment
Nop/Inc (+2, +4)/index addition:
post-increment
—
Dec (–2, –4): pre-decrement
Possible
Not possible
Modulo addressing
Data bus
XDB, YDB
LDB
Data length
16 bits (word)
16/32 bits (word/longword)
Bus contention
No
Yes
Memory
X/Y data memory
Entire memory space
Source register
Dx, Dy: A0, A1
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
Destination register
Dx: X0/X1, Dy: Y0/Y1
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
X/Y Data Addressing: With DSP instructions, the X and Y data memory can be accessed
simultaneously using the MOVX.W and MOVY.W instructions. Two address pointers are
provided for DSP instructions to enable simultaneous access to X and Y data memory. Only
pointer addressing can be used with DSP instructions; immediate addressing is not available.
Address registers are divided into two, with register R4 or R5 functioning as the X memory
address register (Ax), and register R6 or R7 as the Y memory address register (Ay). The following
three kinds of addressing can be used with X and Y data transfer instructions.
1. Non-update address register addressing:
The Ax and Ay registers are address pointers. They are not updated.
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2. Addition index register addressing:
The Ax and Ay registers are address pointers. After a data transfer, the value of the Ix or Iy
register is added to each (post-increment).
3. Increment address register addressing:
The Ax and Ay registers are address pointers. After a data transfer, they are each incremented
by 2 (post- increment).
There is an index register for each address pointer. The R8 register is the index register (Ix) for the
X memory address register (Ax), and the R9 register is the index register (Iy) for the Y memory
address register (Ay).
The X and Y data transfer instructions perform word-length processing, and use 16-bit access to
the X/Y data memory. A value of 2 is therefore added to the address register in the increment
processing. To perform decrementing, –2 is set in the index register and addition index register
addressing is specified. In X/Y data addressing, only bits 1 to 15 of the address pointer are valid.
When using X/Y data addressing, 0 must always be written to bit 0 of the address pointer and
index register.
X/Y data transfer addressing is shown in figure 2.12. When accessing X and Y memory using the
X and Y buses, the upper word of Ax (R4 or R5) and Ay (R6 or R7) is ignored. The result of
@AY+ or @Ay + Iy is stored in the lower word of Ay, while the upper word retains its original
value.
R8[Ix]
R4[Ax]
R5[Ax]
+2 (INC)
+0 (no update)
ALU
Note: Three address processing methods:
R9[Iy]
R6[Ay]
R7[Ay]
+2 (INC)
+0 (no update)
AU
AU: Adder provided
for DSP addressing
1. Increment
2. Index register addition (Ix/Iy)
3. No increment
Post-updating is used in all cases.
The address pointer can be decremented by setting −2/−4 in the index register.
Figure 2.12 X and Y Data Transfer Addressing
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Section 2 CPU
Single Data Addressing: DSP instructions include two single data transfer instructions
(MOVS.W, MOVS.L) that load data into, or store data from, a DSP register. With these
instructions, one of registers R2 to R5 is used as the single data transfer address register (As).
The following four kinds of addressing can be used with single data transfer instructions.
1. Non-update address register addressing:
The As register is an address pointer. It is not updated.
2. Addition index register addressing:
The As register is an address pointer. After a data transfer, the value of the Is register is added
to the As register (post-increment).
3. Increment address register addressing:
The As register is an address pointer. After a data transfer, the As register is incremented by 2
or 4 (post-increment).
4. Decrement address register addressing:
The As register is an address pointer. Before a data transfer, –2 or –4 is added to the As
register (i.e. 2 or 4 is subtracted) (pre-decrement).
The R8 register is the index register (Is) for the address pointer (As). Single data transfer
addressing is shown in figure 2.13.
31
0
R2[As]
31
0
R3[As]
R4[As]
R8[Is]
R5[As]
−2/−4 (DEC)
+2/+4 (INC)
+0 (no update)
ALU
MAB
31
CAB
0
Note: Four address processing methods:
1.
2.
3.
4.
No update
Index register addition (Is)
Increment
Decrement
Post-increment
Pre-decrement
Figure 2.13 Single Data Transfer Addressing
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Section 2 CPU
Modulo Addressing: Like other DSPs, the SH7727 has a modulo addressing mode. Address
registers are updated in the same way in this mode. When the address pointer value reaches the
preset modulo end address, the address pointer value becomes the modulo start address.
Modulo addressing is only available for the X and Y data transfer instructions (MOVX.W,
MOVY.W). Modulo addressing mode is specified for the X address register by setting the DMX
bit in the SR register, and for the Y address register by setting the DMY bit. Modulo addressing is
valid for either the X or the Y address register, only; it cannot be set for both at the same time.
Therefore, DMX and DMY cannot both be set simultaneously (if they are, the DMY setting will
be valid).
The MOD register is provided to set the start and end addresses of the modulo address area. The
MOD register contains MS (Modulo Start) and ME (Modulo End). An example of the use of the
MOD register (MS and ME fields) is shown below.
MOV.L ModAddr,Rn;
Rn=ModEnd, ModStart
LDC Rn,MOD;
ME=ModEnd, MS=ModStart
ModAddr: .DATA.W
.DATA.W
mEnd; ModEnd
mStart;
ModStart
ModStart: .DATA
:
ModEnd:
.DATA
The start and end addresses are specified in MS and ME, then the DMX or DMY bit is set to 1.
The address register contents are compared with ME, and if they match, start address MS is stored
in the address register. The lower 16 bits of the address register are compared with ME.
The maximum modulo size is 64 kbytes. This is sufficient to access the X and Y data memory. A
block diagram of modulo addressing is shown in figure 2.14.
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Section 2 CPU
Instruction (MOVX/MOVY)
31
31
0
R8[Ix]
16 15
R4[Ax]
R5[Ax]
0
DMX
DMY
31
CONT
+2
+0
15
16 15
R6[Ay]
R7[Ay]
0
31
0
R9[Iy]
+2
+0
1
MS
ALU
AU
CMP
ME
ABx
15
1
15
ABy
1
XAB
15
1
YAB
Figure 2.14 Modulo Addressing
An example of modulo addressing is given below.
MS = H'7008; ME=H'700C; R4=H'A5007008;
DMX = 1; DMY = 0:
(Modulo addressing setting for address register Ax (R4, R5))
As a result of the above settings, the R4 register changes as follows.
R4: H'A5007008
Inc.
R4: H'A500700A
Inc.
R4: H'A500700C
Inc.
R4: H'A5007008
(Reaches modulo end address, so becomes modulo start address)
Place the data so that the upper 16 bits of the modulo start and end addresses are the same. This is
because the modulo start address overwrites only the lower 15 bits of the address register,
excluding bit 0.
Note: When addition indexing is used for DSP data addressing, the address pointer may exceed
the ME value without actually reaching it. In this case, the address pointer will not return
to the modulo start address. Not only with modulo addressing, but when X and Y data
addressing is used, bit 0 is ignored. 0 must always be written to bit 0 of the address
pointer, index register, MS, and ME.
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Section 2 CPU
DSP Addressing Operations: DSP addressing operations in the pipeline execution stage (EX),
including modulo addressing, are shown below.
if ( Operation is MOVX.W MOVY.W ) {
ABx=Ax; ABy=Ay;
/* memory access cycle uses ABx and ABy. The addresses to be used
have not been updated */
/* Ax is one of R4,R5 */
if ( DMX==0 || DMX==1 && DMY == 1 )} Ax=Ax+(+2 or R8[Ix] or +0);
/* Inc,Index,Not-Update */
else if (! not-update) Ax=modulo( Ax, (+2 or R8[Ix]) );
/* Ay is one of R6,R7 */
if ( DMY==0 ) Ay=Ay+(+2 or R9[Iy] or +0); /* Inc,Index,Not-Update */
else if (! not-update) Ay=modulo( Ay, (+2 or R9[Iy]) );
}
else if ( Operation is MOVS.W or MOVS.L ) {
if ( Addressing is Nop, Inc, Add-index-reg ) {
MAB=As;
/* memory access cycle uses MAB. The address to be used has not
been updated */
/* As is one of R2 to R5 */
As=As+(+2 or +4 or R8[Is] or +0); /* Inc,Index,Not-Update */
else { /* Decrement, Pre-update */
/* As is one of R2 to R5 */
As=As+(-2 or -4);
MAB=As;
/* memory access cycle uses MAB. The address to be used has been
updated */
}
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Section 2 CPU
/* The value to be added to the address register depends on addressing
operations.
For example, (+2 or R8[Ix] or +0) means that
+2 : if operation is increment
R8[Ix] : if operation is add-index-reg
+0 : if operation is not-update
*/
function modulo ( AddrReg, Index ) {
if ( AdrReg[15:0]==ME ) AdrReg[15:0]==MS;
else AdrReg=AdrReg+Index;
return AddrReg;
}
2.4.3
CPU Instruction Formats
Table 2.14 shows the instruction formats, and the meaning of the source and destination operands,
for instructions executed by the CPU core. The meaning of the operands depends on the
instruction code. The following symbols are used in the table.
xxxx:
mmmm:
nnnn:
iiii:
dddd:
Instruction code
Source register
Destination register
Immediate data
Displacement
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Section 2 CPU
Table 2.14 CPU Instruction Formats
Instruction Format
Source
Operand
Destination
Operand
Sample Instruction
0 type
—
—
NOP
—
nnnn: register
direct
MOVT
Rn
STS
MACH,Rn
15
0
xxxx
xxxx
xxxx
xxxx
n type
15
0
xxxx
nnnn
xxxx
Control register or nnnn: register
system register
direct
xxxx
m type
15
0
xxxx mmmm xxxx
xxxx
Control register or nnnn: preSTC.L
system register
decrement register
indirect
SR,@-Rn
mmmm: register
direct
Rm,SR
Control register or LDC
system register
mmmm: postControl register or LDC.L
increment register system register
indirect
@Rm+,SR
mmmm: register
indirect
—
JMP
@Rm
PC-relative using
Rm
—
BRAF
Rm
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Section 2 CPU
Instruction Format
nm type
15
0
xxxx
nnnn mmmm xxxx
Source
Operand
Destination
Operand
mmmm: register
direct
nnnn: register
direct
ADD
mmmm: register
indirect
nnnn: register
indirect
MOV.L Rm,@Rn
mmmm: postMACH, MACL
increment register
indirect (multiplyand-accumulate
operation)
Sample Instruction
Rm,Rn
MAC.W @Rm+,@Rn+
nnnn: * postincrement register
indirect (multiplyand-accumulate
operation)
md type
15
0
xxxx
xxxx mmmm dddd
nd4 type
15
xxxx
xxxx
nnnn
nnnn: register
direct
mmmm: register
direct
nnnn: preMOV.L Rm,@-Rn
decrement register
indirect
mmmm: register
direct
nnnn: indexed
register indirect
MOV.L @Rm+,Rn
MOV.L Rm,@(R0,Rn)
mmmmdddd:
R0 (register direct) MOV.B @(disp,Rm),R0
register indirect
with displacement
0
R0 (register
direct)
nnnndddd:
MOV.B R0,@(disp,Rn)
register indirect
with displacement
0
mmmm: register
direct
nnnndddd:
MOV.L Rm,@(disp,Rn)
register indirect
with displacement
dddd
nmd type
15
xxxx
mmmm: postincrement
register indirect
nnnn mmmm dddd
mmmmdddd:
nnnn: register
register indirect
direct
with displacement
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REJ09B0254-0500
MOV.L @(disp,Rm),Rn
Section 2 CPU
Source
Operand
Instruction Format
d type
15
0
xxxx
xxxx
dddd
dddd
d12 type
15
0
xxxx
dddd
dddd
15
0
nnnn
dddd
dddd
i type
15
0
xxxx
xxxx
iiii
iiii
ni type
15
0
xxxx
nnnn
iiii
Sample Instruction
dddddddd:
R0 (register direct) MOV.L @@(disp,GBR),R0
GBR indirect with
displacement
R0 (register
direct)
dddddddd: GBR
indirect with
displacement
MOV.L @R0,@(disp,GBR)
dddddddd:
PC-relative with
displacement
R0 (register direct) MOVA @(disp,PC),R0
dddddddd:
PC-relative
—
BF
label
dddddddddddd:
PC-relative
—
BRA
label
(label=disp+PC)
dddddddd:
PC-relative with
displacement
nnnn: register
direct
MOV.L @(disp,PC),Rn
iiiiiiii:
immediate
Indexed GBR
indirect
AND.B #imm,@(R0,GBR)
iiiiiiii:
immediate
R0 (register direct) AND
iiiiiiii:
immediate
—
TRAPA #imm
iiiiiiii:
immediate
nnnn: register
direct
ADD
dddd
nd8 type
xxxx
Destination
Operand
#imm,R0
#imm,Rn
iiii
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
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Section 2 CPU
2.4.4
DSP Instruction Formats
The SH7727 includes new instructions for digital signal processing. The new instructions are of
the following two kinds.
1. Memory and DSP register double and single data transfer instructions (16-bit length)
2. Parallel processing instructions processed by the DSP unit (32-bit length)
The instruction formats are shown in figure 2.15.
0
15
CPU core instructions
0000
..
.
1110
111100
15
Single data transfer
instructions
A field
0
10 9
111101
31
Parallel processing
instructions
0
10 9
15
Double data transfer
instructions
A field
26 25
111110
A field
Figure 2.15 DSP Instruction Formats
Rev. 5.00 Dec 12, 2005 page 58 of 1034
REJ09B0254-0500
0
16 15
B field
Section 2 CPU
Double and Single Data Transfer Instructions: The format of double data transfer instructions
is shown in table 2.15, and that of single data transfer instructions in table 2.16.
Table 2.15 Double Data Transfer Instruction Formats
Type
Mnemonic
X memory NOPX
15 14 13 12 11 10 9
1
1
1
1
0
0
8
7
6
5
4
3
2
0
0
0
0
0
Ax
Dx
0
0
1
data
MOVX.W @Ax,Dx
transfer
MOVX.W @Ax+,Dx
1
0
MOVX.W @Ax+Ix,Dx
1
1
0
1
MOVX.W Da,@Ax+
1
0
MOVX.W Da,@Ax+Ix
1
1
MOVX.W Da,@Ax
Y memory NOPY
0
0
0
0
0
Dy
0
0
1
MOVY.W @Ay+,Dy
1
0
MOVY.W @Ay+Iy,Dy
1
1
MOVY.W @Ay,Dy
transfer
MOVY.W Da,@Ay
1
1
1
1
0
0
1
0
Ay
data
Note: Ax:
Ay:
Dx:
Dy:
Da:
Da
1
0
1
MOVY.W Da,@Ay+
Da
1
1
0
MOVY.W Da,@Ay+Iy
1
1
0 = R4, 1 = R5
0 = R6, 1 = R7
0 = X0, 1 = X1
0 = Y0, 1 = Y1
0 = A0, 1 = A1
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Section 2 CPU
Table 2.16 Single Data Transfer Instruction Formats
Type
Mnemonic
15 14 13 12 11 10 9
1
1
1
0
1
As
7
6
5
4
3
2
1
0
Ds 0:(*)
0
0
0
0
0
1
0
1
1
0
1
1
Single
MOVS.W @-As,Ds
data
MOVS.W @As,Ds
0:R4
1:(*)
transfer
MOVS.W @As+,Ds
1:R5
2:(*)
1
0
MOVS.W @As+Is,Ds
2:R2
3:(*)
1
1
MOVS.W Ds,@-As
3:R3
4:(*)
0
0
5:A1
0
1
MOVS.W Ds,@As
1
8
MOVS.W Ds,@As+
6:(*)
1
0
MOVS.W Ds,@As+Is
7:A0
1
1
MOVS.L @-As,Ds
8:X0
0
0
MOVS.L @As,Ds
9:X1
0
1
MOVS.L @As+,Ds
A:Y0
1
0
MOVS.L @As+Is,Ds
B:Y1
1
1
MOVS.L Ds,@-As
C:M0
0
0
MOVS.L Ds,@As
D:A1G
0
1
MOVS.L Ds,@As+
E:M1
1
0
MOVS.L Ds,@As+Is
F:A0G
1
1
Note: * Codes reserved for system use.
Parallel Processing Instructions: Parallel processing instructions are provided for efficient
execution of digital signal processing using the DSP unit. They are 32 bits long and allow four
simultaneous processes, an ALU operation, multiplication, and two data transfers.
Parallel processing instructions are divided into an A field and a B field. The A field defines data
transfer instructions and the B field an ALU operation instruction and multiply instruction. These
instructions can be defined independently, and the processing is executed in parallel,
independently and simultaneously. A-field parallel data transfer instructions are shown in table
2.17, and B-field ALU operation instructions and multiply instructions in table 2.18.
Rev. 5.00 Dec 12, 2005 page 60 of 1034
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Type
Note: Ax:
Ay:
Dx:
Dy:
Da:
Y memory
data
transfer
X memory
data
transfer
Mnemonic
0 = R4, 1 = R5
0 = R6, 1 = R7
0 = X0, 1 = X1
0 = Y0, 1 = Y1
0 = A0, 1 = A1
NOPX
MOVX.W @Ax, Dx
MOVX.W @Ax+, Dx
MOVX.W @Ax+Ix, Dx
MOVX.W Da, @Ax
MOVX.W Da, @Ax+
MOVX.W Da, @Ax+Ix
NOPY
MOVY.W @Ay, Dy
MOVY.W @Ay+, Dy
MOVY.W @Ay+Iy, Dy
MOVY.W Da, @Ay
MOVY.W Da, @Ay+
MOVY.W Da, @Ay+Iy
1 1 1 1 1 0
1 1 1 1 1 0 0
Ax
0
Ay
0
0
1
Da
1
Da
0
Dy
0
0
0
Dx
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
B field
B field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Section 2 CPU
Table 2.17 A-Field Parallel Data Transfer Instructions
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Type
Mnemonic
PSHL #imm, Dz
PSHA #imm, Dz
Reserved
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PSUBC Sx, Sy, Dz
PADDC Sx, Sy, Dz
PCMP Sx, Sy
Reserved
Reserved
Reserved
PABS Sx, Dz
PRND Sx, Dz
PABS Sy, Dz
PRND Sy, Dz
Reserved
1 1 1 1 1 0
A field
0
0
0
0
1
1 0 0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1 1
1 0
0 1
0 0 0 0
0:Y0
1:Y1
2:X0
3:A1
0:X0
1:X1
2:A0
3:A1
0:Y0
1:Y1
2:M0
3:M1
0 0 0 −16 < = imm < = +16
0 1 0 −32 < = imm < = +32
1
0
1
0 0
Se
Sf
Sx
Sy
0 1 0 1 0:X0
1:X1
0 1 1 0 2:Y0
3:A1
0 1 1 1
0
0
0
0
0
Du
0:X0
1:Y0
2:A0
3:A1
0:(*1)
1:(*1)
2:(*1)
3:(*1)
4:(*1)
5:A1
6:(*1)
7:A0
8:X0
9:X1
A:Y0
B:Y1
C:M0
D:(*1)
E:M1
F:(*1)
Dz
0:M0
1:M1
2:A0
3:A1
Dg
Dz
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Note: 1. Codes reserved for system use.
3-operand
instructions
PSUB Sx, Sy, Du
PMULS Se, Sf, Dg
PADD Sx, Sy, Du
PMULS Se, Sf, Dg
Reserved
6-operand PMULS Se, Sf, Dg
parallel
instructions Reserved
imm. shift
Section 2 CPU
Table 2.18 B-Field ALU Operation Instructions and Multiply Instructions
Type
Mnemonic
1 1 1 1 1 1
1 1 1 1 1 0
A field
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1 1 0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sx
0 *
1 1
1 0
0 0
0 0
if cc
11:
1 1 DCF
10:
1 0 DCT
01:
0:X0
1:X1
Uncon0 1 ditional 2:A0
3:A1
0 0 if cc
0:Y0
1:Y1
2:M0
3:M1
Sy
0:(*1)
1:(*1)
2:(*1)
3:(*1)
4:(*1)
5:A1
6:(*1)
7:A0
8:X0
9:X1
A:Y0
B:Y1
C:M0
D:(*1)
E:M1
F:(*1)
Dz
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Notes: 1. Codes reserved for system use.
2. [if cc]: DCT (DC bit True), DCF (DC bit False) or none (unconditional instruction)
Reserved
Conditional [if cc] PSHL Sx, Sy, Dz
3-operand [if cc] PSHA Sx, Sy, Dz
instructions [if cc] PSUB Sx, Sy, Dz
[if cc] PADD Sx, Sy, Dz
Reserved
[if cc] PAND Sx, Sy, Dz
[if cc] PXOR Sx, Sy, Dz
[if cc] POR Sx, Sy, Dz
[if cc] PDEC Sx, Dz
[if cc] PINC Sx, Dz
[if cc] PDEC Sy, Dz
[if cc] PINC Sy, Dz
[if cc] PCLR Dz
[if cc] PDMSB Sx, Dz
Reserved
[if cc] PDMSB Sy, Dz
[if cc] PNEG Sx, Dz
[if cc] PCOPY Sx, Dz
[if cc] PNEG Sy, Dz
[if cc] PCOPY Sy, Dz
Reserved
[if cc] PSTS MACH, Dz
[if cc] PSTS MACL, Dz
[if cc] PLDS Dz, MACH
[if cc] PLDS Dz, MACL
(*2) Reserved
Section 2 CPU
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Section 2 CPU
2.5
Instruction Set
2.5.1
CPU Instruction Set
The SH-1/SH-2/SH-3 compatible instruction set consists of 68 basic instruction types divided into
six functional groups, as shown in table 2.19. Tables 2.20 to 2.25 show the instruction notation,
machine code, execution time, and function.
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Section 2 CPU
Table 2.19 CPU Instruction Types
Type
Kinds of
Instruction Op Code
Data transfer 5
instructions
MOV
Function
Number of
Instructions
Data transfer
39
Immediate data transfer
Peripheral module data transfer
Structure data transfer
Arithmetic
operation
instructions
21
MOVA
Effective address transfer
MOVT
T bit transfer
SWAP
Upper/lower swap
XTRCT
Extraction of middle of linked registers
ADD
Binary addition
ADDC
Binary addition with carry
ADDV
Binary addition with overflow check
CMP/cond
Comparison
DIV1
Division
DIV0S
Signed division initialization
DIV0U
Unsigned division initialization
DMULS
Signed double-precision multiplication
DMULU
Unsigned double-precision multiplication
DT
Decrement and test
EXTS
Sign extension
EXTU
Zero extension
MAC
Multiply-and-accumulate, doubleprecision multiply-and-accumulate
MUL
Double-precision multiplication
(32 × 32 bits)
MULS
Signed multiplication (16 × 16 bits)
MULU
Unsigned multiplication (16 × 16 bits)
NEG
Sign inversion
NEGC
Sign inversion with borrow
SUB
Binary subtraction
SUBC
Binary subtraction with carry
SUBV
Binary subtraction with underflow
33
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Section 2 CPU
Type
Logic
operation
instructions
Shift
instructions
Branch
instructions
Kinds of
Instruction Op Code
Function
Number of
Instructions
6
Logical AND
14
12
9
AND
NOT
Bit inversion
OR
Logical OR
TAS
Memory test and bit setting
TST
Logical AND and T bit setting
XOR
Exclusive logical OR
ROTL
1-bit left shift
ROTR
1-bit right shift
ROTCL
1-bit left shift with T bit
ROTCR
1-bit right shift with T bit
SHAL
Arithmetic 1-bit left shift
SHAR
Arithmetic 1-bit right shift
SHLL
Logical 1-bit left shift
SHLLn
Logical n-bit left shift
SHLR
Logical 1-bit right shift
SHLRn
Logical n-bit right shift
SHAD
Arithmetic dynamic shift
SHLD
Logical dynamic shift
BF
Conditional branch, delayed conditional
branch (T = 0)
BT
Conditional branch, delayed conditional
branch (T = 1)
BRA
Unconditional branch
BRAF
Unconditional branch
BSR
Branch to subroutine procedure
BSRF
Branch to subroutine procedure
JMP
Unconditional branch
JSR
Branch to subroutine procedure
RTS
Return from subroutine procedure
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16
11
Section 2 CPU
Type
System
control
instructions
Total:
Kinds of
Instruction Op Code
Function
Number of
Instructions
15
T bit clear
75
68
CLRT
CLRMAC
MAC register clear
CLRS
S bit clear
LDC
Load into control register
LDS
Load into system register
LDTLB
PTEH/PTEL load into TLB
NOP
No operation
PREF
Data prefetch to cache
RTE
Return from exception handling
SETS
S bit setting
SETT
T bit setting
SLEEP
Transition to power-down mode
STC
Store from control register
STS
Store from system register
TRAPA
Trap exception handling
189
Rev. 5.00 Dec 12, 2005 page 67 of 1034
REJ09B0254-0500
Section 2 CPU
The instruction code, operation, and number of execution states of the CPU instructions are shown
in the following tables, classified by instruction type, using the format shown below.
Instruction
Instruction Code
Operation
Privilege
Indicated by mnemonic.
Indicated in MSB ↔
LSB order.
Indicates summary of
operation.
Indicates a
privileged
instruction.
Explanation of Symbols
Explanation of Symbols
Explanation of Symbols
OP.Sz SRC, DEST
OP:
Operation code
Sz:
Size
SRC: Source
DEST: Destination
mmmm: Source register
→, ←:
Transfer direction
nnnn: Destination register
0000: R0
0001: R1
.........
(xx):
Memory operand
Rm:
Source register
Rn:
Destination register
imm: Immediate data
1111: R15
iiii:
Immediate data
dddd:
Displacement *2
disp: Displacement
Execution
T Bit
States
Value
when no
wait
states are
inserted.*1
Value of T
bit after
instruction
is executed.
Explanation
of Symbols
—: No
change
M/Q/T: Flag bits in the SR
&:
Logical AND of each bit
|:
Logical OR of each bit
^:
Exclusive logical OR of
each bit
~:
Logical NOT of each bit
<<n: n-bit left shift
>>n: n-bit right shift
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
instruction execution states will be increased in cases such as the following:
(1) When there is contention between an instruction fetch and a data access
(2) When the destination register of a load instruction (memory → register) is also used
by the following instruction
2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.
Rev. 5.00 Dec 12, 2005 page 68 of 1034
REJ09B0254-0500
Section 2 CPU
Data Transfer Instructions
Table 2.20 Data Transfer Instructions
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
MOV
#imm,Rn
imm → Sign extension
→ Rn
1110nnnniiiiiiii
—
1
—
MOV.W
@(disp,PC),Rn
(disp × 2 + PC) → Sign
extension → Rn
1001nnnndddddddd
—
1
—
MOV.L
@(disp,PC),Rn
(disp × 4 + PC) → Rn
1101nnnndddddddd
—
1
—
MOV
Rm,Rn
Rm → Rn
0110nnnnmmmm0011
—
1
—
MOV.B
Rm,@Rn
Rm → (Rn)
0010nnnnmmmm0000
—
1
—
MOV.W
Rm,@Rn
Rm → (Rn)
0010nnnnmmmm0001
—
1
—
MOV.L
Rm,@Rn
Rm → (Rn)
0010nnnnmmmm0010
—
1
—
MOV.B
@Rm,Rn
(Rm) → Sign extension
→ Rn
0110nnnnmmmm0000
—
1
—
MOV.W
@Rm,Rn
(Rm) → Sign extension
→ Rn
0110nnnnmmmm0001
—
1
—
MOV.L
@Rm,Rn
(Rm) → Rn
0110nnnnmmmm0010
—
1
—
MOV.B
Rm,@–Rn
Rn–1 → Rn, Rm → (Rn)
0010nnnnmmmm0100
—
1
—
MOV.W
Rm,@–Rn
Rn–2 → Rn, Rm → (Rn)
0010nnnnmmmm0101
—
1
—
MOV.L
Rm,@–Rn
Rn–4 → Rn, Rm → (Rn)
0010nnnnmmmm0110
—
1
—
MOV.B
@Rm+,Rn
(Rm) → Sign extension
→ Rn, Rm + 1 → Rm
0110nnnnmmmm0100
—
1
—
MOV.W
@Rm+,Rn
(Rm) → Sign extension
→ Rn, Rm + 2 → Rm
0110nnnnmmmm0101
—
1
—
MOV.L
@Rm+,Rn
(Rm) → Rn,Rm + 4 → Rm 0110nnnnmmmm0110
—
1
—
MOV.B
R0,@(disp,Rn)
R0 → (disp + Rn)
10000000nnnndddd
—
1
—
MOV.W
R0,@(disp,Rn)
R0 → (disp × 2 + Rn)
10000001nnnndddd
—
1
—
MOV.L
Rm,@(disp,Rn)
Rm → (disp × 4 + Rn)
0001nnnnmmmmdddd
—
1
—
MOV.B
@(disp,Rm),R0
(disp + Rm) → Sign
extension → R0
10000100mmmmdddd
—
1
—
MOV.W
@(disp,Rm),R0
(disp × 2 + Rm) → Sign
extension → R0
10000101mmmmdddd
—
1
—
MOV.L
@(disp,Rm),Rn
(disp × 4 + Rm) → Rn
0101nnnnmmmmdddd
—
1
—
MOV.B
Rm,@(R0,Rn)
Rm → (R0 + Rn)
0000nnnnmmmm0100
—
1
—
Rev. 5.00 Dec 12, 2005 page 69 of 1034
REJ09B0254-0500
Section 2 CPU
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
MOV.W
Rm,@(R0,Rn)
Rm → (R0 + Rn)
0000nnnnmmmm0101
—
MOV.L
Rm,@(R0,Rn)
Rm → (R0 + Rn)
0000nnnnmmmm0110
—
1
—
MOV.B
@(R0,Rm),Rn
(R0 + Rm) → Sign
extension → Rn
0000nnnnmmmm1100
—
1
—
MOV.W
@(R0,Rm),Rn
(R0 + Rm) → Sign
extension → Rn
0000nnnnmmmm1101
—
1
—
MOV.L
@(R0,Rm),Rn
(R0 + Rm) → Rn
0000nnnnmmmm1110
—
1
—
MOV.B
R0,@(disp,GBR) R0 → (disp + GBR)
11000000dddddddd
—
1
—
MOV.W
R0,@(disp,GBR) R0 → (disp × 2 + GBR)
11000001dddddddd
—
1
—
MOV.L
R0,@(disp,GBR) R0 → (disp × 4 + GBR)
11000010dddddddd
—
1
—
MOV.B
@(disp,GBR),R0 (disp + GBR) → Sign
extension → R0
11000100dddddddd
—
1
—
MOV.W
@(disp,GBR),R0 (disp × 2 + GBR) →
Sign extension → R0
11000101dddddddd
—
1
—
MOV.L
@(disp,GBR),R0 (disp × 4 + GBR) → R0
11000110dddddddd
—
1
—
MOVA
@(disp,PC),R0
disp × 4 + PC → R0
11000111dddddddd
—
1
—
MOVT
Rn
T → Rn
0000nnnn00101001
—
1
—
SWAP.B Rm,Rn
Rm → Swap the bottom
two bytes → REG
0110nnnnmmmm1000
—
1
—
SWAP.W Rm,Rn
Rm → Swap two
consecutive words → Rn
0110nnnnmmmm1001
—
1
—
XTRCT
Rm: Middle 32 bits of
Rn → Rn
0010nnnnmmmm1101
—
1
—
Rm,Rn
Rev. 5.00 Dec 12, 2005 page 70 of 1034
REJ09B0254-0500
1
—
Section 2 CPU
Arithmetic Operation Instructions
Table 2.21 Arithmetic Operation Instructions
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
ADD
Rm,Rn
Rn + Rm → Rn
0011nnnnmmmm1100
—
ADD
#imm,Rn
Rn + imm → Rn
0111nnnniiiiiiii
—
1
—
ADDC
Rm,Rn
Rn + Rm + T → Rn,
Carry → T
0011nnnnmmmm1110
—
1
Carry
ADDV
Rm,Rn
Rn + Rm → Rn,
Overflow → T
0011nnnnmmmm1111
—
1
Overflow
CMP/EQ
#imm,R0
If R0 = imm, 1 → T
10001000iiiiiiii
—
1
Comparison
result
CMP/EQ
Rm,Rn
If Rn = Rm, 1 → T
0011nnnnmmmm0000
—
1
Comparison
result
CMP/HS
Rm,Rn
If Rn ≥ Rm with
unsigned data, 1 → T
0011nnnnmmmm0010
—
1
Comparison
result
CMP/GE
Rm,Rn
If Rn ≥ Rm with signed
data, 1 → T
0011nnnnmmmm0011
—
1
Comparison
result
CMP/HI
Rm,Rn
If Rn > Rm with
unsigned data, 1 → T
0011nnnnmmmm0110
—
1
Comparison
result
CMP/GT
Rm,Rn
If Rn > Rm with signed
data, 1 → T
0011nnnnmmmm0111
—
1
Comparison
result
CMP/PZ
Rn
If Rn ≥ 0, 1 → T
0100nnnn00010001
—
1
Comparison
result
CMP/PL
Rn
If Rn > 0, 1 → T
0100nnnn00010101
—
1
Comparison
result
CMP/STR Rm,Rn
If Rn and Rm have an
equivalent byte, 1 → T
0010nnnnmmmm1100
—
1
Comparison
result
DIV1
Rm,Rn
Single-step division
(Rn/Rm)
0011nnnnmmmm0100
—
1
Calculation
result
DIV0S
Rm,Rn
MSB of Rn → Q, MSB
of Rm → M, M ^ Q → T
0010nnnnmmmm0111
—
1
Calculation
result
0
1
—
DIV0U
0 → M/Q/T
0000000000011001
—
1
DMULS.L Rm,Rn
Signed operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
0011nnnnmmmm1101
—
2
—
(to 5)*1
Rev. 5.00 Dec 12, 2005 page 71 of 1034
REJ09B0254-0500
Section 2 CPU
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
DMULU.L Rm,Rn
Unsigned operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
0011nnnnmmmm0101
—
2
—
(to 5)*1
DT
Rn – 1 → Rn, if Rn =
0, 1 → T, else 0 → T
0100nnnn00010000
—
1
Comparison
result
EXTS.B Rm,Rn
A byte in Rm is signextended → Rn
0110nnnnmmmm1110
—
1
—
EXTS.W Rm,Rn
A word in Rm is signextended → Rn
0110nnnnmmmm1111
—
1
—
EXTU.B Rm,Rn
A byte in Rm is zeroextended → Rn
0110nnnnmmmm1100
—
1
—
EXTU.W Rm,Rn
A word in Rm is zeroextended → Rn
0110nnnnmmmm1101
—
1
—
MAC.L
@Rm+,@Rn+
Signed operation of (Rn) 0000nnnnmmmm1111
× (Rm) + MAC → MAC,
Rn + 4 → Rn,
Rm + 4 → Rm,
32 × 32 + 64 → 64 bits
—
2
—
(to 5)*1
MAC.W
@Rm+,@Rn+
Signed operation of (Rn) 0100nnnnmmmm1111
× (Rm) + MAC → MAC,
Rn + 2 → Rn,
Rm + 2 → Rm,
16 × 16 + 64 → 64 bits
—
2
—
(to 5)*1
MUL.L
Rm,Rn
Rn × Rm → MACL,
32 × 32 → 32 bits
0000nnnnmmmm0111
—
2
—
(to 5)*1
MULS.W Rm,Rn
Signed operation of Rn
× Rm → MACL,
16 × 16 → 32 bits
0010nnnnmmmm1111
—
1
—
(to 3)*2
MULU.W Rm,Rn
Unsigned operation of
Rn × Rm → MACL,
16 × 16 → 32 bits
0010nnnnmmmm1110
—
1
—
(to 3)*2
NEG
Rm,Rn
0–Rm → Rn
0110nnnnmmmm1011
—
1
—
NEGC
Rm,Rn
0–Rm–T → Rn,
Borrow → T
0110nnnnmmmm1010
—
1
Borrow
SUB
Rm,Rn
Rn–Rm → Rn
0011nnnnmmmm1000
—
1
—
SUBC
Rm,Rn
Rn–Rm–T → Rn,
Borrow → T
0011nnnnmmmm1010
—
1
Borrow
SUBV
Rm,Rn
Rn–Rm → Rn,
Underflow → T
0011nnnnmmmm1011
—
1
Underflow
Rn
Rev. 5.00 Dec 12, 2005 page 72 of 1034
REJ09B0254-0500
Section 2 CPU
Notes: 1. The normal minimum number of execution cycles is two, but five cycles are required
when the operation result is read from the MAC register immediately after the
instruction.
2. The normal minimum number of execution cycles is one, but three cycles are required
when the operation result is read from the MAC register immediately after the MUL
instruction.
Logic Operation Instructions
Table 2.22 Logic Operation Instructions
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
AND
Rm,Rn
Rn & Rm → Rn
0010nnnnmmmm1001
—
1
—
AND
#imm,R0
R0 & imm → R0
11001001iiiiiiii
—
1
—
AND.B #imm,@(R0,GBR)
(R0 + GBR) & imm →
(R0 + GBR)
11001101iiiiiiii
—
3
—
NOT
Rm,Rn
~Rm → Rn
0110nnnnmmmm0111
—
1
—
OR
Rm,Rn
Rn | Rm → Rn
0010nnnnmmmm1011
—
1
—
OR
#imm,R0
R0 | imm → R0
11001011iiiiiiii
—
1
—
OR.B
#imm,@(R0,GBR)
(R0 + GBR) | imm →
(R0 + GBR)
11001111iiiiiiii
—
3
—
TAS.B @Rn*
If (Rn) is 0, 1 → T;
1 → MSB of (Rn)
0100nnnn00011011
—
4
Test
result
TST
Rm,Rn
Rn & Rm; if the result
is 0, 1 → T
0010nnnnmmmm1000
—
1
Test
result
TST
#imm,R0
R0 & imm; if the result
is 0, 1 → T
11001000iiiiiiii
—
1
Test
result
TST.B #imm,@(R0,GBR)
(R0 + GBR) & imm;
if the result is 0, 1 → T
11001100iiiiiiii
—
3
Test
result
XOR
Rm,Rn
Rn ^ Rm → Rn
0010nnnnmmmm1010
—
1
—
XOR
#imm,R0
R0 ^ imm → R0
11001010iiiiiiii
—
1
—
(R0 + GBR) ^ imm →
(R0 + GBR)
11001110iiiiiiii
—
3
—
XOR.B #imm,@(R0,GBR)
Note:
*
An on-chip DMAC bus cycle is not inserted between a TAS instruction operand read
cycle and write cycle. Also, bus release is not performed by BREQ.
Rev. 5.00 Dec 12, 2005 page 73 of 1034
REJ09B0254-0500
Section 2 CPU
Shift Instructions
Table 2.23 Shift Instructions
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
ROTL
Rn
T ← Rn ← MSB
0100nnnn00000100
—
ROTR
Rn
LSB → Rn → T
0100nnnn00000101
—
1
LSB
ROTCL
Rn
T ← Rn ← T
0100nnnn00100100
—
1
MSB
ROTCR
Rn
T → Rn → T
0100nnnn00100101
—
1
LSB
SHAD
Rm,Rn
Rn ≥ 0: Rn << Rm → Rn
Rn < 0: Rn >> Rm →
[MSB → Rn]
0100nnnnmmmm1100
—
1
—
SHAL
Rn
T ← Rn ← 0
0100nnnn00100000
—
1
MSB
SHAR
Rn
MSB → Rn → T
0100nnnn00100001
—
1
LSB
SHLD
Rm,Rn
Rn ≥ 0: Rn << Rm → Rn
Rn < 0: Rn >> Rm →
[0 → Rn]
0100nnnnmmmm1101
—
1
—
SHLL
Rn
T ← Rn ← 0
0100nnnn00000000
—
1
MSB
SHLR
Rn
0 → Rn → T
0100nnnn00000001
—
1
LSB
SHLL2
Rn
Rn << 2 → Rn
0100nnnn00001000
—
1
—
SHLR2
Rn
Rn >> 2 → Rn
0100nnnn00001001
—
1
—
SHLL8
Rn
Rn << 8 → Rn
0100nnnn00011000
—
1
—
SHLR8
Rn
Rn >> 8 → Rn
0100nnnn00011001
—
1
—
SHLL16 Rn
Rn << 16 → Rn
0100nnnn00101000
—
1
—
SHLR16 Rn
Rn >> 16 → Rn
0100nnnn00101001
—
1
—
Rev. 5.00 Dec 12, 2005 page 74 of 1034
REJ09B0254-0500
1
MSB
Section 2 CPU
Branch Instructions
Table 2.24 Branch Instructions
Instruction
Operation
Code
Privileged
Mode
Cycles
T Bit
BF
label
If T = 0, disp × 2 + PC → PC;
if T = 1, nop (where label is
disp + PC)
10001011dddddddd
—
3/1*
—
BF/S
label
Delayed branch, if T = 0,
disp × 2 + PC → PC;
if T = 1, nop
10001111dddddddd
—
2/1*
—
BT
label
Delayed branch, if T = 1,
disp × 2 + PC → PC;
if T = 0, nop
10001001dddddddd
—
3/1*
—
BT/S
label
If T = 1, disp × 2 + PC → PC;
if T = 0, nop
10001101dddddddd
—
2/1*
—
BRA
label
Delayed branch,
disp × 2 + PC → PC
1010dddddddddddd
—
2
—
BRAF
Rm
Delayed branch,
Rm + PC → PC
0000mmmm00100011
—
2
—
BSR
label
Delayed branch, PC → PR,
disp × 2 + PC → PC
1011dddddddddddd
—
2
—
BSRF
Rm
Delayed branch, PC → PR,
Rm + PC → PC
0000mmmm00000011
—
2
—
JMP
@Rm
Delayed branch, Rm → PC
0100mmmm00101011
—
2
—
JSR
@Rm
Delayed branch, PC → PR,
Rm → PC
0100mmmm00001011
—
2
—
Delayed branch, PR → PC
0000000000001011
—
2
—
RTS
Note: * One state when the branch is not executed.
Rev. 5.00 Dec 12, 2005 page 75 of 1034
REJ09B0254-0500
Section 2 CPU
System Control Instructions
Table 2.25 System Control Instructions
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
CLRMAC
0 → MACH, MACL
0000000000101000
—
1
—
CLRS
0→S
0000000001001000
—
1
—
CLRT
0→T
0000000000001000
—
1
0
LDC
Rm,SR
Rm → SR
0100mmmm00001110
√
5
LSB
LDC
Rm,GBR
Rm → GBR
0100mmmm00011110
—
3
—
LDC
Rm,VBR
Rm → VBR
0100mmmm00101110
√
3
—
LDC
Rm,SSR
Rm → SSR
0100mmmm00111110
√
3
—
LDC
Rm,SPC
Rm → SPC
0100mmmm01001110
√
3
—
LDC
Rm,R0_BANK
Rm → R0_BANK
0100mmmm10001110
√
3
—
LDC
Rm,R1_BANK
Rm → R1_BANK
0100mmmm10011110
√
3
—
LDC
Rm,R2_BANK
Rm → R2_BANK
0100mmmm10101110
√
3
—
LDC
Rm,R3_BANK
Rm → R3_BANK
0100mmmm10111110
√
3
—
LDC
Rm,R4_BANK
Rm → R4_BANK
0100mmmm11001110
√
3
—
LDC
Rm,R5_BANK
Rm → R5_BANK
0100mmmm11011110
√
3
—
LDC
Rm,R6_BANK
Rm → R6_BANK
0100mmmm11101110
√
3
—
LDC
Rm,R7_BANK
Rm → R7_BANK
0100mmmm11111110
√
3
—
LDC.L @Rm+,SR
(Rm) → SR, Rm + 4 → Rm
0100mmmm00000111
√
7
LSB
LDC.L @Rm+,GBR
(Rm) → GBR, Rm + 4 → Rm
0100mmmm00010111
—
5
—
LDC.L @Rm+,VBR
(Rm) → VBR, Rm + 4 → Rm
0100mmmm00100111
√
5
—
LDC.L @Rm+,SSR
(Rm) → SSR, Rm + 4 → Rm
0100mmmm00110111
√
5
—
LDC.L @Rm+,SPC
(Rm) → SPC, Rm + 4 → Rm
0100mmmm01000111
√
5
—
LDC.L @Rm+,
R0_BANK
(Rm) → R0_BANK,
Rm + 4 → Rm
0100mmmm10000111
√
5
—
LDC.L @Rm+,
R1_BANK
(Rm) → R1_BANK,
Rm + 4 → Rm
0100mmmm10010111
√
5
—
LDC.L @Rm+,
R2_BANK
(Rm) → R2_BANK,
Rm + 4 → Rm
0100mmmm10100111
√
5
—
LDC.L @Rm+,
R3_BANK
(Rm) → R3_BANK,
Rm + 4 → Rm
0100mmmm10110111
√
5
—
LDC.L @Rm+,
R4_BANK
(Rm) → R4_BANK,
Rm + 4 → Rm
0100mmmm11000111
√
5
—
Rev. 5.00 Dec 12, 2005 page 76 of 1034
REJ09B0254-0500
Section 2 CPU
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
LDC.L @Rm+,
R5_BANK
(Rm) → R5_BANK,
Rm + 4 → Rm
0100mmmm11010111
√
5
—
LDC.L @Rm+,
R6_BANK
(Rm) → R6_BANK,
Rm + 4 → Rm
0100mmmm11100111
√
5
—
LDC.L @Rm+,
R7_BANK
(Rm) → R7_BANK,
Rm + 4 → Rm
0100mmmm11110111
√
5
—
LDS
Rm,MACH
Rm → MACH
0100mmmm00001010
—
1
—
LDS
Rm,MACL
Rm → MACL
0100mmmm00011010
—
1
—
LDS
Rm,PR
Rm → PR
0100mmmm00101010
—
1
—
LDS.L @Rm+,MACH
(Rm) → MACH, Rm + 4 → Rm
0100mmmm00000110
—
1
—
LDS.L @Rm+,MACL
(Rm) → MACL, Rm + 4 → Rm
0100mmmm00010110
—
1
—
LDS.L @Rm+,PR
(Rm) → PR, Rm + 4 → Rm
0100mmmm00100110
—
1
—
LDTLB
PTEH/PTEL → TLB
0000000000111000
√
1
—
NOP
No operation
0000000000001001
—
1
—
(Rm) → cache
0000mmmm10000011
—
2
—
RTE
Delayed branch,
SSR/SPC → SR/PC
0000000000101011
√
4
—
SETS
1→S
0000000001011000
—
1
—
SETT
1→T
0000000000011000
—
1
1
SLEEP
Sleep
0000000000011011
√
4*
—
PREF
@Rm
STC
SR,Rn
SR → Rn
0000nnnn00000010
√
1
—
STC
GBR,Rn
GBR → Rn
0000nnnn00010010
—
1
—
STC
VBR,Rn
VBR → Rn
0000nnnn00100010
√
1
—
STC
SSR,Rn
SSR → Rn
0000nnnn00110010
√
1
—
STC
SPC,Rn
SPC → Rn
0000nnnn01000010
√
1
—
STC
R0_BANK,Rn
R0_BANK→ Rn
0000nnnn10000010
√
1
—
STC
R1_BANK,Rn
R1_BANK→ Rn
0000nnnn10010010
√
1
—
STC
R2_BANK,Rn
R2_BANK→ Rn
0000nnnn10100010
√
1
—
STC
R3_BANK,Rn
R3_BANK→ Rn
0000nnnn10110010
√
1
—
STC
R4_BANK,Rn
R4_BANK→ Rn
0000nnnn11000010
√
1
—
STC
R5_BANK,Rn
R5_BANK→ Rn
0000nnnn11010010
√
1
—
STC
R6_BANK,Rn
R6_BANK→ Rn
0000nnnn11100010
√
1
—
STC
R7_BANK,Rn
R7_BANK→ Rn
0000nnnn11110010
√
1
—
Rev. 5.00 Dec 12, 2005 page 77 of 1034
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Section 2 CPU
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
STC.L SR,@–Rn
Rn–4 → Rn, SR → (Rn)
0100nnnn00000011
√
2
—
STC.L GBR,@–Rn
Rn–4 → Rn, GBR → (Rn)
0100nnnn00010011
—
2
—
STC.L VBR,@–Rn
Rn–4 → Rn, VBR → (Rn)
0100nnnn00100011
√
2
—
STC.L SSR,@–Rn
Rn–4 → Rn, SSR → (Rn)
0100nnnn00110011
√
2
—
STC.L SPC,@–Rn
Rn–4 → Rn, SPC → (Rn)
0100nnnn01000011
√
2
—
STC.L R0_BANK,
@–Rn
Rn–4 → Rn, R0_BANK → (Rn)
0100nnnn10000011
√
2
—
STC.L R1_BANK,
@–Rn
Rn–4 → Rn, R1_BANK → (Rn)
0100nnnn10010011
√
2
—
STC.L R2_BANK,
@–Rn
Rn–4 → Rn, R2_BANK → (Rn)
0100nnnn10100011
√
2
—
STC.L R3_BANK,
@–Rn
Rn–4 → Rn, R3_BANK → (Rn)
0100nnnn10110011
√
2
—
STC.L R4_BANK,
@–Rn
Rn–4 → Rn, R4_BANK → (Rn)
0100nnnn11000011
√
2
—
STC.L R5_BANK,
@–Rn
Rn–4 → Rn, R5_BANK → (Rn)
0100nnnn11010011
√
2
—
STC.L R6_BANK,
@–Rn
Rn–4 → Rn, R6_BANK → (Rn)
0100nnnn11100011
√
2
—
STC.L R7_BANK,
@–Rn
Rn–4 → Rn, R7_BANK → (Rn)
0100nnnn11110011
√
2
—
STS
MACH,Rn
MACH → Rn
0000nnnn00001010
—
1
—
STS
MACL,Rn
MACL → Rn
0000nnnn00011010
—
1
—
STS
PR,Rn
PR → Rn
0000nnnn00101010
—
1
—
STS.L MACH,@–Rn
Rn–4 → Rn, MACH → (Rn)
0100nnnn00000010
—
1
—
STS.L MACL,@–Rn
Rn–4 → Rn, MACL → (Rn)
0100nnnn00010010
—
1
—
STS.L PR,@–Rn
Rn–4 → Rn, PR → (Rn)
0100nnnn00100010
—
1
—
TRAPA #imm
PC → SPC, SR → SSR,
imm << 2 → TRA,
VBR + H'0100 → PC
11000011iiiiiiii
—
8
—
Note: * Number of states before the chip enters the sleep state.
The table shows the minimum number of clocks required for execution. In practice, the
number of execution cycles will be increased if there is contention between an instruction
fetch and a data access, or if the destination register of a load instruction (memory →
register) is also used by the following instruction.
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Section 2 CPU
2.6
DSP Extended-Function Instructions
2.6.1
Introduction
The newly added instructions are classified into the following three groups:
1. Additional system control instructions for the CPU unit
2. DSP unit memory-register single and double data transfer
3. DSP unit parallel processing
Group 1 instructions are provided to support loop control and data transfer between CPU core
registers or memory and new control registers added to the CPU core. DSP operations employ a
multi-level nested-loop structure. With a single-level loop, use of the decrement and test, DTRn,
and conditional delayed branch BF/S instructions supported by the SH-3 is adequate. However,
with nested loops, DSP performance can be improved by means of a zero-overhead loop control
function.
The RS, RE, and MOD registers have been added to support loop control and modulo addressing
functions. Instructions are supported for data transfer between these new control registers and
general registers or memory. In addition, the LDRS and LDRE address calculation registers have
been added to reduce the code size for the initial settings for zero-overhead loop control.
An independent control register, DSR, is provided for the DSP engine. This register is treated as a
system register such as MACL and MACH. The A0, X0, X1, Y0, and Y1 registers are treated as
system registers from the CPU side, and LDS/STS instructions are supported for the same
purpose. Table 2.26 shows the instruction code map for the new system control instructions for the
CPU core.
Group 2 instructions are provided to reduce DSP operation program code size. Data transfer
instructions that perform no data processing are frequently executed by the DSP engine. In this
case, a 32-bit instruction code is unnecessarily long, and wastes space in the program memory
area. All instructions in this class have a 16-bit code length, the same as conventional SH core
instructions. Single data transfer instructions have greater flexibility in terms of operands than the
double data transfer instruction or parallel instruction class.
Group 3 instructions are provided for fast execution of digital signal processing operations using
the DSP unit. These instructions have a 32-bit instruction code, so that a maximum of four
instructions—an ALU operation, multiplication, and two data transfer instructions—can be
executed in parallel.
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Section 2 CPU
2.6.2
Added CPU System Control Instructions
The new instructions in this class are treated as part of the CPU core functions, and therefore all
the added instructions have a 16-bit code length. All the additional instructions belong to the
system control instruction group. Table 2.26 summarizes the added system instructions. New
control registers—RS, RE, and MOD—have been added to the CPU core to support loop control
and modulo addressing functions, and LDC and STS type instructions have been provided for
these registers.
The DSP engine’s DSR, A0, X0, X1, Y0, and Y1 registers are treated as system registers such as
MACH and MACL, and therefore STS and LDS instructions are supported for these registers. As
digital signal processing operations usually employ a multi-level nested-loop structure, DSP
performance can be improved by means of a zero-overhead loop control function. SETRC type
instructions are provided to set the repeat count in the RC field in SR[27:16]. When an immediate
operand type SETRC instruction is executed, the 8-bit immediate operand data is set in SR[23:16],
and 0 is set in the remaining bits, SR[27:24]. When a register operand type SETRC instruction is
executed, Rn[11:0] is set in SR[27:16]. The start address and end address of the repeat loop are set
in the RS register and RE register. There are two ways of setting the addresses: by using an LDC
type instruction, or by using the LDRS and LDRE instructions.
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Section 2 CPU
Table 2.26 Added CPU System Control Instructions
Instruction
Instruction Code
Operation
Execution
States
SETRC #imm
10000010iiiiiiii
imm → RC (of SR)
3
SETRC Rn
0100nnnn00010100
Rn[11:0] → R C (of SR)
3
—
LDRS
@(disp,PC)
10001100dddddddd
(disp × 2 + PC) → RS
3
—
LDRE
@(disp,PC)
10001110dddddddd
(disp × 2 + PC) → RE
3
—
STC
MOD,Rn
0000nnnn01010010
MOD → Rn
1
—
STC
RS,Rn
0000nnnn01100010
RS → Rn
1
—
STC
RE,Rn
0000nnnn01110010
RE → Rn
1
—
STS
DSR,Rn
0000nnnn01101010
DSR → Rn
1
—
STS
A0,Rn
0000nnnn01111010
A0 → Rn
1
—
STS
X0,Rn
0000nnnn10001010
X0 → Rn
1
—
STS
X1,Rn
0000nnnn10011010
X1 → Rn
1
—
STS
Y0,Rn
0000nnnn10101010
Y0 → Rn
1
—
STS
Y1,Rn
0000nnnn10111010
Y1 → Rn
1
—
STS.L DSR,@-Rn
0100nnnn01100010
Rn – 4 → Rn, DSR → (Rn)
1
—
STS.L A0,@-Rn
0100nnnn01110010
Rn – 4 → Rn, A0 → (Rn)
1
—
STS.L X0,@-Rn
0100nnnn10000010
Rn – 4 → Rn, X0 → (Rn)
1
—
STS.L X1,@-Rn
0100nnnn10010010
Rn – 4 → Rn, X1 → (Rn)
1
—
STS.L Y0,@-Rn
0100nnnn10100010
Rn – 4 → Rn, Y0 → (Rn)
1
—
STS.L Y1,@-Rn
0100nnnn10110010
Rn – 4 → Rn, Y1 → (Rn)
1
—
STC.L MOD,@-Rn
0100nnnn01010011
Rn – 4 → Rn, MOD → (Rn)
2
—
STC.L RS,@-Rn
0100nnnn01100011
Rn – 4 → Rn, RS → (Rn)
2
—
STC.L RE,@-Rn
0100nnnn01110011
Rn – 4 → Rn, RE → (Rn)
2
—
LDS.L @Rn+,DSR
0100nnnn01100110
(Rn) → DSR, Rn + 4 → Rn
1
—
LDS.L @Rn+,A0
0100nnnn01110110
(Rn) → A0, Rn + 4 → Rn
1
—
LDS.L @Rn+,X0
0100nnnn10000110
(Rn) → X0, Rn + 4 → Rn
1
—
LDS.L @Rn+,X1
0100nnnn10010110
(Rn) → X1, Rn + 4 → Rn
1
—
LDS.L @Rn+,Y0
0100nnnn10100110
(Rn) → Y0, Rn + 4 → Rn
1
—
LDS.L @Rn+,Y1
0100nnnn10110110
(Rn) → Y1, Rn + 4 → Rn
1
—
LDC.L @Rn+,MOD
0100nnnn01010111
(Rn) → MOD, Rn + 4 → Rn
5
—
LDC.L @Rn+,RS
0100nnnn01100111
(Rn) → RS, Rn + 4 → Rn
5
—
T Bit
—
Rev. 5.00 Dec 12, 2005 page 81 of 1034
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Section 2 CPU
Instruction
Instruction Code
Operation
Execution
States
LDC.L @Rn+,RE
0100nnnn01110111
(Rn) → RE, Rn + 4 → Rn
5
—
LDS
Rn,DSR
0100nnnn01101010
Rn → DSR
1
—
LDS
Rn,A0
0100nnnn01111010
Rn → A0
1
—
LDS
Rn,X0
0100nnnn10001010
Rn → X0
1
—
LDS
Rn,X1
0100nnnn10011010
Rn → X1
1
—
LDS
Rn,Y0
0100nnnn10101010
Rn → Y0
1
—
LDS
Rn,Y1
0100nnnn10111010
Rn → Y1
1
—
LDC
Rn,MOD
0100nnnn01011110
Rn → MOD
3
—
LDC
Rn,RS
0100nnnn01101110
Rn → RS
3
—
LDC
Rn,RE
0100nnnn01111110
Rn → RE
3
—
2.6.3
T Bit
Single and Double Data Transfer for DSP Data Instructions
The new instructions in this class are provided to reduce the program code size for DSP
operations. All the new instructions in this class have a 16-bit code length. Instructions in this
class are divided into two groups: single data transfer instructions and double data transfer
instructions. The operand flexibility of the double data transfer instructions is the same as with the
A field in parallel instruction class data transfer instructions described in section 2.6.4, DSP
Operation Instruction Set. However, conditional load instructions cannot be used with these 16-bit
instructions. In single transfer, the Ax pointer and two other pointers are used as the As pointer,
but the Ay pointer is not used. Tables 2.27 and 2.28 list the single and double data transfer
instructions.
With double data transfer group instructions, X memory and Y memory can be accessed in
parallel. The Ax pointer can only be used by X memory access instructions, and the Ay pointer
only by Y memory access instructions. Double data transfer instructions can only access the onchip X and Y memory areas. Single data transfer instructions use a 16-bit instruction code, and can
access any memory address space.
Rn (n = 2 to 7) registers are normally used as the Ax, Ay, and As pointers. The pointer names
themselves can be changed with the assembler rename function. The following renaming scheme
is recommended.
R2:As2, R3:As3, R4:Ax0 (As0), R5:Ax1 (As1), R6:Ay0, R7:Ay1, R8:Ix, R9:Iy
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Section 2 CPU
Table 2.27 Double Data Transfer Instructions
Instruction
Instruction Code
Operation
Execution
States DC
X memory
NOPX
data transfer MOVX.W @Ax,Dx
1111000*0*0*00**
X memory no access
1
—
111100A*D*0*01**
(Ax) → MSW of Dx,
0 → LSW of Dx
1
—
111100A*D*0*10**
(Ax) → MSW of Dx,
0 → LSW of Dx,
Ax + 2 → Ax
1
—
MOVX.W @Ax+Ix,Dx 111100A*D*0*11**
(Ax) → MSW of Dx,
0 → LSW of Dx,
Ax + Ix → Ax
1
—
MOVX.W Da,@Ax
111100A*D*1*01**
MSW of Da → (Ax)
1
—
MOVX.W Da,@Ax+
111100A*D*1*10**
MSW of Da → (Ax),
Ax + 2 → Ax
1
—
MOVX.W Da,@Ax+Ix 111100A*D*1*11**
MSW of Da → (Ax),
Ax + Ix → Ax
1
—
111100*0*0*0**00
Y memory no access
1
—
111100*A*D*0**01
(Ay) → MSW of Dy,
0 → LSW of Dy
1
—
111100*A*D*0**10
(Ay) → MSW of Dy,
0 → LSW of Dy,
Ay + 2 → Ay
1
—
MOVY.W @Ay+Iy,Dy 111100*A*D*0**11
(Ay) → MSW of Dy,
0 → LSW of Dy,
Ay + Iy → Ay
1
—
MOVY.W Da,@Ay
111100*A*D*1**01
MSW of Da → (Ay)
1
—
MOVY.W Da,@Ay+
111100*A*D*1**10
MSW of Da → (Ay),
Ay + 2 → Ay
1
—
MOVY.W Da,@Ay+Iy 111100*A*D*1**11
MSW of Da → (Ay),
Ay + Iy → Ay
1
—
MOVX.W @Ax+,Dx
Y memory
NOPY
data transfer MOVY.W @Ay,Dy
MOVY.W @Ay+,Dy
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Section 2 CPU
Table 2.28 Single Data Transfer Instructions
Execution
States
DC
Instruction
Instruction Code
Operation
MOVS.W @-As,Ds
111101AADDDD0000
As – 2 → As, (As) →
MSW of Ds, 0 → LSW of Ds
1
—
MOVS.W @As,Ds
111101AADDDD0100
(As) → MSW of Ds,
0 → LSW of Ds
1
—
MOVS.W @As+,Ds
111101AADDDD1000
(As) → MSW of Ds,
0 → LSW of Ds, As + 2 → As
1
—
MOVS.W @As+Ix,Ds
111101AADDDD1100
(Asc) → MSW of Ds,
0 → LSW of Ds, As + Ix → As
1
—
MOVS.W Ds,@-As*
111101AADDDD0001
As – 2 → As,
MSW of Ds → (As)
1
—
MOVS.W Ds,@As*
111101AADDDD0101
MSW of Ds → (As)
1
—
MOVS.W Ds,@As+*
111101AADDDD1001
MSW of Ds → (As),
As + 2 → As
1
—
MOVS.W Ds,@As+Ix* 111101AADDDD1101
MSW of Ds → (As),
As + Ix → As
1
—
MOVS.L @-As,Ds
111101AADDDD0010
As – 4 → As, (As) → Ds
1
—
MOVS.L @As,Ds
111101AADDDD0110
(As) → Ds
1
—
MOVS.L @As+,Ds
111101AADDDD1010
(As) → Ds, As + 4 → As
1
—
MOVS.L @As+Ix,Ds
111101AADDDD1110
(As) → Ds, As + Ix → As
1
—
MOVS.L Ds,@-As
111101AADDDD0011
As – 4 → As, Ds → (As)
1
—
MOVS.L Ds,@As
111101AADDDD0111
Ds → (As)
1
—
MOVS.L Ds,@As+
111101AADDDD1011
Ds → (As), As + 4 → As
1
—
MOVS.L Ds,@As+Ix
111101AADDDD1111
Ds → (As), As + Ix → As
1
—
Note: * If guard bit registers A0G and A1G are specified in source operand Ds, the data is output
to the LDB[7:0] bus and the sign bit is copied into the upper bits, [31:8].
Rev. 5.00 Dec 12, 2005 page 84 of 1034
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Section 2 CPU
The correspondence between DSP data transfer operands and registers is shown in table 2.29.
CPU core registers are used as a pointer address that indicates a memory address.
Table 2.29 Correspondence between DSP Data Transfer Operands and Registers
Register
CPU
register
Ax
Ix
Dx
Ay
Iy
Dy
Da
R1
Yes
R3 (As3)
Yes
R4 (Ax0)
Yes
Yes
R5 (Ax1)
Yes
Yes
R6 (Ay0)
Yes
R7 (Ay1)
Yes
R8 (Ix)
Yes
R9 (Iy)
2.6.4
Ds
R0
R2 (As2)
DSP
register
As
Yes
A0
Yes
Yes
A1
Yes
Yes
M0
Yes
M1
Yes
X0
Yes
Yes
X1
Yes
Yes
Y0
Yes
Yes
Y1
Yes
Yes
A0G
Yes
A1G
Yes
DSP Operation Instruction Set
DSP operation instructions are instructions for digital signal processing performed by the DSP
unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed
in parallel. The instruction code is divided into an A field and B field; a parallel data transfer
instruction is specified in the A field, and a single or double data operation instruction in the B
field. Instructions can be specified independently, and are also executed independently. The
parallel data transfer instruction specified in the A field is exactly the same as a double data
transfer instruction. The function of the A field—that is, the data transfer instruction field—is
Rev. 5.00 Dec 12, 2005 page 85 of 1034
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Section 2 CPU
basically the same as in the double data transfer instructions described in section 2.6.3, Single and
Double Data Transfer for DSP Data Instructions, but has a special function in load instructions.
B-field data operation instructions are of three kinds: double data operation instructions,
conditional single data operation instructions, and unconditional single data operation instructions.
The formats of the DSP operation instructions are shown in table 2.30. The respective operands
are selected independently from the DSP registers. The correspondence between DSP operation
instruction operands and registers is shown in table 2.31.
Table 2.30 DSP Operation Instruction Formats
Type
Instruction Formats
Double data operation instructions
ALUop. Sx, Sy, Du
MLTop. Se, Df, Dg
Conditional single data operation
instructions
ALUop. Sx, Sy, Dz
DCT
ALUop. Sx, Sy, Dz
DCF
ALUop. Sx, Sy, Dz
ALUop. Sx, Dz
DCT
ALUop. Sx, Dz
DCF
ALUop. Sx, Dz
ALUop. Sy, Dz
Unconditional single data operation
instructions
DCT
ALUop. Sy, Dz
DCF
ALUop. Sy, Dz
ALUop. Sx, Sy, Dz
ALUop. Sx, Dz
ALUop. Sy, Dz
MLTop. Se, Sf, Dg
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Section 2 CPU
Table 2.31 Correspondence between DSP Instruction Operands and Registers
ALU/BPU Operations
Register
Sx
A0
A1
Sy
Multiply Operations
Dz
Du
Yes
Yes
Yes
Yes
Yes
Yes
Se
Sf
Dg
Yes
Yes
Yes
Yes
M0
Yes
Yes
Yes
M1
Yes
Yes
Yes
X0
Yes
Yes
X1
Yes
Yes
Y0
Yes
Yes
Y1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
When writing parallel instructions, the B-field instruction is written first, followed by the A-field
instruction. A sample parallel processing program is shown in figure 2.16.
PADD A0, M0, A0
DCF PINC X1, A1
PCMP X1, M0
PMULS X0, Y0, M0
MOVX.W @R4+, X0
MOVX.W A0, @R5+R8
MOVX.W @R4
MOVY.W @R6+, Y0 [;]
MOVY.W @R7+, Y0 [;]
[NOPY] [;]
Figure 2.16 Sample Parallel Instruction Program
Square brackets mean that the contents can be omitted.
The no operation instructions NOPX and NOPY can be omitted. Table 2.32 gives an overview of
the B field in parallel operation instructions.
A semicolon is the instruction line delimiter, but this can also be omitted. If the semicolon
delimiter is used, the area to the right of the semicolon can be used as a comment field. This has
the same function as with conventional SH tools.
The DSR register condition code bit (DC) is always updated on the basis of the result of an
unconditional ALU or shift operation instruction. Conditional instructions do not update the DC
bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means
of bits CS0 to CS2 in the DSR register. The DC bit update rules are shown in table 2.33.
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Section 2 CPU
Table 2.32 DSP Operation Instructions
Instruction
Instruction Code
PMULS Se,Sf,Dg 111110**********
Operation
Execution
States
DC
Se * Sf → Dg (signed)
1
—
Sx + Sy → Du
Se * Sf → Dg (signed)
1
*
1
*
0100eeff0000gg00
PADD Sx,Sy,Du
111110**********
PMULS Se,Sf,Dg
0111eeffxxyygguu
PSUB Sx,Sy,Du
111110**********
PMULS Se,Sf,Dg
0110eeffxxyygguu
Sy – Sy → Du
Se * Sf → Dg (signed)
PADD Sx,Sy,Dz
111110**********
Sx + Sy → Dz
1
*
111110**********
If DC = 1, Sx + Sy → Dz
1
*
10110010xxyyzzzz
If DC = 0, nop
1
*
10110001xxyyzzzz
DCT PADD Sx,Sy,Dz
DCF PADD Sx,Sy,Dz
PSUB Sx,Sy,Dz
111110**********
If DC = 0, Sx + Sy → Dz
10110011xxyyzzzz
If DC = 1, nop
111110**********
Sx – Sy → Dz
1
*
1
*
1
*
1
*
1
*
10100001xxyyzzzz
DCT PSUB Sx,Sy,Dz
DCF PSUB Sx,Sy,Dz
PSHA Sx,Sy,Dz
111110**********
If DC = 1, Sx – Sy → Dz
10100010xxyyzzzz
If DC = 0, nop
111110**********
If DC = 0, Sx – Sy → Dz
10100011xxyyzzzz
If DC = 1, nop
111110**********
If Sy > = 0, Sx << Sy → Dz
(arithmetic shift)
1010001xxyyzzzz
If Sy<0, Sx>>Sy → Dz
DCT PSHA Sx,Sy,Dz
111110**********
10010010xxyyzzzz
If DC = 1 & Sy > = 0,
Sx << Sy → Dz (arithmetic
shift)
If DC = 1 & Sy < 0,
Sx >> Sy → Dz
If DC = 0, nop
Rev. 5.00 Dec 12, 2005 page 88 of 1034
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Section 2 CPU
Execution
States
DC
1
*
1
*
If DC = 1 & Sy > = 0,
1
Sx << Sy → Dz (logical shift)
*
Instruction
Instruction Code
Operation
DCF PSHA Sx,Sy,Dz
111110**********
If DC = 0 & Sy > = 0,
Sx << Sy → Dz (arithmetic
shift)
10010011xxyyzzzz
If DC = 0 & Sy < 0,
Sx >> Sy → Dz
If DC = 1, nop
PSHL Sx,Sy,Dz
111110**********
10000001xxyyzzzz
If Sy > = 0, Sx << Sy → Dz
(logical shift)
If Sy < 0, Sx >> Sy → Dz
DCT PSHL Sx,Sy,Dz
111110**********
10000010xxyyzzzz
If DC = 1 & Sy < 0,
Sx >> Sy → Dz
If DC = 0, nop
DCF PSHL Sx,Sy,Dz
111110**********
10000011xxyyzzzz
If DC = 0 & Sy > = 0,
1
Sx << Sy → Dz (logical shift)
*
If DC = 0 & Sy < 0,
Sx >> Sy → Dz
If DC = 1, nop
PCOPY Sx,Dz
Sx → Dz
1
*
Sy → Dz
1
*
111110**********
If DC = 1, Sx → Dz
1
*
11011010xx00zzzz
If DC = 0, nop
1
*
1
*
1
*
1
*
111110**********
11011001xx00zzzz
PCOPY Sy,Dz
111110**********
1111100100yyzzzz
DCT
DCT
DCF
DCF
PCOPY Sx,Dz
PCOPY Sy,Dz
PCOPY Sx,Dz
PCOPY Sy,Dz
PDMSB Sx,Dz
111110**********
If DC = 1, Sy → Dz
1111101000yyzzzz
If DC = 0, nop
111110**********
If DC = 0, Sx → Dz
11011011xx00zzzz
If DC = 1, nop
111110**********
If DC = 0, Sy → Dz
1111101100yyzzzz
If DC = 1, nop
111110**********
Sx → Dz normalization
count shift value
10011101xx00zzzz
Rev. 5.00 Dec 12, 2005 page 89 of 1034
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Section 2 CPU
Instruction
PDMSB Sy,Dz
PDMSB Sx,Dz
DC
Instruction Code
Operation
111110**********
Sx → Dz normalization
count shift value
1
*
If DC = 1, normalization
count shift value Sx → Dz
1
*
1
*
1
*
1
*
MSW of Sx → Dz
1
*
MSW of Sy → Dz
1
*
If DC = 1, MSW of Sx + 1
→ Dz
1
*
1
*
1
*
1
*
0 – Sx → Dz
1
*
0 – Sy → Dz
1
*
1011110100yyzzzz
DCT
Execution
States
111110**********
10011110xx00zzzz
If DC = 0, nop
DCT
PDMSB Sy,Dz
111110**********
1011111000yyzzzz
If DC = 1, normalization
count shift value Sy → Dz
If DC = 0, nop
DCF
PDMSB Sx,Dz
111110**********
10011111xx00zzzz
If DC = 0, normalization
count shift value Sx → Dz
If DC = 1, nop
DCF
PDMSB Sy,Dz
111110**********
1011111100yyzzzz
If DC = 0, normalization
count shift value Sy → Dz
If DC = 1, nop
PINC Sx,Dz
111110**********
10011001xx00zzzz
PINC Sy,Dz
111110**********
1011100100yyzzzz
DCT
PINC Sx,Dz
111110**********
10011010xx00zzzz
If DC = 0, nop
DCT
PINC Sy,Dz
111110**********
1011101000yyzzzz
If DC = 1, MSW of Sy + 1
→ Dz
If DC = 0, nop
DCF
PINC Sx,Dz
111110**********
10011011xx00zzzz
If DC = 0, MSW of Sx + 1
→ Dz
If DC = 1, nop
DCF
PINC Sy,Dz
111110**********
1011101100yyzzzz
If DC = 0, MSW of Sy + 1
→ Dz
If DC = 1, nop
PNEG Sx,Dz
111110**********
11001001xx00zzzz
PNEG Sy,Dz
111110**********
1110100100yyzzzz
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Section 2 CPU
Instruction
Instruction Code
Operation
Execution
States
DCT
111110**********
If DC = 1, 0 – Sx → Dz
1
*
11001010xx00zzzz
If DC = 0, nop
111110**********
If DC = 1, 0 – Sy → Dz
1
*
1110101000yyzzzz
If DC = 0, nop
1
*
1
*
Sx | Sy → Dz
1
*
111110**********
If DC = 1, Sx | Sy → Dz
1
*
10110110xxyyzzzz
If DC = 0, nop
111110**********
If DC = 0, Sx | Sy → Dz
1
*
10110111xxyyzzzz
If DC = 1, nop
111110**********
Sx & Sy → Dz
1
*
111110**********
If DC = 1, Sx & Sy → Dz
1
*
10010110xxyyzzzz
If DC = 0, nop
1
*
DCT
DCF
DCF
PNEG Sx,Dz
PNEG Sy,Dz
PNEG Sx,Dz
PNEG Sy,Dz
111110**********
If DC = 0, 0 – Sx → Dz
11001011xx00zzzz
If DC = 1, nop
111110**********
If DC = 0, 0 – Sy → Dz
1110101100yyzzzz
If DC = 1, nop
POR Sx,Sy,Dz 111110**********
DC
10110101xxyyzzzz
DCT POR Sx,Sy,Dz
DCF POR Sx,Sy,Dz
PAND Sx,Sy,Dz
10010101xxyyzzzz
DCT PAND Sx,Sy,Dz
DCF PAND Sx,Sy,Dz
PXOR Sx,Sy,Dz
111110**********
If DC = 0, Sx & Sy → Dz
10010111xxyyzzzz
If DC = 1, nop
111110**********
Sx ^ Sy → Dz
1
*
1
*
1
*
10100101xxyyzzzz
DCT PXOR Sx,Sy,Dz
DCF PXOR Sx,Sy,Dz
PDEC Sx,Dz
111110**********
If DC = 1, Sx ^ Sy → Dz
10100110xxyyzzzz
If DC = 0, nop
111110**********
If DC = 1, Sx ^ Sy → Dz
10100111xxyyzzzz
If DC = 0, nop
111110**********
Sx [39:16] – 1 → Dz
1
*
Sy [31:16] – 1 → Dz
1
*
10001001xx00zzzz
PDEC Sy,Dz
111110**********
1010100100yyzzzz
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Section 2 CPU
Execution
States
DC
1
*
1
*
1
*
1
*
H'00000000 → Dz
1
*
111110**********
If DC = 1, H'00000000 → Dz
1
*
100011100000zzzz
If DC = 0, nop
111110**********
If DC = 0, H'00000000 → Dz
1
*
100011110000zzzz
If DC = 1, nop
111110**********
If imm > = 0, Dz << imm
→ Dz (arithmetic shift)
1
*
1
*
MACH → Dz
1
—
If DC = 1, MACH → Dz
1
—
If DC = 0, MACH → Dz
1
—
MACL → Dz
1
—
Instruction
Instruction Code
Operation
DCT PDEC Sx,Dz
111110**********
If DC = 1, Sx [39:16] – 1
→ Dz
10001010xx00zzzz
If DC = 0, nop
DCT PDEC Sy,Dz
111110**********
1010101000yyzzzz
If DC = 1, Sy [31:16] – 1
→ Dz
If DC = 0, nop
DCF PDEC Sx,Dz
111110**********
10001011xx00zzzz
If DC = 0, Sx [39:16] – 1
→ Dz
If DC = 1, nop
DCF PDEC Sy,Dz
111110**********
1010101100yyzzzz
If DC = 0, Sy [31:16] – 1
→ Dz
If DC = 1, nop
PCLR Dz
111110**********
100011010000zzzz
DCT PCLR Dz
DCF PCLR Dz
PSHA #imm,Dz
00010iiiiiiizzzz
If imm<0, Dz>>imm → Dz
PSHL #imm,Dz
111110**********
00000iiiiiiizzzz
If imm > = 0, Dz << imm
→ Dz (logical shift)
If imm < 0, Dz >> imm → Dz
PSTS MACH,Dz
111110**********
110011010000zzzz
DCT PSTS MACH,Dz
111110**********
110011100000zzzz
DCF PSTS MACH,Dz
111110**********
110011110000zzzz
PSTS MACL,Dz
111110**********
110111010000zzzz
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Section 2 CPU
Instruction
Instruction Code
Operation
Execution
States
DCT PSTS MACL,Dz
111110**********
If DC = 1, MACL → Dz
1
—
If DC = 0, MACL → Dz
1
—
Dz → MACH
1
—
If DC = 1, Dz → MACH
1
—
If DC = 0, Dz → MACH
1
—
Dz → MACL
1
—
If DC = 1, Dz → MACL
1
—
If DC = 0, Dz → MACL
1
—
Sx + Sy + DC → Dz
1
Carry
1
Borrow
DC
110111100000zzzz
DCF PSTS MACL,Dz
111110**********
110111110000zzzz
PLDS Dz,MACH
111110**********
111011010000zzzz
DCT PLDS Dz,MACH
111110**********
111011100000zzzz
DCF PLDS Dz,MACH
111110**********
111011110000zzzz
PLDS Dz,MACL
111110**********
111111010000zzzz
DCT PLDS Dz,MACL
111110**********
111111100000zzzz
DCF PLDS Dz,MACL
111110**********
111111110000zzzz
PADDC Sx,Sy,Dz 111110**********
10110000xxyyzzzz
PSUBC Sx,Sy,Dz 111110**********
PCMP Sx,Sy
Carry → DC
Sx – Sy – DC → Dz
10100000xxyyzzzz
Borrow → DC
111110**********
Sx – Sy → DC update*
1
*
1
*
1
*
1
*
1
*
10000100xxyy0000
PABS Sx,Dz
PABS Sy,Dz
PRND Sx,Dz
PRND Sy,Dz
111110**********
If Sx < 0, 0 – Sx → Dz
10001000xx00zzzz
If Sx > = 0, nop
111110**********
If Sy < 0, 0 – Sy → Dz
1010100000yyzzzz
If Sx > = 0, nop
111110**********
Sx + H'00008000 → Dz
10011000xx00zzzz
LSW of Dz → H'0000
111110**********
Sy + H'00008000 → Dz
1011100000yyzzzz
LSW of Dz → H'0000
Note: * See table 2.33.
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Section 2 CPU
Table 2.33 DC Bit Update Definitions
CS [2:0]
Condition Mode
Description
0
Carry or borrow
mode
The DC bit is set if an ALU arithmetic operation generates a carry
or borrow, and is cleared otherwise.
0
0
When a PSHA or PSHL shift instruction is executed, the last bit
data shifted out is copied into the DC bit.
When an ALU logical operation is executed, the DC bit is always
cleared.
0
0
1
Negative value
mode
When an ALU or shift (PSHA) arithmetic operation is executed,
the MSB of the result, including the guard bits, is copied into the
DC bit.
When an ALU or shift (PSHL) logical operation is executed, the
MSB of the result, excluding the guard bits, is copied into the DC
bit.
0
1
0
Zero value mode
The DC bit is set if the result of an ALU or shift operation is allzeros, and is cleared otherwise.
0
1
1
Overflow mode
The DC bit is set if the result of an ALU or shift (PSHA) arithmetic
operation exceeds the destination register range, excluding the
guard bits, and is cleared otherwise.
When an ALU or shift (PSHL) logical operation is executed, the
DC bit is always cleared.
1
0
0
Signed greater-than This mode is similar to signed greater-or-equal mode, but DC is
mode
cleared if the result is all-zeros.
DC = ~{(negative value ^ over-range) | zero value};
In case of arithmetic operation
DC = 0; In case of logical operation
1
0
1
Signed greater-orequal mode
If the result of an ALU or shift (PSHA) arithmetic operation
exceeds the destination register range, including the guard bits
(“over-range”), the definition is the same as in negative value
mode. If the result is not over-range, the definition is the opposite
of that in negative value mode.
When an ALU or shift (PSHL) logical operation is executed, the
DC bit is always cleared.
DC = ~(negative value ^ over-range);
In case of arithmetic operation
DC = 0; In case of logical operation
1
1
0
Reserved
1
1
1
Reserved
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Section 2 CPU
Conditional Operations and Data Transfer: Some instructions belonging to this class can be
executed conditionally, as described earlier. The specified condition is valid only for the B field of
the instruction, and is not valid for data transfer instructions for which a parallel specification is
made. Examples are shown in figure 2.17.
DCT PADD X0,Y0,A0
MOVX.W @R4+,X0
MOVY.W A0,@R6+R9 ;
When condition is True
Before execution: X0=H'33333333, Y0=H'55555555,
R4=H'00008000, R6=H'00008233,
(R4)=H'1111, (R6)=H'2222
After execution: X0=H'11110000, Y0=H'55555555,
R4=H'00008002, R6=H'00008237,
(R4)=H'1111, (R6)=H'3456
A0=H'123456789A,
R9=H'00000004
A0=H'0088888888,
R9=H'00000004
When condition is False
Before execution: X0=H'33333333, Y0=H'55555555,
R4=H'00008000, R6=H'00008233,
(R4)=H'1111, (R6)=H'2222
After execution: X0=H'11110000, Y0=H'55555555,
R4=H'00008002, R6=H'00008237,
(R4)=H'1111, (R6)=H'3456
A0=H'123456789A,
R9=H'00000004
A0=H'123456789A,
R9=H'00000004
Figure 2.17 Examples of Conditional Operations and Data Transfer Instructions
Assignment of NOPX and NOPY Instruction Codes: When there is no data transfer instruction
to be parallel-processed simultaneously with a DSP operation instruction, an NOPX or NOPY
instruction can be written as the data transfer instruction, or the instruction can be omitted. The
instruction code is the same whether an NOPX or NOPY instruction is written or the instruction is
omitted. Examples of NOPX and NOPY instruction codes are shown in table 2.34.
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Section 2 CPU
Table 2.34 Examples of NOPX and NOPY Instruction Codes
Instruction
PADD X0,Y0,A0
Code
MOVX.W @R4+,X0
MOVY.W @R6+R9,Y0
1111100000001011
1011000100000111
PADD X0,Y0,A0
NOPX
MOVY.W @R6+R9,Y0
PADD X0,Y0,A0
NOPX
NOPY
1111100000000011
1011000100000111
1111100000000000
1011000100000111
PADD X0,Y0,A0
NOPX
1111100000000000
1011000100000111
PADD X0,Y0,A0
1111100000000000
1011000100000111
MOVX.W @R4+,X0
MOVY.W @R6+R9,Y0
1111000000001011
MOVX.W @R4+,X0
NOPY
1111000000001000
MOVY.W @R6+R9,Y0
1111000000000011
MOVY.W @R6+R9,Y0
1111000000000011
NOPY
1111000000000000
MOVS.W @R4+,X0
NOPX
NOPX
NOP
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1111010010001000
0000000000001001
Section 3 Memory Management Unit (MMU)
Section 3 Memory Management Unit (MMU)
3.1
Overview
3.1.1
Features
The SH7727 has an on-chip memory management unit (MMU) that implements address
translation. The SH7727 features a resident translation look-aside buffer (TLB) that caches
information for user-created address translation tables located in external memory. It enables highspeed translation of logical addresses into physical addresses. Address translation uses the paging
system and supports two page sizes (1 kbyte and 4 kbytes). The access right to logical address
space can be set for privileged and user modes to provide memory protection.
3.1.2
Role of MMU
The MMU is a feature designed to make efficient use of physical memory. As shown in figure 3.1,
if a process is smaller in size than the physical memory, the entire process can be mapped onto
physical memory. However, if the process increases in size to the extent that it no longer fits into
physical memory, it becomes necessary to partition the process and to map those parts requiring
execution onto memory as occasion demands (1). Having the process itself consider this mapping
onto physical memory would impose a large burden on the process. To lighten this burden, the
idea of virtual memory was born as a means of performing en bloc mapping onto physical
memory (2). In a virtual memory system, substantially more virtual memory than physical
memory is provided, and the process is mapped onto this virtual memory. Thus a process only has
to consider operation in virtual memory. Mapping from virtual memory to physical memory is
handled by the MMU. The MMU is normally controlled by the operating system, switching
physical memory to allow the virtual memory required by a process to be mapped onto physical
memory in a smooth fashion. Switching of physical memory is carried out via secondary storage,
etc.
The virtual memory system that came into being in this way is particularly effective in a timesharing system (TSS) in which a number of processes are running simultaneously (3). If processes
running in a TSS had to take mapping onto virtual memory into consideration while running, it
would not be possible to increase efficiency. Virtual memory is thus used to reduce this load on
the individual processes and so improve efficiency (4). In the virtual memory system, virtual
memory is allocated to each process. The task of the MMU is to perform efficient mapping of
these virtual memory areas onto physical memory. It also has a memory protection feature that
prevents one process from inadvertently accessing another process’s physical memory.
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Section 3 Memory Management Unit (MMU)
When address translation from virtual memory to physical memory is performed using the MMU,
it may occur that the relevant translation information is not recorded in the MMU, with the result
that one process may inadvertently access the virtual memory allocated to another process. In this
case, the MMU will generate an exception, change the physical memory mapping, and record the
new address translation information.
Although the functions of the MMU could also be implemented by software alone, the need for
translation to be performed by software each time a process accesses physical memory would
result in poor efficiency. For this reason, a buffer for address translation (translation look-aside
buffer: TLB) is provided in hardware to hold frequently used address translation information. The
TLB can be described as a cache for storing address translation information. Unlike cache
memory, however, if address translation fails, that is, if an exception is generated, switching of
address translation information is normally performed by software. This makes it possible for
memory management to be performed flexibly by software.
The MMU has two methods of mapping from virtual memory to physical memory: a paging
method using fixed-length address translation, and a segment method using variable-length
address translation. With the paging method, the unit of translation is a fixed-size address space
(usually of 1 to 64 kbytes) called a page.
In the following text, the SH7727 address space in virtual memory is referred to as logical address
space, and address space in physical memory as physical memory space.
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Section 3 Memory Management Unit (MMU)
Virtual
memory
Process 1
Physical
memory
Process 1
MMU
Physical
memory
Physical
memory
Process 1
(2)
(1)
Process 1
Process 1
Virtual
memory
MMU
Physical
memory
Physical
memory
Process 2
Process 2
Process 3
Process 3
(3)
(4)
Figure 3.1 MMU Functions
3.1.3
SH7727 MMU
Logical Address Space: The SH7727 uses 32-bit logical addresses to access a 4-Gbyte logical
address space that is divided into several areas. Address space mapping is shown in figure 3.2.
In the privileged mode, there are five areas, P0 to P4.
The P0 and P3 areas are mapped onto physical address space in page units, in accordance with
address translation table information. Write-back or write-through can be selected for write access
by means of a CCR setting.
Mapping of the P1 area is fixed in physical address space (H'00000000 to H'1FFFFFFF). In the
P1 area, setting a logical address MSB (bit 31) to 0 generates the corresponding physical address.
P1 area accesses can be cached, and the cache control register (CCR) is set to indicate whether to
cache or not. Write-back or write-through mode can be selected.
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Section 3 Memory Management Unit (MMU)
Mapping of the P2 area is fixed to physical address space (H'00000000 to H'1FFFFFFF). In the P2
area, setting the top three logical address bits (bits 31, 30, and 29) to 0 generates the corresponding
physical address. P2 area access cannot be cached.
The P1 and P2 areas are not mapped by the address translation table, so the TLB is not used and
no exceptions like TLB misses occur. Initialization of MMU-related registers, exception handling,
and the like are located in the P1 and P2 areas. Because the P1 area is cached, handlers that require
high-speed processing are placed there.
A part of the control register in the peripheral module is allocated in area 1 of the physical address
space. When the physical address space is not used for address translation, allocate that part of the
control register in the P2 area. When the physical address space is used for address translation, set
no caching.
The P4 area is used for mapping on-chip control register addresses.
In the user mode, 2 Gbytes of the logical address space from H'00000000 to H'7FFFFFFF (area
U0) can be accessed. U0 is mapped onto physical address space in page units, in accordance with
address translation table information. When SR.DSP is off, 2 Gbytes of the logical address space
from H'80000000 to H'FFFFFFFF cannot be accessed in the user mode. Attempting to do so
creates an address error. Write-back or write-through mode can be selected for write accesses by
means of a CCR setting.
When the SR.DSP is on, a new 16-MB address space, Uxy, is defined from address H'A5000000
to H'A5FFFFFF for X/Y RAM. This Uxy space is non-cached, fixed physical address space. Any
access to address space beyond U0 and Uxy creates an address error. For details on the X/Y RAM
space, refer to section 6, X/Y Memory.
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Section 3 Memory Management Unit (MMU)
H'00000000
H'00000000
2-Gbyte virtual space,
cacheable
(write-back/write-through)
H'80000000
H'A0000000
H'C0000000
H'E0000000
Area U0
H'80000000
0.5-Gbyte fixed physical
space, cacheable
(write-back/write-through)
Area P1
0.5-Gbyte fixed
physical space,
non-cacheable
Area P2
0.5-Gbyte virtual space,
cacheable
(write-back/write-through)
Area P3
0.5-Gbyte control space,
non-cacheable
2-Gbyte virtual space,
cacheable
(write-back/write-through)
Area P0
Address error
Area Uxy
(present
only when
SR.DSP=1)
Address error
Area P4
H'FFFFFFFF
H'FFFFFFFF
Privileged mode
User mode
Figure 3.2 Logical Address Space Mapping
Physical Address Space: The SH7727 supports a 32-bit physical address space, but the upper 3
bits are actually ignored and treated as a shadow. See section 12, Bus State Controller (BSC), for
details.
Address Translation: When the MMU is enabled, the logical address space is divided into units
called pages. Physical addresses are translated in page units. Address translation tables in external
memory hold information such as the physical address that corresponds to the logical address and
memory protection codes. When an access to an area other than P4 occurs, if the accessed logical
address belongs to area P1 or P2 there is no TLB access and the physical address is uniquely
defined. If it belongs to area P0, P3 or U0, the TLB is searched by logical address and, if that
logical address is registered in the TLB, the access hits the TLB. The corresponding physical
Rev. 5.00 Dec 12, 2005 page 101 of 1034
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Section 3 Memory Management Unit (MMU)
address and the page control information are read from the TLB and the physical address is
determined.
If the logical address is not registered in the TLB, a TLB miss exception occurs and processing
will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in
external memory is searched and the corresponding physical address and the page control
information are registered in the TLB. After returning from the handler, the instruction that caused
the TLB miss is re-executed. When the MMU is enabled, address translation information that
results in a physical address space of H'80000000 to H'FFFFFFFF should not be registered in the
TLB.
When the MMU is disabled, the logical address is used directly as the physical address. As the
SH7727 supports a 29-bit address space as the physical address space, the top 3 bits of the
physical address are ignored, and constitute a shadow space (see section 12, Bus State Controller
(BSC)). For example, addresses H'00001000 in the P0 area, H'80001000 in the P1 area,
H'A0001000 in the P2 area, and H'C0001000 in the P3 area are all mapped onto the same physical
address. When access to these addresses is performed with the cache enabled, an address with the
top 3 bits of the physical address masked to 0 is stored in the cache address array to ensure data
congruity.
Single Virtual Memory Mode and Multiple Virtual Memory Mode: There are two virtual
memory modes: single virtual memory mode and multiple virtual memory mode. In single virtual
memory mode, multiple processes run in parallel using the logical address space exclusively and
the physical address corresponding to a given logical address is specified uniquely. In multiple
virtual memory mode, multiple processes run in parallel sharing the logical address space, so a
given logical address may be translated into different physical addresses depending on the process.
By the value set to the MMU control register (MMUCR), either single or multiple virtual mode is
selected. In terms of operation, the only difference between single virtual memory mode and
multiple virtual memory mode is in the TLB address comparison method (see section 3.3.3, TLB
Address Comparison).
Address Space Identifier (ASID): In multiple virtual memory mode, the address space identifier
(ASID) is used to differentiate between processes running in parallel and sharing logical address
space. The ASID is 8 bits in length and can be set by software setting of the ASID of the currently
running process in PTEH within the MMU. When the process is switched using the ASID, the
TLB does not have to be purged.
In single virtual memory mode, the ASID is used to provide memory protection for processes
running simultaneously and using the logical address space exclusively (see section 3.4.2, MMU
Software Management).
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Section 3 Memory Management Unit (MMU)
3.1.4
Register Configuration
Table 3.1 shows the configuration of the MMU control registers.
Table 3.1
Register Configuration
R/W
Size
Initial Value*
Address
Page table entry register high PTEH
R/W
Longword
Undefined
H'FFFFFFF0
Page table entry register low
PTEL
R/W
Longword
Undefined
H'FFFFFFF4
Translation table base
register
TTB
R/W
Longword
Undefined
H'FFFFFFF8
TLB exception address
register
TEA
R/W
Longword
Undefined
H'FFFFFFFC
MMU control register
MMUCR
R/W
Longword
*2
H'FFFFFFE0
Name
Abbreviation
1
Notes: 1. Initialized by a power-on reset or manual reset.
2. SV bit = undefined
Other bits = 0
3.2
Register Description
There are five registers for MMU processing. These are all peripheral module registers, so they are
located in address space area P4 and can only be accessed from privileged mode by specifying the
address. These registers consist of:
1. The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which
consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the logical
address at which the exception is generated in case of an MMU exception or address error
exception. When the page size is 4 kbytes, the VPN is the upper 20 bits of the logical address,
but in this case the upper 22 bits of the logical address are set. The VPN can also be modified
by software. As the ASID, software sets the number of the currently executing process. The
VPN and ASID are recorded in the TLB by the LDTLB instruction.
2. The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to
store the physical page number and page management information to be recorded in the TLB
by the LDTLB instruction. The contents of this register are only modified in response to a
software command.
3. The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the
base address of the current page table. The software does not set any value in TTB
automatically. TTB is available to software for general purposes.
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Section 3 Memory Management Unit (MMU)
4. The TLB exception address register (TEA) residing at address H'FFFFFFFC, which stores the
logical address corresponding to a TLB or address error exception. This value remains valid
until the next exception or interrupt.
5. The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the
MMU settings described in figure 3.3. Any program that modifies MMUCR should reside in
the P1 or P2 area.
The MMU registers are shown in figure 3.3.
31
10
VPN
7
0
0
ASID
PTEH
10 9 8 7 6
31
4 3 2 1 0
0 V 0 PR SZ C D SH 0
PPN
PTEL
31
0
TTB
TTB
31
0
Virtual address causing TLB-related
or address error exception
TEA
31
8
0
7 6543 2 1
0
SV 00 RC 0 TF IX AT
MMUCR
0: Reserved bits. Always read as 0. Writing is ignored. However, 0 should also be
specified in a write to MMUCR only.
SV: Single virtual memory mode bit. Set to 1 for the single virtual memory mode,
cleared to 0 for the multiple virtual memory mode.
RC: A 2-bit random counter, automatically updated by hardware according to the
following rules in the event of an MMU exception. When a TLB miss exception
occurs, all TLB entry ways corresponding to the virtual address at which the
exception occurred are checked, and if all ways are valid, 1 is added to RC; if
there is one or more invalid way, they are set by priority from way 0, in the order:
way 0, way 1, way 2, way 3. In the event of an MMU exception other than a TLB
miss exception, the way which caused the exception is set in RC.
TF: TLB flush bit. Write 1 to flush the TLB (clear all valid bits of the TLB to 0). Always
reads 0.
IX: Index mode bit. When 0, VPN bits 16 to 12 are used as the TLB index number.
When 1, the value obtained by EX-ORing ASID bits 4 to 0 in PTEH and VPN bits
16 to 12 are used as the TLB index number.
AT: Address translation bit. Enables/disables the MMU.
0: MMU disabled
1: MMU enabled
Figure 3.3 MMU Register Contents
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Section 3 Memory Management Unit (MMU)
3.3
TLB Functions
3.3.1
Configuration of the TLB
The TLB caches address translation table information located in the external memory. The address
translation table stores the physical page number translated from the virtual page number, the
address space identifier, and the control information for the page, which is the unit of address
translation. Figure 3.4 shows the overall TLB configuration. The TLB is 4-way set associative
with 128 entries. There are 32 entries for each way. Figure 3.5 shows the configuration of logical
addresses and TLB entries.
Ways 0 to 3
Entry 0
VPN(31−17)
VPN(11−10) ASID(7−0)
Ways 0 to 3
V
Entry 0 PPN(31−10) PR(1−0) SZ C D SH
Entry 1
Entry 1
Entry 31
Entry 31
Address array
Data array
Figure 3.4 Overall Configuration of the TLB
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Section 3 Memory Management Unit (MMU)
31
10 9
VPN
0
Offset
Virtual address (1-kbyte page)
31
12 11
VPN
0
Offset
Virtual address (4-kbyte page)
(1) (1) (1)
(22)
(2) (1) (1)
VPN (31−17) VPN (11−10) ASID SH SZ V
(15)
(2)
(8)
PPN
PR C D
TLB entry
Legend:
VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of
virtual address for a 4-kbyte page. Since VPN bits 16 to 12 are used as the index number,
they are not stored in the TLB entry.
ASID: Address space identifier. Indicates the process that can access a virtual page. In single
virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0,
the address is compared with the ASID in PTEH when address comparison is performed.
SH: Share status bit
0 = Page not shared between processes
1 = Page shared between processes
SZ: Page-size bit
0 = 1-kbyte page
1 = 4-kbyte page
V: Valid bit. Indicates whether entry is valid.
0 = Invalid
1 = Valid
Cleared to 0 by a power-on reset. Not affected by a manual reset.
PPN: Physical page number. Top 22 bits of physical address. PPN bits 11 and 10 are not used in
case of a 4-kbyte page. Attention must be paid to the synonym problem in case of a 1-kbyte
page (see section 3.4.4, Avoiding Synonym Problems).
PR: Set the most significant bit to 0.
Protection key field. 2-bit field encoded to define the access rights to the page.
00: Reading only is possible in privileged mode.
01: Reading/writing is possible in privileged mode.
10: Reading only is possible in privileged/user mode.
11: Reading/writing is possible in privileged/user mode.
C: Cacheable bit. Indicates whether the page is cacheable.
0 = Non-cacheable
1 = Cacheable
D: Dirty bit. Indicates whether the page has been written to.
0 = Not written to
1 = Written to
Figure 3.5 Logical Address and TLB Structure
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Section 3 Memory Management Unit (MMU)
3.3.2
TLB Indexing
The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16
to 12 and ASID bits 4 to 0 in PTEH are used as the index number. The index number can be
generated in two different ways depending on the setting of the IX bit in MMUCR.
1. When IX = 0, VPN bits 16 to 12 alone are used as the index number
2. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate the index
number
The method 1 is used to prevent lowered TLB efficiency that results when multiple processes run
simultaneously in the same logical address space (multiple virtual memory) and a specific entry is
selected by indexing of each process. Figures 3.6 and 3.7 show the indexing schemes.
Virtual address
31
17 16 12 11
PTEH register
31
0
10
VPN
Exclusive-OR
7
0
0
ASID
ASID(4−0)
Index
Ways 0 to 3
0
VPN(31−17)
VPN(11−10)
ASID(7−0)
V
PPN(31−10) PR(1−0) SZ C
D SH
31
Address array
Data array
Figure 3.6 TLB Indexing (IX = 1)
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Section 3 Memory Management Unit (MMU)
Virtual address
31
17 16 12 11
0
Index
Ways 0 to 3
0
VPN(31−17)
VPN(11−10)
ASID(7−0)
V
PPN(31−10) PR(1−0) SZ C
D SH
31
Address array
Data array
Figure 3.7 TLB Indexing (IX = 0)
3.3.3
TLB Address Comparison
A TLB address comparison is performed when an instruction is fetched from a program in
external memory or data in external memory is referenced. The items used in the comparison are
VPN and ASID. The VPN of the logical address that accesses external memory is compared to the
VPN of the TLB entry selected with the index number. The ASID within the PTEH is compared to
the ASID of the indexed TLB entry. All four ways are searched simultaneously. If the compared
values match, and the indexed TLB entry is valid (V bit = 1), the hit is registered.
It is necessary to have software ensure that TLB hits do not occur simultaneously in more than one
way, as hardware operation is not guaranteed if this occurs. For example, if there are two identical
TLB entries with the same VPN and a setting is made such that a TLB hit is made only by a
process with ASID = H'FF when one is in the shared state (SH = 1) and the other in the non-shared
state (SH = 0), then if the ASID in PTEH is set to H'FF, there is a possibility of simultaneous TLB
hits in both these ways. It is therefore necessary to ensure that this kind of setting is not made by
software.
The object compared varies depending on the page management information (SZ, SH) in the TLB
entry. It also varies depending on whether the system supports multiple virtual memory or single
virtual memory.
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Section 3 Memory Management Unit (MMU)
The page-size information determines whether VPN (11, 10) is compared. VPN (11, 10) is
compared for 1-kbyte pages (SZ = 0) but not for 4-kbyte pages (SZ = 1).
The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry
are compared. ASIDs are compared when there is no sharing between processes (SH = 0) but not
when there is sharing (SH = 1).
When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged
(SR.MD = 1), all process resources can be accessed. This means that ASIDs are not compared
when single virtual memory is supported and privileged mode is engaged. The objects of address
comparison are shown in figure 3.8.
SH = 1 or
(SR.MD = 1 and
MMUCR.SV = 1)?
No
Yes
No (4 kbytes)
No (4 kbytes)
SZ = 0?
SZ = 0?
Yes (1 kbyte)
Bits compared:
VPN (31−17)
VPN (11−10)
Bits compared:
VPN (31−17)
Yes (1 kbyte)
Bits compared:
VPN (31−17)
VPN (11−10)
ASID (7−0)
Bits compared:
VPN (31−17)
ASID (7−0)
Figure 3.8 Objects of Address Comparison
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Section 3 Memory Management Unit (MMU)
3.3.4
Page Management Information
In addition to the SH and SZ bits, the page management information of TLB entries also includes
D, C, and PR bits.
The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit
is 0, an attempt to write to the page results in an initial page write exception. For physical page
swapping between secondary memory and main memory, for example, pages are controlled so that
a dirty page is paged out of main memory only after that page is written back to secondary
memory. To record that there has been a write to a given page in the address translation table in
memory, an initial page write exception is used.
The C bit in the entry indicates whether the referenced page resides in a cacheable or noncacheable area of memory. When the control register in area 1 is mapped, set the C bit to 0.
The PR field specifies the access rights for the page in privileged and user modes and is used to
protect memory. Attempts at nonpermitted accesses result in TLB protection violation exceptions.
Access states designated by the D, C, and PR bits are shown in table 3.2.
Table 3.2
Access States Designated by D, C, and PR Bits
Privileged Mode
D bit
C bit
PR bit
User Mode
Reading
Writing
Reading
Writing
0
Permitted
Initial page write
exception
Permitted
Initial page write
exception
1
Permitted
Permitted
Permitted
Permitted
0
Permitted
(no caching)
Permitted
(no caching)
Permitted
(no caching)
Permitted
(no caching)
1
Permitted
(with caching)
Permitted
(with caching)
Permitted
(with caching)
Permitted
(with caching)
00
Permitted
TLB protection
violation exception
TLB protection
TLB protection
violation exception violation exception
01
Permitted
Permitted
TLB protection
TLB protection
violation exception violation exception
10
Permitted
TLB protection
violation exception
Permitted
TLB protection
violation exception
11
Permitted
Permitted
Permitted
Permitted
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Section 3 Memory Management Unit (MMU)
3.4
MMU Functions
3.4.1
MMU Hardware Management
There are two kinds of MMU hardware management as follows:
1. The MMU decodes the logical address accessed by a process and performs address translation
by controlling the TLB in accordance with the MMUCR settings.
2. In address translation, the MMU receives page management information and bit information
from the TLB, and determines the MMU exception and whether the cache is to be accessed
(using the C bit). For details of the determination method and the hardware processing, see
section 3.5, MMU Exceptions.
3.4.2
MMU Software Management
There are three kinds of MMU software management, as follows.
1. MMU register setting. MMUCR setting, in particular, should be performed in areas P1 and P2
for which address translation is not performed. Also, since SV and IX bit changes constitute
address translation system changes, in this case, TLB flushing should be performed by
simultaneously writing 1 to the TF bit also. Since MMU exceptions are not generated in the
MMU disabled state with the AT bit cleared to 0, use in the disabled state must be avoided
with software that does not use the MMU.
2. TLB entry recording, deletion, and reading. TLB entry recording can be done in two ways by
using the LDTLB instruction, or by writing directly to the memory-mapped TLB. For TLB
entry deletion and reading, the memory allocation TLB can be accessed. See section 3.4.3,
MMU Instruction (LDTLB), for details of the LDTLB instruction, and section 3.6, MemoryMapped TLB, for details of the memory-mapped TLB.
3. MMU exception handling. When an MMU exception is generated, it is handled on the basis of
information set from the hardware side. See section 3.5, MMU Exceptions, for details.
When single virtual memory mode is used, it is possible to create a state in which physical
memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to
specify recording of all TLB entries. This strengthens inter-process memory protection, and
enables special access levels to be created in the privileged mode only.
Recording a 1-kbyte page TLB entry may result in a synonym problem. See section 3.4.4,
Avoiding Synonym Problems.
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Section 3 Memory Management Unit (MMU)
3.4.3
MMU Instruction (LDTLB)
The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is
0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR
to the value specified by PTEH and PTEL, using VPN bits 16 to 12 specified in PTEH as the
index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16 to 12 specified in
PTEH and ASID bits 4 to 0 in PTEH are used as the index number.
Figure 3.9 shows the case where the IX bit in MMUCR is 0.
When an MMU exception occurs, the virtual page number of the logical address that caused the
exception is set in PTEH by hardware. The way is set in the RC bit of MMUCR for each
exception according to the rules shown in figure 3.9. Consequently, if the LDTLB instruction is
issued after setting only PTEL in the MMU exception handling routine, TLB entry recording is
possible. Any TLB entry can be updated by software rewriting of PTEH and the RC bits in
MMUCR.
As the LDTLB instruction changes address translation information, there is a risk of destroying
address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure,
therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an
access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two
instructions after the LDTLB instruction.
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Section 3 Memory Management Unit (MMU)
MMUCR
31
9
0
0
SV 0 0 RC 0 TF IX AT
Way selection
Index
PTEH register
31
17
VPN
12
10
VPN
8
0
PTEL register
31
10
0
PPN
ASID
0
0 V 0 PR SZ C D SH 0
Write
Write
Ways 0 to 3
0
VPN(31−17)
VPN(11−10)
ASID(7−)
V
PPN(31−10) PR(1−0) SZ C
D SH
31
Address array
Data array
Figure 3.9 Operation of LDTLB Instruction
3.4.4
Avoiding Synonym Problems
When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of
logical addresses are mapped onto a single physical address, the same physical address data will
be recorded in a number of cache entries, and it will not be possible to guarantee data congruity.
The reason why this problem only occurs when using a 1-kbyte page is explained below with
reference to figure 3.10.
To achieve high-speed operation of the SH7727 cache, an index number is created using logical
address bits 11 to 4. When a 4-kbyte page is used, logical address bits 11 to 4 are included in the
offset, and since they are not subject to address translation, they are the same as physical address
bits 11 to 4. In cache-based address comparison and recording in the address array, since the cache
tag address is a physical address, physical address bits 31 to 10 are recorded.
When a 1-kbyte page is used, also, a cache index number is created using logical address bits 11 to
4. However, in case of a 1-kbyte page, logical address bits 11 and 10 are subject to address
translation and therefore may not be the same as physical address bits 11 and 10. Consequently,
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Section 3 Memory Management Unit (MMU)
the physical address is recorded in a different entry from that of the index number indicated by the
physical address in the cache address array.
Note: When multiple address information items use the same physical memory to provide for
future expansion of the SuperH RISC engine family, it is recommended that VPN[20:10]
be made equal. Also, the same physical addresses should not be used with different page
size address conversion information.
For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following
translation has been performed are recorded in two TLBs:
Logical address 1
Logical address 2
H'00000000 →
H'00000C00 →
physical address
physical address
H'00000C00
H'00000C00
Logical address 1 is recorded in cache entry H'00, and logical address 2 in cache entry H'C0. Since
two logical addresses are recorded in different cache entries despite the fact that the physical
addresses are the same, memory inconsistency will occur as soon as a write is performed to either
logical address.
Therefore, when recording a 1-kbyte TLB entry, if the physical address is the same as a physical
address already used in another TLB entry, it should be recorded in such a way that physical
address bits 11 and 10 are the same.
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Section 3 Memory Management Unit (MMU)
When using a 4-kbyte page
Virtual address
0
12 11 10
31
VPN
Offset
Virtual address (11−4)
Physical address
31
12 11 10
PPN
0
Cache address
array
Offset
Physical address (31−10)
When using a 1-kbyte page
Virtual address
11 10 9
31
VPN
0
Offset
Virtual address (11−4)
Physical address
11 10 9
31
PPN
0
Cache address
array
Offset
Physical address (31−10)
Figure 3.10 Synonym Problem
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Section 3 Memory Management Unit (MMU)
3.5
MMU Exceptions
There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial
page write.
3.5.1
TLB Miss Exception
A TLB miss results when the logical address and the address array of the selected TLB entry are
compared and no match is found. TLB miss exception handling includes both hardware and
software operations.
Hardware Operations: In a TLB miss, the SH7727 hardware executes a set of prescribed
operations, as follows:
1. The VPN field of the logical address causing the exception is written to the PTEH register.
2. The logical address causing the exception is written to the TEA register.
3. Either exception code H'040 for a load access, or H'060 for a store access, is written to the
EXPEVT register.
4. The PC value indicating the address of the instruction in which the exception occurred is
written to the save program counter (SPC). If the exception occurred in a delay slot, the PC
value indicating the address of the related delayed branch instruction is written to the SPC.
5. The contents of the status register (SR) at the time of the exception are written to the save
status register (SSR).
6. The mode (MD) bit in SR is set to 1 to place the SH7727 in the privileged mode.
7. The block (BL) bit in SR is set to 1 to mask any further exception requests.
8. The register bank (RB) bit in SR is set to 1.
9. The random counter (RC) field in the MMU control register (MMUCR) is incremented by 1
when all ways are checked for the TLB entry corresponding to the logical address at which the
exception occurred, and all ways are valid. If one or more ways are invalid, those ways are set
in RC in prioritized order from way 0 through way 1, way 2, and way 3.
10. Execution branches to the address obtained by adding the value of the VBR contents and
H'00000400 to invoke the user-written TLB miss exception handler.
Software (TLB Miss Handler) Operations: The software searches the page tables in external
memory and allocates the required page table entry. Upon retrieving the required page table entry,
software must execute the following operations:
1. Write the value of the physical page number (PPN) field and the protection key (PR), page size
(SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry
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Section 3 Memory Management Unit (MMU)
recorded in the address translation table in the external memory into the PTEL register in the
SH7727.
2. If using software for way selection for entry replacement, write the desired value to the RC
field in MMUCR.
3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
4. Issue the return from exception handler (RTE) instruction to terminate the handler routine and
return to the instruction stream. The RTE instruction should be issued after two LDTLB
instructions.
3.5.2
TLB Protection Violation Exception
A TLB protection violation exception results when the logical address and the address array of the
selected TLB entry are compared and a valid entry is found to match, but the type of access is not
permitted by the access rights specified in the PR field. TLB protection violation exception
handling includes both hardware and software operations.
Hardware Operations: In a TLB protection violation exception, the SH7727 hardware executes a
set of prescribed operations, as follows:
1. The VPN field of the logical address causing the exception is written to the PTEH register.
2. The logical address causing the exception is written to the TEA register.
3. Either exception code H'0A0 for a load access, or H'0C0 for a store access, is written to the
EXPEVT register.
4. The PC value indicating the address of the instruction in which the exception occurred is
written into SPC (if the exception occurred in a delay slot, the PC value indicating the address
of the related delayed branch instruction is written into SPC).
5. The contents of SR at the time of the exception are written to SSR.
6. The MD bit in SR is set to 1 to place the SH7727 in the privileged mode.
7. The BL bit in SR is set to 1 to mask any further exception requests.
8. The register bank (RB) bit in SR is set to 1.
9. The way that generated the exception is set in the RC field in MMUCR.
10. Execution branches to the address obtained by adding the value of the VBR contents and
H'00000100 to invoke the TLB protection violation exception handler.
Software (TLB Protection Violation Handler) Operations: Software resolves the TLB
protection violation and issues the RTE (return from exception handler) instruction to terminate
the handler and return to the instruction stream. The RTE instruction should be issued after two
LDTLB instructions.
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Section 3 Memory Management Unit (MMU)
3.5.3
TLB Invalid Exception
A TLB invalid exception results when the logical address is compared to a selected TLB entry
address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception
handling includes both hardware and software operations.
Hardware Operations: In a TLB invalid exception, the SH7727 hardware executes a set of
prescribed operations, as follows:
1. The VPN number of the logical address causing the exception is written to the PTEH register.
2. The logical address causing the exception is written to the TEA register.
3. The way number causing the exception is written to RC in MMUCR.
4. Either exception code H'040 for a load access, or H'060 for a store access, is written to the
EXPEVT register.
5. The PC value indicating the address of the instruction in which the exception occurred is
written to the SPC. If the exception occurred in a delay slot, the PC value indicating the
address of the delayed branch instruction is written to the SPC.
6. The contents of SR at the time of the exception are written into SSR.
7. The mode (MD) bit in SR is set to 1 to place the SH7727 in the privileged mode.
8. The block (BL) bit in SR is set to 1 to mask any further exception requests.
9. The register bank (RB) bit in SR is set to 1.
10. Execution branches to the address obtained by adding the value of the VBR contents and
H'00000100, and the TLB protection violation exception handler starts.
Software (TLB Invalid Exception Handler) Operations: The software searches the page tables
in external memory and assigns the required page table entry. Upon retrieving the required page
table entry, software must execute the following operations:
1. Write the values of the physical page number (PPN) field and the values of the protection key
(PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page
table entry recorded in the external memory to the PTEL register.
2. If using software for way selection for entry replacement, write the desired value to the RC
field in MMUCR.
3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
4. Issue the RTE instruction to terminate the handler and return to the instruction stream. The
RTE instruction should be issued after two LDTLB instructions.
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Section 3 Memory Management Unit (MMU)
3.5.4
Initial Page Write Exception
An initial page write exception results in a write access when the logical address and the address
array of the selected TLB entry are compared and a valid entry with the appropriate access rights
is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to). Initial
page write exception handling includes both hardware and software operations.
Hardware Operations: In an initial page write exception, the SH7727 hardware executes a set of
prescribed operations, as follows:
1. The VPN field of the logical address causing the exception is written to the PTEH register.
2. The logical address causing the exception is written to the TEA register.
3. Exception code H'080 is written to the EXPEVT register.
4. The PC value indicating the address of the instruction in which the exception occurred is
written to the SPC. If the exception occurred in a delay slot, the PC value indicating the
address of the related delayed branch instruction is written to the SPC.
5. The contents of SR at the time of the exception are written to SSR.
6. The MD bit in SR is set to 1 to place the SH7727 in the privileged mode.
7. The BL bit in SR is set to 1 to mask any further exception requests.
8. The register bank (RB) bit in SR is set to 1.
9. The way that caused the exception is set in the RC field in MMUCR.
10. Execution branches to the address obtained by adding the value of the VBR contents and
H'00000100 to invoke the user-written initial page write exception handler.
Software (Initial Page Write Handler) Operations: The software must execute the following
operations:
1. Retrieve the required page table entry from external memory.
2. Set the D bit of the page table entry in the external memory to 1.
3. Write the value of the PPN field and the PR, SZ, C, D, SH, and V bits of the page table entry
in the external memory to the PTEL register.
4. If using software for way selection for entry replacement, write the desired value to the RC
field in MMUCR.
5. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
6. Issue the RTE instruction to terminate the handler and return to the instruction stream. The
RTE instruction should be issued after two LDTLB instructions.
Figure 3.11 shows the flowchart for MMU exceptions.
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Section 3 Memory Management Unit (MMU)
Start
SH = 0
and (MMUCR.SV = 0
or SR.MD = 0)?
No
No
Yes
VPNs match?
VPNs
and ASIDs
match?
No
Yes
Yes
No
V = 1?
TLB miss
exception
TLB invalid
exception
Yes
User mode
Privileged mode
User or
privileged?
PR check
00/01
W
10
R/W?
R
PR check
11
R/W?
01/11
W
W
R
No
R/W?
00/10
W
R/W?
R
R
D = 1?
Yes
TLB protection
violation
exception
Initial page
write
exception
No (noncacheable)
Memory
access
TLB protection
violation
C = 1?
Yes (cacheable)
Cache
access
Figure 3.11 MMU Exception Generation Flowchart
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Section 3 Memory Management Unit (MMU)
3.5.5
Processing Flow in Event of MMU Exception (Same Processing Flow for Address
Error)
MMU Exception in the Instruction Fetch Mode
IF
ID
EX
MA
WB
ID
EX
MA
ID
EX
Handler transition
processing
WB
MA
WB
NOP
NOP
MMU exception handler
IF
ID
EX
MA
WB
: Exception source stage
IF
ID
EX
MA
WB
NOP
= Instruction fetch
= Instruction decode
= Instruction execution
= Memory access
= Write back
= No operation
Figure 3.12 MMU Exception Signals in Instruction Fetch
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Section 3 Memory Management Unit (MMU)
MMU Exception in the Data Access Mode
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
ID
EX
MA
WB
ID
EX
MA
WB
ID
EX
MA WB
Handler transition
processing
NOP
NOP
MMU exception handler
IF
ID
EX
: Exception source stage
: Stage cancellation for instruction
that has begun execution
IF
ID
EX
MA
WB
NOP
= Instruction fetch
= Instruction decode
= Instruction execution
= Memory access
= Write back
= No operation
Figure 3.13 MMU Exception Signals in Data Access
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MA WB
Section 3 Memory Management Unit (MMU)
3.5.6
MMU Exception in Repeat Loop
When MMU exception or CPU address error occurs immediately before or within a repeat loop,
the PC of the instruction that generated the exception can not be saved in SPC correctly and repeat
loop can not be restarted after returning from exception handler. EXPEVT is set to H'070 in cases
of TLB miss, TLB invalid, and CPU address error. EXPEVT is set to H'0D0 in case of TLB
protection violation. Figure 3.14 describes the places where this case occurs.
In a repeat loop of 4 or more instructions, only the last 4 instructions are relevant (see figure 3.14
(4)).
(1) 1 instruction repeated (inst1, SR.RC=2)
inst-1
inst0
inst1
inst1
inst2
IF
ID
IF
EX MA WB
ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
(2) 2 instructions repeated (inst1 and inst2, SR.RC=2)
inst-1
inst0
inst1
inst2
inst1
inst2
inst3
IF
ID
IF
EX MA WB
ID EX MA WB
IF ID EX MA
IF ID EX
IF ID
IF
WB
MA
EX
ID
IF
WB
MA WB
EX MA WB
ID EX MA WB
(3) 3 instructions repeated (inst1, inst2 and inst3, SR.RC=2)
inst-1
inst0
inst1
inst2
inst3
inst1
inst2
inst3
inst4
IF
ID
IF
EX MA WB
ID EX MA WB
IF ID EX MA
IF ID EX
IF ID
IF
WB
MA
EX
ID
IF
WB
MA
EX
ID
IF
WB
MA
EX
ID
IF
WB
MA WB
EX MA WB
ID EX MA WB
: Exception source stage where SPC is not correct
and repeat loop can not be restarted
Figure 3.14 MMU Exception in Repeat Loop
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Section 3 Memory Management Unit (MMU)
(4) 4 or more instructions repeated (inst1, inst2, ..., instN, SR.RC=2)
inst-1 IF
inst0
inst1
inst2
:
instN-3
instN-2
instN-1
instN
inst1
inst2
:
instN-3
instN-2
instN-1
instN
instN+1
ID
IF
EX MA WB
ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
:
IF
ID
IF
EX MA WB
ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
:
IF
ID
IF
EX MA WB
ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
: Exception source stage where SPC is not correct
and repeat loop can not be restarted
Figure 3.14 MMU Exception in Repeat Loop (cont)
3.6
Memory-Mapped TLB
In order for TLB operations to be managed by software, TLB contents can be read or written to in
the privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the logical
address space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F2000000 to
H'F2FFFFFF, and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F3000000 to
H'F3FFFFFF. The V bit in the address array can also be accessed from the data array. Only
longword access is possible for both the address array and the data array.
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Section 3 Memory Management Unit (MMU)
3.6.1
Address Array
The address array is assigned to H'F2000000 to H'F2FFFFFF. To access an address array, the
32-bit address field (for read/write operations) and 32-bit data field (for write operations) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the VPN, V bit and ASID to be written to the address array ((1) in figure 3.15).
In the address field, specify VPN (16 to 12) as the index address for selecting the entry (bits 16 to
12), the W bits for selecting the way (bits 9 and 8), and H'F2 to indicate address array access (bits
31 to 24). The IX bit in MMUCR indicates whether an EX-OR of VPN (16 to 12) and ASID (4 to
0) in the PTEH register is taken as the index address.
When writing, the write is performed to the entry selected with the index address and way.
When reading, the VPN, V bit, and ASID of the entry selected with the index address and way in
the format of the data field in figure 3.12 without comparing addresses. 0 is written to data field
bits 16 to 12.
To invalidate a specific entry, specify the entry and way, and write 0 to the corresponding V bit.
3.6.2
Data Array
The data array is assigned to H'F3000000 to H'F3FFFFFF. To access a data array, the 32-bit
address field (for read/write operations), and 32-bit data field (for write operations) must be
specified. The address section specifies information for selecting the entry to be accessed; the data
section specifies the longword data to be written to the data array ((2) in figure 3.15). Longword
data has the same bit configuration as PTEL.
In the address field, specify VPN (16 to 12) as the index address for selecting the entry (bits 16 to
12), the W bits for selecting the way (bits 9 and 8), and H'F3 to indicate data array access (bits 31
to 24). The IX bit in MMUCR indicates whether an EX-OR of VPN (16 to 12) and ASID (4 to 0)
in the PTEH register is taken as the index address.
Both reading and writing use the longword of the data array specified by the entry address and
way number.
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Section 3 Memory Management Unit (MMU)
(1) TLB Address Array Access
Read access
24 23
31
Address field
11110010
17 16
*
*
17 16
31
Data field
VPN
12 11 10 9 8 7 6
**
VPN
W
0
0
*
*
12 11 10 9 8 7
0
0
0 VPN 0 V
ASID
Write access
31
Address field
24 23
11110010
17 16
*
17 16
31
Data field
VPN
VPN:
V:
W:
12 11 10 9 8 7 6
**
VPN
*
W
0
0
*
*
12 11 10 9 8 7
*
*
VPN * V
0
ASID
Virtual page number
ASID: Address space identifier
Valid bit
*: Don't care bit
Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
(2) TLB Data Array Access
Read/write access
31
Address field
31
Data field
17 16
24 23
11110011
*
29 28
**
W
0
*
10 9 8 7 6 5 4
PPN
000
PPN:
PR:
C:
SH:
VPN:
X:
W:
*
12 11 10 9 8 7
VPN
*
3 2
1
0
X V X PR SZ C D SH X
Physical page number
V: Valid bit
Protection key field
SZ: Page-size bit
Cacheable bit
D: Dirty bit
Share status bit
: Don't care bit
*
Virtual page number
0 for read, don't care bit for write
Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
Figure 3.15 Specifying Address and Data for Memory-Mapped TLB Access
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Section 3 Memory Management Unit (MMU)
3.6.3
Usage Examples
Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s
V bit. R0 specifies the write data and R1 specifies the address.
; R0=H'1547 381C
R1=H'F201 30
; MMUCR.IX=0
; VPN(31–17)=B'0001 0101 0100 011
VPN(11–10)=B'10
ASID=B'0001 1100
; corresponding entry association is made from the entry selected by
; the VPN(16–12)=B'1 0011 index, the V bit of the hit way is cleared to
; 0,achieving invalidation.
MOV.L
R0,@R1
Reading the Data of a Specific Entry: This example reads the data section of a specific TLB
entry. The bit order indicated in the data field in figure 3.15 (2) is read. R0 specifies the address
and the data section of a selected entry is read to R1.
; R1=H'F300 4300
VPN(16-12)=B'00100
Way 3
; MOV.L @R0,R1
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Section 3 Memory Management Unit (MMU)
3.7
Usage Notes
1.
Instructions that manipulate the MD or BL bit in register SR (the LDC Rm, SR instruction,
LDC @Rm+, SR instruction, and RTE instruction) and the following instruction, or the
LDTLB instruction, should be used with the TLB disabled or in a fixed physical address
space (the P1 or P2 space).
2.
The value of the RC bit in MMUCR may be set abnormally if all of the following conditions
are met:
(1) MMU is on (AT is set to 1 in MMUCR).
(2) Identical entries in the TLB address array reference the same VPN using multiple ways.
(3) A TLB related exception occurs.
The VPN is not initialized at power on reset or manual reset. Therefore, identical entries may
access two or more VPNs using the same value. In such cases, certain entries in the TLB
address array may end up as shown below if, for example, they are registered in way 3.
In this case way 0 and way 3 reference the same VPN, thereby satisfying condition (2).
After reset
After registration to way 3
WAY VPN
V
WAY VPN
V
0
12345
0
0
12345
0
3
12345
0
3
12345
1
The above conditions can also be satisfied by TLB handling in software. For example, the
situation shown below could occur if, after invalidating way 0 (by setting V from 1 to 0) for an
entry in the TLB address array, the entry is registered to way 3. In this case as well, the same
VPN is assigned for both way 0 and way 3, thereby satisfying condition (2) above.
After invalidation of way 0
After registration to way 3
WAY VPN
V
WAY VPN
V
0
12345
0
0
12345
0
3
11111
0
3
12345
1
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Section 3 Memory Management Unit (MMU)
Measures to avoid the problem
The following two measures should be taken to avoid the problem described above:
a. After performing a reset and before setting AT to 1 in MMUCR, initialize to 1 the upper
four bits of the VPNs for each entry in the TLB address array.
b. When invalidating an entry in the TLB address array, initialize to 1 the upper four bits of
the corresponding VPN in addition to setting V to 0.
The above measures will ensure that the VPN is not in the area referenced after address
conversion. This will prevent condition (3) from being satisfied and prevent the problem
described above from arising.
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Section 3 Memory Management Unit (MMU)
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Section 4 Exception Handling
Section 4 Exception Handling
4.1
Overview
4.1.1
Features
Exception handling is separate from normal program processing, and is performed by a routine
separate from the normal program. In response to an exception handling request due to abnormal
termination of the executing instruction, control is passed to a user-written exception handler.
However, in response to an interrupt request, normal program execution continues until the end of
the executing instruction. Here, all exceptions other than resets and interrupts will be called
general exceptions. There are thus three types of exceptions: resets, general exceptions, and
interrupts.
4.1.2
Register Configuration
Table 4.1 lists the registers used for exception handling. A register with an undefined initial value
should be initialized by software.
Table 4.1
Register Configuration
Register
Abbr.
R/W
Size
Initial Value
Address
R/W
Longword
Undefined
H'FFFFFFD0
Exception event register
EXPEVT R/W
Longword
Power-on reset: H'000 H'FFFFFFD4
Manual reset: H'020
Interrupt event register
INTEVT
Longword
Undefined
H'FFFFFFD8
Interrupt event register2
INTEVT2 R
Longword
Undefined
H'04000000
(H'A4000000)*
TRAPA exception register TRA
R/W
Note: * When address translation by the MMU does not apply, the address in parentheses should
be used.
4.2
Exception Handling Function
4.2.1
Exception Handling Flow
In exception handling, the contents of the program counter (PC) and status register (SR) are saved
in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of
the exception handler is invoked from a vector address. The return from exception handler (RTE)
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Section 4 Exception Handling
instruction is issued by the exception handler routine at the completion of the routine, restoring the
contents of the PC and SR to return to the processor state at the point of interruption and the
address where the exception occurred.
A basic exception handling sequence consists of the following operations:
1. The contents of the PC and SR are saved in the SPC and SSR, respectively.
2. The block (BL) bit in SR is set to 1, masking any subsequent exceptions.
3. The mode (MD) bit in SR is set to 1 to place the SH7727 in the privileged mode.
4. The register bank (RB) bit in SR is set to 1.
5. An exception code identifying the exception event is written to bits 11 to 0 of the exception
event (EXPEVT) or interrupt event (INTEVT or INTEVT2) register.
6. Instruction execution jumps to the designated exception handling vector address to invoke the
handler routine.
4.2.2
Exception Handling Vector Addresses
The reset vector address is fixed at H'A0000000. The other three events are assigned offsets from
the vector base address by software. Translation look-aside buffer (TLB) miss exceptions have an
offset from the vector base address of H'00000400. The vector address offset for general exception
events other than TLB miss exceptions is H'00000100. The interrupt vector address offset is
H'00000600. The vector base address is loaded into the vector base register (VBR) by software.
The vector base address should reside in P1 or P2 fixed physical address space. Figure 4.1 shows
the relationship between the vector base address, the vector offset, and the vector table.
VBR
+ Vector offset
(Vector base address)
H'A000 0000
Vector address
Figure 4.1 Vector Table
With regard to exceptions and their vector addresses, table 4.2 lists exception type, instruction
completion state, priority, exception order, vector address, and vector offset.
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Section 4 Exception Handling
Table 4.2
Exception Event Vectors
Exception
Type
Current
Instruction
Exception Event
Priority*1
Exception
Order
Vector
Address
Vector Offset
Reset
Aborted
Power-on reset
1
—
H'A0000000
—
Manual reset
1
—
H'A0000000
—
H-UDI reset
1
—
H’A0000000
—
CPU address error
(instruction access)
2
1
—
H'00000100
TLB miss
(instruction access
not in repeat loop)
2
2
—
H'00000400
TLB miss
(instruction access in
repeat loop)*4
2
2
—
H’00000100
TLB invalid
(instruction access)
2
3
—
H'00000100
TLB protection
violation
(instruction access)
2
4
—
H'00000100
General illegal
instruction exception
2
5
—
H'00000100
Illegal slot instruction
exception
2
5
—
H'00000100
CPU address error
(data access)
2
6
—
H'00000100
TLB miss
(data access not in
repeat loop)
2
7
—
H'00000400
TLB miss
2
(data access in repeat
loop)*4
7
—
H'00000100
TLB invalid (data
access)
2
8
—
H'00000100
TLB protection
violation
(data access)
2
9
—
H'00000100
Initial page write
2
10
—
H'00000100
Unconditional trap
(TRAPA instruction)
2
5
—
H'00000100
User breakpoint trap
2
n*2
—
H'00000100
DMA address error
2
12
—
H'00000100
General
exception
events
Aborted
and retried
Completed
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Section 4 Exception Handling
Exception
Type
Current
Instruction
Exception Event
General
interrupt
requests
Completed
Nonmaskable interrupt 3
Priority*1
Exception
Order
Vector
Address
Vector Offset
—
—
H'00000600
External hardware
interrupt
4*3
—
—
H'00000600
H-UDI interrupt
4*3
—
—
H'00000600
Notes: 1. Priorities are indicated from high to low, 1 being highest and 4 being lowest.
2. The user defines the break point traps. 1 is a break point before instruction execution
and 11 is a break point after instruction execution. For an operand break point, use 11.
3. Use software to specify relative priorities of external hardware interrupts and peripheral
module interrupts (see section 7, Interrupt Controller (INTC)).
4. See section 4.5.2, General Exceptions for details.
4.2.3
Acceptance of Exceptions
Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All
exception events are prioritized to establish an acceptance order whenever two or more exception
events occur simultaneously. When a power-on reset and a manual reset occur simultaneously, the
power-on reset has priority.
All general exception events occur in a relative order in the execution sequence of an instruction
(i.e., execution order), but are handled at priority level 2 in instruction-stream order (i.e., program
order), where an exception detected in a preceding instruction is accepted prior to an exception
detected in a subsequent instruction.
Three general exception events (general illegal instruction exception, unconditional trap exception,
and illegal slot instruction exception) are detected in the decode stage (ID stage) of different
instructions and are mutually exclusive events in the instruction pipeline. They have the same
execution priority. Figure 4.2 shows the order of general exception acceptance.
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Section 4 Exception Handling
Pipeline Sequence:
Instruction n
IF
ID
EX
MA
WB
TLB miss (data access)
Instruction n + 1
IF
ID
EX
MA
WB
TLB miss (instruction access)
Instruction n + 2
IF
ID
EX
MA
WB
RIE (reserved instruction exception)
Detection Order:
TLB miss (instruction n+1)
TLB miss (instruction n) and RIE (instruction n + 2) = simultaneous detection
Handling Order:
Program Order:
TLB miss (instruction n)
1
Re-execution of instruction n
TLB miss (instruction n + 1)
2
Re-execution of instruction n + 1
RIE (instruction n + 2)
IF
ID
EX
MA
WB
3
= Instruction fetch
= Instruction decode
= Instruction execution
= Memory access
= Write back
Figure 4.2 Example of Acceptance Order of General Exceptions
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Section 4 Exception Handling
All exceptions other than a reset are detected in the pipeline ID stage, and accepted on instruction
boundaries. However, an exception is not accepted between a delayed branch instruction and the
delay slot. A re-execution type exception detected in a delay slot is accepted before execution of
the delayed branch instruction. A completion type exception detected in a delayed branch
instruction or delay slot is accepted after execution of the delayed branch instruction. The delay
slot here refers to the next instruction after a delayed unconditional branch instruction, or the next
instruction when a delayed conditional branch instruction is true.
4.2.4
Exception Codes
Table 4.3 lists the exception codes written to bits 11 to 0 of the EXPEVT register (for reset or
general exceptions) or the INTEVT and INTEVT2 registers (for general interrupt requests) to
identify each specific exception event. An additional exception register, the TRAPA (TRA)
register, is used to hold the 8-bit immediate data in an unconditional trap (TRAPA instruction).
Table 4.3
Exception Codes
Exception Type
Exception Event
Exception Code
Reset
Power-on reset
H'000
Manual reset
H'020
H-UDI reset
H'000
TLB miss/invalid (read)
H'040
TLB miss/invalid (write)
H'060
TLB miss/invalid/CPU Address error in
repeat loop
H'070
Initial page write
H'080
TLB protection violation (read)
H'0A0
TLB protection violation (write)
H'0C0
TLB protection violation in repeat loop
H'0D0
CPU Address error (read)
H'0E0
CPU Address error (write)
H'100
Unconditional trap (TRAPA instruction)
H'160
Illegal general instruction exception
H'180
Illegal slot instruction exception
H'1A0
User breakpoint trap
H'1E0
DMA address error
H'5C0
General exception events
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Exception Type
Exception Event
Exception Code
General interrupt requests
Nonmaskable interrupt
H'1C0
H-UDI interrupt
H'5E0
External hardware interrupts:
IRL3 to IRL0 = 0000
H'200
IRL3 to IRL0 = 0001
H'220
IRL3 to IRL0 = 0010
H'240
IRL3 to IRL0 = 0011
H'260
IRL3 to IRL0 = 0100
H'280
IRL3 to IRL0 = 0101
H'2A0
IRL3 to IRL0 = 0110
H'2C0
IRL3 to IRL0 = 0111
H'2E0
IRL3 to IRL0 = 1000
H'300
IRL3 to IRL0 = 1001
H'320
IRL3 to IRL0 = 1010
H'340
IRL3 to IRL0 = 1011
H'360
IRL3 to IRL0 = 1100
H'380
IRL3 to IRL0 = 1101
H'3A0
IRL3 to IRL0 = 1110
H'3C0
Note: Exception codes H'120, H'140, and H'3E0 are reserved.
4.2.5
Exception Request Masks
When the BL bit in SR is 0, exceptions and interrupts are accepted.
If a general exception event occurs when the BL bit in SR is 1, the CPU’s internal registers are set
to their post-reset state, other module registers retain their contents prior to the general exception,
and a branch is made to the same address (H'A0000000) as for a reset.
If a general interrupt occurs when BL = 1, the request is masked (held pending) and not accepted
until the BL bit is cleared to 0 by software.
For reentrant exception handling, the SPC and SSR must be saved and the BL bit in SR cleared to
0.
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4.2.6
Returning from Exception Handling
The RTE instruction is used to return from exception handling. When RTE is executed, the SPC
value is set in the PC, and the SSR value in SR, and the return from exception handling is
performed by branching to the SPC address.
If the SPC and SSR have been saved in the external memory, set the BL bit in SR to 1, then
restore the SPC and SSR, and issue an RTE instruction.
4.3
Register Description
There are four registers related to exception handling. These are peripheral module registers, and
therefore reside in area P4. They can be accessed by specifying the address in the privileged mode
only.
1. The exception event register (EXPEVT) resides at address H'FFFFFFD4, and contains a 12-bit
exception code. The exception code set in EXPEVT is that for a reset or general exception
event. The exception code is set automatically by hardware when an exception occurs.
EXPEVT can also be modified by software.
2. Interrupt event register 2 (INTEVT2) resides at address H'04000000, and contains a 12-bit
exception code. The exception code set in INTEVT2 is that for an interrupt request. The
exception code is set automatically by hardware when an exception occurs.
3. The interrupt event register (INTEVT) resides at address H'FFFFFFD8, and contains a 12-bit
interrupt exception code or a code indicating the interrupt priority. Which is set when an
interrupt occurs depends on the interrupt source (see tables 7.4 and 7.5). The exception code or
interrupt priority code is set automatically by hardware when an exception occurs. INTEVT
can also be modified by software.
4. The TRAPA exception register (TRA) resides at address H'FFFFFFD0, and contains 8-bit
immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when
a TRAPA instruction is executed. TRA can also be modified by software.
The bit configurations of the EXPEVT, INTEVT, INTEVT2, and TRA registers are shown in
figure 4.3.
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EXPEVT register, INTEVT and INTEVT2 registers
TRA register
31
0
31
0
0 Exception code
0
0:
Reserved bits, always read as zero
11
9
0
2 0
imm
00
imm: 8-bit immediate data in TRAPA instruction
Figure 4.3 Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers
4.4
Exception Handling Operation
4.4.1
Reset
The reset sequence is used to power up or restart the SH7727 from the initialization state. The
RESETP and RESETM signals are sampled every clock cycle, and in the case of a power-on reset,
all processing being executed (excluding the RTC) is suspended, all unfinished events are
canceled, and reset processing is executed immediately. In the case of a manual reset, however,
processing to retain external memory contents is continued. The reset sequence consists of the
following operations:
1. The MD bit in SR is set to 1 to place the SH7727 in privileged mode.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except NMI interrupt when
BLMSK bit is 1).
3. The RB bit in SR is set to 1.
4. An encoded value of H'000 in a power-on reset or H'020 in a manual reset is written to bits 11
to 0 of the EXPEVT register to identify the exception event.
5. Instruction execution jumps to the user-written exception handler at address H'A0000000.
4.4.2
Interrupts
An interrupt processing request is accepted on completion of the current instruction. The interrupt
acceptance sequence consists of the following operations:
1. The contents of the PC and SR are saved in SPC and SSR, respectively.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except NMI interrupt when
BLMSK bit is 1).
3. The MD bit in SR is set to 1 to place the SH7727 in privileged mode.
4. The RB bit in SR is set to 1.
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5. An encoded value identifying the exception event is written to bits 11 to 0 of the INTEVT and
INTEVT2 registers.
6. Instruction execution jumps to the vector location designated by the sum of the value of the
contents of the vector base register (VBR) and H'00000600 to invoke the exception handler.
4.4.3
General Exceptions
When the SH7727 encounters any exception condition other than a reset or interrupt request, it
executes the following operations:
1. The contents of the PC and SR are saved in the SPC and SSR, respectively.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except NMI interrupt when
BLMSK bit is 1).
3. The MD bit in SR is set to 1 to place the SH7727 in privileged mode.
4. The RB bit in SR is set to 1.
5. An encoded value identifying the exception event is written to bits 11 to 0 of the EXPEVT
register.
6. Instruction execution jumps to the vector location designated by either the sum of the vector
base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the
vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke
the exception handler.
4.5
Individual Exception Operations
This section describes the conditions for specific exception handling, and the processor operations.
4.5.1
Resets
• Power-On Reset
Conditions: RESETP low
Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'00000000. In SR, the MD, RB and BL bits are set
to 1 and the interrupt mask bits (I3 to I0) is set to 1111. The CPU and on-chip supporting
modules are initialized. See the register descriptions in the relevant sections for details. A
power-on reset must always be performed when powering on. A high level is output from
the STATUS0 and STATUS1 pins.
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• Manual Reset
Conditions: RESETM low
Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'00000000. In SR, the MD, RB, and BL bits are set
to 1 and the interrupt mask bits (I3 to I0) is set to 1111. The CPU and on-chip supporting
modules are initialized. See the register descriptions in the relevant sections for details. A
high level is output from the STATUS0 and STATUS1 pins.
• H-UDI Reset
Conditions: H-UDI reset command input (see section 31.4.3, H-UDI Reset)
Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the interrupt mask bits (I3 to I0) is set to 1111. The CPU and on-chip supporting
modules are initialized. See the register descriptions in the relevant sections for details.
Table 4.4
Types of Reset
Internal State
Conditions for Transition
to Reset State
CPU
On-Chip Supporting Modules
Power-on
reset
RESETP = Low
Initialized
(See register configuration in
relevant sections)
Manual
reset
RESETM = Low
Initialized
H-UDI
reset
H-UDI reset command input
Initialized
Type
4.5.2
General Exceptions
• TLB miss exception
Conditions: Comparison of TLB addresses shows no address match
Operations: The logical address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The RC bit in MMUCR is
incremented by 1 when all ways are enabled, and if there is a disabled way, setting is
prioritized starting from way 0.
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception
occurred during a write, H'060 is set in EXPEVT. The BL, MD and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0400.
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To speed up TLB miss processing, the offset differs from other exceptions.
• TLB invalid exception
Conditions: Comparison of TLB addresses shows address match but V = 0.
Operations: The logical address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
The PC and SR of the instruction that generated the exception are saved in the SPC and SSR,
respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception
occurred during a write, H'060 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100.
• TLB exception/CPU address error in repeat loop
Conditions: TLB miss, TLB invalid or CPU address error in the last several instructions of
repeat loop (see section 3.5.6, MMU Exception in Repeat Loop)
Operations: TEA, PTEH and RC bit in MMUCR are set in the way of the type of
exception.
The SR of the instruction that generated the exception are saved in the SSR. But the SPC is not
the PC of the instruction that generated the exception. Repeat loop can not be restarted after
returning from exception handler. In order to complete a repeat loop, ensure not to cause TLB
exceptions or CPU address error in the last several instructions of repeat loop (see section
3.5.6, MMU Exception in Repeat Loop). If the TLB exception or CPU address error occurred
in the last several instructions of repeat loop, H'070 is set in EXPEVT. The BL, MD, and RB
bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
• Initial page write exception
Conditions: A hit occurred to the TLB for a store access, but D = 0.
This occurs for initial writes to the page registered by the load.
Operations: The logical address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bit in MMUCR.
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a
branch occurs in PC = VBR + H'0100.
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• TLB protection exception
Conditions: When a hit access violates the TLB protection information (PR bits) shown
below:
PR
Privileged mode
User mode
00
Only read enabled
No access
01
Read/write enabled
No access
10
Only read enabled
Only read enabled
11
Read/write enabled
Read/write enabled
Operations: The logical address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. If the exception occurred during a read, H'0A0 is set in EXPEVT; if the exception
occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100.
• TLB protection violation in repeat loop
Conditions: TLB protection violation in the last several instruction of repeat loop (see
section 3.5.6, MMU Exception in Repeat Loop)
Operations: TEA, PTEH and RC bit in MMUCR are set in the way of the type of
exception.
The SR of the instruction that generated the exception are saved in the SSR. But the SPC is not
the PC of the instruction that generated the exception. Repeat loop can not be restarted after
returning from exception handler. In order to complete a repeat loop, ensure not to cause TLB
exceptions or CPU address error in the last several instructions of repeat loop (see section
3.5.6, MMU Exception in Repeat Loop). If a TLB protection violation occurs in an instruction
immediately before or during a repeat loop, H'0D0 is set in EXPEVT. The BL, MD, and RB
bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
• CPU Address error
Conditions:
a. Instruction fetch from odd address (4n + 1, 4n + 3)
b. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
c. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
4n + 3)
d. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF.
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Operations: The logical address (32 bits) that caused the exception is set in TEA. The PC
and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. If the exception occurred during a read, H'0E0 is set in EXPEVT; if the
exception occurred during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in
SR are set to 1 and a branch occurs to PC = VBR + H'0100. See section 3.5.5, Processing
Flow in Event of MMU Exception, for more information.
• Unconditional trap
Conditions: TRAPA instruction executed
Operations: The exception is a processing-completion type, so the PC of the instruction
after the TRAPA instruction is saved to the SPC. SR from the time when the TRAPA
instruction was executing is saved to SSR. The 8-bit immediate value in the TRAPA
instruction is quadrupled and set in TRA (9 to 0). H'160 is set in EXPEVT. The BL, MD,
and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
• Illegal general instruction exception
Conditions:
a. When undefined code not in a delay slot is decoded
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,
BF/S
Undefined instruction: H'Fxxx
b. When a privileged instruction not in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access
GBR with LDC/STC are not privileged instructions.
c. When a DSP instruction not in a delay slot is decoded without DSP extension
(SR.DSP=0)
DSP instructions: LDS Rm, DSR/A0/X0/X1/Y0/Y1, LDS.L @Rm+,
DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1, Rn, STS.L
DSR/A0/X0/X1/Y0/Y1, @-Rn, LDC Rm, RS/RE/MOD, LDC.L @Rm+, RS/RE/MOD,
STC RS/RE/MOD, Rn, STC.L RS/RE/MOD, @-Rn, LDRS, LDRE, SETRC, MOVS,
MOVX, MOVY, Pxxx
d. When an instruction that rewrites the PC/SR/RS/RE in the last three instructions of
repeat loop is decoded.
Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE,
BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR,
LDC.L @Rm+, SR
Instructions that rewrite the SR: LDC Rm, SR, LDC.L @Rm+, SR, SETRC
Instructions that rewrite the RS: LDC Rm, RS, LDC.L @Rm+, RS, LDRS
Instructions that rewrite the RE: LDC Rm, RE, LDC.L @Rm+, RE, LDRE
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Operations: The PC and SR of the instruction that generated the exception are saved to the
SPC and SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction other
than H'Fxxx is decoded, operation cannot be guaranteed.
• Illegal slot instruction
Conditions:
a. When undefined code in a delay slot is decoded
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,
BF/S, Undefined instruction: H'Fxxx
b. When an instruction that rewrites the PC in a delay slot is decoded
Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT,
BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
c. When a privileged instruction in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access
GBR with LDC/STC are not privileged instructions.
d. When a DSP instruction in a delay slot is decoded without DSP extension (SR.DSP=0)
DSP instructions: LDS Rm, DSR/A0/X0/X1/Y0/Y1, LDS.L @Rm+,
DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1, Rn, STS.L
DSR/A0/X0/X1/Y0/Y1, @-Rn, LDC Rm, RS/RE/MOD, LDC.L @Rm+, RS/RE/MOD,
STC RS/RE/MOD, Rn, STC.L RS/RE/MOD, @-Rn, LDRS, LDRE, SETRC, MOVS,
MOVX, MOVY, Pxxx
Operations: The PC of the previous delay branch instruction is saved to the SPC. SR of the
instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The BL,
MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. When an
undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed.
• User break point trap
Conditions: When a break condition set in the user break controller is satisfied
Operations: When a post-execution break occurs, the PC of the instruction immediately
after the instruction that set the break point is set in the SPC. If a pre-execution break
occurs, the PC of the instruction that set the break point is set in the SPC. SR when the
break occurs is set in SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to PC = VBR + H'0100. See section 8, User Break Controller
(UBC), for more information.
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• DMA Address error
Conditions:
a. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
b. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
4n + 3)
Operations: The PC of the instruction immediately after the instruction executed before the
exception occurs is saved to the SPC. SR when the exception occurs is saved to SSR.
H'5C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs
to PC = VBR + H'0100.
4.5.3
Interrupts
1. NMI
Conditions: NMI pin edge detection
Operations: The PC and SR after the instruction that receives the interrupt are saved to the SPC
and SSR, respectively. H'1C0 is set to INTEVT and INTEVT2. The BL, MD, and RB bits of
the SR are set to 1 and a branch occurs to PC = VBR + H'0600. This interrupt is not masked by
SR.IMASK and received with top priority when the SR’s BL bit in SR is 0. When the BL bit is
1, the interrupt is masked. See section 7, Interrupt Controller (INTC), for more information.
2. IRL Interrupts
Conditions: The value of the interrupt mask bits in SR is lower than the IRL3 to IRL0 level
and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC value after the instruction at which the interrupt is accepted is saved to the
SPC. SR at the time the interrupt is accepted is saved to SSR. The code corresponding to the
IRL3 to IRL0 level is set in INTEVT and INTEVT2. The corresponding code is given as
H'200 + [IRL3 to IRL0] × H'20. See table 7.5, for the corresponding codes. The BL, MD, and
RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not set
in SR.IMASK. See section 7, Interrupt Controller (INTC), for more information.
3. IRQ Pin Interrupts
Conditions: IRQ pin is asserted and SR.IMASK is lower than the IRQ priority level and the
BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC value after the instruction at which the interrupt is accepted is saved to the
SPC. The SR at the point the interrupt is accepted is saved to the SSR. The code corresponding
to the interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR
are set to 1 and a branch occurs to VBR + H'0600. The received level is not set to SR.IMASK.
See section 7, Interrupt Controller (INTC), for more information.
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4. PINT Pin Interrupts
Conditions: The PINT pin is asserted and SR.IMASK is lower than the PINT priority level and
the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC value after the instruction at which the interrupt is accepted is saved to the
SPC. The SR at the point the interrupt is accepted is saved to the SSR. The code corresponding
to the interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR
are set to 1 and a branch occurs to VBR + H'0600. The received level is not set to SR.IMASK.
See section 7, Interrupt Controller (INTC), for more information.
5. On-Chip Peripheral Interrupts
Conditions: SR.IMASK is lower than the on-chip module (TMU, RTC, SCI, SIOF, SCIF, A/D,
DMAC, CPG, REF, PCC, USBH, USBF, LCDC, AFEIF) interrupt level and the BL bit in SR
is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC value after the instruction at which the interrupt is accepted is saved to the
SPC. The SR at the point the interrupt is accepted is saved to the SSR. The code corresponding
to the interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR
are set to 1 and a branch occurs to VBR + H'0600. See section 7, Interrupt Controller (INTC),
for more information.
6. H-UDI Interrupt
Conditions: H-UDI interrupt command is input (see section 31.4.4, H-UDI Interrupt), the value
of the interrupt mask bits of SR is lower than 15, and the BL bit in SR is 0, the interrupt is
accepted at an instruction boundary.
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The SR
at the point the interrupt is accepted is saved to the SSR. H'5E0 is set to INTEVT and
INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to VBR +
H'0600. See section 7, Interrupt Controller (INTC), for more information.
4.6
Usage Notes
• Return from exception handling
Check the BL bit in SR with software. When the SPC and SSR have been saved to external
memory, set the BL bit in SR to 1 before restoring them.
Issue an RTE instruction. Set the SPC in the PC and SSR in SR with the RTE instruction,
branch to the SPC address, and return from exception handling.
• Operation when exception or interrupt occurs while SR.BL = 1
Interrupt: Acceptance is suppressed until the BL bit in SR is set to 0 by software. If there is
a request and the reception conditions are satisfied, the interrupt is accepted after the
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Section 4 Exception Handling
execution of the instruction that sets the BL bit in SR to 0. During the sleep or standby
mode, however, the interrupt will be accepted even when the BL bit in SR is 1.
NMI is accepted when BLMSK in ICR1 is 1, regardless of the setting of the BL bit.
Exception: No user break point trap will occur even when the break conditions are met.
When one of the other exceptions occurs, a branch is made to the fixed address of the reset
(H'A0000000). In this case, the values of the EXPEVT, SPC, and SSR registers are
undefined.
• SPC when an Exception Occurs: The PC saved to the SPC when an exception occurs is as
shown below:
Re-executing-type exceptions: The PC of the instruction that caused the exception is set in
the SPC and re-executed after return from exception handling. If the exception occurred in
a delay slot, however, the PC of the immediately prior delayed branch instruction is set in
the SPC. If the condition of the conditional delayed branch instruction is not satisfied, the
delay slot PC is set in SPC.
Completed-type exceptions and interrupts: The PC of the instruction after the one that
caused the exception is set in the SPC. If the exception was caused by a delayed
conditional branch instruction, however, the branch destination PC is set in SPC. If the
condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is
set in SPC.
• Initial register values after reset
Undefined registers
R0_BANK0/1 to R7_BANK0/1, R8 to R15, GBR, SPC, SSR, MACH, MACL, PR
Initialized registers
VBR = H'00000000
SR.MD = 1, SR.BL = 1, SR.RB = 1, SR.I3 to SR.I0 = H'F. Other SR bits are undefined.
PC = H'A0000000
• Ensure that an exception is not generated at an RTE instruction delay slot, as operation is not
guaranteed in this case.
• When the BL bit in the SR register is set to 1, ensure that a TLB-related exception or address
error does not occur at an LDC instruction that updates the SR register and the following
instruction. This occurrence will be identified as multiple exceptions, and may initiate reset
processing.
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Section 5 Cache
Section 5 Cache
5.1
Overview
5.1.1
Features
The cache specifications are listed in table 5.1.
Table 5.1
Cache Specifications
Parameter
Specification
Capacity
16 kbytes
Structure
Instruction/data mixed, 4-way set associative
Locking
Way 2 and way 3 are lockable
Line size
16 bytes
Number of entries
256 entries/way
Write system
P0, P1, P3, U0: Write-back/write-through selectable
Replacement method
Least-recently-used (LRU) algorithm
5.1.2
Cache Structure
The cache mixes data and instructions and uses a 4-way set associative system. It is composed of
four ways (banks), each of which is divided into an address section and a data section. Each of the
address and data sections is divided into 256 entries. The data section of the entry is called a line.
Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 4 kbytes (16 bytes × 256
entries), with a total of 16 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache
structure.
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Section 5 Cache
Address array (ways 0 to 3)
Entry 0 V U Tag address
Entry 1
Data array (ways 0 to 3)
0
LW0
LW1
LW2
LW3
LRU
0
1
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Entry 255
255
255
128 (32 × 4) bits
24 (1 + 1 + 22) bits
6 bits
LW0−LW3: Longword data 0 to 3
Figure 5.1 Cache Structure
Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is
valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in writeback mode. When the U bit is 1, the entry has been written to; when 0, it has not. The address tag
holds the physical address used in the external memory access. It is composed of 22 bits (address
bits 31 to 10) used for comparison during cache searches.
In the SH7727, the top three of 32 physical address bits are used as shadow bits (see section 12,
Bus State Controller (BSC)), and therefore in a normal replace operation the top three bits of the
tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
The tag address is not initialized by either a power-on or manual reset.
Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units
(16 bytes). The data array is not initialized by a power-on or manual reset.
LRU: With the 4-way set associative system, up to four instructions or data with the same entry
address (address bits 11 to 4) can be registered in the cache. When an entry is registered, the LRU
shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A
least-recently-used (LRU) algorithm is used to select the way.
In normal operation, four ways are used as cache and six LRU bits indicate the way to be replaced
(table 5.2). If a bit pattern other than those listed in table 5.2 is set in the LRU bits by software, the
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Section 5 Cache
cache will not function correctly. When modifying the LRU bits by software, set one of the
patterns listed in table 5.2.
The LRU bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
Table 5.2
LRU and Way Replacement
LRU (5–0)
Way to be Replaced
000000, 000100, 010100, 100000, 110000, 110100
3
000001, 000011, 001011, 100001, 101001, 101011
2
000110, 000111, 001111, 010110, 011110, 011111
1
111000, 111001, 111011, 111100, 111110, 111111
0
5.1.3
Register Configuration
Table 5.3 shows details of the cache control register.
Table 5.3
Register Configuration
Register
Abbr.
R/W
Size
Initial Value
Address
Cache control register
CCR
R/W
Longword
H'00000000
H'FFFFFFEC
Cache control register 2
CCR2
W
Longword
H’00000000
H'040000B0
(H'A40000B0)*
Note: * When address translation by the MMU does not apply, the address in parentheses should
be used.
5.2
Register Description
5.2.1
Cache Control Register (CCR)
The cache is enabled or disabled using the CE bit of the cache control register (CCR). CCR also
has a CF bit (which invalidates all cache entries), and a WT and CB bits (which select either writethrough mode or write-back mode). Programs that change the contents of the CCR register should
be placed in address space that is not cached. Figure 5.2 shows the configuration of the CCR
register.
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Section 5 Cache
31
…
…
…
…
…
…
…
…
6
5
4
3
2
1
0
CF
CB
WT
CE
:
Reserved bits. These bits are always read as 0. The write value should always be 0.
CF:
Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all
cache entries to 0). Always reads 0. Write-back to external memory is not performed when
the cache is flushed.
WT:
Write-through bit. Indicates the cache's operating mode for areas P0, U0 and P3.
1 = write-through mode, 0 = write-back mode.
CE:
Cache enable bit. Indicates whether the cache function is used.
1 = cache used, 0 = cache not used.
CB:
Cache write-back bit. Indicates the cache's operating mode for area P1.
1 = write-back mode, 0 = write-through mode.
Figure 5.2 CCR Register Configuration
5.2.2
Cache Control Register 2 (CCR2)
CCR2 register is used to enable or disable cache locking mechanism during DSP mode (CPU
status register bit 12) only. Executing a prefetch instruction (PREF) during DSP mode will bring
in one line size of data pointed by Rn to cache, according to the setting of CCR2 [9:8] (W3LOAD,
W3LOCK) and [1:0] (W2LOAD, W2LOCK):
When CCR2[9:8]=11, during DSP mode PREF @Rn will bring the data into way 3. When
CCR2[9:8]=00, 01 or 10 during DSP mode, or any setting during non-DSP mode, PREF @Rn will
place the data into the way pointed by LRU.
When CCR2[1:0]=11, during DSP mode PREF @Rn will bring the data into way 2. When
CCR2[1:0]=00, 01 or 10 during DSP mode, or any setting during non-DSP mode, PREF @Rn will
place the data into the way pointed by LRU.
CCR2 must be set before cache is enabled.
When a PREF instruction is issued and there is a cache hit, the operation is treated as NOP.
Figure 5.3 shows the configuration of the CCR2 register.
The CCR2 register is a write-only register. If read, an undefined value will be returned.
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Section 5 Cache
31
9
8
7
2
W3
W3
LOAD LOCK
1
0
W2 W2
LOAD LOCK
W2LOCK: Way 2 lock bit. W2LOAD: Way 2 load bit.
When W2LOCK = 1 & W2LOAD = 1 & DSP = 1, the prefetched data will always be loaded
into Way2. In all other conditions the prefetched data will be loaded into the way pointed by
LRU.
W3LOCK: Way 3 lock bit. W3LOAD: Way 3 load bit.
When W3LOCK = 1 & W3LOAD = 1 & DSP = 1, the prefetched data will always be loaded
into Way3. In all other conditions the prefetched data will be loaded into the way pointed by
LRU.
Note: W2LOAD and W3LOAD should not be set to high at the same time.
Figure 5.3 CCR2 Register Configuration
Whenever CCR2 bit 8 (W3LOCK) or bit 0 (W2LOCK) is high the cache is locked. The locked
data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF
condition during DSP mode matched. During cache locking mode, the LRU in table 5.2 will be
replaced by tables 5.4 to 5.6.
Table 5.4
LRU and Way Replacement (when W2LOCK=1)
LRU (5–0)
Way to be Replaced
000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100
3
000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111
1
101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111
0
Table 5.5
LRU and Way Replacement (when W3LOCK=1)
LRU (5–0)
Way to be Replaced
000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011
2
000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111
1
110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111
0
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Section 5 Cache
Table 5.6
LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)
LRU (5–0)
Way to be Replaced
000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111,
010100, 010110, 011110, 011111
1
100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001,
111011, 111100, 111110, 111111
0
5.3
Cache Operation
5.3.1
Searching the Cache
If the cache is enabled, whenever instructions or data in memory are accessed the cache will be
searched to see if the desired instruction or data is in the cache. Figure 5.4 illustrates the method
by which the cache is searched. The cache is a physical cache and holds physical addresses in its
address section.
Entries are selected using bits 11 to 4 of the address (virtual) of the access to memory and the
address tag of that entry is read. In parallel to reading of the address tag, the logical address is
translated to a physical address in the MMU. The physical address after translation and the
physical address read from the address section are compared. The address comparison uses all four
ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit
occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a
cache miss occurs. Figure 5.4 shows a hit on way 1.
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Section 5 Cache
Virtual address
31
12 11
4 3 21 0
Entry selection
Longword (LW) selection
Ways 0 to 3
Ways 0 to 3
0
1
MMU
V U Tag address
LW0
LW1
LW2
LW3
255
Physical address
CMP0 CMP1 CMP2 CMP3
Hit signal 1
CMP0: Comparison circuit 0
CMP1: Comparison circuit 1
CMP2: Comparison circuit 2
CMP3: Comparison circuit 3
Figure 5.4 Cache Search Scheme
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Section 5 Cache
5.3.2
Read Access
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The
LRU is updated.
Read Miss: An external bus cycle starts and the entry is updated. The way replaced is the one
least recently used. Entries are updated in 16-byte units. When the desired instruction or data that
caused the miss is loaded from external memory to the cache, the instruction or data is transferred
to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the U bit is
cleared to 0 and the V bit is set to 1. In the write-back mode, when the U bit of the entry to be
replaced is 1, the cache update cycle starts after the entry is transferred to the write-back buffer.
After the cache completes its update cycle, the write-back buffer writes back the entry to the
memory. The write-back unit is 16 bytes.
5.3.3
Prefetch Operations
Prefetch Hit: The LRU is updated so that the hit way becomes the most recent. Other cache
contents are not updated. Instruction or data transfer to the CPU is not performed.
Prefetch Miss: Instruction or data transfer to the CPU is not performed, and the way replaced is as
shown in table 5.2, table 5.4, table 5.5, and table 5.6. Other operations are the same as in the case
of a read miss.
5.3.4
Write Access
Write Hit: In a write access in the write-back mode, the data is written to the cache and the U bit
of the entry written is set to 1. Writing occurs only to the cache; no external memory write cycle is
issued. In the write-through mode, the data is written to the cache and an external memory write
cycle is issued.
Write Miss: In the write-back mode, an external write cycle starts when a write miss occurs, and
the entry is updated. The way to be replaced is the one least recently used. When the U bit of the
entry to be replaced is 1, the cache update cycle starts after the entry is transferred to the writeback buffer. The write-back unit is 16 bytes. Data is written to the cache and the U bit is set to 1
and the V bit is also set to 1. After the cache completes its update cycle, the write-back buffer
writes back the entry to the memory. In the write-through mode, no write to cache occurs in a
write miss; the write is only to the external memory.
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Section 5 Cache
5.3.5
Write-Back Buffer
When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to
the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. During the write back cycles, the cache can be accessed. The write-back buffer
can hold one line of the cache data (16 bytes) and its physical address. Figure 5.5 shows the
configuration of the write-back buffer.
PA (31 to 4)
Longword 0
Longword 1
Longword 2
Longword 3
PA (31 to 4):
Physical address written to external memory
Longword 0 to 3: The line of cache data to be written to
external memory
Figure 5.5 Write-Back Buffer Configuration
5.3.6
Coherency of Cache and External Memory
Use software to ensure coherency between the cache and the external memory. When memory
shared by this LSI and another device is accessed, the latest data may be in a write-back mode
cache, so invalidate the entry that includes the latest data in the cache, generate a write back, and
update the data in memory before using it. When the caching area is updated by a device other
than the SH7727, invalidate the entry that includes the updated data in the cache.
5.4
Memory-Mapped Cache
To allow software management of the cache, cache contents can be read and written by means of
MOV instructions in the privileged mode. The cache is mapped onto the P4 area in logical address
space. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data
array onto addresses H'F1000000 to H'F1FFFFFF. Only longword can be used as the access size
for the address array and data array, and instruction fetches cannot be performed.
5.4.1
Address Array
The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the
32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
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Section 5 Cache
field specifies the address, V bit, U bit, and LRU bits to be written to the address array ((1) in
figure 5.6).
In the address field, specify the entry address selecting the entry (bits 11 to 4), W for selecting the
way (bits 12 and 11: in normal mode (8-kbyte cache), 00 is way 0, 01 is way 1, 10 is way 2, and
11 is way 3), and H'F0 to indicate address array access (bits 31 to 24).
When writing, specify bit 3 as the A bit. The A bit indicates whether addresses are compared
during writing. When the A bit is 1, the addresses of four entries selected by the entry addresses
are compared to the addresses to be written into the address array specified in the data field.
Writing takes place to the way that has a hit. When a miss occurs, nothing is written to the address
array and no operation occurs. The way number (W) specified in bits 12 and 11 is not used. When
the A bit is 0, it is written to the entry selected with the entry address and way number without
comparing addresses. The address specified by bits 31 to 10 in the data specification in figure 5.6
(1), address array access, is a logical address. When the MMU is enabled, the address is translated
into a physical address, then the physical address is used in comparing addresses when the A bit is
1. The physical address is written into the address array.
When reading, the address tag, V bit, U bit, and LRU bits of the entry specified by the entry
address and way number (W) are read using the data format shown in figure 5.6 without
comparing addresses. To invalidate a specific entry, specify the entry by its entry address and way
number, and write 0 to its V bit. To invalidate only an entry for an address to be invalidated,
specify 1 for the A bit.
When an entry for which 0 is written to the V bit has a U bit set to 1, it will be written back. This
allows coherency to be achieved between the external memory and cache by invalidating the
entry. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry.
In the SH7727, the upper 3 bits of the 32-bit physical address are treated as a shadow field (see
section 12, Bus State Controller (BSC)). Therefore, when a cache miss occurs, 0 is stored in the
upper 3 bits of the address array address tag.
When using an MOV instruction to modify the address array directly, a nonzero value must not be
written to the upper 3 bits of the address tag.
5.4.2
Data Array
The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit
address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified.
The address field specifies information for selecting the entry to be accessed; the data field
specifies the longword data to be written to the data array ((2) in figure 5.6).
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Section 5 Cache
Specify the entry address for selecting the entry (bits 11 to 4), L indicating the longword position
within the (16-byte) line (bits 3 and 2: 00 is longword 0, 01 is longword 1, 10 is longword 2, and
11 is longword 3), W for selecting the way (bits 12 and 11: in normal mode, 00 is way 0, 01 is
way 1, 10 is way 2, and 11 is way 3), and H'F1 to indicate data array access (bits 31 to 24).
Both reading and writing use the longword of the data array specified by the entry address, way
number and longword address. The access size of the data array is fixed at longword.
1. Address array access
Address specification
Read access
31
24
23
14
13
*…………*
1111 0000
12
11
W
4
Entry
3
2
0
*
3
2
A
*
0
0
0
Write access
31
24
23
14
13
*…………*
1111 0000
12
11
W
4
Entry
0
0
0
Data specification
31 30 29
10
0 0 0
Address tag (31−10)
9
4
3
LRU
X
2
1
0
X
U
V
2. Data array access (both read and write accesses)
Address specification
31
24
1111 0001
23
14
*…………*
13
12
W
11
4
Entry
3
2
L
1
0
0
0
Data specification
31
0
Longword
X: 0 for read, don't care for write
*: Don't care bit
Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access
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Section 5 Cache
5.5
Usage Examples
5.5.1
Invalidating Specific Entries
Specific cache entries can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the
address tag specified by the write data is compared to the address tag within the cache selected by
the entry address, and data is written when a match is found. If no match is found, there is no
operation. R0 specifies the write data in R0 and R1 specifies the address. When the V bit of an
entry in the address array is set to 0, the entry is written back if the entry’s U bit is 1.
; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0
; R1=H'F0000088; address array access, entry=B'00001000, A=1
;
MOV.L R0,@R1
5.5.2
Reading the Data of a Specific Entry
This example reads the data section of a specific cache entry. The longword indicated in the data
field of the data array in figure 5.6 is read to the register. R0 specifies the address and R1 is read.
; R1=H'F100 004C; data array access, entry=B'00000100, Way = 0,
; longword address = 3
;
MOV.L @R0,R1 ; Longword 3 is read.
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Section 6 X/Y Memory
Section 6 X/Y Memory
6.1
Overview
The SH7727 has on-chip X-RAM and Y-RAM. It can be used by CPU, DSP and DMAC to store
instructions or data.
6.1.1
Features
The X/Y Memory features are listed in table 6.1.
Table 6.1
X/Y Memory Specifications
Parameter
Features
Addressing
method
User selectable mapping mechanism
Ports
Size
•
Fixed mapping for mission-critical realtime applications (P2/Uxy area)
•
Automatic mapping through TLB for easy to use (P0/P3/U0 area)
3 independent read/write ports
•
8-/16-/32-bit access from the CPU
•
Maximum of two simultaneous 16-bit accesses, or 16/32-bit accesses,
from the DSP
•
8-/16-/32-bit access from the DMAC
8-kbyte RAM for X and Y memory each
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Section 6 X/Y Memory
6.2
X/Y Memory Access from the CPU
The X/Y memory can be located in either map-enabled area or fixed-mapped area, depending on
the mode bit (MD) and DSP bit (DSP) setting in the status register (SR). Figure 6.1 shows X/Y
memory logical mapping.
1. Privileged Mode
MD = 1, DSP = 0; Any physical address in space P0 or P3 can map to X/Y memory through
TLB translation. Addresses ranging from H'A500 0000 to H'A5FF FFFF in the P2 space can
also fixed map to X/Y memory. Since the DSP extension is disabled, the DSP instruction set
and registers are not available to the programmer.
2. User Mode
MD = 0, DSP = 0; Any physical address in the U0 space can access X/Y memory through TLB
translation. Any access to addresses beyond the U0 space will cause an address error. Since the
DSP extension is disabled, the DSP instruction set and registers are not available to the
programmer.
3. Privileged-DSP Mode
MD = 1, DSP = 1; Any physical address in space P0 or P3 can map to X/Y memory through
TLB translation. Addresses ranging from H'A500 0000 to H'A5FF FFFF in the P2 space can
also fixed-map to X/Y memory. Since the DSP extension is enabled, the DSP instruction set
and registers are available to the programmer.
4. User-DSP Mode
MD = 0, DSP = 1; Any physical address in space U0 can map to X/Y memory through TLB
translation. Addresses ranging from H'A500 0000 to H'A5FF FFFF in the Uxy spaces can also
fixed map to X/Y memory. Any access to outside of U0 and Uxy space will cause an address
error. Since the DSP extension is enabled, the DSP instruction set and registers are available to
the programmer.
It is recommended that for the mappable area, the C (cacheable) bit in the TLB entry must be set
to 0 to guarantee a two-cycle access.
Mapping through TLB translation provides a flexible X/Y memory addressing scheme but takes
two cycles even when the C bit in the TLB entry is cleared to 0. Fixed mapping provides a onecycle access for read and two-cycle access for write, which is the appropriate method for missioncritical realtime operations.
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Section 6 X/Y Memory
The X/Y memory resides on the second 16 MB of physical address space area 1, from H'A500
0000 to H'A5FF FFFF. These 16-MB address spaces are shadowed and maps to the same 128kbyte X/Y ROM/RAM. Figures 6.1 and 6.2 show X/Y memory physical mapping.
MD = 1, DSP = 0
MD = 0, DSP = 0
Privileged mode
User mode
Same as SH-3
In MD = 1, CPU can
change DSP bit
P0
Same as SH-3
In MD = 0, user cannot
change DSP bit
U0
P1
P2
Address error
P3
P4
MD = 1, DSP = 1
MD = 0, DSP = 1
Privileged DSP mode
P0
User DSP mode
In MD = 1, CPU can
change DSP bit
X
P3
X
Y
Y
Address error
P1
P2
U0
Address range
From H'A500 0000
To H'A5FF FFFF
Address error
Uxy: Address range
From H'A500 0000
To H'A5FF FFFF
P4
Figure 6.1 X/Y Memory Logical Address Mapping
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Section 6 X/Y Memory
Area 1, 64 Mbytes
128-kbyte X/Y Memory
4000000
A5000000
X-ROM/X-RAM
Reserved space
I/O register space
16 Mbytes
A5007000
5000000
5020000
X/Y Memory
A5008FFF
Reserved
space
16 Mbytes
X-RAM, 8 kbytes
X-ROM/X-RAM
Reserved space
6000000
A5010000
Y-ROM/Y-RAM
Reserved space
Reserved area
32 Mbytes
A5017000
A5018FFF
Y-RAM, 8 kbytes
Y-ROM/Y-RAM
Reserved space
7FFFFFF
A501FFFF
Figure 6.2 X/Y Memory Physical Address Mapping
6.3
X/Y Memory Access from the DSP
The X/Y memory can be accessed by the DSP through the X bus and Y bus. Accesses via the X
bus/Y bus are always 16-bit, while accesses via the L bus are either 16-bit or 32-bit. Accesses via
the X bus and Y bus cannot be specified simultaneously.
6.4
X/Y Memory Access from the DMAC
The X/Y memory also exists on the I bus and can be accessed by the DMAC. The DMAC access
is 8-/16-/32-bit unit. If the I bus accesses X/Y memory simultaneously with an access from X
bus/Y bus or L bus, the I bus master has a higher priority.
To access the X/Y memory by the DMAC, the physical address from H’05000000 to H’0501FFFF
should be used.
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Section 7 Interrupt Controller (INTC)
Section 7 Interrupt Controller (INTC)
7.1
Overview
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
7.1.1
Features
INTC has the following features:
• 16 levels of interrupt priority can be set: By setting the five interrupt-priority registers, the
priorities of on-chip supporting module, IRQ, and PINT interrupts can be selected from 16
levels for individual request sources.
• NMI noise canceller function: NMI input-level bit indicates NMI pin states. By reading this bit
in the interrupt exception service routine, the pin state can be checked, enabling it to be used as
a noise canceller.
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Section 7 Interrupt Controller (INTC)
7.1.2
Block Diagram
Figure 7.1 is a block diagram of the INTC.
NMI
IRL3 to IRL0
IRQ0 to IRQ5
PINT0 to PINT15
DMAC
SIOF
SCIF
SCI
ADC
TMU
RTC
WDT
REF
H-UDI
4
6
16
Input
control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(refresh request)
(Interrupt request)
ICR
Interrupt
request
Comparator
SR
3 2 1 0
Priority
identifier
CPU
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
IPR
Bus
interface
INTC
Legend:
TMU:
RTC:
SCI:
SCIF:
WDT:
REF:
ICR:
IPRA to IPRG:
SR:
Timer unit
Realtime clock unit
Serial communication interface
Serial communication interface (with FIFO)
Watchdog timer
Refresh requests in the bus state controller
Interrupt control register
Registers A-E for setting the interrupt
proprity levels
Status register
DMAC:
ADC:
H-UDI:
PCC:
LCDC:
USBH:
USBF:
AFE:
SIOF:
Direct memory access controller
Analog-to-digital converter
Hitachi user-debugging interface
PCMCIA controller
LCD controller
USB host
USB function controller
AFE interface
Serial IO
Figure 7.1 INTC Block Diagram
Rev. 5.00 Dec 12, 2005 page 166 of 1034
REJ09B0254-0500
Internal bus
IPRA to IPRG
PCC
LCDC
USBH
USBF
AFE
Section 7 Interrupt Controller (INTC)
7.1.3
Pin Configuration
Table 7.1 lists the INTC pin configuration.
Table 7.1
Pin Configuration
Name
Abbreviation
I/O
Description
Nonmaskable interrupt input
pin
NMI
I
Input of interrupt request signal, which
is nonmaskable by SR.IMASK
Interrupt input pins
IRQ5 to IRQ0
IRL3 to IRL0
I
Input of interrupt request signals, which
is maskable by SR.IMASK
Port interrupt input pins
PINT0 to PINT15
I
Port input of interrupt request signals,
which is maskable by SR.IMASK
7.1.4
Register Configuration
The INTC has 17 registers listed in table 7.2.
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Section 7 Interrupt Controller (INTC)
Table 7.2
Register Configuration
Name
Abbr.
R/W
Initial
1
Value*
Address
Access
Size
Interrupt control register 0
ICR0
R/W
*2
H'FFFFFEE0
16
Interrupt control register 1
ICR1
R/W
H'0000
H'04000010
3
(H'A4000010)*
16
Interrupt control register 2
ICR2
R/W
H'0000
H'04000012
3
(H'A4000012)*
16
Interrupt control register 3
ICR3
R/W
H'0000
H'04000228
3
(H'A4000228)*
16
PINT interrupt enable register
PINTER
R/W
H'0000
H'04000014
3
(H'A4000014)*
16
Interrupt priority level setting register A
IPRA
R/W
H'0000
H'FFFFFEE2
16
Interrupt priority level setting register B
IPRB
R/W
H'0000
H'FFFFFEE4
16
Interrupt priority level setting register C
IPRC
R/W
H'0000
H'04000016
3
(H'A4000016)*
16
Interrupt priority level setting register D
IPRD
R/W
H'0000
H'04000018
3
(H'A4000018)*
16
Interrupt priority level setting register E
IPRE
R/W
H'0000
H'0400001A
3
(H'A400001A)*
16
Interrupt priority level setting register F
IPRF
R/W
H'0000
H'04000220
3
(H'A4000220)*
16
Interrupt priority level setting register G
IPRG
R/W
H'0000
H'04000222
3
(H'A4000222)*
16
Interrupt request register 0
IRR0
R/W
H'00
H'04000004
3
(H'A4000004)*
8
Interrupt request register 1
IRR1
R
H'00
H'04000006
3
(H'A4000006)*
8
Interrupt request register 2
IRR2
R
H'00
H'04000008
3
(H'A4000008)*
8
Interrupt request register 3
IRR3
R
H'00
H'04000224
3
(H'A4000224)*
16
Interrupt request register 4
IRR4
R
H'00
H'04000226
3
(H'A4000226)*
16
Notes: 1. Initialized by a power-on or manual reset.
2. H'8000 when the NMI pin is at high level. H'0000 when the NMI pin is at low level.
3. When address translation by the MMU does not apply, the address in parentheses
should be used.
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Section 7 Interrupt Controller (INTC)
7.2
Interrupt Sources
There are five types of interrupt sources: NMI, IRQ, IRL, PINT, and on-chip supporting modules.
Each interrupt has priority levels (0 to 16) with 0 the lowest and 16 the highest. Priority level 0
masks an interrupt.
7.2.1
NMI Interrupts
The NMI interrupt has the highest priority level of 16. When the BLMSK bit of the interrupt
control register (ICR1) is 1 or the BL bit of the status register (SR) is 0, NMI interrupts are
accepted when the MAI bit of the ICR1 register is 0. NMI interrupts are edge-detected. In sleep or
standby mode, the interrupt is accepted regardless of the BL. The NMI edge select bit (NMIE) in
the interrupt control register 0 (ICR0) is used to select either the rising or falling edge. When the
NMIE bit of the ICR0 register is changed, the NMI interrupt is not detected for 20 cycles after
changing the ICR0.NMIE to avoid a false detection of the NMI interrupt. NMI interrupt exception
handling does not affect the interrupt mask level bits (I3 to I0) in the status register (SR).
When the BLMSK bit of the ICR1 register is set to 1 and only NMI interrupts are accepted, the
SPC register and SSR register are updated by the NMI interrupt handler, making it impossible to
return to the original processing from exception handling initiated prior to the NMI. Use should
therefore be restricted to cases where return is not necessary.
It is possible to wake the chip up from the standby state with an NMI interrupt (except when the
MAI bit of the ICR1 register is set to 1).
7.2.2
IRQ Interrupt
IRQ interrupts are input by priority from pins IRQ0 to IRQ5 with a level or an edge. The priority
level can be set by priority setting registers C, D (IPRC, IPRD) in a range from levels 0 to 15.
When using edge sensing for IRQ interrupts, do the following to clear IR0.
To clear bits IRQ5R to IRQ0R to 0, read from IRR0 before writing. After confirming that the bits
to be cleared to 0 are set to 1, write 0 to them. In this case write 0 only to the bits to be cleared;
write 1 to the other bits. The values of the bits to which 1 is written do not change.
When level sensing is used for IRQ interrupts, bits IRQ5R to IRQ0R indicate whether or not an
interrupt request has been input. They can be set and cleared by the values input to pins IRQ5R to
IRQ0R alone.
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Section 7 Interrupt Controller (INTC)
When the ICR1 register is rewritten, IRQ interrupts may be mistakenly detected, depending on the
pin states. To prevent this, rewrite the register while interrupts are masked, then release the mask
after clearing the illegal interrupt by writing 0 to interrupt request register 0 (IRR0).
It is necessary for an edge input interrupt detection to input a pulse width more than two-cycle
width by P clock basis.
With level detection, the level must be maintained until the interrupt is accepted and the CPU
starts interrupt handling.
The interrupt mask bits (I3 to I0) of the status register (SR) are not affected by IRQ interrupt
processing.
Interrupts IRQ5 to IRQ0 can be used to wake the chip up from the software standby mode (but
only when the RTC 32 kHz oscillator is used).
In this case, the priority level of the interrupt to be used must be higher than the level of bits I3 to
I0 in the SR register.
Notes: The following cautions apply when IRQ edge detection is used:
1. If an IRQ edge is input immediately before the CPU enters the standby mode (between
when the CPU executes the SLEEP instruction and when STATUS0 goes high), the
interrupt may not be detected properly. After this, if the IRQ edge is input again after
STATUS0 goes high, the interrupt will be detected.
2. If an IRQ edge is input while the frequency is changing due to a change in the value of
the STC bit in the FRQCR register (during the count by WDT), the interrupt may not
be detected properly. If the IRQ edge is input again after the WDT count completes,
the interrupt will be detected.
7.2.3
IRL Interrupts
IRL interrupts are input by level at pins IRL3 to IRL0. The priority level is the higher level
indicated by pins IRL3 to IRL0. An IRL3 to IRL0 value of 0 (0000) indicates the highest-level
interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request
(interrupt priority level 0). Figure 7.2 shows an example of an IRL interrupt connection. Table 7.3
shows IRL pins and interrupt levels.
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Section 7 Interrupt Controller (INTC)
SH7727
Priority
encoder
Interrupt
request
4
IRL3 to IRL0
IRL3 to IRL0
Figure 7.2 Example of IRL Interrupt Connection
IRL3 to IRL0 Pins and Interrupt Levels
Table 7.3
IRL3
IRL2
IRL1
IRL0
Interrupt Priority Level
Interrupt Request
0
0
0
0
15
Level 15 interrupt request
0
0
0
1
14
Level 14 interrupt request
0
0
1
0
13
Level 13 interrupt request
0
0
1
1
12
Level 12 interrupt request
0
1
0
0
11
Level 11 interrupt request
0
1
0
1
10
Level 10 interrupt request
0
1
1
0
9
Level 9 interrupt request
0
1
1
1
8
Level 8 interrupt request
1
0
0
0
7
Level 7 interrupt request
1
0
0
1
6
Level 6 interrupt request
1
0
1
0
5
Level 5 interrupt request
1
0
1
1
4
Level 4 interrupt request
1
1
0
0
3
Level 3 interrupt request
1
1
0
1
2
Level 2 interrupt request
1
1
1
0
1
Level 1 interrupt request
1
1
1
1
0
No interrupt request
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every supporting module cycle remain unchanged for two consecutive cycles, so that
no transient level on the IRL pin change is detected. In the standby mode, as the peripheral clock
is stopped, noise cancellation is performed using the 32-kHz clock for the RTC instead. Therefore
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Section 7 Interrupt Controller (INTC)
when the RTC is not used, interruption by means of IRL interrupts cannot be performed in standby
mode.
The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the
interrupt processing starts. Correct operation cannot be guaranteed if the level is not maintained.
However, the priority level can be changed to a higher one.
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRL interrupt
processing.
7.2.4
PINT Interrupt
PINT interrupts are input by priority from pins PINT0 to PINT15 with a level. The priority level
can be set by priority setting registers D (IPRD) in a range from levels 0 to 15, in the unit of
PINT0 to PINT7 or PINT8 to PINT15.
The PINT interrupt level should be held until the interrupt is accepted and interrupt handling is
started.
The interrupt mask bits (I3 to I0) of the status register (SR) are not affected by PINT interrupt
processing.
PINT interrupts can wake the chip up from the standby state when the relevant interrupt level is
higher than I3 to I0 in the SR register (but only when the RTC 32-kHz oscillator is used).
7.2.5
On-Chip Supporting Module Interrupts
On-chip supporting module interrupts are generated by the following fourteen modules:
• Timer unit (TMU)
• Realtime clock (RTC)
• Serial communication interface (SCI, SCIF)
• Bus state controller (BSC)
• Watchdog timer (WDT)
• Direct memory access controller (DMAC)
• Analog-to-digital converter (ADC)
• PC Card controller (PCC)
• OHCI compliant USB HOST controller (USBH)
• USB function controller (USBF)
• AFE interface (AFEIF)
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Section 7 Interrupt Controller (INTC)
• LCD controller (LCDC)
• Hitachi user-debugging interface (H-UDI)
• Serial IO (SIOF)
Not every interrupt source is assigned a different interrupt vector. Sources are reflected on the
interrupt event register (INTEVT and INTEVT2). It is easy to identify sources by using the values
of the INTEVT or INTEVT2 register as branch offsets.
The priority level (from 0 to 15) can be set for each module except for H-UDI by writing to the
interrupt priority setting registers A to G (IPRA to IPRG). The priority level of H-UDI interrupt is
15 (fixed).
The interrupt mask bits (I3 to I0) of the status register are not affected by the on-chip supporting
module interrupt processing.
TMU and RTC interrupts can wake the chip up from the standby state when the relevant interrupt
level is higher than I3 to I0 in the SR register (but only when the RTC 32-kHz oscillator is used).
7.2.6
Interrupt Exception Handling and Priority
Tables 7.4 and 7.5 list the codes for the interrupt event register (INTEVT and INTEVT2), and the
order of interrupt priority. Each interrupt source is assigned unique code. The start address of the
interrupt service routine is common to each interrupt source. This is why, for instance, the value of
INTEVT or INTEVT2 is used as offset at the start of the interrupt service routine and branched to
identify the interrupt source.
The order of priority of the on-chip supporting module, IRQ, and PINT interrupts is set within the
priority levels 0 to 15 at will by using the interrupt priority level set to registers A to G (IPRA to
IPRG). The order of priority of the on-chip supporting module, IRQ, and PINT interrupts is set to
zero by RESET.
When the order of priorities for multiple interrupt sources are set to the same level and such
interrupts are generated at the same time, they are processed according to the default order listed
in tables 7.4 and 7.5.
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Section 7 Interrupt Controller (INTC)
Table 7.4
Interrupt Exception Handling Sources and Priority (IRQ Mode)
Priority
within IPR
Setting
Default
Priority
Unit
Interrupt Source
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
IPR (Bit
(Initial Value) Numbers)
NMI
H'1C0 (H'1C0)
16
—
—
H-UDI
H'5E0 (H'5E0)
15
—
—
IRQ0
H'200–3C0* (H'600)
0–15 (0)
IPRC (3–0)
—
IRQ1
H'200–3C0* (H'620)
0–15 (0)
IPRC (7–4)
—
IRQ2
H'200–3C0* (H'640)
0–15 (0)
IPRC (11–8)
—
IRQ3
H'200–3C0* (H'660)
0–15 (0)
IPRC (15–12)
—
IRQ4
H'200–3C0* (H'680)
0–15 (0)
IPRD (3–0)
—
IRQ5
H'200–3C0* (H'6A0)
0–15 (0)
IPRD (7–4)
—
PINT0–7
H'200–3C0* (H'700)
0–15 (0)
IPRD (15–12)
—
PINT8–15
H'200–3C0* (H'720)
0–15 (0)
IPRD (11–8)
—
0–15 (0)
IPRE (15–12)
High
IRQ
PINT
DMAC
DEI0
H'200–3C0* (H'800)
DEI1
H'200–3C0* (H'820)
DEI2
H'200–3C0* (H'840)
DEI3
H'200–3C0* (H'860)
ERI2
H'200–3C0* (H'900)
RXI2
H'200–3C0* (H'920)
BRI2
H'200–3C0* (H'940)
TXI2
H'200–3C0* (H'960)
ADC
ADI
H'200–3C0* (H'980)
0–15 (0)
IPRE (3–0)
—
LCDC
LCDCI
H'200–3C0* (H'9A0)
0–15 (0)
IPRF(11–8)
—
SIOF
SIFERI
H'200–3C0* (H'B00)
0–15 (0)
IPRF(3–0)
High
SIFTXI
H'200–3C0* (H'B20)
0–15 (0)
SIFRXI
H'200–3C0* (H'B40)
0–15 (0)
SIFCCI
H'200–3C0* (H'B60)
0–15 (0)
USBH
USBHI
H'200–3C0* (H'A00)
0–15 (0)
IPRG(15–12)
—
USBF
USBFI0
H'200–3C0* (H'A20)
0–15 (0)
IPRG(11–8)
High
USBFI1
H'200–3C0* (H'A40)
0–15 (0)
IPRG(7–4)
Low
AFEIFI
H'200–3C0* (H'A 60) 0–15 (0)
IPRG(3–0)
—
SCIF
AFEIF
Rev. 5.00 Dec 12, 2005 page 174 of 1034
REJ09B0254-0500
High
Low
0–15 (0)
IPRE (7–4)
High
Low
Low
Low
Section 7 Interrupt Controller (INTC)
Interrupt
Priority
IPR (Bit
(Initial Value) Numbers)
Priority
within IPR
Setting
Default
Priority
Unit
PC0SWIR H'200–3C0* (H'9C0)
0–15 (0)
High
PC0IRIR
H'200–3C0* (H'9C0)
0–15 (0)
PC0SCIR
H'200–3C0* (H'9C0)
0–15 (0)
PC0CDIR
H'200–3C0* (H'9C0)
0–15 (0)
PC0RCIR
H'200–3C0* (H'9C0)
0–15 (0)
PC0BWIR H'200–3C0* (H'9C0)
0–15 (0)
PC0BDIR
H'200–3C0* (H'9C0)
0–15 (0)
TMU0
TUNI0
H'400 (H'400)
0–15 (0)
IPRA (15–12)
—
TMU1
TUNI1
H'420 (H'420)
0–15 (0)
IPRA (11–8)
—
Interrupt Source
PCC0
INTEVT Code
(INTEVT2 Code)
IPRF(7–4)
Low
TMU2
TUNI2
H'440 (H'440)
0–15 (0)
IPRA (7–4)
—
RTC
ATI
H'480 (H'480)
0–15 (0)
IPRA (3–0)
High
PRI
H'4A0 (H'4A0)
CUI
H'4C0 (H'4C0)
ERI
H'4E0 (H'4E0)
RXI
H'500 (H'500)
TXI
H'520 (H'520)
TEI
H'540 (H'540)
WDT
ITI
H'560 (H'560)
0–15 (0)
IPRB (15–12)
—
REF
RCMI
H'580 (H'580)
0–15 (0)
IPRB (11–8)
High
ROVI
H'5A0 (H'5A0)
SCI0
High
Low
0–15 (0)
IPRB (7–4)
High
Low
Low
Low
Note: * The code corresponding to an interrupt level shown in table 7.6 is set.
Rev. 5.00 Dec 12, 2005 page 175 of 1034
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Section 7 Interrupt Controller (INTC)
Table 7.5
Interrupt Exception Handling Sources and Priority (IRL Mode)
Interrupt Source
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
(Initial
IPR (Bit
Numbers)
Value)
NMI
H'1C0 (H'1C0)
16
—
—
H-UDI
H'5E0 (H'5E0)
15
—
—
IRL(3:0) = 0000
H'200 (H'200)
15
—
—
IRL(3:0) = 0001
H'220 (H'220)
14
—
—
IRL(3:0) = 0010
H'240 (H'240)
13
—
—
IRL(3:0) = 0011
H'260 (H'260)
12
—
—
IRL(3:0) = 0100
H'280 (H'280)
11
—
—
IRL(3:0) = 0101
H'2A0 (H'2A0)
10
—
—
IRL(3:0) = 0110
H'2C0 (H'2C0)
9
—
—
IRL(3:0) = 0111
H'2E0 (H'2E0)
8
—
—
IRL(3:0) = 1000
H'300 (H'300)
7
—
—
IRL(3:0) = 1001
H'320 (H'320)
6
—
—
IRL(3:0) = 1010
H'340 (H'340)
5
—
—
IRL(3:0) = 1011
H'360 (H'360)
4
—
—
IRL(3:0) = 1100
H'380 (H'380)
3
—
—
IRL(3:0) = 1101
H'3A0 (H'3A0)
2
—
—
IRL(3:0) = 1110
H'3C0 (H'3C0)
1
—
—
IRQ4
H'200–3C0* (H'680)
0–15 (0)
IPRD (3–0)
—
IRQ5
H'200–3C0* (H'6A0)
0–15 (0)
IPRD (7–4)
—
PINT0–7
H'200–3C0* (H'700)
0–15 (0)
IPRD (15–12) —
PINT8–15
H'200–3C0* (H'720)
0–15 (0)
IPRD (11–8)
0–15 (0)
IPRE (15–12) High
IRL
IRQ
PINT
DMAC
SCIF
DEI0
H'200–3C0* (H'800)
DEI1
H'200–3C0* (H'820)
DEI2
H'200–3C0* (H'840)
DEI3
H'200–3C0* (H'860)
ERI2
H'200–3C0* (H'900)
RXI2
H'200–3C0* (H'920)
BRI2
H'200–3C0* (H'940)
TXI2
H'200–3C0* (H'960)
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REJ09B0254-0500
Priority
within IPR
Setting
Default
Priority
Unit
High
—
Low
0–15 (0)
IPRE (7–4)
High
Low
Low
Section 7 Interrupt Controller (INTC)
Interrupt Source
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
(Initial
IPR (Bit
Numbers)
Value)
Priority
within IPR
Setting
Default
Priority
Unit
ADC
ADI
H'200–3C0* (H'980)
0–15 (0)
IPRE (3–0)
—
LCDC
LCDCI
H'200–3C0* (H'9A0)
0–15 (0)
IPRF (11–8)
—
SIOF
SIFERI
H'200–3C0* (H'B00)
0–15 (0)
IPRF (3–0)
High
SIFTXI
H'200–3C0* (H'B20)
0–15 (0)
SIFRXI
H'200–3C0* (H'B40)
0–15 (0)
SIFCCI
H'200–3C0* (H'B60)
0–15 (0)
USBH
USBHI
H'200–3C0* (H'A00)
0–15 (0)
IPRG (15–12) —
USBF
USBFI0
H'200–3C0* (H'A20)
0–15 (0)
IPRG (11–8)
High
USBFI1
H'200–3C0* (H'A40)
0–15 (0)
IPRG (7–4)
Low
Low
AFEIF
AFEIFI
H'200–3C0* (H'A60)
0–15 (0)
IPRG (3–0)
—
PCC0
PC0SWIR
H'200–3C0* (H'9C0)
0–15 (0)
IPRF (7–4)
High
PC0IRIR
H'200–3C0* (H'9C0)
0–15 (0)
PC0SCIR
H'200–3C0* (H'9C0)
0–15 (0)
PC0CDIR
H'200–3C0* (H'9C0)
0–15 (0)
PC0RCIR
H'200–3C0* (H'9C0)
0–15 (0)
PC0BWIR
H'200–3C0* (H'9C0)
0–15 (0)
PC0BDIR
H'200–3C0* (H'9C0)
0–15 (0)
TMU0
TUNI0
H'400 (H'400)
0–15 (0)
IPRA (15–12) —
TMU1
TUNI1
H'420 (H'420)
0–15 (0)
IPRA (11–8)
Low
—
TMU2
TUNI2
H'440 (H'440)
0–15 (0)
IPRA (7–4)
—
RTC
ATI
H'480 (H'480)
0–15 (0)
IPRA (3–0)
High
PRI
H'4A0 (H'4A0)
CUI
H'4C0 (H'4C0)
ERI
H'4E0 (H'4E0)
RXI
H'500 (H'500)
SCI0
High
Low
0–15 (0)
IPRB (7–4)
High
TXI
H'520 (H'520)
TEI
H'540 (H'540)
WDT
ITI
H'560 (H'560)
0–15 (0)
IPRB (15–12) —
REF
RCMI
H'580 (H'580)
0–15 (0)
IPRB (11–8)
ROVI
H'5A0 (H'5A0)
Low
High
Low
Low
Note: * The code corresponding to an interrupt level shown in table 7.6 is set.
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Section 7 Interrupt Controller (INTC)
Table 7.6
Interrupt Level and INTEVT Code
Interrupt level
INTEVT Code
15
H'200
14
H'220
13
H'240
12
H'260
11
H'280
10
H'2A0
9
H'2C0
8
H'2E0
7
H'300
6
H'320
5
H'340
4
H'360
3
H'380
2
H'3A0
1
H'3C0
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Section 7 Interrupt Controller (INTC)
7.3
INTC Registers
7.3.1
Interrupt Priority Registers A to G (IPRA to IPRG)
Interrupt priority registers A to G (IPRA to IPRG) are 16-bit read/write registers that set priority
levels from 0 to 15 for on-chip supporting module, IRQ, and PINT interrupts. These registers are
initialized to H'0000 at power-on reset, and manual reset, but are not initialized in standby mode.
Bit:
15
14
13
12
11
10
9
8
Initial value:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
R/W:
Table 7.7 lists the relationship between the interrupt sources and the IPRA to IPRG bits.
Table 7.7
Interrupt Request Sources and IPRA to IPRG
Register
Bits 15 to 12
Bits 11 to 8
Bits 7 to 4
Bits 3 to 0
IPRA
TMU0
TMU1
TMU2
RTC
IPRB
WDT
REF
SCI
Reserved*
IPRC
IRQ3
IRQ2
IRQ1
IRQ0
IPRD
PINT0 to PINT7
PINT8 to PINT15
IRQ5
IRQ4
IPRE
DMAC
Reserved*
SCIF
ADC
IPRF
Reserved*
LCDC
PCC0
SIOF
IPRG
USBH
USBF0
USBF1
AFEIF
Note: * Always read as 0. Only 0 should be written in.
As listed in table 7.7, four sets of on-chip supporting modules or IRQ or PINT interrupts are
assigned to each register. 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set
with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is
requested); H'F is priority level 15 (the highest level). A reset initializes IPRA to IPRG to H'0000.
Rev. 5.00 Dec 12, 2005 page 179 of 1034
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Section 7 Interrupt Controller (INTC)
7.3.2
Interrupt Control Register 0 (ICR0)
The ICR0 is a register that sets the input signal detection mode of the external interrupt input pin
NMI and indicates the input signal level to the NMI pin. This register is initialized to H'0000 or
H'8000 at power-on reset or manual reset, but is not initialized in standby mode.
Bit:
15
14
13
12
11
10
9
8
NMIL
—
—
—
—
—
—
NMIE
0/1*
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Initial value:
Note: * When NMI input is high: 1; when NMI input is low: 0.
Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can
be read to determine the NMI pin level. This bit cannot be modified.
Bit 15: NMIL
Description
0
NMI input level is low
1
NMI input level is high
Bit 8—NMI Edge Select (NMIE): Selects whether the falling or rising edge of the interrupt
request signal to the NMI is detected.
Bit 8: NMIE
Description
0
Interrupt request is detected on the falling edge of NMI input
1
Interrupt request is detected on rising edge of NMI input
(Initial value)
Bits 14 to 9 and 7 to 0—Reserved: These bits are always read as 0. The write value should
always be 0.
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Section 7 Interrupt Controller (INTC)
7.3.3
Interrupt Control Register 1 (ICR1)
The ICR1 is a 16-bit register that specifies the detection mode to external interrupt input pins,
IRQ0 to IRQ5 individually: rising edge, falling edge, or low level. This register, initialized to
H'4000 at power-on reset or manual reset, is not initialized in the standby mode.
Bit:
15
MAI
Initial value:
R/W:
Bit:
14
13
IRQLVL BLMSK
12
11
—
10
9
8
IRQ51S IRQ50S IRQ41S IRQ40S
0
1
0
0
0
0
0
0
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
Initial value:
R/W:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 15—Mask All Interrupts (MAI): Masks NMI interrupts in standby mode when set to 1. Also
selects whether or not all interrupt requests are masked when a low level is being input to the NMI
pin.
Bit 15: MAI
Description
0
All interrupt requests are not masked while NMI pin is receiving low-level input
(Initial value)
1
All interrupt requests are masked while NMI pin is receiving low-level input
Bit 14—Interrupt Request Level Detect (IRQLVL): Selects whether the IRQ3 to IRQ0 pins are
used as four independent interrupt pins or as 15-level interrupt pins encoded as IRL3 to IRL0.
Bit 14: IRQLVL Description
0
Used as four independent interrupt request pins IRQ3 to IRQ0
1
Used as encoded 15-level interrupt pins as IRL3 to IRL0
(Initial value)
Bit 13—BL Bit Mask (BLMSK): Specifies whether NMI interrupts are masked when the BL bit
of the SR register is 1.
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Section 7 Interrupt Controller (INTC)
Bit 13: BLMSK Description
0
NMI interrupts are masked when the BL bit is 1
1
NMI interrupts are accepted regardless of the BL bit setting
(Initial value)
Bit 12—Reserved: This bit is always read as 0. The write value should always be 0.
Bits 11 and 10—IRQ5 Sense Select (IRQ51S and IRQ50S): Select whether the interrupt signal
to the IRQ5 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 11: IRQ51S Bit 10: IRQ50S Description
0
1
0
An interrupt request is detected at IRQ5 input falling edge
(Initial value)
1
An interrupt request is detected at IRQ5 input rising edge
0
An interrupt request is detected at IRQ5 input low level
1
Reserved
Bits 9 and 8—IRQ4 Sense Select (IRQ41S and IRQ40S): Select whether the interrupt signal to
the IRQ4 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 9: IRQ41S
Bit 8: IRQ40S
Description
0
0
An interrupt request is detected at IRQ4 input falling edge
(Initial value)
1
An interrupt request is detected at IRQ4 input rising edge
1
0
An interrupt request is detected at IRQ4 input low level
1
Reserved
Bits 7 and 6—IRQ3 Sense Select (IRQ31S and IRQ30S): Select whether the interrupt signal to
the IRQ3 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 7: IRQ31S
Bit 6: IRQ30S
Description
0
0
An interrupt request is detected at IRQ3 input falling edge
(Initial value)
1
An interrupt request is detected at IRQ3 input rising edge
0
An interrupt request is detected at IRQ3 input low level
1
Reserved
1
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Section 7 Interrupt Controller (INTC)
Bits 5 and 4—IRQ2 Sense Select (IRQ21S and IRQ20S): Select whether the interrupt signal to
the IRQ2 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 5: IRQ21S
Bit 4: IRQ20S
Description
0
0
An interrupt request is detected at IRQ2 input falling edge
(Initial value)
1
An interrupt request is detected at IRQ2 input rising edge
1
0
An interrupt request is detected at IRQ2 input low level
1
Reserved
Bits 3 and 2—IRQ1 Sense Select (IRQ11S and IRQ10S): Select whether the interrupt signal to
the IRQ1 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 3: IRQ11S
Bit 2: IRQ10S
Description
0
0
An interrupt request is detected at IRQ1 input falling edge
(Initial value)
1
An interrupt request is detected at IRQ1 input rising edge
0
An interrupt request is detected at IRQ1 input low level
1
Reserved
1
Bits 1 and 0—IRQ0 Sense Select (IRQ01S and IRQ00S): Select whether the interrupt signal to
the IRQ0 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 1: IRQ01S
Bit 0: IRQ00S
Description
0
0
An interrupt request is detected at IRQ0 input falling edge
(Initial value)
1
An interrupt request is detected at IRQ0 input rising edge
0
An interrupt request is detected at IRQ0 input low level
1
Reserved
1
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Section 7 Interrupt Controller (INTC)
7.3.4
Interrupt Control Register 2 (ICR2)
The ICR2 is a 16-bit read/write register that sets the detection mode to external interrupt input pins
PINT0 to PINT15. This register is initialized to H'0000 at power-on reset or manual reset, but is
not initialized in standby mode.
Bit:
15
14
13
12
11
10
9
8
PINT15S PINT14S PINT13S PINT14S PINT11S PINT10S PINT9S PINT8S
Initial value:
R/W:
Bit:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S
Initial value:
R/W:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 to 0—PINT15 to PINT0 Sense Select (PINT15S to PINT0S): Select whether interrupt
request signals to PINT15 to PINT0 are detected at low levels or high levels.
Bits 15 to 0:
PINT15S to PINT0S
Description
0
Interrupt requests are detected at low level input to the PINT pins
(Initial value)
1
Interrupt requests are detected at high level input to the PINT pins
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Section 7 Interrupt Controller (INTC)
7.3.5
Interrupt Control Register 3 (ICR3)
The ICR3 is a 16-bit read/write register that sets the mask to PC Card controller. This register is
initialized to H'0000 at power-on reset or manual reset, but is not initialized in standby mode.
Bit:
15
—
Initial value:
R/W:
Bit:
Initial value:
R/W:
14
13
12
11
10
9
8
PC0SWIM PC0IRIM PC0SCIM PC0CDIM PC0RCIM PC0BWIM PC0BDIM
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 15—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 14—PC0SWIM: PC Card controller0 SWI mask.
Bit 14:
PC0SWIM
Description
0
Interrupt requests is masked
1
Interrupt requests is not masked
(Initial value)
Bit 13—PC0IRIM: PC Card controller0 IRI mask.
Bits 13:
PC0IRIM
Description
0
Interrupt requests is masked
1
Interrupt requests is not masked
(Initial value)
Bit 12—PC0SCIM: PC Card controller0 SCI mask.
Bit 12:
PC0SCIM
Description
0
Interrupt requests is masked
1
Interrupt requests is not masked
(Initial value)
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Section 7 Interrupt Controller (INTC)
Bit 11—PC0CDIM: PC Card controller0 CDI mask.
Bit 11:
PC0CDIM
Description
0
Interrupt requests is masked
1
Interrupt requests is not masked
(Initial value)
Bit 10—PC0RCIM: PC Card controller0 RCI mask.
Bit 10:
PC0RCIM
Description
0
Interrupt requests is masked
1
Interrupt requests is not masked
(Initial value)
Bit 9—PC0BWIM: PC Card controller0 BWI mask.
Bit 9:
PC0BWIM
Description
0
Interrupt requests is masked
1
Interrupt requests is not masked
(Initial value)
Bit 8—PC0BDIM: PC Card controller0 BDI mask.
Bit 8:
PC0BDIM
Description
0
Interrupt requests is masked
1
Interrupt requests is not masked
(Initial value)
Bits 7 to 0— Reserved: These bits are always read as 0. The write value should always be 0.
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Section 7 Interrupt Controller (INTC)
7.3.6
PINT Interrupt Enable Register (PINTER)
The PINTER is a 16-bit read/write register that enables interrupt requests input to external
interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 at power-on reset or
manual reset, but is not initialized in standby mode.
Bit:
15
14
13
12
11
10
9
8
PINT15E PINT14E PINT13E PINT12E PINT11E PINT10E PINT9E PINT8E
Initial value:
R/W:
Bit:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E
Initial value:
R/W:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 to 0—PINT15 to PINT0 Interrupt Enable (PINT15E to PINT0E): Enable whether the
interrupt requests input to the PINT15 to PINT0 pins.
Bits 15 to 0:
PINT15E to PINT0E
Description
0
Disables PINT input interrupt requests
1
Enables PINT input interrupt requests
(Initial value)
When all or some of these pins, PINT0 to PINT15 are not used as an interrupt input, a bit
corresponding to a pin unused as an interrupt request should be set to 0.
7.3.7
Interrupt Request Register 0 (IRR0)
The IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to
IRQ5 and PINT0 to PINT15. This register is initialized to H'00 at power-on reset or manual reset,
but is not initialized in standby mode.
Bit:
7
6
PINT0R PINT1R
5
4
3
2
1
0
IRQ5R
IRQ4R
IRQ3R
IRQ2R
IRQ1R
IRQ0R
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R/W
R/W
R/W
R/W
R/W
R/W
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Section 7 Interrupt Controller (INTC)
When using edge sensing for IRQ interrupts, do the following to clear IR0.
To clear bits IRQ5R to IRQ0R to 0, read from IRR0 before writing. After confirming that the bits
to be cleared to 0 are set to 1, write 0 to them. In this case write 0 only to the bits to be cleared;
write 1 to the other bits. The values of the bits to which 1 is written do not change.
When level sensing is used for IRQ interrupts, bits IRQ5R to IRQ0R indicate whether or not an
interrupt request has been input. They can be set and cleared by the values input to pins IRQ5R to
IRQ0R alone.
Bit 7—PINT0 to PINT7 Interrupt Request (PINT0R): Indicates whether interrupt requests are
input to PINT0 to PINT7 pins.
Bit 7: PINT0R
Description
0
Interrupt requests are not input to PINT0 to PINT7 pins
1
Interrupt requests are input to PINT0 to PINT7 pins.
(Initial value)
Bit 6—PINT8 to PINT15 Interrupt Request (PINT1R): Indicates whether interrupt requests are
input to PINT8 to PINT15 pins.
Bit 6: PINT1R
Description
0
Interrupt requests are not input to PINT8 to PINT15 pins
1
Interrupt requests are input to PINT8 to PINT15 pins.
(Initial value)
Bit 5—IRQ5 Interrupt Request (IRQ5R): Indicates whether an interrupt request is input to the
IRQ5 pin. When edge detection mode is set for IRQ5, an interrupt request is cleared by clearing
the IRQ5R bit.
Bit 5: IRQ5R
Description
0
An interrupt request is not input to IRQ5 pin
1
An interrupt request is input to IRQ5 pin
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(Initial value)
Section 7 Interrupt Controller (INTC)
Bit 4—IRQ4 Interrupt Request (IRQ4R): Indicates whether an interrupt request is input to the
IRQ4 pin. When edge detection mode is set for IRQ4, an interrupt request is cleared by clearing
the IRQ4R bit.
Bit 4: IRQ4R
Description
0
An interrupt request is not input to IRQ4 pin
1
An interrupt request is input to IRQ4 pin
(Initial value)
Bit 3—IRQ3 Interrupt Request (IRQ3R): Indicates whether an interrupt request is input to the
IRQ3 pin. When edge detection mode is set for IRQ3, an interrupt request is cleared by clearing
the IRQ3R bit.
Bit 3: IRQ3R
Description
0
An interrupt request is not input to IRQ3 pin
1
An interrupt request is input to IRQ3 pin
(Initial value)
Bit 2—IRQ2 Interrupt Request (IRQ2R): Indicates whether an interrupt request is input to the
IRQ2 pin. When edge detection mode is set for IRQ2, an interrupt request is cleared by clearing
the IRQ2R bit.
Bit 2: IRQ2R
Description
0
An interrupt request is not input to IRQ2 pin
1
An interrupt request is input to IRQ2 pin
(Initial value)
Bit 1—IRQ1 Interrupt Request (IRQ1R): Indicates whether an interrupt request is input to the
IRQ1 pin. When edge detection mode is set for IRQ1, an interrupt request is cleared by clearing
the IRQ1R bit.
Bit 1: IRQ1R
Description
0
An interrupt request is not input to IRQ1 pin
1
An interrupt request is input to IRQ1 pin
(Initial value)
Bit 0—IRQ0 Interrupt Request (IRQ0R): Indicates whether an interrupt request is input to the
IRQ0 pin. When edge detection mode is set for IRQ0, an interrupt request is cleared by clearing
the IRQ0R bit.
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Section 7 Interrupt Controller (INTC)
Bit 0: IRQ0R
Description
0
An interrupt request is not input to IRQ0 pin
1
An interrupt request is input to IRQ0 pin
7.3.8
(Initial value)
Interrupt Request Register 1 (IRR1)
The IRR1 is an 8-bit read-only register that indicates whether DMAC or interrupt requests are
generated. This register is initialized to H'00 at power-on reset or manual reset, but is not
initialized in standby mode.
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
DEI3R
DEI2R
DEI1R
DEI0R
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bits 7 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—DEI3 Interrupt Request (DEI3R): Indicates whether a DEI3 (DMAC) interrupt request
is generated.
Bit 3: DEI3R
Description
0
A DEI3 interrupt request is not generated
1
A DEI3 interrupt request is generated
(Initial value)
Bit 2—DEI2 Interrupt Request (DEI2R): Indicates whether a DEI2 (DMAC) interrupt request
is generated.
Bit 2: DEI2R
Description
0
A DEI2 interrupt request is not generated
1
A DEI2 interrupt request is generated
(Initial value)
Bit 1—DEI1 Interrupt Request (DEI1R): Indicates whether a DEI1 (DMAC) interrupt request
is generated.
Bit 1: DEI1R
Description
0
A DEI1 interrupt request is not generated
1
A DEI1 interrupt request is generated
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(Initial value)
Section 7 Interrupt Controller (INTC)
Bit 0—DEI0 Interrupt Request (DEI0R): Indicates whether a DEI0 (DMAC) interrupt request
is generated.
Bit 0: DEI0R
Description
0
A DEI0 interrupt request is not generated
1
A DEI0 interrupt request is generated
7.3.9
(Initial value)
Interrupt Request Register 2 (IRR2)
The IRR2 is an 8-bit read-only register that indicates whether A/D converter, or SCIF interrupt
requests are generated. This register is initialized to H'00 at power-on reset or manual reset, but is
not initialized in standby mode.
Bit:
7
6
5
4
3
2
1
0
—
—
—
ADIR
TXI2R
BRI2R
RXI2R
ERI2R
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bits 7 to 5—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 4—ADI Interrupt Request (ADIR): Indicates whether an ADI (ADC) interrupt request is
generated.
Bit 4: ADIR
Description
0
An ADI interrupt request is not generated
1
An ADI interrupt request is generated
(Initial value)
Bit 3—TXI2 Interrupt Request (TXI2R): Indicates whether a TXI2 (SCIF) interrupt request is
generated.
Bit 3: TXI2R
Description
0
A TXI2 interrupt request is not generated
1
A TXI2 interrupt request is generated
(Initial value)
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Section 7 Interrupt Controller (INTC)
Bit 2—BRI2 Interrupt Request (BRI2R): Indicates whether a BRI2 (SCIF) interrupt request is
generated.
Bit 2: BRI2R
Description
0
A BRI2 interrupt request is not generated
1
A BRI2 interrupt request is generated
(Initial value)
Bit 1—RXI2 Interrupt Request (RXI2R): Indicates whether an RXI2 (SCIF) interrupt request is
generated.
Bit 1: RXI2R
Description
0
An RXI2 interrupt request is not generated
1
An RXI2 interrupt request is generated
(Initial value)
Bit 0—ERI2 Interrupt Request (ERI2R): Indicates whether an ERI2 (SCIF) interrupt request is
generated.
Bit 0: ERI2R
Description
0
An ERI2 interrupt request is not generated
1
An ERI2 interrupt request is generated
7.3.10
(Initial value)
Interrupt Request Register 3 (IRR3)
The IRR3 is a 16-bit read-only register that indicates whether PC Card controller, USB Controller
or LCDC interrupt requests are generated. This register is initialized to H'0000 at power-on reset
or manual reset, but is not initialized in standby mode.
Bit:
15
14
13
12
11
10
9
8
LCDCIR PC0SWIR PC0IRIR PC0SCIR PC0CDIR PC0RCIR PC0BWIR PC0BDIR
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
USBHIR USBF0IR USBF1IR AFEIFIR
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
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Section 7 Interrupt Controller (INTC)
Bit 15—LCDCI interrupt request (LCDCIR): Indicates whether a LCDCI (LCDC) interrupt
request is generated.
Bit 15: LCDCIR
Description
0
A LCDCI interrupt request is not generated
1
A LCDCI interrupt request is generated
(Initial value)
Bit 14—PC0SWI Interrupt Request (PC0SWIR): Indicates whether a PC0SWI (PCC0)
interrupt request is generated.
Bit 14: PC0SWIR
Description
0
A PC0SWI interrupt request is not generated
1
A PC0SWI interrupt request is generated
(Initial value)
Bit 13—PC0IRI Interrupt Request (PC0IRIR): Indicates whether a PC0IREQ (PCC0) interrupt
request is generated.
Bit 13: PC0IRIR
Description
0
A PC0IRI interrupt request is not generated
1
A PC0IRI interrupt request is generated
(Initial value)
Bit 12—PC0SCI Interrupt Request (PC0SCIR): Indicates whether a PC0SCI (PCC0) interrupt
request is generated.
Bit 12: PC0SCIR
Description
0
A PC0SCI interrupt request is not generated
1
A PC0SCI interrupt request is generated
(Initial value)
Bit 11—PC0CDI Interrupt Request (PC0CDIR): Indicates whether a PC0CDI (PCC0) interrupt
request is generated.
Bit 11: PC0CDIR
Description
0
A PC0CDI interrupt request is not generated
1
A PC0CDI interrupt request is generated
(Initial value)
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Section 7 Interrupt Controller (INTC)
Bit 10—PC0RCI Interrupt Request (PC0RCIR): Indicates whether a PC0RCI (PCC0) interrupt
request is generated.
Bit 10: PC0RCIR
Description
0
A PC0RCI interrupt request is not generated
1
A PC0RCI interrupt request is generated
(Initial value)
Bit 9—PC0BWI Interrupt Request (PC0BWIR): Indicates whether a PC0BWI (PCC0)
interrupt request is generated.
Bit 9: PC0BWIR
Description
0
A PC0BWI interrupt request is not generated
1
A PC0BWI interrupt request is generated
(Initial value)
Bit 8—PC0BDI Interrupt Request (PC0BDIR): Indicates whether a PC0BDI (PCC0) interrupt
request is generated.
Bit 8: PC0BDIR
Description
0
A PC0BDI interrupt request is not generated
1
A PC0BDI interrupt request is generated
(Initial value)
Bit 7—USBHI Interrupt Request (USBHIR): Indicates whether a USBHI (USB Host) interrupt
request is generated.
Bit 7: USBHIR
Description
0
A USBHI interrupt request is not generated
1
A USBHI interrupt request is generated
(Initial value)
Bit 6—USBF0I Interrupt Request (USBF0IR): Indicates whether a USBF0I (USB function)
interrupt request is generated.
Bit 6: USBF0IR
Description
0
A USBF0I interrupt request is not generated
1
A USBF0I interrupt request is generated
Rev. 5.00 Dec 12, 2005 page 194 of 1034
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(Initial value)
Section 7 Interrupt Controller (INTC)
Bit 5—USBF1I Interrupt Request (USBF1IR): Indicates whether a USBF1I (USB function)
interrupt request is generated.
Bit 5: USBF1IR
Description
0
A USBF1I interrupt request is not generated
1
A USBF1I interrupt request is generated
(Initial value)
Bit 4—AFEIFI Interrupt Request (AFEIFIR): Indicates whether a AFEIFI (AFE I/F) interrupt
request is generated.
Bit 4: AFEIFIR
Description
0
An AFE I/F interrupt request is not generated
1
An AFE I/F interrupt request is generated
(Initial value)
Bits 3 to 0—Reserved: These bits are always read as 0.
7.3.11
Interrupt Request Register 4 (IRR4)
The IRR4 is a 16-bit read-only register that indicates whether SIOF interrupt requests are
generated. This register is initialized to H'0000 at power-on reset or manual reset, but is not
initialized in standby mode.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
ERI
TXI
RXI
CCI
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 5.00 Dec 12, 2005 page 195 of 1034
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Section 7 Interrupt Controller (INTC)
Bit 3—ERI Interrupt Request (ERI): Indicates whether a ERI (SIOF) interrupt request is
generated.
Bit 3: ERI
Description
0
ERI interrupt request is not generated
1
ERI interrupt request is generated
(Initial value)
Bit 2—TXI Interrupt Request (TXI): Indicates whether a TXI (SIOF) interrupt request is
generated.
Bit 2:TXI
Description
0
TXI interrupt request is not generated
1
TXI interrupt request is generated
(Initial value)
Bit 1—RXI Interrupt Request (RXI): Indicates whether a RXI (SIOF) interrupt request is
generated.
Bit 1: RXI
Description
0
RXI interrupt request is not generated
1
RXI interrupt request is generated
(Initial value)
Bit 0—CCI Interrupt Request (CCI): Indicates whether a CCI (CCI) interrupt request is
generated.
Bit 0: CCI
Description
0
CCI interrupt request is not generated
1
CCI interrupt request is generated
Rev. 5.00 Dec 12, 2005 page 196 of 1034
REJ09B0254-0500
(Initial value)
Section 7 Interrupt Controller (INTC)
7.4
INTC Operation
7.4.1
Interrupt Sequence
The sequence of interrupt operations is explained below. Figure 7.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt from the interrupt requests sent,
following the priority levels set in interrupt priority registers A to G (IPRA to IPRG). Lower
priority interrupts are held pending. If two of these interrupts have the same priority level or if
multiple interrupts occur within a single module, the interrupt with the highest default priority
or the highest priority within its IPR setting unit (as indicated in tables 7.4 and 7.5) is selected.
3. The priority level of the interrupt selected by the interrupt controller is compared with the
interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level
is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends
an interrupt request signal to the CPU.
4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in
synchronization with the peripheral clock (Pφ). The CPU receives an interrupt at a break in
instructions.
5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2).
6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively.
7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1.
8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the
vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt
handler may branch with the INTEVT and INTEVT2 register value as its offset in order to
identify the interrupt source. This enables it to branch to the processing routine for the
individual interrupt source.
Notes: 1. The interrupt mask bits (I3 to I0) in the status register (SR) are not changed by
acceptance of an interrupt in the SH7727.
2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an
interrupt request that should have been cleared is not inadvertently accepted again, read
the interrupt source flag after it has been cleared, then wait for the interval shown in
table 7.8 (Time for priority decision and SR mask bit comparison) before clearing the
BL bit or executing an RTE instruction.
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Section 7 Interrupt Controller (INTC)
Program
execution state
ICR1.MAI = 1?
No
No
Interrupt
generated?
Yes
NMI = low?
Yes
No
Yes
No
ICR1.BLMSK = 1?
No
SR.BL= 0
or sleep mode?
Yes
Yes
No
NMI?
Yes
NMI?
Yes
No
Level 15
interrupt?
Yes
Yes
I3−I0 level
14 or lower?
Set interrupt cause in
INTEVT, INTEVT2
No
Yes
Save SR to SSR;
save PC to SPC
No
Level 14
interrupt?
Yes
I3−I0 level
13 or lower?
No
Yes
No
Level 1
interrupt?
Yes
I3−I0
level 0?
No
Set BL/MD/RB
bits in SR to 1
Branch to exception
handler
I3−I0: Interrupt mask bits in status register (SR)
Figure 7.3 Interrupt Operation Flowchart
Rev. 5.00 Dec 12, 2005 page 198 of 1034
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No
Section 7 Interrupt Controller (INTC)
7.4.2
Multiple Interrupts
When processing multiple interrupts, an interrupt handler should include the following
procedures:
1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2.
The code in INTEVT and INTEVT2 can be used as a branch-offset for branching to the
specific handler.
2. Clear the cause of the interrupt in each specific handler.
3. Save SSR and SPC to the memory.
4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR.
5. Handle the interrupt.
6. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted after clearing BL in step 4.
7.5
Interrupt Response Time
The time from generation of an interrupt request until interrupt exception handling is performed
and fetching of the first instruction of the exception handler is started (the interrupt response time)
is shown in table 7.8. Figure 7.4 shows an example of pipeline operation when an IRL interrupt is
accepted. When SR.BL is 1, interrupt exception handling is masked, and is kept waiting until
completion of an instruction that clears BL to 0.
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Section 7 Interrupt Controller (INTC)
Table 7.8
Interrupt Response Time
Number of States
Item
NMI
IRQ
PINT
Time for priority
decision and SR mask
bit comparison
0.5 × Icyc
+ 0.5 × Bcyc
+ 0.5 × Pcyc
0.5 × Icyc
0.5 × Icyc
+ 1 × Bcyc
+ 3.5 × Pcyc
+ 4.5 × Pcyc*4
Peripheral
Modules
Notes
0.5 × Icyc
+ 1.5 × Pcyc*5
0.5 × Icyc
+ 3 × Pcyc*6
Wait time until end of
sequence being
executed by CPU
X (≥ 0) × Icyc X (≥ 0) × Icyc X (≥ 0) × Icyc X (≥ 0) × Icyc
Time from interrupt
exception handling
(save of SR and PC)
until fetch of first
instruction of
exception handler is
started
5 × Icyc
5 × Icyc
Rev. 5.00 Dec 12, 2005 page 200 of 1034
REJ09B0254-0500
5 × Icyc
5 × Icyc
Interrupt exception
handling is kept
waiting until the
executing instruction
ends. If the number of
instruction execution
states is S*1, the
maximum wait time is:
X = S – 1.
However, if BL is set to
1 by instruction
execution or by an
exception, interrupt
exception handling is
deferred until
completion of an
instruction that clears
BL to 0. If the following
instruction masks
interrupt exception
handling, the
processing may be
further deferred.
Section 7 Interrupt Controller (INTC)
Number of States
Item
Response
time
Total
NMI
IRQ
PINT
Peripheral
Modules
(5.5 + X)
× Icyc + 0.5
× Bcyc + 0.5
× Pcyc
(5.5 + X)
× Icyc + 1
× Bcyc + 4.5
× Pcyc*4
(5.5 + X)
× Icyc + 3.5
× Pcyc*5
(5.5 + X)
× Icyc + 1.5
× Pcyc*5
Notes
(5.5 + X)
× Icyc + 3
× Pcyc*6
Minimum
case*2
7.5
16.5
12.5
8.5*5/11.5*6
At 60-MHz (CKIO =
30) operation:
0.13–0.28 µs
Maximum
case*3
8.5 + S
26.5 + S
18.5 + S
10.5 + S*5
16.5 + S*6
At 60-MHz (CKIO =
15) operation:
0.26–0.56 µs (in case
of operand cache-hit)
At 60-MHz (CKIO =
15) operation:
0.29–0.59 µs (when
external memory
access is performed
with wait = 0)
Icyc: Duration of one cycle of internal clock supplied to CPU.
Bcyc: Duration of one CKIO cycle.
Pcyc: Duration of one cycle of peripheral clock supplied to peripheral modules.
Notes: 1. S also includes the memory access wait time.
The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the
memory access is a cache-hit, this requires seven instruction execution cycles. When
the external access is performed, the corresponding number of cycles must be added.
There are also instructions that perform two external memory accesses; if the external
memory access is slow, the number of instruction execution cycles will increase
accordingly.
2. The internal clock: CKIO: peripheral clock ratio is 2:1:1.
3. The internal clock: CKIO: peripheral clock ratio is 4:1:1.
4. IRQ mode
5. Modules: TMU, RTC, SCI, WDT, REFC
6. Modules: DMAC, ADC, SCIF, LCDC, PCC, USB host, USB function, AFE interface
Rev. 5.00 Dec 12, 2005 page 201 of 1034
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Section 7 Interrupt Controller (INTC)
Interrupt
acceptance
Start of interrupt
processing
0.5 × Icyc
+ 0.5 × Bcyc
+ 2 × Pcyc
5 × Icyc
IRL
Instruction (instruction
replaced by interrupt
exception processing)
IF
Overrun fetch
ID
EX
EX
EX
EX
IF
First instruction of interrupt
handler
IF
ID
EX
IF: Instruction fetch: Instruction is fetched from memory in which program is stored.
ID: Instruction decode: Fetched instruction is decoded.
EX: Instruction execution: Data operation and address calculation are performed in
accordance with result of decoding.
Figure 7.4 Example of Pipeline Operations when IRL Interrupt is Accepted
Rev. 5.00 Dec 12, 2005 page 202 of 1034
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Section 8 User Break Controller
Section 8 User Break Controller
8.1
Overview
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and timing in the
case of instruction fetch.
8.1.1
Features
The UBC has the following features:
• The following break comparison conditions can be set.
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and, then channel B match with logical AND, but
not in the same bus cycle).
Address (Compares 40 bits comprised of a 32-bit logical address prefixed with an ASID
address
Comparison bits are maskable in 32-bit units, user can easily program it to mask addresses
at bottom 12 bits (4-k page), bottom 10 bits (1-k page), or any size of page, etc.
The 8-bit ASID checking is from MMU control to indicate hit or not hit.)
One of four address buses (CPU address bus (LAB), cache address bus (IAB),
X-memory address bus (XAB) and Y-memory address bus (YAB)) can be selected.
Data (only on channel B, 32-bit maskable)
One of the four data buses (CPU data bus (LDB), cache data bus (IDB), X-memory data
bus (XDB) and Y-memory data bus (YDB)) can be selected.
Bus master: CPU cycle or DMAC cycle
Bus cycle: instruction fetch or data access
Read/write
Operand size: byte, word, or longword
• User break is generated upon satisfying break conditions. A user-designed user-break
condition exception processing routine can be run.
• In an instruction fetch cycle, it can be selected that a break is set before or after an instruction
is executed.
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Section 8 User Break Controller
• Maximum repeat times for the break condition: 212 – 1 times. (It is only for channel B)
• Eight pairs of branch source/destination buffers.
8.1.2
Block Diagram
Figure 8.1 is a block diagram of the UBC.
Access
Control
XAB/YAB
IAB
LAB
MDB
Access
comparator
BBRA
BARA
Address
comparator
BAMRA
ASID
comparator
BASRA
Channel A
Access
comparator
BBRB
BARB
Address
comparator
BAMRB
ASID
comparator
BASRB
BDRB
Data
comparator
Channel B
BDMRB
BETR
BRSR
PC Trace
BRDR
BRCR
CONTROL
LDB/IDB/
XDB/YDB
CPU state
signals
User break request
UBC Location
Legend
BBRA:
BARA:
BAMRA:
BASRA:
BBRB:
BARB:
BAMRB:
Break bus cycle register A
Break address register A
Break address mask register A
Break ASID register A
Break bus cycle register B
Break address register B
Break address mask register B
BASRB:
BDRB:
BDMRB:
BETR:
BRSR:
BRDR:
BRCR:
CCN Location
Break ASID register B
Break data register B
Break data mask register B
Break execution times register
Branch source register
Branch destination register
Break control register
Figure 8.1 Block Diagram of User Break Controller
Rev. 5.00 Dec 12, 2005 page 204 of 1034
REJ09B0254-0500
Section 8 User Break Controller
8.1.3
Table 8.1
Register Configuration
Register Configuration
Name
Abbr.
R/W
Initial
1
Value*
Address
Access
Size
Location
Break address register A
BARA
R/W
H'00000000
H'FFFFFFB0
32
UBC
Break address mask
register A
BAMRA
R/W
H'00000000
H'FFFFFFB4
32
UBC
Break bus cycle register A
BBRA
R/W
H'0000
H'FFFFFFB8
16
UBC
Break address register B
BARB
R/W
H'00000000
H'FFFFFFA0
32
UBC
Break address mask
register B
BAMRB
R/W
H'00000000
H'FFFFFFA4
32
UBC
Break bus cycle register B
BBRB
R/W
H'0000
H'FFFFFFA8
16
UBC
Break data register B
BDRB
R/W
H'00000000
H'FFFFFF90
32
UBC
Break data mask register B
BDMRB
R/W
H'00000000
H'FFFFFF94
32
UBC
Break control register
BRCR
R/W
H'00000000
H'FFFFFF98
32
UBC
Execution count break
register
BETR
R/W
H'0000
H'FFFFFF9C
16
UBC
Branch source register
BRSR
R
H'FFFFFFAC 32
UBC
Branch destination register
BRDR
R
Undefined*
2
Undefined*
H'FFFFFFBC 32
UBC
Break ASID register A
BASRA
R/W
Undefined
H'FFFFFFE4
8
CCN
Break ASID register B
BASRB
R/W
Undefined
H'FFFFFFE8
8
CCN
2
Notes: 1. Initialized by power-on reset. Values held in standby state and undefined by manual
resets.
2. Bit 31 of BRSR and BRDR (valid flag) is initialized by power-on resets. But other bits
are not initialized.
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Section 8 User Break Controller
8.2
Register Descriptions
8.2.1
Break Address Register A (BARA)
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BAA
31
BAA
30
BAA
29
BAA
28
BAA
27
BAA
26
BAA
25
BAA
24
BAA
23
BAA
22
BAA
21
BAA
20
BAA
19
BAA
18
BAA
17
BAA
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BAA
15
BAA
14
BAA
13
BAA
12
BAA
11
BAA
10
BAA
9
BAA
8
BAA
7
BAA
6
BAA
5
BAA
4
BAA
3
BAA
2
BAA
1
BAA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BARA is a 32-bit read/write register. BARA specifies the address used as a break condition in
channel A. A power-on reset initializes BARA to H'00000000.
Bits 31 to 0—Break Address A31 to A0 (BAA31 to BAA0): Stores the address on the LAB or
IAB specifying break conditions of channel A.
8.2.2
Break Address Mask Register A (BAMRA)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value:
R/W:
Bit:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address
specified by BARA. A power-on reset initializes BAMRA to H'00000000.
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Section 8 User Break Controller
Bits 31 to 0—Break Address Mask Register A31 to A0 (BAMA31 to BAMA0): Specifies bits
masked in the channel A break address bits specified by BARA (BAA31 to BAA0).
Bits 31 to 0:
BAMAn
Description
0
Break address bit BAAn of channel A is included in the break condition
(Initial value)
1
Break address bit BAAn of channel A is masked and is not included in the break
condition
n = 31 to 0
8.2.3
Break Bus Cycle Register A (BBRA)
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
7
6
5
4
3
2
1
0
CDA1 CDA0 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the
break conditions of channel A. A power-on reset initializes BBRA to H'0000.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU Cycle/DMAC Cycle Select A (CDA1, CDA0): Selects the CPU cycle or
DMAC cycle as the bus cycle of the channel A break condition.
Bit 7: CDA1
Bit 6: CDA0
Description
0
0
Condition comparison is not performed
*
1
The break condition is the CPU cycle
1
0
The break condition is the DMAC cycle
(Initial value)
Note: * Don’t care
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Section 8 User Break Controller
Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1, IDA0): Selects the instruction
fetch cycle or data access cycle as the bus cycle of the channel A break condition.
Bit 5: IDA1
Bit 4: IDA0
Description
0
0
Condition comparison is not performed
1
The break condition is the instruction fetch cycle
0
The break condition is the data access cycle
1
The break condition is the instruction fetch cycle or data access
cycle
1
(Initial value)
Bits 3 and 2—Read/Write Select A (RWA1, RWA0): Selects the read cycle or write cycle as the
bus cycle of the channel A break condition.
Bit 3: RWA1
Bit 2: RWA0
Description
0
0
Condition comparison is not performed
1
The break condition is the read cycle
1
0
The break condition is the write cycle
1
The break condition is the read cycle or write cycle
(Initial value)
Bits 1 and 0—Operand Size Select A (SZA1, SZA0): Selects the operand size of the bus cycle
for the channel A break condition.
Bit 1: SZA1
Bit 0: SZA0
Description
0
0
The break condition does not include operand size
(Initial value)
1
The break condition is byte access
0
The break condition is word access
1
The break condition is longword access
1
Rev. 5.00 Dec 12, 2005 page 208 of 1034
REJ09B0254-0500
Section 8 User Break Controller
8.2.4
Break Address Register B (BARB)
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BAB
31
BAB
30
BAB
29
BAB
28
BAB
27
BAB
26
BAB
25
BAB
24
BAB
23
BAB
22
BAB
21
BAB
20
BAB
19
BAB
18
BAB
17
BAB
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BAB
15
BAB
14
BAB
13
BAB
12
BAB
11
BAB
10
BAB
9
BAB
8
BAB
7
BAB
6
BAB
5
BAB
4
BAB
3
BAB
2
BAB
1
BAB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in
channel B. Control bits XYE and XYS in the BBRB selects an address bus for break condition B.
If the XYE is 0, then BARB specifies the break address on logic or internal bus, LAB or IAB. If
the XYE is 1, then the BAB31 to 16 specifies the break address on XAB (bits 15 to 1) and the
BAB15 to 0 specifies the break address on YAB (bits 15 to 1). However, you have to choose one
of two address buses for the break. A power-on reset initializes BARB to H'00000000.
BAB31 to 16
BAB15 to 0
XYE = 0
L(I) AB31 to 16
L(I) AB15 to 0
XYE = 1
XAB15 to 1 (XYS = 0)
YAB15 to 1 (XYS = 1)
Rev. 5.00 Dec 12, 2005 page 209 of 1034
REJ09B0254-0500
Section 8 User Break Controller
8.2.5
Break Address Mask Register B (BAMRB)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BAMRB is a 32-bit read/write register. BAMRB specifies bits masked in the break address
specified by BARB. A power-on reset initializes BAMRB to H'00000000.
BAMB31 to 16
BAMB15 to 0
XYE = 0
Mask L(I) AB31 to 16
Mask L(I) AB15 to 0
XYE = 1
Mask XAB15 to 1 (XYS = 0)
Mask YAB15 to 1 (XYS = 1)
Bits 31 to 0:
BAMBn
Description
0
Break address BABn of channel B is included in the break condition (Initial value)
1
Break address BABn of channel B is masked and is not included in the break
condition
n = 31 to 0
Rev. 5.00 Dec 12, 2005 page 210 of 1034
REJ09B0254-0500
Section 8 User Break Controller
8.2.6
Break Data Register B (BDRB)
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BDB
31
BDB
30
BDB
29
BDB
28
BDB
27
BDB
26
BDB
25
BDB
24
BDB
23
BDB
22
BDB
21
BDB
20
BDB
19
BDB
18
BDB
17
BDB
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BDB
15
BDB
14
BDB
13
BDB
12
BDB
11
BDB
10
BDB
9
BDB
8
BDB
7
BDB
6
BDB
5
BDB
4
BDB
3
BDB
2
BDB
1
BDB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BDRB is a 32-bit read/write register. The control bits XYE and XYS in BBRB select a data bus
for break condition B. If the XYE is 0, then BDRB specifies the break data on LDB or IDB. If the
XYE is 1, then BDB 31 to 16 specifies the break data on XDB (bits 15 to 0) and BDB 15 to 0
specifies the break data on YDB (bits 15 to 0). However, you have to choose one of two data
buses for the break. A power-on reset initializes BDRB to H'00000000.
BDB31 to 16
BDB15 to 0
XYE = 0
L(I) DB31 to 16
L(I) DB15 to 0
XYE = 1
XDB15 to 0 (XYS = 0)
YDB15 to 0 (XYS = 1)
Rev. 5.00 Dec 12, 2005 page 211 of 1034
REJ09B0254-0500
Section 8 User Break Controller
8.2.7
Break Data Mask Register B (BDMRB)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified
by BDRB. A power-on reset initializes BDMRB to H'00000000.
BDMB31 to 16
BDMB15 to 0
XYE = 0
Mask L(I) DB31 to 16
Mask L(I) DB15 to 0
XYE = 1
Mask XDB15 to 0 (XYS = 0)
Mask YDB15 to 0 (XYS = 1)
Bits 31 to 0:
BDMBn
Description
0
Break data BDBn of channel B is included in the break condition
1
Break data BDBn of channel B is masked and is not included in the break
condition
(Initial value)
n = 31 to 0
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
2. When a byte size is selected as a break condition, the same break data (byte size)
must be set both in bits 15 to 8 and in bits 7 to 0 in BDRB.
Rev. 5.00 Dec 12, 2005 page 212 of 1034
REJ09B0254-0500
Section 8 User Break Controller
8.2.8
Break Bus Cycle Register B (BBRB)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
XYE
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XYS CDB1 CDB0 IDB1 IDB0 RWB1 RWB0 SZB1 SZB0
Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies (1) logic or
internal bus (L or I bus), X bus, of Y bus, (2) CPU cycle or DMAC cycle, (3) instruction fetch or
data access, (4) read/write, and (5) operand size in the break conditions of channel B. A power-on
reset initializes BBRB to H'0000.
Bits 15 to 10—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 9—X/Y Memory Bus Enable (XYE): Selects the logic bus or internal bus (L bus or I bus) or
the X/Y memory bus as the bus of the channel B break condition.
Bit 9: XYE
Description
0
Select internal bus (I bus) for the channel B break condition
1
Select X/Y memory bus (X/Y bus) for the channel B break condition
Bits 8—X or Y Memory Bus Select (XYS): Selects the X bus or the Y bus as the bus of the
channel B break condition.
Bit 8: XYS
Description
0
Select the X bus for the channel B break condition
1
Select the Y bus for the channel B break condition
Bits 7 and 6—CPU Cycle/DMAC Cycle Select B (CDB1 and CDB0): Select the CPU cycle or
DMAC cycle as the bus cycle of the channel B break condition.
Bit 7: CDB1
Bit 6: CDB0
Description
0
0
Condition comparison is not performed
*
1
The break condition is the CPU cycle
1
0
The break condition is the DMAC cycle
(Initial value)
Note: * Don’t care.
Rev. 5.00 Dec 12, 2005 page 213 of 1034
REJ09B0254-0500
Section 8 User Break Controller
Bits 5 and 4—Instruction Fetch/Data Access Select B (IDB1 and IDB0): Select the instruction
fetch cycle or data access cycle as the bus cycle of the channel B break condition.
Bit 5: IDB1
Bit 4: IDB0
Description
0
0
Condition comparison is not performed
1
The break condition is the instruction fetch cycle
0
The break condition is the data access cycle
1
The break condition is the instruction fetch cycle or data access
cycle
1
(Initial value)
Bits 3 and 2—Read/Write Select B (RWB1 and RWB0): Select the read cycle or write cycle as
the bus cycle of the channel B break condition.
Bit 3: RWB1
Bit 2: RWB0
Description
0
0
Condition comparison is not performed
1
The break condition is the read cycle
1
0
The break condition is the write cycle
1
The break condition is the read cycle or write cycle
(Initial value)
Bits 1 and 0—Operand Size Select B (SZB1 and SZB0): Select the operand size of the bus
cycle for the channel B break condition.
Bit 1: SZB1
Bit 0: SZB0
Description
0
0
The break condition does not include operand size (Initial
value)
1
The break condition is byte access
0
The break condition is word access
1
The break condition is longword access
1
Rev. 5.00 Dec 12, 2005 page 214 of 1034
REJ09B0254-0500
Section 8 User Break Controller
8.2.9
Break Control Register (BRCR)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
—
—
—
—
—
—
—
—
—
—
BAS
MA
BAS
MB
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R
R
R
R
15
14
13
12
11
10
7
6
Bit:
SCM SCM SCM SCM PCTE PCBA
FCA FCB FDA FDB
Initial value:
R/W:
9
8
—
—
DBEB PCBB
5
4
3
2
1
0
—
—
SEQ
—
—
ETBE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R
R
R/W
R
R
R/W
BRCR sets the following conditions:
1. Channels A and B are used in two independent channels condition or under the sequential
condition.
2. A break is set before or after instruction execution.
3. A break is set by the number of execution times.
4. Determine whether to include data bus on channel B in comparison conditions.
5. Enable PC trace.
6. Enable the ASID check.
The break control register (BRCR) is a 32-bit read/write register that has break conditions match
flags and bits for setting a variety of break conditions.
A power-on reset initializes BRCR to H'00000000.
Bits 31 to 22—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 21—Break ASID Mask A (BASMA): Specifies whether the bits of the channel A break
ASID7 to ASID0 (BASA7 to BASA0) set in BASRA are masked or not.
Bit 21: BASMA Description
0
All BASRA bits are included in break condition, and ASID is checked
(Initial value)
1
No BASRA bits are included in break condition, and ASID is not checked
Rev. 5.00 Dec 12, 2005 page 215 of 1034
REJ09B0254-0500
Section 8 User Break Controller
Bit 20—Break ASID Mask B (BASMB): Specifies whether the bits of channel B break ASID7
to ASID0 (BASB7 to BASB0) set in BASRB are masked or not.
Bit 20: BASMB Description
0
All BASRB bits are included in break condition, and ASID is checked
(Initial value)
1
No BASRB bits are included in break condition, and ASID is not checked
Bits 19 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 15—CPU Condition Match Flag A (SCMFCA): When the CPU bus cycle condition in the
break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to
clear this flag, write 0 into this bit.
Bit 15:
SCMFCA
Description
0
The CPU cycle condition for channel A does not match
1
The CPU cycle condition for channel A matches
(Initial value)
Bit 14—CPU Condition Match Flag B (SCMFCB): When the CPU bus cycle condition in the
break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to
clear this flag, write 0 into this bit.
Bit 14:
SCMFCB
Description
0
The CPU cycle condition for channel B does not match
1
The CPU cycle condition for channel B matches
(Initial value)
Bit 13—DMAC Condition Match Flag A (SCMFDA): When the on-chip DMAC bus cycle
condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 into this bit.
Bit 13:
SCMFDA
Description
0
The DMAC cycle condition for channel A does not match
1
The DMAC cycle condition for channel A matches
Rev. 5.00 Dec 12, 2005 page 216 of 1034
REJ09B0254-0500
(Initial value)
Section 8 User Break Controller
Bit 12—DMAC Condition Match Flag B (SCMFDB): When the on-chip DMAC bus cycle
condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 into this bit.
Bit 12:
SCMFDB
Description
0
The DMAC cycle condition for channel B does not match
1
The DMAC cycle condition for channel B matches
(Initial value)
Bit 11—PC Trace Enable (PCTE): Enables PC trace.
Bit 11: PCTE
Description
0
Disables PC trace
1
Enables PC trace
(Initial value)
Bit 10—PC Break Select A (PCBA): Selects the break timing of the instruction fetch cycle for
channel A as before or after instruction execution.
Bit 10: PCBA
Description
0
PC break of channel A is set before instruction execution
1
PC break of channel A is set after instruction execution
(Initial value)
Bits 9 and 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Data Break Enable B (DBEB): Selects whether or not the data bus condition is included
in the break condition of channel B.
Bit 7: DBEB
Description
0
No data bus condition is included in the condition of channel B
1
The data bus condition is included in the condition of channel B
(Initial value)
Bit 6—PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for
channel B as before or after instruction execution.
Bit 6: PCBB
Description
0
PC break of channel B is set before instruction execution
1
PC break of channel B is set after instruction execution
(Initial value)
Rev. 5.00 Dec 12, 2005 page 217 of 1034
REJ09B0254-0500
Section 8 User Break Controller
Bits 5 and 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—Sequence Condition Select (SEQ): Selects two conditions of channels A and B as
independent or sequential.
Bit 3: SEQ
Description
0
Channels A and B are compared under the independent condition (Initial value)
1
Channels A and B are compared under the sequential condition
Bits 2 and 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—The Number of Execution Times Break Enable (ETBE): Enable the execution-times
break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the
number of break conditions matches with the number of execution times that is specified by the
BETR register.
Bit 0: ETBE
Description
0
The execution-times break condition is disabled on channel B
1
The execution-times break condition is enabled on channel B
8.2.10
(Initial value)
Execution Times Break Register (BETR)
Bit:
15
14
13
12
—
—
—
—
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When the execution-times break condition of channel B is enabled, this register specifies the
number of execution times to make the break. The maximum number is 212 – 1 times. A power-on
reset initializes BETR to H'0000. When a break condition is satisfied, it decreases the BETR. A
break is issued when the break condition is satisfied after the BETR becomes H'0001. Bits 15 to
12 are always read as 0 and 0 should always be written in these bits.
Rev. 5.00 Dec 12, 2005 page 218 of 1034
REJ09B0254-0500
Section 8 User Break Controller
8.2.11
Branch Source Register (BRSR)
Bit:
31
SVF
30
29
28
PID2 PID1 PID0
27
26
25
24
23
22
21
20
19
18
17
16
BSA
27
BSA
26
BSA
25
BSA
24
BSA
23
BSA
22
BSA
21
BSA
20
BSA
19
BSA
18
BSA
17
BSA
16
Initial value:
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BSA
15
BSA
14
BSA
13
BSA
12
BSA
11
BSA
10
BSA
9
BSA
8
BSA
7
BSA
6
BSA
5
BSA
4
BSA
3
BSA
2
BSA
1
BSA
0
Initial value:
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Note: * Undefined
BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer
(3 bits) which indicates the number of cycles from fetch to execution for the last executed
instruction. BRSR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0,
when BRSR is read and also initialized by power-on resets or manual resets. Other bits are not
initialized by reset. Eight BRSR registers have queue structure and a stored register is shifted
every branch.
Bit 31—BRSR Valid Flag (SVF): Indicates whether the address and the pointer by which the
branch source address can be calculated. When a branch source address is fetched, this flag is set
to 1. This flag is cleared to 0 in reading BRSR.
Bit 31: SVF
Description
0
The value of BRSR register is invalid
1
The value of BRSR register is valid
Bits 30 to 28—Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0 to
7). These bits indicate the instruction buffer number which stores the last executed instruction
before branch.
Bits 30 to 28:
PID
Description
Even
PID indicates the instruction buffer number.
Odd
PiD+2 indicates the instruction buffer number
Rev. 5.00 Dec 12, 2005 page 219 of 1034
REJ09B0254-0500
Section 8 User Break Controller
Bits 27 to 0—Branch Source Address (BSA27 to BSA0): These bits store the last fetched
address before branch.
8.2.12
Branch Destination Register (BRDR)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DVF
—
—
—
BDA
27
BDA
26
BDA
25
BDA
24
BDA
23
BDA
22
BDA
21
BDA
20
BDA
19
BDA
18
BDA
17
BDA
16
Initial value:
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BDA
15
BDA
14
BDA
13
BDA
12
BDA
11
BDA
10
BDA
9
BDA
8
BDA
7
BDA
6
BDA
5
BDA
4
BDA
3
BDA
2
BDA
1
BDA
0
Initial value:
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Note: * Undefined
BRDR is a 32-bit read register. BRDR stores the branch destination fetch address. BRDR has the
flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRDR is read and
also initialized by power-on resets or manual resets. Other bits are not initialized by resets. Eight
BRDR registers have queue structure and a stored register is shifted every branch.
Bit 31—BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored.
When a branch destination address is fetched, this flag is set to 1. This flag is cleared to 0 in
reading BRDR.
Bit 31: DVF
Description
0
The value of BRDR register is invalid
1
The value of BRDR register is valid
Bits 30 to 28—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 27 to 0—Branch Destination Address (BDA27 to BDA0): These bits store the first fetched
address after branch.
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Section 8 User Break Controller
8.2.13
Break ASID Register A (BASRA)
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
BASA7
BASA6
BASA5
BASA4
BASA3
BASA2
BASA1
BASA0
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Undefined
Break ASID register A (BASRA) is an 8-bit read/write register that specifies the ASID that serves
as the break condition for channel A. It is not initialized by resets. It is located in CCN.
Bits 7 to 0—Break ASID A7 to 0 (BASA7 to BASA0): These bits store the ASID (bits 7 to 0)
that is the channel A break condition.
8.2.14
Break ASID Register B (BASRB)
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
BASB7
BASB6
BASB5
BASB4
BASB3
BASB2
BASB1
BASB0
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Undefined
Break ASID register B (BASRB) is an 8-bit read/write register that specifies the ASID that serves
as the break condition for channel B. It is not initialized by resets. It is located in CCN.
Bits 7 to 0: Break ASID A7 to 0 (BASB7 to BASB0): These bits store the ASID (bits 7 to 0) that
is the channel B break condition.
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Section 8 User Break Controller
8.3
Operation Description
8.3.1
Flow of the User Break Operation
The flow from setting of break conditions to user break exception processing is described below:
1. The break addresses and the corresponding ASIDs are loaded in the break address registers
(BARA and BARB) and break ASID registers (BASRA and BASRB in CCN). The masked
addresses are set in the break address mask registers (BAMRA and BAMRB). The break data
is set in the break data register (BDRB). The masked data is set in the break data mask register
(BDMRB). The breaking bus conditions are set in the break bus cycle registers (BBRA and
BBRB). Three groups of the BBRA and BBRB (CPU cycle/DMAC cycle select, instruction
fetch/data access select, and read/write select) are each set. No user break will be generated if
even one of these groups is set with 00. The respective conditions are set in the bits of the
BRCR.
2. When the break conditions are satisfied, the UBC sends a user break request to the interrupt
controller. The break type will be sent to CPU indicating the instruction fetch, pre/post
instruction break, data access break, or on-chip I/O access/LDTLB break. When conditions
match up, the CPU condition match flags (SCMFCA and SCMFCB) and DMAC condition
match flags (SCMFDA and SCMFDB) for the respective channels are set.
3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can
be used to check if the set conditions match or not. The matching of the conditions sets flags,
but they are not reset. 0 must first be written to them before they can be used again.
4. There is a chance that the data access break and its following instruction fetch break occur
around the same time, there will be only one break request to the CPU, but these two break
channel match flags could both be set.
8.3.2
Break on Instruction Fetch Cycle
1. When CPU/instruction fetch/read/word or longword is set in the break bus cycle registers
(BBRA/BBRB), the break condition becomes the CPU instruction fetch cycle. Whether it then
breaks before or after the execution of the instruction can then be selected with the
PCBA/PCBB bits of the break control register (BRCR) for the appropriate channel.
2. An instruction set for a break before execution breaks when it is confirmed that the instruction
has been fetched and will be executed. This means this feature cannot be used on instructions
fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to
be executed). When this kind of break is set for the delay slot of a delay branch instruction, the
break is generated prior to execution of the instruction that then first accepts the break.
Meanwhile, the break set for pre-instruction-break on delay slot instruction and postinstruction-break on SLEEP instruction are also prohibited.
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Section 8 User Break Controller
3. When the condition is specified to be occurred after execution, the instruction set with the
break condition is executed and then the break is generated prior to the execution of the next
instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions.
When this kind of break is set for a delay branch instruction, the break is generated at the
instruction that then first accepts the break.
4. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored.
There is thus no need to set break data for the break of the instruction fetch cycle.
8.3.3
Break by Data Access Cycle
1. The memory cycles in which CPU data access breaks occur are from instructions.
2. The relationship between the data access cycle address and the comparison condition for
operand size are listed in table 8.2:
Table 8.2
Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size
Address Compared
Longword
Compares break address register bits 31 to 2 to address bus bits 31 to 2
Word
Compares break address register bits 31 to 1 to address bus bits 31 to 1
Byte
Compares break address register bits 31 to 0 to address bus bits 31 to 0
This means that when address H'00001003 is set without specifying the size condition, for
example, the bus cycle in which the break condition is satisfied is as follows (where other
conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
3. When the data value is included in the break conditions on B channel:
When the data value is included in the break conditions, either longword, word, or byte is
specified as the operand size of the break bus cycle registers (BBRA and BBRB). When data
values are included in break conditions, a break is generated when the address conditions and
data conditions both match. To specify byte data for this case, set the same data in two bytes at
bits 15 to 8 and bits 7 to 0 of the break data register B (BDRB) and break data mask register B
(BDMRB). When word or byte is set, bits 31 to 16 of BDRB and BDMRB are ignored.
4. When the DMAC data access is included in the break condition:
When the address is included in the break condition on DMAC data access, the operand size of
the break bus cycle registers (BBRA and BBRB) should be byte, word or no operand size
specification. When the data value is included, select either byte or word.
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Section 8 User Break Controller
8.3.4
Break on X/Y-Memory Bus Cycle
1. The break condition on X/Y-memory bus cycle is specified only in channel B. If XYE in
BBRB is set to 1, break address and break data on X/Y-memory bus are selected. At this time,
select X-memory bus or Y-memory bus by specifying XYS in BBRB. The Break condition
cannot include both X-memory and Y-memory at the same time. The break condition is
applied to X/Y-memory bus cycle by specifying CPU/data access/read or write/word or no
operand size specification in the break bus cycle register B (BBRB).
2. When X-memory address is selected as the break condition, specify X-memory address in
upper 16 bits in BARB and BAMRB. When Y-memory address is selected, specify Y-memory
address in lower 16 bits. Specification of X/Y-memory data is the same for BDRB and
BDMRB.
8.3.5
Sequential Break
1. By specifying SEQ in BRCR is set to 1, the sequential break is issued when channel B break
condition matches after channel A break condition matches. A user break is ignored even if
channel B break condition matches before channel A break condition matches. When channels
A and B condition match at the same time, the sequential break is not issued.
2. In sequential break specification, internal/X/Y bus can be selected and the execution times
break condition can be also specified. For example, when the execution times break condition
is specified, the break condition is satisfied at channel B condition match with BETR = H'0001
after channel A condition match.
8.3.6
Value of Saved Program Counter
The PC when a break occurs is saved to the SPC in user breaks. The PC value saved is as follows
depending on the type of break.
1. When instruction fetch (before instruction execution) is specified as a break condition:
The value of the program counter (PC) saved is the address of the instruction that matches the
break condition. The fetched instruction is not executed, and a break occurs before it.
2. When instruction fetch (after instruction execution) is specified as a break condition:
The PC value saved is the address of the instruction to be executed following the instruction in
which the break condition matches. The fetched instruction is executed, and a break occurs
before the execution of the next instruction.
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Section 8 User Break Controller
3. When data access (address only) is specified as a break condition:
The PC value is the address of the instruction to be executed following the instruction that
matched the break condition. The instruction that matched the condition is executed and the
break occurs before the next instruction is executed.
4. When data access (address + data) is specified as a break condition:
The PC value is the start address of the instruction that follows the instruction already executed
when break processing started up. When a data value is added to the break conditions, the
place where the break will occur cannot be specified exactly. The break will occur before the
execution of an instruction fetched around the data access where the break occurred.
8.3.7
PC Trace
1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, repeat, and
interrupt) is generated, the address from which the branch source address can be calculated and
the branch destination address are stored in BRSR and BRDR, respectively. The branch
address and the pointer, which corresponds to the branch, are included in BRSR.
2. The branch address before branch occurs can be calculated from the address and the pointer
stored in BRSR. The expression from BSA (the address in BRSR), PID (the pointer in BRSR),
and IA (the instruction address before branch occurs) is as follows: IA = BSA – 2 * PID.
Notes are needed when an interrupt (a branch) is issued before the branch destination
instruction is executed. In case of the next figure, the instruction “Exec” executed immediately
before branch is calculated by IA = BSA – 2 * PID. However, when branch “branch” has delay
slot and the destination address is 4n + 2 address, the address “Dest” which is specified by
branch instruction is stored in BRSR (Dest = BSA). Therefore, as IA = BSA – 2 * PID is not
applied to this case, this PID is invalid. The case where BSA is 4n + 2 boundary is applied
only to this case and then some cases are classified as follows:
Exec: branch
Dest: instr
Dest
(not executed)
interrupt
Int: interrupt routine
If the PID value is odd, instruction buffer indicates PID+2 buffer. However, these expressions
in this table are accounted for it. Therefore, the true branch source address is calculated with
BSA and PID values stored in BRSR.
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Section 8 User Break Controller
3. The branch address before branch occurrence, IA, has different values due to some kinds of
branch.
a. Branch instruction
The branch instruction address
b. Repeat
The instruction before the last instruction of a repeat loop
Repeat_Start: inst (1);
→ BRDR
inst (2);
:
inst (n-1); → the address calculated from BRSR
Repeat_End:
inst (n);
c. Interrupt
The last instruction executed before interrupt
The top address of interrupt routine is stored in BRDR.
In a repeat loop with instructions less than three, no instruction fetch cycle appears and branch
source address is unknown. Therefore, PC trace is disabled.
4. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the
address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read
BRSR and BRDR in order, the queue only shifts after BRDR is read. When reading BRDR,
longword access should be used. Also, the PC trace has a trace pointer, which initially points
to the bottom of the queues. The first pair of branch addresses will be stored at the bottom of
the queues, then push up when next pairs come into the queues. The trace pointer will points to
the next branch address to be executed, unless it got push out of the queues. When the branch
address has been executed, the trace pointer will shift down to next pair of addresses, until it
reaches the bottom of the queues. After switching the PCTE bit (in BRCR) off and on, the
values in the queues are invalid. The read pointer stay at the position before PCTE is switched,
but the trace pointer restart at the bottom of the queues.
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Section 8 User Break Controller
8.3.8
Usage Examples
Break Condition Specified to a CPU Instruction Fetch Cycle
1. Register specifications
BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300400
Specified conditions: Channel A/channel B independent mode
•
Channel A
Address:
H'00000404, Address mask: H'00000000
Bus cycle: CPU/instruction fetch (after instruction execution)/read (operand size is not
included in the condition)
No ASID check is included
•
Channel B
Address:
H'00008010, Address mask: H'00000006
Data:
H'00000000, Data mask: H'00000000
Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
No ASID check is included
A user break occurs after an instruction of address H'00000404 is executed or before
instructions of adresses H'00008010 to H'00008016 are executed.
2. Register specifications
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B sequence mode
•
Channel A
Address:
H'00037226, Address mask: H'00000000, ASID = H'80
Bus cycle: CPU/instruction fetch (before instruction execution)/read/word
•
Channel B
Address:
H'0003722E, Address mask: H'00000000, ASID = H'70
Data:
H'00000000, Data mask: H'00000000
Bus cycle: CPU/instruction fetch (before instruction execution)/read/word
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Section 8 User Break Controller
An instruction with ASID = H'80 and address H'00037226 is executed, and a user break occurs
before an instruction with ASID = H'70 and address H'0003722E is executed.
3. Register specifications
BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415,
BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300000
Specified conditions: Channel A/channel B independent mode
•
Channel A
Address:
H'00027128, Address mask: H'00000000
Bus cycle: CPU/instruction fetch (before instruction execution)/write/word
No ASID check is included
•
Channel B
Address:
H'00031415, Address mask: H'00000000
Data:
H'00000000, Data mask: H'00000000
Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
No ASID check is included
On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B,
no user break occurs since instruction fetch is performed for an even address.
4. Register specifications
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B sequence mode
•
Channel A
Address:
H'00037226, Address mask: H'00000000, ASID: H'80
Bus cycle: CPU/instruction fetch (before instruction execution)/write/word
•
Channel B
Address:
H'0003722E, Address mask: H'00000000, ASID: H'70
Data:
H'00000000, Data mask: H'00000000
Bus cycle: CPU/instruction fetch (before instruction execution)/read/word
Since instruction fetch is not a write cycle on channel A, a sequence condition does not match.
Therefore, no user break occurs.
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Section 8 User Break Controller
5. Register specifications
BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000,
BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300001, BETR = H'0005
Specified conditions: Channel A/channel B independent mode
•
Channel A
Address:
H'00000500, Address mask: H'00000000
Bus cycle: CPU/instruction fetch (before instruction execution)/read/longword
•
Channel B
Address:
H'00001000, Address mask: H'00000000
Data:
H'00000000, Data mask: H'00000000
Bus cycle: CPU/instruction fetch (before instruction execution)/read/longword
The number of execution-times break enable (5 times)
On channel A, a user break occurs before an instruction of address H'00000500 is executed.
On channel B, a user break occurs before the fifth instruction execution after instructions of
address H'00001000 are executed four times.
6. Register specifications
BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000400, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
•
Channel A
Address:
H'00008404, Address mask: H'00000FFF, ASID: H'80
Bus cycle: CPU/instruction fetch (after instruction execution)/read (operand size is not
included in the condition)
•
Channel B
Address:
H'00008010, Address mask: H'00000006, ASID: H'70
Data:
H'00000000, Data mask: H'00000000
Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
A user break occurs after an instruction with ASID = H'80 and address H'00008000 to
H'00008FFE is executed or before instructions with ASID = H'70 and addresses H'00008010
to H'00008016 are executed.
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Section 8 User Break Controller
Break Condition Specified to a CPU Data Access Cycle
1. Register specifications
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE,
BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
•
Channel A
Address:
H'00123456, Address mask: H'00000000, ASID: H'80
Bus cycle: CPU/data access/read (operand size is not included in the condition)
•
Channel B
Address:
H'000ABCDE, Address mask: H'000000FF, ASID: H'70
Data:
H'0000A512, Data mask: H'00000000
Bus cycle: CPU/data access/write/word
On channel A, a user break occurs with ASID = H'80 during longword read to address
H'00123454, word read to address H'00123456, or byte read to address H'00123456. On
channel B, a user break occurs with ASID = H'70 when word H'A512 is written in addresses
H'000ABC00 to H'000ABCFE.
2. Register specifications
BARA = H'01000000, BAMRA = H'00000000, BBRA = H'0066, BARB = H'0000F000,
BAMRB = H'FFFF0000, BBRB = H'036A, BDRB = H'00004567, BDMRB = H'00000000,
BRCR = H'00300080
Specified conditions: Channel A/channel B independent mode
•
Channel A
Address:
H'01000000, Address mask: H'00000000
Bus cycle: CPU/data access/read/word
No ASID check is included
•
Channel B
Y Address: H'0001F000, Address mask: H'FFFF0000
Data:
H'00004567, Data mask: H'00000000
Bus cycle: CPU/data access/write/word
No ASID check is included
On channel A, a user break occurs during word read to address H'01000000 on the memory
space. On channel B, a user break occurs when word H'4567 is written in address H'0001F000
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Section 8 User Break Controller
on Y memory space. The X/Y-memory space is changed by a mode specification.
Break Condition Specified to a DMAC Data Access Cycle
1. Register specifications
BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555,
BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00000078, BDMRB = H'0000000F,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
•
Channel A
Address:
H'00314156, Address mask: H'00000000, ASID: H'80
Bus cycle: DMAC/instruction fetch/read (operand size is not included in the condition)
•
Channel B
Address:
H'00055555, Address mask: H'00000000, ASID: H'70
Data:
H'00000078, Data mask: H'0000000F
Bus cycle: DMAC/data access/write/byte
On channel A, no user break occurs since instruction fetch is not performed in DMAC cycles.
On channel B, a user break occurs with ASID = H'70 when the DMAC writes byte H'7* in
address H'00055555.
8.3.9
Usage Notes
1. Only CPU can read/write UBC registers.
2. UBC cannot monitor CPU and DMAC access in the same channel.
3. Notes in specification of sequential break are described below:
(1) A condition match occurs when B-channel match occurs in a bus cycle after an A-channel
match occurs in another bus cycle in sequential break setting. Therefore, no condition
match occurs even if a bus cycle, in which an A-channel match and a channel B match
occur simultaneously, is set.
(2) Since the CPU has a pipeline configuration, the pipeline determines the order of an
instruction fetch cycle and a memory cycle. Therefore, when a channel condition matches
in the order of bus cycles, a sequential condition is satisfied.
(3) When the bus cycle condition for channel A is specified as a break before execution
(PCBA = 0 in BRCR) and an instruction fetch cycle (in BBRA), the attention is as follows.
A break is issued and condition match flags in BRCR are set to 1, when the bus cycle
conditions both for channels A and B match simultaneously.
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Section 8 User Break Controller
4. The change of a UBC register value is executed in MA (memory access) stage. Therefore,
even if the break condition matches in the instruction fetch address following the instruction in
which the pre-execution break is specified as the break condition, no break occurs. In order to
know the timing UBC register is changed, read the last written register. Instructions after then
are valid for the newly written register value.
5. Notes in specifying the instruction during repeat execution with repeat instruction as the break
condition are as follows: When the instruction during repeat execution is specified as the break
condition,
(1) The break is not issued during repeat execution, which has fewer than three instructions.
(2) When the execution times break is set, no instruction fetch from memory occurs during
repeat execution under three instructions. Therefore, the execution times register BETR is
not decreased.
6. The branch instruction should not be executed as soon as PC trace register BRSR and BRDR
are read.
7. When PC breaks and TLB exceptions or errors occur in the same instruction. The priority is as
follows:
(1) Break and instruction fetch exceptions: Instruction fetch exception occurs first.
(2) Break before execution and operand exception: Break before execution occurs first.
(3) Break after execution and operand exception: Operand exception occurs first.
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Section 9 Power-Down Modes and Software Reset
Section 9 Power-Down Modes and Software Reset
9.1
Overview
In the power-down modes, all CPU and some on-chip supporting module functions are halted.
This lowers power consumption. In particular, the X/Y memory can be stopped to significantly
reduce power consumption. Software reset function enables each module to reset itself.
9.1.1
Power-Down Modes
The SH7727 has three power-down modes:
1. Sleep mode
2. Standby mode
3. Module standby function (TMU, RTC, SCI, X/Y memory, UBC, DMAC, DAC, ADC, SCIF,
LCDC, PCC, USBH, USBF, AFEIF, and SIOF on-chip supporting modules)
4. Hardware standby mode
Table 9.1 shows the transition conditions for entering any mode from the program execution state,
the CPU and supporting module states in each mode, and the procedures for canceling each mode.
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Section 9 Power-Down Modes and Software Reset
Table 9.1
Power-Down Modes
State
Mode
Transition
Conditions
CPG CPU
CPU
On-Chip
Register Memory
On-Chip
Supporting
Modules
Pins
External
Memory
Canceling
Procedure
Sleep
mode
Execute
Runs Halts
SLEEP
instruction
with STBY bit
cleared to 0
in STBCR*7
Held
Held
Run
Held
Refresh
1. Interrupt
2. Reset
Standby
mode
Execute
Halts Halts
SLEEP
instruction
with STBY bit
set to 1 in
STBCR*4 *5
Held
Held
Halt*1
Held
Selfrefresh
1. Interrupt
2. Reset
Module
standby
function
Set MSTP bit Runs Runs
of STBCR
or
to 1*6
halts
Held
Held
*2
Specified
module halts
Refresh
1. Clear
MSTP bit
to 0
2. Reset
Hardware Drive CA pin Halts Halts
standby low
mode
Held
Held
Halt*3
Selfrefresh
Power-on
reset
Held
Notes: 1. The RTC runs if the START bit in RCR2 is set to 1 (see section 16, Realtime Clock
(RTC)). TMU runs when output of the RTC is used as input to its counter (see section
15, Timer (TMU)).
2. Depends on the on-chip supporting module.
TMU external pin: Held
SCI external pin: Reset
3. The RTC runs if the START bit in RCR2 is set to 1. TMU does not run.
4. USB and LCDC must be stopped before entering standby mode.
1) To stop LCDC, set 0 to DON bit.
2) To stop the USB Host Controller, set USBRESET bit in the HcControl register.
5. For LCDC, refer to the LPS bit in LDPMMR to confirm that power-off sequence has
been completed before entering standby-mode.
6. When putting the RTC into module standby mode, first access one or more of registers
RTC, SCI, and TMU. Then put the RTC into module standby mode.
7. Do not cause the CPU to transition to sleep mode, or cancel sleep mode, during a
transmit or receive operation in which the USB function controller or SIOF uses DMA.
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Section 9 Power-Down Modes and Software Reset
9.1.2
Pin Configuration
Table 9.2 lists the pins used for the power-down modes.
Table 9.2
Pin Configuration
Pin Name
Symbol
I/O
Description
Processing state 1
STATUS1
O
Indicate operating state of the processor.
Processing state 0
STATUS0
O
HH: Reset, HL: Sleep mode, LH: Standby mode,
LL: Normal operation
Note: H means high level, and L means low level.
9.1.3
Register Configuration
Table 9.3 shows the configuration of the control register for the power-down modes.
Table 9.3
Register Configuration
Name
Standby control register
Standby control register 2
Abbreviation R/W
STBCR
STBCR2
Address
Access Size
H'00
*1
H'FFFFFF82
8
R/W
H'00
*1
H'FFFFFF88
8
H’04000230
8
2
(H’A4000230)*
H’04000232
8
2
(H’A4000232)*
R/W
Initial Value
Standby control register 3
STBCR3
R/W
1
H'00*
Software reset register
SRSTR
R/W
H'00*
1
Notes: 1. Initialized by power-on resets. Not initialized by manual resets but the contents are
held.
2. The addresses in parentheses ( ) should be used when no address translation by the
MMU is involved.
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Section 9 Power-Down Modes and Software Reset
9.2
Register Description
9.2.1
Standby Control Register (STBCR)
The standby control register (STBCR) is an 8-bit readable/writable register that sets the powerdown mode. STBCR is initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
STBY
—
—
STBXTL
—
MSTP2
MSTP1
MSTP0
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R
R/W
R/W
R/W
Bit 7—Standby (STBY): Specifies transition to standby mode.
Bit 7: STBY
Description
0
Executing SLEEP instruction puts the chip into sleep mode.
1
Executing SLEEP instruction puts the chip into standby mode.
(Initial value)
Bits 6, 5, and 3—Reserved: These bits are always read as 0. The write value should always as 0.
Bit 4—Standby Crystal (STBXTL): Enables/disables crystal oscillation in standby mode.
Bit 4: STBXTL
Description
0
Crystal oscillation in standby mode disabled
1
Crystal oscillation in standby mode enabled
(Initial value)
Bit 2—Module Stop 2 (MSTP2): Specifies halting the clock supply to the timer unit (TMU) in
the on-chip supporting module. When the MSTP2 bit is set to 1, the clock supply to the TMU is
halted.
Bit 2: MSTP2
Description
0
TMU runs.
1
Clock supply to TMU is halted.
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(Initial value)
Section 9 Power-Down Modes and Software Reset
Bit 1—Module Stop 1 (MSTP1): Specifies halting the clock supply to the realtime clock (RTC)
in the on-chip supporting module. When the MSTP1 bit is set to 1, the clock supply to RTC is
halted. When the clock halts, all RTC registers cannot be accessed, but the counter keeps running.
Bit 1: MSTP1
Description
0
RTC runs.
1
Clock supply to RTC is halted.
(Initial value)
Bit 0—Module Stop 0 (MSTP0): Specifies halting the clock supply to the serial communication
interface (SCI) in the on-chip supporting module. When the MSTP0 bit is set to 1, the clock
supply to the SCI is halted.
Bit 0: MSTP0
Description
0
SCI runs.
1
Clock supply to SCI is halted.
9.2.2
(Initial value)
Standby Control Register 2 (STBCR2)
The standby control register 2 (STBCR2) is an 8-bit readable/writable register that controls the
operation of the peripheral modules in the normal mode and sleep mode. STBCR is initialized to
H'00 by a power-on reset.
Bit:
7
6
5
MSTP9 MDCHG MSTP8
Initial value:
R/W:
4
3
2
1
0
MSTP7
MSTP6
MSTP5
MSTP4
—
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Bit 7— Module Stop 9 (MSTP9): Specifies halting the clock supply to the X/Y memory. When
the MSTP9 bit is set to 1, the clock supply to the X/Y memory is halted. Halting of the clock
supply to the X/Y memory must be controlled by software (any access is not blocked by
hardware).
Bit 7: MSTP9
Description
0
X/Y memory runs
1
Clock supply to X/Y memory is halted
(Initial value)
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Section 9 Power-Down Modes and Software Reset
Bit 6—MD5 to MD0 Pin Control (MDCHG): Specifies whether or not pins MD5 to MD0 are
switched in standby mode. When this bit is set to 1, the MD5 to MD0 pin values are latched when
returning from standby mode by means of a reset or interrupt.
Bit 6: MDCHG
Description
0
Pins MD5 to MD0 are not switched in standby mode
1
Pins MD5 to MD0 are switched in standby mode
(Initial value)
Bit 5— Module Stop 8 (MSTP8): Specifies halting the clock supply to the user break controller
(UBC) in the on-chip supporting module. When the MSTP8 bit is set to 1, the clock supply to the
UBC is halted.
Bit 5: MSTP8
Description
0
UBC runs
1
Clock supply to UBC is halted
(Initial value)
Bit 4—Module Stop 7 (MSTP7): Specifies halting of clock supply to the direct memory access
controller (DMAC) in the on-chip supporting module. When the MSTP7 bit is set to 1, the clock
supply to the DMAC is halted.
Bit 4: MSTP7
Description
0
DMAC runs
1
Clock supply to DMAC halted
(Initial value)
Bit 3—Module Stop 6 (MSTP6): Specifies halting of clock supply to the D/A converter (DAC)
in the on-chip supporting module. When the MSTP6 bit is set to 1, the clock supply to the DAC is
halted.
Bit 3: MSTP6
Description
0
DAC runs
1
Clock supply to DAC halted
(Initial value)
Bit 2—Module Stop 5 (MSTP5): Specifies halting of clock supply to the A/D converter (ADC)
in the on-chip supporting module. When the MSTP5 bit is set to 1, the clock supply to the ADC is
halted and all registers are initialized.
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Section 9 Power-Down Modes and Software Reset
Bit 2: MSTP5
Description
0
ADC runs
1
Clock supply to ADC halted, and all registers initialized
(Initial value)
Bit 1—Module Stop 4 (MSTP4): Specifies halting the clock supply to the serial communication
interface SCI (SCIF) with FIFO. When the MSTP4 bit is set to 1, the clock supply to the SCIF is
halted
Bit 1: MSTP4
Description
0
SCIF runs
1
Clock supply to SCI2 (SCIF) halted
(Initial value)
Bit 0— Reserved: This bit is always read as 0. The write value should always as 0.
9.2.3
Standby Control Register 3 (STBCR3)
The standby control register 3 (STBCR3) is an 8-bit readable/writable register that controls
standby operation for the on-chip supporting modules. STBCR3 is initialized to H'00 by a poweron reset.
Bit:
Initial value:
R/W:
7
6
MSTP17
—
5
4
3
MSTP15 MSTP14 MSTP13
2
—
1
0
MSTP11 MSTP10
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7— Module Stop 17 (MSTP17): Specifies halting the clock supply to the serial IO with FIFO
interface (SIOF). When the MSTP17 bit is set to 1, the clock supply to the serial IO with FIFO
interface (SIOF) is halted.
Bit 7: MSTP17
Description
0
SIOF runs
1
Clock supply to SIOF halted
(Initial value)
Bit 6— Reserved: This bit is always read as 0. The write value should always as 0.
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Section 9 Power-Down Modes and Software Reset
Bit 5— Module Stop 15 (MSTP15): Specifies halting the clock supply to the AFE interface
(AFE IF). When the MSTP15 bit is set to 1, the clock supply to the AFE interface is halted.
Bit 5: MSTP15
Description
0
AFE interface runs
1
Clock supply to AFE interface halted
(Initial value)
Bit 4— Module Stop 14 (MSTP14): Specifies halting the clock supply to the USB function
module (USBF). When the MSTP14 bit is set to 1, the clock supply to the USBF is halted.
Bit 4: MSTP14
Description
0
USBF runs
1
Clock supply to USBF halted
(Initial value)
Bit 3—Module Stop 13 (MSTP13): Specifies halting the clock supply to the USB host controller
(USBH). When the MSTP13 bit is set to 1, the clock supply to the USBH is halted.
Bit 3: MSTP13
Description
0
USBH runs
1
Clock supply to USBH halted
(Initial value)
Note: This bit should not be set to 1 when MSTP14 (bit 4) is 0.
Bit 2——Reserved: This bit is always read as 0. The write value should always as 0.
Bit 1— Module Stop 11 (MSTP11): Specifies halting the clock supply LCD Controller (LCDC).
When the MSTP11 bit is set to 1, the clock supply to the LCDC is halted.
Bit 1: MSTP11
Description
0
LCDC runs
1
Clock supply to LCDC halted
(Initial value)
Bit 0— Module Stop 10 (MSTP10): Specifies halting the clock supply to PC Card Controller
(PCC). When the MSTP10 bit is set to 1, the clock supply to the PCC is halted.
Bit 0: MSTP10
Description
0
PCC runs
1
Clock supply to PCC halted
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(Initial value)
Section 9 Power-Down Modes and Software Reset
9.2.4
Module Software Reset Register (SRSTR)
The Software Reset Register (SRSTR) is an 8-bit readable/writable register that controls module
reset operation equivalent to power-on reset. SRSTR is initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
SIOFR
—
AFECR
USBFR
USBHR
LBSCR
LCDCR
PCCR
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7— SIOF Reset (SIOFR): When the SIOF bit is set to 1, the serial I/O (SIOF) is reset. 0
should be written after writing 1.
Bit 7: SIOFR
Description
0
Not reset SIOF
1
Resets SIOF
(Initial value)
Bit 6—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 5— AFEIF Reset (AFECR): When the AFEC bit is set to 1, the AFE interface (AFEIF) is
reset. 0 should be written after writing 1.
Bit 5: AFECR
Description
0
Not reset AFEIF
1
Resets AFEIF
(Initial value)
Bit 4— USBF Reset (USBFR): When the USBF bit is set to 1, the SUB function module (USBF)
is reset. 0 should be written after writing 1.
Bit 4: USBFR
Description
0
Not reset USBF
1
Resets USBF
(Initial value)
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Section 9 Power-Down Modes and Software Reset
Bit 3— USBH Reset (USBHR): When the USBH bit is set to 1, the USB host controller is reset.
0 should be written after writing 1.
Bit 3: USBHR
Description
0
Not reset USBH
1
Resets USBH
(Initial value)
Bit 2— LBSC Reset (LBSCR): When the LBSC bit is set to 1, the Li bus state controller (LBSC)
is reset. 0 should be written after writing 1.
Bit 2: LBSCR
Description
0
Not reset LBSC
1
Resets LBSC
(Initial value)
Bit 1— LCDC Reset (LCDCR): When the LCDC bit is set to 1, the LCD controller (LCDC) is
reset. 0 should be written after writing 1.
Bit 1: LCDCR
Description
0
Not reset LCDC
1
Resets LCDC
(Initial value)
Bit 0— PCC Reset (PCCR): When the PCC bit is set to 1, PC card controller (PCC) is reset. 0
should be written after writing 1.
Bit 0: PCCR
Description
0
Not reset PCC
1
Resets PCC
Rev. 5.00 Dec 12, 2005 page 242 of 1034
REJ09B0254-0500
(Initial value)
Section 9 Power-Down Modes and Software Reset
9.3
Sleep Mode
9.3.1
Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers are retained. The on-chip supporting
modules continue to run during sleep mode and the clock continues to be output to the CKIO and
CKIO2 pins.
In sleep mode, the STATUS1 pin is set to high and the STATUS0 pin low.
9.3.2
Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, on-chip supporting module interrupt,
PINT) or reset. Interrupts are accepted during sleep mode even when the BL bit in the SR register
is 1. If necessary, save SPC and SSR in the stack before executing the SLEEP instruction.
Canceling with an Interrupt: When an NMI, IRQ, IRL or on-chip supporting module interrupt
occurs, sleep mode is canceled and interrupt exception handling is executed. A code
corresponding to the interrupt source is set in the INTEVT and INTEVT2 registers.
Canceling with a Reset: Sleep mode is canceled by a power-on reset or a manual reset.
9.4
Standby Mode
9.4.1
Transition to Standby Mode
To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The
chip moves from the program execution state to standby mode. In standby mode, not only the
CPU, but the clock and on-chip supporting modules are halted. The clock output from the CKIO
and CKIO2 pins also halts.
The contents of the CPU and cache register are held, but some on-chip supporting modules are
initialized. Table 9.4 lists the states of registers in standby mode.
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Section 9 Power-Down Modes and Software Reset
Table 9.4
Register States in Standby Mode
Module
Registers Initialized
Registers Retaining Data
Interrupt controller (INTC)
—
All registers
On-chip clock pulse generator
(OSC)
—
All registers
User break controller (UBC)
—
All registers
Bus state controller (BSC)
—
All registers
Timer unit (TMU)
TSTR register
Registers other than TSTR
Realtime clock (RTC)
—
All registers
A/D converter (ADC)
All registers
—
D/A converter (DAC)
—
All registers
Li bus state controller (LBSC)
—
All registers
LCD controller (LCDC)
—
All registers
USB host controller (USBH)
—
All registers
USB function module (USBF)
—
All registers
AFE interface (AFEIF)
—
All registers
Serial IO with FIFO (SIOF)
—
All registers
PC card controller (PPC)
—
Registers other than PCC0ISR*
Note: * PCC0ISR reflects the normal status.
The procedure for moving to standby mode is as follows:
1. Clear the TME bit in the WDT’s timer control register (WTCSR) to 0 to stop the WDT.
Set the WDT’s timer counter (WTCNT) to 0 and set a value to the CKS2 to CKS0 bits in the
WTCSR register to secure the specified oscillation settling time.
2. After the STBY bit in the STBCR register is set to 1, the SLEEP instruction is executed.
3. When the chip enters standby mode and the clocks within the chip are halted, he STATUS1
pin output goes low and the STATUS0 pin output goes high.
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Section 9 Power-Down Modes and Software Reset
9.4.2
Canceling Standby Mode
Standby mode is canceled by an interrupt (NMI, IRQ, IRL, on-chip supporting module interrupt or
PINT) or a reset.
Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects
an NMI, IRL, IRQ, PINT*1, or on-chip supporting module (except the interval timer)*2 interrupt,
the clock will be supplied to the entire chip and standby mode canceled after the time set in the
WDT’s timer control/status register has elapsed. The STATUS1 and STATUS0 pins both go low.
Interrupt exception handling then begins and a code corresponding to the interrupt source is set in
the INTEVT and INTEVT2 registers. After branching to the interrupt processing routine occurs,
clear the STBY bit in the STBCR register. The WTCNT stops automatically. If the STBY bit is
not cleared, WTCNT continues operation and transits to the standby mode*3 when it reaches H’80.
This function prevents the data from being destroyed due to a rising voltage under an unstable
power supply. Interrupts are accepted during standby mode even when the BL bit in the SR
register is 1. If necessary, save SPC and SSR in the stack before executing the SLEEP instruction.
Immediately after an interrupt is detected, the phase of the clock output of the CKIO and CKIO2
pin may be unstable, until the standby mode is canceled. The canceling condition is that the
interrupt request level (IRQ, IRL, or on-chip supporting module interrupt) is higher than the mask
level in the I3 to I0 bits in the SR register.
Notes: 1. When the RTC is being used, standby mode can be canceled using IRL3 to IRL0, IRQ4
to IRQ0 or PINT0 to PINT5.
2. Standby mode can be canceled with an RTC or TMU (only when running on the RTC
clock) interrupt.
3. Use a power-on reset to cancel standby mode.
Operation is not guaranteed in the case of a manual reset or interrupt input.
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Section 9 Power-Down Modes and Software Reset
Interrupt
request
WDT overflow and branch to
interrupt handling routine
Crystal oscillator settling
time and PLL synchronization
time
WTCNT value
Clear bit STBCR.STBY before
WTCNT reaches H'80. When
STBCR.STBY is cleared, WTCNT
halts automatically.
H'FF
H'80
Time
Figure 9.1 Canceling Standby Mode with STBCR.STBY
Canceling with a Reset: Standby mode can be canceled with a reset (power-on or manual).
Keep the RESET or RESETM pin low until the clock oscillation settles.
The internal clock will be output continuously to the CKIO pin.
9.4.3
Clock Pause Function
In standby mode, the clock input from the EXTAL pin or CKIO pin can be halted and the
frequency can be changed. This function is used as follows:
1. Enter standby mode using the procedure for changing to standby mode.
2. When the chip enters standby mode and the clock stopped within the chip, the STATUS1 pin
output is low and the STATUS0 pin output is high.
3. When the STATUS1 pin goes low and the STATUS0 pin goes high, the input clock is stopped
or the frequency is changed.
4. When the frequency is changed, an NMI, IRL, IRQ, PINT or on-chip supporting module
(except the internal timer) interrupt is input after changing the frequency. When the clock is
stopped, the same interrupts are input after the clock is applied.
5. After the time set in the WDT has elapsed, the clock starts being applied within the chip, the
STATUS1 and STATUS0 pins both go low, operation resumes from the interrupt exception
handling.
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Section 9 Power-Down Modes and Software Reset
9.5
Module Standby Function
9.5.1
Transition to Module Standby Function
Setting the standby control register STBCR, STBCR2, STBCR3, MSTP17, MSTP15 to MSTP13,
MSTP11 to MSTP4, and MSTP 2 to MSTP0 bits to 1 halts the clock supply to the corresponding
on-chip supporting modules. By using this function, the power consumption in normal mode and
sleep mode can be reduced.
In the module standby function, external pins of the on-chip supporting modules are different
depending on the on-chip supporting modules. TMU external pins hold their state prior to the halt.
SCI external pins go to the reset state. With a few exceptions, all registers hold their values.
Rev. 5.00 Dec 12, 2005 page 247 of 1034
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Section 9 Power-Down Modes and Software Reset
Bit
Value
Description
MSTP17
0
SIOF runs.
1
Clock supply to SIOF halted.
0
AFEIF runs.
1
Clock supply to AFEIF halted.
0
USBF runs.
1
Clock supply to USBF halted.
0
USBH runs.
1
Clock supply to USBH halted.
This bit should not be set to 1 when MSTP14 (bit 4) is 0.
0
LCDC runs.
1
Clock supply to LCDC halted.
MSTP10
0
PCC runs.
1
Clock supply to PCC halted.
MSTP9
0
X/Y memory runs.
1
Clock supply to X/Y memory halted.
0
UBC runs.
1
Clock supply to UBC halted.
0
DMAC runs.
1
Clock supply to DMAC halted.
0
DAC runs.
1
Clock supply to DAC halted.
0
ADC runs.
1
Clock supply to ADC halted, and all registers initialized.
MSTP15
MSTP14
MSTP13
MSTP11
MSTP8
MSTP7
MSTP6
MSTP5
MSTP4
MSTP2
MSTP1
MSTP0
0
SCIF runs.
1
Clock supply to SCIF halted.
0
TMU runs.
1
Clock supply to TMU halted.*
0
RTC runs.
1
Clock supply to RTC halted. Register access prohibited.*
0
SCI runs.
1
Clock supply to SCI halted.
1
2
Notes: 1. The initialized registers are the same as in the standby mode (see table 9.4).
2. The counter runs.
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Section 9 Power-Down Modes and Software Reset
9.5.2
Clearing the Module Standby Function
The module standby function can be cleared by clearing the MSTP17, MSTP15 to MSTP13,
MSTP11 to MSTP4, and MSTP2 to MSTP0 bits to 0, or by a power-on reset or manual reset.
9.6
Timing of STATUS Pin Changes
The timing of STATUS1 and STATUS0 pin changes is shown in figures 9.2 to 9.9.
The meanings of STATUS are as follows:
• Reset:
HH (STATUS1 is high, STATUS0 is high)
• Sleep:
HL (STATUS1 is high, STATUS0 is low)
• Standby: LH (STATUS1 is low, STATUS0 is high)
• Normal: LL (STATUS1 is low, STATUS0 is low)
The meanings of clock units are as follows:
• Bcyc: Bus clock cycle
• Pcyc: Peripheral clock cycle
• Rcyc: 32.768-kHz RTC clock cycle
9.6.1
Timing for Resets
Power-On Reset
CKIO,
CKIO2*
PLL settling
time
RESETP
STATUS
Normal
Reset
0 to 5 Bcyc
Normal
0 to 30 Bcyc
Note: * CKIO2 can be used at only clock modes 0, 1 and 2.
Figure 9.2 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output
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Section 9 Power-Down Modes and Software Reset
Manual Reset
CKIO,
CKIO*2
RESETM
STATUS
Normal
Reset
0 Bcyc or more*1
Normal
0 to 30 Bcyc
Notes: 1. During manual reset, STATUS becomes HH (reset) and the internal reset begins after
waiting for the executing bus cycle to end.
2. CKIO2 can be used at only clock modes 0, 1 and 2.
Figure 9.3 Manual Reset STATUS Output
9.6.2
Timing for Canceling Standbys
Standby to Interrupt
Oscillation stops
Interrupt request
CKIO,
CKIO2*
STATUS
WDT overflow
WDT count
Normal
Standby
Note: * CKIO2 can be used at only clock modes 0, 1 and 2.
Figure 9.4 Standby to Interrupt STATUS Output
Rev. 5.00 Dec 12, 2005 page 250 of 1034
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Normal
Section 9 Power-Down Modes and Software Reset
Standby to Power-On Reset
Oscillation stops
Reset
CKIO,
CKIO2*2
RESETP*1
STATUS
Normal
Standby
*3
0 to 10 Bcyc
Normal
Reset
0 to 30 Bcyc
Notes: 1. When standby mode is cleared with a power-on reset, the WDT does not count.
Keep RESETP low during PLL's oscillation settling time.
2. CKIO2 can be used at only clock modes 0, 1 and 2.
3. Undefined
Figure 9.5 Standby to Power-On Reset STATUS Output
Standby to Manual Reset
Oscillation stops
Reset
CKIO,
CKIO2*2
RESETM*1
STATUS
Normal
Standby
Reset
Normal
0 to 20 Bcyc
Notes: 1. When standby mode is cleared with a power-on reset, the WDT does not count.
Keep RESETM low during PLL's oscillation settling time.
2. CKIO2 can be used at only clock modes 0, 1 and 2.
Figure 9.6 Standby to Manual Reset STATUS Output
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Section 9 Power-Down Modes and Software Reset
9.6.3
Timing for Canceling Sleep Mode
Sleep to Interrupt
Interrupt request
CKIO,
CKIO2*
STATUS
Normal
Sleep
Normal
Note: * CKIO2 can be used at only clock modes 0, 1 and 2.
Figure 9.7 Sleep to Interrupt STATUS Output
Sleep to Power-On Reset
Reset
CKIO,
CKIO2*2
RESETP*1
STATUS
Normal
Sleep
*3
0 to 10 Bcyc
Normal
Reset
0 to 30 Bcyc
Notes: 1. When the PLL's multiplication ratio is changed by a power-on reset, keep RESETP
low during PLL's oscillation settling time.
2. CKIO2 can be used at only clock modes 0, 1 and 2.
3. Undefined
Figure 9.8 Sleep to Power-On Reset STATUS Output
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Section 9 Power-Down Modes and Software Reset
Sleep to Manual Reset
Reset
CKIO,
CKIO2*2
RESETM*1
STATUS
Normal
Sleep
Reset
0 to 80 Bcyc
Normal
0 to 30 Bcyc
Notes: 1. Keep RESETM low until the STATUS becomes reset.
2. CKIO2 can be used at only clock modes 0, 1 and 2.
Figure 9.9 Sleep to Manual Reset STATUS Output
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Section 9 Power-Down Modes and Software Reset
9.7
Hardware Standby Mode
9.7.1
Transition to Hardware Standby Mode
To enter hardware standby mode, set the CA pin low. In hardware standby mode, all modules
except for any modules that run with RTC clock are halted as well as in standby mode entered by
sleep instruction.
Differences between hardware standby mode and standby mode are as follows.
1. Interrupts and manual reset are not accepted in hardware standby mode.
2. The TMU does not run in hardware standby mode.
Operation when the CA pin goes low depends on the CPG status.
1. In standby mode
The chip enters hardware standby mode, clock remains halted.
Interrupts and manual reset are not accepted and the TMU halts.
2. During WDT runs when clearing standby mode with an interrupt
The chip enters hardware standby mode after the CPU resumes operation once standby mode is
cleared.
3. In sleep mode
The chip enters hardware standby mode after the CPU resumes operation once sleep mode is
cleared.
Note that CA pin must keep low during hardware standby mode.
9.7.2
Clearing the Hardware Standby Mode
Hardware standby mode can be cleared only by power-on reset.
The clock starts oscillation by setting CA pin high while RESETP pin is low. At this time, keep
the RESETP pin low until the clock oscillation settles. Then, the CPU starts power-on reset
processing after setting the RESETP pin high.
The operation is not guaranteed when an interrupt or manual reset is occurred.
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Section 9 Power-Down Modes and Software Reset
9.7.3
Timing of Hardware Standby Mode
The timings of each pin in hardware standby mode are shown in figures 9.10 and 9.11.
CA pin is sampled by EXTAL2 (32.768 kHz). Hardware standby request is detected when two
continuous cycles go low in this clock.
Keep CA pin low during hardware standby mode.
The clock starts oscillation when the CA pin is set high after setting the RESETP pin low.
CKIO, CKIO2*6
CA
RESETP
STATUS
Normal*3
Standby*2
*7
Reset*1
0−10Bcyc*4
2 Rcyc or more*5
Notes: 1.
2.
3.
4.
5.
6.
7.
Reset: HH (STATUS1 is high, STATUS0 is high)
Standby: LH (STATUS1 is low, STATUS0 is high)
Normal: LL (STATUS1 is low, STATUS0 is low)
Bcyc: Bus clock cycle
Rcyc: EXTAL2 (32.768 kHz) clock cycle
CKIO2 can be used at only clock modes 0,1 and 2.
Undefined
Figure 9.10 Hardware Standby Mode Timing
(CA = Low in Normal Operation)
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Section 9 Power-Down Modes and Software Reset
CKIO, CKIO2*6
CA
RESETP
STATUS
Normal*3
Standby
Standby*2
WDT operation
*7
Reset*1
0−10Bcyc*4
2 Rcyc or more*5
Notes: 1.
2.
3.
4.
5.
6.
7.
Reset: HH (STATUS1 is high, STATUS0 is high)
Standby: LH (STATUS1 is low, STATUS0 is high)
Normal: LL (STATUS1 is low, STATUS0 is low)
Bcyc: Bus clock cycle
Rcyc: EXTAL2 (32.768 kHz) clock cycle
CKIO2 can be used at only clock modes 0,1 and 2.
Undefined
Figure 9.11 Hardware Standby Mode Timing
(CA = Low during WDT Operation while Standby Mode is Cleared)
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Section 10 On-Chip Oscillation Circuits
Section 10 On-Chip Oscillation Circuits
10.1
Overview
The on-chip oscillation circuits consist of the clock pulse generator (CPG) and watchdog timer
(WDT).
The clock pulse generator (CPG) supplies all clocks to the processor and controls the power-down
modes.
The watchdog timer (WDT) is a single-channel timer that counts the clock settling time and is
used when clearing standby mode and temporary standby, such as frequency changes. It can also
be used as an ordinary watchdog timer or interval timer.
10.1.1
Features
The CPG has the following features:
• Four clock modes: Selection of four clock modes for different frequency ranges, power
consumption, direct crystal input, and external clock input.
• Three clocks generated independently: An internal clock for the CPU, cache, and TLB (Iφ); a
peripheral clock (Pφ) for the on-chip supporting modules; and a bus clock (CKIO) for the
external bus interface.
• Frequency change function: Internal and peripheral clock frequencies can be changed
independently using the PLL circuit and divider circuit within the CPG. Frequencies are
changed by software using frequency control register (FRQCR) settings.
• Power-down mode control: The clock can be stopped for sleep mode and standby mode and
specific modules can be stopped using the module standby function.
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Section 10 On-Chip Oscillation Circuits
The WDT has the following features:
• Can be used to ensure the clock settling time: Use the WDT to cancel standby mode and the
temporary standby which occur when the clock frequency is changed.
• Can switch between watchdog timer mode and interval timer mode.
• Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow.
Selection of power-on reset or manual reset.
• Generates interrupts in interval timer mode: Internal timer interrupts occur after counter
overflow.
• Selection of eight counter input clocks. Eight clocks (×1 to ×1/4096) can be obtained by
dividing the peripheral clock.
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Section 10 On-Chip Oscillation Circuits
10.2
Overview of the CPG
10.2.1
CPG Block Diagram
A block diagram of the on-chip clock pulse generator is shown in figure 10.1.
Clock pulse generator
CAP1
CKIO2
Divider 1
×1
× 1/2
× 1/3
×1/4
PLL circuit 1
(× 1, 2, 3, 4, 6)
CKIO
Divider 2
×1
× 1/2
× 1/3
× 1/4
× 1/6
Cycle = Bcyc
CAP2
XTAL
Crystal
oscillator
PLL circuit 2
(× 1, 4)
Internal
clock (Iφ)
Cycle = Icyc
Peripheral
clock (Pφ)
Cycle = Pcyc
EXTAL
Bus clock (Pφ)
Cycle = Bcyc
CPG control unit
MD2
Clock frequency
control circuit
Standby control
circuit
FRQCR
STBCR
Standby
control
MD1
MD0
Bus interface
Internal bus
Legend:
FRQCR: Frequency control register
STBCR: Standby control register
Figure 10.1 Block Diagram of Clock Pulse Generator
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Section 10 On-Chip Oscillation Circuits
The clock pulse generator blocks function as follows:
1. PLL Circuit 1
PLL circuit 1 doubles, triples, quadruples, sextuples, or leaves unchanged the input clock
frequency from the CKIO pin or PLL circuit 2. The multiplication rate is set by the frequency
control register. When this is done, the phase of the leading edge of the internal clock is
controlled so that it will agree with the phase of the leading edge of the CKIO pin.
2. PLL Circuit 2
PLL circuit 2 leaves quadruples the frequency of the crystal oscillator or the input clock
frequency coming from the EXTAL pin. The multiplication ratio is fixed by the clock
operation mode. The clock operation mode is set by pins MD0, MD1, and MD2. See table 10.3
for more information on clock operation modes.
3. Crystal Oscillator
This oscillator is used when a crystal oscillator element is connected to the XTAL and EXTAL
pins. It operates according to the clock operating mode setting.
4. Divider 1
Divider 1 generates a clock at the operating frequency used by the internal clock. The
operating frequency can be 1, 1/2, 1/3, or 1/4 times the output frequency of PLL circuit 1, as
long as it stays at or above the clock frequency of the CKIO pin. The division ratio is set in the
frequency control register.
5. Divider 2
Divider 2 generates a clock at the operating frequency used by the peripheral clock. The
operating frequencies can be 1, 1/2, 1/3,1/4, or 1/6 times the output frequency of PLL Circuit 1
or the clock frequency of the CKIO pin, as long as it stays at or below the clock frequency of
the CKIO pin. The division ratio is set in the frequency control register.
6. Clock Frequency Control Circuit
The clock frequency control circuit controls the clock frequency using the MD pin and the
frequency control register.
7. Standby Control Circuit
The standby control circuit controls the state of the clock pulse generator and other modules
during clock switching and sleep/standby modes.
8. Frequency Control Register
The frequency control register has control bits assigned for the following functions: clock
output/non-output from the CKIO pin, PLL standby, the frequency multiplication ratio of PLL
1, and the frequency division ratio of the internal clock and the peripheral clock.
9. Standby Control Register
The standby control register has bits for controlling the power-down modes. See section 9,
Power-Down Modes and Software Reset, for more information.
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Section 10 On-Chip Oscillation Circuits
10.2.2
CPG Pin Configuration
Table 10.1 lists the CPG pins and their functions.
Table 10.1 Clock Pulse Generator Pins and Functions
Pin Name
Symbol
I/O
Description
Mode control pins
MD0
I
Set the clock operating mode.
MD1
I
MD2
I
XTAL
O
Connects a crystal oscillator.
EXTAL
I
Connects a crystal oscillator. Also used to input an
external clock.
Clock I/O pin
CKIO
I/O
Inputs or outputs an external clock.
Clock Out pin
CKIO2
O
Output external clock. Level can be fixed. Only clock
modes 0, 1, 2 can be supported for this pin.
Capacitor
connection pins
CAP1
I
Connects capacitor for PLL circuit 1 operation
(recommended value 470 pF).
For PLL
CAP2
I
Connects capacitor for PLL circuit 2 operation
(recommended value 470 pF).
Crystal I/O pins
(clock input pins)
10.2.3
CPG Register Configuration
Table 10.2 shows the CPG register configuration.
Table 10.2 Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Frequency control register
FRQCR
R/W
H'0102
H'FFFFFF80
16 bits
CKIO2 Control Register 2
CKIO2CR
R/W
H'0000
H'0400023A
(H'A400023A)*
16 bits
Note: * When address translation by the MMU does not apply, the address in parentheses should
be used.
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Section 10 On-Chip Oscillation Circuits
10.3
Clock Operating Modes
Table 10.3 shows the relationship between the mode control pin (MD2 to MD0) combinations and
the clock operating modes. Table 10.4 shows the usable frequency ranges in the clock operating
modes.
Table 10.3 Clock Operating Modes
Pin Values
Clock I/O
PLL2
On/Off
PLL1
On/Off
Divider 1 Divider 2 CKIO
Input
Input
Frequency
CKIO
On,
multiplication
ratio: 1
On
PLL1
output
PLL1
(EXTAL)
CKIO
On,
multiplication
ratio: 4
On
PLL1
output
PLL1
(EXTAL) × 4
0
Crystal CKIO
oscillator
On,
multiplication
ratio: 4
On
PLL1
output
PLL1
(Crystal) × 4
1
CKIO
Off
On
PLL1
output
PLL1
(CKIO)
Mode
MD2 MD1 MD0
Source
Output
0
0
0
0
EXTAL
1
0
0
1
EXTAL
2
0
1
7
1
1
—
Mode 0: An external clock is input from the EXTAL pin and undergoes waveform shaping by
PLL circuit 2 before being supplied inside this LSI. PLL circuit 1 is constantly on. An input clock
frequency of 24 MHz to the maximum frequency of CKIO can be used. For details on the CKIO
maximum frequency, see section 32, Electrical Characteristics.
Mode 1: An external clock is input from the EXTAL pin and its frequency is multiplied by 4 by
PLL circuit 2 before being supplied inside this LSI, allowing a low-frequency external clock to be
used. An input clock frequency of 6 MHz to1/4 of the maximum frequency of CKIO can be used.
For details on the CKIO maximum frequency, see section 32, Electrical Characteristics.
Mode 2: The on-chip crystal oscillator operates, with the oscillation frequency being multiplied
by 4 by PLL circuit 2 before being supplied inside this LSI, allowing a low crystal frequency to be
used. A crystal oscillation frequency of 6 MHz to 1/4 of the maximum frequency of CKIO can be
used. For details on the CKIO maximum frequency, see section 32, Electrical Characteristics.
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Section 10 On-Chip Oscillation Circuits
Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and
undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL
circuit 1 before being supplied to this LSI. In modes 0 to 2, the system clock is generated from the
output of this LSI’s CKIO pin. Consequently, if a large number of ICs are operating on the clock
cycle, the CKIO pin load will be large. This mode, however, assumes a comparatively large-scale
system. If a large number of ICs are operating on the clock cycle, a clock generator with a number
of low-skew clock outputs can be provided, so that the ICs can operate synchronously by
distributing the clocks to each one.
As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.
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Section 10 On-Chip Oscillation Circuits
Table 10.4 Available Combination of Clock Mode and FRQCR Values
Clock Mode
FRQCR
PLL1
PLL2
Clock Rate* (I:B:P)
0
H'0100
ON (× 1)
ON (× 1)
1:1:1
H'0101
ON (× 1)
ON (× 1)
1:1:1/2
H'0102
ON (× 1)
ON (× 1)
1:1:1/4
1, 2
H'0111
ON (× 2)
ON (× 1)
2:1:1
H'0112
ON (× 2)
ON (× 1)
2:1:1/2
H'0115
ON (× 2)
ON (× 1)
1:1:1
H'0116
ON (× 2)
ON (× 1)
1:1:1/2
H'0122
ON (× 4)
ON (× 1)
4:1:1
H'0126
ON (× 4)
ON (× 1)
2:1:1
H'012A
ON (× 4)
ON (× 1)
1:1:1
H'A100
ON (× 3)
ON (× 1)
3:1:1
H'A101
ON (× 3)
ON (× 1)
3:1:1/2
H'E100
ON (× 3)
ON (× 1)
1:1:1
H'E101
ON (× 3)
ON (× 1)
1:1:1/2
H'A111
ON (× 6)
ON (× 1)
6:1:1
H'0100
ON (× 1)
ON (× 4)
4:4:4
H'0101
ON (× 1)
ON (× 4)
4:4:2
H'0102
ON (× 1)
ON (× 4)
4:4:1
H'0111
ON (× 2)
ON (× 4)
8:4:4
H'0112
ON (× 2)
ON (× 4)
8:4:2
H'0115
ON (× 2)
ON (× 4)
4:4:4
H'0116
ON (× 2)
ON (× 4)
4:4:2
H'0122
ON (× 4)
ON (× 4)
16:4:4
H'0126
ON (× 4)
ON (× 4)
8:4:4
H'012A
ON (× 4)
ON (× 4)
4:4:4
H'A100
ON (× 3)
ON (× 4)
12:4:4
H'A101
ON (× 3)
ON (× 4)
12:4:2
H'E100
ON (× 3)
ON (× 4)
4:4:4
H'E101
ON (× 3)
ON (× 4)
4:4:2
H’A111
ON (× 6)
ON (× 1)
24:4:4
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Section 10 On-Chip Oscillation Circuits
Clock Mode
FRQCR
PLL1
PLL2
Clock Rate* (I:B:P)
7
H'0100
ON (× 1)
OFF
1:1:1
H'0101
ON (× 1)
OFF
1:1:1/2
H'0102
ON (× 1)
OFF
1:1:1/4
H'0111
ON (× 2)
OFF
2:1:1
H'0112
ON (× 2)
OFF
2:1:1/2
H'0115
ON (× 2)
OFF
1:1:1
H'0116
ON (× 2)
OFF
1:1:1/2
H'0122
ON (× 4)
OFF
4:1:1
H'0126
ON (× 4)
OFF
2:1:1
H'012A
ON (× 4)
OFF
1:1:1
H'A100
ON (× 3)
OFF
3:1:1
H'A101
ON (× 3)
OFF
3:1:1/2
H'E100
ON (× 3)
OFF
1:1:1
H'E101
ON (× 3)
OFF
1:1:1/2
H'A111
ON (× 6)
OFF
6:1:1
Note: * Taking input clock as 1
Cautions:
1. The frequency ranges of the input clock and crystal oscillator should be set within the specified
frequency range based on the clock rate in table 10.4, and section 32.3, AC Characteristics.
2. The input to divider 1 becomes the output of PLL circuit 1 when PLL circuit 1 is on.
3. The input of divider 2 becomes the output of:
•
PLL circuit 1
4. The frequency of the internal clock (Iφ) becomes:
•
The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 1 when PLL circuit 1 is on.
•
Do not set the internal clock frequency lower than the CKIO pin frequency.
•
Depending on the product, the clock ratio should be set to produce a frequency within one
of the ranges indicated below.
100 MHz products: 24 MHz to 100 MHz
160 MHz products: 24 MHz to 160 MHz
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Section 10 On-Chip Oscillation Circuits
5. Bus clock (Bφ) frequency:
•
Depending on the product, the clock ratio should be set to produce a frequency within one
of the ranges indicated below.
100 MHz products: 24 MHz to 50 MHz
160 MHz products: 24 MHz to 66.64 MHz
6. The frequency of the peripheral clock (Pφ) becomes:
•
The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 2.
•
For all products, the peripheral clock frequency (Pφ) should be set within the frequency
range 6 MHz to 33.34 MHz and no higher than the frequency of the CKIO pin.
•
The peripheral clock frequency (Pφ) should be set to 13 MHz or higher if the USB function
module is used.
7. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the
multiplication ratio of PLL circuit 1.
8. ×1, ×2, ×3, ×4, or ×6 can be used as the multiplication ratio of PLL circuit 1. ×1, ×1/2, ×1/3,
and ×1/4 can be selected as the division ratio of divider 1. ×1, ×1/2, ×1/3, ×1/4, and ×1/6 can
be selected as the division ratio of divider 2. Set the rate in the frequency control register. The
on/off state of PLL circuit 2 is determined by the mode.
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Section 10 On-Chip Oscillation Circuits
10.4
Register Descriptions
10.4.1
Frequency Control Register (FRQCR)
The frequency control register (FRQCR) is a 16-bit read/write register that specify the frequency
multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the
peripheral clock.
Only word access can be used on the FRQCR register. FRQCR is initialized to H'0102 by a
power-on reset, but retains its value in a manual reset and in standby mode.
Bit:
15
14
13
12
11
10
9
8
STC2
IFC2
PFC2
—
—
—
—
—
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R
R
R
R
R
7
6
5
4
3
2
1
0
—
—
STC1
STC0
IFC1
IFC0
PFC1
PFC0
Initial value:
0
0
0
0
0
0
1
0
R/W:
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
R/W:
Bit:
Bits 15, 5 and 4—Frequency Multiplication Ratio (STC2, STC1, STC0): These bits specify the
frequency multiplication ratio of PLL circuit 1.
Bit 15: STC2
Bit 5: STC1
Bit 4: STC0
Description
0
0
0
×1
0
0
1
×2
1
0
0
×3
0
1
0
×4
1
0
1
×6
Values other than above
(Initial value)
Reserved (illegal setting)
Note: Do not set the output frequency of PLL circuit 1 higher than the maximum frequency of the
CPU specified in AC Characteristics.
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Section 10 On-Chip Oscillation Circuits
Bits 14, 3 and 2—Internal Clock Frequency Division Ratio (IFC2, IFC1, IFC0): These bits
specify the frequency division ratio of the internal clock with respect to the output frequency of
PLL circuit 1.
Bit 14: IFC2
Bit 3: IFC1
Bit 2: IFC0
Description
0
0
0
×1
0
0
1
× 1/2
1
0
0
× 1/3
0
1
0
× 1/4
Values other than above
(Initial value)
Reserved (illegal setting)
Note: Do not set the internal clock frequency lower than the CKIO frequency.
Bits 13, 1 and 0—Peripheral Clock Frequency Division Ratio (PFC2, PFC1, PFC0): These
bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the
output frequency of PLL circuit 1 or the frequency of the CKIO pin.
Bit 13: PFC2
Bit 1: PFC1
Bit 0: PFC0
Description
0
0
0
×1
0
0
1
× 1/2
1
0
0
× 1/3
0
1
0
× 1/4
1
0
1
× 1/6
Values other than above
(Initial value)
Reserved (illegal setting)
Note: Do not set the peripheral clock frequency higher than the frequency of the CKIO pin.
Bits 12 to 9, 7 and 6—Reserved: These bits are always read as 0. The write value should always
be 0.
Bit 8—Reserved: This bit is always read as 1. The write value should always be 1.
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Section 10 On-Chip Oscillation Circuits
10.4.2
CKIO2 Control Register (CKIO2CR)
CKIO2CR controls CKIO2 pin output.
Upper 8 Bits:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Lower 8 Bits:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
CKIO2EN
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bits 15 to 1—Reserved: These bits always read 0. The write value should always be 0.
Bit 0—CKIO2 (CKIO2EN): Selects output or not output (Hi-Z) for CKIO2 clock.
Bit 0: CKIO2EN
Description
0
Output
1
Not output (Hi-Z)
(Initial value)
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Section 10 On-Chip Oscillation Circuits
10.5
Changing the Frequency
The frequency of the internal clock and peripheral clock can be changed either by changing the
multiplication rate of PLL circuit 1 or by changing the division rates of dividers 1 and 2. All of
these are controlled by software through the frequency control register. The methods are described
below.
10.5.1
Changing the Multiplication Rate
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The onchip WDT counts the settling time.
1. In the initial state, the multiplication rate of PLL circuit 1 is 1.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
WDT. The following must be set:
WTCSR register TME bit = 0: WDT stops
WTCSR register CKS2 to CKS0 bits: Division ratio of WDT count clock
WTCNT counter: Initial counter value
3. Set the desired value in the STC2, STC1 and STC0 bits. The division ratio can also be set in
the IFC2 to IFC0 bits and PFC2 to PFC0 bits.
4. The processor pauses internally and the WDT starts incrementing. In clock modes 0 to 2 and 7,
the internal and peripheral clocks both stop.
5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins
operating again. The WDT stops after it overflows.
10.5.2
Changing the Division Ratio
The WDT will not count unless the multiplication rate is changed simultaneously.
1. In the initial state, IFC2 to IFC0 = 000 and PFC2 to PFC0 = 010.
2. Set the IFC2, IFC1, IFC0, PFC2, PFC1, and PFC0 bits to the new division ratio. The values
that can be set are limited by the clock mode and the multiplication rate of PLL circuit 1. Note
that if the wrong value is set, the processor will malfunction.
3. The clock is immediately supplied at the new division ratio.
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Section 10 On-Chip Oscillation Circuits
10.6
Overview of the WDT
10.6.1
Block Diagram of the WDT
Figure 10.2 shows a block diagram of the WDT.
WDT
Standby
cancellation
Internal
reset
request
Standby
mode
Peripheral
clock
Standby
control
Divider
Reset
control
Clock selection
Clock selector
Interrupt
request
Overflow
Interrupt
control
Clock
WTCSR
WTCNT
Bus interface
Internal bus
Legend:
WTCSR:
WTCNT:
Watchdog timer control/status register
Watchdog timer counter
Figure 10.2 Block Diagram of the WDT
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Section 10 On-Chip Oscillation Circuits
10.6.2
Register Configurations
The WDT has two registers that select the clock, switch the timer mode, and perform other
functions. Table 10.5 shows the WDT register.
Table 10.5 Register Configuration
Name
Abbreviation
R/W
Initial Value
Address
Access Size
Watchdog timer counter
WTCNT
R/W*
H'00
H'FFFFFF84
R: 8;
W: 16*
Watchdog timer control/
status register
WTCSR
R/W*
H'00
H'FFFFFF86
R: 8;
W: 16*
Note: * Write with a word access. Write H'5A and H'A5, respectively, in the upper bytes. Byte or
longword writes are not possible. Read with a byte access.
10.7
WDT Registers
10.7.1
Watchdog Timer Counter (WTCNT)
The watchdog timer counter (WTCNT) is an 8-bit read/write counter that increments on the
selected clock. The WTCNT differs from other registers in that it is more difficult to write to. See
section 10.7.3, Notes on Register Access, for details. When an overflow occurs, it generates a reset
in watchdog timer mode and an interrupt in interval time mode. Its address is H'FFFFFF84. The
WTCNT counter is initialized to H'00 by a power-on reset through the RESETP pin. Use a word
access to write to the WTCNT counter, with H'5A in the upper byte. Use a byte access to read
WTCNT.
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
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Section 10 On-Chip Oscillation Circuits
10.7.2
Watchdog Timer Control/Status Register (WTCSR)
The watchdog timer control/status register (WTCSR) is an 8-bit read/write register composed of
bits to select the clock used for the count, bits to select the timer mode, and overflow flags. The
WTCSR differs from other registers in that it is more difficult to write to. See section 10.7.3,
Notes on Register Access, for details. Its address is H'FFFFFF86. The WTCSR register is
initialized to H'00 only by a power-on reset through the RESETP pin. When a WDT overflow
causes an internal reset, the WTCSR retains its value. When used to count the clock settling time
for canceling a standby, it retains its value after counter overflow. Use a word access to write to
the WTCSR counter, with H'A5 in the upper byte. Use a byte access to read WTCSR.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
TME
WT/IT
RSTS
WOVF
IOVF
CKS2
CKS1
CKS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7—Timer Enable (TME): Starts and stops timer operation. Clear this bit to 0 when using the
WDT in standby mode or when changing the clock frequency.
Bit 7: TME
Description
0
Timer disabled: Count-up stops and WTCNT value is retained
1
Timer enabled
(Initial value)
Bit 6—Timer Mode Select (WT/IT
IT):
IT Selects whether to use the WDT as a watchdog timer or an
interval timer.
Bit 6: WT/IT
IT
Description
0
Use as interval timer
1
Use as watchdog timer
(Initial value)
Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly.
Bit 5—Reset Select (RSTS): Selects the type of reset when the WTCNT overflows in watchdog
timer mode. In interval timer mode, this setting is ignored.
Bit 5: RSTS
Description
0
Power-on reset
1
Manual reset
(Initial value)
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Section 10 On-Chip Oscillation Circuits
Bit 4—Watchdog Timer Overflow (WOVF): Indicates that the WTCNT has overflowed in
watchdog timer mode. This bit is not set in interval timer mode.
Bit 4: WOVF
Description
0
No overflow
1
WTCNT has overflowed in watchdog timer mode
(Initial value)
Bit 3—Interval Timer Overflow (IOVF): Indicates that the WTCNT has overflowed in interval
timer mode. This bit is not set in watchdog timer mode.
Bit 3: IOVF
Description
0
No overflow
1
WTCNT has overflowed in interval timer mode
(Initial value)
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select the clock to be used for the
WTCNT count from the eight types obtainable by dividing the peripheral clock. The overflow
period in the table is the value when the peripheral clock (Pφ) is 15 MHz.
Bit 2: CKS2
Bit 1: CKS1
Bit 0: CKS0
Clock Division Ratio
Overflow Period
(when Pφ
φ = 15 MHz)
0
0
0
1
17 µs
1
1/4
68 µs
1
0
1/16
273 µs
1
1/32
546 µs
0
1/64
1.09 ms
1
1/256
4.36 ms
0
1/1024
17.48 ms
1
1/4096
69.91 ms
1
0
1
(Initial value)
Note: If bits CKS2 to CKS0 are modified when the WDT is running, the up-count may not be
performed correctly. Ensure that these bits are modified only when the WDT is not running.
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Section 10 On-Chip Oscillation Circuits
10.7.3
Notes on Register Access
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers is given
below.
Writing to WTCNT and WTCSR: These registers must be written by a word transfer
instruction. They cannot be written by a byte or longword transfer instruction. When writing to
WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in
figure 10.3. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as
the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
WTCNT write
15
Address: H'FFFFFF84
8
7
H'5A
0
Write data
WTCSR write
15
Address: H'FFFFFF86
8
7
H'A5
0
Write data
Figure 10.3 Writing to WTCNT and WTCSR
10.8
Using the WDT
10.8.1
Canceling Standby Mode
The WDT can be used to cancel standby mode with an NMI or other interrupts. The procedure is
described below. (The WDT does not run when resets are used for canceling, so keep the RESETP
pin low until the clock stabilizes.)
1. Before transitioning to standby mode, always clear the TME bit in WTCSR to 0. When the
TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count
overflows.
2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
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Section 10 On-Chip Oscillation Circuits
3. Move to standby mode by executing a SLEEP instruction to stop the clock.
4. The WDT starts counting by detecting the edge change of the NMI signal or detecting
interrupts.
5. When the WDT count overflows, the CPG starts supplying the clock and the processor
resumes operation. The WOVF flag in WTCSR is not set when this happens.
6. Since the WDT continues counting from H’00, set the STBY bit in the STBCR register to 0 in
the interrupt processing program and this will stop the WDT. When the STBY bit remains 1,
the SH7727 again enters the standby mode when the WDT has counted up to H’80. This
standby mode can be canceled by power-on resets.
10.8.2
Changing the Frequency
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
2. Set the type of count clock used in the CKS2 to CKS0 bits of WTCSR and the initial values for
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
3. When the frequency control register (FRQCR) is written, the clock stops and the processor
enters standby mode temporarily. The WDT starts counting.
4. When the WDT count overflows, the CPG resumes supplying the clock and the processor
resumes operation. The WOVF flag in WTCSR is not set when this happens.
5. The counter stops at the values H'00 to H'01. The stop value depends on the clock ratio.
10.8.3
Using Watchdog Timer Mode
1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type of
count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT
counter.
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
the counter from overflowing.
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the
type of reset specified by the RSTS bit. The counter then resumes counting.
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Section 10 On-Chip Oscillation Circuits
10.8.4
Using Interval Timer Mode
When operating in interval timer mode, interval timer interrupts are generated at every overflow of
the counter. This enables interrupts to be generated at set periods.
1. Clear the WT/IT bit in the WTCSR register to 0, set the type of count clock in the CKS2 to
CKS0 bits, and set the initial value of the counter in the WTCNT counter.
2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval
timer interrupt request is sent to INTC. The counter then resumes counting.
10.9
Notes on Board Design
When Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and
CL2, and damping resistor R close to the EXTAL and XTAL pins. To prevent induction from
interfering with correct oscillation, use a common grounding point for the capacitors connected to
the resonator, and do not locate a wiring pattern near these components.
Avoid crossing
signal lines
CL1
CL2
R
EXTAL
XTAL
SH7727
Note: The values for CL1, CL2, and the damping resistance should be determined after
consultation with the crystal oscillator manufacturer.
Figure 10.4 Points for Attention when Using Crystal Resonator
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Section 10 On-Chip Oscillation Circuits
Decoupling Capacitors: Insert a laminated ceramic capacitor of 0.01 to 0.1 µF as a passive
capacitor for each VSS/VCC pair. Mount the passive capacitors to the SH3 power supply pins, and
use components with a frequency characteristic suitable for the SH3 operating frequency, as well
as a suitable capacitance value.
Digital system VSS/VCC pairs: 35-37, 91-93, 137-139, 155-157, 177-178, 200-202
Digital system VSS Q/VCC Q pairs: 18-20, 29-31, 42-44, 53-55, 64-66, 75-77, 86-88, 100-102, 115117, 132-134, 159-161, 188-190, 207-209
On-chip oscillator VSS/VCC pairs: 1-4
When Using a PLL Oscillator Circuit: Keep the wiring from the PLL VCC and VSS connection
pattern to the power supply pins short, and make the pattern width large, to minimize the
inductance component. Ground the oscillation stabilization capacitors C1 and C2 to VSS (PLL1)
and VSS (PLL2), respectively. Place C1 and C2 close to the CAP1 and CAP2 pins and do not
locate a wiring pattern in the vicinity. In clock mode 7, connect the EXTAL pin to VCC or VSS and
leave the XTAL pin open.
Avoid crossing
signal lines
VCC (PLL2)
Power supply
CAP2
VSS (PLL2)
C2
VCC
Reference values
C1 = 470 pF
C2 = 470 pF
VCC (PLL1)
VSS
CAP1
C1
VSS (PLL1)
Figure 10.5 Points for Attention when Using PLL Oscillator Circuit
Notes on using pins CKIO and CKIO2 as the clock outputs: Perform board design so that the
sum of pin capacitances of the CPU and socket that are connected to pins are 50 pF or less.
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Section 11 Extend Clock Pulse Generator for USB (EXCPG)
Section 11 Extend Clock Pulse Generator for USB
(EXCPG)
11.1
Overview
11.1.1
EXCPG
The SH7727 has an on-chip USB interface (USB) which requires a fixed 48-MHz clock source.
The extend clock pulse generator (EXCPG) generates a divided clock from the internal clock (Iφ),
the bus clock (Bφ), or the external clock (UCLK).
Because the clock sources, which can be a candidate to be used by EXCPG, vary from CPG
setting or external clock source, user of SH7727 must adjust the divided clock, carefully to be 48
MHz.
11.2
Functions
11.2.1
Block Diagram
Figure 11.1 shows a block diagram of the EXCPG.
USB clock
(48 MHz)
Peripheral clock (Pφ)
USB
host
Select
Internal clock (Iφ)
1/1
Bus clock (Bφ)
1/2
External clock (UCLK)
1/3
USB
function
Figure 11.1 Block Diagram of EXCPG
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Section 11 Extend Clock Pulse Generator for USB (EXCPG)
11.2.2
Pin Configuration
Table 11.1 shows a pin configuration of the EXCPG.
Table 11.1 Pin Configuration
Pin Name
Abbreviation
I/O
Description
External clock pin
UCLK
Input
USB clock input pin (48-MHz input)
Note: UCLK is multiplexed with PTD6.
11.2.3
Register Configuration
The EXCPG has the internal registers shown in table 11.2.
Table 11.2 Register Configuration
Name
Abbreviation
R/W
Initial Value
Address
Access Size
EXCPG control register
EXCPGCR
W
H’00
H'A4000236
8
11.3
Register Descriptions
11.3.1
EXCPG Control Register (EXCPGCR)
The EXCPG control register (EXCPGCR) selects the source clock and division ratio for
generation of the EXCPG clock.
EXCPGR is initialized to H'00 by a power-on reset.
Bit:
7
6
5
4
3
2
1
0
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
W
W
W
W
W
W
USBCKS USBCKS USBCKS USBDIVS USBDIVS USBDIVS
EL2
EL1
EL0
EL2
EL1
EL0
Bits 7 and 6—Reserved: These bits are always read as 0. The write value should always be 0.
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Section 11 Extend Clock Pulse Generator for USB (EXCPG)
Bits 5 to 3—Clock Select (USBCKSEL2 to USBCKSEL0): Selects the clock source. Although
initialized as peripheral clock (Pφ) after power on reset, the value of USBCKSEL must be changed
to adequate value to generate 48 MHz. To prevent malfunction, the USB Host and USB Function
must be set in module standby state or module reset state when the value of USBCKSEL is
changed.
Bits 5 to 3
Function (Clock Selection)
000
Peripheral Clock (Pφ)
100
Internal Clock (Iφ)
101
Bus Clock (Bφ)
110
External clock (UCLK)
Another value
Reserved (setting prohibited)
(Initial value)
Bits 2 to 0—Divider Select (USBDIVSEL2 to USBDIVSEL0): Selects the dividing ratio of
clock source to generate USB clock so that the USB clock is 48 MHz.
Bits 2 to 0
Function (Dividing Ratio Selection)
000
1/1
001
1/2
(Initial value)
010
1/3
1**
Internal clock (Iφ), bus clock (Bφ), external clock (UCLK) halted
Note: To reduce power consumption, set USBDIVSEL2 to 1 and halts internal clock (Iφ), bus clock
(Bφ), or external clock (UCLK) input.
11.4
Usage Notes
By selecting LCLK (LCD clock)/UCLK (USB clock) as the function of the LCLK/UCLK/PTD[6]
pin, it is possible to supply the clock input to the pin to both the LCD controller and the USB
function controller.
However, in this case it is necessary, using the divider select bit (USBDIVSEL[2:0]) in
EXCPGCR (EXCPG control register), to set the USB clock so that the final clock frequency is
48 MHz. This means that the input clock frequency will be 48 MHz. If this frequency is not
suitable as the operating clock for the LCD controller, consider selecting an internal clock for
LCLK. In addition, it may be impossible to maintain the accuracy of the USB standard clock
because the CPU clock (Iφ) and bus clock (Bφ) are generated by the internal PLL of the SH7727
by frequency multiplication. Therefore, it is recommended that a dedicated 48 MHz external clock
be input to UCLK to ensure the accuracy of the USB standard clock.
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Section 11 Extend Clock Pulse Generator for USB (EXCPG)
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Section 12 Bus State Controller (BSC)
Section 12 Bus State Controller (BSC)
12.1
Overview
The bus state controller (BSC) divides physical address space and output control signals for
various types of memory and bus interface specifications. BSC functions enable this LSI to link
directly with synchronous DRAM, SRAM, ROM, and other memory storage devices without an
external circuit. The BSC also allows direct connection to PCMCIA interfaces, simplifying system
design and allowing high-speed data transfers in a compact system.
12.1.1
Features
The BSC has the following features:
• Physical address space is divided into six areas
A maximum 64 Mbytes for each of the six areas, 0, 2 to 6
Area bus width can be selected by register (area 0 is set by external pin)
Wait states can be inserted using the WAIT pin
Wait state insertion can be controlled through software. Register settings can be used to
specify the insertion of 1–10 cycles independently for each area (1–38 cycles for areas 5
and 6 and the PCMCIA interface only)
The type of memory connected can be specified for each area, and
Control signals are output for direct memory connection
Wait cycles are automatically inserted to avoid data bus conflict for continuous memory
accesses to different areas or writes directly following reads of the same area
• Direct interface to synchronous DRAM (except if clock ratio Iφ:Bφ = 1:1)
Multiplexes row/column addresses according to synchronous DRAM capacity
Supports burst operation
Has both auto-refresh and self-refresh functions
Controls timing of synchronous DRAM direct-connection control signals according to
register setting
• Burst ROM interface
Insertion of wait states controllable through software
Register setting control of burst transfers
• PCMCIA direct-connection interface*
Insertion of wait states controllable through software
Bus sizing function for I/O bus width (only in the little endian mode)
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Section 12 Bus State Controller (BSC)
• Refresh function
Refresh cycles will be automatically maintained in the sleep mode even after the external
bus frequency is reduced to 1/4 of its normal operating frequency
• The refresh counter can be used as an interval timer
Outputs an interrupt request signal using the compare-matching function
Outputs an interrupt request signal when the refresh counter overflows
• Automatically disables the output of clock signals to anywhere but the refresh counter, except
during execution of external bus cycles
Note: * PCMCIA direct interface supported by the BSC is only signals and bus protocols shown
in table 12.5. For details on other control signals, refer to section 30, PC Card Controller
(PCC) (external circuit and this LSI on-chip card controller. In this BSI, both areas 5 and
6 has PCMICIA direct interface function common to the SH3 Series. The on-chip PC
Card Controller supports only area 6.
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Section 12 Bus State Controller (BSC)
12.1.2
Block Diagram
MD5 to MD3
Mode selection
Wait
controller
WAIT
CS0
CS6 to CS2
CE2A to CE2B
Area
controller
Bus
interface
Internal bus
Figure 12.1 shows the functional block diagram of the BSC.
WCR1
WCR2
BCR1
Peripheral bus
Interrupt
controller
MCR
Memory
controller
Module bus
BCR2
BS
RD
RD/WR
WE3 to WE0
RAS
CAS
CKE
ICIORD, ICIOWR
IOIS16
PCR
MR2
RFCR
RTCNT
Refresh
controller
Comparator
RTCOR
RTCSR
BSC
Legend:
WCR: Wait state contol register
BCR: Bus control register
MCR: Memory control register
PCR: PCMCIS control register
RFCR:
RTCNT:
RTCOR:
RTCSR:
Refresh count register
Refresh timer count register
Refresh time constant register
Refresh timer control/status register
Figure 12.1 Corresponding to Logical Address Space and Physical Address Space
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Section 12 Bus State Controller (BSC)
12.1.3
Pin Configuration
Table 12.1 lists the BSC pin configuration.
Table 12.1 Pin Configuration
Pin Name
Signal
I/O
Description
Address bus
A25–A0
Output
Address output
Data bus
D15–D0
I/O
Data I/O
D31–D16
I/O
When 32-bit bus width, data I/O
Bus cycle start
BS
Output
Shows start of bus cycle. During burst
transfers, asserts every data cycle.
Chip select 0, 2–4
CS0, CS2–CS4
Output
Chip select signal to indicate area being
accessed.
Chip select 5, 6
CS5/CE1A,
CS6/CE1B
Output
Chip select signal to indicate area being
accessed. CS5/CE1A and CS6/CE1B can
also be used as CE1A and CE1B of
PCMCIA.
PCMCIA card select
CE2A, CE2B
Output
When PCMCIA is used, CE2A and CE2B
Read/write
RD/WR
Output
Data bus direction indicator signal.
PCMCIA write indicator signal.
Row address strobe 3
RAS3
Output
When synchronous DRAM is used in area
3, RAS3 for 64-Mbyte address.
Column address strobe
CAS
Output
When synchronous DRAM is used, CAS
signal is used for 64Mbyte address.
Data enable 0
WE0/DQMLL
Output
When memory other than synchronous
DRAM is used, selects D7 to D0 write
strobe signal. When synchronous DRAM is
used, selects D7 to D0.
Data enable 1
WE1/DQMLU/
WE
Output
When memory other than synchronous
DRAM and PCMCIA is used, selects D15
to D8 write strobe signal. When
synchronous DRAM is used, selects D15 to
D8. When PCMCIA is used, strobe signal
that indicates the write cycle.
Data enable 2
WE2/DQMUL/
ICIORD
Output
When memory other than synchronous
DRAM and PCMCIA is used, selects D23
to D16 write strobe signal. When
synchronous DRAM is used, selects D23 to
D16. When PCMCIA is used, strobe signal
indicating I/O read.
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Section 12 Bus State Controller (BSC)
Pin Name
Signal
I/O
Description
Data enable 3
WE3/DQMUU/
ICIOWR
Output
When memory other than synchronous
DRAM and PCMCIA is used, selects D31
to D24 write strobe signal. When
synchronous DRAM is used, selects D31 to
D24. When PCMCIA is used, strobe signal
indicating I/O write.
Read
RD
Output
Strobe signal indicating read cycle
Wait
WAIT
Input
Wait state request signal
Clock enable
CKE
Output
Clock enable control signal of synchronous
DRAM
IOIS16
IOIS16
Input
Signal indicating PCMCIA 16-bit I/O. Valid
only in little-endian mode.
Bus release request
BREQ
Input
Bus release request signal
Bus release
acknowledgment
BACK
Output
Bus release acknowledge signal
Mode selection
MD5 to MD3
Input
Specifies bus width and endian of area 0
12.1.4
Register Configuration
The BSC has 11 registers (table 12.2). The synchronous DRAM also has a built-in synchronous
DRAM mode register. These registers control direct connection interfaces to memory, wait states,
and refreshes.
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Section 12 Bus State Controller (BSC)
Table 12.2 Register Configuration
Name
Abbr.
R/W
Initial Value* Address
Bus Width
Bus control register 1
BCR1
R/W
H'0000
H'FFFFFF60
16
Bus control register 2
BCR2
R/W
H'3FF0
H'FFFFFF62
16
Wait state control register 1
WCR1
R/W
H'3FF3
H'FFFFFF64
16
Wait state control register 2
WCR2
R/W
H'FFFF
H'FFFFFF66
16
Individual memory control
register
MCR
R/W
H'0000
H'FFFFFF68
16
PCMCIA control register
PCR
R/W
H'0000
H'FFFFFF6C
16
Refresh timer control/status
register
RTCSR
R/W
H'0000
H'FFFFFF6E
16
Refresh timer counter
RTCNT
R/W
H'0000
H'FFFFFF70
16
Refresh time constant register
RTCOR
R/W
H'0000
H'FFFFFF72
16
Refresh count register
RFCR
R/W
H'0000
H'FFFFFF74
16
SDMR
W
—
H'FFFFD000–
H'FFFFDFFF
8
Synchronous DRAM
mode register
For
area 2
For
area 3
H'FFFFE000–
H'FFFFEFFF
Notes: For details, see section 12.2.7, Synchronous DRAM Mode Register (SDMR).
* Initialized by power-on resets.
12.1.5
Area Overview
Space Allocation: In the architecture of this LSI, both logical spaces and physical spaces have 32bit address spaces. The logical space is divided into five areas by the value of the upper bits of the
address. The physical space is divided into eight areas.
Logical space can be allocated at physical spaces using a memory management unit (MMU). For
details, refer to section 3, Memory Management Unit (MMU), which describes area allocation for
physical spaces.
As listed in table 12.3, this LSI can be connected directly to six areas of memory/PC card
interface, and it outputs chip select signals (CS0, CS2 to CS6, CE2A, CE2B) for each of them.
CS0 is asserted during area 0 access; CS6 is asserted during area 6 access. When PCMCIA
interface is selected in area 5 or 6, in addition to CS5/CS6, CE2A/CE2B are asserted for the
corresponding bytes accessed.
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Section 12 Bus State Controller (BSC)
H'00000000
H'20000000
H'40000000
P0, U0
H'60000000
Area 0 (CS0)
H'00000000
Internal I/O
H'04000000
Area 2 (CS2)
H'08000000
Area 3 (CS3)
H'0C000000
Area 4 (CS4)
H'10000000
Area 5 (CS5)
H'14000000
H'18000000
Area 6 (CS6)
Reserved area
H'80000000
P1
Physical address space
H'A0000000
P2
H'C0000000
P3
H'E0000000
P4
Logical address space
Note: For logical address spaces P0 and P3, when the memory management unit (MMU) is
on, it can optionally generate a physical address for the logical address. It can be
applied when the MMU is off and when the MMU is on and each physical address for
the logical address is equal except for upper three bits. When translating logical
addresses to arbitrary physical addresses, refer to table 12.3 "Physical Address Space
Map".
Figure 12.2 Corresponding to Logical Address Space and Physical Address Space
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Section 12 Bus State Controller (BSC)
Table 12.3 Physical Address Space Map
Area
Connectable Memory
Physical Address (A28 to A0)
Capacity
Access Size
H'00000000 to H'03FFFFFF
64 Mbytes
8, 16, 32*
H'00000000 + H'2000000 x n to
H'03FFFFFF + H'2000000 x n
Shadow
(n = 1 to 6)
H'04000000 to H'07FFFFFF
64 Mbytes
8, 16, 32*
H'04000000 + H'2000000 x n to
H'07FFFFFF + H'2000000 x n
Shadow
(n = 1 to 6)
1
Ordinary memory* ,
Synchronous DRAM
H'08000000 to H'0BFFFFFF
64 Mbyte
3 4
8, 16, 32* *
H'08000000 + H'2000000 x n to
H'0BFFFFFF + H'2000000 x n
Shadow
(n = 1 to 6)
Ordinary memory,
Synchronous DRAM
H'0C000000 to H'0FFFFFFF
64 Mbytes
3 4
8, 16, 32* *
H'0C000000 + H'2000000 x n to
H'0FFFFFFF + H'2000000 x n
Shadow
(n = 1 to 6)
Ordinary memory
H'10000000 to H'13FFFFFF
64 Mbytes
8, 16, 32*
H'10000000 + H'2000000 x n to
H'13FFFFFF + H'2000000 x n
Shadow
(n = 1 to 6)
H'14000000 to H'15FFFFFF
32 Mbytes
3 5
8, 16, 32* *
H'16000000 to H'17FFFFFF
32 Mbytes
H'16000000 + H'2000000 x n to
H'17FFFFFF + H'2000000 x n
Shadow
(n = 1 to 6)
H'18000000 to H'19FFFFFF
32 Mbytes
3 5
8, 16, 32* *
H'1A000000 to H'1BFFFFFF
32 Mbytes
H'1A000000 + H'2000000 x n to
H'1BFFFFFF + H'2000000 x n
Shadow
*1
Ordinary memory ,
burst ROM
0
Internal I/O registers*
7
1
2
3
4
5
Ordinary memory,
PCMCIA, burst ROM
6
Ordinary memory,
PCMCIA, bust ROM
7*
6
Reserved area
Notes: 1.
2.
3.
4.
5.
6.
7.
H'1C000000 + H'20000000 × n to
H'1FFFFFFF + H'20000000 × n
2
3
3
(n = 1 to 6)
n = 0–7
Memory with interface such as SRAM or ROM.
Use external pin to specify memory bus width.
Use register to specify memory bus width.
With synchronous DRAM interfaces, bus width must be 16 or 32 bits.
With PCMCIA interface, bus width must be 8 or 16 bits.
The access to reserved area is prohibited.
When the control register in area 1 is not used for address translation by the MMU, set
the top three bits of the logical address to 101 to allocate in the P2 space.
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Section 12 Bus State Controller (BSC)
Area 0: H'00000000
Area 1: H'04000000
Ordinary memory/
burst ROM
Internal I/O
Area 2: H'08000000
Ordinary memory/
synchronous DRAM
Area 3: H'0C000000
Ordinary memory/
synchronous DRAM
Area 4: H'10000000
Ordinary memory
Area 5: H'14000000
Ordinary memory/
burst ROM/PCMCIA
The PCMCIA interface is shared
by the memory and I/O card
Area 6: H'18000000
Ordinary memory/
burst ROM/PCMCIA
The PCMCIA interface is shared
by the memory and I/O card
Figure 12.3 Physical Space Allocation
Memory Bus Width: The memory bus width in this LSI can be set for each area. In area 0, an
external pin can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on
reset as setting of MD4 and MD3 as below table .
Table 12.4 Correspondence between External Pins (MD4 and MD3) and Memory bus
width in area0
MD4
MD3
Memory Size
0
0
Reserved (Setting prohibited)
1
8 bits
1
0
16 bits
1
32 bits
For areas 2 to 6, byte, word, and longword may be chosen for the bus width using bus control
register 2 (BCR2) whenever ordinary memory, ROM, or burst ROM are used.
When the PCMCIA interface is used, set the bus width to byte or word. When synchronous
DRAM is connected to both area 2 and area 3, set the same bus width for areas 2 and 3. When
using the port function, set each of the bus widths to byte or word for all areas. For more
information, see section 12.2.2, Bus Control Register 2 (BCR2).
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Section 12 Bus State Controller (BSC)
Shadow Space: Areas 0, 2 to 6 are decoded by physical addresses A28 to A26, which correspond
to areas 000 to 110. Address bits 31 to 29 are ignored. This means that the range of area 0
addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the
address space obtained by adding to it H'20000000 × n (n = 1 to 6). The address range for area 7,
which is on-chip I/O space, is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 +
H'20000000 × n to H'1FFFFFFF + H'20000000 × n (n = 0 to 7) corresponding to the area 7
shadow space is reserved, so do not use it.
12.1.6
PC Card Support
The Bus Controller of this LSI supports protocol signals of PCMCIA standard interface
specifications in physical space areas 5 and 6 as another SH3 Series.
PC Card Bus signal (CEIA,CE2A,CE1B,CE2B,IOIS16) are supported for PC Card Bus Protocol
as same as SH7708/SH7709/SH7729 series.
Dynamic bus sizing of I/O bus width is supported only in the little endian made.
Table 12.5 SH7727 and PCMCIA Pins
SH7727
PCMCIA
CE1A
CE1
CE1B
CE1
CE2A
CE2
CE2B
CE2
WE
WE/PGM
RD
OE
IOIS16
WP/IOIS16
ICIORD
IORD
ICIOWR
IOWR
A25–A0
A25–A0
D15–D0
D15–D0
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Section 12 Bus State Controller (BSC)
12.2
BSC Registers
12.2.1
Bus Control Register 1 (BCR1)
Bus control register 1 (BCR1) is a 16-bit read/write register that sets the functions and bus cycle
state for each area. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual
reset or by standby mode. Do not access external memory outside area 0 until BCR1 register
initialization is complete.
Bit:
15
14
PULA PULD
Initial value:
R/W:
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HIZ
HIZ ENDI A0
A0
A5
A5
A6
A6 DRAM DRAM DRAM A5
A6
MEM CNT AN BST1 BST0 BST1 BST0 BST1 BST0 TP2 TP1 TP0 PCM PCM
0
0
0
0
0/1*
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Samples the value of the external pin (MD5) designating endian at power-on reset.
Bit 15—Pins A25 to A0 Pull-Up (PULA): Specifies whether or not pins A25 to A0 are pulled up
for 4 cycles immediately after BACK is asserted.
Bit 15: PULA
Description
0
Not pulled up
1
Pulled up
(Initial value)
Bit 14—Pins D31 to D0 Pull-Up (PULD): Specifies whether or not pins D31 to D0 are pulled up
when not in use.
Bit 14: PULD
Description
0
Not pulled up (Initial value)
1
Pulled up
Bit 13—Hi-Z memory control (HIZMEM): Specifies the state of A25 to A0, BS, CS, RD/WR,
WE/DQM, RD, CE2A, CE2B and DRAK0 in standby mode.
Bit 13: HIZMEM
Description
0
High-impedance state in standby mode.
1
High in standby mode.
(Initial value)
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Section 12 Bus State Controller (BSC)
Bit 12—High-Z Control (HIZCNT): Specifies the state of the RAS and the CAS signals at
standby and bus right release.
Bit 12: HIZCNT
Description
0
The RAS and the CAS signals are high-impedance state (High-Z) at standby
and bus right release.
(Initial value)
1
The RAS and the CAS signals are driven at standby and bus right release.
Bit 11—Endian Flag (ENDIAN): Samples the value of the external pin designating endian upon
a power-on reset. Endian for all physical spaces is decided by this bit, which is read-only.
Bit 11: ENDIAN
Description
0
(On reset) Endian setting external pin (MD5) is low. Indicates this LSI is set
as big endian.
1
(On reset) Endian setting external pin (MD5) is high. Indicates this LSI is set
as little endian.
Bits 10 and 9—Area 0 Burst ROM Control (A0BST1, A0BST0): Specify whether to use burst
ROM in physical space area 0. When burst ROM is used, set the number of burst transfers.
Bit 10: A0BST1
Bit 9: A0BST0
Description
0
0
Access area 0 as ordinary memory
1
Access area 0 as burst ROM (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
0
Access area 0 as burst ROM (8 consecutive accesses).
Can be used when bus width is 8 or 16.
1
Access area 0 as burst ROM (16 consecutive
accesses). Can be used only when bus width is 8.
1
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(Initial value)
Section 12 Bus State Controller (BSC)
Bits 8 and 7—Area 5 Burst Enable (A5BST1, A5BST0): Specify whether to use burst ROM
and PCMCIA burst mode in physical space area 5. When burst ROM and PCMCIA burst mode
are used, set the number of burst transfers.
Bit 8: A5BST1
Bit 7: A5BST0
Description
0
0
Access area 5 as ordinary memory
1
Burst access of area 5 (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
0
Burst access of area 5 (8 consecutive accesses).
Can be used when bus width is 8 or 16.
1
Burst access of area 5 (16 consecutive accesses).
Can be used only when bus width is 8.
1
(Initial value)
Bits 6 and 5—Area 6 Burst Enable (A6BST1, A6BST0): Specify whether to use burst ROM
and PCMCIA burst mode in physical space area 6. When burst ROM and PCMCIA burst mode
are used, set the number of burst transfers.
Bit 6: A6BST1
Bit 5: A6BST0
Description
0
0
Access area 6 as ordinary memory
1
Burst access of area 6 (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
0
Burst access of area 6 (8 consecutive accesses).
Can be used when bus width is 8 or 16.
1
Burst access of area 6 (16 consecutive accesses).
Can be used only when bus width is 8.
1
(Initial value)
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Section 12 Bus State Controller (BSC)
Bits 4 to 2—Area 2, Area 3 Memory Type (DRAMTP2, DRAMTP1, DRAMTP0): Designate
the types of memory connected to physical space areas 2 and 3. Ordinary memory, such as ROM,
SRAM, or flash ROM, can be directly connected. Synchronous DRAM can also be directly
connected.
Bit 4: DRAMTP2
Bit 3: DRAMTP1
Bit 2: DRAMTP0
Description
0
0
0
Areas 2 and 3 are ordinary memory
(Initial value)
1
Reserved (Setting disabled)
0
Area 2: ordinary memory;
1
Area 3: synchronous DRAM*
1
Areas 2 and 3 are synchronous
1 2
DRAM* *
0
Reserved (Setting disabled)
1
Reserved (Setting disabled)
0
Reserved (Setting disabled)
1
Reserved (Setting disabled)
1
1
0
1
Notes: 1. When selecting this mode, set the same bus width for area 2 and area 3.
2. If clock rate is specified as 1φ : Bus clock = 1:1 , synchronous DRAM cannot be
accessed.
Bit 1—Area 5 Bus Type (A5PCM): Designates whether to access physical space area 5 as
PCMCIA space.
Bit 1: A5PCM
Description
0
Access physical space area 5 as ordinary memory
1
Access physical space area 5 as PCMCIA space
(Initial value)
Bit 0—Area 6 Bus Type (A6PCM): Designates whether to access physical space area 6 as
PCMCIA space.
Bit 0: A6PCM
Description
0
Access physical space area 6 as ordinary memory
1
Access physical space area 6 as PCMCIA space
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(Initial value)
Section 12 Bus State Controller (BSC)
12.2.2
Bus Control Register 2 (BCR2)
The bus control register 2 (BCR2) is a 16-bit read/write register that selects the bus-size width of
each area. It is initialized to H'3FF0 by a power-on reset, but is not initialized by a manual reset or
by standby mode. Do not access external memory outside area 0 until BCR2 register initialization
is complete.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
A6
SZ1
A6
SZ0
A5
SZ1
A5
SZ0
A4
SZ1
A4
SZ0
A3
SZ1
A3
SZ0
A2
SZ1
A2
SZ0
—
—
—
—
Initial value:
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
R/W:
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
Bits 15, 14, 3, 2, 1, and 0—Reserved: These bits are always read as 0. The write value should
always be 0.
Bits 2n + 1, 2n—Area n (2 to 6) Bus Size Specification (AnSZ1, AnSZ0): Specify the bus sizes
of physical space area n (n = 2 to 6).
Bit 2n + 1: AnSZ1
Bit 2n: AnSZ0
Port A / B
Description
0
0
Unused
Reserved (Setting disabled)
1
1
Byte (8-bit) size
0
Word (16-bit) size
1
Longword (32-bit) size
0
0
Used
Reserved (Setting disabled)
1
Byte (8-bit) size
1
0
Word (16-bit) size
1
Reserved (Setting disabled)
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Section 12 Bus State Controller (BSC)
12.2.3
Wait State Control Register 1 (WCR1)
Wait state control register 1 (WCR1) is a 16-bit read/write register that specifies the number of
idle (wait) state cycles inserted for each area. For some memories, the drive of the data bus may
not be turned off quickly even when the read signal from the external device is turned off. This
can result in conflicts between data buses when consecutive memory accesses are to different
memories or when a write immediately follows a memory read. This LSI automatically inserts idle
states equal to the number set in WCR1 in those cases.
WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or by
standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WAIT
SEL
—
A6
IW1
A6
IW0
A5
IW1
A5
IW0
A4
IW1
A4
IW0
A3
IW1
A3
IW0
A2
IW1
A2
IW0
—
—
A0
IW1
A0
IW0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Bit 15—WAIT Sampling Timing Select (WAITSEL): Specifies the WAIT signal sampling
timing.
Bit 15: WAITSEL
Description
0
Set to 1 when WAIT signal is used.*
1
Sampled at the falling edge of CKIO.
(Initial value)
Note: * If low level is input to the WAIT by setting the WAITSEL bit, the LSI operation cannot be
guaranteed.
Bits 14, 3, and 2 —Reserved: These bits are always read as 0. The write value should always be
0.
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Section 12 Bus State Controller (BSC)
Bits 2n + 1, 2n—Area n (6 to 2, 0) Intercycle Idle Specification (AnIW1, AnIW0): Specify the
number of idles inserted between bus cycles when switching between physical space area n (6 to
2, 0) to another space or between a read access to a write access in the same physical space.
Bit 2n + 1: AnIW1
Bit 2n: AnIW0
Description
0
0
1 idle cycle inserted
1
1 idle cycle inserted
0
2 idle cycles inserted
1
3 idle cycles inserted (Initial value)
1
12.2.4
Wait State Control Register 2 (WCR2)
Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of
wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory
accesses. This allows direct connection of even low-speed memories without an external circuit.
WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or by
standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A6
W2
A6
W1
A6
W0
A5
W2
A5
W1
A5
W0
A4
W2
A4
W1
A4
W0
A3
W1
A3
W0
A2
W1
A2
W0
A0
W2
A0
W1
A0
W0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 12 Bus State Controller (BSC)
Bits 15 to 13—Area 6 Wait Control (A6W2, A6W1, A6W0): Specify the number of wait states
inserted into physical space area 6. Also specify the burst pitch for burst transfer.
Description
Burst Cycle
(Excluding First Cycle)
First Cycle
Bit 15: Bit 14:
A6W2
A6W1
Bit 13:
A6W0
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
0
0
Disable
2
Enable
1
1
Enable
2
Enable
0
2
Enable
3
Enable
1
3
Enable
4
Enable
0
4
Enable
4
Enable
1
6
Enable
6
Enable
0
8
Enable
8
Enable
1
10
(Initial value)
Enable
10
Enable
0
1
1
0
1
Bits 12 to 10—Area 5 Wait Control (A5W2, A5W1, A5W0): Specify the number of wait states
inserted into physical space area 5. Also specify the burst pitch for burst transfer.
Description
Burst Cycle
(Excluding First Cycle)
First Cycle
Bit 12:
A5W2
Bit 11:
A5W1
Bit 10:
A5W0
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
0
0
0
Disable
2
Enable
1
1
Enable
2
Enable
0
2
Enable
3
Enable
1
3
Enable
4
Enable
0
4
Enable
4
Enable
1
6
Enable
6
Enable
0
8
Enable
8
Enable
1
10
(Initial value)
Enable
10
Enable
1
1
0
1
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Section 12 Bus State Controller (BSC)
Bits 9 to 7—Area 4 Wait Control (A4W2, A4W1, A4W0): Specify the number of wait states
inserted into physical space area 4.
Description
Bit 9: A4W2
Bit 8: A4W1
Bit 7: A4W0
Inserted Wait State
WAIT Pin
0
0
0
0
Ignored
1
1
Enable
0
2
Enable
1
3
Enable
0
4
Enable
1
6
Enable
0
8
Enable
1
10
Enable (Initial value)
1
1
0
1
Bits 6 and 5—Area 3 Wait Control (A3W1, A3W0): Specify the number of wait states inserted
into physical space area 3.
• For Ordinary memory
Description
Bit 6: A3W1
Bit 5: A3W0
Inserted Wait States
WAIT Pin
0
0
0
Ignored
1
1
Enable
0
2
Enable
1
3
Enable
1
(Initial value)
• For Synchronous SDRAM
Description
Bit 6: A3W1
Bit 5: A3W0
Synchronous SDRAM: CAS Latency
0
0
1
1
1
0
2
1
3
1
(Initial value)
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Section 12 Bus State Controller (BSC)
Bits 4 and 3—Area 2 Wait Control (A2W1, A2W0): Specify the number of wait states inserted
into physical space area 2.
• For Ordinary memory
Description
Bit 4: A2W0
Bit 3: A2W0
Inserted Wait States
WAIT Pin
0
0
0
Ignored
1
1
Enable
0
2
Enable
1
3
Enable
1
(Initial value)
• For Synchronous SDRAM
Description
Bit 4: A2W1
Bit 3: A2W0
Synchronous DRAM: CAS Latency
0
0
1
1
1
0
2
1
3
1
(Initial value)
Bits 2 to 0—Area 0 Wait Control (A0W2, A0W1, A0W0): Specify the number of wait states
inserted into physical space area 0. Also specify the burst pitch for burst transfer.
Description
Burst Cycle
(Excluding First Cycle)
First Cycle
Bit 2:
A0W2
Bit 1:
A0W1
Bit 0:
A0W0
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
0
0
0
Ignored
2
1
1
Enable
2
Enable
1
0
2
Enable
3
Enable
1
3
Enable
4
Enable
0
4
Enable
4
Enable
1
6
Enable
6
Enable
0
8
Enable
8
Enable
1
10
(Initial value)
Enable
10
Enable
1
0
1
Rev. 5.00 Dec 12, 2005 page 302 of 1034
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Enable
Section 12 Bus State Controller (BSC)
12.2.5
Individual Memory Control Register (MCR)
The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS
and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address
multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without
external circuits.
The MCR is initialized to H'0000 by power-on resets, but is not initialized by manual resets or
standby mode. The bits TPC1 to TPC0, RCD1 to RCD0, TRWL1 to TRWL0, TRAS1 to TRAS0,
AMX3 to AMX0, and are written to at the initialization after a power-on reset and are not then
modified again. When RFSH and RMODE are written to, write the same values to the other bits.
When using synchronous DRAM, do not access areas 2 and 3 until this register is initialized.
Bit:
15
14
13
12
11
10
9
8
7
TPC1 TPC0 RCD1 RCD0 TRWL TRWL TRAS TRAS
1
0
1
0
Initial value:
R/W:
—
6
5
4
3
2
1
AMX3 AMX2 AMX1 AMX0 RFSH RMO
DE
0
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 and 14—RAS Precharge Time (TPC1, TPC0): These bits set the minimum number of
cycles until output of the next bank-active command after precharge, when the synchronous
DRAM interface is selected for external memory. However, the number of cycles inserted
immediately after the precharge all banks (PALL) command is issued when performing autorefresh is one fewer than the number of cycles during normal operation.
Description
Bit 15:
TPC1
Bit 14:
TPC0
Normal Operation
Immediately After
Precharge Command*
Immediately After
Self-refresh
0
0
1 cycle
0 cycle
2 cycles
1
2 cycles
1 cycle
5 cycles
1
0
3 cycles
2 cycles
8 cycles
1
4 cycles
3 cycles
11 cycles
(Initial value)
(Initial value)
(Initial value)
Note: * Immediately after the precharge all banks (PALL) command is issued when performing
auto-refresh.
Rev. 5.00 Dec 12, 2005 page 303 of 1034
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Section 12 Bus State Controller (BSC)
Bits 13 and 12—RAS–CAS Delay (RCD1, RCD0): When synchronous DRAM interface is
selected, sets the bank active read/write command delay time.
Bit 13: RCD1
Bit 12: RCD0
Description
0
0
1 cycle
1
2 cycles
0
3 cycles
1
4 cycles
1
(Initial value)
Bits 11 and 10—Write-Precharge Delay (TRWL1, TRWL0): The TRWL bits set the
synchronous DRAM write-precharge delay time. This designates the time between the end of a
write cycle and the next bank-active command. This is valid only when synchronous DRAM is
connected. After the write cycle, the next bank-active command is not issued for the period TPC +
TRWL.
Bit 11: TRWL1
Bit 10: TRWL0
Description
0
0
1 cycle
1
2 cycles
1
0
3 cycles
1
Reserved (Setting disabled)
(Initial value)
Bits 9 and 8—CAS
CAS-Before-RAS
RAS Refresh RAS Assert Time (TRAS1, TRAS0): When
CAS
synchronous DRAM interface is selected, no bank-active command is issues during the period
TPC + TRAS after an auto-refresh command.
Bit 9: TRAS1
Bit 8: TRAS0
Description
0
0
2 cycles
1
3 cycles
0
4 cycles
1
5 cycles
1
(Initial value)
Bit 7—Reserved: This bit is always read as 0. The write value should always be 0.
Bits 6 to 3—Address Multiplex (AMX3 , AMX2, AMX1, AMX0): The AMX bits specify
address multiplexing for synchronous DRAM. The actual address shift value differs between
synchronous DRAM interface.
Rev. 5.00 Dec 12, 2005 page 304 of 1034
REJ09B0254-0500
Section 12 Bus State Controller (BSC)
For Synchronous DRAM Interface: (see table 12.12)
Bit6:
AMX3
Bit5:
AMX2
Bit 4:
AMX1
Bit 3:
AMX0
Description
1
1
0
1
The row address begins with A10 when bus width is 16 bit.
The row address begins with A11 when bus width is 32 bit.
(The A10 value is output at A1 when the row address is
output. 4M × 16-bit × 4-bank products)
1
0
The row address begins with A11 when bus width is 16 bit.
(The A11 value is output at A1 when the row address is
1
output. 8M × 16-bit × 4-bank products)*
0
1
0
0
The row address begins with A9 when bus width is 16 bit.
The row address begins with A10 when bus width is 32 bit.
(The A9 value is output at A1 when the row address is
output. 1M × 16-bit × 4-bank products)
1
The row address begins with A10 when bus width is 16 bit.
The row address begins with A11 when bus width is 32 bit.
(The A10 value is output at A1 when the row address is
output. 2M × 16-bit × 4-bank products)
1
0
The row address begins with A11 when bus width is 32 bit.*
2
(The A11 value is output at A1 when the row address is
output. 2M × 16-bit × 4-bank products)
1
The row address begins with A9 when bus width is 16 bit.
The row address begins with A10 when bus width is 32 bit.
(The A9 value is output at A1 when the row address is
output. 512K × 32-bit × 4-bank products)
0
0
Values other than above
0
Reserved. AMX3 to AMX0 must be set to *1*** before
accessing synchronous DRAM memory.
(Initial value)
Reserved (illegal setting)
Notes: 1. Can only be set when using a 16-bit bus width.
2. Can only be set when using a 32-bit bus width.
Rev. 5.00 Dec 12, 2005 page 305 of 1034
REJ09B0254-0500
Section 12 Bus State Controller (BSC)
Bit 2—Refresh Control (RFSH): The RFSH bit determines whether or not the refresh operation
of the synchronous DRAM is performed. The timer for generation of the refresh request frequency
can also be used as an interval timer.
Bit 2: RFSH
Description
0
No refresh
1
Refresh
(Initial value)
Bit 1—Refresh Mode (RMODE): The RMODE bit selects whether to perform an ordinary
refresh or a self-refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 0, a CASbefore-RAS refresh or an auto-refresh is performed on synchronous DRAM at the period set by
the refresh-related registers RTCNT, RTCOR and RTCSR. When a refresh request occurs during
an external bus cycle, the bus cycle will be ended and the refresh cycle performed. When the
RFSH bit is 1 and this bit is also 1, the synchronous DRAM will wait for the end of any executing
external bus cycle before going into a self-refresh. All refresh requests to memory that is in the
self-refresh state are ignored.
Bit 1: RMODE
Description
0
CAS-before-RAS refresh (RFSH must be 1)
1
Self-refresh (RFSH must be 1)
(Initial value)
Bit 0—Reserved: This bit is always read as 0. The write value should always be 0.
12.2.6
PCMCIA Control Register (PCR)
The PCMCIA control register (RCR) specifies the assert/negate timing of the OE and WE signals
(RD and WE1 pins of this LSI) for the PCMCIA interface connected to areas 5 and 6. Note that
the assertion widths of OE and WE are set using the wait control bits of the WCR2 register.
The PCR register is a 16-bit read/write register. It is initialized at a power-on reset to H'0000.
However, the register is not initialized and the contents remain unchanged at a manual reset and
when in standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
A6
W3
A5
W3
—
—
11
10
9
8
7
6
5
4
3
2
1
0
A5
A6
A5
A6
A5
A5
A6
A6
A5
A5
A6
A6
TED2 TED2 TEH2 TEH2 TED1 TED0 TED1 TED0 TEH1 TEH0 TEH1 TEH0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Dec 12, 2005 page 306 of 1034
REJ09B0254-0500
Section 12 Bus State Controller (BSC)
Bit 15—Area 6 Wait Control (A6W3): The A6W3 bit specifies the number of inserted wait
states for area 6 combined with bits A6W2 to A6W0 in WCR2. It also specifies the number of
transfer states in burst transfer. Set this bit to 0 when area 6 is not set to PCMCIA.
Top Cycle
Burst Cycle
A6W3
A6W2
A6W1
A6W0
Inserted
Wait State
WAIT Pin
Number of
States per
One-data
Transfer
0
0
0
0
0
Ignored
2
Enabled
1
1
Enabled
2
Enabled
0
2
Enabled
3
Enabled
1
3
Enabled
4
Enabled
0
4
Enabled
5
Enabled
1
6
Enabled
7
Enabled
0
8
Enabled
9
Enabled
1
10
(Initial value)
Enabled
11
Enabled
0
12
Enabled
13
Enabled
1
14
Enabled
15
Enabled
0
18
Enabled
19
Enabled
1
22
Enabled
23
Enabled
0
26
Enabled
27
Enabled
1
30
Enabled
31
Enabled
0
34
Enabled
35
Enabled
1
38
Enabled
39
Enabled
1
1
0
1
1
0
0
1
1
0
1
WAIT Pin
Bit 14—Area 5 Wait Control (A5W3): The A5W3 bit specifies the number of inserted wait
states for area 5 combined with bits A5W2 to A5W0 in WCR2. It also specifies the number of
transfer states in burst transfer. Set this bit to 0 when area 5 is not set to PCMCIA.
The relationship between the setting value and the number of waits is the same as A6W3.
Bits 13 and 12—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 5.00 Dec 12, 2005 page 307 of 1034
REJ09B0254-0500
Section 12 Bus State Controller (BSC)
Bits 11, 7, and 6—Area 5 Address OE/WE
OE WE Assert Delay (A5TED2, A5TED1, and A5TED0):
The A5TED bits specify the address to OE/WE assert delay time for the PCMCIA interface
connected to area 5.
Bit 11:
A5TED2
Bit 7:
A5TED1
Bit 6:
A5TED0
Description
0
0
0
0.5-cycle delay
1
1.5-cycle delay
0
2.5-cycle delay
1
3.5-cycle delay
0
4.5-cycle delay
1
5.5-cycle delay
0
6.5-cycle delay
1
7.5-cycle delay
1
1
0
1
(Initial value)
Bits 10, 5 and 4—Area 6 Address OE/WE
OE WE Assert Delay (A6TED2, A6TED1, and A6TED0):
The A6TED bits specify the address to OE/WE assert delay time for the PCMCIA interface
connected to area 6.
Bit 10:
A6TED2
Bit 5:
A6TED1
Bit 4:
A6TED0
Description
0
0
0
0.5-cycle delay
1
1.5-cycle delay
0
2.5-cycle delay
1
3.5-cycle delay
0
4.5-cycle delay
1
5.5-cycle delay
0
6.5-cycle delay
1
7.5-cycle delay
1
1
0
1
Rev. 5.00 Dec 12, 2005 page 308 of 1034
REJ09B0254-0500
(Initial value)
Section 12 Bus State Controller (BSC)
Bits 9, 3, and 2—Area 5 OE/WE
OE WE Negate Address Delay(A5TEH2, A5TEH1, and A5TEH0):
The A5TEH bits specify the OE/WE negate address delay time for the PCMCIA interface
connected area 5.
Bit 9:
A5TEH2
Bit 3:
A5TEH1
Bit 2:
A5TEH0
Description
0
0
0
0.5-cycle delay
1
1.5-cycle delay
0
2.5-cycle delay
1
3.5-cycle delay
0
4.5-cycle delay
1
5.5-cycle delay
0
6.5-cycle delay
1
7.5-cycle delay
1
1
0
1
(Initial value)
Bits 8, 1, and 0—Area6 OE/WE
OE WE Negate Address Delay (A6TEH2, A6TEH1, and A6TEH0):
The A6TEH bits specify the OE/WE negate address delay time for the PCMCIA interface
connected to area 6.
Bit 8:
A6TEH2
Bit 1:
A6TEH1
Bit 0:
A6TEH0
Description
0
0
0
0.5-cycle delay
1
1.5-cycle delay
0
2.5-cycle delay
1
3.5-cycle delay
0
4.5-cycle delay
1
5.5-cycle delay
0
6.5-cycle delay
1
7.5-cycle delay
1
1
0
1
(Initial value)
Rev. 5.00 Dec 12, 2005 page 309 of 1034
REJ09B0254-0500
Section 12 Bus State Controller (BSC)
12.2.7
Synchronous DRAM Mode Register (SDMR)
The synchronous DRAM mode register (SDMR) is written to via the synchronous DRAM address
bus and is an 8-bit write-only register. It sets synchronous DRAM mode for areas 2 and 3. SDMR
is undefined after a power-on reset. The register contents are not initialized by a manual reset or
standby mode; values remain unchanged.
Bit:
31
......................
12
SDMR address
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
Initial value:
—
......................
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W:
—
......................
—
W*
W*
W
W
W
W
W
W
W
W
—
—
Note: * Depending on the type of synchronous DRAM.
Writes to the synchronous DRAM mode register use the address bus rather than the data bus. If
the value to be set is X and the SDMR address is Y, the value X is written in the synchronous
DRAM mode register by writing in address X + Y. Since, with a 32-bit bus width, A0 of the
synchronous DRAM is connected to A2 of the chip and A1 of the synchronous DRAM is
connected to A3 of the chip, the value actually written to the synchronous DRAM is the X value
shifted two bits right. With a 16-bit bus width, the value written is the X value shifted one bit
right. For example, with a 32-bit bus width, when H'0230 is written to the SDMR register of area
2, random data is written to the address H'FFFFD000 (address Y) + H'08C0 (value X), or
H'FFFFD8C0. As a result, H'0230 is written to the SDMR register. The range for value X is
H'0000 to H'0FFC. When H'0230 is written to the SDMR register of area 3, random data is written
to the address H'FFFFE000 (address Y) + H'08C0 (value X), or H'FFFFE8C0. As a result, H'0230
is written to the SDMR register. The range for value X is H'0000 to H'0FFC.
Rev. 5.00 Dec 12, 2005 page 310 of 1034
REJ09B0254-0500
Section 12 Bus State Controller (BSC)
12.2.8
Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTCSR) is a 16-bit read/write register that specifies the
refresh cycle, whether to generate an interrupt, and that interrupt's cycle. It is initialized to H'0000
by a power-on reset, but is not initialized by a manual reset or standby mode. Before specifying
the CKS2 to CKS0 of RTCST, the RTCOR must be specified.
Note: Writing to the RTCSR differs from that to general registers to ensure the RTCSR is not
rewritten incorrectly. Use the word-transfer instruction to set the upper byte as
B'10100101 and the lower byte as the write data. For details, see section 12.2.12, Cautions
on Accessing Refresh Control Related Registers.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Compare Match Flag (CMF): The CMF status flag indicates that the values of RTCNT
and RTCOR match.
Bit 7: CMF
Description
0
The values of RTCNT and RTCOR do not match.
Clear condition: When a refresh is performed After 0 has been written in
CMF and RFSH = 1 and RMODE = 0 (to perform a CBR refresh).
(Initial value)
1
The values of RTCNT and RTCOR match.
Set condition: RTCNT = RTCOR*
Note: * Contents do not change when 1 is written to CMF.
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request
caused when the CMF of RTCSR is set to 1. Do not set this bit to 1 when using CAS-before-RAS
refresh or auto-refresh.
Bit 6: CMIE
Description
0
Disables an interrupt request caused by CMF
1
Enables an interrupt request caused by CMF
(Initial value)
Rev. 5.00 Dec 12, 2005 page 311 of 1034
REJ09B0254-0500
Section 12 Bus State Controller (BSC)
Bits 5 to 3—Clock Select Bits (CKS2 to CKS0): Select the clock input to RTCNT. The source
clock is the external bus clock (BCLK). The RTCNT count clock is CKIO divided by the specified
ratio. The specified ratios are shown below in the normal external bus clock. Before specifying
the CKS2 to CKS0 of RTCST, the RTCOR must be specified.
Description
Bit 5: CKS2
Bit 4: CKS1
Bit 3: CKS0
Normal external bus clock
0
0
0
Disables clock input
1
Bus clock (CKIO)/4
0
CKIO/16
1
CKIO/64
0
CKIO/256
1
CKIO/1024
0
CKIO/2048
1
CKIO/4096
1
1
0
1
(Initial value)
Bit 2—Refresh Count Overflow Flag (OVF): The OVF status flag indicates when the number of
refresh requests indicated in the refresh count register (RFCR) exceeds the limit set in the LMTS
bit of RTCSR.
Bit 2: OVF
Description
0
RFCR has not exceeded the count limit value set in LMTS
Clear Conditions: When 0 is written to OVF
1
(Initial value)
RFCR has exceeded the count limit value set in LMTS
Set Conditions: When the RFCR value has exceeded the count limit value
set in LMTS*
Note: * Contents don't change when 1 is written to OVF.
Bit 1—Refresh Count Overflow Interrupt Enable (OVIE): OVIE selects whether to suppress
generation of interrupt requests by OVF when the OVF bit of RTCSR is set to 1.
Bit 1: OVIE
Description
0
Disables interrupt requests from the OVF
1
Enables interrupt requests from the OVF
Rev. 5.00 Dec 12, 2005 page 312 of 1034
REJ09B0254-0500
(Initial value)
Section 12 Bus State Controller (BSC)
Bit 0—Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be
compared to the number of refreshes indicated in the refresh count register (RFCR). When the
value RFCR overflows the value specified by LMTS, the OVF flag is set.
Bit 0: LMTS
Description
0
Count limit value is 1024
1
Count limit value is 512
12.2.9
(Initial value)
Refresh Timer Counter (RTCNT)
RTCNT is a 16-bit read/write register. RTCNT is an 8-bit counter that counts up with input
clocks. The clock select bits (CKS2 to CKS0) of RTCSR select the input clock. When RTCNT
matches RTCOR, the CMF bit of TCSR is set and RTCNT is cleared. RTCNT is initialized to
H'00 by a power-on reset; it continues incrementing after a manual reset; it is not initialized by
standby mode and holds its values unchanged.
Note: Writing to the RTCNT differs from that to general registers to ensure the RTCNT is not
rewritten incorrectly. Use the word-transfer instruction to set the upper byte as
B'10100101 and the lower byte as the write data. For details, see section 12.2.12, Cautions
on Accessing Refresh Control Related Registers.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Dec 12, 2005 page 313 of 1034
REJ09B0254-0500
Section 12 Bus State Controller (BSC)
12.2.10 Refresh Time Constant Register (RTCOR)
The refresh time constant register (RTCOR) is a 16-bit read/write register. The values of RTCOR
and RTCNT (bottom 8 bits) are constantly compared. When the values match, the compare match
flag (CMF) of RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) of the
individual memory control register (MCR) is set to 1 and the refresh mode is set to CAS-beforeRAS refresh, a memory refresh cycle occurs when the CMF bit is set. RTCOR is initialized to
H'00 by a power-on reset. It is not initialized by a manual reset or standby mode, but holds its
contents. Make the RTCOR setting before setting bits CKS2 to CKS0 in RTCSR.
Note: Writing to the RTCOR differs from that to general registers to ensure the RTCOR is not
rewritten incorrectly. Use the word-transfer instruction to set the upper byte as
B'10100101 and the lower byte as the write data. For details, see section 12.2.12, Cautions
on Accessing Refresh Control Related Registers.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
12.2.11 Refresh Count Register (RFCR)
The refresh count register (RFCR) is a 16-bit read/write register. It is a 10-bit counter that
increments every time RTCOR and RTCNT match. When RFCR exceeds the count limit value set
in the LMTS of RTCSR, RTCSR's OVF bit is set and RFCR clears. RFCR is initialized to H'0000
when a power-on reset is performed. It is not initialized by a manual reset or standby mode, but
holds its contents.
Note: Writing to the RFCR differs from that to general registers to ensure the RFCR is not
rewritten incorrectly. Use the word-transfer instruction to set the MSB and followed six
bits of upper bytes as B'101001 and remaining bits as the write data. For details, see
section 12.2.12, Cautions on Accessing Refresh Control Related Registers.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Dec 12, 2005 page 314 of 1034
REJ09B0254-0500
Section 12 Bus State Controller (BSC)
12.2.12 Cautions on Accessing Refresh Control Related Registers
RFCR, RTCSR, RTCNT, and RTCOR require that a specific code be appended to the data when it
is written to prevent data from being mistakenly overwritten by program overruns or other write
operations (figure 12.4). Perform reads and writes using the following methods:
1. Writing to RFCR, RTCSR, RTCNT, and RTCOR
When writing to RFCR, RTCSR, RTCNT, and RTCOR, use only word transfer instructions.
You cannot write with byte transfer instructions.
When writing to RTCNT, RTCSR, or RTCOR, place B'10100101 in the upper byte and the
write data in the lower byte. When writing to RFCR, place B'101001 in the top 6 bits and the
write data in the remaining bits, as shown in figure 12.4.
2. Reading from RFCR, RTCSR, RTCNT, and RTCOR
When reading from RFCR, RTCSR, RTCNT, and RTCOR, carry out reads with 16-bit width.
0 is read out from undefined bit sections.
15
RTCSR, RTCNT,
RTCOR
1
8
0
1
0
0
15
RFCR
1
1
0
1
0
7
Write data
10 9
0
1
0
0
1
0
Write data
Figure 12.4 Writing to RFCR, RTCSR, RTCNT, and RTCOR
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Section 12 Bus State Controller (BSC)
12.3
BSC Operation
12.3.1
Endian/Access Size and Data Alignment
This LSI supports both big endian, in which the 0 address is the most significant byte in the byte
data, and little endian, in which the 0 address is the least significant byte. This switchover is
designated by an external pin (MD5 pin) at the time of a power-on reset. After a power-on reset,
big endian is engaged when MD5 is low; little endian is engaged when MD5 is high.
Three data bus widths are available for ordinary memory (byte, word, longword) and two data bus
widths (word and long word) for synchronous DRAM. For the PCMCIA interface, choose from
byte and word. This means data alignment is done by matching the device's data width and endian.
The access unit must also be matched to the device's bus width. This also means that when
longword data is read from a byte-width device, the read operation must happen 4 times. In this
LSI, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 12.6 to 12.11 show the relationship between endian, device data width, and access unit.
Table 12.6 32-Bit External Device/Big Endian Access and Data Alignment
Data Bus
Strobe Signals
Operation
D31 to
D24
D23 to
D16
D15 to
D8
D7 to
D0
WE3,
WE3
DQMUU
Byte access
at 0
Data
7 to 0
—
—
—
Assert
Byte access
at 1
—
Data
7 to 0
—
—
Byte access
at 2
—
—
Data
7 to 0
—
Byte access
at 3
—
—
—
Data
7 to 0
Word access Data
at 0
15 to 8
Data
7 to 0
—
—
Word access —
at 2
—
Data
15 to 8
Data
7 to 0
Longword
access at 0
Data
23 to 16
Data
15 to 8
Data
7 to 0
Data
31 to 24
Rev. 5.00 Dec 12, 2005 page 316 of 1034
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WE2,
WE2
DQMUL
WE1,
WE1
DQMLU
WE0,
WE0
DQMLL
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Section 12 Bus State Controller (BSC)
Table 12.7 16-Bit External Device/Big Endian Access and Data Alignment
Data Bus
Strobe Signals
WE3,
WE3
DQMUU
WE2,
WE2
DQMUL
WE1,
WE1
DQMLU
WE0,
WE0
DQMLL
Assert
—
Operation
D31 to D23 to D15 to
D24
D16
D8
D7 to
D0
Byte access at 0
—
—
Data
7 to 0
—
Byte access at 1
—
—
—
Data
7 to 0
Byte access at 2
—
—
Data
7 to 0
—
Byte access at 3
—
—
—
Data
7 to 0
Word access at 0
—
—
Data
15 to 8
Data
7 to 0
Assert
Assert
Word access at 2
—
—
Data
15 to 8
Data
7 to 0
Assert
Assert
Longword 1st
—
access
time at 0
at 0
2nd
—
time at 2
—
Data
Data
31 to 24 23 to 16
Assert
Assert
—
Data
15 to 8
Assert
Assert
Data
7 to 0
Assert
Assert
—
Assert
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Section 12 Bus State Controller (BSC)
Table 12.8 8-Bit External Device/Big Endian Access and Data Alignment
Data Bus
Strobe Signals
WE3,
WE2,
WE3
WE2
DQMUU DQMUL
WE1,
WE0,
WE1
WE0
DQMLU DQMLL
Operation
D31 to D23 to D15 to D7 to
D24
D16
D8
D0
Byte access at 0
—
—
—
Data
7 to 0
Assert
Byte access at 1
—
—
—
Data
7 to 0
Assert
Byte access at 2
—
—
—
Data
7 to 0
Assert
Byte access at 3
—
—
—
Data
7 to 0
Assert
Word
1st time —
access at 0 at 0
—
—
Data
15 to 8
Assert
2nd time —
at 1
—
—
Data
7 to 0
Assert
Word
1st time —
access at 2 at 2
—
—
Data
15 to 8
Assert
2nd time —
at 3
—
—
Data
7 to 0
Assert
Longword 1st time —
access at 0 at 0
—
—
Data
31 to 24
Assert
2nd time —
at 1
—
—
Data
23 to 16
Assert
3rd time —
at 2
—
—
Data
15 to 8
Assert
4th time —
at 3
—
—
Data
7 to 0
Assert
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Section 12 Bus State Controller (BSC)
Table 12.9 32-Bit External Device/Little Endian Access and Data Alignment
Data Bus
Strobe Signals
WE3,
WE3
DQMUU
WE2,
WE2
DQMUL
D31 to
D24
D23 to
D16
D15 to
D8
D7 to
D0
Byte access
at 0
—
—
—
Data
7 to 0
Byte access
at 1
—
—
Data
7 to 0
—
Byte access
at 2
—
Data
7 to 0
—
—
Byte access
at 3
Data
7 to 0
—
—
—
Word access —
at 0
—
Data
15 to 8
Data
7 to 0
Word access Data
at 2
15 to 8
Data
7 to 0
—
—
Assert
Assert
Longword
access at 0
Data
23 to 16
Data
15 to 8
Data
7 to 0
Assert
Assert
Operation
Data
31 to 24
WE1,
WE1
DQMLU
WE0,
WE0
DQMLL
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert
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Section 12 Bus State Controller (BSC)
Table 12.10 16-Bit External Device/Little Endian Access and Data Alignment
Data Bus
Strobe Signals
WE3,
WE3
DQMUU
WE2,
WE2
DQMUL
WE1,
WE1
DQMLU
WE0,
WE0
DQMLL
Operation
D31 to D23 to D15 to
D24
D16
D8
D7 to
D0
Byte access at 0
—
—
—
Data
7 to 0
Byte access at 1
—
—
Data
7 to 0
—
Byte access at 2
—
—
—
Data
7 to 0
Byte access at 3
—
—
Data
7 to 0
—
Assert
Word access at 0
—
—
Data
15 to 8
Data
7 to 0
Assert
Assert
Word access at 2
—
—
Data
15 to 8
Data
7 to 0
Assert
Assert
Longword 1st
—
access at time at 0
0
2nd
—
time at 2
—
Data
15 to 8
Data
7 to 0
Assert
Assert
—
Data
Data
31 to 24 23 to 16
Assert
Assert
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Assert
Assert
Assert
Section 12 Bus State Controller (BSC)
Table 12.11 8-Bit External Device/Little Endian Access and Data Alignment
Data Bus
Strobe Signals
WE3,
WE2,
WE1,
WE0,
WE3
WE2
WE1
WE0
DQMUU DQMUL DQMLU DQMLL
Operation
D31 to D23 to D15 to D7 to
D24
D16
D8
D0
Byte access at 0
—
—
—
Data
7 to 0
Assert
Byte access at 1
—
—
—
Data
7 to 0
Assert
Byte access at 2
—
—
—
Data
7 to 0
Assert
Byte access at 3
—
—
—
Data
7 to 0
Assert
Word
1st time —
access at 0 at 0
—
—
Data
7 to 0
Assert
2nd time —
at 1
—
—
Data
15 to 8
Assert
Word
1st time —
access at 2 at 2
—
—
Data
7 to 0
Assert
2nd time —
at 3
—
—
Data
15 to 8
Assert
Longword 1st time —
access at 0 at 0
—
—
Data
7 to 0
Assert
2nd time —
at 1
—
—
Data
15 to 8
Assert
3rd time —
at 2
—
—
Data
23 to 16
Assert
4th time —
at 3
—
—
Data
31 to 24
Assert
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Section 12 Bus State Controller (BSC)
12.3.2
Description of Areas
Area 0: Area 0 physical addresses A28 to A26 are 0'0. Addresses A31 to A29 are ignored and the
address range is H'00000000 + H'20000000 × n – H'03FFFFFF + H'20000000 × n (n = 0 to 6 and
n = 1 to 6 are the shadow spaces).
Ordinary memories such as SRAM, ROM, and burst ROM can be connected to this space. Byte,
word, or longword can be selected as the bus width using external pins MD3 and MD4. When the
area 0 space is accessed, a CS0 signal is asserted. An RD signal that can be used as OE and the
WE0 to WE3 signals for write control are also asserted. The number of bus cycles is selected
between 0 and 10 wait cycles using the A0W2 to A0W0 bits of WCR2. In addition, any number of
waits can be inserted in each bus cycle by means of the external wait pin (WAIT).
When the burst function is used, the bus cycle pitch of the burst cycle is determined within a range
of 2 to 10 according to the number of waits.
Area 1: Area 1 physical addresses A28 to A26 are 001. Addresses A31 to A29 are ignored and the
address range is H'04000000 + H'20000000 × n – H'07FFFFFF + H'20000000 × n (n = 0 to 6 and
n = 1 to 6 are the shadow spaces).
Area 1 is the area specifically for the internal peripheral modules. The external memories cannot
be connected.
Control registers of peripheral modules shown below are mapped to this area 1. Their addresses
are physical address, to which logical addresses can be mapped with the MMU enabled:
DMAC, PORT, SCIF, ADC, DAC, LCDC, PCC, SIOF, AFEIF, USBF, USBH, INTC
(except INTEVT, IPRA, IPRB)
Those registers must be set not to be cached.
Area 2: Area 2 physical addresses A28 to A26 are 010. Addresses A31 to A29 are ignored and the
address range is H'08000000 + H'20000000 × n – H'0BFFFFFF + H'20000000 × n (n = 0 to 6 and
n = 1 to 6 are the shadow spaces).
Ordinary memories like SRAM and ROM, as well as synchronous DRAM, can be connected to
this space. Byte, word, or longword can be selected as the bus width using the A2SZ1 to A2SZ0
bits of BCR2 for ordinary memory.
When the area 2 space is accessed, a CS2 signal is asserted. When ordinary memories are
connected, an RD signal that can be used as OE and the WE0 to WE3 signals for write control are
also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the
A2W1 to A2W0 bits of WCR2. In addition, any number of waits can be inserted in each bus cycle
by means of the external wait pin (WAIT) only when the ordinary memories are connected.
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Section 12 Bus State Controller (BSC)
When synchronous DRAM is connected, the RAS3 signal, CAS signal, RD/WR signal, and byte
controls DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed.
Control of RAS3, CAS, data timing, and address multiplexing is set with MCR.
Area 3: Area 3 physical addresses A28 to A26 are 011. Addresses A31 to A29 are ignored and the
address range is H'0C000000 + H'20000000 × n to H'0FFFFFFF + H'20000000 × n (n = 0 to 6 and
n = 1 to 6 are the shadow spaces).
Ordinary memories like SRAM and ROM, as well as synchronous DRAM, can be connected to
this space. Byte, word or longword can be selected as the bus width using the A3SZ1 to A3SZ0
bits of BCR2 for ordinary memory. When area 3 space is accessed, CS3 is asserted.
When ordinary memories are connected, an RD signal that can be used as OE and the WE0 to
WE3 signals for write control are asserted and the number of bus cycles is selected between 0 and
3 wait cycles using the A3W1 to A3W0 bits of WCR2. In addition, any number of waits can be
inserted in each bus cycle by means of the external wait pin (WAIT).only when the ordinary
memories are connected.
When synchronous DRAM is connected, the RAS3 signal, CAS signal, RD/WR signal, and byte
controls DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed.
Area 4: Area 4 physical addresses A28 to A26 are 1'0. AddressesA31 to A29 are ignored and the
address range is H'10000000 + H'20000000 × n – H'13FFFFFF + H'20000000 × n (n = 0 to 6 and
n = 1 to 6 are the shadow spaces).
Only ordinary memories like SRAM and ROM can be connected to this space. Byte, word, or
longword can be selected as the bus width using the A4SZ1 to A4SZ0 bits of BCR2. When the
area 4 space is accessed, a CS4 signal is asserted. An RD signal that can be used as OE and the
WE0 to WE3 signals for write control are also asserted. The number of bus cycles is selected
between 0 and 10 wait cycles using the A4W2 to A4W0 bits of WCR2. In addition, any number
of waits can be inserted in each bus cycle by means of the external wait pin (WAIT).
Area 5: Area 5 physical addresses A28 to A26 are 101. Addresses A31 to A29 are ignored and the
address range is the 64 Mbytes at H'14000000 + H'20000000 × n to H'17FFFFFF + H'20000000 ×
n (n = 0 to 6 and n = 1 to 6 are the shadow spaces).
Ordinary memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be
connected to this space. When the PCMCIA interface is used, the IC memory card interface
address range-comprises the 32 Mbytes at H'14000000 + H'20000000 × n to H'15FFFFFF +
H'20000000 × n (n = 0 to 6 and n = 1 to 6 are the shadow spaces), and the I/O card interface
address range-comprises the 32 Mbytes at H'16000000 + H'20000000 × n to H'17FFFFFF +
H'20000000 × n (n = 0 to 6 and n = 1 to 6 are the shadow spaces).
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Section 12 Bus State Controller (BSC)
For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width
using the A5SZ1 to A5SZ0 bits of BCR2. For the PCMCIA interface, byte, and word can be
selected as the bus width using the A5SZ1 to A5SZ0 bits of BCR2.
When the area 5 space is accessed and ordinary memory is connected, a CS5 signal is asserted. An
RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted.
When the PCMCIA interface is used, the CE1A signal, CE2A signal, RD signal as OE signal, and
WE, ICIORD, ICIOWR signal are asserted.
The number of bus cycles is selected between 0 and 10 wait cycles using the A5W2 to A5W0 bits
of WCR2. With the PCMCIA interface, from 0 to 38 wait cycles can be selected using the A5W2
to A5W0 bits of WCR2 and the A5W3 bit of PCR. In addition, any number of waits can be
inserted in each bus cycle by means of the external wait pin (WAIT).
When a burst function is used, the bus cycle pitch of the burst cycle is determined within a range
of 2 to 11 (2 to 39 for the PCMCIA interface) according to the number of waits. The setup and
hold times of address/CS5 for the read/write strobe signal can be set in the range 0.5 to 7.5 cycles
using A5TED2 to A5TED0 and A5TEH2 to A5TEH0 bits of the PCR register. (Single-cycle units)
Area 6: Area 6 physical addresses A28 to A26 are 110. Address A31 to A29 are ignored and the
address range is the 64 Mbytes at H'18000000 + H'20000000 × n to H'1BFFFFFF + H'20000000 ×
n (n = 0 to 6 and n = 1 to 6 are the shadow spaces).
Ordinary memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be
connected to this space. When the PCMCIA interface is used, the IC memory card interface
address range is 32 Mbytes at H'18000000 + H'20000000 × n to H'19FFFFFF + H'2000'000 × n
and 'he I/O card interface address range is 32 Mbytes at H'1A000000 + H'20000000 × n to
H'1BFFFFFF + H'20000000 × n (n = 0 to 6 and n = 1 to 6 are the shadow spaces).
For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width
using the A6SZ1 to A6SZ0 bits of BCR2. For the PCMCIA interface, byte, and word can be
selected as the bus width using the A6SZ1 to A6SZ0 bits of BCR2.
When the area 6 space is accessed and ordinary memory is connected, a CS6 signal is asserted. An
RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted.
When the PCMCIA interface is used, the CI1B signal, CE2B signal, RD signal as OE signal, and
WE, ICIORD, and ICIOWR signals are asserted.
The number of bus cycles is selected between 0 to 10 wait cycles using the A6W2 to A6W0 bits of
WCR2. With the PCMCIA interface, from 0 to 38 wait cycles can be selected using the A6W2 to
A6W0 bits of WCR2 and the A6W3 bit of PCR. In addition, any number of waits can be inserted
in each bus cycle by means of the external wait pin (WAIT). The bus cycle pitch of the burst cycle
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Section 12 Bus State Controller (BSC)
is determined within a range of 2 to 11 (2 to 39 for the PCMCIA interface) according to the
number of waits. The setup and hold times of address/CS6 for the read/write strobe signals can be
set in the range 0.5 to 7.5 cycles using A6TED2 to A6TED0 and A6TEH2 to A6TEH0 bits of the
PCR register. (Single-cycle units)
12.3.3
Basic Interface
Basic Timing: The basic interface of this LSI uses strobe signal output in consideration of the fact
that mainly static RAM will be directly connected. Figure 12.5 shows the basic timing of normal
space accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for
one cycle to indicate the start of a bus cycle. The CSn signal is negated on the T2 clock falling
edge to secure the negation period. Therefore, in case of access at minimum pitch, there is a halfcycle negation period.
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WE
signal for the byte to be written is asserted. For details, see section 12.3.1, Endian/Access Size and
Data Alignment.
Read/write for cache fill or write-back follows the set bus width and transfers a total of 16 bytes
continuously. The bus is not released during this transfer. For cache misses that occur during byte
or word operand accesses or branching to odd word boundaries, the fill is always performed by
longword accesses on the chip-external interface. Write-through-area write access and noncacheable read/write access are based on the actual address size.
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Section 12 Bus State Controller (BSC)
T1
T2
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D31 to D0
WEn
Write
D31 to D0
BS
Figure 12.5 Basic Timing of Basic Interface
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Section 12 Bus State Controller (BSC)
Figures 12.6, 12.7, and 12.8 show examples of connection to 32, 16, and 8-bit data-width static
RAM, respectively.
128k × 8 bit
SRAM
SH7727
A18
··
··
··
··
··
··
··
··
··
··
··
··
A2
CSn
RD
D31
D24
WE3
D23
D16
WE2
D15
··
··
··
··
··
··
D0
WE0
A16
··
··
A0
CS
OE
I/O7
··
··
I/O0
WE
··
··
··
··
D8
WE1
D7
··
··
··
··
··
··
A16
··
··
A0
CS
OE
I/O7
··
··
I/O0
WE
A16
··
··
A0
CS
OE
I/O7
··
··
I/O0
WE
··
··
··
··
A16
··
··
A0
CS
OE
I/O7
··
··
I/O0
WE
Figure 12.6 Example of 32-Bit Data-Width Static RAM Connection
Rev. 5.00 Dec 12, 2005 page 327 of 1034
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Section 12 Bus State Controller (BSC)
128k × 8 bit
SRAM
SH7727
A17
··
··
··
··
··
··
··
··
··
··
··
··
A1
CSn
RD
D15
D8
WE1
D7
D0
WE0
··
··
A16
··
··
A0
CS
OE
I/O7
··
··
I/O0
WE
··
··
··
··
A16
··
··
A0
CS
OE
I/O7
··
··
I/O0
WE
Figure 12.7 Example of 16-Bit Data-Width Static RAM Connection
128k × 8 bit
SRAM
SH7727
A16
··
··
··
··
··
··
··
··
··
··
··
··
A0
CSn
RD
D7
D0
WE0
A16
··
··
A0
CS
OE
I/O7
··
··
I/O0
WE
Figure 12.8 Example of 8-Bit Data-Width Static RAM Connection
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Section 12 Bus State Controller (BSC)
Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2
settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a
software wait is inserted in accordance with that specification. For details, see section 12.2.4, Wait
State Control Register 2 (WCR2).
The specified number of Tw cycles are inserted as wait cycles using the basic interface wait timing
shown in figure 12.9.
T1
Tw
T2
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D31 to D0
WEn
Write
D31 to D0
BS
Figure 12.9 Basic Interface Wait Timing (Software Wait Only)
When software wait insertion is specified by WCR2, the external wait input WAIT signal is also
sampled. TO input low level signal to WAIT, set the WAITSEL bit of the WCR1 register to 1.
WAIT pin sampling is shown in figure 12.10. A 2-cycle wait is specified as a software wait.
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Section 12 Bus State Controller (BSC)
Sampling is performed at the transition from the Tw state to the T2 state; therefore, if the WAIT
signal has no effect if asserted in the T1 cycle or the first Tw cycle.
The WAIT signal is sampled at the falling edge of the clock. If the setup time and hold times with
respect to the falling edge of the clock are not satisfied, the value sampled at the next falling edge
is used..
However, the WAIT signal is ignored in the following three cases:
• When writing to an external address area using DMA 16-byte transfer in dual address mode
• When transferring data from a DACK-equipped external device to an external address area
using DMA 16-byte transfer in dual address mode
• During cache write-back access
Wait states inserted
by WAIT signal
T1
Tw
Tw
Tw
T2
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D31 to D0
WEn
Write
D31 to D0
WAIT
BS
Figure 12.10 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal
WAITSEL = 1)
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Section 12 Bus State Controller (BSC)
12.3.4
Synchronous DRAM Interface
Synchronous DRAM Direct Connection: Since synchronous DRAM can be selected by the CS
signal, physical space areas 2 and 3 can be connected using RAS and other control signals in
common. If the memory type bits (DRAMTP2 to DRAMTP0) in BCR1 are set to 010, area 2 is
ordinary memory space and area 3 is synchronous DRAM space; if set to 011, areas 2 and 3 are
both synchronous DRAM space.
With this LSI, burst length 1 burst read/single write mode is supported as the synchronous DRAM
operating mode. A data bus width of 16 or 32 bits can be selected. A 16-bit burst transfer is
performed in a cache fill/write-back cycle, and only one access is performed in a write-through
area write or a non-cacheable area read/write.
The control signals for direct connection of synchronous DRAM are RAS3, CAS, RD/WR, CS2 or
CS3, DQMUU, DQMUL, DQMLU, DQMLL, and CKE. All the signals other than CS2 and CS3
are common to all areas, and signals other than CKE are valid and fetched to the synchronous
DRAM only when CS2 or CS3 is asserted. Synchronous DRAM can therefore be connected in
parallel to a number of areas. CKE is negated (low) only when self-refreshing is performed, and is
always asserted (high) at other times.
Commands for synchronous DRAM are specified by RAS3, CAS, RD/WR, and special address
signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks
(PALL), row address strobe bank active (ACTV), read (READ), read with precharge (READA),
write (WRIT), write with precharge (WRITA), and mode register write (MRS).
Byte specification is performed by DQMUU, DQMUL, DQMLU, and DQMLL. A read/write is
performed for the byte for which the corresponding DQM is low. In big-endian mode, DQMUU
specifies an access to address 4n, and DQMLL specifies an access to address 4n + 3. In littleendian mode, DQMUU specifies an access to address 4n + 3, and DQMLL specifies an access to
address 4n.
Figures 12.11 and 12.12 show examples of the connection of two 1M × 16-bit × 4-bank
synchronous DRAMs and one 1M × 16-bit × 4-bank synchronous DRAM, respectively.
CKIO and CKIO2 are the clock signals that can be input to the synchronous DRAM. When using
multiple synchronous DRAMs, use either CKIO or CKIO2, but not both. Also to prevent big
signal delays due to overloading, design the board so that the load capacity is 50 pF or less.
Aim to ensure wiring lengths are equal and avoid chaining the clock wiring to the synchronous
DRAMs.
Rev. 5.00 Dec 12, 2005 page 331 of 1034
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Section 12 Bus State Controller (BSC)
CKIO has higher drive capacity than CKIO2. CKIO is suitable for driving heavy load, while
CKIO2 offers higher resistance to EMI noise and reflection. However, as the degree of these
characteristics vary depending on applications, their usage is not specified.
64M synchronous DRAM
(1M × 16-bit × 4-bank)
SH7727
A13
A12
A11
A15
A14
A13
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
A2
CKIO, CKIO2
CKE
CSn
RAS3
CAS
RD/WR
D31
A0
CLK
CKE
CS
RAS
CAS
WE
DQ15
D0
DQMLU
DQMLL
·
·
·
·
DQ0
DQMU
DQML
D16
DQMUU
DQMUL
D15
·
·
·
·
·
·
·
·
·
·
·
·
A13
A12
A11
·
·
·
·
·
·
·
·
·
·
·
·
A0
CLK
CKE
CS
RAS
CAS
WE
DQ15
·
·
·
·
DQ0
DQMU
DQML
Figure 12.11 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width)
Rev. 5.00 Dec 12, 2005 page 332 of 1034
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Section 12 Bus State Controller (BSC)
64M synchronous DRAM
(1M × 16-bit × 4-bank)
SH7727
A13
A12
A11
A14
A13
A12
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
A1
CKIO, CKIO2
CKE
CSn
RAS3
CAS
RD/WR
D15
·
·
·
D0
DQMLU
DQMLL
·
·
·
A0
CLK
CKE
CS
RAS
CAS
WE
DQ15
·
·
·
DQ0
DQMU
DQML
Figure 12.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width)
Address Multiplexing: Synchronous DRAM can be connected without external multiplexing
circuitry in accordance with the address multiplex specification bits AMX3 to AMX0 in MCR.
Table 12.12 shows the relationship between the address multiplex specification bits and the bits
output at the address pins. Table 12.13 shows the relationship between LSI address pins and
synchronous DRAM address pins.
A25 to A17 and A0 are not multiplexed; the original values are always output at these pins.
When A0, the LSB of the synchronous DRAM address, is connected to this LSI, it performs
longword address specification. Connection should therefore be made in the following order: with
a 32-bit bus width, connect pin A0 of the synchronous DRAM to pin A2 of this LSI, then connect
pin A1 to pin A3; with a 16-bit bus width, connect pin A0 of the synchronous DRAM to pin A1 of
this LSI, then connect pin A1 and pin A2.
Rev. 5.00 Dec 12, 2005 page 333 of 1034
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Section 12 Bus State Controller (BSC)
Table 12.12
Relationship between Synchronous DRAM type, bus width and AMX
128 Mbits 1M × 32-bit × 4-bank*
2M × 16-bit × 4-bank*
64 Mbits
AMX0
32 bits 256 Mbits 4M × 16-bit × 4-bank*
AMX1
Memory Type
AMX2
Bus
Width
External Address Pin
AMX3
Setting
1
1
0
1
0
0
1
1
0
0
0
1
Output Timing
A1 to A8
A9
A10 A11 A12 A13 A14 A15 A16
A10 A11 L/H
Column address
A1–A8
A9
Row address
A10–A17
A18 A19 A20 A21 A22 A23 A24 A25
Column address
A1–A8
A9
Row address
A9–A16
A17 A18 A19 A20 A21 A22 A23 A16
Column address
A1–A8
A9
Row address
A10–A17
A18 A19 A20 A21 A22 A23 A24 A16
A1–A8
A9
A10 A11 L/H
A10 A11 L/H
A13 A23 A24 A25
A13 A22 A23 A16
A13 A23 A24 A16
4M × 8-bit × 4-bank*
0
1
1
0
Column address
Row address
A11–A18
A19 A20 A21 A22 A23 A24 A25 A16
1M × 16-bit × 4-bank*
0
1
0
0
Column address
A1–A8
A9
Row address
A9–A16
A17 A18 A19 A20 A21 A22 A23 A16
2M × 8-bit × 4-bank*
0
1
0
1
Column address
A1–A8
A9
Row address
A10–A17
A18 A19 A20 A21 A22 A23 A24 A16
4M × 4-bit × 4-bank*
0
1
1
0
Column address
A1–A8
A9
Row address
A11–A18
A19 A20 A21 A22 A23 A24 A25 A16
512K × 32-bit × 4-bank
0
1
1
1
Column address
A1–A8
A9
Row address
A9–A16
A17 A18 A19 A20 A21 A22 A23 A16
Column address
A1–A8
A9
Row address
A11–A18
A19 A20 A21 A22 A23 A24 A25 A16
Column address
A1–A8
A9
Row address
A10–A17
A18 A19 A20 A21 A22 A23 A24 A16
Column address
A1–A8
A9
Row address
A11–A18
A19 A20 A21 A22 A23 A24 A25 A16
A1–A8
A9
16 bits 512 Mbits 8M × 16-bit × 4-bank*
256 Mbits 4M × 16-bit × 4-bank
8M × 8-bit × 4-bank*
1
1
1
1
1
1
1
0
1
0
1
0
A10 A11 L/H
A10 A11 L/H
A10 A11 L/H
A10 A11 L/H
A10 A11 L/H
A10 L/H
A10 L/H
A10 L/H
A13 A24 A25 A16
A13 A22 A23 A16
A13 A23 A24 A16
A13 A24 A25 A16
A21 A22 A15 A16
A12 A13 A24 A25 A16
A12 A22 A23 A24 A16
A12 A23 A24 A25 A16
128 Mbits 2M × 16-bit × 4-bank
0
1
0
1
Column address
Row address
A10–A17
A18 A19 A20 A21 A22 A23 A24 A16
1M × 16-bit × 4-bank
0
1
0
0
Column address
A1–A8
A9
Row address
A9–A16
A17 A18 A19 A20 A21 A22 A23 A16
2M × 8-bit × 4-bank
0
1
0
1
Column address
A1–A8
A9
Row address
A10–A17
A18 A19 A20 A21 A22 A23 A24 A16
64 Mbits
Notes: * L/H is a bit used to specify commands. It is fixed to L or H by the access mode.
: Bank address
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A10 L/H
A10 L/H
A10 L/H
A12 A22 A23 A24 A16
A12 A21 A22 A15 A16
A12 A22 A23 A15 A16
Section 12 Bus State Controller (BSC)
Table 12.13 Relationship between LSI Address Pins and Synchronous DRAM Address Pins
SH7727
Address Pin
RAS Cycle
CAS Cycle
SDRAM
Address Pin
Function
A16
A24
A16
A14
Address
A15
A23
A23
A13
BANK select bank address
A14
A22
A22
A12
A13
A21
A13
A11
Address
A12
A20
L/H
A10
Address precharge
specification
A11
A19
A11
A9
Address
A10
A18
A10
A8
A9
A17
A9
A7
A8
A16
A8
A6
A7
A15
A7
A5
A6
A14
A6
A4
A5
A13
A5
A3
A4
A12
A4
A2
A3
A11
A3
A1
A2
A10
A2
A0
A1
A9
A1
Unused
A0
A0
A0
Unused
Burst Read: In the example in figure 12.13 it is assumed that four 2M × 8-bit synchronous
DRAMs are connected and a 32-bit data width is used, and the burst length is 1. Following the Tr
cycle in which ACTV command output is performed, a READ command is issued in the Tc1, Tc2,
and Tc3 cycles, and a READA command in the Tc4 cycle, and the read data is accepted on the
rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is
used to wait for completion of auto-precharge based on the READA command inside the
synchronous DRAM; no new access command can be issued to the same bank during this cycle,
but access to synchronous DRAM for another area is possible. In this LSI, the number of Tpc
cycles is determined by the TPC bit specification in MCR, and commands cannot be issued for the
same synchronous DRAM during this interval.
To connect low-speed synchronous DRAM, the cycle can be extended by setting WCR2 and MCR
bits. The number of cycles from the ACTV command output cycle, Tr, to the READ command
output cycle, Tc1, can be specified by the RCD bit in MCR, with a values of 0 to 3 specifying 1 to
4 cycles, respectively. In case of 2 or more cycles, a Trw cycle, in which an NOP command is
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Section 12 Bus State Controller (BSC)
issued for the synchronous DRAM, is inserted between the Tr cycle and the Tc cycle. The number
of cycles from READ and READA command output cycles Tc1 to Tc4 to the first read data latch
cycle, Td1, can be specified as 1 to 3 cycles independently for areas 2 and 3 by means of A2W1
and A2W0 or A3W1 and A3W0 in WCR2. This number of cycles corresponds to the number of
synchronous DRAM CAS latency cycles.
Tr
Tc1
Tc2/Td1
Tc3/Td2
Tc4/Td3
Td4
Tpc
CKIO,
CKIO2
A25 to A16,
A13
A12
A15, A14,
A11 to A0
CS2 or CS3
RAS3
CAS
RD/WR
DQMxx
D31 to D0
BS
Figure 12.13 Basic Timing for Synchronous DRAM Burst Read
Figure 12.14 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10,
and TPC is set to 1.
The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal access space, is
asserted in each of cycles Td1 to Td4 in a synchronous DRAM cycle. When a burst read is
performed, the address is updated each time CAS is asserted. As the unit of burst transfer is 16
bytes, address updating is performed for A3 and A2 only. The order of access is as follows: in a
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Section 12 Bus State Controller (BSC)
fill operation in the event of a cache miss, the missed data is read first, then 16-byte boundary data
including the missed data is read in wraparound mode.
Tr
Trw
Tc1
Tc2
Tc3/Td1 Tc4/Td2
Td3
Td4
Tpc
CKIO,
CKIO2
A25 to A16,
A13
A12
A15, A14,
A11 to A0
CS2 or CS3
RAS3
CAS
RD/WR
DQMxx
D31 to D0
BS
Figure 12.14 Synchronous DRAM Burst Read Wait Specification Timing
Single Read: Figure 12.15 shows the timing when a single address read is performed. As the burst
length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is
output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is
accessed.
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Section 12 Bus State Controller (BSC)
Tr
Tc1
Td1
Tpc
CKIO,
CKIO2
A25 to A16,
A13
A12
A15, A14,
A11 to A0
CS2 or CS3
RAS3
CAS
RD/WR
DQMxx
D31 to D0
BS
Figure 12.15 Basic Timing for Synchronous DRAM Single Read
Burst Write: The timing chart for a burst write is shown in figure 12.16. In this LSI, a burst write
occurs only in the event of cache write-back. In a burst write operation, following the Tr cycle in
which ACTV command output is performed, a WRIT command is issued in the Tc1, Tc2, and Tc3
cycles, and a WRITA command that performs auto-precharge is issued in the Tc4 cycle. In the
write cycle, the write data is output at the same time as the write command. In case of the write
with auto-precharge command, precharging of the relevant bank is performed in the synchronous
DRAM after completion of the write command, and therefore no command can be issued for the
same bank until precharging is completed. Consequently, in addition to the precharge wait cycle,
Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started
following the write command. Issuance of a new command for the same bank is postponed during
this interval. The number of Trwl cycles can be specified by the TRWL bit in MCR.
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Section 12 Bus State Controller (BSC)
Tr
Tc1
Tc2
Tc3
Tc4
(Tpc)
(Tpc)
CKIO,
CKIO2
Address
upper bits
A12, A11,
A10 or A9
Address
lower bits
CSn
RD/WR
RAS3
CAS
DQMxx
D31 to D0
(read)
BS
Figure 12.16 Basic Timing for Synchronous DRAM Burst Write
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Section 12 Bus State Controller (BSC)
Single Write: The basic timing chart for write access is shown in figure 12.17. In a single write
operation, following the Tr cycle in which ACTV command output is performed, a WRITA
command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write
data is output at the same time as the write command. In case of the write with auto-precharge
command, precharging of the relevant bank is performed in the synchronous DRAM after
completion of the write command, and therefore no command can be issued for the same bank
until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in
a read access, cycle Trwl is also added as a wait interval until precharging is started following the
write command. Issuance of a new command for the same bank is postponed during this interval.
The number of Trwl cycles can be specified by the TRWL bit in MCR.
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Section 12 Bus State Controller (BSC)
Tr
Tc1
(Trwl)
(Tpc)
CKIO,
CKIO2
Address
upper bits
A12 or A10
Address
lower bits
CSn
RD/WR
RAS3
CAS
DQMxx
D31 to D0
BS
CKE
Figure 12.17 Basic Timing for Synchronous DRAM Single Write
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Section 12 Bus State Controller (BSC)
Refreshing: The bus state controller is provided with a function for controlling synchronous
DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting
the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh
mode, in which the power consumption for data retain is low, can be activated by setting both the
RMODE bit and the RFSH bit to 1.
1. Auto-Refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0
in RTCSR, and the value set in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should be
set so as to satisfy the refresh interval stipulation for the synchronous DRAM used. First make the
settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2 to
CKS0 setting. When the clock is selected by CKS2 to CKS0, RTCNT starts counting up from the
value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the
two values are the same, a refresh request is generated and an auto-refresh is performed. At the
same time, RTCNT is cleared to zero and the count-up is restarted. Figure 12.18 shows the autorefresh cycle timing.
All-bank precharging is performed in the Tp cycle, then an REF command is issued in the TRr
cycle following the interval specified by the TPC bits in MCR. After the TRr cycle, new command
output cannot be performed for the duration of the number of cycles specified by the TRAS bits in
MCR plus the number of cycles specified by the TPC bits in MCR. The TRAS and TPC bits must
be set so as to satisfy the synchronous DRAM refresh cycle time stipulation (active/active
command delay time).
Auto-refreshing is performed in normal operation, in sleep mode, and in case of a manual reset.
RTCNT cleared to 0 when
RTCNT = RTCOR
RTCOR value
RTCNT
Time
H'00000000
RTCSR.CKS(2−0)
= 000
≠ 000
CMF
CMF flag cleared by start of
refresh cycle
External bus
Auto-refresh cycle
Figure 12.18 Auto-Refresh Operation
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Section 12 Bus State Controller (BSC)
Tp
TRr
TRrw
TRrw
(Tpc)
CKIO,
CKIO2
CKE
CSn
RAS3
CAS
RD/WR
Figure 12.19 Synchronous DRAM Auto-Refresh Timing
2. Self-Refreshing
Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are
generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE
bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low.
Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is
cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command
issuance is disabled for the number of cycles specified by the TPC bits in MCR. Self-refresh
timing is shown in figure 12.20. Settings must be made so that self-refresh clearing and data
retention are performed correctly, and auto-refreshing is performed at the correct intervals. When
self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby
mode other than through a power-on reset, auto-refreshing is restarted if RFSH is set to 1 and
RMODE is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of selfRev. 5.00 Dec 12, 2005 page 343 of 1034
REJ09B0254-0500
Section 12 Bus State Controller (BSC)
refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration
when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value
will enable refreshing to be started immediately.
After self-refreshing has been set, the self-refresh state continues even if the chip standby state is
entered using this LSI's standby function, and is maintained even after recovery from standby
mode other than through a power-on reset. In case of a power-on reset, the bus state controller's
registers are initialized, and therefore the self-refresh state is cleared.
Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in case of a
manual reset. In addition, halt USB and LCDC before entering standby mode.
When the synchronous DRAM is used, self-refreshing is initiated in the following procedure.
1. Clear the refresh control bit to 0.
2. Write H'00 to RTCNT
3. Set the refresh control bit and refresh mode bit to 1.
Tp
TRs1
(TRs2)
(TRs2)
TRs3
CKIO, CKIO2
CKE
CSn
RAS3
CAS
RD/WR
Figure 12.20 Synchronous DRAM Self-Refresh Timing
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REJ09B0254-0500
(Tpc)
(Tpc)
Section 12 Bus State Controller (BSC)
Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed
after powering on. To perform synchronous DRAM initialization correctly, the bus state controller
registers must first be set, followed by a write to the synchronous DRAM mode register. In
synchronous DRAM mode register setting, the address signal value at that time is latched by a
combination of the RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state
controller provides for value X to be written to the synchronous DRAM mode register by
performing a write to address H'FFFFD000 + X for area 2 synchronous DRAM, and to address
H'FFFFE000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the
mode write is performed as a byte-size access. To set burst read/single write, CAS latency 1 to 3,
wrap type = sequential, and burst length 1 supported by this LSI, arbitrary data is written in a bytesize access to the following addresses.
With 32-bit bus width:
CAS latency 1
CAS latency 2
CAS latency 3
Area 2
FFFFD840
FFFFD880
FFFFD8C0
Area 3
FFFFE840
FFFFE880
FFFFE8C0
Area 2
FFFFD420
FFFFD440
FFFFD460
Area 3
FFFFE420
FFFFE440
FFFFE460
With 16-bit bus width:
CAS latency 1
CAS latency 2
CAS latency 3
Mode register setting timing is shown in figure 12.21.
As a result of the write to address H'FFFFD000 + X or H'FFFFE000 + X, a precharge all banks
(PALL) command is first issued in the TRp1 cycle, then a mode register write command is issued
in the TMw1 cycle.
Address signals, when the mode-register write command is issued, are as follows:
A15 to A9 = 0000100 (burst read and single write)
A8 to A6 = CAS latency
A5 = 0 (burst type = sequential)
A4 to A2 = 000 (burst length 1)
Before mode register setting, a 100 µs idle time (depending on the memory manufacturer) must be
guaranteed after powering on requested by the synchronous DRAM. If the reset signal pulse width
is greater than this idle time, there is no problem in performing mode register setting immediately.
The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must
be executed. This is usually achieved automatically while various kinds of initialization are being
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Section 12 Bus State Controller (BSC)
performed after auto-refresh setting, but a way of carrying this out more dependably is to set a
short refresh request generation interval just while these dummy cycles are being executed. With
simple read or write access, the address counter in the synchronous DRAM used for autorefreshing is not initialized, and so the cycle must always be an auto-refresh cycle.
TRp1
TRp2
TRp3
TRp4
TMw1
TMw2
TMw3
CKIO, CKIO2
A15 to A13
or A15 to A12
A11
A12 or A10
A9 to A2
CSn
RD/WR
RAS3
CAS
D31 to D0
CKE
(High)
Figure 12.21 Synchronous DRAM Mode Write Timing
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TMw4
Section 12 Bus State Controller (BSC)
12.3.5
Burst ROM Interface
Setting bits A0BST (1, 0), A5BST (1, 0), and A6BST (1, 0) in BCR1 to a non-zero value allows
burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed
access to ROM that has a nibble access function. The timing for nibble access to burst ROM is
shown in figure 12.22. Two wait cycles are set. Basically, access is performed in the same way as
for normal space, but when the first cycle ends the CS0 signal is not negated, and only the address
is changed before the next access is executed. When 8-bit ROM is connected, the number of
consecutive accesses can be set as 4, 8, or 16 by bits A0BST (1, 0), A5BST (1, 0), or A6BST (1,
0). When 16-bit ROM is connected, 4 or 8 can be set in the same way. When 32-bit ROM is
connected, only 4 can be set.
WAIT pin sampling is performed in the first access if one or more wait states are set, and is
always performed in the second and subsequent accesses.
Even if no wait state insertion is specified in burst ROM interface settings, two wait cycles are
automatically inserted in the second and subsequent accesses as shown in figure 12.23.
However, the WAIT signal is ignored in the following three cases:
•
When writing to an external address area using DMA 16-byte transfer in dual address mode
•
When transferring data from a DACK-equipped external device to an external address area
using DMA 16-byte transfer in single address mode
•
During cache write-back access
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Section 12 Bus State Controller (BSC)
T1
TW
TW
TB2
TB1
TW
TB2
TB1
CKIO
A25 to A4
A3 to A0
CSn
RD/WE
RD
D31 to
D0
BS
WAIT
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 12.22 Burst ROM Wait Access Timing
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T2
Section 12 Bus State Controller (BSC)
T1
TB2
TB1
TB2
TB1
TB2
TB1
T2
CKIO
A25 to A4
A3 to A0
CSn
RD/WE
RD
D31 to D0
BS
WAIT
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 12.23 Burst ROM Basic Access Timing
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Section 12 Bus State Controller (BSC)
12.3.6
PCMCIA Interface
In this LSI, setting the A5PCM bit in BCR1 to 1 makes the bus interface for physical space area 5
an IC memory card and I/O card interface as stipulated in JEIDA version 4.2 (PCMCIA2.1).
Setting the A6PCM bit to 1 makes the bus interface for physical space area 6 an IC memory card
and I/O card interface as stipulated in JEIDA version 4.2.
When the PCMCIA interface is used, a bus size of 8 or 16 bits can be set by bits A5SZ1 and
A5SZ0, or A6SZ1 and A6SZ0, in BCR2.
Figure 12.24 shows an example of PCMCIA card connection to this LSI. To enable active
insertion of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a
3-state buffer must be connected between this LSI's bus interface and the PCMCIA cards.
As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications,
the PCMCIA interface for this LSI in big-endian mode is stipulated independently.
However, the WAIT signal is ignored in the following three cases:
•
When writing to an external address area using DMA 16-byte transfer in dual address mode
•
When transferring data from a DACK-equipped external device to an external address area
using DMA 16-byte transfer in single address mode
•
During cache write-back access
Rev. 5.00 Dec 12, 2005 page 350 of 1034
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Section 12 Bus State Controller (BSC)
A24 to A0
A25 to A0
G
D15 to D0
D7 to D0
RD/WR
CE1B/(CS6)
CE1A/(CS5)/(PTK[3])
CE2B/(PTE[5])
CE2A/(PTE[4])
D15 to D0
G
DIR
D15 to D8
PC card
(memory/IO)
G
DIR
SH7727
CE1
CE2
OE
WE/PGM
(IORD)
RD
WE/(WE1)/(DQMLU)
ICIORD/(WE2)/
(DQMUL)/(PTK[6])
ICIOWR/(WE3)/
(DQMUU)/(PTK[7])
WAIT
IOIS16/(PTG[7])
G
(IOWR)
WAIT
(IOIS16)
Card
detection
circuit
Output
port
CD1, CD2
A25 to A0
G
D7 to D0
D15 to D0
G
DIR
D15 to D8
PC card
(memory/IO)
G
DIR
CE1
CE2
OE
WE/PGM
G
WAIT
Card
detection
circuit
CD1, CD2
Figure 12.24 Example of PCMCIA Interface (If Internal PC Card Controller is not used.)
Rev. 5.00 Dec 12, 2005 page 351 of 1034
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Section 12 Bus State Controller (BSC)
Memory Card Interface Basic Timing: Figure 12.25 shows the basic timing for the PCMCIA IC
memory card interface. When physical space areas 5 and 6 are designated as PCMCIA interface
areas, bus accesses are automatically performed as IC memory card interface accesses.
With a high external bus frequency (CKIO), the setup and hold times for the address (A24 to A0),
card enable (CS5, CE2A, CS6, CE2B), and write data (D15 to D0) in a write cycle, become
insufficient with respect to RD and WR (the WE pin in this LSI). This LSI provides for this by
enabling setup and hold times to be set for physical space areas 5 and 6 in the PCR register. Also,
software waits by means of a WCR2 register setting and hardware waits by means of the WAIT
pin can be inserted in the same way as for the basic interface. Figure 12.26 shows the PCMCIA
memory bus wait timing.
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Section 12 Bus State Controller (BSC)
Tpcm1
Tpcm2
CKIO
A25 to A0
CExx
RD/WR
RD
(read)
D15 to D0
(read)
WE
(write)
D15 to D0
(read)
BS
Figure 12.25 Basic Timing for PCMCIA Memory Card Interface
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Section 12 Bus State Controller (BSC)
Tpcm0
Tpcm0w
Tpcm1
Tpcm1w Tpcm1w
Tpcm2
Tpcm2w
CKIO
A25 to A0
CExx
RD/WR
RD
(read)
D15 to D0
(read)
WE
(write)
D15 to D0
(write)
BS
WAIT
Figure 12.26 Wait Timing for PCMCIA Memory Card Interface
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Section 12 Bus State Controller (BSC)
Memory Card Interface Burst Timing: In this LSI, when the IC memory card interface is
selected, page mode burst access mode can be used, for read access only, by setting bits A5BST1
and A5BST0 in BCR1 for physical space area 5, or bits A6BST1 and A6BST0 in BCR1 for area
6. This burst access mode is not stipulated in JEIDA version 4.2 (PCMCIA2.1), but allows highspeed data access using ROM provided with a burst mode, etc.
Burst access mode timing is shown in figures 12.27 and 12.28.
Tpcm1
Tpcm2
Tpcm1
Tpcm2
Tpcm1
Tpcm2
Tpcm1
Tpcm2
CKIO
A25 to A4
A3 to A0
CExx
RD/WR
RD
(read)
D15 to D0
(read)
BS
Figure 12.27 Basic Timing for PCMCIA Memory Card Interface Burst Access
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Section 12 Bus State Controller (BSC)
Tpcm0
Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2
Tpcm1 Tpcm1w
Tpcm2 Tpcm2w
CKIO
A25 to A4
A3 to A0
CExx
RD/WR
RD
(read)
D15 to D0
(read)
BS
WAIT
Figure 12.28 Wait Timing for PCMCIA Memory Card Interface Burst Access
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Section 12 Bus State Controller (BSC)
When the IC memory card interface uses entire 32-Mbyte memory space, the REG signal to
switch common memory and attribute memory can be generated by a port. If the IC card memory
interface uses memory area of 16 Mbytes or less, 32-Mbyte memory space can be used as 16Mbyte common memory space and 16-Mbyte attribute memory space as shown in figure 12.29.
In this case, A24 pin can be used as the REG signal.
IC memory interface = 32 Mbytes (I/O port is used for REG)
Area 5: H'14000000
Common/Attribute memory
Area 5: H'16000000
I/O space
Area 6: H'18000000
Common/Attriute memory
Area 6: H'1A000000
I/O space
IC memory interface = 16 Mbytes or less (A24 is used for REG)
Area 5: H'14000000
Attribute memory
Area 5: H'15000000
Common memory
Area 5: H'16000000
I/O space
H'17000000
Area 6: H'18000000
Attribute memory
Area 6: H'19000000
Common memory
Area 6: H'1A000000
I/O space
H'1B000000
Figure 12.29 PCMCIA Space Assignment
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Section 12 Bus State Controller (BSC)
I/O Card Interface Timing: Figures 12.30 and 12.31 show the timing for the PCMCIA I/O card
interface.
Switching between the I/O card interface and the IC memory card interface is performed
according to the accessed address. When PCMCIA is designed for physical space area 5, the bus
access is automatically performed as an I/O card interface access when a physical address from
H'16000000 to H'17FFFFFF is accessed. When PCMCIA is designated for physical space area 6,
the bus access is automatically performed as an I/O card interface access when a physical address
from H'1A000000 to H'1BFFFFFF is accessed.
When accessing a PCMCIA I/O card, the access should be performed using a non-cacheable area
in virtual space (P2 or P3 space) or an area specified as non-cacheable by the MMU.
When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic
sizing of the I/O bus width is possible using the IOIS16 pin. When a 16-bit bus width is set for
area 5 or area 6, if the IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is
recognized as being 8 bits in width. In this case, a data access for only 8 bits is performed in the
I/O bus cycle being executed, followed automatically by a data access for the remaining 8 bits.
Figure 12.32 shows the basic timing for dynamic bus sizing.
In big-endian mode, the IOIS16 signal is not supported.
In big-endian mode, the IOIS16 signal should be fixed low.
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Section 12 Bus State Controller (BSC)
Tpci1
Tpci2
CKIO
A25 to A0
CExx
RD/WR
ICIORD
(read)
D15 to D0
(read)
ICIOWR
(write)
D15 to D0
(write)
BS
Figure 12.30 Basic Timing for PCMCIA I/O Card Interface
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Section 12 Bus State Controller (BSC)
Tpci0
Tpci0w
Tpci1
Tpci1w
Tpci1w
Tpci2
Tpci2w
CKIO
A25 to A0
CExx
RD/WR
ICIORD
(read)
D15 to D0
(read)
ICIOWR
(write)
D15 to D0
(write)
BS
WAIT
IOIS16
Figure 12.31 Wait Timing for PCMCIA I/O Card Interface
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Section 12 Bus State Controller (BSC)
Tpci0
Tpci1 Tpci1w Tpci2
Tpci1
Tpci1w Tpci2 Tpci2w
CKIO
A25 to A1
A0
CExx
RD/WR
ICIORD
(read)
D15 to D0
(read)
ICIOWR
(write)
D15 to D0
(write)
BS
WAIT
IOIS16
Figure 12.32 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface
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Section 12 Bus State Controller (BSC)
12.3.7
Waits between Access Cycles
A problem associated with higher external memory bus operating frequencies is that data buffer
turn-off on completion of a read from a low-speed device may be too slow, causing a collision
with data in the next access. This results in lower reliability or incorrect operation. To avoid this
problem, a data collision prevention feature has been provided. This memorizes the preceding
access area and the kind of read/write. If there is a possibility of a bus collision when the next
access is started, a wait cycle is inserted before the access cycle thus preventing a data collision.
There are two cases in which a wait cycle is inserted: when an access is followed by an access to a
different area, and when a read access is followed by a write access from this LSI. When this LSI
performs consecutive write cycles, the data transfer direction is fixed (from this LSI to other
memory) and there is no problem. With read accesses to the same area, in principle, data is output
from the same data buffer, and wait cycle insertion is not performed. Bits AnIW1 and AnIW0 (n =
0, 2 to 6) in WCR1 specify the number of idle cycles to be inserted between access cycles when a
physical space area access is followed by an access to another area, or when this LSI performs a
write access after a read access to physical space area n. If there is originally space between
accesses, the number of idle cycles inserted is the specified number of idle cycles minus the
number of empty cycles.
Waits are not inserted between accesses when bus arbitration is performed, since empty cycles are
inserted for arbitration purposes.
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Section 12 Bus State Controller (BSC)
T1
T2
Twait
T1
T2
Twait
T1
T2
CKIO
A25 to A0
CSm
CSn
BS
RD/WR
RD
D31 to D0
Area m read
Area n space read
Area n space write
Area m inter-access wait specification
Area n inter-access wait specification
Figure 12.33 Waits between Access Cycles
12.3.8
Bus Arbitration
When a bus release request (BREQ) is received from an external device, buses are released after
the bus cycle being executed is completed and a bus grant signal (BACK) is output. The bus is not
released during burst transfers for cache fills or TAS instruction execution between the read cycle
and write cycle. Bus arbitration is not executed in multiple bus cycles that are generated when the
data bus width is shorter than the access size; i.e. in the bus cycles when longword access is
executed for the 8-bit memory. At the negation of BREQ, BACK is negated and bus use is
restarted. See Appendix A.1, Pin Functions, for the pin state when the bus is released.
Rev. 5.00 Dec 12, 2005 page 363 of 1034
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Section 12 Bus State Controller (BSC)
12.3.9
Bus Pull-Up
With this LSI, address pin pull-up can be performed when the bus is released by setting the PULA
bit in BCR1 to 1. The address pins are pulled up for a 4-clock period after BACK is asserted.
Figure 12.34 shows the address pin pull-up timing. Similarly, data pin pull-up can be performed
by setting the PULD bit in BCR1 to 1. The data pins should be pulled up when the data bus is not
in use. The data pin pull-up timing for a read cycle is shown in figure 12.35, and the timing for a
write cycle in figure 12.36.
CKIO
A25 to A0
Pull-up
Hi-Z
BACK
Figure 12.34 Pins A25 to A0 Pull-Up Timing
CKIO
D31 to D0
Pull-up
Pull-up
RD
CSn
Figure 12.35 Pins D31 to D0 Pull-Up Timing (Read Cycle)
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Section 12 Bus State Controller (BSC)
CKIO
D31 to D0
Pull-up
Pull-up
WEn
CSn
Figure 12.36 Pins D31 to D0 Pull-Up Timing (Write Cycle)
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Section 12 Bus State Controller (BSC)
Rev. 5.00 Dec 12, 2005 page 366 of 1034
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Section 13 Li Bus State Controller (LBSC)
Section 13 Li Bus State Controller (LBSC)
13.1
Overview
The Li bus state controller (LBSC) functions enable LCD controller and Open HCI compliant
USB Host controller to link directly with synchronous DRAM. LBSC is a slave bus state
controller of BSC.
13.1.1
Features
The LBSC has the following features:
• Direct interface to synchronous DRAM
Physical address space is specified only to area 3
A maximum 64 Mbytes
Multiplexes row/column addresses according to synchronous DRAM capacity
Supports burst operation with various burst length; selectable from 1 to 32
Controls timing of synchronous DRAM direct-connection control signals according to
register setting
16-bit or 32-bit bus width according to register setting
13.1.2
Register Configuration
The LBSC does not have any register inside, but refers BSC registers shown in table 13.1.
Table 13.1 Register Configuration
Name
Abbr.
R/W
Initial Value*
Address
Bus Width
Bus control register 1
BCR1
R/W
H'0000
H'FFFFFF60
16
Bus control register 2
BCR2
R/W
H'3FF0
H'FFFFFF62
16
Wait state control register 1
WCR1
R/W
H'3FF3
H'FFFFFF64
16
Wait state control register 2
WCR2
R/W
H'FFFF
H'FFFFFF66
16
Individual memory control
register
MCR
R/W
H'0000
H'FFFFFF68
16
Note: * Initialized by power-on resets.
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Section 13 Li Bus State Controller (LBSC)
13.1.3
Bus Control Register 1 (BCR1)
Bus control register 1 (BCR1) is a 16-bit read/write register that sets the functions and bus cycle
state for each area. It is initialized to H'0000 by a power-on reset, but it is not initialized by a
manual reset or in standby mode. Do not access external memory except area 0 until BCR1
register initialization is complete.
Bit:
Initial value:
R/W:
Bit:
15
14
13
PULA
PULD
0
0
R/W:
11
10
9
8
0
0
0/1*
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
7
6
5
1
0
HIZMEM HIZCNT ENDIAN A0BST1 A0BST0 A5BST1
A5BST0 A6BST1 A6BST0
Initial value:
12
4
3
2
DRAM
TP2
DRAM
TP1
DRAM
TP0
A5PCM A6PCM
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Samples the value of the external pin (MD5) designating endian at power-on reset.
Bits 15 to 12—Not referenced
Bit 11—Endian Flag (ENDIAN): Samples a value at the external pin which designates endian
(MD5) at a power-on reset. Endian for all physical spaces is decided by this bit. This bit is readonly.
Bit 11: ENDIAN
Description
0
At a reset, the endian setting external pin (MD5) is low, which indicates that
the SH7727 is set as big endian.
1
At a reset, the endian setting external pin (MD5) is high, which indicates that
the SH7727 is set as little endian.
Bits 10 to 5—Not referenced
Rev. 5.00 Dec 12, 2005 page 368 of 1034
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Section 13 Li Bus State Controller (LBSC)
Bits 4 to 2—Area 2, Area 3 Memory Type (DRAMTP2, DRAMTP1, DRAMTP0): Specifies
the type of memory connected to the physical space areas 2 and 3. Before using LCDC and USB,
set area 3 to synchronous DRAM (DRAMTP2 to DRAMTP0 equal to 010 or 011).
Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description
0
0
1
1
0
1
0
Ordinary memory for areas 2 and 3
(Initial value)
1
Reserved (Setting disabled)
0
Ordinary memory for area 2 and
1
synchronous DRAM for area 3*
1
1 2
Synchronous DRAM for areas 2 and 3* *
0
Reserved
1
Reserved
0
Reserved (Setting disabled)
1
Reserved (Setting disabled)
Notes: 1. It is not possible to access synchronous DRAM if clock ratio Iφ:bus clock = 1:1.
2. When selecting this mode, set the same bus width for area 2 and area 3.
Bits 1 and 0 —Not referenced
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Section 13 Li Bus State Controller (LBSC)
13.1.4
Bus Control Register 2 (BCR2)
The bus control register 2 (BCR2) is a 16-bit read/write register that sets the bus-size width of
each area and selects whether an 8-bit port is used or not. It is initialized to H'3FF0 by a power-on
reset, but is not initialized by a manual reset or by standby mode. Do not access external memory
outside area 0 until BCR2 register initialization is complete.
Bit:
15
14
13
12
11
10
9
8
—
—
A6SZ1
A6SZ0
A5SZ1
A5SZ0
A4SZ1
A4SZ0
Initial value:
0
0
1
1
1
1
1
1
R/W:
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
A3SZ1
A3SZ0
A2SZ1
A2SZ0
—
—
—
—
1
1
1
1
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
Initial value:
R/W:
Bits 15 to 8 and 5 to 0 —Not referenced
Bits 7 and 6—Area 3 Bus Size Specification (A3SZ1, A3SZ0): Specifies the bus sizes of
physical space area 3.
Bit 7: A3SZ1
Bit 6: A3SZ0
Port A/B
Description
0
0
Unused
Reserved (Setting disabled)
1
0
1
1
Reserved (Setting disabled)
0
16-bit bus width
1
32-bit bus width
0
Used
Reserved (Setting disabled)
1
Reserved (Setting disabled)
0
16-bit bus width
1
Reserved (Setting disabled)
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Section 13 Li Bus State Controller (LBSC)
13.1.5
Wait State Control Register 1 (WCR1)
Wait state control register 1 (WCR1) is a 16-bit read/write register that specifies the number of
idle (wait) state cycles inserted for each area. For some memories, the drive of the data bus may
not be turned off quickly even when the read signal from the external device is turned off. This
can result in conflicts between data buses when consecutive memory accesses are to different
memories or when a write immediately follows a memory read. This LSI automatically inserts idle
states equal to the number set in WCR1 in those cases.
WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or by
standby mode.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
WAIT
SEL
—
A6IW1
A6IW0
A5IW1
A5IW0
A4IW1
A4IW0
0
0
1
1
1
1
1
1
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
A3IW1
A3IW0
A2IW1
A2IW0
—
—
A0IW1
A0IW0
1
1
1
1
0
0
1
1
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Bits 15 to 8 and 5 to 0 —Not referenced
Bits 7 and 6— Area 3 Idle Setting between Cycles (A3IW1, A3IW0): Specifies the number of
idle state cycles to insert between bus cycles when switching from a read address in area 3 of the
physical space to a write address in another space or within the same space.
Bit 7: A3IW1
Bit 6: A3IW0
Description
0
0
1 idle state cycle inserted
1
1 idle state cycle inserted
1
0
2 idle state cycle inserted
1
3 idle state cycle inserted
(Initial value)
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Section 13 Li Bus State Controller (LBSC)
13.1.6
Wait State Control Register 2 (WCR2)
Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of
wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory
accesses. This allows direct connection of even low-speed memories without an external circuit.
WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or in
standby mode.
Bit:
15
14
13
12
11
10
9
8
A6W2
A6W1
A6W0
A5W2
A5W1
A5W0
A4W2
A4W1
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
R/W:
Bit:
7
6
5
4
3
2
1
0
A4W0
A3W1
A3W0
A2W1
A2W0
A0W2
A0W1
A0W0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
R/W:
Bits 15 to 7 and 4 to 0 —Not referenced
Bits 6 and 5— Area 3 Wait Control (A3W1, A3W0): Specifies the CAS latency for the
SDRAM of area 3 of the physical space.
Bit 6: A3W1
Bit 5: A3W0
Description
SDRAM CAS Latency
0
1
0
1
1
1
0
2
1
3
Rev. 5.00 Dec 12, 2005 page 372 of 1034
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(Initial value)
Section 13 Li Bus State Controller (LBSC)
13.1.7
Individual Memory Control Register (MCR)
The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS
and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address
multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without
external circuits.
The MCR is initialized to H'0000 by power-on resets, but is not initialized by manual resets or
standby mode. The bits TPC1 to TPC0, RCD1 to RCD0, TRWL1 to TRWL0, TRAS1 to TRAS0,
and AMX3 to AMX0 are written to at the initialization after a power-on reset and should not be
modified again. When RFSH and RMODE are written to, write the same values to the other bits.
When using synchronous DRAM, do not access areas 2 and 3 until this register initialization is
complete.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
TPC1
TPC0
RCD1
RCD0
TRWL1
TRWL0
TRAS1
TRAS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
—
AMX3
AMX2
AMX1
AMX0
RFSH
RMODE
—
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 and 14—RAS Precharge Time (TPC1, TPC0): When synchronous DRAM interface is
selected, these bits set the minimum number of cycles until output of the next bank-active
command after precharge.
Bit 15: TPC1
Bit 14: TPC0
Description
0
0
1 cycle
1
2 cycles
1
0
3 cycles
1
4 cycles
(Initial value)
Rev. 5.00 Dec 12, 2005 page 373 of 1034
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Section 13 Li Bus State Controller (LBSC)
Bits 13 and 12—RAS–CAS Delay (RCD1, RCD0): When synchronous DRAM interface is
selected, these bits set the bank active read/write command delay time.
Bit 13: RCD1
Bit 12: RCD0
Description
0
0
1 cycle
1
2 cycles
0
3 cycles
1
4 cycles
1
(Initial value)
Bits 11 and 10—Write-Precharge Delay (TRWL1, TRWL0): The TRWL bits set the
synchronous DRAM write-precharge delay time. This designates the time between the end of a
write cycle and the automatic precharge activation. After the write cycle, the next bank-active
command is not issued for the period TPC + TRWL.
Bit 11: TRWL1
Bit 10: TRWL0
Description
0
0
1 cycle
1
2 cycles
0
3 cycles
1
Reserved (Setting disabled)
1
(Initial value)
Bits 9 and 8—CAS
CAS-Before-RAS
RAS Refresh RAS Assert Time (TRAS1, TRAS0): When
CAS
synchronous DRAM interface is selected, no bank-active command is issues during the period
TPC + TRAS after an auto-refresh command.
Bit 9: TRAS1
Bit 8: TRAS0
Description
0
0
2 cycles
1
3 cycles
1
0
4 cycles
1
5 cycles
Bit 7—Reserved: This bit is always read as 0 and should only be written with 0.
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(Initial value)
Section 13 Li Bus State Controller (LBSC)
Bits 6 to 3—Address Multiplex (AMX3 , AMX2, AMX1, AMX0): The AMX bits specify
address multiplexing for synchronous DRAM.
Bit6:
AMX3
Bit5:
AMX2
Bit 4:
AMX1
Bit 3:
AMX0
1
1
0
1
When using a 16-bit bus width, the row address begins with
A10. When using a 32-bit bus width, it begins with A11.
(The A10 value is output at A1 when the row address is
output. 4M × 16-bit × 4-bank products)
1
0
When using a 16-bit bus width, the row address begins with
A11.
(The A11 value is output at A1 when the row address is
1
output. 8M × 16-bit × 4-bank products)*
0
0
When using a 16-bit bus width, the row address begins with
A9. When using a 32-bit bus width, it begins with A10.
(The A9 value is output at A1 when the row address is
output. 1M × 16-bit × 4-bank products)
1
When using a 16-bit bus width, the row address begins with
A10. When using a 32-bit bus width, it begins with A11.
(The A10 value is output at A1 when the row address is
output. 2M × 8-bit products)
0
The row address begins with A11 when bus width is 32 bit. *
0
1
Description
2
(The A11 value is output at A1 when the row address is
output. 4M × 8-bit × 4-bank products)
0
1
1
When using a 16-bit bus width, the row address begins with
A9. When using a 32-bit bus width, it begins with A10.
(The A9 value is output at A1 when the row address is output.
2
512K × 32-bit × 4-bank products) *
0
0
Reserved. AMX3 to AMX0 must be set to *1*** before
accessing synchronous DRAM memory.
(Initial value)
Other values
Reserved (Illegal setting)
Notes: 1. Can be set only when using a 16-bit bus width.
2. Can be set only when using a 32-bit bus width.
Bits 2 and 1—Not referenced
Bit 0—Reserved: This bit is always read as 0 and should only be written with 0.
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Section 13 Li Bus State Controller (LBSC)
13.2
LBSC Operation
13.2.1
Bus Sharing Architecture
LCDC and USB Host Controller can share the system memory with CPU and DMA Controller, so
these bus masters are able to work without any independent external memory and have huge
available memory space up to 64 Mbyte at area 3.
Since each LCDC, USB Host Controller, CPU, and DMA Controller can access area 3
individually. Set addresses for each controller to avoid address sharing.
13.2.2
Usable System Memory
LBSC works at below memories.
Memory area
Area3
Memory type
Synchronous DRAM
Bus width
16 or 32 bits
Burst length
1 to 4 burst (USBH)
4 to 32 burst (LCDC) with 32-bit bus width, 8 to 64
burst (LCDC) with 16-bit bus width
13.2.3
Bus Arbitration
LBSC accepts a request that comes from LCDC or USB Host at a same time without any
prioritization to each module. LBSC tries to get bus right from BSC at any time when it get a
request from LCDC or USB Host. Once BSC gives LBSC a right, LCDC or BSC can access
external memory directly. The arbiter of LBSC gives a bus right to LCDC or USB Host as even.
13.2.4
LCDC Li Bus Access
While displaying images, the LCDC continuously reads data from the system memory with a 32
burst length. The LCDC burst length is specified by a register in the LCDC. If the data length is
shorter than 32 burst length, such as the case for the edge of LCD panel, the LCDC uses a shorter
burst length.
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Section 13 Li Bus State Controller (LBSC)
13.2.5
USBH Li Bus Access
USB Host issues 1 to 4 burst request to LBSC as normal read or write action. Since the burst
length issued by USB Host is occasionally changed as FIFO pointer rises up or falls, it is not
supposed as 4 burst exactly.
SH7727
BSC
Bus arbitration
Synchronous
DRAM
Bus
(Area 3)
USBH
LBSC
Li bus
LCDC
Figure 13.1 Block Diagram of Li Bus Architecture
13.2.6
Setting of DMA Transfer with Bus Arbitration of Other Module
This LSI has five types of bus master: CPU, DMAC and Refresh (BSC system), and LCDC and
USBH (LBSC system). The following priority order is set for these buses.
1. The BSC and LBSC systems are the same in priority level.
2. In the BSC system, Refresh has the highest priority.
3. Between CPU and DMAC, DMAC is higher in priority when DMA burst setting is made. In
cycle steal, CPU and DMAC are the same in priority level.
4. LCDC and USBH are the same priority level in the LBSC system.
In cycle steal, the priority level of DMA transfer is very low. Therefore, if the DMAC transfer
speed may cause problems, it is recommended to use the level-input burst transfer setting for
DMAC, especially when DREQ signals from an external device can be negated.
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Section 13 Li Bus State Controller (LBSC)
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Section 14 Direct Memory Access Controller (DMAC)
Section 14 Direct Memory Access Controller (DMAC)
14.1
Overview
This chip includes a four-channel direct memory access controller (DMAC). The DMAC can be
used in place of the CPU to perform high-speed transfers between external devices that have
DACK (transfer request acknowledge signal), external memory, memory-mapped external
devices, and on-chip supporting modules (SIOF, SCIF, USB function, and A/D converter). Using
the DMAC reduces the burden on the CPU and increases overall operating efficiency.
14.1.1
Features
The DMAC has the following features.
• Four channels
• 4-GB physical address space
• Selectable data transfer length: 8-bit, 16-bit, 32-bit, or 16-byte transfer (In 16-byte transfer,
four 32-bit reads are executed, followed by four 32-bit writes.)
• Maximum of 16 M times of transfers (16777216 times)
• Address mode: Dual address mode and single address mode are supported. In addition, direct
address transfer mode or indirect address transfer mode can be selected.
Dual address mode transfer: Both the transfer source and transfer destination are accessed
by address. Dual address mode has direct address transfer mode and indirect address
transfer mode.
Direct address transfer mode: The values specified in the DMAC registers indicates the
transfer source and transfer destination. Two bus cycles are required for one data transfer.
Indirect address transfer mode: Data is transferred with the address stored prior to the
address specified in the transfer source address in the DMAC. Other operations are the
same as those of direct address transfer mode. This function is only valid in channel 3.
Four bus cycles are requested for one data transfer.
Single address mode transfer: Either the transfer source or transfer destination peripheral
device is accessed (selected) by means of the DACK signal, and the other device is
accessed by address. One transfer unit of data is transferred in one bus cycle.
• Channel functions: Transfer mode that can be specified is different in each channel.
Channel 0: Can accept requests from peripheral modules and external requests.
Channel 1: Can accept requests from peripheral modules.
Channel 2: Can accept requests from peripheral modules. This channel has a source address
reload function, which reloads a source address for each 4 transfers.
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Section 14 Direct Memory Access Controller (DMAC)
Channel 3: Can accept requests from peripheral modules. Direct address transfer mode or
indirect address transfer mode can be specified.
• Reload function: The value that was specified in the source address register can be
automatically reloaded every 4 DMA transfers. This function is only valid in channel 2.
• Three types of transfer requests
External requests (From two DREQ pins (channels 0 only). DREQ can be detected either
by falling edge or by low level)
On-chip module requests (Requests from on-chip supporting modules such as serial
communications interface (SIOF, SCIF), A/D converter (A/D) and a timer (CMT) . This
request can be accepted in all the channels)
Auto requests (the transfer request is generated automatically within the DMAC)
• Selectable bus modes: Cycle-steal mode or burst mode
• Selectable channel priority levels:
Fixed mode: The channel priority is fixed.
Round-robin mode: The priority of the channel in which the execution request was accepted is
made the lowest.
• Interrupt request: An interrupt request can be generated to the CPU after the specified number
of times of transfers.
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Section 14 Direct Memory Access Controller (DMAC)
14.1.2
Block Diagram
Figure 14.1 is a block diagram of the DMAC.
DMAC module
Interation
control
SARn
Register
control
DARn
On-chip
supporting
module
USBF
SIOF
Internal bus
Peripheral bus
X/Y memory
DMATCRn
Start-up
control
CHCRn
Selector Ch0 to Ch3
CHRAR
DMAOR
DREQ0
SCIF
A/D converter
CMT
DEIn
Request
priority
control
DACK0, DRAK0
External
ROM
Bus interface
External
RAM
Legend:
External I/O
(memory
mapped)
External I/O
(with
acknowledge)
Bus state
controller
DMAOR: DMAC operation register
DMAC source address register
SARn:
DMAC destination address register
DARn:
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
CHRAR: DMA channel assign register
DMA transfer-end interrupt request to
DEIn:
CPU
0 to 3
n:
Figure 14.1 DMAC Block Diagram
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Section 14 Direct Memory Access Controller (DMAC)
14.1.3
Pin Configuration
Table 14.1 shows the DMAC pins.
Table 14.1 Pin Configuration
Channel
Name
Symbol
I/O
Function
0
DMA transfer request
DREQ0
Input
DMA transfer request input from
external device to channel 0
DREQ acknowledge
DACK0
Output
Strobe output to an external I/O at DMA
transfer request from external device to
channel 0
DMA request
acknowledge
DRAK0
Output
Output showing that DREQ0 has been
accepted
14.1.4
Register Configuration
Table 14.2 summarizes the DMAC registers. DMAC has a total of 18 registers, four registers for
each channel and two registers for controlling all channels.
Table 14.2 DMAC Registers
Abbreviation
R/W
Initial
Value
SAR0
R/W
Undefined
H'04000020
32 bits
(H'A4000020)*4
16, 32*2
DMA destination address DAR0
register 0
R/W
Undefined
H'04000024
32 bits
(H'A4000024)*4
16, 32*2
DMA transfer count
register 0
DMATCR0 R/W
Undefined
H'04000028
24 bits
(H'A4000028)*4
16, 32*3
DMA channel control
register 0
CHCR0
R/W*1 H'00000000 H'0400002C
32 bits
(H'A400002C)*4
8, 16,
32*2
DMA source address
register 1
SAR1
R/W
Undefined
H'04000030
32 bits
(H'A4000030)*4
16, 32*2
DMA destination address DAR1
register 1
R/W
Undefined
H'04000034
32 bits
(H'A4000034)*4
16, 32*2
DMA transfer count
register 1
DMATCR1 R/W
Undefined
H'04000038
24 bits
(H'A4000038)*4
16, 32*3
DMA channel control
register 1
CHCR1
Channel
Name
0
DMA source address
register 0
1
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Address
Register Access
Size
Size
R/W*1 H'00000000 H'0400003C
32 bits
(H'A400003C)*4
8, 16,
32*2
Section 14 Direct Memory Access Controller (DMAC)
Abbreviation
R/W
Initial
Value
SAR2
R/W
Undefined
H'04000040
32 bits
(H'A4000040)*4
16, 32*2
DMA destination address DAR2
register 2
R/W
Undefined
H'04000044
32 bits
(H'A4000044)*4
16, 32*2
DMA transfer count
register 2
DMATCR2 R/W
Undefined
H'04000048
24 bits
(H'A4000048)*4
16, 32*3
DMA channel control
register 2
CHCR2
R/W*1 H'00000000 H'0400004C
32 bits
(H'A400004C)*4
8, 16,
32*2
DMA source address
register 3
SAR3
R/W
Undefined
H'04000050
32 bits
(H'A4000050)*4
16, 32*2
DMA destination address DAR3
register 3
R/W
Undefined
H'04000054
32 bits
(H'A4000054)*4
16, 32*2
DMA transfer count
register 3
DMATCR3 R/W
Undefined
H'04000058
24 bits
(H'A4000058)*4
16, 32*3
DMA channel control
register 3
CHCR3
R/W*1 H'00000000 H'0400005C
32 bits
(H'A400005C)*4
8, 16,
32*2
DMA operation register
DMAOR
R/W *1 H'0000
H'04000060
16 bits
(H'A4000060)*4
8, 16*2
DMA channel assign
register
CHRAR
R/W
H’0400022A
16 bits
(H’A400022A)*4
16
Channel
Name
2
DMA source address
register 2
3
Shared
H’0000
Address
Register Access
Size
Size
Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on,
either access these registers from the P2 area of logical space or else make an appropriate
setting using the MMU so that these registers are not cached.
1. Only a write of 0 after a read of 1 to clear a flag is enabled for bit 1 in CHCR0 to
CHCR3 and bits 1 and 2 in DMAOR.
2. If SAR0 to SAR3, DAR0 to DAR3, and CHCR0 to CHCR3 are accessed in 16 bits, the
16 bit values that were not accessed are held.
3. DMATCR comprises the 24 bits from bit 0 to bit 23. The upper 8 bits, bits 24 to 31,
cannot be written with 1 and are always read as 0.
4. When address translation by the MMU does not apply, the address in parentheses
should be used.
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Section 14 Direct Memory Access Controller (DMAC)
14.2
Register Descriptions
14.2.1
DMA Source Address Registers 0 to 3 (SAR0 to SAR3)
Bit:
Initial value:
R/W:
Bit:
31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
…
0
…
Initial value:
R/W:
—
—
—
—
…
—
R/W
R/W
R/W
R/W
…
R/W
The DMA source address registers 0 to 3 (SAR0 to SAR3) are 32-bit read/write registers that
specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the
next source address.
To transfer data in 16 bits or in 32 bits, specify the address on the 16-bit or 32-bit boundary.
When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the
source address value. If any other address is specified, correct operation is not guaranteed.
Initial values are undefined after a reset. The previous values are held in standby mode.
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Section 14 Direct Memory Access Controller (DMAC)
14.2.2
DMA Destination Address Registers 0 to 3 (DAR0 to DAR3)
Bit:
31
30
29
28
27
26
25
24
Initial value:
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
R/W:
Bit:
…
0
…
Initial value:
R/W:
—
—
—
—
…
—
R/W
R/W
R/W
R/W
…
R/W
The DMA destination address registers 0 to 3 (DAR0 to DAR3) are 32-bit read/write registers that
specify the destination address of a DMA transfer. These registers include count functions, and
during a DMA transfer, these registers indicate the next destination address.
To transfer data in 16 bits or in 32 bits, specify the address on the 16-bit or 32-bit boundary.
When transferring data in 16-byte units, always set a value at a 16-byte boundary (16n address) as
the destination address. If any other address is specified, correct operation is not guaranteed.
Initial values are undefined after a reset. The previous value is held in standby mode.
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Section 14 Direct Memory Access Controller (DMAC)
14.2.3
DMA Transfer Count Registers 0 to 3 (DMATCR0 to DMATCR3)
Bit:
31
30
29
28
27
26
25
24
Initial value:
—
—
—
—
—
—
—
—
R/W:
R
R
R
R
R
R
R
R
Bit:
23
22
21
20
...
0
...
Initial value:
R/W:
—
—
—
—
...
—
R/W
R/W
R/W
R/W
...
R/W
The DMA transfer count registers 0 to 3 (DMATCR0 to DMATCR3) are 24-bit read/write
registers that specify the DMA transfer count (bytes, words, or longwords). The number of
transfers is 1 when the setting is H'000001, and 16777216 (the maximum) when H'000000 is set.
During a DMA transfer, these registers indicate the remaining transfer count.
To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one.
The upper eight bits in DMATCR are always read as 0 and should only be written with 0.
Initial values are undefined after a reset. The previous value is held in standby mode.
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Section 14 Direct Memory Access Controller (DMAC)
14.2.4
DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3)
Bit:
31
...
21
20
19
18
17
16
—
...
—
DI
RO
RL
AM
AL
Initial value:
0
...
0
0
R/W:
R
...
R
Bit:
15
14
13
12
11
10
9
8
DM1
DM0
SM1
SM0
RS3
RS2
RS1
RS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
—
DS
TM
TS1
TS0
IE
TE
DE
Initial value:
R/W:
Bit:
Initial value:
0
0
R/W:
R
(R/W)*
2
0
0
0
0
2
2
2
2
2
*
*
*
*
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)*
0
0
0
0
0
R/W
R/W
R/W
R/W
R/(W)*
0
1
R/W
Notes: 1. Only a write of 0 after a read of 1 is enabled for the TE bit.
2. DI, RO, RL, AM, AL, and DS bits are not included in some channels.
The DMA channel control registers 0 to 3 (CHCR0 to CHCR3) are 32-bit read/write registers that
specify operation mode, transfer method, or others in each channel. Writing to bits 31 to 21 and 7
in this register is invalid, and these bits are always read as 0.
Bit 20 is only used in CHCR3. It is not used in CHCR0 to CHCR2. Consequently, writing to this
bit is invalid in CHCR0 to CHCR2, and this bit is always read as 0.
Bit 19 is only used in CHCR2. It is not used in CHCR0, CHCR1, and CHCR3. Consequently,
writing to this bit is invalid in CHCR0, CHCR1, and CHCR3, and this bit is always read as 0.
Bits 6 and 16 to 18 are only used in CHCR0 and CHCR1. They are not used in CHCR2 and
CHCR3. Consequently, writing to these bits is invalid in CHCR2 and CHCR3, and these bits are
always read as 0.
These registers are initialized to 0 after a power-on reset. The previous values are held in standby
mode.
Bits 31 to 21—Reserved: These bits are always read as 0 and should only be written with 0.
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Section 14 Direct Memory Access Controller (DMAC)
Bit 20—Direct/Indirect Selection (DI): DI selects direct address mode operation or indirect
address mode operation for a channel 3 source address.
This bit is only valid in CHCR3. This bit in CHCR0 to CHCR2 is always read as 0 and should
only be written with 0.
When using 16-byte transfer, direct address mode must be specified. Operation is not guaranteed if
indirect address mode is specified.
Bit 20: DI
Description
0
Direct address mode
1
Indirect address mode
(Initial value)
Bit 19—Source Address Reload (RO): RO selects whether the source address initial value is
reloaded in channel 2.
This bit is only valid in CHCR2. This bit in CHCR0, CHCR1, and CHCR3 is always read as 0
and should only be written with 0.
When using 16-byte transfer, this bit must be cleared to 0, specifying non-reloading. Operation is
not guaranteed if reloading is specified.
Bit 19: RO
Description
0
A source address is not reloaded
1
A source address is reloaded
(Initial value)
Bit 18—Request Check Level (RL): RL specifies the DRAK (acknowledge of DREQ) signal
output is high active or low active.
This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and
should only be written with 0.
Bit 18: RL
Description
0
Low-active output of DRAK
1
High-active output of DRAK
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(Initial value)
Section 14 Direct Memory Access Controller (DMAC)
Bit 17—Acknowledge Mode (AM): AM specifies whether DACK is output in data read cycle or
in data write cycle in dual address mode.
In single address mode, DACK is always output regardless of this bit specification.
This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and
should only be written with 0.
Bit 17: AM
Description
0
DACK output in read cycle
1
DACK output in write cycle
(Initial value)
Bit 16—Acknowledge Level (AL): AL specifies the DACK (acknowledge) signal output is high
active or low active.
This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and
should only be written with 0.
Bit 16: AL
Description
0
Low-active output of DACK
1
High-active output of DACK
(Initial value)
Bits 15 and 14—Destination Address Mode 1, 0 (DM1 and DM0): DM1 and DM0 select
whether the DMA destination address is incremented, decremented, or fixed.
Bit 15: DM1
Bit 14: DM0
Description
0
0
Fixed destination address*
1
Destination address is incremented (+1 in 8-bit transfer, +2 in
16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer)
0
Destination address is decremented (–1 in 8-bit transfer, –2 in
16-bit transfer, –4 in 32-bit transfer; illegal setting in 16-byte
transfer)
1
Reserved (illegal setting)
1
(Initial value)
Note: * This setting cannot be used to perform 16-byte transfers with a destination in X/Y memory.
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Section 14 Direct Memory Access Controller (DMAC)
Bits 13 and 12—Source Address Mode 1, 0 (SM1 and SM0): SM1 and SM0 select whether the
DMA source address is incremented, decremented, or fixed.
Bit 13: SM1
Bit 12: SM0
Description
0
0
Fixed source address*
1
Source address is incremented (+1 in 8-bit transfer, +2 in 16bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer)
0
Source address is decremented (–1 in 8-bit transfer, –2 in 16bit transfer, –4 in 32-bit transfer; illegal setting in 16-byte
transfer)
1
Reserved (illegal setting)
1
(Initial value)
Note: * This setting cannot be used to perform 16-byte transfers with a destination in X/Y memory.
If the transfer source is specified in indirect address, specify the address (indirect address) where
the address of data to be transferred is stored as data, in source address register 3 (SAR3).
Specification of SAR3 increment or decrement in indirect address mode depends on SM1 and
SM0 settings. In this case, however, the SAR3 increment or decrement value is +4, –4, or fixed to
0 regardless of the transfer data size specified in TS1 and TS0.
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Section 14 Direct Memory Access Controller (DMAC)
Bits 11 to 8—Resource 3 to 0 (RS3 to RS0): RS3 to RS0 specify which transfer requests will be
sent to the DMAC.
Bit 11: Bit 10: Bit 9:
RS3
RS2
RS1
Bit 8:
RS0
Description
0
0
0
External request* , dual address mode
1
Illegal setting
1
0
External request* /Single address mode
1
External address space → external device with DACK
1
External request* /Single address mode
0
Auto request
1
Illegal setting
0
Illegal setting
1
Illegal setting
0
0
Select DMA request expansion*
1
Illegal setting
1
0
Illegal setting
1
Illegal setting
0
SCIF transmission*
2
SCIF reception*
0
1
(Initial value)
1
External device with DACK → external address space
1
0
1
1
0
1
0
1
1
0
1
3
2
Internal A/D*
2
CMT*
2
Notes: 1. External request specification is valid only for channels 0. None of the request sources
can be selected for channels 1, 2 and 3.
2. When using 16-byte transfer, the following settings must not be made:
1100 SCIF transmission
1101 SCIF reception
1110 A/D converter
1111 CMT
Operation is not guaranteed if these settings are made.
3. When DMA transfer is provided with the USB function controller or SIOF, set RS3 to
RS0 to 1000 and select a desired module with the CHRAR register.
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Section 14 Direct Memory Access Controller (DMAC)
Bit 6—DREQ
DREQ Select (DS): DS selects the sampling method of the DREQ pin that is used in
external request mode is detection in low level or at the falling edge.
This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and
should only be written with 0.
Also, it should be cleared to 0 (low-level detection) if an on-chip supporting module is specified as
a transfer request source in channel 0.
Bit 6: DS
Description
0
DREQ detected in low level
1
DREQ detected at falling edge
(Initial value)
Bit 5—Transmit Mode (TM): TM specifies the bus mode when transferring data.
Bit 5: TM
Description
0
Cycle steal mode
1
Burst mode
(Initial value)
Bits 4 and 3—Transmit Size 1, 0 (TS1 and TS0): TS1 and TS0 specify the size of data to be
transferred.
Bit 4: TS1
Bit 3: TS0
Description
0
0
Byte size (8 bits)
0
1
Word size (16 bits)
1
0
Longword size (32 bits)
1
1
16-byte unit (4 longword transfers)
(Initial value)
Bit 2—Interrupt Enable (IE): Setting this bit to 1 generates an interrupt request when the
number of times of data transfers specified with DMATCR has completed (TE = 1).
Bit 2: IE
Description
0
Interrupt request is not generated even when data transfer ends by the
specified count
(Initial value)
1
Interrupt request is generated when data transfer ends by the specified count
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Section 14 Direct Memory Access Controller (DMAC)
Bit 1—Transfer End (TE): TE is set to 1 when data transfer ends by the count specified in
DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated.
Before this bit is set to 1, if data transfer ends due to an NMI interrupt, a DMAC address error, or
clearing the DE bit or the DME bit in DMAOR, this bit is not set to 1. Even if the DE bit is set to
1 while this bit is set to 1, transfer is not enabled.
Bit 1: TE
Description
0
Data transfer does not end by the count specified in DMATCR
(Initial value)
Clear condition: Writing 0 after TE = 1 read at power-on reset or manual reset
1
Data transfer ends by the specified count
Bit 0—DMAC Enable (DE): DE enables channel operation.
Bit 0: DE
Description
0
Disables channel operation
1
Enables channel operation
(Initial value)
If the auto request is specified in RS3 to RS0, transfer starts when this bit is set to 1. For an
external request or an on-chip module request, transfer starts if a transfer request is generated after
this bit is set to 1. Clearing this bit during transfer can terminate transfer.
Even if the DE bit is set, transfer is not enabled when the TE bit is 1, the DME bit in DMAOR is
0, or the NMIF bit or AE bit in DMAOR is 1.
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Section 14 Direct Memory Access Controller (DMAC)
14.2.5
DMA Channel Request Assign Register (CHRAR )
The DMA channel request assign register (CHRAR) is a 16-bit read/write registers that assign
requests from USBF or SIOF to each DMA channel, to each expanded DMA. It is initialized to 0
at power-on reset, or in hardware standby mode or software standby mode. These register values
are initialized to 0s after a power-on reset. The previous value is held in standby mode.
Bit:
15,14,13,12
11,10,9,8
CH3RID3 to CH0RID0
CH2RID3 to CH2RID0
0
0
R/W
R/W
Initial value:
R/W:
Bit:
7,6,5,4
3,2,1,0
CH1RID3 to CH1RID0
CH0RID3 to CH0RID0
0
0
R/W
R/W
Initial value:
R/W:
Bits 15 to 12 —DMA Channel 3 Request Assign 3 to 0 (CH3RID3 to CH3RID0): These bits
select DMA requests from DMA channel 3.
Bits 15 to 12:
CH3RID3 to CH3RID0
Description
0000
Unused
0001
USBF (USB function) reception requests to the DMA are selected from
channel 3
0010
USBF (USB function) transmission requests to the DMA are selected
from channel 3
1001
SIOF reception requests to the DMA are selected from channel 3
1010
SIOF transmission requests to the DMA are selected from channel 3
Rev. 5.00 Dec 12, 2005 page 394 of 1034
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(Initial value)
Section 14 Direct Memory Access Controller (DMAC)
Bits 11 to 8 — DMA Channel 2 Request Assign 3 to 0 (CH2RID3 to CH2RID0): These bits
select DMA requests from DMA channel 2.
Bits 11 to 8:
CH2RID3 to CH2RID0
Description
0000
Unused
0001
USBF (USB function) reception requests to the DMA are selected from
channel 2
0010
USBF (USB function) transmission requests to the DMA are selected
from channel 2
1001
SIOF reception requests to the DMA are selected from channel 2
1010
SIOF transmission requests to the DMA are selected from channel 2
(Initial value)
Bits 7 to 4— DMA Channel 1 Request Assign 3 to 0 (CH1RID3 to CH1RID0): These bits
select DMA requests from DMA channel 1.
Bits 7 to 4:
CH1RID3 to CH1RID0
Description
0000
Unused
0001
USBF (USB function) reception requests to the DMA are selected from
channel 1
0010
USBF (USB function) transmission requests to the DMA are selected
from channel 1
1001
SIOF reception requests to the DMA are selected from channel 1
1010
SIOF transmission requests to the DMA are selected from channel 1
(Initial value)
Bits 3 to 0— DMA Channel 0 Request Assign 3 to 0 (CH0RID3 to CH0RID0): These bits
select DMA requests from DMA channel 0.
Bits 3 to 0:
CH0RID3 to CH0RID0
Description
0000
Unused
0001
USBF (USB function) reception requests to the DMA are selected from
channel 0
0010
USBF (USB function) transmission requests to the DMA are selected
from channel 0
1001
SIOF reception requests to the DMA are selected from channel 0
1010
SIOF transmission requests to the DMA are selected from channel 0
(Initial value)
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Section 14 Direct Memory Access Controller (DMAC)
14.2.6
DMA Operation Register (DMAOR)
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
PR1
PR0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
AE
NMIF
DME
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R/(W)*
R/(W)*
R/W
Note: * Only a write of 0 after a read of 1 is enabled for the AE and NMIF bits.
The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMAC
transfer mode.
This register is initialized to 0 by a power-on reset. The previous values are held in standby mode.
Bits 15 to 10—Reserved: These bits are always read as 0 and should only be written with 0.
Bits 9 and 8—Priority Mode 1, 0 (PR1 and PR0): PR1 and PR0 select the priority level between
channels when transfer requests are generated for multiple channels simultaneously.
Bit 9: PR1
Bit 8: PR0
Description
0
0
CH0 > CH1 > CH2 > CH3
1
CH0 > CH2 > CH3 > CH1
1
0
CH2 > CH0 > CH1 > CH3
1
Round-robin
(Initial value)
Bits 7 to 3—Reserved: These bits are always read as 0 and should only be written with 0.
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Section 14 Direct Memory Access Controller (DMAC)
Bit 2—Address Error Flag (AE): AE indicates that an address error occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended. The CPU
cannot write 1 to this bit. This bit can only be cleared by writing of 0 after reading of 1.
Bit 2: AE
Description
0
No DMAC address error. DMA transfer is enabled.
(Initial value)
Clear conditions: When this bit is written with 0 after it is read as 1
By a power-on reset
By a manual reset
1
DMAC address error. DMA transfer is disabled.
Setting condition: When a DMAC address error occurred
Bit 1—NMI Flag (NMIF): NMIF indicates that an NMI interrupt occurred. This bit is set both in
operating state and in halt state. The CPU cannot write 1 to this bit. This bit can only be cleared
by writing of 0 after reading of 1.
Bit 1: NMIF
Description
0
No NMI input. DMA transfer is enabled.
(Initial value)
Clear conditions: When this bit is written with 0 after it is read as 1
By a power-on reset
By a manual reset
1
NMI input. DMA transfer is disabled.
Setting condition: When an NMI interrupt is generated
Bit 0—DMA Master Enable (DME): DME enables or disables DMA transfer for all channels. If
the DME bit and the DE bit corresponding to each channel in CHCR are set to 1, transfer is
enabled in the corresponding channel. If this bit is cleared during transfer, transfer in all the
channels can be terminated.
Even if the DME bit is set, transfer is not enabled when the TE bit is 1 or the DE bit is 0 in CHCR,
or the NMIF bit is 1 in DMAOR.
Bit 0: DME
Description
0
Disable DMA transfer for all channels
1
Enable DMA transfer for all channels
(Initial value)
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Section 14 Direct Memory Access Controller (DMAC)
14.3
Operation
When a DMA transfer request is generated, the DMAC starts the transfer according to the
predetermined channel priority order. When a transfer end condition is satisfied, it ends the
transfer. Three types of transfer requests can be, auto request, external request, and on-chip
module request. For the dual address mode, the direct address transfer mode and indirect address
transfer mode are supported. For the bus mode, the burst mode or the cycle steal mode can be
selected.
14.3.1
DMA Transfer Flow
When transfer conditions have been set to the DMA source address registers (SAR), DMA
destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel
control registers (CHCR), and DMA operation register (DMAOR), the DMAC transfers data
according to the following procedure:
1. Checks that transfer is enabled (DE = 1, DME = 1, AE = 0, TE = 0, NMIF = 0)
2. When transfer is enabled and a transfer request is generated, the DMAC transfers 1 transfer
unit of data (set with the TS0 and TS1 bits). In auto request mode, the transfer operation begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented on each transfer. The actual transfer flows vary according to the address mode
and bus mode.
3. When the specified number of transfers have been completed (when DMATCR reaches 0), the
transfer operation ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt
is sent to the CPU.
4. When an NMI interrupt is generated, the transfer operation is aborted. The transfer operation is
also aborted when the DE bit in CHCR or the DME bit in DMAOR is changed to 0.
Figure 14.2 shows a flowchart of this procedure.
Rev. 5.00 Dec 12, 2005 page 398 of 1034
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Section 14 Direct Memory Access Controller (DMAC)
Start
Initial settings
(SAR, DAR, DMATCR, CHCR, DMAOR)
DE, DME = 1 and
AE, NMIF, TE = 0?
No
Yes
Transfer request
occurs?*1
No
*2
*3
Yes
Transfer (1 transfer unit);
DMATCRD1 → DMATCR, SAR and DAR
updated
DMATCR = 0?
No
Yes
DEI interrupt request (when IE = 1)
Does
AE = 1 or NMIF = 1 or
DE = 0 or DME
= 0?
Yes
Transfer end
Bus mode,
transfer request mode,
DREQ detection selection
system
Does
AE = 1 or NMIF = 1 or
DE = 0 or DME
= 0?
Yes
No
Transfer aborted
No
Normal end
Notes: 1. In auto-request mode, transfer begins when AE, NMIF and TE are all 0 and the DE and
DME bits are set to 1.
2. DREQ = level detection in burst mode (external request) or cycle-steal mode.
3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst
mode.
Figure 14.2 DMAC Transfer Flowchart
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Section 14 Direct Memory Access Controller (DMAC)
14.3.2
DMA Transfer Requests
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by devices and on-chip supporting modules that are neither the source
nor the destination. There are three types of transfer requests, an auto request, an external request
and an on-chip module request. The request mode is selected with the RS3 to RS0 bits in the
DMA channel control registers 0 to 3 (CHCR0 to CHCR3).
Auto-Request Mode: When no transfer request signal is input from an external source, such as
transfer between memories or between memory and an on-chip supporting module on which a
transfer request is disabled, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bits in CHCR0 to CHCR3 and the DME bit in
DMAOR are set to 1, a transfer is started. At this time, the TE bits in CHCR0 to CHCR3 and the
NMIF bit in DMAOR should be all 0.
External Request Mode: A transfer is started by the transfer request signal (DREQ) from an
external device. Choose one of the modes shown in table 14.3 according to the application system.
If DREQ is input when the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0), a
DMA transfer starts. Select whether DREQ is detected on the falling edge or low level with the
DS bit in CHCR0 (level detection when DS = 0, edge detection when DS = 1).
The source of the transfer request does not have to be the data transfer source or destination.
Table 14.3 Selecting External Request Modes with the RS Bits
RS3
RS2
RS1
RS0
Address Mode
Source
Destination
0
0
0
0
Dual address
mode
Arbitrary*
Arbitrary*
1
0
Single address
mode
External memory,
memory-mapped
external device
External device with
DACK
External device with
DACK
External memory,
memory-mapped
external device
1
Note: * External memory, memory-mapped external device, on-chip memory, on-chip supporting
module (excluding DMAC, UBC, and BSC)
On-Chip Module Request Mode: A transfer is started by the transfer request signal (interrupt
request signal) from an on-chip supporting module. This mode cannot be set in case of 16-byte
transfer. There are eight types of transfer request signals, a receive data full interrupt (RXI) and a
transmit data empty interrupt (TXI) from the serial communication interface (SCIF), an A/D
conversion end interrupt (ADI) from the A/D converter, an compare-match timer interrupt (CMI)
Rev. 5.00 Dec 12, 2005 page 400 of 1034
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Section 14 Direct Memory Access Controller (DMAC)
from CMT, a transmit request (TDREQ) and a receive request (RDREQ) from SIOR, and a
transmit request (DREQN1) and a receive request (DREQN0) from USBF. TDREQ, RDREQ,
DREQN1, and DREQN0 are supported for expansion.
When the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, and NMIF = 0) in this mode, a
transfer is started by the transfer request signal input. The source of the transfer request does not
have to be the data transfer source or destination.
When RXI2 is set as a transfer request, however, the transfer source must be the SCIF's receive
data register (RDR2). Likewise, when TXI2 is set as a transfer request, the transfer source must be
the SCIF's transmit data register (TDR2). In addition, when the transfer requester is the A/D
converter, the data transfer source must be the A/D data register (ADDR).
Table 14.4 Selection of On-Chip Module Request Modes Using RS3 to RS0 Bits
RS3
RS2
RS1
RS0
1
0
0
0
1
DMA Transfer Request
Source
DMA Transfer
Request Signal
Source
Destination Bus Mode
Expansion USBF
receiver
DREQN[0]
(DMA transfer
request output)
EPDR1
Arbitrary*
USBF
transmitter
DREQN[1]
(DMA transfer
request output)
Arbitrary* EPDR2
Cycle steal
SIOF
receiver
RDREQ
(receive-data
transfer request)
SIRDR
Cycle steal
SIOF
transmitter
TDRQ
(transmit-data
transfer request)
Arbitrary* SITDR
Arbitrary*
Cycle steal
Cycle steal
0
0
SCIF transmitter
TXI2
Arbitrary* TDR2
(SCIF transmit data
empty interrupt)
Cycle steal
0
1
SCIF receiver
RXI2
(SCIF receive data
full interrupt)
RDR2
Arbitrary*
Cycle steal
1
0
A/D converter
ADI
(A/D conversion
end interrupt)
ADDR
Arbitrary*
Cycle steal
1
1
CMT
CMI
(Compare-match
timer interrupt)
Arbitrary* Arbitrary*
Burst/
cycle steal
Note: * External memory, memory-mapped external device, on-chip supporting module (excluding
DMAC, BSC, UBC)
Rev. 5.00 Dec 12, 2005 page 401 of 1034
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Section 14 Direct Memory Access Controller (DMAC)
In order to output a transfer request from an on-chip supporting module, set the corresponding
interrupt enable bit for outputting the interrupt signal.
When the interrupt request signal from an on-chip supporting module is used as a DMA transfer
request signal, an interrupt is not generated to the CPU.
The DMA transfer request signals shown in table 14.4 are automatically canceled when the
corresponding DMA transfer is completed. This operation is provided at the first transfer in cycle
steal mode, and at the last transfer in burst mode.
14.3.3
Channel Priority
When the DMAC receives multiple transfer requests simultaneously, it provides transfer operation
according to a specified priority order. The fixed mode or round-robin mode can be selected for
the channel priority with the PR1 and PR0 bit in the DMA operation register (DMAOR).
Fixed Mode: The channel priority is fixed. There are three kinds of orders as follows:
CH0 > CH1 > CH2 > CH3
CH0 > CH2 > CH3 > CH1
CH2 > CH0 > CH1 > CH3
The priority is selected by the PR1 and PR0 bits in the DMA operation register (DMAOR).
Round-Robin Mode: The priority order is rotated each time one transfer unit (word, byte, or
longword) of data has been transferred. The channel on which the transfer was just finished is
located at the lowest in priority. The round-robin mode operation is shown in figure 14.3. The
priority of the round-robin mode is CH0 > CH1 > CH2 > CH3 immediately after a reset.
Rev. 5.00 Dec 12, 2005 page 402 of 1034
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Section 14 Direct Memory Access Controller (DMAC)
(1) When channel 0 transfers
Initial priority order
Channel 0 becomes bottom
priority
CH0 > CH1 > CH2 > CH3
Priority order
afrer transfer
CH1 > CH2 > CH3 > CH0
(2) When channel 1 transfers
Initial priority order
Priority order
afrer transfer
Channel 0 becomes bottom
priority.
The priority of channel 0, which
was higher than channel 3, is also
shifted.
CH0 > CH1 > CH2 > CH3
CH2 > CH3 > CH0 > CH1
(3) When channel 2 transfers
Channel 2 becomes bottom
priority.
The priority of channels 0 and 1,
which were higher than channel 2,
are also shifted. If immediately
Priority order
CH3 > CH0 > CH1 > CH2 after there is a request to transfer
afrer transfer
channel 1 only, channel 1 becomes
bottom priority and the priority of
channels 0 and 3, which were
Post-transfer priority order
higher than channel 1, are also
when there is an
CH2 > CH3 > CH0 > CH1 shifted.
immediate transfer
request to channel 1 only
Initial priority order
CH0 > CH1 > CH2 > CH3
(4) When channel 3 transfers
Priority order
afrer transfer
CH0 > CH1 > CH2 > CH3
Priority order
afrer transfer
CH0 > CH1 > CH2 > CH3
Initial priority order
Figure 14.3 Operation in Round-Robin Mode
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Section 14 Direct Memory Access Controller (DMAC)
Figure 14.4 shows how the priority order changes when transfer requests for channel 0 and
channel 3 are generated simultaneously and a transfer request for channel 1 is requested during the
channel 0 transfer. The DMAC operates as follows:
1. Transfer requests are generated simultaneously for channels 0 and 3.
2. Channel 0 has the higher priority, so the channel 0 transfer begins first (channel 3 waits for
transfer).
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
waiting)
4. When the channel 0 transfer ends, channel 0 has the lowest priority.
5. At this time, channel 1 has the higher priority than channel 3, so the channel 1 transfer begins
(channel 3 waits for transfer).
6. When the channel 1 transfer ends, channel 1 has the lowest priority.
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority order so that
channel 3 has the lowest priority.
Transfer request
Waiting channel(s) DMAC operation
Channel priority
(1) Channels 0 and 3
(3) Channel 1
3
1,3
0>1>2>3
(2) Channel 0 transfer
start
(4) Channel 0 transfer
ends
Priority order
changes
1>2>3>0
(5) Channel 1 transfer
starts
3
(6) Channel 1 transfer
ends
(7) Channel 3 transfer
starts
None
(8) Channel 3 transfer
ends
Priority order
changes
Priority order
changes
2>3>0>1
0>1>2>3
Figure 14.4 Channel Priority Order in Round-Robin Mode
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Section 14 Direct Memory Access Controller (DMAC)
14.3.4
DMA Transfer Types
The DMAC supports the transfers shown in table 14.5. The dual address mode comprises the
direct address mode and indirect address mode. In the direct address mode, an output address
value is the data transfer target address. In the indirect address mode, the value stored in the output
address, not the output address value itself, is the data transfer target address. The data transfer
timing differs depending on the bus mode. The bus mode comprises the cycle steal mode and burst
mode.
Table 14.5 DMA Transfers
Destination
Source
External
Device with
DACK
External
Memory
MemoryMapped
External
Device
On-Chip
Supporting
Module
XY Memory
External device with
DACK
Not available Dual, single
Dual, single
Not available Not available
External memory
Dual, single
Dual
Dual
Dual
Dual
Memory-mapped
external device
Dual, single
Dual
Dual
Dual
Dual
On-chip supporting
module
Not available Dual
Dual
Dual
Dual
X/Y memory
Not available Dual
Dual
Dual
Dual
Notes: 1. Dual: Dual address mode
2. Single: Single address mode
3. The dual address mode includes the direct address mode and the indirect address
mode.
4. 16-byte transfer is not available for on-chip supporting modules.
Address Mode:
• Dual Address Mode
In the dual address mode, the transfer source and destination are accessed by addresses. Both
external and internal addresses can be used for the transfer source or destination. The dual address
mode consists of the direct address transfer mode (1) and indirect address transfer mode (2).
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Section 14 Direct Memory Access Controller (DMAC)
(1) Direct address transfer mode
DMA transfer requires two bus cycles because data is read from the transfer source in a data
read cycle and written to the transfer destination in a data write cycle. At this time, transfer
data is temporarily stored in the DMAC. In the transfer between external memories as shown
in figure 14.5, data is read from one external memory to the DMAC in a data read cycle, and
then that data is written to the other external memory in a write cycle. Figures 14.6 to 14.8
show examples of this operation timing
DMAC
SAR
Data bus
Address bus
DAR
Memory
Transfer source
module
Transfer destination
module
Data buffer
Data is read from the transfer source module using the SAR value as
the address, and the read data is stored in the DMAC temporarily.
First bus cycle
DMAC
SAR
Data bus
Address bus
DAR
Memory
Transfer source
module
Transfer destination
module
Data buffer
The value stored in the DMAC is written to the transfer destination
module using the DAR value as the address.
Second bus cycle
Figure 14.5 Operation in Direct Address Mode
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Section 14 Direct Memory Access Controller (DMAC)
CKIO
A25 to A0
Transfer source
address
Transfer destination
address
CSn
D31 to D0
RD
WEn
DACKn
Data read cycle
Data write cycle
(1st cycle)
(2nd cycle)
Note: When DACK is output in a read cycle during transfer between external memories,
the output timing is the same as that of CSn.
Figure 14.6 Example of DMA Transfer Timing in the Direct Address Mode
(Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)
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Section 14 Direct Memory Access Controller (DMAC)
CKIO
A25 to A0
Transfer
+4
source address
+8
+12
Transfer
+4
destination address
+8
+12
CSn
D31 to D0
RD
WEm
DACK
Data read cycle
(1st cycle)
(2nd cycle)
Note: When DACK is output in a read cycle during transfer between external memories,
the output timing is the same as that of CSn.
Figure 14.7 Example of DMA Transfer Timing in the Direct Address Mode
(16-byte Transfer, Transfer Source: Ordinary Memory, Transfer Destination: Ordinary
Memory)
CKIO
A25 to A0
Transfer source address
Transfer destination address
+4
+8
+12
CSn
D31 to D0
RAS
CAS
RD/WR
DACK
Data read cycle
(1st cycle)
Data write cycle
(2nd cycle)
Note: When DACK is output in a read cycle during transfer between external memories,
the output timing is the same as that of CSn.
Figure 14.8 Example of DMA Transfer Timing in the Direct Address Mode
(16-byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination: Ordinary
Memory)
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Section 14 Direct Memory Access Controller (DMAC)
(2) In the indirect address transfer mode
The address of the memory in which data to be transferred is stored is specified in the transfer
source address register (SAR3) in the DMAC. 16-byte transfer is not provided in this mode.
The address value specified in the transfer source address register in the DMAC is read first,
and this value is temporarily stored in the DMAC. Next, the read value is output as an address,
and data on that address is stored in in the DMAC again. Then, the value read afterwards is
written to the address specified by the transfer destination address register; thus one DMA
transfer is completed.
Figure 14.9 shows an example of this operation. In this example, the transfer destination,
transfer source, and storage destination of the indirect address are all in external memories, and
the transfer data size is 16 or 8 bits. Figure 14.10 shows an example of the transfer timing.
In this mode, one NOP cycle (CK1 cycle shown in figure 14.10) is required to output data
which was read as an indirect address to an address bus.
For a 32-bit data transfer, third and fourth bus cycles shown in figure 14.10 are required twice
for each; a total of six bus cycles and one NOP cycle are required.
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Section 14 Direct Memory Access Controller (DMAC)
DAR3
Temporary
buffer
Memory
Data bus
D
M
A
C
Address bus
SAR3
Transfer source module
Transfer destination
module
Data
buffer
Data is read from memory using the SAR3 value as the data address, and the read
data is stored in the temporary buffer. The read data must be a 32-bit value because it
is used as an address.
Two bus cycles are required if a 16-bit data bus is used to connect to an external
device.
First and second bus cycles
SAR3
Temporary
buffer
Data bus
DAR3
Address bus
D
M
A
C
Memory
Transfer source module
Transfer destination
module
Data
buffer
Data is read from the source module using the temporary buffer value as the address,
and the read data is transferred to the data buffer.
Third bus cycle
SAR3
Temporary
buffer
Data bus
DAR3
Address bus
D
M
A
C
Memory
Transfer source module
Transfer destination
module
Data
buffer
The data buffer value is written to the destination module using the DAR3 value as the
destination address.
Fourth bus cycle
Note: The above description uses the memory, transfer source module, or transfer
destination module; in practice, any module can be connected in the addressing
space.
Figure 14.9 Operation in Indirect Address Mode
(When the External Memory Space is Set to 16-bit Width)
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Section 14 Direct Memory Access Controller (DMAC)
CK
A25 to A0
Transfer source
address (H)
Transfer source
address (L)
NOP
Transfer destination address
Indirect address
CSn
D31 to D0
Internal
address bus
Indirect
address (H)
Indirect
address (L)
Transfer source
address*1
Internal data
bus
Indirect
address
NOP
Transfer source
address*2
DMAC indirect
address buffer
Transfer
data
Transfer
data
Transfer data
Transfer
data
Indirect address
DMAC data
buffer
Transfer data
RD
WEn
Address read cycle
(1st)
(2nd)
NOP
cycle
Data
read cycle
(3rd)
Data
write cycle
(4th)
Notes: 1. The internal address bus value does not change, and controlled by the port.
2. The DMAC does not fetch the value until 32-bit data is output to the internal
data bus.
Transfer between external memories (external memories is 16-bit bus width)
Figure 14.10 Example of Transfer Timing in Indirect Address Mode
(Transfer between External Memories, External Memory with 16-bit Width)
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Section 14 Direct Memory Access Controller (DMAC)
• Single Address Mode
The single address mode is used when transfer is performed between external devices including
external memories, one of which is accessed (selected) by the DACK signal and the other of
which is accessed by address. In this mode, the DMAC outputs the transfer request acknowledge
signal DACK to one external device, and simultaneously outputs an address to the other device;
thus DMA transfer is performed in one bus cycle. An example of transfer between an external
memory and an external device with DACK is shown in figure 14.11. The external device outputs
data to a data bus and the data is written to the external memory in a single bus cycle.
External address bus
External data bus
SH7727
External
memory
DMAC
External device
with DACK
DACK
DREQ
Data flow
Figure 14.11 Data Flow in Single Address Mode
Two kinds of transfer are possible in single address mode: (1) transfer between an external device
with DACK and a memory-mapped external device, and (2) transfer between an external device
with DACK and an external memory. In both cases, only the external request signal (DREQ) is
used as a transfer request.
Figures 14.12 and 14.13 show examples of the DMA transfer timing in single address mode.
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Section 14 Direct Memory Access Controller (DMAC)
CK
Address output to external memory space
A25 to A0
CSn
WE
Write strobe signal to external memory space
D31 to D0
Data output from external device with DACK
DACKn
DACK signal (active-low) to external device with DACK
BS
(a) External device with DACK
external memory space (ordinary memory)
CK
Address output to external memory space
A25 to A0
CSn
RD
Read strobe signal to external memory space
Data output from external memory space
D31 to D0
DACKn
DACK signal (active-low) to external device with DACK
BS
(b) External memory space
external device with DACK (active-low)
Figure 14.12 Example of DMA Transfer Timing in Single Address Mode
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Section 14 Direct Memory Access Controller (DMAC)
CKIO
A25 to A0
Transfer
source address
+4
+8
+12
CSn
D31 to D0
RD
WEn
DACKn
Figure 14.13 Example of DMA Transfer Timing in Single Address Mode
(External Memory Space (Ordinary Memory) → External Device with DACK)
Bus Modes: There are two types of bus modes, cycle steal mode and burst mode. Select the mode
in the TM bits in CHCR0 to CHCR3.
• Cycle-Steal Mode
In the cycle-steal mode, the bus right is moved to another bus master after one transfer unit (byte,
word, longword, or 16-byte unit) of DMA transfer. If another transfer request occurs after the bus
right moving, the bus right are re-moved to the DMAC. Then, the DMAC performs transfer for
one transfer unit and releases the bus right again. This operation is repeated until the transfer end
condition is satisfied.
In the cycle-steal mode, transfer areas are not affected by settings of the transfer request source,
transfer source, and transfer destination. Figure 14.14 shows an example of the DMA transfer
timing in the cycle steal mode. In this example, the following conditions are set:
•
•
Dual address mode
DREQ level detection
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Section 14 Direct Memory Access Controller (DMAC)
DREQ
Bus right returned to CPU
Bus cycle
CPU
CPU
CPU
DMAC DMAC
Read
CPU
Write
DMAC DMAC CPU
Read
CPU
Write
Figure 14.14 Transfer Example in Cycle-Steal Mode
• Burst Mode
Once the DMAC obtains the bus right, the transfer is continued until the transfer end condition is
satisfied. However, when the DREQ pin is driven high in the external request mode with low level
detection of the DREQ pin, the bus right is passed to the other bus master after the DMA transfer
request that has already been accepted ends, even if the transfer end condition has not been
satisfied.
The burst mode cannot be used when the transfer request source is set to the serial
communications interface with FIFO (SCIF). Figure 14.15 shows a timing of the DMA transfer
operation in the burst mode.
DREQ
Bus cycle
CPU
CPU
CPU
DMAC DMAC DMAC DMAC DMAC DMAC
Read
Write
Read
Write
Read
CPU
Write
Figure 14.15 Example of Transfer in Burst Mode
Relationship between Request Mode and Bus Mode: Table 14.6 shows the relationship between
request mode and bus mode for each combination of DMA transfer areas.
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Section 14 Direct Memory Access Controller (DMAC)
Table 14.6 Relationship of Request Modes and Bus Modes
Address
Mode
Transfer Areas
Request
Mode
Bus
Mode
Transfer
Size (bits)
Usable
Channels
Dual
External device with DACK and
external memory
External
B/C
8/16/32/128
0
External device with DACK and
memory-mapped external device
External
B/C
8/16/32/128
0
External memory and external
memory
All*
B/C
8/16/32/128
0–3*
External memory and memorymapped external device
All*
B/C
8/16/32/128
0–3*
Memory-mapped external device and
memory-mapped external device
All*
B/C
8/16/32/128
0–3*
External memory and on-chip
supporting module
All*
B/C*
8/16/32*
0–3*
Memory-mapped external device and
on-chip supporting module
All*
B/C*
8/16/32*
0–3*
On-chip supporting module and onchip supporting module
All*
B/C*
8/16/32*
0–3*
X/Y memory and X/Y memory
All
B/C
8/16/32/128
0–3
X/Y memory and memory-mapped
external device
1
All*
B/C
8/16/32/128
0–3
X/Y memory and on-chip supporting
module
All*
B/C*
8/16/32
0–3
X/Y memory and external memory
All
B/C
8/16/32/128
0–3
External device with DACK and
external memory
External
B/C
8/16/32/128
0
External device with DACK and
memory-mapped external device
External
B/C
8/16/32/128
0
Single
1
1
1
2
2
2
2
3
3
3
3
4
4
4
5
5
5
5
5
5
B: Burst
C: Cycle steal
Notes: 1. External requests, auto requests and on-chip supporting module (CMT) requests are all
available.
2. External requests, auto requests and on-chip supporting module requests are all
available. When the SIOF, USBF, SCIF, or A/D converter is the transfer request source,
the transfer destination or transfer source must be also the SIOF, USBF, SCIF, or A/D
converter, respectively.
3. The SIOF, USBF, SCIF, or A/D converter can be specified for the transfer request
source in the cycle-steal mode only.
4. The access size permitted when the transfer destination or source is an on-chip
supporting module register.
5. If the transfer request is an external request, only channel 0 is available.
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Section 14 Direct Memory Access Controller (DMAC)
Bus Mode and Channel Priority Order: For example, when channel 1 provides transfer
operation in burst mode and then a transfer request to channel 0 with the higher priority is
generated, the transfer of channel 0 will begin immediately.
At this time, if the priority is set in the fixed mode (CH0 > CH1), the channel 1 transfer will be
continued after the channel 0 transfer has completely finished, even if channel 0 is set to the cycle
steal mode or burst mode.
If the round-robin mode is selected, channel 1 will begin operating again after channel 0 completes
the transfer of one transfer unit, even if channel 0 is set to the cycle steal mode or burst mode. The
bus is moved between the two in the order channel 1, channel 0, channel 1, channel 0.
Even if the fixed mode or in the round-robin mode is selected, the bus is not passed to the CPU
since channel 1 is in the burst mode. Figure 14.16 shows an example of operation in the roundrobin mode.
CPU
CPU
DMAC
CH1
DMAC
CH1
DMAC CH1
Burst mode
DMAC
CH0
DMAC
CH1
DMAC
CH0
CH0
CH1
CH0
Round-robin mode in
DMAC CH0 and CH1
DMAC
CH1
DMAC
CH1
DMAC CH1
Burst mode
CPU
CPU
Priority: Round-robin mode
CH0: Cycle-steal mode
CH1: Burst mode
Figure 14.16 Bus State in Multiple Channel Operation
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Section 14 Direct Memory Access Controller (DMAC)
14.3.5
Number of Bus Cycle States and DREQ Pin Sampling Timing
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states
is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
For details, see section 12, Bus State Controller (BSC).
DREQ Pin Sampling Timing: In external request mode, the DREQ pin is sampled with the clock
pulse (CKIO) falling edge detection or low level detection. When a DREQ input is detected, a
DMAC bus cycle is generated and DMA transfer starts three or more states later.
The second and subsequent DREQ sampling operations are started two cycles after the first
sample.
Operation
• Cycle-Steal Mode
In cycle-steal mode, the DREQ sampling timing does not change according to the DREQ
detection method, the level detection or edge detection.
For example, as shown in figure 14.17 (cycle-steal mode, level detection), DMA transfer
begins, at the earliest, three cycles after the first sampling is performed. The second sampling
is started two cycles after the first. If DREQ is not detected at this time, sampling is performed
in each subsequent cycle.
Thus, DREQ sampling is performed one step in advance. The third sampling operation is not
performed until the idle cycle following the end of the first DMA transfer.
The above operation is performed continuously for the desired CPU transfer cycles or DMA
transfer cycles, as shown in figures 14.18 and 14.19.
Figures 14.17 and 14.18 show examples in which DACK is output in a read and in a write,
respectively. In both cases, DACK is output for the same period as CSn.
Figure 14.20 shows an example in which sampling is executed in all subsequent cycles when
DREQ cannot be detected. Figure 14.21 shows an example of operation in cycle steal mode
with the edge detection.
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Section 14 Direct Memory Access Controller (DMAC)
• Burst Mode, Level Detection
In the case of burst mode with level detection, the DREQ sampling timing is the same as in the
cycle-steal mode.
For example, as shown in figure 14.22, DMAC transfer begins, at the earliest, three cycles
after the first sampling is performed. The second sampling is started two cycles after the first.
Subsequent sampling operations are performed in the idle cycle following the end of the DMA
transfer cycle.
In the burst mode, also, the DACK output period is the same as that in the cycle-steal mode.
• Burst Mode, Edge Detection
In the case of burst mode with edge detection, DREQ sampling is performed only once.
For example, as shown in figure 14.23, DMAC transfer begins, at the earliest, three cycles
after the first sampling is performed. After this, DMAC transfer is executed continuously until
the number of data transfers set in the DMATCR register have been completed. DREQ is not
sampled during this operation.
To restart DMA transfer after it has been suspended by an NMI, first clear NMIF, then input
an edge request again.
In the burst mode, also, the DACK output period is the same as that in the cycle-steal mode.
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DACK
Bus cycle
DRAK
DREQ
CKIO
1st sampling
CPU
2nd sampling
DMAC(R)
DMAC(W)
3rd sampling
CPU
DMAC(R)
DMAC(W)
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles)
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DACK
Bus cycle
DRAK
DREQ
CKIO
1st sampling
CPU
2nd sampling
DMAC(R)
DMAC(W)
3rd sampling
CPU
DMAC(R)
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles)
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DACK
(RD output)
Bus cycle
DRAK
(High output)
DREQ
CKIO
CPU
1st sampling
2nd sampling
DMAC(R)
DMAC(W)
3rd sampling
CPU
DMAC(W)
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access:
4 Cycles)
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DACK
(RD output)
Bus cycle
DRAK
DREQ
CKIO
CPU
1st sampling
DMAC(R)
2nd sampling
2nd sampling is performed,
but since DREQ is high,
per-cycle sampling starts
DMAC(W)
CPU
3rd sampling is performed,
but since DREQ is high,
per-cycle sampling starts
DMAC(R)
3rd sampling
DMAC(W)
CPU
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed)
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CPU
DMAC(R)
High
High
DMAC(W)
2nd sampling
CPU
DMAC(R)
High
2nd sampling is performed,
but since there is no DREQ falling edge,
per-cycle sampling starts
Note: When a DREQ falling edge is detected, DREQ must be high for at least one cycle before the sampling point.
DACK
(RD output)
Bus cycle
DRAK
DREQ
CKIO
1st sampling
3rd sampling is performed,
but since there is no DREQ falling edge,
per-cycle sampling starts
High
DMAC(W)
3rd sampling
CPU
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles)
DACK
Bus cycle
DRAK
DREQ
CKIO
CPU
1st sampling
2nd sampling
DMAC(R)
DMAC(W)
3rd sampling
DMAC(R)
DMAC(W)
DMAC(R)
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.22 Burst Mode, Level Input
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DACK
Bus cycle
DRAK
DREQ
CKIO
CPU
1st sampling
DMAC(R)
DMAC(W)
DMAC(R)
DMAC(W)
DMAC(R)
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.23 Burst Mode, Edge Input
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Section 14 Direct Memory Access Controller (DMAC)
14.3.6
Source Address Reload Function
Channel 2 includes a reload function, in which the value set in the source address register (SAR2)
is restored every four transfers when the RO bit in CHCR2 is set to 1. This function cannot be
used with the 16-byte transfer. Figure 14.24 shows this operation. Figure 14.25 shows a timing
chart of the source address reload function with the following conditions: burst mode, auto
request, 16-bit transfer data size, SAR2 count-up, DAR2 fixed, reload function on, and usage of
only channel 2.
DMAC
DMAC control
Count signal
Transfer
request
Reload control
Reload signal
Reload
signal
4 time
count
CHCR2
DMATCR2
SAR2
(initial value)
Address bus
RO bit = 1
SAR2
Figure 14.24 Source Address Reload Function Diagram
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Section 14 Direct Memory Access Controller (DMAC)
CK
Internal
address bus
Internal
data bus
SAR2
DAR2
SAR2+2
SAR2 data
DAR2
SAR2+4
SAR2+2 data
DAR2
SAR2+6
SAR2+4 data
DAR2
SAR2
SAR2+6 data
First transfer of
channel 2
Second transfer
Third transfer
Fourth transfer
SAR2 output
DAR2 output
SAR2+2 output
DAR2 output
SAR2+4 output
DAR2 output
SAR2+6 output
DAR2 output
Fifth transfer
SAR2 reload
SAR2 output
DAR2 output
Figure 14.25 Timing Chart of Source Address Reload Function
The reload function can be used for the 8-, 16- and 32-bit data transfer.
DMATCR2, which specifies a transfer count, is incremented by 1 each time a transfer ends
regardless of the reload function setting. Consequently, be sure to specify the value multiple of
four in DMATCR2 when the reload function is on. If other values are specified, correct operation
is not guaranteed.
The counters that count transfers of four times for the reload function are reset by clearing the
DME bit in DMAOR or the DE bit in CHCR2, by setting the transfer end flag (TE bit in CHCR2),
by inputting an NMI, besides by a reset or in standby mode. However, the SAR2, DAR2,
DMATCR2 registers are not reset. Therefore, the above reset source is generated, some counters
are initialized but some are not in the DMAC, which may cause a malfunction when the DMAC is
restarted. To avoid this problem, if a reset source except the TE bit setting is generated when the
reload function is used, set SAR2, DAR2, and DMATCR2 again.
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Section 14 Direct Memory Access Controller (DMAC)
14.3.7
DMA Transfer Ending
DMA transfer ending conditions to terminate transfer differ according to the ending types,
individual channel ending and all channel ending. At a transfer end, the following conditions are
applied except the case when the DMA transfer count register (DMATCR) value reaches 0.
(a) Cycle-steal mode (external request, internal request, and auto request)
When a transfer ending condition is satisfied, DMAC transfer request acceptance is suspended.
The DMAC stops operation after completing the number of transfers that has accepted before
the ending conditions are satisfied.
In the cycle-steal mode, the same operation is provided regardless of the transfer request
detection method; the level detection or the edge detection.
(b) Burst mode, edge detection (external request, internal request, and auto request)
The timing of DMAC operation ending after an ending condition is satisfied differs from that
in cycle steal mode. In the edge detection in the burst mode, though only one transfer request
is generated at the DMAC start-up, a stop request sampling is performed in the same timing as
a transfer request sampling in the cycle-steal mode. As a result, the period when a stop request
is not sampled is regarded as the period when a transfer request is generated, and after
performing the DMA transfer for this period, the DMAC stops operation.
(c) Burst mode, level detection (external request)
Same as described in (a).
(d) Bus timing when transfers are suspended
Transfer is suspended when one transfer ends. Even if a transfer ending condition is satisfied
during a read with the direct address transfer in the dual address mode, the subsequent write
process is executed, and after the transfer in (a) to (c) above has been executed, DMAC
operation suspends.
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Section 14 Direct Memory Access Controller (DMAC)
Conditions for Individual-Channel Ending: When one of the following conditions is satisfied,
transfer in the corresponding channel ends.
When the value in the DMA transfer count register (DMATCR) is 0
When the DE bit in CHCR is cleared to 0.
• When DMATCR is 0: When the DMATCR value reaches 0, the DMA transfer in the
corresponding channel ends and the transfer end flag bit (TE) in CHCR is set. If the IE
(interrupt enable) bit is set at this time, a DMAC interrupt (DEI) is requested to the CPU. The
conditions described in (a) to (d) above are not applied for this transfer ending.
• When DE in CHCR is 0: When the DE bit in CHCR is cleared, the DMA transfer in the
corresponding channel stops. The conditions described in (a) to (d) above are not applied for
this transfer ending.
Conditions for All-Channel Ending: When one of the following conditions is satisfied, transfer
in all channels end simultaneously.
When the NMIF (NMI flag) bit in DMAOR is set to 1
When the DME bit in DMAOR is cleared to 0.
• When the NMIF bit in DMAOR is set to 1: When an NMI interrupt occurs, the NMIF bit in
DMAOR is set to 1 and all channels stop their transfers according to the conditions in (a) to (d)
described above, and pass the bus right to another bus master. Consequently, even if the NMI
bit is set to 1 during transfer, the SAR, DAR, DMATCR are updated. Then the TE bit is not
set. To resume the transfer after the NMI interrupt exception handling, clear the NMIF bit to 0.
At this time, for the channels that should not be restarted, clear the corresponding DE bit in
CHCR.
• When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the DMAOR forcibly
aborts the transfers on all channels. Then the TE bit is not set. All channels abort their transfers
according to the conditions (a) to (d) described in section 14.3.7, DMAC Transfer Ending, in
the same way as that at the generation of an address error by the DMAC or NMI interrupt
generation. In this case, the values in SAR, DAR, and DMATCR are also updated.
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Section 14 Direct Memory Access Controller (DMAC)
14.4
Compare-Match Timer (CMT)
14.4.1
Overview
The DMAC has an on-chip compare-match timer (CMT) to generate DMA transfer requests. The
CMT is 16-bit counter.
Features
The CMT has the following features:
• Four types of counter input clocks can be selected
One of four internal clocks (Pφ/4, Pφ/8, Pφ/16, and Pφ/64) can be selected.
• Generates a DMA transfer request when a compare-match occurs.
Block Diagram
Figure 14.26 shows a CMT block diagram.
Pφ/4 Pφ/8 Pφ/16 Pφ/64
CMT
Clock selection
CMCNT0
Comparator
CMCOR0
CMCSR0
CMSTR
Control circuit
Bus
interface
Module bus
Internal bus
CMSTR:
CMCSR0:
CMCOR0:
CMCNT0:
Compare match timer start register
Compare match timer control/status register 0
Compare match timer constant register 0
Compare match timer counter 0
Figure 14.26 CMT Block Diagram
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Section 14 Direct Memory Access Controller (DMAC)
Register Configuration
Table 14.7 summarizes the CMT register configuration.
Table 14.7 Register Configuration
Name
Abbreviation
R/W
Initial
Value
Compare-match timer start
register
CMSTR
R/(W)
H'0000
8, 16, 32
H'04000070
2
(H'A4000070)*
Compare-match timer
control/status register 0
CMCSR0
R/(W)*
H'0000
H'04000072
8, 16, 32
2
(H'A4000072)*
Compare-match counter 0
CMCNT0
R/W
H'0000
H'04000074
8, 16, 32
2
(H'A4000074)*
Compare-match constant
register
CMCOR0
R/W
H'FFFF
H'04000076
8, 16, 32
2
(H'A4000076)*
1
Access Size
(Bits)
Address
Notes: 1. Only a 0 can be written to CMF bits in CMCSR0, to clear the flag.
2. When the address conversion by the MMU is not provided, use the address in
parentheses.
14.4.2
Register Descriptions
Compare-Match Timer Start Register (CMSTR)
The compare-match timer start register (CMSTR) is a 16-bit register that selects whether comparematch counter 0 (CMCNT0) is operated or halted. CMSTR is initialized to H'0000 by a reset, but
it retains its previous values in standby mode.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
STR0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R/W
R/W
Bits 15 to 2—Reserved: These bits are always read as 0 and should only be written with 0.
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Section 14 Direct Memory Access Controller (DMAC)
Bit 1—Reserved: This is a readable/writable bit, but the write value should be always be 0.
Bit 0—Count start 0 (STR0): Selects whether the compare-match timer counter 0 is operated or
halted.
Bit 0: STR0
Description
0
CMCNT0 count operation is halted
1
CMCNT0 count operation is provided
(Initial value)
Compare-Match Timer Control/Status Register 0 (CMCSR0)
The compare-match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates a
compare-match occurrence and sets the incrementation clock. CMCSR0 is initialized to H'0000 by
a reset, but it retains its previous values in standby mode.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
CMF
—
—
—
—
—
CKS1
CKS0
Initial value:
R/W:
0
0
0
0
0
0
0
0
R/(W)*
R/W
R
R
R
R
R/W
R/W
Note: * Only a 0 can be written, to clear the flag.
Bits 15 to 8 and 5 to 2—Reserved: These bits are always read as 0and should only be written
with 0.
Bit 7—Compare-Match Flag (CMF): This flag indicates that a compare-match of the comparematch timer counter 0 (CMCNT0) and compare-match constant register 0 (CMCOR0) occurred.
Bit 7: CMF
Description
0
CMCNT0 and CMCOR0 have not matched
(Initial value)
Clear condition: Write 0 to CMF after reading CMF = 1
1
A compare-match of CMCNT0 and CMCOR0 occurred
Bit 6—Reserved: This is a readable/writable bit, but the write value should be always be 0.
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Section 14 Direct Memory Access Controller (DMAC)
Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to CMCNT
from four clocks which are divided from the peripheral clock (Pφ). When the STR0 bit in CMSTR
is set to 1, the CMCNT0 starts incrementation with the clock selected by CKS1 and CKS0.
Bit 1: CKS1
Bit 0: CKS0
Description
0
0
Pφ/4
1
Pφ/8
0
Pφ/16
1
Pφ/64
1
(Initial value)
Compare-Match Counter 0 (CMCNT0)
The compare-match counter 0 (CMCNT0) is a 16-bit register that is used as an up-counter.
When the clock is selected with the CKS1 and CKS0 bits in CMCSR0 and the STR0 bit in
CMSTR is set to 1, CMCNT0 starts incrementation with the selected clock. When the CMCNT0
value matches that in the compare-match constant register 0 (CMCOR0), the CMCNT0 is cleared
to H'0000 and the CMF flag in CMCSR0 is set to 1.
CMCNT0 is initialized to H'0000 by a reset, but it retains its previous values in standby mode.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 14 Direct Memory Access Controller (DMAC)
Compare-Match Constant Register 0 (CMCOR0)
The compare-match constant register 0 (CMCOR0) is a 16-bit register that sets the period until a
compare-match of CMCNT0 and CMCOR0 occurs.
The CMCOR0 is initialized to H'FFFF by a reset, but it retains its previous values in standby
mode.
Bit:
15
14
13
12
11
10
9
8
Initial value:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
R/W:
14.4.3
Operation
Period Count Operation
When the clock is selected with the CKS1 and CKS0 bits in CMCSR0 and the STR0 bit in
CMSTR is set to 1, the CMCNT0 starts incrementation with the selected clock. When the
CMCNT value matches that in CMCOR0, CMCNT0 is cleared to H'0000 and the CMF flag in
CMCSR0 is set to 1. The CMCNT0 counter starts incrementation again from H'0000.
Figure 14.27 shows the compare-match counter operation.
CMCNT0 value
Counter cleared by
CMCOR0 compare match
CMCOR0
H'0000
Time
Figure 14.27 Counter Operation
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Section 14 Direct Memory Access Controller (DMAC)
CMCNT0 Count Timing
One of four peripheral clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) which are divided from the clock (Pφ)
can be selected with the CKS1 and CKS0 bits in CMCSR0. Figure 14.28 shows the timing.
Peripheral clock
(Pφ)
CMT clock
CMCNT0 input
clock
CMCNT0
N-1
N
N+1
Figure 14.28 Count Timing
14.4.4
Compare-Match
Compare-Match Flag Set Timing
When the CMCOR0 register and the CMCNT0 counter match, a compare-match signal is
generated and the CMF bit in the CMCSR0 register is set to 1. The compare-match signal is
generated upon the final state of the match (timing at which the CMCNT0 counter value is
updated). Consequently, after the CMCOR0 register and the CMCNT0 counter match, a comparematch signal will not be generated until a CMCNT0 counter input clock occurs. Figure 14.29
shows a timing of the CMF bit setting.
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Section 14 Direct Memory Access Controller (DMAC)
Peripheral clock
(Pφ)
CMCNT0
input clock
CMCNT0
N
CMCOR0
N
0
Compare
match signal
CMF
CMI
Figure 14.29 Timing of CMF Setting
Compare-Match Flag Clear Timing
The CMF bit in the CMCSR0 register is cleared by writing 0 to the bit after reading 1. Figure
14.30 shows the timing when the CMF bit is cleared by the CPU.
CMCSR0 write cycle
T2
T1
Peripheral clock
(Pφ)
CMF
Figure 14.30 Timing of CMF Clear by the CPU
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Section 14 Direct Memory Access Controller (DMAC)
14.5
Examples for Use
14.5.1
Example of DMA Transfer between A/D Converter and External Memory
(Address Reload on)
In this example, DMA transfer is performed between the on-chip A/D converter (transfer source)
and the external memory (transfer destination) with the address reload function on. Table 14.8
shows the transfer conditions and register settings.
Table 14.8 Transfer Conditions and Register Settings for Transfer between On-Chip A/D
Converter and External Memory
Transfer Conditions
Register
Setting
Transfer source: on-chip A/D converter
SAR2
H'04000080
Transfer destination: external memory
DAR2
H'00400000
Number of transfers: 128 (reloading 32 times)
DMATCR2
H'00000080
Transfer source address: incremented
CHCR2
H'00089E35
DMAOR
H'0101
Transfer destination address: decremented
Transfer request source: A/D converter
Bus mode: burst
Transfer unit: long word
Interrupt request generated at end of transfer
Channel priority order: 0 > 2 > 3 > 1
When the address reload function is turned on, the value set in SAR returns to the initially set
value at each four transfers. In this example, when an interrupt request is generated from the AD
converter, longword data is read from the register in address H'04000080 of the A/D converter,
and the data is written to external memory address H'00400000. Since longword data has been
transferred, the values in SAR and DAR are H'04000084 and H'003FFFFC, respectively. The bus
right is retained and data transfers are successively performed because this transfer is in the burst
mode.
After four transfers end, fifth and sixth transfers are performed when the address reload function is
turned off, and the value in SAR is incremented by 4, such as H'0400008C, H'04000090,
H'04000094,.... When the address reload function is on, the DMA transfer stops after the fourth
transfer ends and the bus request signal to the CPU is cleared. At this time, the value stored in
SAR is not incremented from H'0400008C to H'04000090, but returns to the initially set value
H'04000080. The value in DAR continues being incremented regardless of the address reload
function setting.
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Section 14 Direct Memory Access Controller (DMAC)
The state in the DMAC differ depending on the address reload function setting as shown in table
14.9.
Table 14.9 DMAC Sate after the Fourth Transfer Ends
Items
Address Reload On
Address Reload Off
SAR
H'04000080
H'04000090
DAR
H'003FFFFC
H'003FFFFC
DMATCR
H'0000007C
H'0000007C
Bus right
Released
Held
DMAC operation
Stops
Continues operating
Interrupt
Not generated
Not generated
Transfer request source flag
clear
Executed
Not executed
Notes: 1. When the value in DMATCR reaches 0 and the IE bit in CHCR has been set to 1,
interrupts are generated regardless of the address reload function setting.
2. When the value in DMATCR reaches 0, the transfer request source flag is cleared
regardless of the address reload function setting.
3. Specify the burst mode when using the address reload function. This function may not
be correctly executed in the cycle steal mode.
4. Set the DMATCR value to a multiple of four when using the address reload function.
This function may not be correctly executed if other values are specified.
14.5.2
Example of DMA Transfer between External Memory and SCIF Transmitter
(Indirect Address on)
In this example, DMA transfer is performed between the external memory specified with the
indirect address (transfer source) and the SCIF transmitter (transfer destination) using DMAC
channel 3. Table 14.10 shows the transfer conditions and register settings. In addition, it is
recommendable that the trigger for the number of transmit FIFO data is set to 1 (TTRG1 = TTRG0
= 1 in SCFCR).
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Section 14 Direct Memory Access Controller (DMAC)
Table 14.10 Transfer Conditions and Register Settings for Transfer between External
Memory and SCIF Transmitter
Transfer Conditions
Register
Setting
Transfer source: external memory
SAR3
H'00400000
Value stored in address H'00400000
—
H'00450000
Value stored in address H'04500000
—
H'55
Transfer destination: On-chip SCIF TDR2
DAR3
H'04000156
Number of transfers: 10
DMATCR3
H'0000000A
Transfer source address: incremented
CHCR3
H'00011C01
DMAOR
H'0001
Transfer destination address: fixed
Transfer request source: SCIF (TXI2)
Bus mode: cycle steal
Transfer unit: byte
No interrupt request generated at end of transfer
Channel priority order: 0 > 1 > 2 > 3
When the indirect address is on, data stored in the address set in SAR is not used as transfer source
data. In the indirect address, after the value stored in the address set in SAR is read, the read value
is used as an address again, and the value stored in the address is read and stored in the address set
in DAR.
In the example shown in table 14.10, when an SCIF transfer request is generated, the DMAC reads
the value in address H'00400000 that is set in SAR3. Since the value H'00450000 is stored in the
address, the DMAC reads the value H'00450000. Next, the DMAC uses the read value as an
address again, and reads the value H'55 stored in that address. Then, the DMAC writes the value
H'55 to address H'04000156 that is set in DAR3; thus one indirect address transfer has completed.
In the indirect address, when data is read first from the address set in SAR3, the data transfer size
is always longword regardless of the settings of the TS0 and the TS1 bits that specify the transfer
data size. However, whether the transfer source address is fixed, incremented, or decremented is
specified with the SM0 and SM1 bits. Therefore, in this example, though the transfer data size is
specified as byte, the value in SAR3 is H'00400004 when one transfer ends. The write operation is
the same as that in the normal dual address transfer.
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Section 14 Direct Memory Access Controller (DMAC)
14.6
Usage Notes
1. The DMA channel control registers (CHCR0 to CHCR3) can be accessed with any data size.
The DMA operation register (DMAOR) must be accessed in byte (8 bits) or word (16 bits)
units; other registers must be accessed in word (16 bits) or longword (32 bits) units.
2. When modifying the RS0 to RS3 bits in CHCR0 to CHCR3, first clear the DE bit to 0 (when
modifying CHCR with a byte address, be sure to set the DE bit to 0 in advance).
3. If an NMI interrupt is input when the DMAC is not operating, the NMIF bit of the DMAOR is
set.
4. A transition to standby mode should be made after the DME bit in DMAOR is cleared to 0 and
the transfers that has been accepted by the DMAC end.
5. The on-chip supporting modules that the DMAC can access are, SIOF, SCIF, USB function,
A/D converter, and I/O ports. Do not access the other on-chip supporting modules by the
DMAC.
6. When starting up the DMAC, set CHCR or DMAOR last. Specifying other registers last does
not guarantee normal operation.
7. When the DMA transfer ends normally and subsequently the maximum number of transfers is
performed in the same channel, write 0 to DMATCR. Otherwise, normal DMA transfer may
not be performed.
8. When using the address reload function, specify the burst mode for the transfer mode. In the
cycle-steal mode, normal DMA transfer may not be performed.
9. When using the address reload function, set a multiple of four to DMATCR. Specifying other
values does not guarantee normal operation.
10. When detecting an external request at the falling edge, keep the external request pin high when
setting the DMAC.
11. Do not access the space from H'4000062 to H'400006F, which is not used by the DMAC.
Accessing that space may cause malfunctions.
12. The WAIT signal is ignored when writing to an external address area using DMA 16-byte
transfer in dual address mode, and also when transferring data from a DACK-equipped
external device to an external address area using DMA 16-byte transfer in single address
mode.
13. Big-endian access is used when transferring data from XY memory using the DMAC if all of
the following conditions are met:
Conditions:
(1) Transfer source address in XY memory
(2) Indirect addressing mode
(3) Byte size data
(4) Little-endian data transfer
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Section 14 Direct Memory Access Controller (DMAC)
Measures to avoid the problem:
The problem described above occurs only when all of the above conditions are met. It does
not arise if even one of the conditions is not met. One of the methods listed below should
therefore be employed when using the DMAC to transfer data from XY memory:
(1) Use the direct address mode
(2) Use long word size or word size data
(3) Use big-endian data transfer
14. Do not use the DMAC when in sleep mode. Alternately, set the clock ratio to Iφ:Bφ = 1:1
when using sleep mode. Normal operation cannot be guaranteed otherwise.
15. Do not use the DMAC when only the IFC[2:0] bits in the frequency control register (FRQCR)
are modified and the clock ratio is set to other than Iφ:Bφ = 1:1. Normal operation cannot be
guaranteed otherwise. However, there is no problem if the STC[2:0] bits are modified
simultaneously with the IFC[2:0] bits in the frequency control register (FRQCR).
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Section 15 Timer (TMU)
Section 15 Timer (TMU)
15.1
Overview
This LSI has an on-chip 32-bit timer unit (TMU) comprised of three 32-bit timer channels
(channels 0 to 2).
15.1.1
Features
The TMU has the following features:
• Auto-reload 32-bit down-counters for each channel
• Auto-reload 32-bit constant registers and 32-bit down counters that can be read or written to at
any time for each channel
• Interrupt request generation at the counter underflow:
Interrupt requests can be generated when the 32-bit down counter underflows (H'00000000 →
H'FFFFFFFF) in each channel.
• Selection of six counter input clocks for each channel:
On-chip RTC output clock (16 kHz), Pφ/4, Pφ/16, Pφ/64, and Pφ/256
• All channels can operate when the SH7727 is in standby mode:
When the RTC output clock is used as the counter input clock, the count operation is normally
performed in standby mode.
• Synchronized read:
TCNT is a 32-bit register that is successively modified. Since the internal bus for the SH7727
on-chip supporting modules is 16 bits wide, a time lag can occur between the time when the
upper 16 bits and lower 16 bits are read. To correct the discrepancy in the counter read value
caused by this time lag, a synchronization circuit is built in the TCNT so that the entire 32-bit
data in the TCNT can be read at once.
• The maximum 2 MHz operating frequency for the 32-bit counter in each channel:
Operate the SH7727 so that the clock input to each channel timer counter does not exceed the
maximum operating frequency, by dividing the external clock and peripheral clock (Pφ) with
the prescaler.
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Section 15 Timer (TMU)
15.1.2
Block Diagram
Pφ
Prescaler
RTCCLK
Clock
controller
Bus interface
TSTR
Ch. 0
TCR0
Counter
controller
TCNT0
TCOR0
Ch. 1
TCR1
Counter
controller
TUNI1
Interrupt
controller
TCNT1
Module bus
TUNI0
Interrupt
controller
TCOR1
Ch. 2
TCR2
Counter
controller
TCNT2
TCOR2
TUNI2
Interrupt
controller
TMU
Legend:
TSTR: Timer start register
TCR: Timer control register
TCNT: 32-bit timer counter
TCOR: 32-bit timer constant register
Figure 15.1 TMU Block Diagram
Rev. 5.00 Dec 12, 2005 page 444 of 1034
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Internal bus
Figure 15.1 shows a block diagram of the TMU.
Section 15 Timer (TMU)
15.1.3
Register Configuration
Table 15.1 shows the TMU register configuration.
Table 15.1 TMU Register Configuration
Channel
Register
Abbreviation
R/W
Initial Value* Address
Access
Size
Common
Timer start register
TSTR
R/W
H'00
8
0
Timer constant register 0
TCOR0
R/W
H'FFFFFFFF H'FFFFFE94
32
Timer counter 0
TCNT0
R/W
H'FFFFFFFF H'FFFFFE98
32
Timer control register 0
TCR0
R/W
H'0000
H'FFFFFE9C
16
Timer constant register 1
TCOR1
R/W
H'FFFFFFFF H'FFFFFEA0
32
Timer counter 1
TCNT1
R/W
H'FFFFFFFF H'FFFFFEA4
32
Timer control register 1
TCR1
R/W
H'0000
H'FFFFFEA8
16
Timer constant register 2
TCOR2
R/W
H'FFFFFFFF H'FFFFFEAC
32
Timer counter 2
TCNT2
R/W
H'FFFFFFFF H'FFFFFEB0
32
Timer control register 2
TCR2
R/W
H'0000
16
1
2
H'FFFFFE92
H'FFFFFEB4
Note: * Initialized by a power-on reset or manual reset.
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Section 15 Timer (TMU)
15.2
TMU Registers
15.2.1
Timer Start Register (TSTR)
TSTR is an 8-bit read/write register that selects starting or stopping of the timer counters (TCNT)
for channels 0 to 2. TSTR is initialized to H'00 by a power-on reset or manual reset. TSTR is not
initialized in standby mode when the on-chip RTC clock (RTCCLK) is selected as the input clock
for the channel. However, only if the peripheral clock (Pφ) is selected for the channels, it is
initialized in standby mode when the multiplying ratio of PLL circuit 1 is modified and when the
MSTP2 bit in STBCR is set to 1.
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
STR2
STR1
STR0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R/W
R/W
R/W
Bits 7 to 3—Reserved: These bits are always read as 0 and should be written with 0.
Bit 2—Counter Start 2 (STR2): Selects starting or stopping of the timer counter 2 (TCNT2).
Bit 2: STR2
Description
0
Halts TCNT2 operation
1
Starts TCNT2 operation
(Initial value)
Bit 1—Counter Start 1 (STR1): starting or stopping of the timer counter 1 (TCNT1).
Bit 1: STR1
Description
0
Halts TCNT1 operation
1
Starts TCNT1 operation
(Initial value)
Bit 0—Counter Start 0 (STR0): Selects starting or stopping of the timer counter 0 (TCNT0).
Bit 0: STR0
Description
0
Halts TCNT0 operation
1
Starts TCNT0 operation
Rev. 5.00 Dec 12, 2005 page 446 of 1034
REJ09B0254-0500
(Initial value)
Section 15 Timer (TMU)
15.2.2
Timer Control Register (TCR)
The timer control registers (TCR) are 16-bit read/write registers that control the timer counters
(TCNT) and interrupts. The TMU has a total of three TCR registers, one for each channel.
The TCR registers control the interrupt generated when the flag that indicates the timer counter
(TCNT) underflow has been set to 1, and select the counter clock. When an external clock has
been selected, the clock edge can also be selected.
TCR is initialized to H'0000 by a power-on reset or manual reset. In standby mode, it is not
initialized and retains the value.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
UNF
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
UNIE
—
—
TPSC2
TPSC1
TPSC0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R/W
R
R
R/W
R/W
R/W
Bits 15 to 9, 7, 6, 4, and 3—Reserved: These bits are always read as 0 and should only be written
with 0.
Bit 8—Underflow Flag (UNF): This is a status flag that indicates that TCNT underflowed.
Bit 8: UNF
Description
0
TCNT has not underflowed.
Clear condition: When 0 is written to UNF
1
(Initial value)
TCNT has underflowed (H'00000000 → H'FFFFFFFF).
Setting condition: When TCNT underflows*
Note: * When a write of 1 is provided to UNF, it is not modified and the previous value is retained.
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Section 15 Timer (TMU)
Bit 5—Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt
generation when the status flag (UNF) that indicates TCNT underflow has been set to 1.
Bit 5: UNIE
Description
0
Interrupt due to UNF (TUNI) is disabled.
1
Interrupt due to UNF (TUNI) is enabled.
(Initial value)
Bits 2 to 0—Timer Prescalers 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT count
clock.
Bit 2: TPSC2
Bit 1: TPSC1
Bit 0: TPSC0
Description
0
0
0
Counts on peripheral clock Pφ/4
1
Counts on peripheral clock Pφ/16
0
Counts on peripheral clock Pφ/64
1
Counts on peripheral clock Pφ/256
0
Counts on on-chip RTC clock outputs (RTCCLK)
1
Reserved (Setting disabled)
0
Reserved (Setting disabled)
1
Reserved (Setting disabled)
1
1
0
1
15.2.3
(Initial value)
Timer Constant Register (TCOR)
The TMU has a total of three TCOR registers, one for each channel. The TCOR registers are 32bit read/write registers that specify a value to be set to the TCNT counter after a TCNT counter
underflow occurred.
TCOR is initialized to H'FFFFFFFF by a power-on reset or manual reset. In standby mode, it is
not initialized and retains the value.
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Section 15 Timer (TMU)
Bit:
Initial value:
R/W:
Bit:
Initial value:
30
29
28
27
26
25
24
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
15
14
13
12
11
10
9
8
Initial value:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
R/W:
R/W:
15.2.4
31
Timer Counters (TCNT)
The TMU has a total of three timer counters (TCNT), one for each channel. The TCNT counters
are 32-bit read/write registers that are decremented according to the input clock. The input clock
can be selected with the TPSC2 to TPSC0 bits in the timer control register (TCR).
When a TCNT decrementation results in an underflow (H'00000000 → H'FFFFFFFF), the
underflow flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR
value is simultaneously set in TCNT itself and the decrementation continues from that value.
The TCNT counter is a 32-bit readable/writable register. Because the internal bus for the SH7727
on-chip peripheral modules is 16 bits wide, a time lag occurs when reading data from 32-bit
registers because the upper 16 bits and lower 16 bits are read separately. Since TCNT counts
sequentially, this time lag can create discrepancies between the data in the upper and lower halves.
To prevent this, a buffer register is connected to TCNT so that upper and lower halves are not read
separately. Thus all 32 bits in TCNT can thus be read at once and no timing discrepancies occur
when reading data.
Rev. 5.00 Dec 12, 2005 page 449 of 1034
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Section 15 Timer (TMU)
TCNT is initialized to H'FFFFFFFF by a power-on reset or manual reset. In standby mode, it is
not initialized and retains the value.
Bit:
Initial value:
R/W:
Bit:
Initial value:
31
30
29
28
27
26
25
24
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
15
14
13
12
11
10
9
8
Initial value:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
R/W:
R/W:
Rev. 5.00 Dec 12, 2005 page 450 of 1034
REJ09B0254-0500
Section 15 Timer (TMU)
15.3
TMU Operation
15.3.1
Overview
Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). The
TCNT is a down-counter. The auto-reload function can be used to enable synchronized counting
and counting by external events.
15.3.2
Basic Functions
Counter Operation: When the STR0 to STR2 bits in the timer start register (TSTR) are set, the
corresponding timer counters (TCNT) start decrementation. When TCNT underflows, the UNF
flag in the corresponding timer control register (TCR) is set. At this time, if the UNIE bit in TCR
is 1, an interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to
TCNT and the decrementation is continued.
The decrementation is set as follows (figure 15.2):
Select operation
(1)
(1) Select the counter clock with the TPSC2
to TPSC0 bits in the timer control register
(TCR).
Set underflow
interrupt generation
(2)
(2) Set whether or not an interrupt is
generated when TCNT underflows, with
the UNIE bit in TCR.
Set timer constant
register
(3)
Select counter
clock
(3) Set a value in the timer constant register
(TCOR) (the cycle is the set value plus 1).
Initialize timer
counter
(4)
Start counting
(5)
(4) Set the initial value in the timer counter
(TCNT).
(5) Set the STR bit in the timer start register
(TSTR) to 1 to start operation.
Note: When an interrupt has been generated, clear the flag in the interrupt handler that
caused it.
If interrupts are enabled without clearing the flag, another interrupt will be generated.
Figure 15.2 Setting the Count Operation
Rev. 5.00 Dec 12, 2005 page 451 of 1034
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Section 15 Timer (TMU)
Auto-Reload Count Operation: Figure 15.3 shows the TCNT auto-reload operation.
TCOR value set to
TCNT during underflow
TCNT value
TCOR
Time
H'00000000
STR0 to STR2
UNF
Figure 15.3 Auto-Reload Counter Operation
TCNT Count Timing:
• Internal Clock Operation
Select one of the four internal clocks (Pφ/4, Pφ/16, Pφ/64, Pφ/256), which are divided from the
peripheral clock Pφ, with the TPSC2 to TPSC0 bits in TCR. Figure 15.4 shows the timing.
Pφ
Divided
clock
TCNT
input clock
TCNT
N+1
N
Figure 15.4 Count Timing when Internal Clock is Operating
Rev. 5.00 Dec 12, 2005 page 452 of 1034
REJ09B0254-0500
N−1
Section 15 Timer (TMU)
• On-Chip RTC Clock Operation
Select the on-chip RTC clock as the timer clock with the TPSC2 to TPSC0 bits in TCR.
RTC output
clock
TCNT input
clock
TCNT
N+1
N−1
N
Figure 15.5 Count Timing when On-Chip RTC Clock is Operating
15.4
Interrupts
There is only one source for TMU interrupts: underflow interrupts (TUNI).
15.4.1
Status Flag Set Timing
The UNF bit is set to 1 when TCNT underflows. Figure 15.6 shows the timing.
Pφ
TCNT
H'00000000
TCOR value
Underflow
signal
UNF
TUNI
Figure 15.6 UNF Set Timing
Rev. 5.00 Dec 12, 2005 page 453 of 1034
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Section 15 Timer (TMU)
15.4.2
Status Flag Clear Timing
The status flag is cleared when 0 is written by the CPU. Figure 15.7 shows the timing.
TCR write cycle
T1
T2
T3
Pφ
Peripheral address bus
TCR address
UNF
Figure 15.7 Status Flag Clear Timing
15.4.3
Interrupt Sources and Priorities
The TMU generates underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the corresponding interrupt is requested. When an interrupt is
generated, codes are set in the interrupt event register (INTEVT, INTEVT2). Provide the
appropriate interrupt handling according to the codes.
The channel priority can be changed using the interrupt controller (see section 4, Exception
Handling, and section 7, Interrupt Controller (INTC)). Table 15.2 lists TMU interrupt sources.
Table 15.2 TMU Interrupt Sources
Channel
Interrupt Source
Description
Priority
0
TUNI0
Underflow interrupt 0
High
1
TUNI1
Underflow interrupt 1
2
TUNI2
Underflow interrupt 2
Rev. 5.00 Dec 12, 2005 page 454 of 1034
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Low
Section 15 Timer (TMU)
15.5
Usage Notes
15.5.1
Writing to Registers
Synchronous processing is not performed for timer count operation during register writes. When
writing to registers, always clear the start bits (STR2 to STR0) for the desired channel in the timer
start register (TSTR) to halt timer counting.
15.5.2
Reading Registers
Synchronous processing is performed for timer count operation during register reads. When timer
counting and register read processing are performed simultaneously, the register value prior to the
TCNT decrementation is read with the synchronous processing.
Rev. 5.00 Dec 12, 2005 page 455 of 1034
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Section 15 Timer (TMU)
Rev. 5.00 Dec 12, 2005 page 456 of 1034
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Section 16 Realtime Clock (RTC)
Section 16 Realtime Clock (RTC)
16.1
Overview
This LSI has a realtime clock (RTC) with its own 32.768-kHz crystal oscillation circuit.
16.1.1
Features
The RTC has the following features:
• Clock and calendar functions (BCD display): Seconds, minutes, hours, date, day of the week,
month, and year
• 1 to 64-Hz timer (binary display)
• Start/stop function
• 30-second adjustment
• Alarm interrupt:
Frame comparisons of seconds, minutes, hours, date, day of the week, and month can be
selected for the alarm interrupt condition
• Periodic interrupts:
The interrupt cycle can be selected from 1/256 second, 1/64 second, 1/16 second, 1/4 second,
1/2 second, 1 second, or 2 seconds
• Carry interrupt: A carry interrupt indicates when a carry occurs during a counter read
• Automatic leap year correction
Rev. 5.00 Dec 12, 2005 page 457 of 1034
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Section 16 Realtime Clock (RTC)
16.1.2
Block Diagram
Figure 16.1 shows a block diagram of the RTC.
Oscillator
circuit
XTAL2
128 Hz
30second
Reset ADJ
R64CNT
32.768 kHz
RSECCNT
Prescaler
(÷ 2)
RTCCLK
Bus
interface
RMINCNT
RHRCNT
16.384 kHz
RWKCNT
RDAYCNT
Prescaler
(÷ 128)
RMONCNT
RYRCNT
PRI
Interrupt
control
circuit
Comparator
RSECAR
RMINAR
CUI
Carry
detection
circuit
Module bus
ATI
RHRAR
RWKAR
RDAYAR
RMONAR
RCR1
RCR2
Legend:
R64CNT:
RSECCNT:
RMINCNT:
RHRCNT:
RWKCNT:
RDAYCNT:
RMONCNT:
RYRCNT:
64-Hz counter
Second counter
Minute counter
Hour counter
Day of the week counter
Date counter
Month counter
Year counter
RSECAR:
RHRAR:
RMINAR:
RWKAR:
RDAYAR:
RMONAR:
RCR1:
RCR2:
RTC
Second alarm register
Minute alarm register
Hour alarm register
Day of the week alarm register
Date alarm register
Month alarm register
RTC control register 1
RTC control register 2
Figure 16.1 RTC Block Diagram
Rev. 5.00 Dec 12, 2005 page 458 of 1034
REJ09B0254-0500
Internal bus
Externally
connected
circuit
EXTAL2
Section 16 Realtime Clock (RTC)
16.1.3
Pin Configuration
Table 16.1 shows the RTC pin configuration.
Table 16.1 RTC Pin Configuration
Pin
Abbreviation
I/O
Description
RTC oscillator crystal pin
EXTAL2
I
RTC oscillator crystal pin
XTAL2
O
Connects crystal to RTC oscillator*
1
Connects crystal to RTC oscillator*
Power-supply pin dedicated
for RTC
Vcc-RTC
—
Power-supply pin for RTC oscillator*
GND pin dedicated for RTC
Vss-RTC
—
GND pin for RTC oscillator*
1
1
2
Notes: 1. When the RTC is not used, set EXTAL2 to pull-up (to Vcc) and make no connection for
XTAL2.
2. Input of external noise via the Vss-RTC pin can cause the device to malfunction. To
prevent external noise input via the Vss-RTC, the system and circuitry should include a
noise elimination circuit.
Rev. 5.00 Dec 12, 2005 page 459 of 1034
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Section 16 Realtime Clock (RTC)
16.1.4
RTC Register Configuration
Table 16.2 shows the RTC register configuration.
Table 16.2 RTC Registers
Name
Abbreviation
R/W
Initial Value
Address
Access Size
64-Hz counter
R64CNT
R
Undefined
H'FFFFFEC0
8
Second counter
RSECCNT
R/W
Undefined
H'FFFFFEC2
8
Minute counter
RMINCNT
R/W
Undefined
H'FFFFFEC4
8
Hour counter
RHRCNT
R/W
Undefined
H'FFFFFEC6
8
Day of week counter
RWKCNT
R/W
Undefined
H'FFFFFEC8
8
Date counter
RDAYCNT
R/W
Undefined
H'FFFFFECA
8
Month counter
RMONCNT
R/W
Undefined
H'FFFFFECC
8
Year counter
RYRCNT
R/W
Undefined
H'FFFFFECE
8
Second alarm register
RSECAR
R/W
Undefined*
H'FFFFFED0
8
Minute alarm register
RMINAR
R/W
Undefined*
H'FFFFFED2
8
Hour alarm register
RHRAR
R/W
Undefined*
H'FFFFFED4
8
Day of week alarm register
RWKAR
R/W
Undefined*
H'FFFFFED6
8
Date alarm register
RDAYAR
R/W
Undefined*
H'FFFFFED8
8
Month alarm register
RMONAR
R/W
Undefined*
H'FFFFFEDA
8
RTC control register 1
RCR1
R/W
H'00
H'FFFFFEDC
8
RTC control register 2
RCR2
R/W
H'09
H'FFFFFEDE
8
Note: * Only the ENB bit in each register is initialized.
Rev. 5.00 Dec 12, 2005 page 460 of 1034
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Section 16 Realtime Clock (RTC)
16.2
Register Descriptions
16.2.1
64-Hz Counter (R64CNT)
The 64-Hz counter (R64CNT) is an 8-bit read-only register that indicates the state of the RTC
divider circuits (RTC prescaler or R64CNT) between 64 Hz and 1 Hz.
R64CNT is reset to H'00 when the RESET bit in RTC control register 2 (RCR2) or the ADJ bit in
RCR2 is set to 1.
R64CNT is not initialized by a power-on reset or manual reset, or in standby mode, and the
operation is continued.
Bit 7 is always read as 0.
Bit:
16.2.2
7
6
5
4
3
2
1
0
—
1Hz
2Hz
4Hz
8Hz
16Hz
32Hz
64Hz
Initial value:
0
—
—
—
—
—
—
—
R/W:
R
R
R
R
R
R
R
R
Second Counter (RSECCNT)
The second counter (RSECCNT) is an 8-bit read/write register that is used for setting/counting in
the BCD-coded second section of the RTC. The count operation is performed by a carry for each
second of the 64-Hz counter.
The settable range is 00 to 59 in decimal. If other values are set, correct operation is not provided.
When modifying RSECCNT, check that the count operation has been halted with the START bit
in RCR2.
RSECCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the
operation is continued.
Bit:
7
6
—
5
4
3
10 seconds
2
1
0
1 second
Initial value:
0
—
—
—
—
—
—
—
R/W:
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Dec 12, 2005 page 461 of 1034
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Section 16 Realtime Clock (RTC)
16.2.3
Minute Counter (RMINCNT)
The minute counter (RMINCNT) is an 8-bit read/write register used for setting/counting in the
BCD-coded minute section of the RTC. The count operation is performed by a carry for each
minute of the second counter.
The settable range is 00 to 59 in decimal. If other values are set, correct operation is not provided.
When modifying RMINCNT, check that the count operation has been halted with the START bit
in RCR2.
RMINCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the
operation is continued.
Bit:
7
6
—
16.2.4
5
4
3
2
10 minutes
1
0
1 minute
Initial value:
0
—
—
—
—
—
—
—
R/W:
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Hour Counter (RHRCNT)
The hour counter (RHRCNT) is an 8-bit read/write register used for setting/counting in the BCDcoded hour section of the RTC. The count operation is performed by a carry for each 1 hour of the
minute counter.
The settable range is 00 to 23 in decimal. If other values are set, correct operation is not provided.
When modifying RHRCNT, check that the count operation has been halted with the START bit in
RCR2.
RHRCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the
operation is continued.
Bit:
7
6
—
—
5
4
3
2
10 hours
1
0
1 hour
Initial value:
0
0
—
—
—
—
—
—
R/W:
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Dec 12, 2005 page 462 of 1034
REJ09B0254-0500
Section 16 Realtime Clock (RTC)
16.2.5
Day of the Week Counter (RWKCNT)
The day of the week counter (RWKCNT) is an 8-bit read/write register used for setting/counting
in the BCD-coded day of week section of the RTC. The count operation is performed by a carry
for each day of the date counter.
The settable range is 0 to 6 in decimal. If other values are set, correct operation is not provided.
When modifying RWKCNT, check that the count operation has been halted with the START bit
in RCR2.
RWKCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the
operation is continued.
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
Initial value:
0
0
0
0
0
—
Day of week
—
—
R/W:
R
R
R
R
R
R/W
R/W
R/W
Days of the week are coded as shown in table 16.3.
Table 16.3 Day-of-Week Codes (RWKCNT)
Day of Week
Code
Sunday
0
Monday
1
Tuesday
2
Wednesday
3
Thursday
4
Friday
5
Saturday
6
Rev. 5.00 Dec 12, 2005 page 463 of 1034
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Section 16 Realtime Clock (RTC)
16.2.6
Date Counter (RDAYCNT)
The date counter (RDAYCNT) is an 8-bit read/write register used for setting/counting in the
BCD-coded date section of the RTC. The count operation is performed by a carry for each day of
the hour counter.
The settable range is 01 to 31 in decimal. If other values are set, correct operation is not provided.
When modifying RDAYCNT, check that the count operation has been halted with the START bit
in RCR2.
RDAYCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the
operation is continued.
The settable RDAYCNT range differs according to the month and leap year. Please confirm the
correct setting.
Bit:
16.2.7
7
6
5
4
3
2
10 days
1
0
—
—
Initial value:
0
0
—
—
—
—
1 day
—
—
R/W:
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Month Counter (RMONCNT)
The month counter (RMONCNT) is an 8-bit read/write register used for setting/counting in the
BCD-coded month section of the RTC. The count operation is performed by a carry for each
month of the date counter.
The settable range is 01 to 12 in decimal. If other values are set, correct operation is not provided.
When modifying RMONCNT, check that the count operation has been halted with the START bit
in RCR2.
RMONCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the
operation is continued.
Bit:
7
6
5
4
—
—
—
10
months
Initial value:
0
0
0
—
—
R/W:
R
R
R
R/W
R/W
Rev. 5.00 Dec 12, 2005 page 464 of 1034
REJ09B0254-0500
3
2
1
0
—
—
—
R/W
R/W
R/W
1 month
Section 16 Realtime Clock (RTC)
16.2.8
Year Counter (RYRCNT)
The year counter (RYRCNT) is an 8-bit read/write register used for setting/counting in the BCDcoded year section of the RTC. The least significant 2 digits of the western calendar year are
displayed. The count operation is performed by a carry for each year of the month counter.
The settable range is 00 to 99 in decimal. If other values are set, correct operation is not provided.
When modifying RYRCNT, check that the count operation is halted with the START bit in RCR2.
RYRCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the
operation is continued.
Leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result
of 0. Note that a counter value of 00 is treated as a leap year.
Bit:
7
6
5
4
3
2
10 years
Initial value:
R/W:
16.2.9
1
0
1 year
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Second Alarm Register (RSECAR)
The second alarm register (RSECAR) is an 8-bit read/write alarm register that corresponds to the
BCD-coded second section counter RSECCNT of the RTC. When the ENB bit is set to 1in
RSECAR, the RSECAR value and RSECCNT value are compared. In this way, the RSECAR,
RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are checked, and when the
ENB bit is set to 1, the alarm register and the corresponding counter are compared. If all values in
the specified alarm registers and the corresponding counters match, an RTC alarm interrupt is
generated.
The settable range is “00 to 59 in decimal + ENB bit”. If other values are set, correct operation is
not provided.
Only the ENB bit in RSECAR is initialized to 0 by a power-on reset, and the other bits are not
initialized. The RSECAR contents are retained after a manual reset or in standby mode.
Bit:
7
6
ENB
Initial value:
R/W:
5
4
3
10 seconds
2
1
0
1 second
0
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Dec 12, 2005 page 465 of 1034
REJ09B0254-0500
Section 16 Realtime Clock (RTC)
16.2.10 Minute Alarm Register (RMINAR)
The minute alarm register (RMINAR) is an 8-bit read/write alarm register that corresponds to the
BCD-coded minute section counter RMINCNT of the RTC. When the ENB bit is set to 1in
RMINAR, the RMINAR value and RMINCNT value are compared. In this way, the RSECAR,
RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are checked, and when the
ENB bit is set to 1, the alarm register and the corresponding counter are compared. If all values in
the specified alarm registers and the corresponding counters match, an RTC alarm interrupt is
generated.
The settable range is “00 to 59 in decimal + ENB bit”. If other values are set, correct operation is
not provided.
Only the ENB bit in RMINAR is initialized to 0 by a power-on reset, and the other bits are not
initialized. The RMINAR contents are retained after a manual reset or in standby mode.
Bit:
7
6
ENB
Initial value:
R/W:
5
4
3
10 minutes
2
1
0
1 minute
0
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16.2.11 Hour Alarm Register (RHRAR)
The hour alarm register (RHRAR) is an 8-bit read/write alarm register that corresponds to the
BCD-coded hour section counter RHRCNT of the RTC. When the ENB bit is set to 1in RHRAR,
the RHRAR value and RHRCNT value are compared. In this way, the RSECAR, RMINAR,
RHRAR, RWKAR, RDAYAR, and RMONAR registers are checked, and when the ENB bit is set
to 1, the alarm register and the corresponding counter are compared. If all values in the specified
alarm registers and the corresponding counters match, an RTC alarm interrupt is generated.
The settable range is “00 to 23 in decimal + ENB bit”. If other values are set, correct operation is
not provided.
Only the ENB bit in RHRAR is initialized to 0 by a power-on reset, and the other bits are not
initialized. The RHRAR contents are retained after a manual reset or in standby mode.
Bit:
Initial value:
R/W:
7
6
5
4
3
ENB
—
0
0
—
—
—
R/W
R
R/W
R/W
R/W
2
1
0
—
—
—
R/W
R/W
R/W
10 hours
Rev. 5.00 Dec 12, 2005 page 466 of 1034
REJ09B0254-0500
1 hour
Section 16 Realtime Clock (RTC)
16.2.12 Day of the Week Alarm Register (RWKAR)
The day of the week alarm register (RWKAR) is an 8-bit read/write alarm register that
corresponds to the BCD-coded day of week section counter RWKCNT of the RTC. When the
ENB bit is set to 1in RWKAR, the RWKAR value and RWKCNT value are compared. In this
way, the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are
checked, and when the ENB bit is set to 1, the alarm register and the corresponding counter are
compared. If all values in the specified alarm registers and the corresponding counters match, an
RTC alarm interrupt is generated.
The settable range is “0 to 6 in decimal + ENB bit”. If other values are set, correct operation is not
provided.
Only the ENB bit in RWKAR is initialized to 0 by a power-on reset, and the other bits are not
initialized. The RWKAR contents are retained after a manual reset or in standby mode.
Bit:
Initial value:
R/W:
7
6
5
4
3
ENB
—
—
—
—
2
1
0
0
0
0
0
0
—
—
—
R/W
R
R
R
R
R/W
R/W
R/W
Day of week
Days of the week are coded as shown in table 16.4.
Table 16.4 Day-of-Week Codes (RWKAR)
Day of Week
Code
Sunday
0
Monday
1
Tuesday
2
Wednesday
3
Thursday
4
Friday
5
Saturday
6
16.2.13 Date Alarm Register (RDAYAR)
The date alarm register (RDAYAR) is an 8-bit read/write alarm register that corresponds to the
BCD-coded date section counter RDAYCNT of the RTC. When the ENB bit is set to 1in
RDAYAR, the RDAYAR value and RDAYCNT value are compared. In this way, the RSECAR,
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Section 16 Realtime Clock (RTC)
RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are checked, and when the
ENB bit is set to 1, the alarm register and the corresponding counter are compared. If all values in
the specified alarm registers and the corresponding counters match, an RTC alarm interrupt is
generated.
The settable range is “01 to 31 in decimal + ENB bit”. If other values are set, correct operation is
not provided. The settable RDAYCNT range differs according to the month and leap year. Please
confirm the correct setting.
Only the ENB bit in RDAYAR is initialized to 0 by a power-on reset, and the other bits are not
initialized. The RDAYAR contents are retained after a manual reset or in standby mode.
Bit:
Initial value:
R/W:
7
6
ENB
—
0
0
R/W
R
5
4
3
2
1
0
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
10 days
1 day
16.2.14 Month Alarm Register (RMONAR)
The month alarm register (RMONAR) is an 8-bit read/write alarm register that corresponds to the
BCD-coded month section counter RMONCNT of the RTC. When the ENB bit is set to 1in
RMONAR, the RMONAR value and RMONCNT value are compared. In this way, the RSECAR,
RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are checked, and when the
ENB bit is set to 1, the alarm register and the corresponding counter are compared. If all values in
the specified alarm registers and the corresponding counters match, an RTC alarm interrupt is
generated.
The settable range is “01 to 12 in decimal + ENB bit”. If other values are set, correct operation is
not provided.
Only the ENB bit in RMONAR is initialized to 0 by a power-on reset, and the other bits are not
initialized. The RMONAR contents are retained after a manual reset or in standby mode.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
ENB
—
—
10
months
0
0
0
—
—
—
—
—
R/W
R
R
R/W
R/W
R/W
R/W
R/W
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1 month
Section 16 Realtime Clock (RTC)
16.2.15 RTC Control Register 1 (RCR1)
The RTC control register 1 (RCR1) is an 8-bit read/write register that contains carry flags and
alarm flags. It also selects whether to generate interrupts for each flag. Avoid the use of readmodify-write processing for this register because flags are sometimes set after an operand read.
RCR1 is an 8-bit read/write register. The CIE, AIE, and AF bits are initialized by a power-on reset
or manual reset. However, the value of the CF flag is undefined after a power-on reset or manual
reset. It must therefore be initialized without fail before use. This register is not initialized in
standby mode.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
CF
—
—
CIE
AIE
—
—
AF
—
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R
R
R/W
Bit 7—Carry Flag (CF): Status flag that indicates that a carry has occurred. CF is set to 1 when a
carry occurs in R64CNT or RSECCNT. If the count register is read at this time, the value is not
guaranteed; therefore, another read is required.
Bit 7: CF
Description
0
No carry in R64CNT or RSECCNT.
Clearing condition: When 0 is written to CF
1
Setting condition:
Carry occurred in RSECCNT
Read of R64CNT at carry occurrence
When 1 is written to CF
Bits 6, 5, 2, and 1—Reserved: These bits are always read as 0 and should only be written with 0.
Bit 4—Carry Interrupt Enable Flag (CIE): Enables or disables interrupt generation when the
carry flag (CF) is set to 1.
Bit 4: CIE
Description
0
A carry interrupt is not generated when the CF flag is set to 1
1
A carry interrupt is generated when the CF flag is set to 1
(Initial value)
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Section 16 Realtime Clock (RTC)
Bit 3—Alarm Interrupt Enable Flag (AIE): Enables or disables interrupt generation when the
alarm flag (AF) is set to 1.
Bit 3: AIE
Description
0
An alarm interrupt is not generated when the AF flag is set to 1
1
An alarm interrupt is generated when the AF flag is set to 1
(Initial value)
Bit 0—Alarm Flag (AF): The AF flag is set to 1 when the alarm time set in alarm registers (only
for the registers with ENB bit set to 1) match the clock and calendar time. This flag is cleared to 0
when 0 is written, but the previous value is retained when 1 is to be written.
Bit 0: AF
Description
0
Clock/calendar and alarm register have not matched since last reset to 0.
Clearing condition: When 0 is written to AF
(Initial value)
1
Setting condition: Clock/calendar and alarm register have matched (only for the
registers with ENB set to 1)*
Note: * The value is not modified when 1 is written to AF.
16.2.16 RTC Control Register 2 (RCR2)
The RTC control register 2 (RCR2) is an 8-bit read/write register that controls periodic interrupts,
30-second adjustment ADJ, divider circuits RESET, and starting and stopping of the RTC count. It
is initialized to H'09 by a power-on reset. By a manual reset, bits except RTCEN and START are
initialized. RCR2 is not initialized and retains its contents in standby mode.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
PEF
PES2
PES1
PES0
RTCEN
ADJ
RESET
START
0
0
0
0
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 16 Realtime Clock (RTC)
Bit 7—Periodic Interrupt Flag (PEF): Indicates that interrupts are generated with the period
designated by the PES bits. When this bit is set to 1, periodic interrupts are generated.
Bit 7: PEF
Description
0
Interrupts not generated with the period designated by the PES bits.
Clearing condition: When 0 is written to PEF
1
(Initial value)
Setting condition:
When interrupts are generated with the period designated by the PES bits
When 1 is written to PEF
Bits 6 to 4—Periodic Interrupt Flags (PES2 to PES0): These bits specify the periodic interrupt.
Bit 6: PES2
Bit 5: PES1
Bit 4: PES0
Description
0
0
0
No periodic interrupts generated
1
Periodic interrupt generated every 1/256 second
0
Periodic interrupt generated every 1/64 second
1
Periodic interrupt generated every 1/16 second
0
Periodic interrupt generated every 1/4 second
1
Periodic interrupt generated every 1/2 second
0
Periodic interrupt generated every 1 second
1
Periodic interrupt generated every 2 seconds
1
1
0
1
(Initial value)
Bit 3—RTCEN: Controls the operation of the crystal oscillator for the RTC.
Bit 3: RTCEN
Description
0
Halts the crystal oscillator for the RTC. *
1
Runs the crystal oscillator for the RTC. *
(Initial value)
Note: * RTCEN should be set to 0 when the RTC is not used.
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Section 16 Realtime Clock (RTC)
Bit 2—30 Second Adjustment (ADJ): When the ADJ bit is written with 1, the time of 29
seconds or less will be rounded to 00 seconds and the time of 30 seconds or more to 1 minute. The
divider circuits (RTC prescaler and R64CNT) will be simultaneously reset. This bit is always read
as 0.
Bit 2: ADJ
Description
0
Normal operation
1 (write)
30-second adjustment.
(Initial value)
Bit 1—Reset (RESET): When 1 is written to the RESET bit, the divider circuits (RTC prescaler
and R64CNT) are initialized. This bit is always read as 0.
Bit 1: RESET
Description
0
Runs normally.
1 (Write)
Divider circuits are reset.
(Initial value)
Bit 0—Start Bit (START): Halts and restarts the counter (clock).
Bit 0: START
Description
0
Second, minute, hour, day, week, month, and year counters are halted.*
1
Second, minute, hour, day, week, month, and year counters operate normally.*
(Initial value)
Note: * The 64-Hz counter operates normally until it is stopped with the RTCEN bit.
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Section 16 Realtime Clock (RTC)
16.3
RTC Operation
16.3.1
Initial Settings of Registers after Power-On
All RTC registers should be set initially after the power is turned on.
16.3.2
Setting the Time
Figures 16.2 (a) and 16.2 (b) show how to set the time after stopping the clock. This procedure can
be used to set the entire calendar and clock function. It can be programmed easily.
Usage Notes
1. Initialization Timing for 64 Hz Counter (R64CNT)
If it is necessary, after initializing the counter by means of the RESET bit in the RTC’s RCR2
register, to confirm that the change has taken effect by reading the R64CNT value, wait at least
107 µs after setting the RESET bit to 1 before reading the R64CNT counter. Note that the
divider circuit (RTC prescaler) is also initialized when the RESET bit is set to 1.
2. Incrementing RSECCNT by Initializing R64CNT
Either method (a) or method (b) below may be used.
(a) After setting the RESET bit to 1 and confirming that R64CNT has been initialized, set the
START bit to 1. This process is shown in figure 16.2 (a).
(b) Set the START bit to 1 and the RESET bit to 1 at the same time. This process is shown in
figure 16.2 (b). Note that the processing indicated by the asterisk (*) in figure 16.2 (b) may
be omitted if nothing is written to the RCR2 register during an interval of approximately
107 µs after the START bit is set to 1.
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Section 16 Realtime Clock (RTC)
Confirm R64CNT is not 0
Stop clock
Reset divider circuit
Write 1 to RESET and
0 to START in the RCR2 register
Set seconds, minutes,
hour, day, day of the
week, month and year
Order is irrelevant
Confirm R64CNT is 0
No
Yes
Start clock
Write 1 to START in the RCR2 register
Figure 16.2(a) Setting the Time
*
Confirm R64CNT is not 0
Stop clock
Reset divider circuit
Write 1 to RESET and
0 to START in the RCR2 register
Set seconds, minutes,
hour, day, day of the
week, month and year
Order is irrelevant
Write 1 to RESET and
Start clock
Reset divider circuit
*
Confirm R64CNT is 0
*
Write to RCR2
1 to START in the RCR2 register
No
Yes
Figure 16.2(b) Setting the Time
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Section 16 Realtime Clock (RTC)
16.3.3
Reading the Time
Figure 16.3 shows how to read the time. If a carry occurs while reading the time, the correct time
will not be obtained, so it must be read again. The method of reading the time without using
interrupts is shown at (a) in figure 16.3, and the method using carry interrupts is shown at (b). To
keep the program simple, method (a) is used normally.
a. To read the time
without using interrupts
Disable the carry
interrupt
Clear the carry flag
Write 0 to CIE in RCR1
Write 0 to CF in RCR1
Note: Set AF to 1 so that alarm
flag is not cleared.
Read counter
register
Yes
Carry flag = 1?
Read RCR1 and check CF
No
b. To use interrupts
Enable the carry
interrupt
Clear the carry flag
Write 1 to CIE in RCR1,
and write 0 to CF in RCR1
Note: Set AF in RCR1 to 1 so that
alarm flag is not cleared.
Read counter
register
Yes
Interrupt
generated?
No
Disable the carry
interrupt
Write 0 to CIE in RCR1
Figure 16.3 Reading the Time
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Section 16 Realtime Clock (RTC)
16.3.4
Alarm Function
Figure 16.4 shows how to use the alarm function.
Alarm can be generated using seconds, minutes, hours, day of the week, date, month, or any
combination of these. Set the ENB bits (bit 7) in the desired alarm registers to 1, and then set the
alarm time in the lower bits. Clear the ENB bits in the registers which are not used for the alarm to
0.
When the clock and alarm time match, the AF bit (bit 0) in RCR1 is set to 1. The alarm detection
can be checked by reading this bit, but normally it is checked by the interrupt generation. If the
AIE bit (bit 3) in RCR1 is written with 1, an interrupt is generated when an alarm occurs.
Clock running
Cancel alarm
interrupt
Disables interrupts (clears the AIE bit in
RCR1 to 0) in order to prevent erroneous
interrupts, and then writes 1.
Set alarm time
Clear alarm flag
Always reset the alarm flag, since a flag may
have been set while the alarm time was being
set (clear the AF bit in RCR1 register to 0).
Monitor alarm time
(wait for interrupt or
check alarm flag)
Figure 16.4 Using the Alarm Function
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Section 16 Realtime Clock (RTC)
16.3.5
Crystal Oscillator Circuit
Crystal oscillator circuit constants (recommended values) are shown in table 16.5, and the RTC
crystal oscillator circuit in figure 16.5.
Table 16.5 Recommended Oscillator Circuit Constants (Recommended Values)
fosc
Cin
Cout
32.768 kHz
10 to 22 pF
10 to 22 pF
Rf
SH7727
RD
XTAL2
EXTAL2
XTAL
Cin
Cout
Notes: 1. Select either the Cin or Cout side for frequency adjustment variable capacitor
according to requirements such as frequency range, degree of stability, etc.
2. Built-in resistance value Rf (Typ value) = 10 MΩ, RD (Typ value) = 400 kΩ
3. Cin and Cout values include floating capacitance due to the wiring. Take care
when using a ground plane.
4. The crystal oscillation settling time depends on the mounted circuit constants,
floating capacitance, etc., and should be decided after consultation with the
crystal resonator manufacturer.
5. Place the crystal resonator and load capacitors Cin and Cout as close as possible
to the chip.
(Correct oscillation may not be possible if there is externally induced noise in the
EXTAL2 and XTAL2 pins.)
6. Ensure that the crystal resonator connection pin (EXTAL2, XTAL2) wiring is
routed as far away as possible from other power lines (except GND) and signal
lines.
Figure 16.5 Example of Crystal Oscillator Circuit Connection
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Section 16 Realtime Clock (RTC)
16.4
Usage Notes
16.4.1
Writing Registers During RTC Count Operation
During the RTC count operation (RCR2 bits 0 = 1), the following registers cannot be written.
RSECCNT, RMICNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, and RYRCNT
To write these registers, the RTC count operation should be stopped.
16.4.2
RTC Periodic Interrupts
Figure 16.6 shows the periodic interrupt function setting flow.
Periodic interrupts can be generated with the period specified by the periodic interrupt enable flag
(PES) in the RTC control register (RCR2). When the time period specified by PES passed, the
periodic interrupt flag (PEF) is set to 1.
PEF is cleared to 0 when PES is set and a periodic interrupt is generated. The periodic interrupt
generation can be checked by reading this bit, but is usually checked by the interrupt function.
Set PES and clear PEF
PES is set and PEF is
cleared in RCR2.
Period set by PES passed
Clears PEF
PEF is cleared to 0.
Figure 16.6 Periodic Interrupt Function Setting
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Section 16 Realtime Clock (RTC)
16.4.3
Using the ADJ Bit in the Real Time Clock (RTC)
(1) Description
The maximum amount of time from when the ADJ bit in RCR2 of the RTC is set to 1 and when
the value read from the second counter (RSECCNT) is reflected is approximately 91.6 µs (the
time required for pin of the EXTAL2 to connect to the 32.768 kHz oscillator). Note that the
second counter itself performs a 30-second adjustment when the ADJ bit is set to 1, so the above
delay causes no problems with the functioning of the RTC.
(2) Precautions
If it is necessary to ensure that the 30-second adjustment triggered by the ADJ bit in RCR2 of the
RTC is properly read and its value reflected, the second counter should not be read until a
minimum of approximately 91.6 µs has passed following the setting of the ADJ bit.
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Section 16 Realtime Clock (RTC)
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Section 17 Serial Communication Interface (SCI)
Section 17 Serial Communication Interface (SCI)
17.1
Overview
This LSI has an on-chip serial communication interface (SCI) that supports both asynchronous and
clock synchronous serial communication. It also has a multiprocessor communication function for
serial communication among two or more processors. The SCI supports a smart card interface,
which is a serial communications feature for IC card interfaces that conforms to the ISO/IEC
standard 7816-3 for identification cards data transmission protocol type T = 0. See section 18,
Smart Card Interface, for more information.
17.1.1
Features
Select asynchronous or clock synchronous as the serial communications mode.
• Asynchronous mode:
Serial data communications are synched by start-stop in character units. The SCI can
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. It can also communicate with two or more other
processors using the multiprocessor communication function. There are 12 selectable serial
data communication formats.
Data length: Seven or eight bits
Stop bit length: One or two bits
Parity: Even, odd, or none
Multiprocessor bit: 1 or 0
Receive error detection: Parity, overrun, and framing errors
Break detection: By reading the RxD level directly from the port SC data register
(SCSPTR) when a framing error occurs
• Clock synchronous mode:
Serial data communication is synchronized with a clock signal. The SCI can communicate
with other chips having a clock synchronous communication function. There is one serial
data communication format.
Data length: Eight bits
Receive error detection: Overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the
SCI can transmit and receive simultaneously. Both sections use double buffering, so
continuous data transfer is possible in both the transmit and receive directions.
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Section 17 Serial Communication Interface (SCI)
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)
• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently.
• When the SCI is not in use, it can be stopped by halting the clock supplied to it, saving power.
17.1.2
Block Diagram
Bus interface
Figure 17.1 shows an SCI block diagram.
Module data bus
SCRDR
RxD0
TxD0
SCRSR
SCTDR
SCTSR
SCPCR
SCPDR
SCSSR
SCSSR
SCSCR
SCSMR
Transmit/
receive
control
Parity check
SCBRR
Baud rate
generator
Pφ/64
External clock
SCI
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
SCSCR:
SCSSR:
SCBRR:
SCPDR:
SCPCR:
Serial control register
Serial status register
Bit rate register
SC port data register
SC port control register
Figure 17.1 SCI Block Diagram
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Pφ/4
Pφ/16
Legend:
SCRSR:
SCRDR:
SCTSR:
SCTDR:
SCSMR:
Pφ
Clock
Parity generation
SCK0
Internal
data bus
TEI
TXI
RXI
ERI
Section 17 Serial Communication Interface (SCI)
Figures 17.2 to 17.4 show the block diagrams of the SCI I/O port.
SCI pin I/O and data control is performed by bits 3 to 0 of SCPCR and bits 1 and 0 of SCPDR. For
details, see section 17.2.8, Port SC Control Register (SCPCR)/Port SC Data Register (SCPDR).
Reset
R
D
SCP1MD0
Q
C
Internal data bus
PCRW
Reset
Q
R
D
SCP1MD1
C
SCI
PCRW
Reset
SCPT[1]/SCK0
Clock input enable
R
Q
D
SCP1DT1
C
PDRW
Output enable
Serial clock output
PDRR*
Serial clock input
Legend:
PDRW: SCPDR write
PDRR: SCPDR read
PCRW: SCPCR write
Note: * When reading the SCK0 pin, clear the C/A bit in SCSMR and the CKE1 and CKE0
bits in SCSCR to 0, and set the SCP1MD1 bit in SCPCR to 1 (see section 17.2.8).
Figure 17.2 SCPT[1]/SCK0 Pin
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Section 17 Serial Communication Interface (SCI)
Reset
R
D
SCP0MD0
Q
C
PCRW
Reset
Q
Internal data bus
R
D
SCP0MD1
C
PCRW
Reset
SCPT[0]/TxD0
R
Q
D
SCP0DT1
C
SCI
PDRW
Output enable
Serial
transmission
output
Legend:
PCRW: SCPCR write
PDRW: SCPDR write
Figure 17.3 SCPT[0]/TxD0 Pin
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Section 17 Serial Communication Interface (SCI)
SCI
SCPT[0]/RxD0
Serial
receive
data
Internal data bus
PDRR*
Legend:
PDRR: PDR read
Note: * When reading the RxD0 pin, set the RE bit in SCSCR to 1.
Figure 17.4 SCPT[0]/RxD0 Pin
17.1.3
Pin Configuration
The SCI has the serial pins summarized in table 17.1.
Table 17.1 SCI Pins
Pin Name
Abbreviation
I/O
Function
Serial clock pin
SCK0
I/O
Clock I/O
Receive data pin
RxD0
Input
Receive data input
Transmit data pin
TxD0
Output
Transmit data output
Note: They are made to function as serial pins by performing SCI operation settings with the TE,
RE, CKEI, and CKEO bits in SCSCR and the C/A bit in SCSMR. Break state transmission
and detection can be performed by means of the SCI’s SCSPTR register.
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Section 17 Serial Communication Interface (SCI)
17.1.4
Register Configuration
Table 17.2 summarizes the SCI internal registers. These registers select the communication mode
(asynchronous or clock synchronous), specify the data format and bit rate, and control the
transmitter and receiver sections.
Table 17.2 Registers
Name
Abbreviation
R/W
Initial Value
Address
Access size
Serial mode register
SCSMR
R/W
H'00
H'FFFFFE80
8
Bit rate register
SCBRR
R/W
H'FF
H'FFFFFE82
8
Serial control register
SCSCR
R/W
H'00
H'FFFFFE84
8
Transmit data register
SCTDR
R/W
H'FFFFFE86
8
Serial status register
SCSSR
H'FF
1
*
R/(W)
H'84
H'FFFFFE88
8
Receive data register
SCRDR
R
H'00
H'FFFFFE8A
8
Port SC data register
SCPDR
R/W
H'00
H'04000136
8
2
(H'A4000136)*
Port SC control register
SCPCR
R/W
H'8008
H'04000116
16
2
(H'A4000116)*
Notes: Registers with addresses beginning at H'04 are located in area 1 of physical space.
Consequently, when the cache is on, either access these registers from the P2 area of
logical space or else make an appropriate setting using the MMU so that these registers
are not cached.
1. The only value that can be written is 0 to clear the flags.
2. When address translation by the MMU is not executed, the address in parentheses
should be used.
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Section 17 Serial Communication Interface (SCI)
17.2
Register Descriptions
17.2.1
Receive Shift Register (SCRSR)
Bit:
7
6
5
4
3
2
1
0
R/W:
—
—
—
—
—
—
—
—
The receive shift register (SCRSR) receives serial data.
Data input at the RxD0 pin is loaded into the SCRSR in the order received, LSB (bit 0) first,
converting the data to parallel form. When one byte has been received, it is automatically
transferred to the SCRDR.
The CPU cannot read or write the SCRSR directly.
17.2.2
Receive Data Register (SCRDR)
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
The receive data register (SCRDR) stores serial receive data.
The SCI completes the reception of one byte of serial data by moving the received data from the
receive shift register (SCRSR) into the SCRDR for storage. The SCRSR is then ready to receive
the next data.
This double buffering allows the SCI to receive data continuously.
The CPU can read but not write to SCRDR. SCRDR is initialized to H'00 by a reset and in standby
or module standby mode.
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Section 17 Serial Communication Interface (SCI)
17.2.3
Transmit Shift Register (SCTSR)
Bit:
7
6
5
4
3
2
1
0
R/W:
—
—
—
—
—
—
—
—
The transmit shift register (SCTSR) transmits serial data.
The SCI loads transmit data from the transmit data register (SCTDR) into the SCTSR, then
transmits the data serially from the TxD0 pin, LSB (bit 0) first.
After transmitting one-byte data, the SCI automatically loads the next transmit data from the
SCTDR into the SCTSR and starts transmitting again. If the TDRE bit of the SCSSR is 1,
however, the SCI does not load the SCTDR contents into the SCTSR.
The CPU cannot read or write the SCTSR directly.
17.2.4
Transmit Data Register (SCTDR)
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The transmit data register (SCTDR) is an eight-bit register that stores data for serial transmission.
When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data
written in the SCTDR into the SCTSR and starts serial transmission. Continuous serial
transmission is possible by writing the next transmit data in the SCTDR during serial transmission
from the SCTSR.
The CPU can always read and write the SCTDR. The SCTDR is initialized to H'FF by a reset or in
standby and module standby modes.
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Section 17 Serial Communication Interface (SCI)
17.2.5
Serial Mode Register (SCSMR)
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The serial mode register (SCSMR) is an eight-bit register that specifies the SCI serial
communication format and selects the clock source for the baud rate generator.
The CPU can always read and write the SCSMR.
The SCSMR is initialized to H'00 by a reset or in standby and module standby modes.
Bit 7—Communication Mode (C/A
A): Selects whether the SCI operates in the asynchronous or
clock synchronous mode.
Bit 7: C/A
A
Description
0
Asynchronous mode
1
Clock synchronous mode
(Initial value)
Bit 6—Character Length (CHR): Selects seven-bit or eight-bit data in the asynchronous mode.
In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Bit 6: CHR
Description
0
Eight-bit data
1
Seven-bit data*
(Initial value)
Note: * When seven-bit data is selected, the MSB (bit 7) of the transmit data register is not
transmitted.
Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data, in the asynchronous mode. In the clock synchronous mode, a parity bit is
neither added nor checked, regardless of the PE setting.
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Section 17 Serial Communication Interface (SCI)
Bit 5: PE
Description
0
Parity bit not added or checked
1
Parity bit added and checked*
(Initial value)
Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the
parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E)
mode setting.
Bit 4—Parity Mode (O/E
E): Selects even or odd parity when parity bits are added and checked.
The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set
to 1 to enable parity addition and check. The O/E setting is ignored in the clock synchronous
mode, or in the asynchronous mode when parity addition and check is disabled.
Bit 4: O/E
E
Description
0
Even parity*
2
Odd parity*
1
1
(Initial value)
Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even
number of 1s in the transmitted character and parity bit combined. Receive data is
checked to see if it has an even number of 1s in the received character and parity bit
combined.
2. If odd parity is selected, the parity bit is added to transmit data to make an odd number
of 1s in the transmitted character and parity bit combined. Receive data is checked to
see if it has an odd number of 1s in the received character and parity bit combined.
Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in the
asynchronous mode. This setting is used only in the asynchronous mode. It is ignored in the clock
synchronous mode because no stop bits are added.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of
the next incoming character.
Bit 3: STOP
Description
0
One stop bit *
2
Two stop bits*
1
1
(Initial value)
Notes: 1. In transmitting, a single bit of 1 is added at the end of each transmitted character.
2. In transmitting, two bits of 1 are added at the end of each transmitted character.
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Section 17 Serial Communication Interface (SCI)
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit
setting is used only in the asynchronous mode; it is ignored in the clock synchronous mode. For
the multiprocessor communication function, see section 17.3.3, Multiprocessor Communication.
Bit 2: MP
Description
0
Multiprocessor function disabled
1
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source of the on-chip baud rate generator. Four clock sources are available. Pφ, Pφ/4, Pφ/16 and
Pφ/64. For further information on the clock source, bit rate register settings, and baud rate, see
section 17.2.9, Bit Rate Register (SCBRR).
Bit 1: CKS1
Bit 0: CKS0
Description
0
0
Pφ
1
Pφ/4
0
Pφ/16
1
Pφ/64
1
(Initial value)
Note: Pφ: Peripheral clock
17.2.6
Serial Control Register (SCSCR)
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock
output in the asynchronous mode, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write the SCSCR. The SCSCR is
initialized to H'00 by a reset or in standby and module standby modes.
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Section 17 Serial Communication Interface (SCI)
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the transmit data register empty bit (TDRE) in the serial status register
(SCSSR) is set to 1 due to transfer of serial transmit data from the SCTDR to the SCTSR.
Bit 7: TIE
Description
0
Transmit-data-empty interrupt request (TXI) is disabled*
1
Transmit-data-empty interrupt request (TXI) is enabled
(Initial value)
Note: * The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then
clearing TDRE to 0, or by clearing TIE to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)
requested when the receive data register full bit (RDRF) in the serial status register (SCSSR) is set
to 1 due to transfer of serial receive data from the SCRSR to the SCRDR. It also enables or
disables receive-error interrupt (ERI) requests.
Bit 6: RIE
Description
0
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are
disabled*
(Initial value)
1
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are
enabled
Note: * RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag
(FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing
RIE to 0.
Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter.
Bit 5: TE
Description
0
Transmitter disabled*
2
Transmitter enabled*
1
1
(Initial value).
Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SCSSR) is
fixed to 1.
2. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial
status register (SCSSR) is cleared to 0 after writing of transmit data into the SCTDR.
Select the transmit format in the SCSMR before setting TE to 1.
Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver.
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Section 17 Serial Communication Interface (SCI)
Bit 4: RE
Description
0
Receiver disabled*
2
Receiver enabled*
1
1
(Initial value)
Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These
flags retain their previous values.
2. Serial reception starts when a start bit is detected in the asynchronous mode, or
synchronous clock input is detected in the clock synchronous mode. Select the receive
format in the SCSMR before setting RE to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode bit
(MP) in the serial mode register (SCSMR) is set to 1 during reception. The MPIE setting is
ignored in the clock synchronous mode or when the MP bit is cleared to 0.
Bit 3: MPIE
Description
0
Multiprocessor interrupts are disabled (normal receive operation)
(Initial value)
[Clear conditions]
1. When MPIE is cleared to 0
2. When the multiprocessor bit (MPB) is set to 1 in receive data
1
Multiprocessor interrupts are enabled*
Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI),
and setting of the RDRF, FER, and ORER status flags in the serial status register
(SCSSR) are disabled until data with a multiprocessor bit of 1 is received.
Note: * The SCI does not transfer receive data from the SCRSR to the SCRDR, does not detect
receive errors, and does not set the RDRF, FER, and ORER flags in the serial status
register (SCSSR). When it receives data that includes MPB = 1, the SCSSR’s MPB flag is
set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if
the TIE and RIE bits in the SCSCR are set to 1), and allows the FER and ORER bits to be
set.
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if SCTDR does not contain new transmit data when the MSB is transmitted.
Bit 2: TEIE
Description
0
Transmit-end interrupt (TEI) requests are disabled*
1
Transmit-end interrupt (TEI) requests are enabled*
(Initial value)
Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register
(SCSSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end
(TEND) bit to 0, or by clearing the TEIE bit to 0.
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Section 17 Serial Communication Interface (SCI)
Bits 1 and 0—Clock Enable 1 and 0 (CKE1 and CKE0): These bits select the SCI clock source
and enable or disable clock output from the SCK0 pin. Depending on the combination of CKE1
and CKE0, the SCK0 pin can be used for serial clock output or serial clock input.
The CKE0 setting is valid only when the asynchronous mode and the internal clock are selected
(CKE1 = 0). The CKE0 setting is ignored in the clock synchronous mode, or when an external
clock source is selected (CKE1 = 1). Before selecting the SCI operating mode in the serial mode
register (SCSMR), set CKE1 and CKE0. For further details on selection of the SCI clock source,
see table 17.10 in section 17.3, Operation.
Bit 1:
CKE1
Bit 0:
CKE0
Description
0
0
Asynchronous mode
Internal clock, SCK pin used for input pin (input
1
signal is ignored)*
Clock synchronous mode
Internal clock, SCK pin used for synchronous clock
1
output*
2
Internal clock, SCK pin used for clock output*
1
Asynchronous mode
Clock synchronous mode
1
0
Asynchronous mode
Clock synchronous mode
1
Asynchronous mode
Clock synchronous mode
Internal clock, SCK pin used for synchronous clock
output
3
External clock, SCK pin used for clock input*
External clock, SCK pin used for synchronous clock
input
3
External clock, SCK pin used for clock input*
External clock, SCK pin used for synchronous clock
input
Notes: 1. Initial value
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
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Section 17 Serial Communication Interface (SCI)
17.2.7
Serial Status Register (SCSSR)
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
1
0
0
0
0
1
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Note: * The only value that can be written is a 0 to clear the flag.
The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and
status flags that indicate SCI operating state.
The CPU can always read and write the SCSSR, but cannot write 1 in the status flags (TDRE,
RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written.
The SCSSR is initialized to H'84 by a reset or in standby and module standby modes.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from the SCTDR into the SCTSR and new serial transmit data can be written in the SCTDR.
Bit 7: TDRE
Description
0
SCTDR contains valid transmit data
[Clear condition]
When software reads TDRE after it has been set to 1, then writes 0 in TDRE or
data is written in SCTDR.
1
SCTDR does not contain valid transmit data
(Initial value)
[Setting conditions]
1. When the chip is reset or enters standby mode
2. When the TE bit in the serial control register (SCSCR) is cleared to 0
3. When SCTDR contents are loaded into SCTSR, so new data can be written
in SCTDR.
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Section 17 Serial Communication Interface (SCI)
Bit 6—Receive Data Register Full (RDRF): Indicates that SCRDR contains received data.
Bit 6: RDRF
Description
0
SCRDR does not contain valid received data
(Initial value)
[Clear conditions]
1. When the chip is reset or enters standby mode
2. When software reads RDRF after it has been set to 1, then writes 0 in RDRF.
1
SCRDR contains valid received data
[Setting condition]
When serial data is received normally and transferred from SCRSR to SCRDR.
Note: The SCRDR and RDRF are not affected by detection of receive errors or by clearing of the
RE bit to 0 in the serial control register. They retain their previous contents.
If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER)
occurs and the received data is lost.
Bit 5—Overrun Error (ORER): Indicates that data reception aborted due to an overrun error.
Bit 5: ORER
Description
0
Receiving is in progress or has ended normally*
1
(Initial value)
[Clear conditions]
1. When the chip is reset or enters standby mode
2. When ORER=1 is read and then 0 is written to ORER.
1
A receive overrun error occurred*
2
[Setting condition]
When reception of the next serial data ends when RDRF is set to 1.
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which
retains its previous value.
2. SCRDR continues to hold the data received before the overrun error, so subsequent
receive data is lost. Serial receiving cannot continue while ORER is set to 1. In the
clock synchronous mode, serial transmitting is also disabled.
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Section 17 Serial Communication Interface (SCI)
Bit 4—Framing Error (FER): Indicates that data reception aborted due to a framing error in the
asynchronous mode.
Bit 4: FER
Description
0
1
Receiving is in progress or has ended normally*
(Initial value)
[Clear conditions]
1. When the chip is reset or enters standby mode
2. When FER=1 is read and then 0 is written to FER.
1
A receive framing error occurred
FER is set to 1 if the stop bit at the end of receive data is checked and found to
2
be 0.*
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which
retains its previous value.
2. When the stop bit length is two bits, only the first bit is checked. The second stop bit is
not checked. When a framing error occurs, the SCI transfers the receive data into the
SCRDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1.
In the clock synchronous mode, serial transmitting is also disabled.
Bit 3—Parity Error (PER): Indicates that data reception (with parity) aborted due to a parity
error in the asynchronous mode.
Bit 3: PER
Description
0
1
Receiving is in progress or has ended normally*
(Initial value)
[Clear conditions]
1. When the chip is reset or enters standby mode
1
2. When PER=1 is read and then 0 is written to PER.
2
A receive parity error occurred*
[Setting condition]
When the number of 1s in receive data, including the parity bit, does not match
the even or odd parity setting of the parity mode bit (O/E) in the serial mode
register (SCSMR).
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which
retains its previous value.
2. When a parity error occurs, the SCI transfers the receive data into the SCRDR but does
not set RDRF. Serial receiving cannot continue while PER is set to 1. In the clock
synchronous mode, serial transmitting is also disabled.
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Section 17 Serial Communication Interface (SCI)
Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, the SCTDR did not contain valid data, so transmission has ended. TEND is a readonly bit and cannot be written.
Bit 2: TEND
Description
0
Transmission is in progress
[Clear condition]
When TDRE=1 is read and then 0 is written to TDRE.
1
End of transmission
(Initial value)
[Setting conditions]
1. When the chip is reset or enters standby mode
2. When TE is cleared to 0 in the serial control register (SCSCR)
3. If TDRE is 1 when the last bit of a one-byte serial character is transmitted.
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is selected for receiving in the asynchronous mode. The MPB is a
read-only bit and cannot be written.
Bit 1: MPB
Description
0
Multiprocessor bit value in receive data is 0*
1
Multiprocessor bit value in receive data is 1
(Initial value)
Note: * If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its
previous value.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode.
The MPBT setting is ignored in the clock synchronous mode, when a multiprocessor format is not
selected, or when the SCI is not transmitting.
Bit 0: MPBT
Description
0
Multiprocessor bit value in transmit data is 0
1
Multiprocessor bit value in transmit data is 1
Rev. 5.00 Dec 12, 2005 page 498 of 1034
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(Initial value)
Section 17 Serial Communication Interface (SCI)
17.2.8
Port SC Control Register (SCPCR)/Port SC Data Register (SCPDR)
The port SC control register (SCPCR) and port SC data register (SCPDR) control I/O and data for
the port multiplexed with the serial communication interface (SCI) pins.
SCPCR settings are used to perform I/O control, to enable data written in SCPDR to be output to
the TxD0 pin, and input data to be read from the RxD0 pin, and to control serial
transmission/reception breaks.
It is also possible to read data on the SCK0 pin, and write output data.
SCPCR
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCP7 SCP7 SCP6 SCP6 SCP5 SCP5 SCP4 SCP4 SCP3 SCP3 SCP2 SCP2 SCP1 SCP1 SCP0 SCP0
MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0
Initial value:
R/W:
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCPDR
Bit:
7
6
5
4
3
2
1
0
SCP7DT
SCP6DT
SCP5DT
SCP4DT
SCP3DT
SCP2DT
SCP1DT
SCP0DT
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCI pin I/O and data control are performed by bits 3 to 0 of SCPCR and bits 1 and 0 of SCPDR.
SCPCR Bits 3 and 2—Serial Clock Port I/O (SCP1MD1, SCP1MD0): These bits specify serial
port SCK0 pin I/O. When the SCK0 pin is actually used as a port I/O pin, clear the C/A bit of
SCSMR and bits CKE1 and CKE0 of SCSCR to 0.
Bit 3:
SCP1MD1
Bit 2:
SCP1MD0
Description
0
0
SCP1DT bit value is not output to SCK0 pin
1
SCP1DT bit value is output to SCK0 pin
0
SCK0 pin value is read from SCP1DT bit
1
(Initial values: 1 and 0)
1
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Section 17 Serial Communication Interface (SCI)
SCPDR Bit 1—Serial Clock Port Data (SCP1DT): Specifies the serial port SCK0 pin I/O data.
Input or output is specified by the SCP1MD0 and SCP1MD1 bits. In output mode, the value of
the SCP1DT bit is output from the SCK0 pin.
Bit 1:
SCP1DT
Description
0
I/O data is low
1
I/O data is high
(Initial value)
SCPCR Bits 1 and 0—Serial Port Break I/O (SCP0MD1, SCP0MD0): These bits specify the
serial port TxD0 pin output condition. When the TxD0 pin is actually used as a port output pin
and outputs the value set with the SCP0DT bit, clear the TE bit of SCSCR to 0.
Bit 1:
SCP0MD1
Bit 0:
SCP0MD0
Description
0
0
SCP0DT bit value is not output to TxD0 pin
0
1
SCP0DT bit value is output to TxD0 pin
(Initial value)
SCPDR Bit 0—Serial Port Break Data (SCP0DT): Specifies the serial port RxD0 pin input data
and TxD0 pin output data. The TxD0 pin output condition is specified by the SCP0MD0 and
SCP0MD1 bits. When the TxD0 pin is set to output mode, the value of the SCP0DT bit is output
to the TxD0 pin. The RxD0 pin value is read from the SCP0DT bit regardless of the values of the
SCP0MD0 and SCP0MD1 bits, if RE in the SCSCR is set to 1. The initial value of this bit after a
power-on reset is undefined.
Bit 0:
SCP0DT
Description
0
I/O data is low
1
I/O data is high
(Initial value)
Block diagrams of the SCI I/O ports are shown in figures 17.2 to 17.4.
17.2.9
Bit Rate Register (SCBRR)
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
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Section 17 Serial Communication Interface (SCI)
The bit rate register (SCBRR) is an eight-bit register that, together with the baud rate generator
clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR),
determines the serial transmit/receive bit rate.
The CPU can always read and write the SCBRR.
The SCBRR is initialized to H'FF by a reset or in module standby or standby mode. Each channel
has independent baud rate generator control, so different values can be set in two channels.
The SCBRR setting is calculated as follows:
Asynchronous mode: N =
Clock synchronous mode: N =
B:
N:
Pφ:
n:
Pφ
64 × 2
2n–1
×B
Pφ
8×2
2n–1
×B
× 106 – 1
× 106 – 1
Bit rate (bit/s)
SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency for peripheral modules (MHz)
Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 17.3.)
Table 17.3 SCSMR Settings
SCSMR Settings
n
Clock Source
CKS1
CKS0
0
Pφ
0
0
1
Pφ/4
0
1
2
Pφ/16
1
0
3
Pφ/64
1
1
Note: Find the bit rate error for the asynchronous mode by the following formula:
Error (%) =
Pφ × 106
(N + 1) × B × 64 × 22n–1
–1
× 100
Table 17.4 lists examples of SCBRR settings in the asynchronous mode; table 17.5 lists examples
of SCBRR settings in the clock synchronous mode.
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Section 17 Serial Communication Interface (SCI)
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1)
Pφ
φ (MHz)
2
2.097152
2.4576
Bit Rate
(bits/s)
n
N
Error (%
%)
n
N
Error (%
%)
n
N
Error (%
%)
110
1
141
0.03
1
148
–0.04
1
174
–0.26
150
1
103
0.16
1
108
0.21
1
127
0.00
300
0
207
0.16
0
217
0.21
0
255
0.00
600
0
103
0.16
0
108
0.21
0
127
0.00
1200
0
51
0.16
0
54
–0.70
0
63
0.00
2400
0
25
0.16
0
26
1.14
0
31
0.00
4800
0
12
0.16
0
13
–2.48
0
15
0.00
9600
0
6
–6.99
0
6
–2.48
0
7
0.00
19200
0
2
8.51
0
2
13.78
0
3
0.00
31250
0
1
0.00
0
1
4.86
0
1
22.88
38400
0
1
–18.62
0
1
–14.67
0
1
0.00
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (2)
Pφ
φ (MHz)
3
3.6864
4
Bit Rate
(bits/s)
n
N
Error (%
%)
n
N
Error (%
%)
n
N
Error (%
%)
110
1
212
0.03
2
64
0.70
2
70
0.03
150
1
155
0.16
1
191
0.00
1
207
0.16
300
1
77
0.16
1
95
0.00
1
103
0.16
600
0
155
0.16
0
191
0.00
0
207
0.16
1200
0
77
0.16
0
95
0.00
0
103
0.16
2400
0
38
0.16
0
47
0.00
0
51
0.16
4800
0
19
–2.34
0
23
0.00
0
25
0.16
9600
0
9
–2.34
0
11
0.00
0
12
0.16
19200
0
4
–2.34
0
5
0.00
0
6
–6.99
31250
0
2
0.00
—
—
—
0
3
0.00
38400
—
—
—
0
2
0.00
0
2
8.51
Rev. 5.00 Dec 12, 2005 page 502 of 1034
REJ09B0254-0500
Section 17 Serial Communication Interface (SCI)
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (3)
Pφ
φ (MHz)
4.9152
5
6
Bit Rate
(bits/s)
n
N
Error (%
%)
n
N
Error (%
%)
n
N
Error (%
%)
110
2
86
0.31
2
88
–0.25
2
106
–0.44
150
1
255
0.00
2
64
0.16
2
77
0.16
300
1
127
0.00
1
129
0.16
1
155
0.16
600
0
255
0.00
1
64
0.16
1
77
0.16
1200
0
127
0.00
0
129
0.16
0
155
0.16
2400
0
63
0.00
0
64
0.16
0
77
0.16
4800
0
31
0.00
0
32
–1.36
0
38
0.16
9600
0
15
0.00
0
15
1.73
0
19
–2.34
19200
0
7
0.00
0
7
1.73
0
9
–2.34
31250
0
4
–1.70
0
4
0.00
0
5
0.00
38400
0
3
0.00
0
3
1.73
0
4
–2.34
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (4)
Pφ
φ (MHz)
6.144
7.3728
8
Bit Rate
(bits/s)
n
N
Error (%
%)
n
N
Error (%
%)
n
N
Error (%
%)
110
2
108
0.08
2
130
–0.07
2
141
0.03
150
2
79
0.00
2
95
0.00
2
103
0.16
300
1
159
0.00
1
191
0.00
1
207
0.16
600
1
79
0.00
1
95
0.00
1
103
0.16
1200
0
159
0.00
0
191
0.00
0
207
0.16
2400
0
79
0.00
0
95
0.00
0
103
0.16
4800
0
39
0.00
0
47
0.00
0
51
0.16
9600
0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
2.40
0
6
5.33
0
7
0.00
38400
0
4
0.00
0
5
0.00
0
6
–6.99
Rev. 5.00 Dec 12, 2005 page 503 of 1034
REJ09B0254-0500
Section 17 Serial Communication Interface (SCI)
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (5)
Pφ
φ (MHz)
9.8304
10
12
12.288
Bit Rate
(bits/s)
n
N
Error
(%
%)
n
N
Error
(%
%)
n
N
Error
(%
%)
n
N
Error
(%
%)
110
2
174
–0.26
2
177
–0.25
2
212
0.03
2
217
0.08
150
2
127
0.00
2
129
0.16
2
155
0.16
2
159
0.00
300
1
255
0.00
2
64
0.16
2
77
0.16
2
79
0.00
600
1
127
0.00
1
129
0.16
1
155
0.16
1
159
0.00
1200
0
255
0.00
1
64
0.16
1
77
0.16
1
79
0.00
2400
0
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
4800
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
31
0.00
0
32
–1.36
0
38
0.16
0
39
0.00
19200
0
15
0.00
0
15
1.73
0
19
0.16
0
19
0.00
31250
0
9
–1.70
0
9
0.00
0
11
0.00
0
11
2.40
38400
0
7
0.00
0
7
1.73
0
9
–2.34
0
9
0.00
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (6)
Pφ
φ (MHz)
14.7456
16
19.6608
20
Bit Rate
(bits/s)
n
N
Error
(%
%)
n
N
Error
(%
%)
n
N
Error
(%
%)
n
N
Error
(%
%)
110
3
64
0.70
3
70
0.03
3
86
0.31
3
88
–0.25
150
2
191
0.00
2
207
0.16
2
255
0.00
3
64
0.16
300
2
95
0.00
2
103
0.16
2
127
0.00
2
129
0.16
600
1
191
0.00
1
207
0.16
1
255
0.00
2
64
0.16
1200
1
95
0.00
1
103
0.16
1
127
0.00
1
129
0.16
2400
0
191
0.00
0
207
0.16
0
255
0.00
1
64
0.16
4800
0
95
0.00
0
103
0.16
0
127
0.00
0
129
0.16
9600
0
47
0.00
0
51
0.16
0
63
0.00
0
64
0.16
19200
0
23
0.00
0
25
0.16
0
31
0.00
0
32
–1.36
31250
0
14
–1.70
0
15
0.00
0
19
–1.70
0
19
0.00
38400
0
11
0.00
0
12
0.16
0
15
0.00
0
15
1.73
Rev. 5.00 Dec 12, 2005 page 504 of 1034
REJ09B0254-0500
Section 17 Serial Communication Interface (SCI)
Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (7)
Pφ
φ (MHz)
24
24.576
28.7
30
Bit Rate
(bits/s)
n
N
Error
(%
%)
n
N
Error
(%
%)
n
N
Error
(%
%)
n
N
Error
(%
%)
110
3
106
–0.44
3
108
0.08
3
126
0.31
3
132
0.13
150
3
77
0.16
3
79
0.00
3
92
0.46
3
97
–0.35
300
2
155
0.16
2
159
0.00
2
186
–0.08
2
194
0.16
600
2
77
0.16
2
79
0.00
2
92
0.46
2
97
–0.35
1200
1
155
0.16
1
159
0.00
1
186
–0.08
1
194
0.16
2400
1
77
0.16
1
79
0.00
1
92
0.46
1
97
–0.35
4800
0
155
0.16
0
159
0.00
0
186
–0.08
0
194
–1.36
9600
0
77
0.16
0
79
0.00
0
92
0.46
0
97
–0.35
19200
0
38
0.16
0
39
0.00
0
46
–0.61
0
48
–0.35
31250
0
23
0.00
0
24
–1.70
0
28
–1.03
0
29
0.00
38400
0
19
–2.34
0
19
0.00
0
22
1.55
0
23
1.73
Rev. 5.00 Dec 12, 2005 page 505 of 1034
REJ09B0254-0500
Section 17 Serial Communication Interface (SCI)
Table 17.5 Bit Rates and SCBRR Settings in Clock Synchronous Mode
Pφ
φ (MHz)
4
8
16
28.7
30
Bit Rate
(bits/s)
n
N
n
N
n
N
n
N
n
N
110
—
—
—
—
—
—
—
—
—
—
250
2
249
3
124
3
249
—
—
—
—
500
2
124
2
249
3
124
3
223
3
233
1k
1
249
2
124
2
249
3
111
3
116
2.5k
1
99
1
199
2
99
2
178
2
187
5k
0
199
1
99
1
199
2
89
2
93
10k
0
99
0
199
1
99
1
178
1
187
25k
0
39
0
79
0
159
1
71
1
74
50k
0
19
0
39
0
79
0
143
0
149
100k
0
9
0
19
0
39
0
71
0
74
250k
0
3
0
7
0
15
—
—
0
29
500k
0
1
0
3
0
7
—
—
0
14
1M
0
0*
0
1
0
3
—
—
—
—
0
0*
0
1
—
—
—
—
2M
Notes: Settings with an error of 1% or less are recommended.
Blank: No setting possible
—:
Setting possible, but error occurs. (Refer to section 17.2.9, Bit Rate Register
(SCBRR))
*:
Continuous transmit/receive not possible as transfer capability to the buffer
becomes insufficient.
Rev. 5.00 Dec 12, 2005 page 506 of 1034
REJ09B0254-0500
Section 17 Serial Communication Interface (SCI)
Table 17.6 indicates the maximum bit rates in the asynchronous mode when the baud rate
generator is being used. Tables 17.7 and 17.8 list the maximum rates for external clock input.
Table 17.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)
Settings
Pφ
φ (MHz)
Maximum Bit Rate (bits/s)
n
N
2
62500
0
0
2.097152
65536
0
0
2.4576
76800
0
0
3
93750
0
0
3.6864
115200
0
0
4
125000
0
0
4.9152
153600
0
0
8
250000
0
0
9.8304
307200
0
0
12
375000
0
0
14.7456
460800
0
0
16
500000
0
0
19.6608
614400
0
0
20
625000
0
0
24
750000
0
0
24.576
768000
0
0
28.7
896875
0
0
30
937500
0
0
Rev. 5.00 Dec 12, 2005 page 507 of 1034
REJ09B0254-0500
Section 17 Serial Communication Interface (SCI)
Table 17.7 Maximum Bit Rates during External Clock Input (Asynchronous Mode)
Pφ
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
2
0.5000
31250
2.097152
0.5243
32768
2.4576
0.6144
38400
3
0.7500
46875
3.6864
0.9216
57600
4
1.0000
62500
4.9152
1.2288
76800
8
2.0000
125000
9.8304
2.4576
153600
12
3.0000
187500
14.7456
3.6864
230400
16
4.0000
250000
19.6608
4.9152
307200
20
5.0000
312500
24
6.0000
375000
24.576
6.1440
384000
28.7
7.1750
448436
30
7.5000
468750
Table 17.8 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode)
Pφ
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
8
1.3333
1333333.3
16
2.6667
2666666.7
24
4.0000
4000000.0
28.7
4.7833
4783333.3
30
5.0000
5000000.0
Rev. 5.00 Dec 12, 2005 page 508 of 1034
REJ09B0254-0500
Section 17 Serial Communication Interface (SCI)
17.3
Operation
17.3.1
Overview
For serial communication, the SCI has an asynchronous mode in which characters are
synchronized individually, and a clock synchronous mode in which communication is
synchronized with clock pulses.
Asynchronous/clock synchronous mode and the transmission format are selected in the serial
mode register (SCSMR), as listed in table 17.9. The SCI clock source is selected by the
combination of the C/A bit in the serial mode register (SCSMR) and the CKE1 and CKE0 bits in
the serial control register (SCSCR), as listed in table 17.10.
Asynchronous Mode:
• Data length is selectable: seven or eight bits.
• Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The
combination of the preceding selections constitutes the communication format and character
length.
• In receiving, it is possible to detect framing errors, parity errors, overrun errors and breaks.
• An internal or external clock can be selected as the SCI clock source.
When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and can output a serial clock signal with a frequency matching the bit rate.
When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The on-chip baud rate generator is not used.)
Clock Synchronous Mode:
• The transmission/reception format has a fixed eight-bit data length.
• In receiving, it is possible to detect overrun errors.
• An internal or external clock can be selected as the SCI clock source.
When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and outputs a synchronous clock signal to external devices.
When an external clock is selected, the SCI operates on the input synchronous clock. The
on-chip baud rate generator is not used.
Rev. 5.00 Dec 12, 2005 page 509 of 1034
REJ09B0254-0500
Section 17 Serial Communication Interface (SCI)
Table 17.9 Serial Mode Register Settings and SCI Communication Formats
SCSMR Settings
SCI Communication Format
Bit 7 Bit 6
C/A
A CHR
Bit 5
PE
Bit 2
MP
Bit 3
STOP
Mode
Data
Length
Parity
Bit
Multipro- Stop Bit
cessor Bit Length
0
0
0
0
Asynchronous
8-bit
Not set
Not set
0
1
1
2 bits
0
Set
1 bit
1
1
0
2 bits
0
7-bit
Not set
1 bit
1
1
2 bits
0
Set
1 bit
1
0
*
1
1
*
1
1
*
0
*
1
*
*
2 bits
0
*
1 bit
Asynchronous
(multiprocessor
format)
8-bit
Not set
Set
1 bit
2 bits
7-bit
1 bit
2 bits
Clock
synchronous
*
8-bit
Not set
None
Note: * Don’t care.
Table 17.10 SCSMR and SCSCR Settings and SCI Clock Source Selection
SCSMR
SCSCR Settings
Bit 7
C/A
A
Bit 1
CKE1
Bit 0
CKE0
0
0
0
1
1
SCI Transmit/Receive Clock
Mode
Asynchronous
mode
0
Clock
Source
SCK0
Pin Function
Internal
SCI does not use the SCK0 pin
Outputs a clock with frequency
matching the bit rate
External
Inputs a clock with frequency 16
times the bit rate
Internal
Outputs the synchronous clock
External
Inputs the synchronous clock
1
1
0
0
1
1
0
Clock
synchronous
mode
1
Rev. 5.00 Dec 12, 2005 page 510 of 1034
REJ09B0254-0500
Section 17 Serial Communication Interface (SCI)
17.3.2
Operation in Asynchronous Mode
In the asynchronous mode, each transmitted or received character begins with a start bit and ends
with a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full duplex communication
is possible. The transmitter and receiver are both double buffered, so data can be written and read
while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
Figure 17.5 shows the general format of asynchronous serial communication. In asynchronous
serial communication, the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and stop bit (high), in that order.
When receiving in the asynchronous mode, the SCI synchronizes on the falling edge of the start
bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit
rate. Receive data is latched at the center of each bit.
1
Serial
data
(LSB)
0
D0
(MSB)
D1
D2
D3
D4
D5
D6
Start
bit
D7
Idling (marking)
1
0/1
1
1
Parity
bit
Stop
bit
1 or
no bit
1 or
2 bits
Transmit/receive data
7 or 8 bits
1 bit
One unit of communication data (character or frame)
Figure 17.5 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
Transmit/Receive Formats
Table 17.11 lists the 12 communication formats that can be selected in the asynchronous mode.
The format is selected by settings in the serial mode register (SCSMR).
Rev. 5.00 Dec 12, 2005 page 511 of 1034
REJ09B0254-0500
Section 17 Serial Communication Interface (SCI)
Table 17.11 Serial Communication Formats (Asynchronous Mode)
SCSMR Bits
Serial Transmit/Receive Format and Frame Length
CHR
PE
MP STOP
0
0
0
0
START
8-bit data
STOP
0
0
0
1
START
8-bit data
STOP
STOP
0
1
0
0
START
8-bit data
P
STOP
0
1
0
1
START
8-bit data
P
STOP
1
0
0
0
START
7-bit data
STOP
1
0
0
1
START
7-bit data
STOP
STOP
1
1
0
0
START
7-bit data
P
STOP
1
1
0
1
START
7-bit data
P
STOP
STOP
0
—
1
0
START
8-bit data
MPB
STOP
0
—
1
1
START
8-bit data
MPB
STOP
1
—
1
0
START
7-bit data
MPB
STOP
1
—
1
1
START
7-bit data
MPB
STOP
Notes: —:
START:
STOP:
P:
MPB:
1
2
3
Don’t care bits
Start bit
Stop bit
Parity bit
Multiprocessor bit
Rev. 5.00 Dec 12, 2005 page 512 of 1034
REJ09B0254-0500
4
5
6
7
8
9
10
11
STOP
12
STOP
STOP
Section 17 Serial Communication Interface (SCI)
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK0 pin can be selected as the SCI transmit/receive clock. The clock source is selected by the
C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control
register (SCSCR) (table 17.10).
When an external clock is input at the SCK0 pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCI operates on an internal clock, it can output a clock signal at the SCK0 pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 17.6 so that
the rising edge of the clock occurs at the center of each transmit data bit.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 17.6 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)
Transmitting and Receiving Data
SCI Initialization (Asynchronous Mode):
Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register
(SCSCR), then initialize the SCI as follows.
When changing the operation mode or communication format, always clear the TE and RE bits to
0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the
transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDRF, PER,
FER, and ORER flags or receive data register (SCRDR), which retain their previous contents.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCI operation becomes unreliable if the clock is stopped.
Figure 17.7 is a sample flowchart for initializing the SCI. The procedure for initializing the SCI is:
Rev. 5.00 Dec 12, 2005 page 513 of 1034
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Section 17 Serial Communication Interface (SCI)
Initialize
Clear TE and RE bits in SCSCR to 0
Set CKE1 and CKE0 bits in SCSCR
(TE and RE bits are 0)
(1)
Select transmit/receive
format in SCSMR
(2)
Set value to SCBRR
(3)
Wait
Has a 1-bit
interval elapsed?
No
Yes
Set TE or RE in SCSCR to 1.
Also set RIE, TIE, TEIE, and MPIE
as necessary.
(4)
(1) Select the clock source in the serial
control register (SCSCR). Leave
RIE, TIE, TEIE, MPIE, TE, and RE
cleared to 0. If clock output is
selected in asynchronous mode,
clock output starts immediately
after the setting is made to SCSCR.
(2) Select the communication format in
the serial mode register (SCSMR).
(3) Write the value corresponding to
the bit rate in the bit rate register
(SCBRR) unless an external clock
is used.
(4) Wait at least one bit interval, then
set TE or RE in the serial control
register (SCSCR) to 1. Also set
RIE, TIE, TEIE, and MPIE as
necessary. Setting TE and RE
enables the TxD and RxD pins to
be used. The initial states are the
mark transmit state, and the idle
receive state (waiting for a start bit).
End
Figure 17.7 Sample SCI Initialization Flowchart
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Section 17 Serial Communication Interface (SCI)
Serial Data Transmission (Asynchronous Mode):
Figure 17.8 shows a sample flow chart for serial data transmission. After enabling the SCI
transmission, transmit serial data following the procedure shown below:
Start transmission
Read TDRE bit in SCSSR
(1)
No
TDRE = 1?
Yes
Write transmission data to
SCTDR and clear TDRE bit in
SCSSR to 0
(2) To continue transmitting serial data:
Read the TDRE bit to check whether it
is safe to write (if it reads 1); if so, write
data in SCTDR, then clear TDRE to 0.
(2)
No
All data transmitted?
Yes
Read TEND bit in SCSSR
No
TEND = 1?
Yes
(3) To output a break at the end of serial
transmission:
Set the SC port data register (SCPDR)
and SC port control register (SCPCR),
then clear the TE bit to 0 in the serial
control register (SCSCR). For SCPCR
and SCPDR settings, see section
17.2.8, Port SC Control Register
(SCPCR)/Port SC Data Register
(SCPDR).
No
Break output?
Yes
(1) SCI status check and transmit data
write:
Read the serial status register
(SCSSR), check that the TDRE bit is 1,
then write transmit data in the transmit
data register (SCTDR) and clear TDRE
to 0.
(3)
Set SCPDR and SCPCR
Clear TE bit SCSCR to 0
End transmission
Figure 17.8 Sample Serial Transmission Flowchart
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Section 17 Serial Communication Interface (SCI)
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0, the SCI
recognizes that the transmit data register (SCTDR) contains new data, and loads this data from
the SCTDR into the transmit shift register (SCTSR).
2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and
starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the
SCSCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
a. Start bit: One 0 bit is output.
b. Transmit data: Seven or eight bits of data are output, LSB first.
c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor
bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can
also be selected.
d. Stop bit: One or two 1 bits (stop bits) are output.
e. Marking: Output of 1 bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit.
If TDRE is 0, the SCI loads new data from the SCTDR into the SCTSR, outputs the stop bit,
then begins serial transmission of the next frame.
If TDRE is 1, the SCI sets the TEND bit to 1 in the SCSSR, outputs the stop bit, then continues
output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in the SCSCR is set
to 1, a transmit-end interrupt (TEI) is requested.
Figure 17.9 shows an example of SCI transmit operation in the asynchronous mode.
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Section 17 Serial Communication Interface (SCI)
1
Serial
data
Start
bit
0
Parity Stop Start
bit
bit
bit
Data
D0
D1
D7
0/1
1
0
Parity Stop
bit
bit
Data
D0
D1
D7
0/1
1
Idle
1
(marking)
TDRE
TEND
TXI interrupt
request
generated
Writes data to
TXI interrupt
SCTDR with the
request
TXI interrupt
generated
processing routine
and clear TDRE
bit to 0
TEI interrupt
request
generated
1 frame
Figure 17.9 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
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Section 17 Serial Communication Interface (SCI)
Serial Data Reception (Asynchronous Mode):
Figure 17.10 shows a sample flow chart for serial data reception. After enabling the SCI reception,
receive serial data following the procedure shown below:
Start reception
(1) Receive error processing and
break detection:
If a receive error occurs, read
Read ORER, PER, and FER
the ORER, PER and FER bits
bits in SCSSR
of the SCSSR to identify the
error. After executing the
necessary error processing,
Yes
PER, FER, ORER = 1?
clear ORER, PER and FER all
to 0. Receiving cannot resume if
No
ORER, PER or FER remain set
(1)
to 1. When a framing error
Error processing occurs, the RxD pin can be read
to detect the break state.
Read the RDRF bit in SCSSR
No
(2)
RDRF = 1?
Yes
Read reception data of SCRDR
(3)
and clear RDRF bit in SCSSR to 0
No
All data received?
Yes
Clear the RE bit in SCSCR to 0
(2) SCI status check and receivedata read:
Read the serial status register
(SCSSR), check that RDRF is
set to 1, then read receive data
from the receive data register
(SCRDR) and clear RDRF to 0.
The RXI interrupt can also be
used to determine if the RDRF
bit has changed from 0 to 1.
(3) To continue receiving serial
data:
Read the SCRDR receive data
and clear the RDRF flag in
SCSSR to 0 before the stop bit
of the current frame is received.
End reception
Figure 17.10 Sample Serial Reception Data Flowchart (1)
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Section 17 Serial Communication Interface (SCI)
Error processing
No
ORER = 1?
Yes
Overrun error processing
No
FER = 1?
Yes
Break?
Yes
No
Framing error processing
No
Clear RE bit in SCSCR to 0
PER = 1?
Yes
Parity error processing
Clear ORER, PER, and
FER bits in SCSSR to 0
End
Figure 17.10 Sample Serial Reception Data Flowchart (2)
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Section 17 Serial Communication Interface (SCI)
In receiving, the SCI operates as follows:
1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes
internally and starts receiving.
2. Receive data is shifted into the SCRSR in order from the LSB to the MSB.
3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following
checks:
a. Parity check: The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in the SCSMR.
b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit
is checked.
c. Status check: RDRF must be 0 so that receive data can be loaded from the SCRSR into the
SCRDR.
If these checks all pass, the SCI sets RDRF to 1 and stores the received data in the SCRDR. If
one of the checks fails (receive error), the SCI operates as indicated in table 17.12.
Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1.
Be sure to clear the error flags.
4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
SCSCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER,
PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCSCR is
also set to 1, the SCI requests a receive-error interrupt (ERI).
Table 17.12 Receive Error Conditions and SCI Operation
Receive Error
Abbreviation
Condition
Data Transfer
Overrun error
ORER
Receiving of next data ends while
RDRF is still set to 1 in SCSSR
Receive data not loaded
from SCRSR into SCRDR
Framing error
FER
Stop bit is 0
Receive data loaded from
SCRSR into SCRDR
Parity error
PER
Parity of receive data differs from
even/odd parity setting in SCSMR
Receive data loaded from
SCRSR into SCRDR
Figure 17.11 shows an example of SCI receive operation in the asynchronous mode.
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Section 17 Serial Communication Interface (SCI)
1
Serial
data
Start
bit
0
Parity Stop Start
bit
bit
bit
Data
D0
D1
D7
0/1
1
0
Parity Stop
bit
bit
Data
D0
D1
D7
0/1
1
1
Idling
(marking)
RDRF
RXI interrupt
request generated
FER
1 frame
Reads data with
the RXI interrupt
processing routine
and clears RDRF
bit to 0
ERI interrupt
request generated
by framing error
Figure 17.11 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
17.3.3
Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in the asynchronous mode using a format with
an additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by a unique ID.
A serial communication cycle consists of an ID-sending cycle that identifies the receiving
processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from
data-sending cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1.
When they receive data with the multiprocessor bit set to 1, receiving processors compare the data
with their IDs. The receiving processor with a matching ID continues to receive further incoming
data. Processors with IDs not matching the received data skip further incoming data until they
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Section 17 Serial Communication Interface (SCI)
again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive
data in this way.
Figure 17.12 shows an example of communication among processors using the multiprocessor
format.
Transmitting
station
Serial communications circuit
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'01
H'AA
(MPB = 1)
ID transmit cycle =
specifies receiving station
(MPB = 0)
Data transmit cycle =
data transmission to
receiving station specified
by ID
MPB: Multiprocessor bit
Figure 17.12 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
Communication Formats
Four formats are available. Parity-bit settings are ignored when the multiprocessor format is
selected. For details see table 17.11.
Clock
See the description in the asynchronous mode section.
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Section 17 Serial Communication Interface (SCI)
Transmitting and Receiving Data
Multiprocessor Serial Data Transmission:
Figure 17.13 shows a sample flow chart for multiprocessor serial data transmission. After enabling
the SCI transmission, transmit multiprocessor serial data following the procedure shown below:
Start transmission
Read TDRE bit in SCSSR
TDRE = 1?
(1) SCI status check and transmit data
write:
Read the serial status register
(SCSSR), check that the TDRE bit is
1, then write transmit data in the
transmit data register (SCTDR). Also
set MPBT (multiprocessor bit transfer)
to 0 or 1 in SCSSR. Finally, clear
TDRE to 0.
(1)
No
Yes
Write transmission data to SCTDR
and set MPBT bit in SCSSR
(2) To continue transmitting serial data:
Read the TDRE bit to check whether it
is safe to write (if it reads 1); if so, write
data in SCTDR, then clear TDRE to 0.
Clear TDRE bit to 0
Transmission ended?
No
Yes
Read TEND bit in SCSSR
TEND = 1?
No
Yes
Break output?
No
(2)
(3) To output a break at the end of serial
transmission:
Set the port SC data register (SCPDR)
and port SC control register (SCPCR),
then clear the TE bit to 0 in the serial
control register (SCSCR). For SCPCR
and SCPDR settings, see section
17.2.8, Port SC Control Register
(SCPCR)/Port SC Data Register
(SCPDR).
Yes (3)
Set SCPDR and SCPCR
Clear TE bit SCSCR to 0
End transmission
Figure 17.13 Sample Multiprocessor Serial Transmission Flowchart
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Section 17 Serial Communication Interface (SCI)
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes
that the transmit data register (SCTDR) contains new data, and loads this data from the
SCTDR into the transmit shift register (SCTSR).
2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and
starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to
1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is
transmitted in the following order from the TxD pin:
a. Start bit: One 0 bit is output.
b. Transmit data: Seven or eight bits are output, LSB first.
c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
d. Stop bit: One or two 1 bits (stop bits) are output.
e. Marking: Output of 1 bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
from the SCTDR into the SCTSR, outputs the stop bit, then begins serial transmission of the
next frame. If TDRE is 1, the SCI sets the TEND bit in the SCSSR to 1, outputs the stop bit,
then continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit
(TEIE) in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
Figure 17.14 shows SCI transmission in the multiprocessor format.
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Section 17 Serial Communication Interface (SCI)
1
Serial
data
Multiprocessor
bit Stop Start
Data
bit
bit
Start
bit
0
D0
D1
D7
0/1
1
0
Multiprocessor
bit Stop
Data
bit
D0
D1
D7
0/1
1
1
Idling
(marking)
TDRE
TEND
TXI interrupt
request
generated
Writes data to
TXI interrupt
TDR with the TXI
request
interrupt progenerated
cessing routine and
clears TDRE bit to 0
TEI interrupt
request
generated
1 frame
Figure 17.14 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 17 Serial Communication Interface (SCI)
Multiprocessor Serial Data Reception:
Figure 17.15 shows a sample flow chart for multiprocessor serial data reception. After enabling
the SCI reception, receive multiprocessor serial data following the procedure shown below:
Start reception
Set MPIE bit in SCSCR to 1
(1)
Read ORER and FER
bits in SCSSR
FER = 1 or ORER = 1?
No
Read RDRF bit in SCSSR
No
Yes
(2)
RDRF = 1?
Yes
Read receive data in SCRDR
No
Yes
Read ORER and FER
bits in SSCSR
Yes
No
Read RDRF bit in SCSSR
RDRF = 1?
Yes
(2) SCI status check and compare to
ID reception:
Read the serial status register
(SCSSR), check that RDRF is set
to 1, then read data from the
receive data register (SCRDR) and
compare with the processor's own
ID. If the ID does not match the
receive data, set MPIE to 1 again
and clear RDRF to 0. If the ID
matches the receive data, clear
RDRF to 0.
(3) SCI status check and data
receiving:
Read SCSSR, check that RDRF is
set to 1, then read data from the
receive data register (SCRDR).
Is ID the
station’s ID?
FER = 1 or ORER = 1?
(1) ID receive cycle:
Set the MPIE bit in the serial control
register (SCSCR) to 1.
(4)
No
(4) Receive error processing and break
detection:
If a receive error occurs, read the
ORER and FER bits in SCSSR to
identify the error. After executing
the necessary error processing,
clear both ORER and FER to 0.
Receiving cannot resume if ORER
or FER remain set to 1. When a
framing error occurs, the RxD pin
can be read to detect the break
state.
Read receive data in SCRDR
No
All data received?
Yes
Clear RE bit in SCSCR to 0
(3)
Error processing
End reception
Figure 17.15 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 17 Serial Communication Interface (SCI)
Error processing
No
ORER = 1?
Yes
Overrun error processing
No
FER = 1?
Yes
Break?
Yes
No
Framing error processing
Clear RE bit in SCSCR to 0
Clear ORER and
FER bits in SCSSR to 0
End
Figure 17.15 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 17 Serial Communication Interface (SCI)
Figure 17.16 shows an example of SCI receive operation using a multiprocessor format.
1
Serial
data
Start
bit
0
Data
(ID1)
D0
Stop Start Data
MPB bit
bit (data 1)
D1
D7
1
1
0
D0
D1
Stop
MPB bit
D7
0
1
1
Idling
(marking)
MPIE
RDRF
RDR
value
ID1
RXI interrupt request
(multiprocessor interrupt)
generated, MPIE = 0
Reads RDR data with
the RXI interrupt
processing routine
and clears RDRF bit to 0
ID is not station’s No RXI interrupt,
ID, so MPIE bit is
generated
set to 1 again
RDR state
is maintained
(a) Own ID does not match data
1
Serial
data
Start
bit
0
Data
(ID2)
D0
D1
MPB
D7
1
Data
Stop Start
bit bit (Data 2)
1
0
D0
D1
Stop
MPB bit
D7
0
1
Idling
1
(marking)
MPIE
RDRF
RDR
value
ID1
RXI interrupt
request
(multiprocessor
interrupt) generated,
MPIE = 0
Reads RDR data with
the RXI interrupt
processing routine
and clears
RDRF bit to 0
ID2
Data2
ID is that of station,
so reception
continues unchanged
and data is received
by the RXI interrupt
processing routine
MPIE bit
set to 1
again
(b) Own ID matches data
Figure 17.16 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 17 Serial Communication Interface (SCI)
17.3.4
Clock Synchronous Operation
In the clock synchronous mode, the SCI transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver are independent, so full-duplex communication is possible while
sharing the same clock. The transmitter and receiver are also double buffered, so continuous
transmitting or receiving is possible by reading or writing data while transmitting or receiving is in
progress.
Figure 17.17 shows the general format in clock synchronous serial communication.
One unit of communication data (character or frame)
*
*
Synchronization clock
LSB
Serial data Don't
care
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Note: * High except in continuous transmitting or receiving
Figure 17.17 Data Format in Clock Synchronous Communication
In clock synchronous serial communication, each data bit is output on the communication line
from one falling edge of the serial clock to the next. Data are guaranteed valid at the rising edge of
the serial clock.
In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB
(last). After output of the MSB, the communication line remains in the state of the MSB.
In the clock synchronous mode, the SCI transmits or receives data by synchronizing with the
rising edge of the serial clock.
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Section 17 Serial Communication Interface (SCI)
Communication Format
The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added.
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A
bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register
(SCSCR). See table 17.10.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock
pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains in the high state. When only receiving, the SCI receives in 2character units, so a 16 pulse synchronization clock is output. To receive in 1-character units,
select an external clock source.
Transmitting and Receiving Data
SCI Initialization (clock synchronous mode)
Before transmitting and receiving data, the TE and RE bits in SCSCR should be cleared to 0, then
the SCI should be initialized as described in a sample flowchart in figure 17.18.
When the operating mode, or transfer format, is changed for example, the TE and RE bits must be
cleared to 0 before making the change using the following procedure. When the TE bit is cleared
to 0, the TDRE flag is set to 1 and the transmit shift register (SCTSR) is initialized.
Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and
ORER flags, or the contents of SCRDR.
Figure 17.18 is a sample flowchart for initializing the SCI.
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Section 17 Serial Communication Interface (SCI)
Initialize
(1) Select the clock source in the
serial control register (SCSCR).
Leave RIE, TIE, TEIE, MPIE, TE
and RE cleared to 0.
Clear TE and RE bits in SCSCR to 0
Set RIE, TIE, TEIE, MPIE, CKE1,
and CKE0 bits in SCSCR
(TE and RE are 0)
(1)
(2) Select the communication format
in the serial mode register
(SCSMR).
Set transmit/receive format in SCSMR (2)
(3) Write the value corresponding to
the bit rate in the bit rate register
(SCBRR) unless an external
clock is used.
Set value in SCBRR
(3)
Wait
Has a 1-bit
period elapsed?
No
Yes
Set TE and RE bits in SCSCR to 1
and set RIE, TIE, TEIE, and MPIE bits (4)
(4) Wait for at least the interval
required to transmit or receive
one bit, then set TE or RE in the
serial control register (SCSCR)
to 1. Also set RIE, TIE, TEIE and
MPIE. Setting TE and RE allows
use of the TxD and RxD pins.
End
Figure 17.18 Sample SCI Initialization Flowchart
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Section 17 Serial Communication Interface (SCI)
Serial Data Transmission (Clock Synchronous Mode):
Figure 17.19 shows a sample flow chart for serial data transmission. After enabling the SCI
transmission, transmit serial data following the procedure shown below:
Start transmission
Read TDRE bit in SCSSR
TDRE = 1?
(1)
No
Yes
Write transmission data to SCTDR
and clear TDRE bit in SCSSR to 0
All data transmitted?
No
Yes
(2)
(1) SCI status check and transmit
data write:
Read the serial status register
(SCSSR), check that the TDRE
bit is 1, then write transmit data
in the transmit data register
(SCTDR) and clear TDRE to 0.
(2) To continue transmitting serial
data:
Read the TDRE bit to check
whether it is safe to write (if it
reads 1); if so, write data in
SCTDR, then clear TDRE to 0.
Read TEND bit in SCSSR
TEND = 1?
No
Yes
Clear TE bit in SCSCR to 0
End transmission
Figure 17.19 Sample Serial Transmission Flowchart
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Section 17 Serial Communication Interface (SCI)
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes
that the transmit data register (SCTDR) contains new data and loads this data from the SCTDR
into the transmit shift register (SCTSR).
2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and
starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to
1, the SCI requests a transmit-data-empty interrupt (TXI) at this time.
If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external
clock source is selected, the SCI outputs data in synchronization with the input clock. Data are
output from the TxD0 pin in order from the LSB (bit 0) to the MSB (bit 7).
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads
data from the SCTDR into the SCTSR, then begins serial transmission of the next frame. If
TDRE is 1, the SCI sets the TEND bit in the SCSSR to 1, transmits the MSB, then holds the
transmit data pin (TxD0) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in
the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
4. After the end of serial transmission, the SCK0 pin is held in the high state.
Figure 17.20 shows an example of SCI transmit operation.
Transfer direction
Synchronization
clock
Serial data
LSB
Bit 0
Bit 1
MSB
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt Writes data to TDR TXI interrupt
with the TXI interrupt
request
request
processing routine
generated
generated
and clears TDRE
bit to 0
TEI interrupt
request
generated
1 frame
Figure 17.20 Sample SCI Transmission Operation in Clocked Synchronous Mode
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Section 17 Serial Communication Interface (SCI)
Serial Data Reception (Clock Synchronous Mode):
Figure 17.21 shows a sample flow chart for serial data reception. After enabling the SCI
transmission, transmit serial data following the procedure shown below:
When switching from the asynchronous mode to the clock synchronous mode, make sure that
ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and
both transmitting and receiving will be disabled.
Start reception
Read ORER bit in SCSSR
ORER = 1?
Yes
(1)
No
Error processing
Read RDRF bit in SCSSR
No
(2)
RDRF = 1?
Yes
Read receive data in SCRDR and
(3)
clear RDRF bit in SCSSR to 0
No
All data received?
Yes
Clear RE bit in SCSCR to 0
(1) Receive error processing:
If a receive error occurs, read
the ORER bit in SCSSR to
identify the error. After
executing the necessary error
processing, clear ORER to 0.
Transmitting/receiving cannot
resume if ORER remains set
to 1.
(2) SCI status check and receive
data read:
Read the serial status register
(SCSSR), check that RDRF is
set to 1, then read receive
data from the receive data
register (SCRDR) and clear
RDRF to 0. The RXI interrupt
can also be used to determine
if the RDRF bit has changed
from 0 to 1.
(3) To continue receiving serial
data:
Read SCRDR, and clear
RDRF to 0 before the frame
MSB (bit 7) of the current
frame is received.
End reception
Figure 17.21 Sample Serial Reception Flowchart (1)
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Section 17 Serial Communication Interface (SCI)
Error processing
No
ORER = 1?
Yes
Overrun error processing
Clear ORER bit in SCSSR to 0
End
Figure 17.21 Sample Serial Reception Flowchart (2)
In receiving, the SCI operates as follows:
1. The SCI synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into the SCRSR in order from the LSB to the MSB. After receiving the
data, the SCI checks that RDRF is 0 so that receive data can be loaded from the SCRSR into
the SCRDR. If this check is passed, the SCI sets RDRF to 1 and stores the received data in the
SCRDR. If the check is not passed (receive error), the SCI operates as indicated in table 17.12.
This state prevents further transmission or reception. While receiving, the RDRF bit is not set
to 1. Be sure to clear the error flag.
3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
SCSCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the
receive-data-full interrupt enable bit (RIE) in the SCSCR is also set to 1, the SCI requests a
receive-error interrupt (ERI).
Figure 17.22 shows an example of the SCI receive operation.
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Section 17 Serial Communication Interface (SCI)
Transfer direction
Synchronization
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt
request
generated
Reads data with
the RXI interrupt
processing routine
and clears RDRF
bit to 0
RXI interrupt
request
generated
ERI interrupt
request generated
by overrun error
1 frame
Figure 17.22 Example of SCI Operation in Reception
Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode)
Figure 17.23 shows a sample flowchart for simultaneous serial transmit and receive operations.
After enabling the SCI transmission/reception, provide simultaneous serial transmit and receive
operations following the procedure shown below:
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Section 17 Serial Communication Interface (SCI)
Start transmission/reception
Read TDRE bit in SCSSR
No
(1) SCI status check and transmit
data write:
Read the serial status register
(SCSSR), check that the TDRE bit
is 1, then write transmit data in the
transmit data register (SCTDR)
and clear TDRE to 0. The TXI
interrupt can also be used to
determine if the TDRE bit has
changed from 0 to 1.
(1)
TDRE = 1?
Yes
Write transmission data to SCTDR
and clear TDRE bit in SCSSR to 0
Read ORER bit in SCSSR
Yes
ORER = 1?
No
(2)
Error processing
Read RDRF bit in SCSSR
No
(3)
RDRF = 1?
Yes
Read receive data of SCRDR
and clear RDRF bit in SCSSR to 0
No
All data
transmitted/received?
Yes
Clear TE and RE bits
in SCSCR to 0
End transmission/reception
(4)
(2) Receive error processing:
If a receive error occurs, read the
ORER bit in SCSSR to identify the
error. After executing the
necessary error processing, clear
ORER to 0. Transmitting/receiving
cannot resume if ORER remains
set to 1.
(3) SCI status check and receive data
read:
Read the serial status register
(SCSSR), check that RDRF is set
to 1, then read receive data from
the receive data register (SCRDR)
and clear RDRF to 0. The RXI
interrupt can also be used to
determine if the RDRF bit has
changed from 0 to 1.
(4) To continue transmitting and
receiving serial data:
Read the RDRF bit and SCRDR,
and clear RDRF to 0 before the
frame MSB (bit 7) of the current
frame is received. Also read the
TDRE bit to check whether it is
safe to write (if it reads 1); if so,
write data in SCTDR, then clear
TDRE to 0 before the MSB (bit 7)
of the current frame is transmitted.
Note: When switching transmit or receive operation to simultaneous serial transmit and receive
operations, first clear the TE bit and RE bit to 0, and then set both these bits to 1
simultaneously.
Figure 17.23 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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Section 17 Serial Communication Interface (SCI)
17.4
SCI Interrupt Sources
The SCI has four interrupt sources in each channel: Transmit-end (TEI), receive-error (ERI),
receive-data-full (RXI), and transmit-data-empty (TXI). Table 17.13 lists the interrupt sources and
indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE
bits in the serial control register (SCSCR). Each interrupt request is sent separately to the interrupt
controller.
TXI is requested when the TDRE bit in the SCSSR is set to 1.
RXI is requested when the RDRF bit in the SCSSR is set to 1.
ERI is requested when the ORER, PER, or FER bit in the SCSSR is set to 1.
TEI is requested when the TEND bit in the SCSSR is set to 1. Where the TXI interrupt indicates
that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is
complete.
Table 17.13 SCI Interrupt Sources
Interrupt Source
Description
Priority When Reset Is Cleared
ERI
Receive error (ORER, PER, or FER)
High
RXI
Receive data full (RDRF)
TXI
Transmit data empty (TDRE)
TEI
Transmit end (TEND)
Low
See section 4, Exception Handling, for information on the priority order and relationship to nonSCI interrupts.
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Section 17 Serial Communication Interface (SCI)
17.5
Usage Notes
Note the following points when using the SCI.
SCTDR Write and TDRE Flags: The TDRE bit in the serial status register (SCSSR) is a status
flag indicating loading of transmit data from the SCTDR into the SCTSR. The SCI sets TDRE to 1
when it transfers data from the SCTDR to the SCTSR. Data can be written to the SCTDR
regardless of the TDRE bit state. If new data is written in the SCTDR when TDRE is 0, however,
the old data stored in the SCTDR will be lost because the data has not yet been transferred to the
SCTSR. Before writing transmit data to the SCTDR, be sure to check that TDRE is set to 1.
Simultaneous Multiple Receive Errors: Table 17.14 indicates the state of the SCSSR status
flags when multiple receive errors occur simultaneously. When an overrun error occurs, the
SCRSR contents cannot be transferred to the SCRDR, so receive data is lost.
Table 17.14 SCSSR Status Flags and Transfer of Receive Data
SCSSR Status Flags
Receive Error Status
RDRF
ORER
FER PER
Receive Data Transfer
SCRSR → SCRDR
Overrun error
1
1
0
0
X
Framing error
0
0
1
0
O
Parity error
0
0
0
1
O
Overrun error + framing error
1
1
1
0
X
Overrun error + parity error
1
1
0
1
X
Framing error + parity error
0
0
1
1
O
Overrun error + framing error + parity error 1
1
1
1
X
X: Receive data is not transferred from SCRSR to SCRDR.
O: Receive data is transferred from SCRSR to SCRDR.
Break Detection and Processing: Break signals can be detected by reading the RxD0 pin directly
when a framing error (FER) is detected. In the break state, the input from the RxD0 pin consists of
all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI
receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again.
Sending a Break Signal: The TxD0 pin I/O condition and level can be determined by means of
the SCP0DT bit of the port SC data register (SCPDR) and bits SCP0MD0 and SCP0MD1 of the
port SC control register (SCPCR). These bits can be used to send breaks. To send a break during
serial transmission, clear the SCP0DT bit to 0 (designating low level), then clear the TE bit to 0
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Section 17 Serial Communication Interface (SCI)
(halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of
the current transmission state, and 0 is output from the TxD0 pin.
TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit
of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND
flag has been confirmed, the stop bit will be in the process of transmission and will not be
transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial clock
cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag setting is confirmed.
Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only): When a
receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if
TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that
clearing RE to 0 does not clear the receive error flags.
Receive Data Sampling Timing and Reception Margin in the Asynchronous Mode: In the
asynchronous mode, the SCI operates on a base clock of 16 times the transfer rate frequency. In
receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples
on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure
17.24).
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
Basic
clock
Receive
data (RxD)
−7.5 clocks
Start bit
+7.5 clocks
D0
Synchronization
sampling
timing
Data
sampling
timing
Figure 17.24 Receive Data Sampling Timing in Asynchronous Mode
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D1
Section 17 Serial Communication Interface (SCI)
The reception margin in the asynchronous mode is given by formula 1.
Formula 1:
M = 0.5 −
Where:
1
D − 0.5
(1 + F) × 100%
− (L − 0.5)F −
2N
N
M = Reception margin (%)
N = Ratio of clock frequency to bit rate (N = 16)
D = Clock duty cycle (D = 0–1.0)
L = Frame length (L = 9–12)
F = Absolute deviation of clock frequency
Assuming values of F = 0, D = 0.5 and N = 372 in formula (1), the reception margin is given by
formula 2.
Formula 2:
M = (0.5 – 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%.
Cautions for Clock Synchronous External Clock Mode:
• Set TE = RE = 1 only when the external clock SCK is 1.
• Do not set TE = RE = 1 until at least four clocks after the external clock SCK has changed
from 0 to 1.
• When receiving, RDRF is 1 when RE is set to zero 2.5 to 3.5 clocks after the rising edge of the
SCK input of the D7 bit in RxD, but it cannot be copied to SCRDR.
Caution for Clock Synchronous Internal Clock Mode: When receiving, RDRF is 1 when RE is
set to zero 1.5 clocks after the rising edge of the SCK output of the D7 bit in RxD, but it cannot be
copied to SCRDR.
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Section 17 Serial Communication Interface (SCI)
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Section 18 Smart Card Interface
Section 18 Smart Card Interface
18.1
Overview
As an additional serial communications interface function (SCI), an IC card (smart card) interface
that is compatible to the ISO/IEC standard 7816-3 for identification of cards is supported. Register
settings are used to switch between the ordinary serial communication interface and the smart card
interface.
18.1.1
Features
The smart card interface has the following features:
• Asynchronous mode
Data length: Eight bits
Parity bit generation and check
Receive mode error signal detection (parity error)
Transmit mode error signal detection and automatic re-transmission of data
Supports both direct convention and inverse convention
• Bit rate can be selected using on-chip baud rate generator.
• Three types of interrupts: Transmit-data-empty, receive-data-full, and communication-error
interrupts are requested independently.
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Section 18 Smart Card Interface
18.1.2
Block Diagram
Bus interface
Figure 18.1 shows a block diagram of the smart card interface.
Module data bus
SCRDR
RxD0
TxD0
SCRSR
SCTDR
SCTSR
Parity generation
Parity check
SCK0
SCSCMR
SCSSR
SCSCR
SCSMR
Transmit/
receive
control
SCBRR
Baud rate
generator
Pφ/4
Pφ/64
Clock
External clock
SCI
Smart card mode register
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register
Figure 18.1 Smart Card Interface Block Diagram
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Pφ
Pφ/16
Legend:
SCSCMR:
SCRSR:
SCRDR:
SCTSR:
SCTDR:
SCSMR:
SCSCR:
SCSSR:
SCBRR:
Internal
data bus
TXI
RXI
ERI
Section 18 Smart Card Interface
18.1.3
Pin Configuration
Table 18.1 summarizes the smart card interface pins.
Table 18.1 SCI Pins
Pin Name
Abbreviation
I/O
Function
Serial clock pin
SCK0
Output
Clock output
Receive data pin
RxD0
Input
Receive data input
Transmit data pin
TxD0
Output
Transmit data output
18.1.4
Register Configuration
Table 18.2 summarizes the registers used by the smart card interface. The SCSMR, SCBRR,
SCSCR, SCTDR, and SCRDR registers are the same as in the ordinary SCI function. They are
described in section 17, Serial Communication Interface (SCI).
Table 18.2 Registers
Name
Abbreviation
R/W
3
Initial Value* Address
Access Size
Serial mode register
SCSMR
R/W
H'00
8
H'FFFFFE80
Bit rate register
SCBRR
R/W
H'FF
H'FFFFFE82
8
Serial control register
SCSCR
R/W
H'00
H'FFFFFE84
8
Transmit data register
SCTDR
R/W
H'FFFFFE86
8
Serial status register
SCSSR
H'FF
1
*
R/(W) H'84
H'FFFFFE88
8
Receive data register
SCRDR
R
H'FFFFFE8A
8
Smart card mode register
SCSCMR
R/W
H'FFFFFE8C
8
H'00
*2
Notes: 1. Only 0 can be written, to clear the flags.
2. Bits 0, 2, and 3 are cleared. The value of the other bits is undefined.
3. Initialized by a power-on or manual reset.
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Section 18 Smart Card Interface
18.2
Register Descriptions
This section describes the registers added for the smart card interface and the bits whose functions
are changed.
18.2.1
Smart Card Mode Register (SCSCMR)
The smart card mode register (SCSCMR) is an 8-bit read/write register that selects smart card
interface functions. SCSCMR bits 0, 2, and 3 are initialized to H’00 by a reset and in standby
mode.
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
SDIR
SINV
—
SMIF
Initial value:
—
—
—
—
0
0
—
0
R/W:
R
R
R
R
R/W
R/W
R
R/W
Bits 7 to 4 and 1—Reserved: These bits are always read as 0. The write value should always be
0.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
Bit 3: SDIR
Description
0
Contents of SCTDR are transferred as LSB first, receive data is stored in
SCRDR as LSB first.
(Initial value)
1
Contents of SCTDR are transferred as MSB first, receive data is stored in
SCRDR as MSB first.
Bit 2—Smart Card Data Inversion (SINV): Specifies whether to invert the logic level of the
data. This function is used in combination with bit 3 for transmitting and receiving with an inverse
convention card. SINV does not affect the logic level of the parity bit. See section 18.3.4, Register
Settings, for information on how parity is set.
Bit 2: SINV
Description
0
Contents of SCTDR are transferred unchanged, receive data is stored in SCRDR
unchanged.
(Initial value)
1
Contents of SCTDR are inverted before transfer, receive data is inverted before
storage in SCRDR.
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Section 18 Smart Card Interface
Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.
Bit 0: SMIF
Description
0
Smart card interface function disabled
1
Smart card interface function enabled
18.2.2
(Initial value)
Serial Status Register (SCSSR)
In the smart card interface mode, the function of SCSSR bit 4 is changed. The setting conditions
for bit 2, the TEND bit, are also changed.
Bit:
Initial value:
R/W:
7
6
TDRE
RDRF
5
4
ORER FER/ERS
3
2
1
0
PER
TEND
MPB
MPBT
1
0
0
0
0
1
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Note: * Only 0 can be written, to clear the flag.
Bits 7 to 5—These bits have the same function as in the ordinary SCI. See section 17, Serial
Communication Interface (SCI), for more information.
Bit 4—Error Signal Status (ERS): In the smart card interface mode, bit 4 indicates the state of
the error signal returned from the receiving side during transmission. The smart card interface
cannot detect framing errors.
Bit 4: ERS
Description
0
Receiving ended normally with no error signal.
(Initial value)
ERS is cleared to 0 when the chip is reset or enters standby mode, or when
software reads ERS after it has been set to 1, then writes 0 in ERS.
1
An error signal indicating a parity error was transmitted from the receiving side.
ERS is set to 1 if the error signal sampled is low.
Note: The ERS flag maintains its state even when the TE bit in SCSCR is cleared to 0.
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Section 18 Smart Card Interface
Bits 3 to 0—These bits have the same function as in the ordinary SCI. See section 17, Serial
Communication Interface (SCI), for more information. The setting conditions for bit 2, the
transmit end bit (TEND), are changed as follows.
Bit 2: TEND
Description
0
Transmission is in progress.
TEND is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE.
1
End of transmission.
(Initial value)
TEND is set to 1 when:
•
the chip is reset or enters standby mode,
•
the TE bit in SCSCR is 0 and the FER/ERS bit is also 0,
•
the C/A bit in SCSMR is 0, and TDRE = 1 and FER/ERS = 0 (normal
transmission) 2.5 etu after a one-byte serial character is transmitted, or
•
the C/A bit in SCSMR is 1, and TDRE = 1 and FER/ERS = 0 (normal
transmission) 1.0 etu after a one-byte serial character is transmitted.
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
18.3
Operation
18.3.1
Overview
The primary functions of the smart card interface are described below.
1. Each frame consists of 8-bit data and 1 parity bit.
2. During transmission, the card leaves a guard time of at least 2 etu (elementary time units: time
for transfer of 1 bit) from the end of the parity bit to the start of the next frame.
3. During reception, the card outputs an error signal low level for 1 etu after 10.5 etu has elapsed
from the start bit if a parity error was detected.
4. During transmission, it automatically transmits the same data after allowing at least 2 etu from
the time the error signal is sampled.
5. Only start-stop type asynchronous communication functions are supported; no synchronous
communication functions are available.
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Section 18 Smart Card Interface
18.3.2
Pin Connections
Figure 18.2 shows the pin connection diagram for the smart card interface. During communication
with an IC card, transmission and reception are both carried out over the same data transfer line,
so connect the TxD0 and RxD0 pins on the chip. Pull up the data transfer line to the power supply
VCC side with a resistor.
When using the clock generated by the smart card interface on an IC card, input the SCK pin
output to the IC card’s CLK pin. This connection is not necessary when the internal clock is used
on the IC card.
Use the chip’s port output as the reset signal. Apart from these pins, the power and ground pin
connections are usually also required.
Note: When the IC card is not connected and both RE and TE are set to 1, closed communication
is possible and auto-diagnosis can be performed.
VCC
TxD0
IO
Data line
RxD0
SCK0
Clock line
CLK
LSI
Px (port)
Connected device
Reset line
RST
IC card
Figure 18.2 Pin Connection Diagram for the Smart Card Interface
18.3.3
Data Format
Figure 18.3 shows the data format for the smart card interface. In this mode, parity is checked
every frame while receiving and error signals sent to the transmitting side whenever an error is
detected so that data can be re-transmitted. During transmission, error signals are sampled and data
re-transmitted whenever an error signal is detected.
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Section 18 Smart Card Interface
With no parity error
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D6
D7
Dp
Transmitting station output
With parity error
Ds
D0
D1
D2
D3
D4
D5
DE
Transmitting station output
Ds:
D0 to D7:
Dp:
DE:
Start bit
Data bits
Parity bit
Error signal
Receiving
station output
Figure 18.3 Data Format for Smart Card Interface
The operating sequence is:
1. The data line is high impedance when not in use and is fixed high with a pull-up resistor.
2. The transmitting side starts one frame of data transmission. The data frame starts with a start
bit (Ds, low level). The start bit is followed by eight data bits (D0 to D7) and a parity bit (Dp).
3. On the smart card interface, the data line returns to high impedance after this. The data line is
pulled high with a pull-up resistor.
4. The receiving side checks parity. When the data is received normally with no parity errors, the
receiving side then waits to receive the next data. When a parity error occurs, the receiving
side outputs an error signal (DE, low level) and requests re-transfer of data. The receiving
station returns the signal line to high impedance after outputting the error signal for a specified
period. The signal line is pulled high with a pull-up resistor.
5. The transmitting side transmits the next frame of data unless it receives an error signal. If it
does receive an error signal, it returns to step 2 to re-transmit the erroneous data.
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Section 18 Smart Card Interface
18.3.4
Register Settings
Table 18.3 shows the bit map of the registers that the smart card interface uses. Bits shown as 1 or
0 must be set to the indicated value. The settings for the other bits are described below.
Table 18.3 Register Settings for the Smart Card Interface
Register
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCSMR
H'FFFFFE80
C/A
0
1
O/E
1
0
CKS1
CKS0
SCBRR
H'FFFFFE82
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
SCSCR
H'FFFFFE84
TIE
RIE
TE
RE
0
0
CKE1
CKE0
SCTDR
H'FFFFFE86
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
SCSSR
H'FFFFFE88
TDRE
RDRF
ORER
FER/
ERS
PER
TEND
0
0
SCRDR
H'FFFFFE8A
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
SCSCMR
H'FFFFFE8C
—
—
—
—
SDIR
SINV
—
SMIF
Note: Dashes indicate unused bits.
1. Setting the serial mode register (SCSMR): The C/A bit selects the set timing of the TEND flag,
and selects the clock output state with the combination of bits CKE1 and CKE0 in the serial
control register (SCSCR). Set the O/E bit to 0 when the IC card uses the direct convention or
to 1 when it uses the inverse convention. Select the on-chip baud rate generator clock source
with the CKS1 and CKS0 bits (see section 18.3.5, Clock).
2. Setting the bit rate register (SCBRR): Set the bit rate. See section 18.3.5, Clock, to see how to
calculate the set value.
3. Setting the serial control register (SCSCR): The TIE, RIE, TE and RE bits function as they do
for the ordinary SCI0. See section 17, Serial Communication Interface (SCI), for more
information. The CKE0 bit specifies the clock output. When no clock is output, set 0; when a
clock is output, set 1.
4. Setting the smart card mode register (SCSCMR): The SDIR and SINV bits are both set to 0 for
IC cards that use the direct convention and both to 1 when the inverse convention is used. The
SMIF bit is set to 1 for the smart card interface.
Figure 18.4 shows sample waveforms for register settings of the two types of IC cards (direct
convention and inverse convention) and their start characters.
In the direct convention type, the logical 1 level is state Z, the logical 0 level is state A, and
communication is LSB first. The start character data is H'3B. The parity bit is even (from the
smart card standards), and thus 1.
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Section 18 Smart Card Interface
In the inverse convention type, the logical 1 level is state A, the logical 0 level is state Z, and
communication is MSB first. The start character data is H'3F. The parity bit is even (from the
smart card standards), and thus 0, which corresponds to state Z.
Only data bits D7 to D0 are inverted by the SINV bit. To invert the parity bit, set the O/E bit in
SCSMR to odd parity mode. This applies to both transmission and reception.
(Z)
A
Z
Z
A
Z
Z
Z
A
A
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Z
(Z)
State
(Z)
State
Dp
a. Direct convention (SDIR, SINV, and O/E are all 0)
(Z)
A
Z
Z
A
A
A
A
A
A
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Z
Dp
b. Inverse convention (SDIR, SINV, and O/E are all 1)
Figure 18.4 Waveform of Start Character
18.3.5
Clock
Only the internal clock generated by the on-chip baud rate generator can be used as the
communication clock in the smart card interface. The bit rate for the clock is set by the bit rate
register (SCBRR) and the CKS1 and CKS0 bits in the serial mode register (SCSMR), and is
calculated using the equation below. Table 18.5 shows sample bit rates. If clock output is then
selected by setting CKE0 to 1, a clock with a frequency 372 times the bit rate is output from the
SCK0 pin.
B=
Pφ
× 106
1488 × 22n−1 × (N + 1)
Where: N = Value set in SCBRR (0 ≤ N ≤ 255)
B = Bit rate (bit/s)
Pφ = Peripheral module operating frequency (MHz)
n = 0 to 3 (table 18.4)
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Section 18 Smart Card Interface
Table 18.4 Relationship of n to CKS1 and CKS0
n
CKS1
CKS0
0
0
0
1
0
1
2
1
0
3
1
1
Table 18.5 Examples of Bit Rate B (Bit/s) for SCBRR Settings (n = 0)
Pφ (MHz)
N
7.1424
10.00
10.7136
13.00
14.2848
16.00
18.00
0
9600.0
13440.9
14400.0
17473.1
19200.0
21505.4
24193.5
1
4800.0
6720.4
7200.0
8736.6
9600.0
10752.7
12096.8
2
3200.0
4480.3
4800.0
5824.4
6400.0
7168.5
8064.5
Note: The bit rate is rounded to two decimal places.
Calculate the value to be set in the bit rate register (SCBRR) from the operating frequency and the
bit rate. N is an integer in the range 0 ≤ N ≤ 255, specifying a smallish error.
N=
Pφ
× 106 − 1
1488 × 22n−1 × B
Table 18.6 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0)
φ (MHz) (9600 Bits/s)
7.1424
10.00
10.7136
13.00
14.2848
16.00
18.00
N
Error
N
Error
N
Error
N
Error
N
Error
N
Error
N
Error
0
0.00
1
30.00
1
25.00
1
8.99
1
0.00
1
12.01
2
15.99
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Section 18 Smart Card Interface
Table 18.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode)
Pφ (MHz)
Maximum Bit Rate (Bit/s)
N
n
7.1424
9600
0
0
10.00
13441
0
0
10.7136
14400
0
0
13.00
17473
0
0
14.2848
19200
0
0
16.00
21505
0
0
18.00
24194
0
0
The bit rate error is found as follows:
Error (%) = (
1488 ×
Pφ
× 106 − 1) × 100
× B × (N + 1)
22n−1
Table 18.8 shows the relationship between transmit/receive clock register set values and output
states on the smart card interface.
Table 18.8 Register Set Values and SCK Pin
Register Value
SCK Pin
Setting
SMIF
C/A
A
CKE1
CKE0
Output
State
1
1*
1
0
0
0
Port
Determined by setting of port
register SCP1MD1 and
SCP1MD0 bits
1
0
0
1
1
1
0
0
2
2*
3*
2
1
1
0
1
1
1
1
0
1
1
1
1
SCK (serial clock) output state
Low output
Low output state
High output
High output state
SCK (serial clock) output state
SCK (serial clock) output state
Notes: 1. The SCK output state changes as soon as the CKE0 bit is modified. The CKE1 bit
should be cleared to 0.
2. The clock duty remains constant despite stopping and starting of the clock by
modification of the CKE0 bit.
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Section 18 Smart Card Interface
18.3.6
Data Transmission and Reception
Initialization: Initialize the SCI0 using the following procedure before sending or receiving data.
Initialization is also required for switching from transmit mode to receive mode or from receive
mode to transmit mode. Figure 18.5 shows a flowchart of the initialization process (example).
1. Clear TE and RE in the serial control register (SCSCR) to 0.
2. Clear error flags FER/ERS, PER, and ORER to 0 in the serial status register (SCSSR).
3. Set the C/A bit, parity bit (O/E bit), and baud rate generator select bits (CKS1 and CKS0 bits)
in the serial mode register (SCSMR). At this time also clear the CHR and MP bits to 0 and set
the STOP and PE bits to 1.
4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR). When the
SMIF bit is set to 1, the TxD and RxD pins both switch from ports to SCI0 pins and become
high impedance.
5. Set the value corresponding to the bit rate in the bit rate register (SCBRR).
6. Set the clock source select bits (CKE1 and CKE0 bits) in the serial control register (SCSCR).
Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. When the CKE0 bit is set to 1, a clock
is output from the SCK pin.
7. After waiting at least 1 bit, set the TIE, RIE, TE, and RE bits in SCSCR. Do not set the TE and
RE bits simultaneously unless performing auto-diagnosis.
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Section 18 Smart Card Interface
Initialize
Clear TE and RE bits in SCSCR to 0
(1)
Clear SCSSR's FER/ERS,
PER and ORER flags to 0
(2)
Set SCSMR's O/E bit to parity,
set CKS1 and CKS0 bits to
the clock and set C/A
(3)
Set SCSMR's SMIF, SDIR,
and SINV bits
(4)
Set value in SCBRR
(5)
Set SCSCR's CKE1 and CKE0 bits
to the clock and clear TIE, RIE,
TE, RE, MPIE, and TEIE bits to 0
(6)
Wait
Has a 1-bit
interval elapsed?
No
Yes
Set SCSCR's
TIE, RIE, TE, and RE bits
(7)
End
Note:
Numbers refer to the preceding procedure.
Figure 18.5 Initialization Flowchart (Example)
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Section 18 Smart Card Interface
Serial Data Transmission: The processing procedures in the smart card mode differ from
ordinary SCI processing because data is retransmitted when an error signal is sampled during a
data transmission. This results in the transmission processing flowchart shown in figure 18.6
(example).
1. Initialize the smart card interface mode as described in initialization above.
2. Check that the FER/ERS bit in SCSSR is cleared to 0.
3. Repeat steps 2 and 3 until the TEND flag in SCSSR is set to 1.
4. Write the transmit data into SCTDR, clear the TDRE flag to 0 and start transmitting. The
TEND flag will be cleared to 0.
5. To transmit more data, return to step 2.
6. To end transmission, clear the TE bit to 0.
This processing can be interrupted. When the TIE bit is set to 1 and interrupt requests are enabled,
a transmit-data-empty interrupt (TXI) will be requested when the TEND flag is set to 1 at the end
of the transmission. When the RIE bit is set to 1 and interrupt requests are enabled, a
communication error interrupt (ERI) will be requested when the ERS flag is set to 1 when an error
occurs in transmission. See Interrupt Operation below for more information.
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Section 18 Smart Card Interface
Start
Initialize
(1)
Start transmission
FER/ERS = 0?
(2)
No
Yes
Error processing
No
TEND = 1?
(3)
Yes
Write transmit data in SCTDR
and clear TDRE
flag in SCSSR to 0
(4)
All data transmitted?
(5)
No
Yes
FER/ERS = 0?
No
Yes
Error processing
No
TEND = 1?
Yes
Clear TE bit in SCSCR to 0
(6)
End transmission
Note:
Numbers refer to the preceding procedure.
Figure 18.6 Transmission Flowchart (Example)
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Section 18 Smart Card Interface
Serial Data Reception: The processing procedures in the smart card mode are the same as in
ordinary SCI processing. The reception processing flowchart is shown in figure 18.7 (example).
1. Initialize the smart card interface mode as described above in Initialization and in figure 18.5.
2. Check that the ORER and PER flags in SCSSR are cleared to 0. If either flag is set, clear both
to 0 after performing the appropriate error processing procedures.
3. Repeat steps 2 and 3 until the RDRF flag is set to 1.
4. Read the receive data from SCRDR.
5. To receive more data, clear the RDRF flag to 0 and return to step 2.
6. To end reception, clear the RE bit to 0.
This processing can be interrupted. When the RIE bit is set to 1 and interrupt requests are enabled,
a receive-data-full interrupt (RXI) will be requested when the RDRF flag is set to 1 at the end of
the reception. When an error occurs during reception and either the ORER or PER flag is set to 1,
a communication error interrupt (ERI) will be requested. See Interrupt Operation below for more
information.
The received data will be transferred to SCRDR even when a parity error occurs during reception
and PER is set to 1, so this data can still be read.
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Section 18 Smart Card Interface
Start
Initialize
(1)
Start reception
ORER = 0 or PER = 0?
(2)
No
Yes
Error processing
No
RDRF = 1?
(3)
Yes
Write receive data from
SCRDR and clear
RDRF flag in SCSSR to 0
(4)
All data received?
(5)
No
Yes
Clear RE bit in SCSCR to 0
(6)
End reception
Note:
Numbers refer to the preceding procedure.
Figure 18.7 Reception Flowchart (Example)
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Section 18 Smart Card Interface
Switching Modes: When switching from receive mode to transmit mode, check that the receive
operation is completed before starting initialization and setting RE to 0 and TE to 1. The RDRF,
PER, and ORER flags can be used to check if reception is completed. When switching from
transmit mode to receive mode, check that the transmit operation is completed before starting
initialization and setting TE to 0 and RE to 1. The TEND flag can be used to check if transmission
is completed.
Interrupt Operation: In the smart card interface mode, there are three types of interrupts:
transmit-data-empty (TXI), communication error (ERI) and receive-data-full (RXI). In this mode,
the transmit-end interrupt (TEI) cannot be requested.
Set the TEND flag in SCSSR to 1 to request a TXI interrupt. Set the RDRF flag in SCSSR to 1 to
request an RXI interrupt. Set the ORER, PER, or FER/ERS flag in SCSSR to 1 to request an ERI
interrupt (table 18.9).
Table 18.9 Smart Card Mode Operating State and Interrupt Sources
Mode
State
Flag
Mask Bit
Interrupt Source
Transmit mode
Normal
TEND
TIE
TXI
Error
FER/ERS
RIE
ERI
Receive mode
Normal
RDRF
RIE
RXI
Error
PER,
ORER
RIE
ERI
18.4
Usage Notes
When the SCI is used as a smart card interface, be sure that all criteria in sections 18.4.1, Receive
Data Timing and Receive Margin in Asynchronous Mode and 18.4.2, Retransmission (Receive
and Transmit Modes) are applied.
18.4.1
Receive Data Timing and Receive Margin in Asynchronous Mode
In asynchronous mode, the SCI runs on a basic clock with a frequency of 372 times the transfer
rate. During reception, the SCI0 samples the falling of the start bit using the base clock to achieve
internal synchronization. Receive data is latched internally on the rising edge of the 186th basic
clock cycle (figure 18.8).
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Section 18 Smart Card Interface
372 clock cycles
186 clock cycles
0
185
371 0
185
371 0
Base clock
Start
bit
Receive
data (RxD)
D0
Synchronization
sampling
timing
Data
sampling
timing
Figure 18.8 Receive Data Sampling Timing in Smart Card Mode
The receive margin is found from the following equation:
For smart card mode:
M = (0.5 −
1
D − 0.5
(1 + F) × 100%
) − (L − 0.5)F −
2N
N
Where: M = Receive margin (%)
N = Ratio of bit rate to clock (N = 372)
D = Clock duty (D = 0 to 1.0)
L = Frame length (L = 10)
F = Absolute value of clock frequency deviation
Using this equation, the receive margin when F = 0 and D = 0.5 is as follows:
M = (0.5 – 1/2 × 372) × 100% = 49.866%
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D1
Section 18 Smart Card Interface
18.4.2
Retransmission (Receive and Transmit Modes)
Retransmission by the SCI in Receive Mode: Figure 18.9 shows the retransmission operation in
the SCI receive mode.
1. When the received parity bit is checked and an error is found, the PER bit in SCSSR is
automatically set to 1. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is
requested. Be sure to clear the PER bit before the next parity bit is sampled.
2. The RDRF bit in SCSSR is not set in the frame that caused the error.
3. When the received parity bit is checked and no error is found, the PER bit in SCSSR is not set.
4. When the received parity bit is checked and no error is found, reception is considered to have
been completed normally and the RDRF bit in SCSSR is automatically set to 1. If the RIE bit
in SCSCR is enabled at this time, an RXI interrupt is requested.
5. When a normal frame is received, the pin maintains a three-state state when it transmits the
error signal.
nth transfer frame
Retransmitted frame
Transfer frame n + 1
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
5
Ds D0 D1 D2 D3 D4
RDRF
2
4
1
3
PER
Figure 18.9 Retransmission in SCI Receive Mode
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Section 18 Smart Card Interface
Retransmission by the SCI in Transmit Mode: Figure 18.10 shows the retransmission operation
in the SCI transmit mode.
1. After transmission of one frame is completed, the FER/ERS bit in SCSSR is set to 1 when a
error signal is returned from the receiving side. If the RIE bit in SCSCR is enabled at this time,
an ERI interrupt is requested. Be sure to clear the FER/ERS bit before the next parity bit is
sampled.
2. The TEND bit in SCSSR is not set in the frame that received the error signal that indicated the
error.
3. The FER/ERS bit in SCSSR is not set when no error signal is returned from the receiving side.
4. When no error signal is returned from the receiving side, the TEND bit in SCSSR is set to 1
when the transmission of the frame that includes the retransmission is considered completed. If
the TIE bit in SCSCR is enabled at this time, a TXI interrupt will be requested.
nth transfer frame
Retransmitted frame
Transfer frame n + 1
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
TDRE
Transfer from SCTDR
to SCTSR
TEND
Ds D0 D1 D2 D3 D4
Transfer from
SCTDR to SCTSR
Transfer from
SCTDR to SCTSR
4
2
FER/ERS
1
3
Figure 18.10 Retransmission in SCI Transmit Mode
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Section 19 Serial Communication Interface with FIFO (SCIF)
Section 19 Serial Communication Interface with FIFO
(SCIF)
19.1
Overview
This LSI has one-channel serial communication interface with FIFO (SCIF) that supports
asynchronous serial communication. It also has 16-stage FIFO registers for both transfer and
receive that enables this LSI efficient high-speed continuous communication.
19.1.1
Features
• Asynchronous serial communication:
Serial data communications are performed by start-stop in character units. The SCI can
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are eight selectable serial data
communication formats.
Data length: Seven or eight bits
Stop bit length: One or two bits
Parity: Even, odd, or none
Receive error detection: Parity and framing errors
Break detection: Break is detected when the receive data next the generated framing error
is the space 0 level and has the framing error. It is also detected by reading the RxD level
directly from the port SC data register (SCPDR) when a framing error occurs
• Full duplex communication: The transmitting and receiving sections are independent, so the
SCI can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so
high-speed continuous data transfer is possible in both the transmit and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal transmit/receive clock source
• Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and
receive-error interrupts are requested independently. The direct memory access controller
(DMAC) can be activated to execute a data transfer by a transmit-FIFO-data-empty or receiveFIFO-data-full interrupt.
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
power.
• On-chip modem control functions (RTS2 and CTS2)
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Section 19 Serial Communication Interface with FIFO (SCIF)
• The quantity of data in the transmit and receive FIFO registers and the number of receive
errors of the receive data in the receive FIFO register can be known.
• The time-out error (DR) can be detected in receiving.
19.1.2
Block Diagram
Bus interface
Figure 19.1 shows a block diagram of the SCIF.
Module data bus
SCFRDR2
(16stages)
RxD2
TxD2
SCRSR2
SCFTDR2
(16stages)
SCTSR2
SCPCR2
SCFDR2
SCFDR2
SCFCR2
SCSSR2
SCSCR2
SCSMR2
Transmit/
receive
control
Internal
data bus
SCBRR2
Baud rate
generator
Pφ
Pφ/4
Pφ/16
Pφ/64
Clock
Parity generation
Parity check
RTS2
CTS2
SCIF
ERI
TXI
BRI
BRI
Legend:
SCRSR2:
SCFRDR2:
SCTSR2:
SCFTDR2:
SCSMR2:
SCSCR2:
Receive shift register 2
Receive FIFO data register 2
Transmit shift register 2
Transmit FIFO data register 2
Serial mode register 2
Serial control register 2
SCSSR2:
SCBRR2:
SCFCR2:
SCFDR2:
SCPDR2:
SCPCR2:
Serial status register 2
Bit rate register 2
FIFO control register 2
FIFO data count set register 2
Port SC data register 2
Port SC control register 2
Figure 19.1 SCIF Block Diagram
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Section 19 Serial Communication Interface with FIFO (SCIF)
Figures 19.2 and 19.3 show SCIF I/O ports. Bits 15, 14, 9, 8 of SCPCR and bits 7 and 4 of
SCPDR control an input/output and data of the SCIF pins. See section 26.3.13, SC Port Control
Register (SCPCR) for more details.
Reset
R
D
SCP4MD0
Q
C
PCRW
Reset
R
D
SCP4MD1
C
PCRW
Internal data bus
Q
Reset
SCPT[4]/TxD2
R
Q
D
SCP4DT1
C
SCIF
PDRW
Output enable
Serial
transmission
output
Legend:
PCRW: SCPCR write
PDRW: SCPDR write
Figure 19.2 SCPT[4]/TxD2 Pin
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Section 19 Serial Communication Interface with FIFO (SCIF)
SCIF
Internal data bus
SCPT[4]/RxD2
Serial
receive
data
PDRR*
Legend:
PDRR: SCPDR read
Note: * When reading the RxD2 pin, set the RE bit in SCSCR2 to 1.
Figure 19.3 SCPT[4]/RxD2 Pin
19.1.3
Pin Configuration
The SCIF has the serial pins summarized in table 19.1.
Table 19.1 SCIF Pins
Pin Name
Abbreviation
I/O
Function
Receive data pin
RxD2
Input
Receive data input
Transmit data pin
TxD2
Output
Transmit data output
Request to send pin
RTS2
Output
Request to send
Clear to send pin
CTS2
Input
Clear to send
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.1.4
Register Configuration
Table 19.2 summarizes the SCIF internal registers. These registers specify the data format and bit
rate, and control the transmitter and receiver sections.
Table 19.2 Registers
Register Name
Abbreviation
R/W
Initial
Value
Serial mode register 2
SCSMR2
R/W
H'00
8 bits
H'04000150
2
(H'A4000150)*
Bit rate register 2
SCBRR2
R/W
H'FF
H'04000152
8 bits
2
(H'A4000152)*
Serial control register 2
SCSCR2
R/W
H'00
H'04000154
8 bits
2
(H'A4000154)*
Transmit FIFO data register 2
SCFTDR2
W
—
H'04000156
8 bits
2
(H'A4000156)*
Serial status register 2
SCSSR2
R/(W)*
H'0060
H'04000158
16 bits
2
(H'A4000158)*
Receive FIFO data register 2
SCFRDR2
R
Undefined H'0400015A
8 bits
2
(H'A400015A)*
FIFO control register 2
SCFCR2
R/W
H'00
H'0400015C
8 bits
2
(H'A400015C)*
FIFO data count set register 2
SCFDR2
R
H'0000
H'0400015E
16 bits
2
(H'A400015E)*
1
Address
Access
Size
Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on,
either access these registers from the P2 area of logical space or else make an appropriate
setting using the MMU so that these registers are not cached.
1. Only 0 can be written to clear the flag.
2. When address translation by the MMU does not apply, the address in parentheses
should be used.
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.2
Register Descriptions
19.2.1
Receive Shift Register 2 (SCRSR2)
The receive shift register 2 (SCRSR2) receives serial data. Data input at the RxD2 pin is loaded
into the SCRSR2 in the order received, LSB (bit 0) first, converting the data to parallel form.
When one byte has been received, it is automatically transferred to the SCFRDR2, which is a
receive FIFO data register 2. The CPU cannot read or write the SCRSR2 directly.
19.2.2
Bit:
7
6
5
4
3
2
1
0
R/W:
—
—
—
—
—
—
—
—
Receive FIFO Data Register 2 (SCFRDR2)
The 16-byte receive FIFO data register 2 (SCFRDR2) stores serial receive data. The SCIF
completes the reception of one byte of serial data by moving the received data from the receive
shift register 2 (SCRSR2) into the SCFRDR2 for storage. Continuous receive is enabled until 16
bytes are stored.
The CPU can read but not write the SCFRDR2. When data is read without received data in the
SCFRDR2, the value is undefined. When the received data in this register becomes full, the
subsequent serial data is lost.
Bit:
7
6
5
4
3
2
1
0
R/W:
R
R
R
R
R
R
R
R
Rev. 5.00 Dec 12, 2005 page 570 of 1034
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.3
Transmit Shift Register 2 (SCTSR2)
The transmit shift register 2 (SCTSR2) transmits serial data. The SCI loads transmit data from the
transmit FIFO data register 2 (SCFTDR2) into the SCTSR2, then transmits the data serially from
the TxD2 pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the
next transmit data from the SCFTDR2 into the SCTSR2 and starts transmitting again. The CPU
cannot read or write the SCTSR2 directly.
19.2.4
Bit:
7
6
5
4
3
2
1
0
R/W:
—
—
—
—
—
—
—
—
Transmit FIFO Data Register 2 (SCFTDR2)
The transmit FIFO data register 2 (SCFTDR2) is a 16-byte 8-bit-length FIFO register that stores
data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR2) is
empty, it moves transmit data written in the SCFTDR2 into the SCTSR2 and starts serial
transmission. Continuous serial transmission is performed until the transmit data in the SCFTDR2
becomes empty. The CPU can always write to the SCFTDR2.
When the transmit data in the SCFTDR2 is full (16 bytes), next data cannot be written. If
attempted to write, the data is ignored.
Bit:
7
6
5
4
3
2
1
0
R/W:
W
W
W
W
W
W
W
W
Rev. 5.00 Dec 12, 2005 page 571 of 1034
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.5
Serial Mode Register 2 (SCSMR2)
The serial mode register 2 (SCSMR2) is an eight-bit register that specifies the SCIF serial
communication format and selects the clock source for the baud rate generator.
The CPU can always read and write the SCSMR2. The SCSMR2 is initialized to H'00 by a reset or
in standby and module standby modes.
Bit:
7
6
5
4
3
2
1
0
—
CHR
PE
O/E
STOP
—
CKS1
CKS0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R/W
R/W
R/W
R/W
R
R/W
R/W
Bit 7—Reserved: This bit always read 0. The write value should always be 0.
Bit 6—Character Length (CHR): Selects seven-bit or eight-bit data in the asynchronous mode.
Bit 6: CHR
Description
0
Eight-bit data.
1
Seven-bit data. *
(Initial value)
Note: * When seven-bit data is selected, the MSB (bit 7) of the transmit FIFO data register 2 is not
transmitted.
Bit 5—Parity Enable (PE): Selects whether or not to add a parity bit to transmit data and to
check the parity of receive data.
Bit 5: PE
Description
0
Parity bit not added or checked.
1
Parity bit added and checked.
(Initial value)
When PE is set to 1, an even or odd parity bit is added to transmit data,
depending on the parity mode (O/E) setting. Receive data parity is checked
according to the even/odd (O/E) mode setting.
Bit 4—Parity Mode (O/E
E): Selects even or odd parity when parity bits are added and checked.
The O/E setting is used only when the parity enable bit (PE) is set to 1 to enable parity addition
and check. The O/E setting is ignored when parity addition and check is disabled.
Rev. 5.00 Dec 12, 2005 page 572 of 1034
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 4: O/E
E
Description
0
Even parity.
(Initial value)
If even parity is selected, the parity bit is added to transmit data to make an even
number of 1s in the transmitted character and parity bit combined. Receive data
is checked to see if it has an even number of 1s in the received character and
parity bit combined.
1
Odd parity.
If odd parity is selected, the parity bit is added to transmit data to make an odd
number of 1s in the transmitted character and parity bit combined. Receive data
is checked to see if it has an odd number of 1s in the received character and
parity bit combined.
Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of
the next incoming character.
Bit 3: STOP
Description
0
One stop bit.
(Initial value)
In transmitting, a single bit of 1 is added at the end of each transmitted character.
1
Two stop bits.
In transmitting, two bits of 1 are added at the end of each transmitted character.
Bit 2—Reserved: This bit is always read as 0. The write value should always be 0.
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source of the on-chip baud rate generator. Four clock sources are available. Pφ, Pφ/4, Pφ/16 and
Pφ/64. For further information on the clock source, bit rate register 2 settings, and baud rate, see
section 19.2.8, Bit Rate Register 2 (SCBRR2).
Bit 1: CKS1
Bit 0: CKS0
Description
0
0
Pφ clock
1
Pφ/4 clock
0
Pφ/16 clock
1
Pφ/64 clock
1
(Initial value)
Note: Pφ: Peripheral clock
Rev. 5.00 Dec 12, 2005 page 573 of 1034
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.6
Serial Control Register 2 (SCSCR2)
The serial control register 2 (SCSCR2) operates the SCI transmitter/receiver, selects the serial
clock output in the asynchronous mode, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write the SCSCR2. The SCSCR2 is
initialized to H'00 by a reset or in standby and module standby modes.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
—
—
CKE1
CKE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-FIFO-data-empty
interrupt (TXI) requested when serial transmit data is transferred from transmit FIFO data register
2 (SCFTDR2) to transmit shift register 2 (SCTSR2), when the quantity of data in transmit FIFO
register 2 becomes less than the specified number of transmission triggers, and when the TDFE
flag in serial status register 2 (SCSSR2) is set to1.
Bit 7: TIE
Description
0
Transmit-FIFO-data-empty interrupt request (TXI) is disabled.*
1
Transmit-FIFO-data-empty interrupt request (TXI) is enabled
(Initial value)
Note: * The TXI interrupt request can be cleared by writing the greater quantity of transmit data
than the specified number of transmission triggers to SCFTDR2 and by clearing TDFE to 0
after reading 1 from TDFE, or can be cleared by clearing TIE to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full (RXI) and
receive-error (ERI) interrupts requested when serial receive data is transferred from receive shift
register 2 (SCRSR2) to receive FIFO data register 2 (SCFRDR2), when the quantity of data in
receive FIFO register 2 becomes more than the specified number of receive triggers, and when the
RDRF flag in SCSSR2 is set to1.
Bit 6: RIE
Description
0
Receive-data-full interrupt (RXI), receive-error interrupt (ERI), and receive break
interrupt (BRI) requests are disabled.*
(Initial value)
1
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are
enabled.
Note: * RXI and ERI interrupt requests can be cleared by reading the DR, ER, or RDF flag after it
has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. At RDF, read 1 from
the RDF flag and clear it to 0, after reading the received data from SCFRDR2 until the
quantity of received data becomes less than the specified number of the receive triggers.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 5—Transmit Enable (TE): Enables or disables the SCIF serial transmitter.
Bit 5: TE
Description
0
Transmitter disabled.
1
Transmitter enabled. *
(Initial value)
Note: * Serial transmission starts after writing of transmit data into the SCFTDR2. Select the
transmit format in the SCSMR2 and SCFCR2 and reset the SCFTDR2 before setting TE to
1.
Bit 4—Receive Enable (RE): Enables or disables the SCIF serial receiver.
Bit 4: RE
Description
0
Receiver disabled.*
2
Receiver enabled.*
1
1
(Initial value)
Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, FER, and PER).
These flags retain their previous values.
2. Serial reception starts when a start bit is detected. Select the receive format in the
SCSMR2 before setting RE to 1.
Bits 3 and 2—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1 and CKE0): These bits should always be set to 00.
Rev. 5.00 Dec 12, 2005 page 575 of 1034
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Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.7
Serial Status Register 2 (SCSSR2)
Serial status register 2 (SCSSR2) is a 16-bit register. The upper 8 bits indicate the number of
receive errors in the data of receive FIFO data register 2, and the lower 8 bits indicate SCIF
operating state.
The CPU can always read and write the SCSSR2, but cannot write 1 in the status flags (ER,
TEND, TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been
read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. The
SCSSR2 is initialized to H'0060 by a reset or in standby and module standby modes.
Lower 8 bits:
Initial value:
R/W:
7
6
5
4
3
2
1
0
ER
TEND
TDFE
BRK
FER
PER
RDF
DR
0
1
1
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/(W)*
R/(W)*
Note: * The only value that can be written is 0 to clear the flag.
Bit 7—Receive Error (ER): Indicates that a parity error has occurred when received data
includes a framing error or a parity.
Bit 7: ER
Description
0
Receive is in progress, or receive is normally completed.*
1
(Initial value)
ER is cleared to 0 when the chip is reset or enters standby mode, or when 0 is
written after 1 is read from ER.
1
A framing error or a parity error has occurred.
ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit
2
of the received data is 1 at the end of one-data receive* , or when the total
number of 1's in the received data and in the parity bit does not match the
even/odd parity specification specified by the O/E bit of the SCSMR2.
Notes: 1. Clearing the RE bit to 0 in SCSCR2 does not affect the ER bit, which retains its
previous value. Even if a receive error occurs, the received data is transferred to
SCFRDR2 and the receive operation is continued. Whether or not the data read from
SCFRDR2 includes a receive error can be detected by the FER and PER bits of
SCSSR2.
2. In the stop mode, only the first stop bit is checked; the second stop bit is not checked.
Rev. 5.00 Dec 12, 2005 page 576 of 1034
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 6—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, the SCFTDR2 did not contain valid data, so transmission has ended.
Bit 6: TEND
Description
0
Transmission is in progress.
TEND is cleared to 0 when data is written in SCFTDR2.
1
End of transmission.
(Initial value)
TEND is set to 1 when the chip is reset or enters standby mode, TE is cleared to
0 in the serial control register (SCSCR2), or when SCFTDR2 does not contain
received data when the last bit of a one-byte serial character is transmitted.
Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data is transferred from transmit
FIFO data register 2 (SCFTDR2) to transmit shift register (SCTSR), the quantity of data in
SCFTDR2 becomes less than the number of transmission triggers specified by the TTRG1 and
TTRG0 bits in FIFO control register 2 (SCFCR2), and writing the transmit data to SCFTDR2 is
enabled.
Bit 5: TDFE
Description
0
The quantity of transmit data written to SCFTDR2 is greater than the specified
number of transmission triggers.
(Initial value)
TDFE is cleared to 0 when data exceeding the specified transmission trigger
number is written to SCFTDR2, and software reads 1 from TDFE and then writes
0 to TDFE.
1
The quantity of transmit data in SCFTDR2 is less than the specified number of
transmission triggers.*
TDFE is set to 1 at reset or at standby mode, or when the quantity of
transmission data in SCFTDR2 becomes less than the specified number of
transmission triggers as a result of transmission.
Note: * Since SCFTDR2 is a 16-byte FIFO register, the maximum quantity of data which can be
written when TDFE is 1 is “16 minus the specified number of transmission triggers.” If an
attempt is made to write additional data, the data is ignored. The quantity of data in
SCFTDR2 is indicated by the upper 8 bits of SCFTDR2.
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 4—Break Detection (BRK): Indicates that a break signal is detected in received data.
Bit 4: BRK
Description
0
No break signal is being received.
(Initial value)
BRK is cleared to 0 when the chip is reset or enters standby mode, or software
reads BRK after it has been set to 1, then writes 0 in BRK.
1
The break signal is received.*
BRK is set to 1 when data including a framing error is received and a framing
error occurs with space 0 in the subsequent received data.
Note: * When a break is detected, transfer of the received data (H'00) to SCFRDR2 stops after
detection. When the break ends and the receive signal becomes mark 1, the transfer of
the received data resumes. The received data of a frame in which a break signal is
detected is transferred to SCFRDR2. After this, however, no received data is transferred
until a break ends with the received signal being mark 1 and the next data is received.
Bit 3—Framing Error (FER): Indicates a framing error in the data read from the receive FIFO
data register 2 (SCFRDR2).
Bit 3: FER
Description
0
No receive framing error occurred in the data read from SCFRDR2. (Initial value)
FER is cleared to 0 when the chip is power-on reset or enters standby mode, or
when no framing error is present in the data read from SCFRDR2.
1
A receive framing error occurred in the data read from SCFRDR2.
FER is set to 1 when a framing error is present in the data read from SCFRDR2.
Bit 2—Parity Error (PER): Indicates a parity error in the data read from the receive FIFO data
register 2 (SCFRDR2).
Bit 2: PER
Description
0
No receive parity error occurred in the data read from SCFRDR2.
(Initial value)
PER is cleared to 0 when the chip is power-on reset or enters standby mode, or
when no parity error is present in the data read from SCFRDR2.
1
A receive parity error occurred in the data read from SCFRDR2.
PER is set to 1 when a parity error is present in the data read from SCFRDR2.
Rev. 5.00 Dec 12, 2005 page 578 of 1034
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Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 1—Receive FIFO Data Full (RDF): Indicates that received data is transferred to the receive
FIFO data register 2 (SCFRDR2), the quantity of data in SCFRDR2 becomes more than the
number of receive triggers specified by the RTRG1 and RTRG0 bits in FIFO control register 2
(SCFCR2).
Bit 1: RDF
Description
0
The quantity of transmit data written to SCFRDR2 is less than the specified
number of receive triggers.
(Initial value)
RDF is cleared to 0 at power-on reset or in standby mode, or when SCFRDR2 is
read until the quantity of receive data in SCFRDR2 is less than the specified
receive trigger number, and software reads 1 from RDF and then writes 0 to
RDF.
1
The quantity of receive data in SCFRDR2 is more than the specified number of
receive triggers.
RDF is set to 1 when the quantity of receive data which is greater than the
specified number of receive triggers is stored in SCFRDR2.*
Note: * Since SCFTDR2 is a 16-byte FIFO register, the maximum quantity of data which can be
read when RDF is 1 is the specified number of receive triggers. If attempted to read after
all data in the SCFRDR2 have been read, the data is undefined. The quantity of receive
data in SCFRDR2 is indicated by the lower 8 bits of SCFTDR2.
Bit 0—Receive Data Ready (DR): Indicates that the receive FIFO data register 2 (SCFRDR2)
stores the data which is less than the specified number of receive triggers, and that next data is not
yet received after 15 ETU has elapsed from the last stop bit.
Bit 0: DR
Description
0
Receive is in progress, or no received data remains in SCFRDR2 after
completing receive normally.
(Initial value)
DR is cleared to 0 when the chip is power-on reset or enters standby mode, or
software reads DR after it has been set to 1, then writes 0 in DR.
1
Next receive data is not received.
DR is set to 1 when SCFRDR2 stores the data which is less than the specified
number of receive triggers, and that next data is not yet received after 15 ETU
has elapsed from the last stop bit.*
Note: * This is equivalent to 1.5 frames with the 8-bit 1-stop-bit format. (ETU: Element Time Unit)
Rev. 5.00 Dec 12, 2005 page 579 of 1034
REJ09B0254-0500
Section 19 Serial Communication Interface with FIFO (SCIF)
Upper 8 bits:
15
14
13
12
11
10
9
8
PER3
PER2
PER1
PER0
FER3
FER2
FER1
FER0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bits 15 to 12—Number of Parity Errors 3 to 0 (PER3 to PER0): Indicates the quantity of data
including a parity error in the received data stored in the receive FIFO data register 2 (SCFRDR2).
The value indicated by the bits 15 to 12 represents the number of parity errors in SCFRDR2.
Bits 11 to 8—Number of Framing Errors 3 to 0 (FER3 to FER0): Indicates the quantity of data
including a framing error in the received data stored in SCFRDR2. The value indicated by bits 11
to 8 represents the number of framing errors in SCFRDR2.
19.2.8
Bit Rate Register 2 (SCBRR2)
The bit rate register 2 (SCBRR2) is an eight-bit register that, together with the baud rate generator
clock source selected by the CKS1 and CKS0 bits in the serial mode register 2 (SCSMR2),
determines the serial transmit/receive bit rate.
The CPU can always read and write the SCBRR2. The SCBRR2 is initialized to H'FF by a reset or
in module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
The SCBRR2 setting is calculated as follows:
Asynchronous mode:
N=
B:
N:
Pφ:
n:
Pφ
64 × 2
2n–1
×B
× 106 – 1
Bit rate (bit/s)
SCBRR2 setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency for peripheral modules (MHz)
Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 19.3.)
Rev. 5.00 Dec 12, 2005 page 580 of 1034
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Section 19 Serial Communication Interface with FIFO (SCIF)
Table 19.3 SCSMR2 Settings
SCSMR2 Settings
n
Clock Source
CKS1
CKS0
0
Pφ
0
0
1
Pφ/4
0
1
2
Pφ/16
1
0
3
Pφ/64
1
1
Note: Find the bit rate error by the following formula:
Pφ
× 106 − 1
Error (%) =
(N+1) × 64 × 22n−1 × B
× 100
Table 19.4 lists examples of SCBRR2 settings.
Table 19.4 Bit Rates and SCBRR2 Settings
Pφ
φ (MHz)
2
2.097152
2.4576
Bit Rate (bits/s) n
N
Error (%
%) n
N
Error (%
%) n
N
Error (%
%)
110
1
141
0.03
1
148
–0.04
1
174
–0.26
150
1
103
0.16
1
108
0.21
1
127
0.00
300
0
207
0.16
0
217
0.21
0
255
0.00
600
0
103
0.16
0
108
0.21
0
127
0.00
1200
0
51
0.16
0
54
–0.70
0
63
0.00
2400
0
25
0.16
0
26
1.14
0
31
0.00
4800
0
12
0.16
0
13
–2.48
0
15
0.00
9600
0
6
–6.99
0
6
–2.48
0
7
0.00
19200
0
2
8.51
0
2
13.78
0
3
0.00
31250
0
1
0.00
0
1
4.86
0
1
22.88
38400
0
1
–18.62
0
0
–14.67
0
1
0.00
Rev. 5.00 Dec 12, 2005 page 581 of 1034
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Section 19 Serial Communication Interface with FIFO (SCIF)
Pφ
φ (MHz)
3
3.6864
4
Bit Rate (bits/s) n
N
Error (%
%) n
N
Error (%
%) n
N
Error (%
%)
110
1
212
0.03
2
64
0.70
2
70
0.03
150
1
155
0.16
1
191
0.00
1
207
0.16
300
1
77
0.16
1
95
0.00
1
103
0.16
600
0
155
0.16
0
191
0.00
0
207
0.16
1200
0
77
0.16
0
95
0.00
0
103
0.16
2400
0
38
0.16
0
47
0.00
0
51
0.16
4800
0
19
–2.34
0
23
0.00
0
25
0.16
9600
0
9
–2.34
0
11
0.00
0
12
0.16
19200
0
4
–2.34
0
5
0.00
0
6
–6.99
31250
0
2
0.00
0
3
–7.84
0
3
0.00
38400
—
—
—
0
2
0.00
0
2
8.51
Pφ
φ (MHz)
4.9152
5
6
Bit Rate (bits/s) n
N
Error (%
%) n
N
Error (%
%) n
N
Error (%
%)
110
2
86
0.31
2
88
–0.25
2
106
–0.44
150
1
255
0.00
2
64
0.16
2
77
0.16
300
1
127
0.00
1
129
0.16
1
155
0.16
600
0
255
0.00
1
64
0.16
1
77
0.16
1200
0
127
0.00
0
129
0.16
0
155
0.16
2400
0
63
0.00
0
64
0.16
0
77
0.16
4800
0
31
0.00
0
32
–1.36
0
38
0.16
9600
0
15
0.00
0
15
1.73
0
19
–2.34
19200
0
7
0.00
0
7
1.73
0
9
–2.34
31250
0
4
–1.70
0
4
0.00
0
5
0.00
38400
0
3
0.00
0
3
1.73
0
4
–2.34
Rev. 5.00 Dec 12, 2005 page 582 of 1034
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Section 19 Serial Communication Interface with FIFO (SCIF)
Pφ
φ (MHz)
6.144
7.3728
8
Bit Rate (bits/s) n
N
Error (%
%) n
N
Error (%
%) n
N
Error (%
%)
110
108
0.08
130
–0.07
141
0.03
2
2
2
150
2
79
0.00
2
95
0.00
2
103
0.16
300
1
159
0.00
1
191
0.00
1
207
0.16
600
1
79
0.00
1
95
0.00
1
103
0.16
1200
0
159
0.00
0
191
0.00
0
207
0.16
2400
0
79
0.00
0
95
0.00
0
103
0.16
4800
0
39
0.00
0
47
0.00
0
51
0.16
9600
0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
2.40
0
6
5.33
0
7
0.00
38400
0
4
0.00
0
5
0.00
0
6
–6.99
Pφ
φ (MHz)
9.8304
10
Bit Rate
(bits/s)
n
N
Error
(%
%)
110
1
174
150
1
300
0
12
N
Error
(%
%)
–0.26 2
177
127
0.00
2
255
0.00
12.288
N
Error
(%
%)
n
N
Error
(%
%)
–0.25 1
212
0.03
2
217
0.08
129
0.16
1
155
0.16
2
159
0.00
2
64
0.16