To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. Hitachi SuperHTM RISC engine SH-2 SH7052 F-ZTAT™ SH7053 F-ZTAT™ SH7054 F-ZTAT™ Hardware Manual ADE-602-185B Rev. 3.0 3/3/03 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Preface The SH7052F/SH7053F/SH7054F is a single-chip RISC (reduced instruction set computer) microcomputer that has an original Hitachi RISC type CPU as its core, and also includes peripheral functions necessary for system configuration. The CPU of the SH7052F/SH7053F/SH7054F has a RISC type instruction set, with basic instructions executed in one system clock cycle, for a higher instruction execution speed. It employs an internal 32-bit configuration, and offers enhanced data processing performance. The CPU of the SH7052F/SH7053F/SH7054F makes it possible to create high-performance, highfunctionality systems at low cost, even for applications requiring high speed such as real-time control, which could not be realized with conventional microcomputers. The SH7052F/SH7053F/SH7054F is also equipped with on-chip peripheral functions necessary for system configuration, including large-capacity ROM and RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), Hitachi controller area network (HCAN), A/D converter, interrupt controller (INTC), and I/O ports. In addition, an external memory access support function allows direct connection of ROM and SRAM, enabling system costs to be greatly reduced. The SH7052F/SH7053F/SH7054F is an F-ZTAT™ (Flexible Zero Turn-Around Time) version with flash memory as its on-chip ROM. Flash memory programs can be written with a programmer that supports SH7052F/SH7053F/SH7054F programming, and the flash memory can also be programmed and erased by software. This allows reprogramming to be carried out by the user with the chip mounted on a board. This Hardware Manual describes the hardware of the SH7052F/SH7053F/SH7054F. Details of instructions can be found in the Programming Manual. Related Manual Covering SH7052F/SH7053F/SH7054F execution instructions: SH-1/SH-2/SH-DSP Programming Manual Please consult your Hitachi sales representative for details of the development environment system. Main Revisions and Additions in this Edition Page Item Revisions (See Manual for Details) 8 1.3.1 Pin Arrangement Name of 155 th pin amended (PK11/TO8L) 61 5.1.1 Types of Exception Processing and Priority Table 5.1 Types of Exception Processing and Priority Order Compare match timer (CMT1), A/D converter channel 1 (A/D1) added Module abbreviations amended: CMT0, A/D0 160 9.3.5 Dual Address Mode Figure 9.5 Dual Address Mode and Indirect Address Operation (16-Bit-Width External Memory Space) Description of 1st and 2nd bus cycles amended If the data bus is 16 bits wide when the external memory space is accessed, two bus cycles are necessary. 217 10.2.3 Timer Control Registers Timer Control Register 9A, 9B, 9C (TCR9A, TCR9B, (TCR) TCR9C) Description of Bits 1 and 0 amended x=A, C, or E 306 10.2.15 Free-Running Counters Description of Free-Running Counter 0 added (TCNT) When the bits corresponding to the timer start register 1 (TSTR1) are set to 1, this counter starts to count. 307 Description of Free-Running Counters 1A, 1B, 2A, 2B, 3, 4, 5, 11 added When the bits corresponding to the timer start register 1, 3 (TSTR1, TSTR3) are set to 1, these counters start to count. 335 10.3.1 Overview 337 Description of Channel 2 amended Description of Channel 10 amended 348 10.3.9 PWM Timer Function Description amended ..., and H'0002, H'0003, H'0004 (100%), and H'0000 (0%) in BFR6A. 375 10.6 Sample Setup Procedures Sample Setup Procedure for Channel 0 Input Capture Triggered by Channel 10 Compare-Match Register name amended 399 Writing to ROM Area Immediately after ATU Register Write Description added Page Item Revisions (See Manual for Details) 400, 401 10.8 ATU-II Registers And Pins Table 10.4 ATU-II Registers and Pins Register names amended Pin names added and deleted 435 13.4.2 Compare Match Flag Set Figure 13.4 CMF Set Timing Timing CMCNT timing waveform amended 435 13.4.3 Compare Match Flag Clear Timing Description deleted 445 14.2.5 Serial Mode Register (SMR) Description amended 448 14.2.6 Serial Control Register (SCR) Description amended 456 14.2.8 Bit Rate Register (BRR) Description amended 463 14.2.9 Serial Direction Control Register (SDCR) Description amended 497 14.5.3 Break Detection and Processing Description added (Asynchronous Mode Only) 14.5.4 Sending a Break Signal 504 Table 15.2 HCAN Registers RFPR register name amended IMR initial value amended 510 15.2.3 Bit Configuration Register BCR setting constraints amended (BCR) Table note added 517 15.2.11 Interrupt Register (IRR) Initial value of bits 10 and 9 amended 519 Description of bit 9 amended 520 Description of bit 8 amended 533 15.3.1 Hardware Reset and Software Reset Description of Hardware Reset amended 537 Table 15.4 BCR Setting Limits Description amended 541 Figure 15.7 Transmission Flowchart Description amended 548 Figure 15.9 Reception Flowchart Description amended 552 Figure 15.11 HCAN Sleep Mode Description amended Flowchart 554 Figure 15.12 HCAN Halt Mode Flowchart Description amended 560 16.1.1 Features Description deleted Page Item Revisions (See Manual for Details) 562 16.1.3 Pin Configuration Description amended 570 16.2.3 A/D Control Registers 0 and 1 (ADCR0, ADCR1) Description amended 585 16.4.4 External Triggering of A/D Converter Description amended 600 17.5.3 ROM Area Writes New description added 701 20.5.5 RAM Emulation Register Description of bits 15 to 4 added (RAMER) The write value should always be 0. 713 20.7.3 Erase Mode Description amended 722 20.10 Note on Flash Memory Programming/Erasing Description added 763 21.7.3 Erase Mode Description amended 797 23.3.1 Transition to Hardware Standby Mode Description added 815 to 819 24.2 DC Characteristics Table 24.4 DC Characteristics 837 24.3.9 HCAN Timing Description amended Table 24.14 HCAN Timing Description amended 840 24.3.11 AUD Timing Table 24.16 AUD Timing Load conditions added 863, 867 Appendix A.1 Address Table A.1 Address 881, 884 to 886 A.2 Register States in Reset and Table A.2 Register States in Reset and Power-Down Power-Down States States 891 Appendix D Package Dimensions Register abbreviations amended: H’FFFFF466, H’FFFFF526 Description amended Figure D.1 Package Dimensions (FP-208A) Amended Contents Section 1 1.1 1.2 1.3 1 Features.............................................................................................................................. 1 Block Diagram................................................................................................................... 7 Pin Description .................................................................................................................. 8 1.3.1 Pin Arrangement .................................................................................................. 8 1.3.2 Pin Functions........................................................................................................ 9 1.3.3 Pin Assignments ................................................................................................... 16 Section 2 2.1 2.2 2.3 2.4 2.5 Overview ........................................................................................................... CPU ..................................................................................................................... 23 Register Configuration ...................................................................................................... 2.1.1 General Registers (Rn) ......................................................................................... 2.1.2 Control Registers.................................................................................................. 2.1.3 System Registers .................................................................................................. 2.1.4 Initial Values of Registers .................................................................................... Data Formats...................................................................................................................... 2.2.1 Data Format in Registers...................................................................................... 2.2.2 Data Format in Memory ....................................................................................... 2.2.3 Immediate Data Format........................................................................................ Instruction Features ........................................................................................................... 2.3.1 RISC-Type Instruction Set ................................................................................... 2.3.2 Addressing Modes................................................................................................ 2.3.3 Instruction Format ................................................................................................ Instruction Set by Classification........................................................................................ Processing States ............................................................................................................... 2.5.1 State Transitions ................................................................................................... Section 3 3.1 Operating Modes ............................................................................................ Operating Mode Selection ................................................................................................. Section 4 4.1 4.2 4.3 4.4 Clock Pulse Generator (CPG) ..................................................................... Overview............................................................................................................................ 4.1.1 Block Diagram...................................................................................................... 4.1.2 Pin Configuration ................................................................................................. Frequency Ranges.............................................................................................................. Clock Source...................................................................................................................... 4.3.1 Connecting a Crystal Oscillator............................................................................ 4.3.2 External Clock Input Method ............................................................................... Usage Notes ....................................................................................................................... 23 23 24 25 25 26 26 26 26 27 27 30 34 37 50 50 53 53 55 55 55 56 56 57 57 58 59 i Section 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Exception Processing .................................................................................... Overview............................................................................................................................ 5.1.1 Types of Exception Processing and Priority ........................................................ 5.1.2 Exception Processing Operations ......................................................................... 5.1.3 Exception Processing Vector Table...................................................................... Resets................................................................................................................................. 5.2.1 Types of Reset ...................................................................................................... 5.2.2 Power-On Reset.................................................................................................... 5.2.3 Manual Reset........................................................................................................ Address Errors ................................................................................................................... 5.3.1 Address Error Sources.......................................................................................... 5.3.2 Address Error Exception Processing.................................................................... Interrupts............................................................................................................................ 5.4.1 Interrupt Sources .................................................................................................. 5.4.2 Interrupt Priority Level......................................................................................... 5.4.3 Interrupt Exception Processing ............................................................................ Exceptions Triggered by Instructions................................................................................ 5.5.1 Types of Exceptions Triggered by Instructions.................................................... 5.5.2 Trap Instructions .................................................................................................. 5.5.3 Illegal Slot Instructions ........................................................................................ 5.5.4 General Illegal Instructions .................................................................................. When Exception Sources Are Not Accepted..................................................................... Stack Status after Exception Processing Ends................................................................... Usage Notes ....................................................................................................................... 5.8.1 Value of Stack Pointer (SP).................................................................................. 5.8.2 Value of Vector Base Register (VBR) ................................................................. 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... Section 6 6.1 6.2 6.3 ii Interrupt Controller (INTC) ......................................................................... Overview............................................................................................................................ 6.1.1 Features ................................................................................................................ 6.1.2 Block Diagram...................................................................................................... 6.1.3 Pin Configuration ................................................................................................. 6.1.4 Register Configuration ......................................................................................... Interrupt Sources................................................................................................................ 6.2.1 NMI Interrupts...................................................................................................... 6.2.2 User Break Interrupt ............................................................................................. 6.2.3 IRQ Interrupts ...................................................................................................... 6.2.4 On-Chip Peripheral Module Interrupts ................................................................ 6.2.5 Interrupt Exception Vectors and Priority Rankings ............................................. Description of Registers .................................................................................................... 6.3.1 Interrupt Priority Registers A, C to L (IPRA, IPRC to IPRL) ............................. 6.3.2 Interrupt Control Register (ICR) .......................................................................... 61 61 61 62 63 65 65 65 66 67 67 68 68 68 69 69 70 70 70 71 71 72 73 74 74 74 74 75 75 75 76 77 77 78 78 78 78 79 79 88 88 89 6.4 6.5 6.6 6.3.3 IRQ Status Register (ISR) .................................................................................... Interrupt Operation ............................................................................................................ 6.4.1 Interrupt Sequence................................................................................................ 6.4.2 Stack after Interrupt Exception Processing .......................................................... Interrupt Response Time ................................................................................................... Data Transfer with Interrupt Request Signals ................................................................... 6.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources ............... 6.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources ................ Section 7 7.1 7.2 7.3 7.4 7.5 User Break Controller (UBC) ..................................................................... Overview............................................................................................................................ 7.1.1 Features ................................................................................................................ 7.1.2 Block Diagram...................................................................................................... 7.1.3 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 7.2.1 User Break Address Register (UBAR)................................................................. 7.2.2 User Break Address Mask Register (UBAMR) ................................................... 7.2.3 User Break Bus Cycle Register (UBBR) ............................................................. 7.2.4 User Break Control Register (UBCR).................................................................. Operation ........................................................................................................................... 7.3.1 Flow of the User Break Operation........................................................................ 7.3.2 Break on On-Chip Memory Instruction Fetch Cycle ........................................... 7.3.3 Program Counter (PC) Values Saved ................................................................... Examples of Use................................................................................................................ 7.4.1 Break on CPU Instruction Fetch Cycle ................................................................ 7.4.2 Break on CPU Data Access Cycle........................................................................ 7.4.3 Break on DMA Cycle........................................................................................... Usage Notes ....................................................................................................................... 7.5.1 Simultaneous Fetching of Two Instructions......................................................... 7.5.2 Instruction Fetch at Branches ............................................................................... 7.5.3 Contention between User Break and Exception Processing ................................ 7.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 7.5.5 User Break Trigger Output................................................................................... 7.5.6 Module Standby.................................................................................................... Section 8 8.1 8.2 90 92 92 94 95 97 97 97 99 99 99 100 101 101 101 102 104 106 107 107 109 109 110 110 111 111 112 112 112 113 113 113 114 Bus State Controller (BSC) ......................................................................... 115 Overview............................................................................................................................ 8.1.1 Features ................................................................................................................ 8.1.2 Block Diagram...................................................................................................... 8.1.3 Pin Configuration ................................................................................................. 8.1.4 Register Configuration ......................................................................................... 8.1.5 Address Map ........................................................................................................ Description of Registers .................................................................................................... 115 115 116 117 117 118 122 iii 8.3 8.4 8.5 8.6 8.2.1 Bus Control Register 1 (BCR1)............................................................................ 8.2.2 Bus Control Register 2 (BCR2)............................................................................ 8.2.3 Wait Control Register (WCR).............................................................................. 8.2.4 RAM Emulation Register (RAMER) ................................................................... Accessing External Space.................................................................................................. 8.3.1 Basic Timing ........................................................................................................ 8.3.2 Wait State Control................................................................................................ 8.3.3 CS Assert Period Extension.................................................................................. Waits between Access Cycles ........................................................................................... 8.4.1 Prevention of Data Bus Conflicts ......................................................................... 8.4.2 Simplification of Bus Cycle Start Detection ........................................................ Bus Arbitration .................................................................................................................. Memory Connection Examples ......................................................................................... Section 9 9.1 9.2 9.3 9.4 iv Direct Memory Access Controller (DMAC) .......................................... Overview............................................................................................................................ 9.1.1 Features ................................................................................................................ 9.1.2 Block Diagram...................................................................................................... 9.1.3 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 9.2.1 DMA Source Address Registers 0 to 3 (SAR0 to SAR3) .................................... 9.2.2 DMA Destination Address Registers 0 to 3 (DAR0 to DAR3)............................ 9.2.3 DMA Transfer Count Registers 0 to 3 (DMATCR0 to DMATCR3) .................. 9.2.4 DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3) ............................ 9.2.5 DMAC Operation Register (DMAOR) ................................................................ Operation ........................................................................................................................... 9.3.1 DMA Transfer Flow ............................................................................................. 9.3.2 DMA Transfer Requests....................................................................................... 9.3.3 Channel Priority.................................................................................................... 9.3.4 DMA Transfer Types ........................................................................................... 9.3.5 Dual Address Mode.............................................................................................. 9.3.6 Bus Modes............................................................................................................ 9.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category ............................................................................................................... 9.3.8 Bus Mode and Channel Priorities......................................................................... 9.3.9 Source Address Reload Function ......................................................................... 9.3.10 DMA Transfer Ending Conditions ....................................................................... 9.3.11 DMAC Access from CPU .................................................................................... Examples of Use................................................................................................................ 9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory.......... 9.4.2 Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On) ............................................................................................ 122 123 126 128 130 130 131 133 134 134 135 136 137 139 139 139 140 141 142 142 143 144 145 150 152 152 154 157 157 157 163 164 165 165 166 167 168 168 168 9.4.3 9.5 Example of DMA Transfer between External Memory and SCI1 Transmitting Side (Indirect Address On) ........................................................................................... 170 Usage Notes ....................................................................................................................... 172 Section 10 Advanced Timer Unit-II (ATU-II) ............................................................ 173 10.1 Overview............................................................................................................................ 10.1.1 Features ................................................................................................................ 10.1.2 Pin Configuration ................................................................................................. 10.1.3 Register Configuration ......................................................................................... 10.1.4 Block Diagrams.................................................................................................... 10.1.5 Inter-Channel and Inter-Module Signal Communication Diagram...................... 10.1.6 Prescaler Diagram ................................................................................................ 10.2 Register Descriptions......................................................................................................... 10.2.1 Timer Start Registers (TSTR) .............................................................................. 10.2.2 Prescaler Registers (PSCR) .................................................................................. 10.2.3 Timer Control Registers (TCR)............................................................................ 10.2.4 Timer I/O Control Registers (TIOR).................................................................... 10.2.5 Timer Status Registers (TSR) .............................................................................. 10.2.6 Timer Interrupt Enable Registers (TIER)............................................................. 10.2.7 Interval Interrupt Request Registers (ITVRR) ..................................................... 10.2.8 Trigger Mode Register (TRGMDR) .................................................................... 10.2.9 Timer Mode Register (TMDR) ............................................................................ 10.2.10 PWM Mode Register (PMDR)............................................................................. 10.2.11 Down-Count Start Register (DSTR) .................................................................... 10.2.12 Timer Connection Register (TCNR) .................................................................... 10.2.13 One-Shot Pulse Terminate Register (OTR).......................................................... 10.2.14 Reload Enable Register (RLDENR) .................................................................... 10.2.15 Free-Running Counters (TCNT) .......................................................................... 10.2.16 Down-Counters (DCNT)...................................................................................... 10.2.17 Event Counters (ECNT) ....................................................................................... 10.2.18 Output Compare Registers (OCR)........................................................................ 10.2.19 Input Capture Registers (ICR).............................................................................. 10.2.20 General Registers (GR) ........................................................................................ 10.2.21 Offset Base Registers (OSBR) ............................................................................. 10.2.22 Cycle Registers (CYLR) ...................................................................................... 10.2.23 Buffer Registers (BFR) ........................................................................................ 10.2.24 Duty Registers (DTR) .......................................................................................... 10.2.25 Reload Register (RLDR) ...................................................................................... 10.2.26 Channel 10 Registers............................................................................................ 10.3 Operation ........................................................................................................................... 10.3.1 Overview .............................................................................................................. 10.3.2 Free-Running Counter Operation and Cyclic Counter Operation........................ 10.3.3 Compare-Match Function .................................................................................... 173 173 178 182 192 202 203 204 204 208 209 219 231 260 282 286 286 288 290 296 301 305 306 308 309 310 311 312 314 315 316 317 318 318 333 333 339 341 v 10.4 10.5 10.6 10.7 10.8 10.3.4 Input Capture Function......................................................................................... 10.3.5 One-Shot Pulse Function...................................................................................... 10.3.6 Offset One-Shot Pulse Function and Output Cutoff Function ............................. 10.3.7 Interval Timer Operation...................................................................................... 10.3.8 Twin-Capture Function ........................................................................................ 10.3.9 PWM Timer Function .......................................................................................... 10.3.10 Channel 3 to 5 PWM Function............................................................................. 10.3.11 Event Count Function and Event Cycle Measurement......................................... 10.3.12 Channel 10 Functions ........................................................................................... Interrupts............................................................................................................................ 10.4.1 Status Flag Setting Timing ................................................................................... 10.4.2 Status Flag Clearing ............................................................................................. CPU Interface .................................................................................................................... 10.5.1 Registers Requiring 32-Bit Access ...................................................................... 10.5.2 Registers Permitting 8-Bit, 16-Bit, or 32-Bit Access ........................................... 10.5.3 Registers Requiring 16-Bit Access ...................................................................... 10.5.4 8-Bit or 16-Bit Accessible Registers .................................................................... 10.5.5 Registers Requiring 8-Bit Access ........................................................................ Sample Setup Procedures .................................................................................................. Usage Notes ....................................................................................................................... ATU-II Registers And Pins ............................................................................................... 342 343 344 345 346 347 349 350 352 360 360 365 367 367 369 370 371 372 372 387 400 Section 11 Advanced Pulse Controller (APC) ............................................................ 403 11.1 Overview............................................................................................................................ 11.1.1 Features ................................................................................................................ 11.1.2 Block Diagram...................................................................................................... 11.1.3 Pin Configuration ................................................................................................. 11.1.4 Register Configuration ......................................................................................... 11.2 Register Descriptions......................................................................................................... 11.2.1 Pulse Output Port Control Register (POPCR)...................................................... 11.3 Operation ........................................................................................................................... 11.3.1 Overview .............................................................................................................. 11.3.2 Advanced Pulse Controller Output Operation...................................................... 11.4 Usage Notes ....................................................................................................................... 403 403 404 405 405 406 406 407 407 408 411 Section 12 Watchdog Timer (WDT) .............................................................................. 413 12.1 Overview............................................................................................................................ 12.1.1 Features ................................................................................................................ 12.1.2 Block Diagram...................................................................................................... 12.1.3 Pin Configuration ................................................................................................. 12.1.4 Register Configuration ......................................................................................... 12.2 Register Descriptions......................................................................................................... 12.2.1 Timer Counter (TCNT) ........................................................................................ vi 413 413 414 414 415 415 415 12.2.2 Timer Control/Status Register (TCSR) ................................................................ 12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 12.2.4 Register Access .................................................................................................... 12.3 Operation ........................................................................................................................... 12.3.1 Watchdog Timer Mode ........................................................................................ 12.3.2 Interval Timer Mode ............................................................................................ 12.3.3 Clearing Software Standby Mode ........................................................................ 12.3.4 Timing of Setting the Overflow Flag (OVF)........................................................ 12.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 12.4 Usage Notes ....................................................................................................................... 12.4.1 TCNT Write and Increment Contention............................................................... 12.4.2 Changing CKS2 to CKS0 Bit Values................................................................... 12.4.3 Changing between Watchdog Timer/Interval Timer Modes................................ 12.4.4 System Reset by WDTOVF Signal...................................................................... 12.4.5 Internal Reset in Watchdog Timer Mode ............................................................. 12.4.6 Manual Reset in Watchdog Timer........................................................................ 416 418 419 420 420 422 422 423 423 424 424 424 424 425 425 425 Section 13 Compare Match Timer (CMT) ................................................................... 427 13.1 Overview............................................................................................................................ 13.1.1 Features ................................................................................................................ 13.1.2 Block Diagram...................................................................................................... 13.1.3 Register Configuration ......................................................................................... 13.2 Register Descriptions......................................................................................................... 13.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 13.2.2 Compare Match Timer Control/Status Register (CMCSR).................................. 13.2.3 Compare Match Timer Counter (CMCNT).......................................................... 13.2.4 Compare Match Timer Constant Register (CMCOR).......................................... 13.3 Operation ........................................................................................................................... 13.3.1 Cyclic Count Operation........................................................................................ 13.3.2 CMCNT Count Timing ........................................................................................ 13.4 Interrupts............................................................................................................................ 13.4.1 Interrupt Sources and DTC Activation................................................................. 13.4.2 Compare Match Flag Set Timing ......................................................................... 13.4.3 Compare Match Flag Clear Timing...................................................................... 13.5 Usage Notes ....................................................................................................................... 13.5.1 Contention between CMCNT Write and Compare Match ................................... 13.5.2 Contention between CMCNT Word Write and Incrementation .......................... 13.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 427 427 428 429 430 430 431 432 433 433 433 434 434 434 434 435 436 436 437 438 Section 14 Serial Communication Interface (SCI) .................................................... 439 14.1 Overview............................................................................................................................ 439 14.1.1 Features ................................................................................................................ 439 14.1.2 Block Diagram...................................................................................................... 440 vii 14.2 14.3 14.4 14.5 14.1.3 Pin Configuration ................................................................................................. 14.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 14.2.1 Receive Shift Register (RSR)............................................................................... 14.2.2 Receive Data Register (RDR) .............................................................................. 14.2.3 Transmit Shift Register (TSR).............................................................................. 14.2.4 Transmit Data Register (TDR) ............................................................................. 14.2.5 Serial Mode Register (SMR)................................................................................ 14.2.6 Serial Control Register (SCR).............................................................................. 14.2.7 Serial Status Register (SSR)................................................................................. 14.2.8 Bit Rate Register (BRR)....................................................................................... 14.2.9 Serial Direction Control Register (SDCR) ........................................................... 14.2.10 Inversion of SCK Pin Signal ................................................................................ Operation ........................................................................................................................... 14.3.1 Overview .............................................................................................................. 14.3.2 Operation in Asynchronous Mode........................................................................ 14.3.3 Multiprocessor Communication ........................................................................... 14.3.4 Synchronous Operation ........................................................................................ SCI Interrupt Sources and the DMAC............................................................................... Usage Notes ....................................................................................................................... 14.5.1 TDR Write and TDRE Flag.................................................................................. 14.5.2 Simultaneous Multiple Receive Errors ................................................................ 14.5.3 Break Detection and Processing (Asynchronous Mode Only)............................. 14.5.4 Sending a Break Signal (Asynchronous Mode Only) .......................................... 14.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only)....... 14.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode.... 14.5.7 Constraints on DMAC Use .................................................................................. 14.5.8 Cautions on Synchronous External Clock Mode.................................................. 14.5.9 Caution on Synchronous Internal Clock Mode .................................................... 441 442 443 443 444 444 445 445 448 452 456 463 464 464 464 466 476 484 495 496 496 496 497 497 497 497 499 499 499 Section 15 Hitachi Controller Area Network (HCAN) ............................................ 501 15.1 Overview............................................................................................................................ 15.1.1 Features ................................................................................................................ 15.1.2 Block Diagram...................................................................................................... 15.1.3 Pin Configuration ................................................................................................. 15.1.4 Register Configuration ......................................................................................... 15.2 Register Descriptions......................................................................................................... 15.2.1 Master Control Register (MCR)........................................................................... 15.2.2 General Status Register (GSR)............................................................................. 15.2.3 Bit Configuration Register (BCR)........................................................................ 15.2.4 Mailbox Configuration Register (MBCR)............................................................ 15.2.5 Transmit Wait Register (TXPR) .......................................................................... 15.2.6 Transmit Wait Cancel Register (TXCR) .............................................................. viii 501 501 502 503 504 506 506 507 508 512 512 513 15.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 15.2.8 Abort Acknowledge Register (ABACK).............................................................. 15.2.9 Receive Complete Register (RXPR) .................................................................... 15.2.10 Remote Request Register (RFPR)........................................................................ 15.2.11 Interrupt Register (IRR) ....................................................................................... 15.2.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 15.2.13 Interrupt Mask Register (IMR) ............................................................................ 15.2.14 Receive Error Counter (REC) .............................................................................. 15.2.15 Transmit Error Counter (TEC) ............................................................................. 15.2.16 Unread Message Status Register (UMSR) ........................................................... 15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) ........................................... 15.2.18 Message Control (MC0 to MC15)........................................................................ 15.2.19 Message Data (MD0 to MD15)............................................................................ 15.3 Operation ........................................................................................................................... 15.3.1 Hardware Reset and Software Reset .................................................................... 15.3.2 Initialization after a Hardware Reset.................................................................... 15.3.3 Transmit Mode ..................................................................................................... 15.3.4 Receive Mode....................................................................................................... 15.3.5 HCAN Sleep Mode .............................................................................................. 15.3.6 HCAN Halt Mode ................................................................................................ 15.3.7 Interrupt Interface................................................................................................. 15.3.8 DMAC Interface................................................................................................... 15.4 CAN Bus Interface ............................................................................................................ 15.5 Usage Notes ....................................................................................................................... 514 515 516 517 517 521 522 524 525 525 526 527 531 533 533 536 539 546 552 554 555 556 557 558 Section 16 A/D Converter ................................................................................................. 559 16.1 Overview............................................................................................................................ 16.1.1 Features ................................................................................................................ 16.1.2 Block Diagram...................................................................................................... 16.1.3 Pin Configuration ................................................................................................. 16.1.4 Register Configuration ......................................................................................... 16.2 Register Descriptions......................................................................................................... 16.2.1 A/D Data Registers 0 to 15 (ADDR0 to ADDR15) ............................................. 16.2.2 A/D Control/Status Register 0 (ADCSR0)........................................................... 16.2.3 A/D Control Registers 0 and 1 (ADCR0, ADCR1) ............................................. 16.2.4 A/D Control/Status Register 1 (ADCSR1)........................................................... 16.2.5 A/D Trigger Registers 0 and 1 (ADTRGR0, ADTRGR1) ................................... 16.3 CPU Interface .................................................................................................................... 16.4 Operation ........................................................................................................................... 16.4.1 Single Mode.......................................................................................................... 16.4.2 Scan Mode............................................................................................................ 16.4.3 Analog Input Sampling and A/D Conversion Time ............................................. 16.4.4 External Triggering of A/D Converter ................................................................. 559 559 561 562 564 565 565 566 570 572 575 576 577 577 579 583 585 ix 16.4.5 A/D Converter Activation by ATU-II .................................................................. 16.5 Interrupt Sources and DMA Transfer Requests ................................................................ 16.6 Usage Notes ....................................................................................................................... 16.6.1 A/D conversion accuracy definitions ................................................................... 586 586 586 588 Section 17 Advanced User Debugger (AUD) ............................................................. 591 17.1 Overview............................................................................................................................ 17.1.1 Features ................................................................................................................ 17.1.2 Block Diagram...................................................................................................... 17.2 Pin Configuration .............................................................................................................. 17.2.1 Pin Descriptions ................................................................................................... 17.3 Branch Trace Mode ........................................................................................................... 17.3.1 Overview .............................................................................................................. 17.3.2 Operation .............................................................................................................. 17.4 RAM Monitor Mode.......................................................................................................... 17.4.1 Overview .............................................................................................................. 17.4.2 Communication Protocol...................................................................................... 17.4.3 Operation .............................................................................................................. 17.5 Usage Notes ....................................................................................................................... 17.5.1 Initialization.......................................................................................................... 17.5.2 Operation in Software Standby Mode .................................................................. 17.5.3 ROM Area Writes ................................................................................................ 591 591 592 592 593 595 595 595 597 597 597 598 599 599 599 600 Section 18 Pin Function Controller (PFC).................................................................... 601 18.1 Overview............................................................................................................................ 601 18.2 Register Configuration ...................................................................................................... 606 18.3 Register Descriptions......................................................................................................... 607 18.3.1 Port A IO Register (PAIOR) ................................................................................ 607 18.3.2 Port A Control Registers H and L (PACRH, PACRL) ........................................ 607 18.3.3 Port B IO Register (PBIOR)................................................................................. 612 18.3.4 Port B Control Registers H and L (PBCRH, PBCRL) ......................................... 612 18.3.5 Port B Invert Register (PBIR) .............................................................................. 618 18.3.6 Port C IO Register (PCIOR)................................................................................. 619 18.3.7 Port C Control Register (PCCR) .......................................................................... 620 18.3.8 Port D IO Register (PDIOR) ................................................................................ 622 18.3.9 Port D Control Registers H and L (PDCRH, PDCRL) ........................................ 623 18.3.10 Port E IO Register (PEIOR) ................................................................................. 627 18.3.11 Port E Control Register (PECR)........................................................................... 628 18.3.12 Port F IO Register (PFIOR).................................................................................. 633 18.3.13 Port F Control Registers H and L (PFCRH, PFCRL) .......................................... 634 18.3.14 Port G IO Register (PGIOR) ................................................................................ 640 18.3.15 Port G Control Register (PGCR).......................................................................... 641 18.3.16 Port H IO Register (PHIOR) ................................................................................ 643 x 18.3.17 18.3.18 18.3.19 18.3.20 18.3.21 18.3.22 Port H Control Register (PHCR).......................................................................... Port J IO Register (PJIOR) ................................................................................... Port J Control Registers H and L (PJCRH, PJCRL) ............................................ Port K IO Register (PKIOR) ................................................................................ Port K Control Registers H and L (PKCRH, PKCRL) ........................................ Port K Invert Register (PKIR).............................................................................. 644 650 651 655 656 660 Section 19 I/O Ports (I/O).................................................................................................. 661 19.1 Overview............................................................................................................................ 661 19.2 Port A................................................................................................................................. 662 19.2.1 Register Configuration ......................................................................................... 662 19.2.2 Port A Data Register (PADR) .............................................................................. 663 19.3 Port B ................................................................................................................................. 664 19.3.1 Register Configuration ......................................................................................... 664 19.3.2 Port B Data Register (PBDR)............................................................................... 665 19.4 Port C ................................................................................................................................. 666 19.4.1 Register Configuration ......................................................................................... 666 19.4.2 Port C Data Register (PCDR)............................................................................... 666 19.5 Port D................................................................................................................................. 668 19.5.1 Register Configuration ......................................................................................... 668 19.5.2 Port D Data Register (PDDR) .............................................................................. 669 19.6 Port E ................................................................................................................................. 670 19.6.1 Register Configuration ......................................................................................... 670 19.6.2 Port E Data Register (PEDR) ............................................................................... 671 19.7 Port F ................................................................................................................................. 673 19.7.1 Register Configuration ......................................................................................... 673 19.7.2 Port F Data Register (PFDR)................................................................................ 674 19.8 Port G................................................................................................................................. 676 19.8.1 Register Configuration ......................................................................................... 676 19.8.2 Port G Data Register (PGDR) .............................................................................. 676 19.9 Port H................................................................................................................................. 678 19.9.1 Register Configuration ......................................................................................... 679 19.9.2 Port H Data Register (PHDR) .............................................................................. 679 19.10 Port J.................................................................................................................................. 681 19.10.1 Register Configuration ......................................................................................... 681 19.10.2 Port J Data Register (PJDR) ................................................................................. 682 19.11 Port K................................................................................................................................. 683 19.11.1 Register Configuration ......................................................................................... 683 19.11.2 Port K Data Register (PKDR) .............................................................................. 684 19.12 POD (Port Output Disable) Control .................................................................................. 685 Section 20 ROM (SH7052F/SH7053F) ........................................................................ 687 20.1 Features.............................................................................................................................. 687 xi 20.2 Overview............................................................................................................................ 20.2.1 Block Diagram...................................................................................................... 20.2.2 Mode Transitions.................................................................................................. 20.2.3 On-Board Programming Modes ........................................................................... 20.2.4 Flash Memory Emulation in RAM....................................................................... 20.2.5 Differences between Boot Mode and User Program Mode.................................. 20.2.6 Block Configuration ............................................................................................. 20.3 Pin Configuration .............................................................................................................. 20.4 Register Configuration ...................................................................................................... 20.5 Register Descriptions......................................................................................................... 20.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 20.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 20.5.3 Erase Block Register 1 (EBR1)............................................................................ 20.5.4 Erase Block Register 2 (EBR2)............................................................................ 20.5.5 RAM Emulation Register (RAMER) ................................................................... 20.6 On-Board Programming Modes ........................................................................................ 20.6.1 Boot Mode............................................................................................................ 20.6.2 User Program Mode ............................................................................................. 20.7 Programming/Erasing Flash Memory................................................................................ 20.7.1 Program Mode...................................................................................................... 20.7.2 Program-Verify Mode .......................................................................................... 20.7.3 Erase Mode........................................................................................................... 20.7.4 Erase-Verify Mode ............................................................................................... 20.8 Protection........................................................................................................................... 20.8.1 Hardware Protection............................................................................................. 20.8.2 Software Protection .............................................................................................. 20.8.3 Error Protection .................................................................................................... 20.9 Flash Memory Emulation in RAM.................................................................................... 20.10 Note on Flash Memory Programming/Erasing.................................................................. 20.11 Flash Memory Programmer Mode .................................................................................... 20.11.1 Socket Adapter Pin Correspondence Diagram ..................................................... 20.11.2 Programmer Mode Operation............................................................................... 20.11.3 Memory Read Mode............................................................................................. 20.11.4 Auto-Program Mode ............................................................................................ 20.11.5 Auto-Erase Mode.................................................................................................. 20.11.6 Status Read Mode................................................................................................. 20.11.7 Status Polling........................................................................................................ 20.11.8 Programmer Mode Transition Time..................................................................... 20.11.9 Notes on Memory Programming.......................................................................... 688 688 689 690 692 693 694 694 695 696 696 698 699 699 701 703 703 708 708 709 710 713 714 717 717 718 718 720 722 722 723 725 726 729 731 733 734 734 735 Section 21 ROM (SH7054F) ............................................................................................ 737 21.1 Features.............................................................................................................................. 737 21.2 Overview............................................................................................................................ 738 xii 21.3 21.4 21.5 21.6 21.7 21.8 21.9 21.10 21.11 21.2.1 Block Diagram...................................................................................................... 21.2.2 Mode Transitions.................................................................................................. 21.2.3 On-Board Programming Modes ........................................................................... 21.2.4 Flash Memory Emulation in RAM....................................................................... 21.2.5 Differences between Boot Mode and User Program Mode.................................. 21.2.6 Block Configuration ............................................................................................. Pin Configuration .............................................................................................................. Register Configuration ...................................................................................................... Register Descriptions......................................................................................................... 21.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 21.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 21.5.3 Erase Block Register 1 (EBR1)............................................................................ 21.5.4 Erase Block Register 2 (EBR2)............................................................................ 21.5.5 RAM Emulation Register (RAMER) ................................................................... On-Board Programming Modes ........................................................................................ 21.6.1 Boot Mode............................................................................................................ 21.6.2 User Program Mode ............................................................................................. Programming/Erasing Flash Memory................................................................................ 21.7.1 Program Mode...................................................................................................... 21.7.2 Program-Verify Mode .......................................................................................... 21.7.3 Erase Mode........................................................................................................... 21.7.4 Erase-Verify Mode ............................................................................................... Protection........................................................................................................................... 21.8.1 Hardware Protection............................................................................................. 21.8.2 Software Protection .............................................................................................. 21.8.3 Error Protection .................................................................................................... Flash Memory Emulation in RAM.................................................................................... Note on Flash Memory Programming/Erasing.................................................................. Flash Memory Programmer Mode .................................................................................... 21.11.1 Socket Adapter Pin Correspondence Diagram ..................................................... 21.11.2 Programmer Mode Operation............................................................................... 21.11.3 Memory Read Mode............................................................................................. 21.11.4 Auto-Program Mode ............................................................................................ 21.11.5 Auto-Erase Mode.................................................................................................. 21.11.6 Status Read Mode................................................................................................. 21.11.7 Status Polling........................................................................................................ 21.11.8 Programmer Mode Transition Time..................................................................... 21.11.9 Notes on Memory Programming.......................................................................... 738 739 740 742 743 744 744 745 746 746 748 749 749 751 753 753 758 759 759 760 763 764 767 767 768 768 770 772 772 773 775 776 779 781 783 784 784 785 Section 22 RAM ................................................................................................................... 787 22.1 Overview............................................................................................................................ 787 22.2 Operation ........................................................................................................................... 789 xiii Section 23 Power-Down State.......................................................................................... 791 23.1 Overview............................................................................................................................ 23.1.1 Power-Down States .............................................................................................. 23.1.2 Pin Configuration ................................................................................................. 23.1.3 Related Registers.................................................................................................. 23.2 Register Descriptions......................................................................................................... 23.2.1 Standby Control Register (SBYCR) .................................................................... 23.2.2 System Control Register (SYSCR) ...................................................................... 23.2.3 Module Standby Control Register (MSTCR)....................................................... 23.2.4 Notes on Register Access ..................................................................................... 23.3 Hardware Standby Mode ................................................................................................... 23.3.1 Transition to Hardware Standby Mode ................................................................ 23.3.2 Canceling Hardware Standby Mode .................................................................... 23.3.3 Hardware Standby Mode Timing ......................................................................... 23.4 Software Standby Mode .................................................................................................... 23.4.1 Transition to Software Standby Mode.................................................................. 23.4.2 Canceling Software Standby Mode...................................................................... 23.4.3 Software Standby Mode Application Example .................................................... 23.5 Sleep Mode........................................................................................................................ 23.5.1 Transition to Sleep Mode ..................................................................................... 23.5.2 Canceling Sleep Mode.......................................................................................... 791 791 793 793 794 794 795 796 797 797 797 797 798 798 798 800 801 802 802 802 Section 24 Electrical Characteristics ............................................................................. 803 24.1 Absolute Maximum Ratings.............................................................................................. 24.2 DC Characteristics ............................................................................................................. 24.3 AC Characteristics ............................................................................................................. 24.3.1 Power-On/Off Timing .......................................................................................... 24.3.2 Clock Timing........................................................................................................ 24.3.3 Control Signal Timing.......................................................................................... 24.3.4 Bus Timing ........................................................................................................... 24.3.5 Advanced Timer Unit Timing and Advance Pulse Controller Timing ................ 24.3.6 I/O Port Timing .................................................................................................... 24.3.7 Watchdog Timer Timing ...................................................................................... 24.3.8 Serial Communication Interface Timing.............................................................. 24.3.9 HCAN Timing...................................................................................................... 24.3.10 A/D Converter Timing ......................................................................................... 24.3.11 AUD Timing ........................................................................................................ 24.3.12 UBC Trigger Timing............................................................................................ 24.3.13 Measuring Conditions for AC Characteristics ..................................................... 24.4 A/D Converter Characteristics .......................................................................................... xiv 803 804 821 821 822 824 827 831 833 834 835 837 838 840 842 843 844 Appendix A On-Chip Supporting Module Registers................................................ 845 A.1 A.2 Address .............................................................................................................................. 845 Register States in Reset and Power-Down States.............................................................. 881 Appendix B Pin States ....................................................................................................... 887 Appendix C Product Code Lineup ................................................................................. 890 Appendix D Package Dimensions .................................................................................. 891 xv xvi Section 1 Overview 1.1 Features The SH7052F/SH7053F/SH7054F is a single-chip RISC microcontroller that integrates a RISC CPU core using an original Hitachi architecture with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Basic instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance/high-functionality systems even for applications such as real-time control, which could not previously be handled by microcontrollers because of their high-speed processing requirements. In addition, the SH7052F/SH7053F/SH7054F includes on-chip peripheral functions necessary for system configuration, such as ROM , RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), Hitachi controller area network (HCAN), A/D converter, interrupt controller (INTC), and I/O ports. ROM and SRAM can be directly connected by means of an external memory access support function, greatly reducing system cost. On-chip ROM is available as flash memory in the F-ZTAT™* (Flexible Zero Turn Around Time) version. The flash memory can be programmed with a programmer that supports SH7052F/SH7053F/SH7054F programming, and can also be programmed and erased by software. This enables the chip to be programmed at the user site while mounted on a board. The features of the SH7052F/SH7053F/SH7054F are summarized in table 1.1. Note: * F-ZTAT is a trademark of Hitachi, Ltd. 1 Table 1.1 SH7052F/SH7053F/SH7054F Features Item Features CPU • Maximum operating frequency: 40 MHz • Original Hitachi SH-2 CPU • 32-bit internal architecture • General register machine Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers Operating states • Instruction execution time: Basic instructions execute in one state (25 ns/instruction at 40 MHz operation) • Address space: Architecture supports 4 Gbytes • Five-stage pipeline • Operating modes Single-chip mode 8/16-bit bus expanded mode • Mode with on-chip ROM • Mode with no on-chip ROM • Processing states Reset state Program execution state Exception handling state Bus-released state Power-down state • Power-down state Sleep mode Software standby mode Hardware standby mode Module standby Multiplier • 32 × 32 → 64 multiply operations executed in two to four cycles 32 × 32 + 64 → 64 multiply-and-accumulate operations executed in two to four cycles 2 Table 1.1 SH7052F/SH7053F/SH7054F Features (cont) Item Features Clock pulse generator (CPG/PLL) • On-chip clock pulse generator (maximum operating frequency: 40 MHz) • Independent generation of CPU system clock and peripheral clock for peripheral modules • On-chip clock-multiplication PLL circuit (×4) Internal clock frequency range: 5 to 10 MHz Interrupt controller (INTC) • Five external interrupt pins (NMI, IRQ0 to IRQ3) • 109 internal interrupt sources (ATU-II × 75, SCI × 20, DMAC × 4, A/D × 2, WDT × 1, UBC × 1, CMT × 2, HCAN × 4) User break controller (UBC) • 16 programmable priority levels • Requests an interrupt when the CPU or DMAC generates a bus cycle with specified conditions (interrupt can also be masked) • Trigger pulse output (UBCTRG) on break condition Selection of trigger pulse width (φ ×1, ×4, ×8, ×16) Bus state controller (BSC) • Simplifies configuration of an on-chip debugger • Supports external memory access (SRAM and ROM directly connectable) 8/16-bit bus space • 3.3 V bus interface • 16 MB address space divided into four areas, with the following parameters settable for each area: Bus size (8 or 16 bits) Number of wait cycles Chip select signals (CS0 to CS3) output for each area • Wait cycles can be inserted using an external WAIT signal • External access in minimum of two cycles • Provision for idle cycle insertion to prevent bus collisions 3 Table 1.1 SH7052F/SH7053F/SH7054F Features (cont) Item Features Direct memory access controller (DMAC) (4 channels) • DMA transfer possible for the following devices: External memory, on-chip memory, on-chip peripheral modules (excluding DMAC, UBC, BSC) • DMA transfer requests by on-chip modules SCI, A/D converter, ATU-II, HCAN • Cycle steal or burst mode transfer • Dual address mode Direct transfer mode Indirect transfer mode (channel 3 only) Advanced timer unit-II (ATU-II) • Address reload function (channel 2 only) • Transfer data width: Byte/word/longword • Maximum 63 inputs or outputs can be processed Four 32-bit input capture inputs Twenty-eight 16-bit input capture inputs/output compare outputs Sixteen 16-bit one-shot pulse outputs Eight 16-bit PWM outputs Six 8-bit event counters One gap detection function • I/O pin output inversion function Advanced pulse controller (APC) • Maximum eight pulse outputs on reception of ATU-II (channel 11) comparematch signal Watchdog timer (WDT) (1 channel) • Can be switched between watchdog timer and interval timer function • Internal reset, external signal, or interrupt generated by counter overflow • Two kinds of internal reset Power-on reset Manual reset Compare-match timer (CMT) (2 channels) 4 • Selection of 4 counter input clocks • A compare-match interrupt can be requested independently for each channel Table 1.1 SH7052F/SH7053F/SH7054F Features (cont) Item Features Serial communication interface (SCI) (5 channels) • Selection of asynchronous or synchronous mode • Simultaneous transmission/reception (full-duplex) capability • Serial data communication possible between multiple processors (asynchronous mode) • Clock inversion function • LSB-/MSB-first selection function for transmission Hitachi controller area network (HCAN) (1 channel) • CAN version: Bosch 2.0B active compatible • Buffer size (per channel): Transmit/receive × 15, receive-only × 1 • Receive message filtering capability A/D converter • Sixteen channels • Two sample-and-hold circuits Independent operation of 12 channels × 1 and 4 channels × 1 • Selection of two conversion modes Single conversion mode Scan mode • Continuous scan mode • Single-cycle scan mode Advanced user debugger (AUD) • Can be activated by external trigger or ATU-II compare-match • 10-bit resolution • Accuracy: ±2 LSB • Eight dedicated pins • RAM monitor mode Data input/output frequency: φ/4 or less Possible to read/write to a module connected to the internal/external bus I/O ports (including timer I/O pins, address and data buses) • Branch address output mode • Dual-function input/output pins: 135 • Schmitt input pins: NMI, IRQ, RES, HSTBY, FWE, TCLK, IC, IC/OC, SCK, ADTRG • Input port protection 5 Table 1.1 SH7052F/SH7053F/SH7054F Features (cont) Item Features On-chip memory 6 Product Memory SH7052F SH7053F SH7054F Flash memory 256 kB 256 kB 384 kB RAM 12 kB 16 kB 16 kB ; ;; ;; ; Port/control signals Port/address signals ROM (Flash) 256kB/384kB* CK EXTAL XTAL PLLVCC PLLVSS PLLCAP Vcc (×6) PVcc1 (×4) PVcc2 (×6) Vss (×16) AVref AVcc AVss AN15 to 0 AUDRST AUDMD AUDATA3 to 0 AUDCK AUDSYNC Clock pulse generator CPU DMAC (4 channels) Multipiler Interrupt controller HCAN (1 channel) ATU-II WDT Port : Peripheral address bus (9 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) Note: * SH7052F: ROM 256kB RAM 12kB SH7053F: ROM 256kB RAM 16kB SH7054F: ROM 384kB RAM 16kB Port Port Port PJ15/TI9F PJ14/TI9E PJ13/TI9D PJ12/TI9C PJ11/TI9B PJ10/TI9A PJ9/TIO5D PJ8/TIO5C PJ7/TIO2H PJ6/TIO2G PJ5/TIO2F PJ4/TIO2E PJ3/TIO2D PJ2/TIO2C PJ1/TIO2B PJ0/TIO2A A/D convertor PK15/TO8P PK14/TO8O PK13/TO8N PK12/TO8M PK11/TO8L PK10/TO8K PK9/TO8J PK8/TO8I PK7/TO8H PK6/TO8G PK5/TO8F PK4/TO8E PK3/TO8D PK2/TO8C PK1/TO8B PK0/TO8A AUD PH15/D15 PH14/D14 PH13/D13 PH12/D12 PH11/D11 PH10/D10 PH9/D9 PH8/D8 PH7/D7 PH6/D6 PH5/D5 PH4/D4 PH3/D3 PH2/D2 PH1/D1 PH0/D0 BSC SCI (5 channels) CMT (2 channels) PD0/TIO1A PD1/TIO1B PD2/TIO1C PD3/TIO1D PD4/TIO1E PD5/TIO1F PD6/TIO1G PD7/TIO1H PD8/PULS0 PD9/PULS1 PD10/PULS2 PD11/PULS3 PD12/PULS4 PD13/PULS6/HTxD RAM 12kB/16kB* Port/address signals RES HSTBY FWE MD2 MD1 MD0 NMI WDTOVF PF13/CS3 PF12/CS2 PF11/CS1 PF10/CS0 PF5/A21/POD PF4/A20 PF3/A19 PF2/A18 PF1/A17 PF0/A16 PE15/A15 PE14/A14 PE13/A13 PE12/A12 PE11/A11 PE10/A10 PE9/A9 PE8/A8 PE7/A7 PE6/A6 PE5/A5 PE4/A4 PE3/A3 PE2/A2 PE1/A1 PE0/A0 Block Diagram PF15/BREQ PF14/BACK PF8/WAIT PF9/RD PF7/WRH PF6/WRL 1.2 PA0/TI0A PA1/TI0B PA2/TI0C PA3/TI0D PA4/TIO3A PA5/TIO3B PA6/TIO3C PA7/TIO3D PA8/TIO4A PA9/TIO4B PA10/TIO4C PA11/TIO4D PA12/TIO5A PA13/TIO5B PA14/TxD0 PA15/RxD0 PB0/TO6A PB1/TO6B PB2/TO6C PB3/TO6D PB4/TO7A/TO8A PB5/TO7B/TO8B PB6/TO7C/TO8C PB7/TO7D/TO8D PB8/TxD3/TO8E PB9/RxD3/TO8F PB10/TxD4/HTxD/TO8G PB11/RxD4/HRxD/TO8H PB12/TCLKA/UBCTRG PB13/SCK0 PB14/SCK1/TCLKB/TI10 PB15/PULS5/SCK2 PC0/TxD1 PC1/RxD1 PC2/TxD2 PC3/RxD2 PC4/IRQ0 PG0/PULS7/HRxD PG1/IRQ1 PG2/IRQ2 PG3/IRQ3/ADTRG0 Figure 1.1 Block Diagram 7 Pin Description 1.3.1 Pin Arrangement 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PK12/TO8M PK11/TO8L PK10/TO8K PK9/TO8J PK8/TO8I PK7/TO8H PK6/TO8G PK5/TO8F PK4/TO8E PK3/TO8D PK2/TO8C PK1/TO8B PK0/TO8A Vss PJ15/TI9F PVcc2 PJ14/TI9E PJ13/TI9D PJ12/TI9C PJ11/TI9B PJ10/TI9A PJ9/TIO5D PJ8/TIO5C Vss PJ7/TIO2H Vcc PJ6/TIO2G PJ5/TIO2F PJ4/TIO2E PJ3/TIO2D PJ2/TIO2C Vss PJ1/TIO2B Vcc PJ0/TIO2A PG3/IRQ3/ADTRG0 PG2/IRQ2 PG1/IRQ1 PG0/PULS7/HRxD Vss PC4/IRQ0 PVcc2 PC3/RxD2 PC2/TxD2 PC1/RxD1 PC0/TxD1 PB15/PULS5/SCK2 PB14/SCK1/TCLKB/TI10 PB13/SCK0 PB12/TCLKA/UBCTRG PB11/RxD4/HRxD/TO8H PB10/TxD4/HTxD/TO8G 1.3 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 FP-208A (Top view) INDEX PF1/A17 PF2/A18 PF3/A19 PF4/A20 PF5/A21/POD PF6/WRL PF7/WRH PF8/WAIT PF9/RD PVcc1 PF10/CS0 Vss PF11/CS1 PF12/CS2 PF13/CS3 PF14/BACK PF15/BREQ MD2 Vcc CK Vss MD1 MD0 EXTAL Vss XTAL Vcc FWE HSTBY RES NMI PLLVcc PLLCAP PLLVss PH0/D0 PH1/D1 PH2/D2 PH3/D3 PH4/D4 PH5/D5 PH6/D6 PVcc1 PH7/D7 Vss PH8/D8 PH9/D9 PH10/D10 PH11/D11 PH12/D12 PH13/D13 PH14/D14 PH15/D15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 PK13/TO8N PVcc2 PK14/TO8O Vss PK15/TO8P AUDRST AUDMD AUDATA0 AUDATA1 AUDATA2 AUDATA3 AUDCK AUDSYNC PD0/TIO1A PD1/TIO1B PD2/TIO1C PD3/TIO1D PVcc2 PD4/TIO1E Vss PD5/TIO1F PD6/TIO1G PD7/TIO1H PD8/PULS0 PD9/PULS1 PD10/PULS2 Vcc PD11/PULS3 Vss PD12/PULS4 PD13/PULS6/HTxD PE0/A0 PE1/A1 PE2/A2 PE3/A3 PE4/A4 PE5/A5 PVcc1 PE6/A6 Vss PE7/A7 PE8/A8 PE9/A9 PE10/A10 PE11/A11 PE12/A12 PE13/A13 PE14/A14 PVcc1 PE15/A15 Vss PF0/A16 Figure 1.2 Pin Arrangement 8 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 PB9/RxD3/TO8F PB8/TxD3/TO8E PB7/TO7D/TO8D PB6/TO7C/TO8C PB5/TO7B/TO8B PB4/TO7A/TO8A PB3/TO6D Vss PB2/TO6C PVcc2 PB1/TO6B PB0/TO6A PA15/RxD0 PA14/TxD0 PA13/TIO5B PA12/TIO5A PA11/TIO4D PA10/TIO4C PA9/TIO4B PA8/TIO4A PA7/TIO3D PA6/TIO3C PA5/TIO3B Vss PA4/TIO3A Vcc PA3/TI0D PA2/TI0C Vss PA1/TI0B PVcc2 PA0/TI0A WDTOVF AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVss AVref AVcc 1.3.2 Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Type Symbol Pin No. I/O Name Function Power supply VCC 19, 27, 79, 123, 131, 183 Input Power supply Power supply for chip-internal and system ports (RES, MD2 to MD0, FWE, HSTBY, NMI, CK, EXTAL, XTAL). Connect all V CC pins to the system power supply. The chip will not operate if there are any open pins. PVCC1 10, 42, 194, Input 205 Port power supply 1 Power supply for bus ports (ports E, F, and H). Connect all PV CC1 pins to the system bus power supply. The chip will not operate if there are any open pins. PVCC2 74, 95, 115, Input 141, 158, 174 Port power supply 2 Power supply for peripheral module ports (ports A, B, C, D, G, J, K, the AUD, and WDTOVF). Connect all PV CC2 pins to the system peripheral module power supply. The chip will not operate if there are any open pins. VSS 12, 21, 25, 44, 76, 81, 97, 117, 125, 133, 143, 160, 176, 185, 196, 207 Input Ground For connection to ground. 28 Input Flash memory FWE Connect all V SS pins to the system ground. The chip will not operate if there are any open pins. Flash write enable Connected to ground in normal operation. Apply VCC during on-board programming. 9 Table 1.2 Pin Functions (cont) Type Symbol Pin No. I/O Name Function Clock PLLVCC 32 Input PLL power supply On-chip PLL oscillator power supply. For power supply connection, see section 4, Clock Pulse Generator. PLLVSS 34 Input PLL ground On-chip PLL oscillator ground. For power supply connection, see section 4, Clock Pulse Generator. PLLCAP 33 Input PLL capacitance On-chip PLL oscillator external capacitance connection pin. For external capacitance connection, see section 4, Clock Pulse Generator. EXTAL 24 Input External clock For connection to a crystal resonator. An external clock source can also be connected to the EXTAL pin. XTAL 26 Input Crystal For connection to a crystal resonator. CK 20 Output System clock Supplies the system clock to peripheral devices. 30 Input Power-on reset Executes a power-on reset when driven low. WDTOVF 72 Output Watchdog timer overflow WDT overflow output signal. BREQ 17 Input Bus request Driven low when an external device requests the bus. BACK 16 Output Bus request acknowledge Indicates that the bus has been granted to an external device. The device that output the BREQ signal recognizes that the bus has been acquired when it receives the BACK signal. System control RES 10 Table 1.2 Pin Functions (cont) Type Symbol Pin No. I/O Name Function Operating mode control MD0 to MD2 18, 22, 23 Input Mode setting These pins determine the operating mode. Do not change the input values during operation. HSTBY 29 Input Hardware standby When driven low, this pin forces a transition to hardware standby mode. NMI 31 Input Nonmaskable interrupt Nonmaskable interrupt request pin. Interrupts Acceptance on the rising edge or falling edge can be selected. IRQ0 to IRQ3 116, 119, 120, 121 Input Output Interrupt requests 0 to 3 Maskable interrupt request pins. Address bus Address output pins. Level input or edge input can be selected. Address bus A0 to A21 1 to 5, 188 to 193, 195, 197 to 204, 206, 208 Data bus D0 to D15 35 to 41, Input/ 43, 45 to 52 output Data bus 16-bit bidirectional data bus pins. Bus control CS0 to CS3 11, 13 to 15 Output Chip select 0 to 3 Chip select signals for external memory or devices. RD 9 Output Read Indicates reading from an external device. WRH 7 Output Upper write Indicates writing of the upper 8 bits of external data. WRL 6 Output Lower write Indicates writing of the lower 8 bits of external data. WAIT 8 Input Wait Input for wait cycle insertion in bus cycles during external space access. 11 Table 1.2 Pin Functions (cont) Type Symbol Pin No. I/O Name Function Advanced timer unit-II (ATU-II) TCLKA TCLKB 107, 109 Input ATU-II timer clock input ATU-II counter external clock Input pins. TI0A to TI0D 73, 75, 77, 78 Input ATU-II input capture (channel 0) Channel 0 input capture input pins. TIO1A to TIO1H 170 to 173, 175, 177 to 179 Input/ output ATU-II input capture/output compare (channel 1) Channel 1 input capture input/output compare output pins. TIO2A to TIO2H 122, 124, 126 to 130, 132 Input/ output ATU-II input capture/output compare (channel 2) Channel 2 input capture input/output compare output pins. TIO3A to TIO3D 80, 82 to 84 Input/ output ATU-II input capture/output compare/ PWM output (channel 3) Channel 3 input capture input/output compare/PWM output pins. TIO4A to TIO4D 85 to 88 Input/ output ATU-II input capture/output compare/ PWM output (channel 4) Channel 4 input capture input/output compare/PWM output pins. TIO5A to TIO5D 89, 90, 134, Input/ 135 output ATU-II input capture/output compare/ PWM output (channel 5) Channel 5 input capture input/output compare/PWM output pins. TO6A to TO6D 93, 94, 96, 98 Output ATU-II PWM output (channel 6) Channel 6 PWM output pins. TO7A to TO7D 99 to 102 Output ATU-II PWM output (channel 7) Channel 7 PWM output pins. TO8A to TO8P 99 to 106, 144 to 157, 159, 161 Output ATU-II Channel 8 down-counter oneone-shot pulse shot pulse output pins. (channel 8) 12 Table 1.2 Pin Functions (cont) Type Symbol Pin No. I/O Name Function Advanced timer unit-II (ATU-II) TI9A to TI9F 136 to 140, 142 Input ATU-II event input (channel 9) Channel 9 event counter input pins. TI10 109 Input Channel 10 external clock ATU-II multiplied clock input pin. generation (channel 10) Advanced PULS0 to pulse controller PULS7 (APC) 110, 118, 180 to 182, 184, 186, 187 Output APC pulse outputs 0 to 7 APC pulse output pins. Serial TxD0 to communication TxD4 interface (SCI) 91, 103, 105, Output 111, 113 Transmit data (channels 0 to 4) SCI0 to SCI4 transmit data output pins. RxD0 to RxD4 92, 104, 106, Input 112, 114 Receive data (channels 0 to 4) SCI0 to SCI4 receive data input pins. SCK0 to SCK2 108, 109, 110 Input/ output Serial clock (channels 0 to 2) SCI0 to SCI2 clock input/output pins. Hitachi HTxD controller area network HRxD (HCAN) 105, 187 Output Transmit data CAN bus transmit data output pins. 106, 118 input Receive data CAN bus receive data input pins. A/D converter AVCC 53 Input Analog power supply A/D converter power supply. AVSS 55 Input Analog ground A/D converter power supply. AVref 54 Input Analog reference power supply Analog reference power supply input pins. AN0 to AN15 56 to 71 Input Analog input Analog signal input pins. ADTRG0 121 Input A/D conversion External trigger input pins for trigger input starting A/D conversion. 13 Table 1.2 Type Pin Functions (cont) Symbol Pin No. I/O Name Function User break UBCTRG controller (UBC) 107 Output User break trigger output UBC condition match trigger output pin. Advanced AUDATA0 user debugger to (AUD) AUDATA3 164 to 167 Input/ output AUD data Realtime trace mode: Branch destination address output pins. RAM monitor mode: Monitor address input / data input/output pins. AUDRST 162 Input AUD reset AUDMD 163 Input AUD mode Reset signal input pin. Mode select signal input pin. Realtime trace mode: Low RAM monitor mode: High AUDCK 168 Input/ output AUD clock Realtime trace mode: Serial clock output pin. RAM monitor mode: Serial clock input pin. AUDSYNC 169 Input/ output AUD Realtime trace mode: Data synchronization start position identification signal signal output pin. RAM monitor mode: Data start position identification signal input pin. I/O ports 14 POD 5 PA0 to PA15 73, 75, 77, Input/ 78, 80, 82 to output 92 Input Port output disable Port A Input pin for port pin drive control when general port is set for output. General input/output port pins. Input or output can be specified bit by bit. Table 1.2 Pin Functions (cont) Type Symbol Pin No. I/O Name Function I/O ports PB0 to PB15 93, 94, 96, 98 to 110 Input/ output Port B General input/output port pins. PC0 to PC4 111 to 114, 116 Input/ output Port C PD0 to PD13 170 to 173, 175, 177 to 182, 184, 186, 187 Input/ output Port D PE0 to PE15 188 to 193, 195, 197 to 204, 206 Input/ output Port E PF0 to PF15 1 to 9, 11, Input/ 13 to 17, 208 output Port F PG0 to PG3 118 to 121 Input/ output Port G PH0 to PH15 35 to 41, 43, Input/ 45 to 52 output Port H PJ0 to PJ15 122, 124, 126 to 130, 132, 134 to 140, 142 Input/ output Port J PK0 to PK15 144 to 157, 159, 161 Input/ output Port K Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. 15 1.3.3 Table 1.3 Pin Assignments Pin Assignments Pin No. MCU Mode Programmer Mode 1 PF1/A17 A17 2 PF2/A18 A18 3 PF3/A19 N.C 4 PF4/A20 N.C 5 PF5/A21/POD N.C 6 PF6/WRL N.C 7 PF7/WRH N.C. 8 PF8/WAIT N.C. 9 PF9/RD N.C. 10 PVcc1 Vcc 11 PF10/CS0 N.C. 12 Vss Vss 13 PF11/CS1 Vcc 14 PF12/CS2 Vcc 15 PF13/CS3 Vss 16 PF14/BACK N.C. 17 PF15/BREQ Vcc 18 MD2 Vss 19 Vcc Vcc 20 CK N.C. 21 Vss Vss 22 MD1 Vcc 23 MD0 Vcc 24 EXTAL EXTAL 25 Vss Vss 26 XTAL XTAL 27 Vcc Vcc 28 FWE FWE 29 HSTBY Vcc 30 RES RES 16 Table 1.3 Pin Assignments (cont) Pin No. MCU Mode Programmer Mode 31 NMI Vss 32 PLLVcc PLLVcc 33 PLLCAP PLLCAP 34 PLLVss PLLVss 35 PH0/D0 D0 36 PH1/D1 D1 37 PH2/D2 D2 38 PH3/D3 D3 39 PH4/D4 D4 40 PH5/D5 D5 41 PH6/D6 D6 42 PVcc1 Vcc 43 PH7/D7 D7 44 Vss Vss 45 PH8/D8 N.C. 46 PH9/D9 N.C. 47 PH10/D10 N.C. 48 PH11/D11 N.C. 49 PH12/D12 N.C. 50 PH13/D13 N.C. 51 PH14/D14 N.C. 52 PH15/D15 N.C. 53 AVcc Vcc 54 AVref Vcc 55 AVss Vss 56 AN0 N.C. 57 AN1 N.C. 58 AN2 N.C. 59 AN3 N.C. 60 AN4 N.C. 61 AN5 N.C. 17 Table 1.3 Pin Assignments (cont) Pin No. MCU Mode Programmer Mode 62 AN6 N.C. 63 AN7 N.C. 64 AN8 N.C. 65 AN9 N.C. 66 AN10 N.C. 67 AN11 N.C. 68 AN12 N.C. 69 AN13 N.C. 70 AN14 N.C. 71 AN15 N.C. 72 WDTOVF N.C. 73 PA0/TI0A N.C. 74 PVcc2 Vcc 75 PA1/TI0B N.C. 76 Vss Vss 77 PA2/TI0C N.C. 78 PA3/TI0D N.C. 79 Vcc Vcc 80 PA4/TIO3A N.C. 81 Vss Vss 82 PA5/TIO3B N.C. 83 PA6/TIO3C N.C. 84 PA7/TIO3D N.C. 85 PA8/TIO4A N.C. 86 PA9/TIO4B N.C. 87 PA10/TIO4C N.C. 88 PA11/TIO4D N.C. 89 PA12/TIO5A N.C. 90 PA13/TIO5B N.C. 91 PA14/TxD0 N.C. 92 PA15/RxD0 N.C. 18 Table 1.3 Pin Assignments (cont) Pin No. MCU Mode Programmer Mode 93 PB0/TO6A N.C. 94 PB1/TO6B N.C. 95 PVcc2 Vcc 96 PB2/TO6C N.C. 97 Vss Vss 98 PB3/TO6D N.C. 99 PB4/TO7A/TO8A N.C. 100 PB5/TO7B/TO8B N.C. 101 PB6/TO7C/TO8C N.C. 102 PB7/TO7D/TO8D N.C. 103 PB8/TxD3/TO8E N.C. 104 PB9/RxD3/TO8F N.C. 105 PB10/TxD4/HTxD/TO8G N.C. 106 PB11/RxD4/HRxD/TO8H N.C. 107 PB12/TCLKA/UBCTRG N.C. 108 PB13/SCK0 N.C. 109 PB14/SCK1/TCLKB/TI10 N.C. 110 PB15/PULS5/SCK2 N.C. 111 PC0/TxD1 N.C. 112 PC1/RxD1 N.C. 113 PC2/TxD2 N.C. 114 PC3/RxD2 N.C. 115 PVcc2 Vcc 116 PC4/IRQ0 N.C. 117 Vss Vss 118 PG0/PULS7/HRxD N.C. 119 PG1/IRQ1 CE 120 PG2/IRQ2 WE 121 PG3/IRQ3/ADTRG0 OE 122 PJ0/TIO2A N.C. 123 Vcc Vcc 19 Table 1.3 Pin Assignments (cont) Pin No. MCU Mode Programmer Mode 124 PJ1/TIO2B N.C. 125 Vss Vss 126 PJ2/TIO2C N.C. 127 PJ3/TIO2D N.C. 128 PJ4/TIO2E N.C. 129 PJ5/TIO2F N.C. 130 PJ6/TIO2G N.C. 131 Vcc Vcc 132 PJ7/TIO2H N.C. 133 Vss Vss 134 PJ8/TIO5C N.C. 135 PJ9/TIO5D N.C. 136 PJ10/TI9A N.C. 137 PJ11/TI9B N.C. 138 PJ12/TI9C N.C. 139 PJ13/TI9D N.C. 140 PJ14/TI9E N.C. 141 PVcc2 Vcc 142 PJ15/TI9F N.C. 143 Vss Vss 144 PK0/TO8A N.C. 145 PK1/TO8B N.C. 146 PK2/TO8C N.C. 147 PK3/TO8D N.C. 148 PK4/TO8E N.C. 149 PK5/TO8F N.C. 150 PK6/TO8G N.C. 151 PK7/TO8H N.C. 152 PK8/TO8I N.C. 153 PK9/TO8J N.C. 154 PK10/TO8K N.C. 20 Table 1.3 Pin Assignments (cont) Pin No. MCU Mode Programmer Mode 155 PK11/TO8L N.C. 156 PK12/TO8M N.C. 157 PK13/TO8N N.C. 158 PVcc2 Vcc 159 PK14/TO8O N.C. 160 Vss Vss 161 PK15/TO8P N.C. 162 AUDRST N.C. 163 AUDMD N.C. 164 AUDATA0 N.C. 165 AUDATA1 N.C. 166 AUDATA2 N.C. 167 AUDATA3 N.C. 168 AUDCK N.C. 169 AUDSYNC N.C. 170 PD0/TIO1A N.C. 171 PD1/TIO1B N.C. 172 PD2/TIO1C N.C. 173 PD3/TIO1D N.C. 174 PVcc2 Vcc 175 PD4/TIO1E N.C. 176 Vss Vss 177 PD5/TIO1F N.C. 178 PD6/TIO1G N.C. 179 PD7/TIO1H N.C. 180 PD8/PULS0 N.C. 181 PD9/PULS1 N.C. 182 PD10/PULS2 N.C. 183 Vcc Vcc 184 PD11/PULS3 N.C. 185 Vss Vss 21 Table 1.3 Pin Assignments (cont) Pin No. MCU Mode Programmer Mode 186 PD12/PULS4 N.C. 187 PD13/PULS6/HTxD N.C. 188 PE0/A0 A0 189 PE1/A1 A1 190 PE2/A2 A2 191 PE3/A3 A3 192 PE4/A4 A4 193 PE5/A5 A5 194 PVcc1 Vcc 195 PE6/A6 A6 196 Vss Vss 197 PE7/A7 A7 198 PE8/A8 A8 199 PE9/A9 A9 200 PE10/A10 A10 201 PE11/A11 A11 202 PE12/A12 A12 203 PE13/A13 A13 204 PE14/A14 A14 205 PVcc1 Vcc 206 PE15/A15 A15 207 Vss Vss 208 PF0/A16 A16 22 Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0 to R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. Figure 2.1 shows the general registers. 31 0 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 Notes: 1. 2. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. R15 functions as a hardware stack pointer (SP) during exception processing. Figure 2.1 General Registers 23 2.1.2 Control Registers The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts). Figure 2.2 shows a control register. 31 SR 9 8 7 6 5 4 32 1 0 M Q I3 I2 I1 I0 SR: Status register ST T bit: The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, and CLRT instructions use the T bit to indicate true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S, DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow. S bit: Used by the MAC instruction. Reserved bits. This bit always read 0. The write value should always be 0. Bits I0 to I3: Interrupt mask bits. M and Q bits: Used by the DIV0U, DIV0S, and DIV1 instructions. Reserved bits. 0 is read. Write only. 31 GBR 31 0 Global base register (GBR): Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register areas and in logic operations. 0 VBR Vector base register (VBR): Stores the base address of the exception processing vector area. Figure 2.2 Control Registers 24 2.1.3 System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply and accumulate registers store the results of multiply and accumulate operations. The procedure register stores the return address from the subroutine procedure. The program counter stores program addresses to control the flow of the processing. Figure 2.3 shows a system register. 31 0 MACH MACL 31 0 Procedure register (PR): Stores a return address from a subroutine procedure. 0 Program counter (PC): Indicates the fourth byte (second instruction) after the current instruction. PR 31 Multiply and accumulate (MAC) registers high and low (MACH, MACL): Stores the results of multiply and accumulate operations. PC Figure 2.3 System Registers 2.1.4 Initial Values of Registers Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers Classification Register Initial Value General registers R0 to R14 Undefined R15 (SP) Value of the stack pointer in the vector address table SR Bits I3 to I0 are 1111 (H'F), reserved bits are 0, and other bits are undefined GBR Undefined VBR H'00000000 MACH, MACL, PR Undefined PC Value of the program counter in the vector address table Control registers System registers 25 2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure 2.4). 31 0 Longword Figure 2.4 Longword Operand 2.2.2 Data Format in Memory Memory data formats are classified into bytes, words, and longwords. Byte data can be located at any address, but word data must begin at address 2n and longword data at address 4n. An address error will occur if access is attempted beginning at an address other than these boundaries. In such cases, the data accessed cannot be guaranteed. The hardware stack area, referred to by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register (figure 2.5). Address m + 1 Address m 23 31 Byte Address 2n Address 4n Address m + 3 Address m + 2 7 15 Byte Byte Word 0 Byte Word Longword Figure 2.5 Byte, Word, and Longword Alignment 2.2.3 Immediate Data Format Byte (8-bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. 26 Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. 2.3 Instruction Features 2.3.1 RISC-Type Instruction Set All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using the pipeline system. Instructions are executed in 25 ns at 40 MHz. Data Length: Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations. It also is handled as longword data (table 2.2). Table 2.2 Sign Extension of Word Data SH7052F/SH7053F/SH7054F CPU Description MOV.W @(disp,PC),R1 ADD R1,R0 ......... .DATA.W H'1234 Data is sign-extended to 32 bits, and R1 becomes H'00001234. It is next operated upon by an ADD instruction. Example of Conventional CPU ADD.W #H'1234,R0 Note: @(disp, PC) accesses the immediate data. Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction following the delayed branch instruction (table 2.3). This reduces pipeline disruption when branching. There are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. 27 Table 2.3 Delayed Branch Instructions SH7052F/SH7053F/SH7054F CPU Description BRA TRGET ADD R1,R0 Executes an ADD before branching to TRGET Example of Conventional CPU ADD.W R1,R0 BRA TRGET Multiplication/Accumulation Operation: 16-bit × 16-bit → 32-bit multiplication operations are executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiplication/accumulation operations are executed in two to three cycles. 32-bit × 32-bit → 64-bit and 32-bit × 32-bit + 64bit → 64-bit multiplication/accumulation operations are executed in two to four cycles. T Bit: The T bit in the status register reflects the result of the comparison, and its value is the condition (true/false) that determines whether the program will branch. The number of instructions that change the T bit is kept to a minimum to improve the processing speed. Table 2.4 T Bit SH7052F/SH7053F/ SH7054F CPU CMP/GE R1,R0 BT TRGET0 BF TRGET1 ADD #1,R0 CMP/EQ #0,R0 BT TRGET Description Example of Conventional CPU T bit is set when R0 ≥ R1. The program branches to TRGET0 when R0 ≥ R1 and to TRGET1 when R0 < R1. CMP.W R1,R0 BGE TRGET0 BLT TRGET1 T bit is not changed by ADD. T bit is SUB.W set when R0 = 0. The program BEQ branches if R0 = 0. #1,R0 TRGET Immediate Data: Byte (8-bit) immediate data resides in instruction code. Word or longword immediate data is not input via instruction codes but is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement (table 2.5). 28 Table 2.5 Immediate Data Accessing Classification SH7052F/SH7053F/SH7054F CPU Example of Conventional CPU 8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOV.W @(disp,PC),R0 MOV.W #H'1234,R0 MOV.L #H'12345678,R0 ................. .DATA.W 32-bit immediate MOV.L H'1234 @(disp,PC),R0 ................. .DATA.L H'12345678 Note: @(disp, PC) accesses the immediate data. Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect register addressing mode (table 2.6). Table 2.6 Absolute Address Accessing Classification SH7052F/SH7053F/SH7054F CPU Example of Conventional CPU Absolute address MOV.L @(disp,PC),R1 MOV.B MOV.B @R1,R0 @H'12345678,R0 .................. .DATA.L H'12345678 Note: @(disp,PC) accesses the immediate data. 16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the preexisting displacement value is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect indexed register addressing mode (table 2.7). Table 2.7 Displacement Accessing Classification SH7052F/SH7053F/SH7054F CPU Example of Conventional CPU 16-bit displacement MOV.W MOV.W MOV.W @(disp,PC),R0 @(H'1234,R1),R2 @(R0,R1),R2 .................. .DATA.W H'1234 Note: @(disp,PC) accesses the immediate data. 29 2.3.2 Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Modes and Effective Addresses Addressing Mode Instruction Format Effective Addresses Calculation Direct register addressing Rn The effective address is register Rn. (The operand is the contents of register Rn.) — Indirect register addressing @Rn The effective address is the content of register Rn. Rn Post-increment indirect register addressing @Rn+ Rn Equation Rn The effective address is the content of register Rn. A constant is added to the content of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn Rn + 1/2/4 @–Rn Rn 1/2/4 30 Byte: Rn + 1 → Rn Longword: Rn + 4 → Rn The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn – 1/2/4 (After the instruction executes) Word: Rn + 2 → Rn + 1/2/4 Pre-decrement indirect register addressing Rn – Rn – 1/2/4 Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn (Instruction executed with Rn after calculation) Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mode Instruction Format Effective Addresses Calculation Indirect register addressing with displacement @(disp:4, The effective address is Rn plus a 4-bit Rn) displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Rn disp (zero-extended) Equation Byte: Rn + disp Word: Rn + disp × 2 Longword: Rn + disp × 4 Rn + disp × 1/2/4 + × 1/2/4 Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0. register Rn addressing + Rn + R0 Rn + R0 R0 Indirect GBR addressing with displacement @(disp:8, The effective address is the GBR value plus an GBR) 8-bit displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR disp (zero-extended) + GBR + disp × 1/2/4 Byte: GBR + disp Word: GBR + disp × 2 Longword: GBR + disp × 4 × 1/2/4 31 Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mode Instruction Format Effective Addresses Calculation Indirect indexed @(R0, GBR) The effective address is the GBR value plus the R0. GBR addressing GBR + Equation GBR + R0 GBR + R0 R0 PC relative addressing with displacement @(disp:8, The effective address is the PC value plus an 8-bit PC) displacement (disp). The value of disp is zeroextended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked. PC & H'FFFFFFFC + disp (zero-extended) × 2/4 32 (for longword) PC + disp × 2 or PC & H'FFFFFFFC + disp × 4 Word: PC + disp × 2 Longword: PC & H'FFFFFFFC + disp × 4 Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mode Instruction Format Effective Addresses Calculation PC relative addressing disp:8 The effective address is the PC value sign-extended with an 8-bit displacement (disp), doubled, and added to the PC value. Equation PC + disp × 2 PC disp (sign-extended) + PC + disp × 2 × 2 disp:12 The effective address is the PC value sign-extended with a 12-bit displacement (disp), doubled, and added to the PC value. PC + disp × 2 PC disp (sign-extended) + PC + disp × 2 × 2 Rn The effective address is the register PC value plus Rn. PC + Rn PC + PC + Rn Rn Immediate addressing #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions are zero-extended. — #imm:8 The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions are sign-extended. — #imm:8 The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and is quadrupled. — 33 2.3.3 Instruction Format Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols are used as follows: • • • • • xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement Table 2.9 Instruction Formats Instruction Formats Source Operand Destination Operand Example 0 format — — NOP — nnnn: Direct register MOVT Rn Control register or system register nnnn: Direct register STS MACH,Rn Control register or system register nnnn: Indirect pre- STC.L decrement register SR,@-Rn mmmm: Direct register Control register or system register LDC Rm,SR mmmm: Indirect post-increment register Control register or system register LDC.L @Rm+,SR mmmm: Direct register — JMP @Rm mmmm: PC relative using Rm — BRAF Rm 15 0 xxxx xxxx xxxx xxxx n format 15 0 xxxx nnnn xxxx xxxx m format 15 0 xxxx mmmm xxxx 34 xxxx Table 2.9 Instruction Formats (cont) Source Operand Destination Operand Instruction Formats nm format 15 0 xxxx nnnn mmmm xxxx Example mmmm: Direct register nnnn: Direct register ADD Rm,Rn mmmm: Direct register nnnn: Indirect register MOV.L Rm,@Rn mmmm: Indirect post-increment register (multiply/ accumulate) MACH, MACL MAC.W @Rm+,@Rn+ mmmm: Indirect post-increment register nnnn: Direct register MOV.L @Rm+,Rn mmmm: Direct register nnnn: Indirect predecrement register MOV.L Rm,@-Rn mmmm: Direct register nnnn: Indirect indexed register MOV.L Rm,@(R0,Rn) mmmmdddd: indirect register with displacement R0 (Direct register) MOV.B @(disp,Rm),R0 R0 (Direct register) nnnndddd: Indirect register with displacement MOV.B R0,@(disp,Rn) mmmm: Direct register nnnndddd: Indirect register with displacement MOV.L Rm,@(disp,Rn) mmmmdddd: Indirect register with displacement nnnn: Direct register MOV.L @(disp,Rm),Rn nnnn*: Indirect post-increment register (multiply/ accumulate) md format 15 0 xxxx xxxx mmmm dddd nd4 format 15 xxxx xxxx 0 nnnn dddd nmd format 15 0 xxxx nnnn mmmm dddd Note: * In multiply/accumulate instructions, nnnn is the source register. 35 Table 2.9 Instruction Formats (cont) Source Operand Destination Operand Instruction Formats d format 15 0 xxxx xxxx dddd dddd d12 format 15 0 xxxx dddd dddd 15 0 xxxx nnnn dddd dddd i format 15 0 xxxx xxxx iiii 15 0 36 nnnn iiii R0(Direct register) dddddddd: Indirect GBR with displacement dddddddd: PC relative with displacement R0 (Direct register) MOVA @(disp,PC),R0 dddddddd: PC relative — BF label dddddddddddd: PC relative — BRA label dddddddd: PC relative with displacement nnnn: Direct register MOV.L @(disp,PC),Rn iiiiiiii: Immediate Indirect indexed GBR AND.B #imm,@(R0,GBR) iiiiiiii: Immediate R0 (Direct register) AND #imm,R0 iiiiiiii: Immediate — TRAPA #imm iiiiiiii: Immediate nnnn: Direct register ADD #imm,Rn MOV.L R0,@(disp,GBR) (label = disp + PC) iiii ni format xxxx dddddddd: Indirect GBR with displacement dddd nd8 format Example R0 (Direct register) MOV.L @(disp,GBR),R0 iiii 2.4 Instruction Set by Classification Table 2.10 Classification of Instructions Operation Classification Types Code Function Data transfer Arithmetic operations 5 21 No. of Instructions MOV Data transfer, immediate data transfer, 39 peripheral module data transfer, structure data transfer MOVA Effective address transfer MOVT T bit transfer SWAP Swap of upper and lower bytes XTRCT Extraction of the middle of registers connected ADD Binary addition ADDC Binary addition with carry ADDV Binary addition with overflow check 33 CMP/cond Comparison DIV1 Division DIV0S Initialization of signed division DIV0U Initialization of unsigned division DMULS Signed double-length multiplication DMULU Unsigned double-length multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension MAC Multiply/accumulate, double-length multiply/accumulate operation MUL Double-length multiply operation MULS Signed multiplication MULU Unsigned multiplication NEG Negation NEGC Negation with borrow SUB Binary subtraction SUBC Binary subtraction with borrow SUBV Binary subtraction with underflow 37 Table 2.10 Classification of Instructions (cont) Operation Classification Types Code Function No. of Instructions Logic operations 14 Shift Branch 38 6 10 9 AND Logical AND NOT Bit inversion OR Logical OR TAS Memory test and bit set TST Logical AND and T bit set XOR Exclusive OR ROTL One-bit left rotation ROTR One-bit right rotation ROTCL One-bit left rotation with T bit ROTCR One-bit right rotation with T bit SHAL One-bit arithmetic left shift SHAR One-bit arithmetic right shift SHLL One-bit logical left shift SHLLn n-bit logical left shift SHLR One-bit logical right shift SHLRn n-bit logical right shift BF Conditional branch, conditional branch with delay (Branch when T = 0) BT Conditional branch, conditional branch with delay (Branch when T = 1) BRA Unconditional branch BRAF Unconditional branch BSR Branch to subroutine procedure BSRF Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure RTS Return from subroutine procedure 14 11 Table 2.10 Classification of Instructions (cont) Operation Classification Types Code Function No. of Instructions System control 31 Total: 11 62 CLRT T bit clear CLRMAC MAC register clear LDC Load to control register LDS Load to system register NOP No operation RTE Return from exception processing SETT T bit set SLEEP Shift into power-down mode STC Storing control register data STS Storing system register data TRAPA Trap exception handling 142 Table 2.11 shows the format used in tables 2.12 to 2.17, which list instruction codes, operation, and execution states in order by classification. 39 Table 2.11 Instruction Code Format Item Format Explanation Instruction OP.Sz SRC,DEST OP: Operation code Sz: Size (B: byte, W: word, or L: longword) SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement* 1 Instruction code MSB ↔ LSB mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 . . . 1111: R15 iiii: Immediate data dddd: Displacement Operation →, ← Direction of transfer (xx) Memory operand M/Q/T Flag bits in the SR & Logical AND of each bit | Logical OR of each bit ^ Exclusive OR of each bit ~ Logical NOT of each bit <<n n-bit left shift >>n n-bit right shift Execution cycles — Value when no wait states are inserted*2 T bit — Value of T bit after instruction is executed. An em-dash (—) in the column means no change. Notes: 1. Depending on the operand size, displacement is scaled ×1, ×2, or ×4. For details, see the SH-1/SH-2/SH-DSP Programming Manual. 2. Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory → register) and the register used by the next instruction are the same. 40 Table 2.12 Data Transfer Instructions Execution Cycles T Bit Instruction Instruction Code Operation MOV #imm,Rn 1110nnnniiiiiiii #imm → Sign extension → Rn 1 — MOV.W @(disp,PC),Rn 1001nnnndddddddd (disp × 2 + PC) → Sign extension → Rn 1 — MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp × 4 + PC) → Rn 1 — MOV 0110nnnnmmmm0011 Rm → Rn 1 — MOV.B Rm,@Rn 0010nnnnmmmm0000 Rm → (Rn) 1 — MOV.W Rm,@Rn 0010nnnnmmmm0001 Rm → (Rn) 1 — MOV.L Rm,@Rn 0010nnnnmmmm0010 Rm → (Rn) 1 — MOV.B @Rm,Rn 0110nnnnmmmm0000 (Rm) → Sign extension → Rn 1 — MOV.W @Rm,Rn 0110nnnnmmmm0001 (Rm) → Sign extension → Rn 1 — MOV.L @Rm,Rn 0110nnnnmmmm0010 (Rm) → Rn 1 — MOV.B Rm,@–Rn 0010nnnnmmmm0100 Rn–1 → Rn, Rm → (Rn) 1 — MOV.W Rm,@–Rn 0010nnnnmmmm0101 Rn–2 → Rn, Rm → (Rn) 1 — MOV.L Rm,@–Rn 0010nnnnmmmm0110 Rn–4 → Rn, Rm → (Rn) 1 — MOV.B @Rm+,Rn 0110nnnnmmmm0100 (Rm) → Sign extension → Rn,Rm + 1 → Rm 1 — MOV.W @Rm+,Rn 0110nnnnmmmm0101 (Rm) → Sign extension → Rn,Rm + 2 → Rm 1 — MOV.L @Rm+,Rn 0110nnnnmmmm0110 (Rm) → Rn,Rm + 4 → Rm 1 — MOV.B R0,@(disp,Rn) 10000000nnnndddd R0 → (disp + Rn) 1 — MOV.W R0,@(disp,Rn) 10000001nnnndddd R0 → (disp × 2 + Rn) 1 — MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd Rm → (disp × 4 + Rn) 1 — MOV.B @(disp,Rm),R0 10000100mmmmdddd (disp + Rm) → Sign extension → R0 1 — MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp × 2 + Rm) → Sign extension → R0 1 — MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd (disp × 4 + Rm) → Rn 1 — MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rm → (R0 + Rn) 1 — Rm,Rn 41 Table 2.12 Data Transfer Instructions (cont) Instruction Instruction Code Operation Execution Cycles MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn) 1 — MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm → (R0 + Rn) 1 — MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 (R0 + Rm) → Sign extension → Rn 1 — MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) → Sign extension → Rn 1 — MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) → Rn 1 — MOV.B R0,@(disp,GBR) 11000000dddddddd R0 → (disp + GBR) 1 — MOV.W R0,@(disp,GBR) 11000001dddddddd R0 → (disp × 2 + GBR) 1 — MOV.L R0,@(disp,GBR) 11000010dddddddd R0 → (disp × 4 + GBR) 1 — MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR) → Sign extension → R0 1 — MOV.W @(disp,GBR),R0 11000101dddddddd (disp × 2 + GBR) → Sign extension → R0 1 — MOV.L @(disp,GBR),R0 11000110dddddddd (disp × 4 + GBR) → R0 1 — MOVA @(disp,PC),R0 11000111dddddddd disp × 4 + PC → R0 1 — MOVT Rn 0000nnnn00101001 T → Rn 1 — SWAP.B Rm,Rn 0110nnnnmmmm1000 Rm → Swap the bottom two 1 bytes → Rn — SWAP.W Rm,Rn 0110nnnnmmmm1001 Rm → Swap two consecutive words → Rn 1 — XTRCT 0010nnnnmmmm1101 Rm: Middle 32 bits of Rn → Rn 1 — 42 Rm,Rn T Bit Table 2.13 Arithmetic Operation Instructions Instruction Instruction Code Operation Execution Cycles ADD Rm,Rn 0011nnnnmmmm1100 Rn + Rm → Rn 1 — ADD #imm,Rn 0111nnnniiiiiiii Rn + imm → Rn 1 — ADDC Rm,Rn 0011nnnnmmmm1110 Rn + Rm + T → Rn, Carry → T 1 Carry ADDV Rm,Rn 0011nnnnmmmm1111 Rn + Rm → Rn, Overflow → T 1 Overflow CMP/EQ #imm,R0 10001000iiiiiiii If R0 = imm, 1 → T 1 Comparison result CMP/EQ Rm,Rn 0011nnnnmmmm0000 If Rn = Rm, 1 → T 1 Comparison result CMP/HS Rm,Rn 0011nnnnmmmm0010 If Rn ≥ Rm with unsigned data, 1 → T 1 Comparison result CMP/GE Rm,Rn 0011nnnnmmmm0011 If Rn ≥ Rm with signed data, 1 → T 1 Comparison result CMP/HI Rm,Rn 0011nnnnmmmm0110 If Rn > Rm with unsigned data, 1 → T 1 Comparison result CMP/GT Rm,Rn 0011nnnnmmmm0111 If Rn > Rm with signed data, 1 → T 1 Comparison result CMP/PL Rn 0100nnnn00010101 If Rn > 0, 1 → T 1 Comparison result CMP/PZ Rn 0100nnnn00010001 If Rn ≥ 0, 1 → T 1 Comparison result CMP/STR Rm,Rn 0010nnnnmmmm1100 If Rn and Rm have an equivalent byte, 1→T 1 Comparison result DIV1 Rm,Rn 0011nnnnmmmm0100 Single-step division (Rn/Rm) 1 Calculation result DIV0S Rm,Rn 0010nnnnmmmm0111 MSB of Rn → Q, MSB of Rm → M, M ^ Q → T 1 Calculation result 0000000000011001 0 → M/Q/T 1 0 DIV0U T Bit 43 Table 2.13 Arithmetic Operation Instructions (cont) Execution Cycles T Bit Instruction Instruction Code Operation DMULS.L Rm,Rn 0011nnnnmmmm1101 Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bit 2 to 4* — DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bit 2 to 4* — DT Rn 0100nnnn00010000 Rn – 1 → Rn, when Rn 1 is 0, 1 → T. When Rn is nonzero, 0 → T Comparison result EXTS.B Rm,Rn 0110nnnnmmmm1110 A byte in Rm is signextended → Rn 1 — EXTS.W Rm,Rn 0110nnnnmmmm1111 A word in Rm is signextended → Rn 1 — EXTU.B Rm,Rn 0110nnnnmmmm1100 A byte in Rm is zeroextended → Rn 1 — EXTU.W Rm,Rn 0110nnnnmmmm1101 A word in Rm is zeroextended → Rn 1 — MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of (Rn) × (Rm) + MAC → MAC 32 × 32 → 64 bit 3/(2 to 4)* — MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of (Rn) × (Rm) + MAC → MAC 16 × 16 + 64 → 64 bit 3/(2)* — MUL.L Rm,Rn 0000nnnnmmmm0111 Rn × Rm → MACL, 32 × 32 → 32 bit 2 to 4* — MULS.W Rm,Rn 0010nnnnmmmm1111 Signed operation of Rn × Rm → MAC 16 × 16 → 32 bit 1 to 3* — MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of Rn × Rm → MAC 16 × 16 → 32 bit 1 to 3* — NEG Rm,Rn 0110nnnnmmmm1011 0–Rm → Rn 1 — NEGC Rm,Rn 0110nnnnmmmm1010 0–Rm–T → Rn, Borrow →T 1 Borrow 44 Table 2.13 Arithmetic Operation Instructions (cont) Instruction Instruction Code Operation Execution Cycles SUB Rm,Rn 0011nnnnmmmm1000 Rn–Rm → Rn 1 — SUBC Rm,Rn 0011nnnnmmmm1010 Rn–Rm–T → Rn, Borrow → T 1 Borrow SUBV Rm,Rn 0011nnnnmmmm1011 Rn–Rm → Rn, Underflow → T 1 Overflow T Bit Note: * The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with following instructions.) 45 Table 2.14 Logic Operation Instructions Instruction Instruction Code Operation Execution Cycles AND Rm,Rn 0010nnnnmmmm1001 Rn & Rm → Rn 1 — AND #imm,R0 11001001iiiiiiii R0 & imm → R0 1 — AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm → (R0 + GBR) 3 — NOT Rm,Rn 0110nnnnmmmm0111 ~Rm → Rn 1 — OR Rm,Rn 0010nnnnmmmm1011 Rn | Rm → Rn 1 — OR #imm,R0 11001011iiiiiiii R0 | imm → R0 1 — OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm → (R0 + GBR) 3 — TAS.B @Rn 0100nnnn00011011 If (Rn) is 0, 1 → T; 1 → MSB of (Rn) 4 Test result TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm; if the result is 0, 1 → T 1 Test result TST #imm,R0 11001000iiiiiiii R0 & imm; if the result is 0, 1 → T 1 Test result TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm; if the result is 0, 1 → T 3 Test result XOR Rm,Rn 0010nnnnmmmm1010 Rn ^ Rm → Rn 1 — XOR #imm,R0 11001010iiiiiiii R0 ^ imm → R0 1 — XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm → (R0 + GBR) 3 — 46 T Bit Table 2.15 Shift Instructions Instruction Instruction Code Operation Execution Cycles ROTL Rn 0100nnnn00000100 T ← Rn ← MSB 1 MSB ROTR Rn 0100nnnn00000101 LSB → Rn → T 1 LSB ROTCL Rn 0100nnnn00100100 T ← Rn ← T 1 MSB ROTCR Rn 0100nnnn00100101 T → Rn → T 1 LSB SHAL Rn 0100nnnn00100000 T ← Rn ← 0 1 MSB SHAR Rn 0100nnnn00100001 MSB → Rn → T 1 LSB SHLL Rn 0100nnnn00000000 T ← Rn ← 0 1 MSB SHLR Rn 0100nnnn00000001 0 → Rn → T 1 LSB SHLL2 Rn 0100nnnn00001000 Rn<<2 → Rn 1 — SHLR2 Rn 0100nnnn00001001 Rn>>2 → Rn 1 — SHLL8 Rn 0100nnnn00011000 Rn<<8 → Rn 1 — SHLR8 Rn 0100nnnn00011001 Rn>>8 → Rn 1 — SHLL16 Rn 0100nnnn00101000 Rn<<16 → Rn 1 — SHLR16 Rn 0100nnnn00101001 Rn>>16 → Rn 1 — T Bit 47 Table 2.16 Branch Instructions Exec. Cycles T Bit If T = 0, disp × 2 + PC → PC; if T = 1, nop 3/1* — 10001111dddddddd Delayed branch, if T = 0, disp × 2 + PC → PC; if T = 1, nop 3/1* — label 10001001dddddddd If T = 1, disp × 2 + PC → PC; if T = 0, nop 3/1* — BT/S label 10001101dddddddd Delayed branch, if T = 1, disp × 2 + PC → PC; if T = 0, nop 2/1* — BRA 1010dddddddddddd Delayed branch, disp × 2 + PC → PC 2 — BRAF Rm 0000mmmm00100011 Delayed branch, Rm + PC → PC 2 — BSR 1011dddddddddddd Delayed branch, PC → PR, disp × 2 + PC → PC 2 — BSRF Rm 0000mmmm00000011 Delayed branch, PC → PR, Rm + PC → PC 2 — JMP @Rm 0100mmmm00101011 Delayed branch, Rm → PC 2 — JSR @Rm 0100mmmm00001011 Delayed branch, PC → PR, Rm → PC 2 — 0000000000001011 Delayed branch, PR → PC 2 — Instruction Instruction Code Operation BF label 10001011dddddddd BF/S label BT RTS label label Note: * One state when it does not branch. 48 Table 2.17 System Control Instructions Instruction Instruction Code Operation Exec. Cycles T Bit CLRT 0000000000001000 0→T 1 0 CLRMAC 0000000000101000 0 → MACH, MACL 1 — LDC Rm,SR 0100mmmm00001110 Rm → SR 1 LSB LDC Rm,GBR 0100mmmm00011110 Rm → GBR 1 — LDC Rm,VBR 0100mmmm00101110 Rm → VBR 1 — LDC.L @Rm+,SR 0100mmmm00000111 (Rm) → SR, Rm + 4 → Rm 3 LSB LDC.L @Rm+,GBR 0100mmmm00010111 (Rm) → GBR, Rm + 4 → Rm 3 — LDC.L @Rm+,VBR 0100mmmm00100111 (Rm) → VBR, Rm + 4 → Rm 3 — LDS Rm,MACH 0100mmmm00001010 Rm → MACH 1 — LDS Rm,MACL 0100mmmm00011010 Rm → MACL 1 — LDS Rm,PR 0100mmmm00101010 Rm → PR 1 — LDS.L @Rm+,MACH 0100mmmm00000110 (Rm) → MACH, Rm + 4 → Rm 1 — LDS.L @Rm+,MACL 0100mmmm00010110 (Rm) → MACL, Rm + 4 → Rm 1 — LDS.L @Rm+,PR 0100mmmm00100110 (Rm) → PR, Rm + 4 → Rm 1 — NOP 0000000000001001 No operation 1 — RTE 0000000000101011 Delayed branch, stack area → PC/SR 4 — SETT 0000000000011000 1→T 1 1 SLEEP 0000000000011011 Sleep 3* — STC SR,Rn 0000nnnn00000010 SR → Rn 1 — STC GBR,Rn 0000nnnn00010010 GBR → Rn 1 — STC VBR,Rn 0000nnnn00100010 VBR → Rn 1 — STC.L SR,@–Rn 0100nnnn00000011 Rn–4 → Rn, SR → (Rn) 2 — STC.L GBR,@–Rn 0100nnnn00010011 Rn–4 → Rn, GBR → (Rn) 2 — STC.L VBR,@–Rn 0100nnnn00100011 Rn–4 → Rn, BR → (Rn) 2 — STS MACH,Rn 0000nnnn00001010 MACH → Rn 1 — STS MACL,Rn 0000nnnn00011010 MACL → Rn 1 — STS PR,Rn 0000nnnn00101010 PR → Rn 1 — 49 Table 2.17 System Control Instructions (cont) Instruction Instruction Code Operation Exec. Cycles T Bit STS.L MACH,@–Rn 0100nnnn00000010 Rn–4 → Rn, MACH → (Rn) 1 — STS.L MACL,@–Rn 0100nnnn00010010 Rn–4 → Rn, MACL → (Rn) 1 — STS.L PR,@–Rn 0100nnnn00100010 Rn–4 → Rn, PR → (Rn) 1 — TRAPA #imm 11000011iiiiiiii PC/SR → stack area, 8 — (imm × 4 + VBR) → PC Note: * The number of execution cycles before the chip enters sleep mode: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory → register) and the register used by the next instruction are the same. 2.5 Processing States 2.5.1 State Transitions The CPU has five processing states: reset, exception processing, bus release, program execution and power-down. Figure 2.6 shows the transitions between the states. 50 From any state when RES = 0 and HSTBY = 1 RES = 0 HSTBY = 1 Power-on reset state RES = 1 When an interrupt source or DMA address error occurs Exception processing state Bus request cleared NMI interrupt source occurs Bus request generated Exception processing source occurs Bus release state Bus request generated Bus request generated Exception processing ends Bus request cleared Bus request cleared Program execution state SBY bit cleared for SLEEP instruction SBY bit set for SLEEP instruction Sleep mode Software standby mode Hardware standby mode Power-down state From any state when RES = 0 and HSTBY = 1 Figure 2.6 Transitions between Processing States 51 Reset State: The CPU resets in the reset state. When the RES pin level goes low, a power-on reset results. When the RES pin is high and MRES is low, a manual reset will occur. Exception Processing State: The exception processing state is a transient state that occurs when exception processing sources such as resets or interrupts alter the CPU’s processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception processing vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. Program Execution State: In the program execution state, the CPU sequentially executes the program. Power-Down State: In the power-down state, the CPU operation halts and power consumption declines. The SLEEP instruction places the CPU in the power-down state. This state has two modes: sleep mode and standby mode. In addition, driving the HSTBY pin low while the RES pin is low causes a transition to hardware standby mode. Bus Release State: In the bus release state, the CPU releases access rights to the bus to the device that has requested them. 52 Section 3 Operating Modes 3.1 Operating Mode Selection The SH7052F/SH7053F/SH7054F has five operating modes that are selected by pins MD2 to MD0 and FWE. The mode setting pins should not be changed during operation of the SH7052F/SH7053F/SH7054F, and only the setting combinations shown in Table 3.1 should be used. The PVCC1 power supply voltage must be within the range shown in table 3.1. Table 3.1 Operating Mode Selection Pin Settings Operating Mode No. FWE MD2 MD1 MD0 Mode Name Mode 0 0 1 0 0 Mode 1 0 1 0 1 MCU expanded mode Mode 2 0 1 1 0 Mode 3 0 1 1 1 Mode 4 1 1 0 0 Mode 5 1 1 0 1 Mode 6 1 1 1 0 Mode 7 1 1 1 1 — 0/1 0 1 1 On-Chip ROM Area 0 Bus Width PVCC1 Voltage Disabled 8 bits 3.3 V ±0.3 V 16 bits Enabled Set by BCR1 MCU single-chip mode Enabled — 5.0 V ±0.5 V Boot mode Enabled Set by BCR1 3.3 V ±0.3 V — 5.0 V ±0.5 V Set by BCR1 3.3 V ±0.3 V — 5.0 V ±0.5 V — 3.3 V ±0.3 V User program mode Enabled Programmer mode — There are two MCU operating modes: MCU single-chip mode and MCU expanded mode. Modes in which the flash memory can be programmed are boot mode and user program mode (the two on-board programming modes) and programmer mode in which programming is performed with an EPROM programmer (a type which supports programming of this device). For details, see section 20, ROM (SH7052F/SH7053F) and section 21, ROM (SH7054F). Caution: In the SH7052F/SH7053F/SH7054F expanded modes (modes 0, 1, and 2), the guaranteed operating range of bus port power supply (port power supply 1: PVCC1) in the MCU expanded modes is 3.3 V ±0.3 V. Since operation is not guaranteed in the MCU expanded modes on a voltage outside this range, a voltage within this range must be used. 53 54 Section 4 Clock Pulse Generator (CPG) 4.1 Overview The clock pulse generator (CPG) supplies clock pulses inside the SH7052F/SH7053F/SH7054F chip and to external devices. The SH7052F/SH7053F/SH7054F CPG consists of an oscillator circuit and a PLL multiplier circuit. There are two methods of generating a clock with the CPG: by connecting a crystal resonator, or by inputting an external clock. The oscillator circuit oscillates at the same frequency as the input clock. A chip operating frequency of 4 times the oscillator frequency is generated by the PLL multiplier circuit. The CPG is halted in software standby mode and hardware standby mode. 4.1.1 Block Diagram A block diagram of the clock pulse generator is shown in figure 4.1. CPG EXTAL Oscillator circuit XTAL PLLVcc PLLVss PLL multiplier circuit PLLCAP CK (system clock) f×4 Internal clock Figure 4.1 Block Diagram of Clock Pulse Generator 55 4.1.2 Pin Configuration The pins relating to the clock pulse generator are shown in table 4.1. Table 4.1 CPG Pins Pin Name Abbreviation I/O Description External clock EXTAL Input Crystal resonator or external clock input Crystal XTAL Input Crystal resonator connection System clock CK Output System clock output PLL power supply PLLVCC Input PLL multiplier circuit power supply PLL ground PLLVSS Input PLL multiplier circuit ground PLL capacitance PLLCAP Input PLL multiplier circuit oscillation external capacitance pin 4.2 Frequency Ranges The input frequency and operating frequency ranges are shown in table 4.2. Table 4.2 Input Frequency and Operating Frequency Input Frequency Range (MHz) PLL Multiplication Factor Operating Frequency Range (MHz) 5 to 10 ×4 20 to 40 Note: Crystal resonator and external clock input For the chip operating frequency, a frequency of 4 times the input frequency (EXTAL pin) is generated as the internal clock (φ) by the on-chip PLL circuit. The system clock (CK pin) output frequency is the same as that of the internal clock (φ). Some on-chip peripheral modules operate on a peripheral clock (Pφ) obtained by dividing the internal clock (φ) by 2. Figure 4.2 shows the relationship between the various clocks. As regards the system clock, since the input clock is multiplied by the PLL multiplier circuit, the phases of both clocks are not determined uniformly. 56 Input clock (EXTAL pin) System clock (CK pin) Internal clock (φ) Peripheral clock (Pφ) Figure 4.2 Input Clock and System Clock 4.3 Clock Source Clock pulses can be supplied from a connected crystal resonator or an external clock. 4.3.1 Connecting a Crystal Oscillator Circuit Configuration: Figure 4.3 shows an example of connecting a crystal resonator. Use the damping resistance (Rd) shown in table 4.3. An AT-cut parallel-resonance type crystal resonator should be used. Load capacitors (CL1, CL2) must be connected as shown in the figure. The clock pulses generated by the crystal resonator and internal oscillator are sent to the PLL multiplier circuit, where a multiplied frequency is selected and supplied inside the SH7052F/SH7053F/SH7054F chip and to external devices. The crystal oscillator manufacturer should be consulted concerning the compatibility between the crystal oscillator and the chip. CL2 EXTAL CL1 XTAL Rd CL1 = CL2 = 18 to 22 pF (recommended value) Figure 4.3 Connection of Crystal Oscillator (Example) 57 Table 4.3 Damping Resistance Values (Recommended Values) Frequency (MHz) Parameter 5 10 Rd (Ω) 500 0 Crystal Oscillator: Figure 4.4 shows an equivalent circuit of the crystal oscillator. Use a crystal oscillator with the characteristics listed in table 4.4. L CL Rs XTAL EXTAL C0 Figure 4.4 Crystal Oscillator Equivalent Circuit Table 4.4 Crystal Oscillator Parameters (Recommended Values) Frequency (MHz) Parameter 5 10 Rs max (Ω) 100 50 C0 max (pF) 7 7 The crystal oscillator manufacturer should be consulted concerning the compatibility between the crystal oscillator and the chip. 4.3.2 External Clock Input Method An example of external clock input connection is shown in figure 4.5. When the XTAL pin is placed in the open state, the parasitic capacitance should be 10 pF or less. Even when an external clock is input, provide for a wait of at least the oscillation settling time when powering on or exiting standby mode in order to secure the PLL settling time. 58 Open External clock input XTAL EXTAL Figure 4.5 External Clock Input Method (Example) 4.4 Usage Notes Notes on Board Design: When connecting a crystal oscillator, observe the following precautions: • To prevent induction from interfering with correct oscillation, do not route any signal lines near the oscillator circuitry (figure 4.6). • When designing the board, place the crystal oscillator and its load capacitors as close as possible to the XTAL and EXTAL pins. Figure 4.6 shows the precautions regarding oscillator circuit system board design. Crossing of signal lines prohibited CL1 XTAL CL2 EXTAL Figure 4.6 Precautions for Oscillator Circuit System Board Design PLL Oscillation Power Supply: Place oscillation capacitor C1 and resistor R1 close to the PLL CAP pin, and ensure that no other signal lines cross this line. Supply the C1 ground from PLLV SS . Separate PLLVCC and PLLVSS from the other VCC and VSS lines at the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins. 59 R1 C1 PLLCAP Rp PLLVCC CPB PLLVSS VCC CB VSS Recommended values CPB, CB: 0.1 µF Rp: 200 Ω R1: 3 kΩ C1: 470 pF (laminated ceramic) Figure 4.7 Points for Caution in PLL Power Supply Connection EXTAL Vss XTAL Vcc PLLVcc PLLCAP PLLVss Figure 4.8 Actual Example of Board Design 60 Section 5 Exception Processing 5.1 Overview 5.1.1 Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 5.1. When several exception processing sources occur at once, they are processed according to the priority shown. Table 5.1 Types of Exception Processing and Priority Order Exception Source Priority Reset Power-on reset High Manual reset Address error CPU address error Interrupt NMI DMAC address error User break IRQ On-chip peripheral modules: • Direct memory access controller (DMAC) • Advanced timer unit-II (ATU-II) • Compare match timer 0 (CMT0) • A/D converter channel 0 (A/D0) • Compare match timer (CMT1) • A/D converter channel 1 (A/D1) • Serial communication interface (SCI) • Hitachi controller area network (HCAN) • Watchdog timer (WDT) Instructions Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Illegal slot instructions (undefined code placed directly after a delay branch Low instruction* 1 or instructions that rewrite the PC*2) Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF. 61 5.1.2 Exception Processing Operations The exception processing sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2 Timing of Exception Source Detection and Start of Exception Processing Exception Source Timing of Source Detection and Start of Processing Reset Power-on reset Starts when the RES pin changes from low to high or when the WDT overflows. Manual reset Starts when the WDT overflows. Address error Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Interrupts Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Instructions Trap instruction Starts from the execution of a TRAPA instruction. General illegal instructions Starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). Illegal slot instructions Starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the PC. When exception processing starts, the CPU operates as follows: 1. Exception processing triggered by reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception processing vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets). See section 5.1.3, Exception Processing Vector Table, for more information. H'00000000 is then written to the vector base register (VBR) and H'F (1111) is written to the interrupt mask bits (I3 to I0) of the status register (SR). The program begins running from the PC address fetched from the exception processing vector table. 2. Exception processing triggered by address errors, interrupts and instructions: SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the interrupt priority level is written to the SR’s interrupt mask bits (I3 to I0). For address error and instruction exception processing, the I3 to I0 bits are not affected. The start address is then fetched from the exception processing vector table and the program begins running from that address. 62 5.1.3 Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. During exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table, which is indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Exception Processing Vector Table Vector Numbers Vector Table Address Offset PC 0 H'00000000 to H'00000003 SP 1 H'00000004 to H'00000007 PC 2 H'00000008 to H'0000000B SP 3 H'0000000C to H'0000000F General illegal instruction 4 H'00000010 to H'00000013 (Reserved by system) 5 H'00000014 to H'00000017 Slot illegal instruction 6 H'00000018 to H'0000001B (Reserved by system) 7 H'0000001C to H'0000001F 8 H'00000020 to H'00000023 CPU address error 9 H'00000024 to H'00000027 DMAC address error 10 H'00000028 to H'0000002B NMI 11 H'0000002C to H'0000002F User break 12 H'00000030 to H'00000033 13 H'00000034 to H'00000037 Exception Sources Power-on reset Manual reset Interrupts (Reserved by system) : 31 : H'0000007C to H'0000007F 63 Table 5.3 Exception Processing Vector Table (cont) Exception Sources Vector Numbers Vector Table Address Offset Trap instruction (user vector) 32 H'00000080 to H'00000083 : : 63 H'000000FC to H'000000FF IRQ0 64 H'00000100 to H'00000103 IRQ1 65 H'00000104 to H'00000107 IRQ2 66 H'00000108 to H'0000010B IRQ3 67 H'0000010C to H'0000010F Reserved by system 68 to 71 H'00000110 to H'0000011F On-chip peripheral module* 72 H'00000120 to H'00000124 Interrupts : 255 : H'000003FC to H'000003FF Note: * The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in table 6.3, Interrupt Exception Processing Vectors and Priorities, in section 6, Interrupt Controller. Table 5.4 Calculating Exception Processing Vector Table Addresses Exception Source Vector Table Address Calculation Resets Vector table address = (vector table address offset) = (vector number) × 4 Address errors, interrupts, instructions Vector table address = VBR + (vector table address offset) = VBR + (vector number) × 4 Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 5.3. 3. Vector number: See table 5.3. 64 5.2 Resets 5.2.1 Types of Reset A reset is the highest-priority exception processing source. There are two kinds of reset, power-on and manual. As shown in table 5.5, the CPU state is initialized in both a power-on reset and a manual reset. On-chip peripheral module registers are also initialized by a power-on reset, but not by a manual reset. Table 5.5 Exception Source Detection and Exception Processing Start Timing Conditions for Transition to Reset State Internal States CPU/MULT/ FPU/INTC On-Chip Peripheral Modules PFC, IO Port Type RES WDT Overflow Power-on reset Low — Initialized Initialized Initialized High Power-on reset Initialized Initialized Not initialized High Manual reset Initialized Not initialized Not initialized Manual reset 5.2.2 Power-On Reset Power-On Reset by Means of RES Pin: When the RES pin is driven low, the chip enters the power-on reset state. To reliably reset the chip, the RES pin should be kept at the low level for at least the duration of the oscillation settling time at power-on or when in standby mode (when the clock is halted), or at least 20 tcyc when the clock is running. In the power-on reset state, the CPU’s internal state and all the on-chip peripheral module registers are initialized. See Appendix B, Pin States, for the state of individual pins in the power-on reset state. In the power-on reset state, power-on reset exception processing starts when the RES pin is first driven low for a set period of time and then returned to high. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (1111). 4. The values fetched from the exception processing vector table are set in the PC and SP, and the program begins executing. Be certain to always perform power-on reset processing when turning the system power on. 65 Power-On Reset Initiated by WDT: When a setting is made for a power-on reset to be generated in the WDT’s watchdog timer mode, and the WDT’s TCNT overflows, the chip enters the poweron reset state. The pin function controller (PFC) registers and I/O port registers are not initialized by the reset signal generated by the WDT (these registers are only initialized by a power-on reset from offchip). If reset caused by the input signal at the RES pin and a reset caused by WDT overflow occur simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0. When WDT-initiated power-on reset processing is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of the status register (SR) are set to H'F (1111). 4. The values fetched from the exception processing vector table are set in the PC and SP, and the program begins executing. 5.2.3 Manual Reset When a setting is made for a manual reset to be generated in the WDT’s watchdog timer mode, and the WDT’s TCNT overflows, the chip enters the power-on reset state. When WDT-initiated manual reset processing is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of the status register (SR) are set to H'F (1111). 4. The values fetched from the exception processing vector table are set in the PC and SP, and the program begins executing. In a manual reset the bus cycle is retained, but if a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception processing will be deferred until the CPU acquires the bus. However, if the interval from generation of the manual reset until the end of the bus cycle is equal to or longer than the internal manual reset interval of 512 cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception processing is not executed. 66 5.3 Address Errors 5.3.1 Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Instruction fetch Data read/write Bus Master Bus Cycle Description Address Errors CPU Instruction fetched from even address None (normal) Instruction fetched from odd address Address error occurs Instruction fetched from other than on-chip peripheral module space* None (normal) Instruction fetched from on-chip peripheral module space* Address error occurs Instruction fetched from external memory space when in single chip mode Address error occurs Word data accessed from even address None (normal) Word data accessed from odd address Address error occurs Longword data accessed from a longword boundary None (normal) Longword data accessed from other than a long-word boundary Address error occurs Byte or word data accessed in on-chip peripheral module space* None (normal) Longword data accessed in 16-bit on-chip peripheral module space* None (normal) Longword data accessed in 8-bit on-chip peripheral module space* Address error occurs External memory space accessed when in single chip mode Address error occurs CPU or DMAC Note: * See section 8, Bus State Controller, for details of the on-chip peripheral module space. 67 5.3.2 Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then finishes, address error exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the address error that occurred and the program starts executing from that address. The jump that occurs is not a delayed branch. 5.4 Interrupts 5.4.1 Interrupt Sources Table 5.7 shows the sources that start up interrupt exception processing. These are divided into NMI, user breaks, IRQ and on-chip peripheral modules. Table 5.7 Interrupt Sources Type Request Source Number of Sources NMI NMI pin (external input) 1 User break User break controller 1 IRQ IRQ0 to IRQ3 (external input) 4 On-chip peripheral module Direct memory access controller (DMAC) 4 Advanced timer unit-II (ATU-II) 75 Compare match timer (CMT) 2 A/D converter (A/D) 2 Serial communication interface (SCI) 20 Watchdog timer (WDT) 1 Hitachi controller area network (HCAN) 4 Each interrupt source is allocated a different vector number and vector table offset. See table 6.3, Interrupt Exception Processing Vectors and Priorities, in section 6, Interrupt Controller, for more information on vector numbers and vector table address offsets. 68 5.4.2 Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts up processing according to the results. The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The user break interrupt and H-UDI interrupt priority level is 15. IRQ interrupts and on-chip peripheral module interrupt priority levels can be set freely using the INTC’s interrupt priority registers A, C to L (IPRA, IPRC to IPRL) as shown in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 6.3.1, Interrupt Priority Registers A, C to L (IPRA, IPRC to IPRL), for details of the interrupt priority registers. Table 5.8 Interrupt Priority Order Type Priority Level Comment NMI 16 Fixed priority level. Cannot be masked. User break 15 Fixed priority level. IRQ 0 to 15 Set with interrupt priority level setting registers A and C through L (IPRA, IPRC to IPRL). On-chip peripheral module 0 to 15 Set with interrupt priority level setting registers A and C through L (IPRA, IPRC to IPRL). 5.4.3 Interrupt Exception Processing When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR). When an interrupt is accepted, exception processing begins. In interrupt exception processing, the CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the exception processing vector table for the accepted interrupt, that address is jumped to and execution begins. See section 6.4, Interrupt Operation, for further details. 69 5.5 Exceptions Triggered by Instructions 5.5.1 Types of Exceptions Triggered by Instructions Exception processing can be triggered by trap instructions, general illegal instructions, and illegal slot instructions, as shown in table 5.9. Table 5.9 Types of Exceptions Triggered by Instructions Type Source Instruction Trap instructions TRAPA Illegal slot instructions Undefined code placed immediately after a delayed branch instruction (delay slot) and instructions that rewrite the PC General illegal instructions 5.5.2 Comment Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF Undefined code anywhere besides in a delay slot Trap Instructions When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the vector number specified in the TRAPA instruction. That address is jumped to and the program starts executing. The jump that occurs is not a delayed branch. 70 5.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. When the instruction placed in the delay slot is undefined code, illegal slot exception processing starts up when that undefined code is decoded. Illegal slot exception processing also starts up when an instruction that rewrites the program counter (PC) is placed in a delay slot. The processing starts when the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the exception that occurred. That address is jumped to and the program starts executing. The jump that occurs is not a delayed branch. 5.5.4 General Illegal Instructions When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The CPU handles general illegal instructions in the same way as illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value stored is the start address of the undefined code. 71 5.6 When Exception Sources Are Not Accepted When an address error or interrupt is generated after a delayed branch instruction or interruptdisabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.10. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 5.10 Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-Disabled Instruction Exception Source Point of Occurrence Bus Error Interrupt FPU Exception Immediately after a delayed branch instruction* 1 Not accepted Not accepted Not accepted Immediately after an interrupt-disabled instruction* 2 Not accepted* 3 Not accepted Accepted Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF 2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L 3. In the SH-2 a bus error is accepted. 72 5.7 Stack Status after Exception Processing Ends The status of the stack after exception processing ends is as shown in table 5.11. Table 5.11 Stack Status After Exception Processing Ends Exception Type Stack Status Address error SP Address of instruction 32 bits after executed instruction SR 32 bits Address of instruction after TRAPA instruction 32 bits SR 32 bits Start address of illegal instruction 32 bits SR 32 bits Trap instruction SP General illegal instruction SP Interrupt SP Address of instruction after executed instruction 32 bits SR Illegal slot instruction SP 32 bits Jump destination address of delay branch instruction 32 bits SR 32 bits 73 5.8 Usage Notes 5.8.1 Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing When the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start up as soon as the first exception processing is ended. Address errors will then also occur in the stacking for this address error exception processing. To ensure that address error exception processing does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the address error exception service routine and enables error processing. When an address error occurs during exception processing stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the SP is decremented by 4 for both, so the value of SP will not be a multiple of four after the stacking either. The address value output during stacking is the SP value, so the address where the error occurred is itself output. This means the write data stacked will be undefined. 74 Section 6 Interrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be used by the user to order the priorities in which the interrupt requests are processed. 6.1.1 Features The INTC has the following features: • 16 levels of interrupt priority By setting the twelve interrupt-priority level registers, the priorities of IRQ interrupts and onchip peripheral module interrupts can be set in 16 levels for different request sources. • NMI noise canceler function NMI input level bits indicate the NMI pin status. By reading these bits with the interrupt exception service routine, the pin status can be confirmed, enabling it to be used as a noise canceler. 75 6.1.2 Block Diagram Figure 6.1 is a block diagram of the INTC. IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 Input control CPU/ DMAC request judgment Priority ranking judgment Comparator Interrupt request SR UBC DMAC ATU-II CMT A/D SCI WDT HCAN (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) I3 I2 I1 I0 CPU ICR IPR ISR Bus interface Module bus INTC UBC: DMAC: ATU-II: CMT: A/D: SCI: User break controller Direct memory access controller Advanced timer unit Compare match timer A/D converter Serial communication interface Watchdog timer Hitachi controller area network Interrupt control register IRQ status register Interrupt priority level setting registers A, C to L SR: Status register WDT: HCAN: ICR: ISR: IPRA, IPRC to IPRL: Figure 6.1 INTC Block Diagram 76 Internal bus IPRA, IPRC to IPRL 6.1.3 Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Abbreviation I/O Function Non-maskable interrupt input pin NMI I Input of non-maskable interrupt request signal Interrupt request input pins IRQ0 to IRQ3 I Input of maskable interrupt request signals 6.1.4 Register Configuration The INTC has the 14 registers shown in table 6.2. These registers set the priority of the interrupts and control external interrupt input signal detection. Table 6.2 Register Configuration Name Abbr. R/W Initial Value Address Access Sizes Interrupt priority register A IPRA R/W H'0000 H'FFFF ED00 8, 16, 32 Interrupt priority register C IPRC R/W H'0000 H'FFFF ED04 8, 16, 32 Interrupt priority register D IPRD R/W H'0000 H'FFFF ED06 8, 16, 32 Interrupt priority register E IPRE R/W H'0000 H'FFFF ED08 8, 16, 32 Interrupt priority register F IPRF R/W H'0000 H'FFFF ED0A 8, 16, 32 Interrupt priority register G IPRG R/W H'0000 H'FFFF ED0C 8, 16, 32 Interrupt priority register H IPRH R/W H'0000 H'FFFF ED0E 8, 16, 32 Interrupt priority register I IPRI R/W H'0000 H'FFFF ED10 8, 16, 32 Interrupt priority register J IPRJ R/W H'0000 H'FFFF ED12 8, 16, 32 Interrupt priority register K IPRK R/W H'0000 H'FFFF ED14 8, 16, 32 Interrupt priority register L IPRL R/W H'0000 H'FFFF ED16 8, 16, 32 ICR R/W *1 H'FFFF ED18 8, 16, 32 ISR 2 R(W)* H'0000 H'FFFF ED1A 8, 16, 32 Interrupt control register IRQ status register Notes: Three access cycles are required for byte access and word access, and six cycles for longword access. 1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000. 2. Only 0 can be written, in order to clear flags. 77 6.2 Interrupt Sources There are five types of interrupt sources: NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. 6.2.1 NMI Interrupts The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. 6.2.2 User Break Interrupt A user break interrupt has a priority of level 15, and occurs when the break condition set in the user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are held until accepted. User break interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. For more information about the user break interrupt, see section 7, User Break Controller. 6.2.3 IRQ Interrupts IRQ interrupts are requested by input from pins IRQ0 to IRQ3. Set the IRQ sense select bits (IRQ0S to IRQ3S) of the interrupt control register (ICR) to select low level detection or falling edge detection for each pin. The priority level can be set from 0 to 15 for each pin using interrupt priority registers A and B (IPRA to IPRB). When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC during the period the IRQ pin is low. Interrupt request signals are not sent to the INTC when the IRQ pin becomes high. Interrupt request levels can be confirmed by reading the IRQ flags (IRQ0F to IRQ3F) of the IRQ status register (ISR). When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the INTC upon detecting a change on the IRQ pin from high to low level. IRQ interrupt request detection results are maintained until the interrupt request is accepted. Confirmation that IRQ interrupt requests have been detected is possible by reading the IRQ flags (IRQ0F to IRQ3F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request detection results can be withdrawn. In IRQ interrupt exception processing, the interrupt mask bits (I3 to I0) of the status register (SR) are set to the priority level value of the accepted IRQ interrupt. 78 6.2.4 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules: • • • • • • • Direct memory access controller (DMAC) Advanced timer unit (ATU-II) Compare match timer (CMT) A/D converter (A/D) Serial communication interface (SCI) Watchdog timer (WDT) Hitachi controller area network (HCAN) A different interrupt vector is assigned to each interrupt source, so the exception service routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers C to L (IPRC to IPRL). On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.2.5 Interrupt Exception Vectors and Priority Rankings Table 6.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from vector numbers and address offsets. In interrupt exception processing, the exception service routine start address is fetched from the vector table indicated by the vector table address. See table 5.4, Calculating Exception Processing Vector Table Addresses, in section 5, Exception Processing. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A and C to L (IPRA, IPRC to IPRL). The ranking of interrupt sources for IPRC to IPRL, however, must be the order listed under Priority within IPR Setting Range in table 6.3 and cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 6.3. 79 Table 6.3 Interrupt Exception Processing Vectors and Priorities Interrupt Vector Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Setting Default Range Priority Interrupt Source Vector Table Vector Address No. Offset NMI 11 H'0000002C to 16 H'0000002F — — UBC 12 H'00000030 to 15 H'00000033 — — IRQ0 64 H'00000100 to 0 to 15 (0) IPRA H'00000103 (15 to 12) — IRQ1 65 H'00000104 to 0 to 15 (0) IPRA H'00000107 (11 to 8) — IRQ2 66 H'00000108 to 0 to 15 (0) IPRA H'0000010B (7 to 4) — IRQ3 67 H'0000010C to 0 to 15 (0) IPRA H'0000010F (3 to 0) — High DMAC0 DEI0 72 H'00000120 to 0 to 15 (0) IPRC H'00000123 (15 to 12) ↑ 1 DMAC1 DEI1 74 H'00000128 to 0 to 15 (0) H'0000012B ↓ 2 DMAC2 DEI2 76 H'00000130 to 0 to 15 (0) IPRC H'00000133 (11 to 8) ↑ 1 DMAC3 DEI3 78 H'00000138 to 0 to 15 (0) H'0000013B ↓ 2 ATU0 ATU01 ITV1 ITV2A ITV2B 80 H'00000140 to 0 to 15 (0) IPRC H'00000143 (7 to 4) ATU02 ICI0A 84 H'00000150 to 0 to 15 (0) IPRC H'00000153 (3 to 0) ↑ 1 ICI0B 86 H'00000158 to H'0000015B ↓ 2 ICI0C 88 H'00000160 to 0 to 15 (0) IPRD H'00000163 (15 to 12) ↑ 1 ICI0D 90 H'00000168 to H'0000016B ↓ 2 OVI0 92 H'00000170 to 0 to 15 (0) IPRD H'00000173 (11 to 8) ATU03 ATU04 80 Low Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address No. Offset Interrupt Source ATU1 ATU11 ATU12 ATU13 Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Setting Default Range Priority ↑ IMI1A/ CMI1 96 H'00000180 to 0 to 15 (0) IPRD H'00000183 (7 to 4) IMI1B 97 H'00000184 to H'00000187 2 IMI1C 98 H'00000188 to H'0000018B 3 IMI1D 99 H'0000018C to H'0000018F ↓ 4 IMI1E 100 H'00000190 to 0 to 15 (0) IPRD H'00000193 (3 to 0) ↑ 1 IMI1F 101 H'00000194 to H'00000197 2 IMI1G 102 H'00000198 to H'0000019B 3 IMI1H 103 H'0000019C to H'0000019F OVI1A/ 104 OVI1B H'000001A0 to 0 to 15 (0) IPRE H'000001A3 (15 to 12) ↓ 1 High 4 Low 81 Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address No. Offset Interrupt Source ATU2 ATU21 ATU22 ATU3 Corresponding IPR (Bits) Priority within IPR Setting Default Range Priority ↑ IMI2A/ CMI2A 108 H'000001B0 to 0 to 15 (0) IPRE H'000001B3 (11 to 8) 1 IMI2B/ CMI2B 109 H'000001B4 to H'000001B7 2 IMI2C/ CMI2C 110 H'000001B8 to H'000001BB 3 IMI2D/ CMI2D 111 H'000001BC to H'000001BF ↓ 4 IMI2E/ CMI2E 112 H'000001C0 to 0 to 15 (0) IPRE H'000001C3 (7 to 4) ↑ 1 IMI2F/ CMI2F 113 H'000001C4 to H'000001C7 2 IMI2G/ CMI2G 114 H'000001C8 to H'000001CB 3 IMI2H/ CMI2H 115 H'000001CC to H'000001CF ↓ 4 ↑ 1 ATU23 OVI2A/ 116 OVI2B H'000001D0 to 0 to 15 (0) IPRE H'000001D3 (3 to 0) ATU31 IMI3A 120 H'000001E0 to 0 to 15 (0) IPRF H'000001E3 (15 to 12) IMI3B 121 H'000001E4 to H'000001E7 2 IMI3C 122 H'000001E8 to H'000001EB 3 IMI3D 123 H'000001EC to H'000001EF OVI3 124 H'000001F0 to 0 to 15 (0) IPRF H'000001F3 (11 to 8) ATU32 82 Interrupt Priority (Initial Value) ↓ High 4 Low Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address No. Offset Interrupt Source ATU4 ATU5 ATU41 Corresponding IPR (Bits) Priority within IPR Setting Default Range Priority ↑ IMI4A 128 H'00000200 to 0 to 15 (0) IPRF H'00000203 (7 to 4) IMI4B 129 H'00000204 to H'00000207 2 IMI4C 130 H'00000208 to H'0000020B 3 IMI4D 131 H'0000020C to H'0000020F ATU42 OVI4 132 H'00000210 to 0 to 15 (0) IPRF H'00000213 (3 to 0) ATU51 IMI5A 136 H'00000220 to 0 to 15 (0) IPRG H'00000223 (15 to 12) IMI5B 137 H'00000224 to H'00000227 2 IMI5C 138 H'00000228 to H'0000022B 3 IMI5D 139 H'0000022C to H'0000022F OVI5 140 H'00000230 to 0 to 15 (0) IPRG H'00000233 (11 to 8) CMI6A 144 H'00000240 to 0 to 15 (0) IPRG H'00000243 (7 to 4) CMI6B 145 H'00000244 to H'00000247 2 CMI6C 146 H'00000248 to H'0000024B 3 CMI6D 147 H'0000024C to H'0000024F ATU52 ATU6 Interrupt Priority (Initial Value) 1 ↓ 4 ↑ 1 ↓ 4 ↑ 1 ↓ 4 High Low 83 Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address No. Offset Interrupt Source ATU7 ATU8 ATU81 ATU82 ATU83 84 Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Setting Default Range Priority ↑ CMI7A 148 H'00000250 to 0 to 15 (0) IPRG H'00000253 (3 to 0) CMI7B 149 H'00000254 to H'00000257 2 CMI7C 150 H'00000258 to H'0000025B 3 CMI7D 151 H'0000025C to H'0000025F ↓ 4 OSI8A 152 H'00000260 to 0 to 15 (0) IPRH H'00000263 (15 to 12) ↑ 1 OSI8B 153 H'00000264 to H'00000267 2 OSI8C 154 H'00000268 to H'0000026B 3 OSI8D 155 H'0000026C to H'0000026F ↓ 4 OSI8E 156 H'00000270 to 0 to 15 (0) IPRH H'00000273 (11 to 8) ↑ 1 OSI8F 157 H'00000274 to H'00000277 2 OSI8G 158 H'00000278 to H'0000027B 3 OSI8H 159 H'0000027C to H'0000027F ↓ 4 OSI8I 160 H'00000280 to 0 to 15 (0) IPRH H'00000283 (7 to 4) ↑ 1 OSI8J 161 H'00000284 to H'00000287 2 OSI8K 162 H'00000288 to H'0000028B 3 OSI8L 163 H'0000028C to H'0000028F ↓ 1 4 High Low Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address No. Offset Interrupt Source ATU8 ATU9 ATU84 ATU91 ATU92 Corresponding IPR (Bits) Priority within IPR Setting Default Range Priority ↑ OSI8M 164 H'00000290 to 0 to 15 (0) IPRH H'00000293 (3 to 0) OSI8N 165 H'00000294 to H'00000297 2 OSI8O 166 H'00000298 to H'0000029B 3 OSI8P 167 H'0000029C to H'0000029F ↓ 4 CMI9A 168 H'000002A0 to 0 to 15 (0) IPRI H'000002A3 (15 to 12) ↑ 1 CMI9B 169 H'000002A4 to H'000002A7 2 CMI9C 170 H'000002A8 to H'000002AB 3 CMI9D 171 H'000002AC to H'000002AF ↓ 4 CMI9E 172 H'000002B0 to 0 to 15 (0) IPRI H'000002B3 (11 to 8) ↑ 1 CMI9F 174 H'000002B8 to H'000002BB ↓ 2 H'000002C0 to 0 to 15 (0) IPRI H'000002C3 (7 to 4) ↑ 1 H'000002C8 to H'000002CB ↓ 2 ↑ 1 ATU10 ATU101 CMI10A 176 CMI10B 178 ATU102 ICI10A/ 180 CMI10G ATU11 Interrupt Priority (Initial Value) H'000002D0 to 0 to 15(0) H'000002D3 1 High IPRI (3 to 0) IMI11A 184 H'000002E0 to 0 to 15 (0) IPRJ H'000002E3 (15 to 12) IMI11B 186 H'000002E8 to H'000002EB OVI11 187 H'000002EC to H'000002EF 2 ↓ 3 Low 85 Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address No. Offset Interrupt Source Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Setting Default Range Priority CMT0 CMTI0 188 H'000002F0 to 0 to 15 (0) I PRJ H'000002F3 (11 to 8) ↑ 1 A/D0 ADI0 190 H'000002F8 to H'000002FB ↓ 2 CMT1 CMTI1 192 H'00000300 to 0 to 15 (0) IPRJ H'00000303 (7 to 4) ↑ 1 A/D1 ADI1 194 H'00000308 to H'0000030B ↓ 2 SCI0 ERI0 200 H'00000320 to 0 to 15 (0) IPRK H'00000323 (15 to 12) ↑ 1 RXI0 201 H'00000324 to H'00000327 2 TXI0 202 H'00000328 to H'0000032B 3 TEI0 203 H'0000032C to H'0000032F ↓ 4 ERI1 204 H'00000330 to 0 to 15 (0) IPRK H'00000333 (11 to 8) ↑ 1 RXI1 205 H'00000334 to H'00000337 2 TXI1 206 H'00000338 to H'0000033B 3 TEI1 207 H'0000033C to H'0000033F ↓ 4 ERI2 208 H'00000340 to 0 to 15 (0) IPRK H'00000343 (7 to 4) ↑ 1 RXI2 209 H'00000344 to H'00000347 2 TXI2 210 H'00000348 to H'0000034B 3 TEI2 211 H'0000034C to H'0000034F SCI1 SCI2 86 ↓ 4 High Low Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address No. Offset Interrupt Source SCI3 SCI4 HCAN WDT Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Setting Default Range Priority ↑ ERI3 212 H'00000350 to 0 to 15 (0) IPRK H'00000353 (3 to 0) RXI3 213 H'00000354 to H'00000357 2 TXI3 214 H'00000358 to H'0000035B 3 TEI3 215 H'0000035C to H'0000035F ↓ 4 ERI4 216 H'00000360 to 0 to 15 (0) IPRL H'00000363 (15 to 12) ↑ 1 RXI4 217 H'00000364 to H'00000367 2 TXI4 218 H'00000368 to H'0000036B 3 TEI4 219 H'0000036C to H'0000036F ↓ 4 ERS 220 H'00000370 to 0 to 15 (0) IPRL H'00000373 (11 to 8) ↑ 1 OVR 221 H'00000374 to H'00000377 2 RM 222 H'00000378 to H'0000037B 3 SLE 223 H'0000037C to H'0000037F ITI 224 H'00000380 to 0 to 15 (0) IPRL H'00000383 (7 to 4) ↓ 1 High 4 Low 87 6.3 Description of Registers 6.3.1 Interrupt Priority Registers A, C to L (IPRA, IPRC to IPRL) Interrupt priority registers A, C to L (IPRA, IPRC to IPRL) are 16-bit readable/writable registers that set priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts. Correspondence between interrupt request sources and each of the IPRA, IPRC to IPRL bits is shown in table 6.4. Bit: Initial value: R/W: Bit: Initial value: R/W: Table 6.4 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Interrupt Request Sources and IPRA, IPRC to IPRL Bits Register 15 to 12 11 to 8 7 to 4 3 to 0 Interrupt priority register A IRQ0 IRQ1 IRQ2 IRQ3 Interrupt priority register C DMAC0, 1 DMAC2, 3 ATU01 ATU02 Interrupt priority register D ATU03 ATU04 ATU11 ATU12 Interrupt priority register E ATU13 ATU21 ATU22 ATU23 Interrupt priority register F ATU31 ATU32 ATU41 ATU42 Interrupt priority register G ATU51 ATU52 ATU6 ATU7 Interrupt priority register H ATU81 ATU82 ATU83 ATU84 Interrupt priority register I ATU91 ATU92 ATU101 ATU102 Interrupt priority register J ATU11 CMT0, A/D0 CMT1, A/D1 Interrupt priority register K SCI0 SCI1 SCI2 SCI3 Interrupt priority register L SCI4 HCAN WDT 88 As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to each register. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 (0000) to H'F (1111) in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F. If multiple on-chip peripheral modules are assigned to the same bit (DMAC0 and DMAC1, DMAC2 and DMAC3, CMT0 and A/D0, and CMT1 and A/D1), those multiple modules are set to the same priority rank. IPRA, IPRC to IPRL are initialized to H'0000 by a reset and in hardware standby mode. They are not initialized in software standby mode. 6.3.2 Interrupt Control Register (ICR) ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and IRQ0 to IRQ3 and indicates the input signal level at the NMI pin. A reset and hardware standby mode initialize ICR but the software standby mode does not. Bit: 15 14 13 12 11 10 9 8 NMIL — — — — — — NMIE Initial value: * 0 0 0 0 0 0 0 R/W: R — — — — — — R/W Bit: 7 6 5 4 3 2 1 0 IRQ0S IRQ1S IRQ2S IRQ3S 0 0 0 0 0 0 0 0 R/W R/W R/W R/W Initial value: R/W: Note: * When NMI input is high: 1; when NMI input is low: 0 • Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. Bit 15: NMIL Description 0 NMI input level is low 1 NMI input level is high • Bits 14 to 9—Reserved: These bits always read 0. The write value should always be 0. 89 • Bit 8—NMI Edge Select (NMIE) Bit 8: NMIE Description 0 Interrupt request is detected on falling edge of NMI input (Initial value) 1 Interrupt request is detected on rising edge of NMI input • Bits 7 to 4—IRQ0 to IRQ3 Sense Select (IRQ0S to IRQ3S): These bits set the IRQ0 to IRQ3 interrupt request detection mode. Bits 7 to 4: IRQ0S to IRQ3S Description 0 Interrupt request is detected on low level of IRQ input 1 Interrupt request is detected on falling edge of IRQ input (Initial value) • Bits 3 to 0—Reserved: These bits always read 0. The write value should always be 0. 6.3.3 IRQ Status Register (ISR) ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins IRQ0 to IRQ3. When IRQ interrupts are set to edge detection, held interrupt requests can be withdrawn by writing 0 to IRQnF after reading IRQnF = 1. A reset and hardware standby mode initialize ISR but software standby mode does not. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 IRQ0F IRQ1F IRQ2F IRQ3F — — — — 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R R R R Initial value: R/W: • Bits 15 to 8—Reserved: These bits always read 0. The write value should always be 0. 90 • Bits 7 to 4—IRQ0 to IRQ3 Flags (IRQ0F to IRQ3F): These bits display the IRQ0 to IRQ3 interrupt request status. Bits 7 to 4: IRQ0F to IRQ3F Detection Setting Description 0 No IRQn interrupt request exists Level detection [Clearing condition] When IRQn input is high Edge detection No IRQn interrupt request was detected (Initial value) [Clearing conditions] 1 Level detection • When 0 is written after reading IRQnF = 1 • When IRQn interrupt exception processing has been executed An IRQn interrupt request exists [Setting condition] When IRQn input is low Edge detection An IRQn interrupt request was detected [Setting condition] When a falling edge occurs at an IRQn input • Bits 3 to 0—Reserved: These bits always read 0. The write value should always be 0. 91 6.4 Interrupt Operation 6.4.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6.2 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent, following the priority levels set in interrupt priority registers A, C to L (IPRA, IPRC to IPRL). Lower-priority interrupts are ignored. They are held pending until interrupt requests designated as edge-detect type are accepted. For IRQ interrupts, however, withdrawal is possible by accessing the IRQ status register (ISR). See section 6.2.3, IRQ Interrupts, for details. Interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its IPR setting range (as indicated in table 6.3) is selected. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3 to I0) in the CPU’s status register (SR). If the request priority level is equal to or less than the level set in I3 to I0, the request is ignored. If the request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The CPU detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception processing (figure 6.4). 5. SR and PC are saved onto the stack. 6. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in the status register (SR). 7. The CPU reads the start address of the exception service routine from the exception vector table for the accepted interrupt, jumps to that address, and starts executing the program there. This jump is not a delay branch. 92 Program execution state No Interrupt? Yes No NMI? Yes User break? Yes No H-UDI interrupt? Yes No Level 15 interrupt? Yes Yes Save SR to stack I3 to I0 ≤ level 14? No Save PC to stack Yes No Level 14 interrupt? Yes Level 1 interrupt? I3 to I0 ≤ level 13? Yes No Copy accept-interrupt level to I3 to I0 No Yes No I3 to I0 = level 0? No Read exception vector table Branch to exception service routine I3 to I0: Interrupt mask bits of status register Figure 6.2 Interrupt Sequence Flowchart 93 6.4.2 Stack after Interrupt Exception Processing Figure 6.3 shows the stack after interrupt exception processing. Address 4n–8 PC*1 32 bits 4n–4 SR 32 bits SP*2 4n Notes: 1. 2. PC: Start address of the next instruction (return destination instruction) after the executing instruction Always be certain that SP is a multiple of 4 Figure 6.3 Stack after Interrupt Exception Processing 94 6.5 Interrupt Response Time Table 6.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 6.4 shows an example of pipeline operation when an IRQ interrupt is accepted. Table 6.5 Interrupt Response Time Number of States NMI, Peripheral Module Item IRQ Notes DMAC activation judgment 0 or 1 0 1 state required for interrupt signals for which DMAC activation is possible Compare identified interrupt priority with SR mask level 2 3 Wait for completion of sequence currently being executed by CPU X (≥ 0) The longest sequence is for interrupt or address-error exception processing (X = 4 + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Time from start of interrupt 5 + m1 + m2 + m3 exception processing until fetch of first instruction of exception service routine starts Interrupt response time Total: (7 or 8) + m1 + m2 + m3 + X Performs the PC and SR saves and vector address fetch. 8 + m1 + m2 + m3 + X Minimum: 10 11 0.25 to 0.28 µs at 40 MHz Maximum: 12 + 2 (m1 + m2 + m3) + m4 12 + 2 (m1 + m2 + m3) + m4 0.48 µs at 40 MHz* Note: * When m1 = m2 = m3 = m4 = 1 m1–m4 are the number of states needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine 95 Interrupt acceptance 5 + m1 + m2 + m3 3 m1 m2 1 m3 1 3 IRQ Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction F D E E M M E M E E F F D E F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address calculation is performed according to the results of decoding). M: Memory access (data in memory is accessed). Figure 6.4 Example of Pipeline Operation when an IRQ Interrupt is Accepted 96 6.6 Data Transfer with Interrupt Request Signals The following data transfer can be carried out using interrupt request signals: • Activate DMAC only, without generating CPU interrupt Among interrupt sources, those designated as DMAC activating sources are masked and not input to the INTC. The masking condition is as follows: Mask condition = DME · (DE0 · source selection 0 + DE1 · source selection 1 + DE2 · source selection 2 + DE3 · source selection 3) 6.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources 1. Either do not select the DMAC as a source, or clear the DME bit to 0. 2. Activating sources are applied to the CPU when interrupts occur. 3. The CPU clears interrupt sources with its interrupt processing routine and performs the necessary processing. 6.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources 1. Select the DMAC as a source and set the DME bit to 1. CPU interrupt sources are masked regardless of the interrupt priority level register settings. 2. Activating sources are applied to the DMAC when interrupts occur. 3. The DMAC clears activating sources at the time of data transfer. 97 98 Section 7 User Break Controller (UBC) 7.1 Overview The user break controller (UBC) provides functions that simplify program debugging. Break conditions are set in the UBC and a user break interrupt is generated according to the conditions of the bus cycle generated by the CPU or DMAC. This function makes it easy to design an effective self-monitoring debugger, enabling the chip to easily debug programs without using a large incircuit emulator. 7.1.1 Features The features of the user break controller are: • The following break compare conditions can be set: Address CPU cycle/DMA cycle Instruction fetch or data access Read or write Operand size: byte/word/longword • User break interrupt generated upon satisfying break conditions A user-designed user break interrupt exception processing routine can be run. • Select either to break in the CPU instruction fetch cycle before the instruction is executed or after. • Satisfaction of a break condition can be output to the UBCTRG pin. 99 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the UBC. UBCR UBBR UBAMRH UBARH UBAMRL UBARL Internal bus Bus interface Module bus Break condition comparator User break interrupt generating circuit Trigger output generating circuit UBARH, UBARL: UBAMRH, UBAMRL: UBBR: UBCR: Interrupt request Interrupt controller UBCTRG pin output User break address registers H, L User break address mask registers H, L User break bus cycle register User break control register Figure 7.1 User Break Controller Block Diagram 100 7.1.3 Register Configuration The UBC has the six registers shown in table 7.1. Break conditions are established using these registers. Table 7.1 Register Configuration Name Abbr. R/W Initial Value Address* Access Size User break address register H UBARH R/W H'0000 H'FFFFEC00 8, 16, 32 User break address register L UBARL R/W H'0000 H'FFFFEC02 8, 16, 32 User break address mask register H UBAMRH R/W H'0000 H'FFFFEC04 8, 16, 32 User break address mask register L UBAMRL R/W H'0000 H'FFFFEC06 8, 16, 32 User break bus cycle register UBBR R/W H'0000 H'FFFFEC08 8, 16, 32 User break control register UBCR R/W H'0000 H'FFFFEC0A 8, 16, 32 Note: * In register access, three cycles are required for byte access and word access, and six cycles for longword access. 7.2 Register Descriptions 7.2.1 User Break Address Register (UBAR) UBARH: Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 UBA31 UBA30 UBA29 UBA28 UBA27 UBA26 UBA25 UBA24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 UBA23 UBA22 UBA21 UBA20 UBA19 UBA18 UBA17 UBA16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 101 UBARL: Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 UBA15 UBA14 UBA13 UBA12 UBA11 UBA10 UBA9 UBA8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 UBA7 UBA6 UBA5 UBA4 UBA3 UBA2 UBA1 UBA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The user break address register (UBAR) consists of user break address register H (UBARH) and user break address register L (UBARL). Both are 16-bit readable/writable registers. UBARH stores the upper bits (bits 31 to 16) of the address of the break condition, while UBARL stores the lower bits (bits 15 to 0). UBARH and UBARL are initialized to H'0000 by a power-on reset and in module standby mode. They are not initialized in software standby mode. • UBARH Bits 15 to 0—User Break Address 31 to 16 (UBA31 to UBA16): These bits store the upper bit values (bits 31 to 16) of the address of the break condition. • UBARL Bits 15 to 0—User Break Address 15 to 0 (UBA15 to UBA0): These bits store the lower bit values (bits 15 to 0) of the address of the break condition. 7.2.2 User Break Address Mask Register (UBAMR) UBAMRH: Bit: 15 UBM31 Initial value: R/W: Bit: R/W: 102 13 UBM30 UBM29 12 11 UBM28 UBM27 10 UBM26 9 8 UBM25 UBM24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 UBM23 Initial value: 14 UBM22 UBM21 UBM20 UBM19 UBM18 UBM17 UBM16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W UBAMRL: Bit: 15 14 UBM15 Initial value: R/W: Bit: Initial value: R/W: 13 UBM14 UBM13 12 11 UBM12 UBM11 10 9 8 UBM10 UBM9 UBM8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 UBM7 UBM6 UBM5 UBM4 UBM3 UBM2 UBM1 UBM0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The user break address mask register (UBAMR) consists of user break address mask register H (UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit readable/writable registers. UBAMRH designates whether to mask any of the break address bits established in UBARH, and UBAMRL designates whether to mask any of the break address bits established in UBARL. UBAMRH and UBAMRL are initialized to H'0000 by a power-on reset and in module standby mode. They are not initialized in software standby mode. • UBAMRH Bits 15 to 0—User Break Address Mask 31 to 16 (UBM31 to UBM16): These bits designate whether to mask the corresponding break address 31 to 16 bits (UBA31 to UBA16) established in UBARH. • UBAMRL Bits 15 to 0—User Break Address Mask 15 to 0 (UBM15 to UBM0): These bits designate whether to mask the corresponding break address 15 to 0 bits (UBA15 to UBA0) established in UBARL. Bit 15 to 0: UBMn Description 0 Break address UBAn is included in the break conditions (Initial value) 1 Break address UBAn is not included in the break conditions Note: n = 31 to 0 103 7.2.3 User Break Bus Cycle Register (UBBR) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 CP1 CP0 ID1 ID0 RW1 RW0 SZ1 SZ0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: The user break bus cycle register (UBBR) is a 16-bit readable/writable register that selects from among the following four break conditions: 1. 2. 3. 4. CPU cycle/DMA cycle Instruction fetch/data access Read/write Operand size (byte, word, longword) UBBR is initialized to H'0000 by a power on reset and in module standby mode. It is not initialized in software standby mode. • Bits 15 to 8—Reserved: These bits always read 0. The write value should always be 0. • Bits 7 and 6—CPU Cycle/DMA Cycle Select (CP1, CP0): These bits designate break conditions for CPU cycles or DMA cycles. Bit 7: CP1 Bit 6: CP0 Description 0 0 No user break interrupt occurs 1 Break on CPU cycles 0 Break on DMA cycles 1 Break on both CPU and DMA cycles 1 104 (Initial value) • Bits 5 and 4—Instruction Fetch/Data Access Select (ID1, ID0): These bits select whether to break on instruction fetch and/or data access cycles. Bit 5: ID1 Bit 4: ID0 Description 0 0 No user break interrupt occurs 1 Break on instruction fetch cycles 0 Break on data access cycles 1 Break on both instruction fetch and data access cycles 1 (Initial value) • Bits 3 and 2—Read/Write Select (RW1, RW0): These bits select whether to break on read and/or write cycles. Bit 3: RW1 Bit 2: RW0 Description 0 0 No user break interrupt occurs 1 Break on read cycles 0 Break on write cycles 1 Break on both read and write cycles 1 (Initial value) • Bits 1 and 0—Operand Size Select (SZ1, SZ0): These bits select operand size as a break condition. Bit 1: SZ1 Bit 0: SZ0 Description 0 0 Operand size is not a break condition 1 Break on byte access 0 Break on word access 1 Break on longword access 1 (Initial value) Note: When breaking on an instruction fetch, clear the SZ0 bit to 0. All instructions are considered to be word-size accesses (even when there are instructions in on-chip memory and two instruction fetches are performed simultaneously in one bus cycle). Operand size is word for instructions or determined by the operand size specified for the CPU/DMAC data access. It is not determined by the bus width of the space being accessed. 105 7.2.4 User Break Control Register (UBCR) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — CKS1 CKS0 UBID Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W The user break control register (UBCR) is a 16-bit readable/writable register that (1) enables or disables user break interrupts and (2) sets the pulse width of the UBCTRG signal output in the event of a break condition match. UBCR is initialized to H'0000 by a power-on reset and in module standby mode. It is not initialized in software standby mode. • Bits 15 to 3—Reserved: These bits always read 0. The write value should always be 0. • Bits 2 and 1—Clock Select 1 and 0 (CKS1, CKS0): These bits specify the pulse width of the UBCTRG signal output in the event of a condition match. Bit 2: CKS1 Bit 1: CKS0 Description 0 0 UBCTRG pulse width is φ 1 UBCTRG pulse width is φ/4 0 UBCTRG pulse width is φ/8 1 UBCTRG pulse width is φ/16 1 (Initial value) Note: φ: Internal clock • Bit 0—User Break Disable (UBID): Enables or disables user break interrupt request generation in the event of a user break condition match. Bit 0: UBID Description 0 User break interrupt request is enabled 1 User break interrupt request is disabled 106 (Initial value) 7.3 Operation 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break interrupt exception processing is described below: 1. The user break addresses are set in the user break address register (UBAR), the desired masked bits in the addresses are set in the user break address mask register (UBAMR) and the breaking bus cycle type is set in the user break bus cycle register (UBBR). If even one of the three groups of the UBBR’s CPU cycle/DMA cycle select bits (CP1, CP0), instruction fetch/data access select bits (ID1, ID0), and read/write select bits (RW1, RW0) is set to 00 (no user break generated), no user break interrupt will be generated even if all other conditions are in agreement. When using user break interrupts, always be certain to establish bit conditions for all of these three groups. 2. The UBC uses the method shown in figure 7.2 to judge whether set conditions have been fulfilled. When the set conditions are satisfied, the UBC sends a user break interrupt request signal to the interrupt controller (INTC). At the same time, a condition match signal is output at the UBCTRG pin with the pulse width set in bits CKS1 and CKS0. 3. The interrupt controller checks the accepted user break interrupt request signal’s priority level. The user break interrupt has priority level 15, so it is accepted only if the interrupt mask level in bits I3 to I0 in the status register (SR) is 14 or lower. When the I3 to I0 bit level is 15, the user break interrupt cannot be accepted but it is held pending until user break interrupt exception processing can be carried out. Consequently, user break interrupts within NMI exception service routines cannot be accepted, since the I3 to I0 bit level is 15. However, if the I3 to I0 bit level is changed to 14 or lower at the start of the NMI exception service routine, user break interrupts become acceptable thereafter. Section 6, Interrupt Controller, describes the handling of priority levels in greater detail. 4. The INTC sends the user break interrupt request signal to the CPU, which begins user break interrupt exception processing upon receipt. See Section 6.4, Interrupt Operation, for details on interrupt exception processing. 107 UBARH/UBARL UBAMRH/UBAMRL 32 32 Internal address bits 31 to 0 32 CP1 CP0 ID1 ID0 32 32 CPU cycle DMA cycle Instruction fetch User break interrupt Data access RW1 RW0 SZ1 SZ0 Read cycle Write cycle Byte size Word size Longword size UBID Figure 7.2 Break Condition Judgment Method 108 7.3.2 Break on On-Chip Memory Instruction Fetch Cycle On-chip memory (on-chip ROM and/or RAM) is always accessed as 32 bits in one bus cycle. Therefore, two instructions can be retrieved in one bus cycle when fetching instructions from onchip memory. At such times, only one bus cycle is generated, but by setting the start addresses of both instructions in the user break address register (UBAR) it is possible to cause independent breaks. In other words, when wanting to effect a break using the latter of two addresses retrieved in one bus cycle, set the start address of that instruction in UBAR. The break will occur after execution of the former instruction. 7.3.3 Program Counter (PC) Values Saved Break on Instruction Fetch: The program counter (PC) value saved to the stack in user break interrupt exception processing is the address that matches the break condition. The user break interrupt is generated before the fetched instruction is executed. If a break condition is set in an instruction fetch cycle placed immediately after a delayed branch instruction (delay slot), or on an instruction that follows an interrupt-disabled instruction, however, the user break interrupt is not accepted immediately, but the break condition establishing instruction is executed. The user break interrupt is accepted after execution of the instruction that has accepted the interrupt. In this case, the PC value saved is the start address of the instruction that will be executed after the instruction that has accepted the interrupt. Break on Data Access (CPU/DMA): The program counter (PC) value is the top address of the next instruction after the last instruction executed before the user break exception processing started. When data access (CPU/DMA) is set as a break condition, the place where the break will occur cannot be specified exactly. The break will occur at the instruction fetched close to where the data access that is to receive the break occurs. 109 7.4 Examples of Use 7.4.1 Break on CPU Instruction Fetch Cycle 1. Register settings: UBARH = H'0000 UBARL = H'0404 UBBR = H'0054 UBCR = H'0000 Conditions set: Address: H'00000404 Bus cycle: CPU, instruction fetch, read (operand size not included in conditions) Interrupt requests enabled A user break interrupt will occur before the instruction at address H'00000404. If it is possible for the instruction at H'00000402 to accept an interrupt, the user break exception processing will be executed after execution of that instruction. The instruction at H'00000404 is not executed. The PC value saved is H'00000404. 2. Register settings: UBARH = H'0015 UBARL = H'389C UBBR = H'0058 UBCR = H'0000 Conditions set: Address: H'0015389C Bus cycle: CPU, instruction fetch, write (operand size not included in conditions) Interrupt requests enabled A user break interrupt does not occur because the instruction fetch cycle is not a write cycle. 3. Register settings: UBARH = H'0003 UBARL = H'0147 UBBR = H'0054 UBCR = H'0000 Conditions set: Address: H'00030147 Bus cycle: CPU, instruction fetch, read (operand size not included in conditions) Interrupt requests enabled A user break interrupt does not occur because the instruction fetch was performed for an even address. However, if the first instruction fetch address after the branch is an odd address set by these conditions, user break interrupt exception processing will be carried out after address error exception processing. 110 7.4.2 Break on CPU Data Access Cycle 1. Register settings: UBARH = H'0012 UBARL = H'3456 UBBR = H'006A UBCR = H'0000 Conditions set: Address: H'00123456 Bus cycle: CPU, data access, write, word Interrupt requests enabled A user break interrupt occurs when word data is written into address H'00123456. 2. Register settings: UBARH = H'00A8 UBARL = H'0391 UBBR = H'0066 UBCR = H'0000 Conditions set: Address: H'00A80391 Bus cycle: CPU, data access, read, word Interrupt requests enabled A user break interrupt does not occur because the word access was performed on an even address. 7.4.3 Break on DMA Cycle 1. Register settings: UBARH = H'0076 UBARL = H'BCDC UBBR = H'00A7 UBCR = H'0000 Conditions set: Address: H'0076BCDC Bus cycle: DMA, data access, read, longword Interrupt requests enabled A user break interrupt occurs when longword data is read from address H'0076BCDC. 2. Register settings: UBARH = H'0023 UBARL = H'45C8 UBBR = H'0094 UBCR = H'0000 Conditions set: Address: H'002345C8 Bus cycle: DMA, instruction fetch, read (operand size not included in conditions) Interrupt requests enabled A user break interrupt does not occur because no instruction fetch is performed in the DMA cycle. 111 7.5 Usage Notes 7.5.1 Simultaneous Fetching of Two Instructions Two instructions may be simultaneously fetched from on-chip memory. If a break condition is set on the second of these two instructions but the contents of the UBC break condition registers are changed so as to alter the break condition immediately after the first of the two instructions is fetched, a user break interrupt will still occur when the second instruction is fetched. 7.5.2 Instruction Fetch at Branches When a conditional branch instruction or TRAPA instruction causes a branch, instructions are fetched and executed as follows: 1. Conditional branch instruction, branch taken: BT, BF TRAPA instruction, branch taken: TRAPA Instruction fetch order: Branch instruction fetch → next instruction overrun fetch → overrun fetch of instruction after next → branch destination instruction fetch Instruction execution order: Branch instruction execution → branch destination instruction execution 2. When branching with a delayed conditional instruction: BT/S and BF/S instructions Instruction fetch order: Branch instruction fetch → next instruction fetch (delay slot) → overrun fetch of instruction after next → branch destination instruction fetch Instruction execution order: Branch instruction execution → delay slot instruction execution → branch destination instruction execution When a conditional branch instruction or TRAPA instruction causes a branch, the branch destination will be fetched after the next instruction or the one after that performs an overrun fetch. However, because the instruction that is the object of the break first breaks after a definite instruction fetch and execution, the kind of overrun fetch instructions noted above do not become objects of a break. If data access breaks are also included with instruction fetch breaks as break conditions, a break occurs because the instruction overrun fetch is also regarded as becoming a data break. 112 7.5.3 Contention between User Break and Exception Processing If a user break is set for the fetch of a particular instruction, and exception processing with higher priority than a user break is in contention and is accepted in the decode stage for that instruction (or the next instruction), user break exception processing may not be performed after completion of the higher-priority exception service routine (on return by RTE). Thus, if a user break condition is applied to the branch destination instruction fetch after a branch (BRA, BRAF, BT, BF, BT/S, BF/S, BSR, BSRF, JMP, JSR, RTS, RTE, exception processing), and that branch instruction accepts exception processing with higher priority than a user break interrupt, user break exception processing is not performed after completion of the higher-priority exception service routine. Therefore, a user break condition should not be set for the fetch of the branch destination instruction after a branch. 7.5.4 Break at Non-Delay Branch Instruction Jump Destination When a branch instruction with no delay slot (including exception processing) jumps to the jump destination instruction on execution of the branch, a user break will not be generated even if a user break condition has been set for the first jump destination instruction fetch. 7.5.5 User Break Trigger Output Information on internal bus condition matches monitored by the UBC is output as UBCTRG. The trigger width can be set with clock select bits 1 and 0 (CKS1, CKS0) in the user break control register (UBCR). If a condition matches occurs again during trigger output, the UBCTRG pin continues to output a low level, and outputs a pulse of the length set in bits CKS1 and CKS0 from the cycle in which the last condition match occurs. The trigger output conditions differ from those in the case of a user break interrupt when a CPU instruction fetch condition is satisfied. When a condition occurs in an overrun fetch instruction as described in section 7.5.2, Instruction Fetch at Branches, a user break interrupt is not requested but a trigger is output from the UBCTRG pin. In other CPU data accesses and DMAC bus cycles, pulse output is performed under conditions similar to user break interrupt conditions. Setting the user break interrupt disable (UBID) bit to 1 in UBCR enables trigger output to be monitored externally without requesting a user break interrupt. 113 7.5.6 Module Standby After a power-on reset the UBC is in the module standby state, in which the clock supply is halted. When using the UBC, the module standby state must be cleared before making UBC register settings. Module standby is controlled by the module standby control register (MSTCR). See section 23.2.3, Module Standby Control Register, for further details. 114 Section 8 Bus State Controller (BSC) 8.1 Overview The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM and ROM to be linked directly to the chip without external circuitry, simplifying system design and enabling high-speed data transfer to be achieved in a compact system. 8.1.1 Features The BSC has the following features: • Address space is divided into four spaces A maximum linear 2 Mbytes for on-chip ROM effective mode, and a maximum 4 Mbytes for on-chip ROM disabled mode, for address space CS0 A maximum linear 4 Mbytes for each of address spaces CS1 to CS3 Bus width can be selected for each space (8 or 16 bits) Wait states can be inserted by software for each space Wait state insertion with WAIT pin in external memory space access Outputs control signals for each space according to the type of memory connected • On-chip ROM and RAM interfaces On-chip ROM and RAM access of 32 bits in 1 state 115 8.1.2 Block Diagram WAIT On-chip memory control unit RAMER Wait control unit WCR Module bus Bus interface BCR1 CS0 to CS3 Area control unit BCR2 RD Memory control unit WRH, WRL BSC WCR: Wait control register RAMER: RAM emulation register BCR1: BCR2: Bus control register 1 Bus control register 2 Figure 8.1 BSC Block Diagram 116 Internal bus Figure 8.1 shows the BSC block diagram. 8.1.3 Pin Configuration Table 8.1 shows the bus state controller pin configuration. Table 8.1 Pin Configuration Name Abbr. I/O Description Address bus A21 to A0 O Address output Data bus D15 to D0 I/O 16-bit data bus Chip select CS0 to CS3 O Chip select signals indicating the area being accessed Read RD O Strobe that indicates the read cycle for ordinary space/multiplex I/O Upper write WRH O Strobe that indicates a write cycle to the upper 8 bits (D15 to D8) Lower write WRL O Strobe that indicates a write cycle to the lower 8 bits (D7 to D0) Wait WAIT I Wait state request signal Bus request BREQ I Bus release request input Bus acknowledge BACK O Bus use enable output Note: When an 8-bit bus width is selected for external space, WRL is enabled. When a 16-bit bus width is selected for external space, WRH and WRL are enabled. 8.1.4 Register Configuration The BSC has four registers. These registers are used to control wait states, bus width, and interfaces with memories like ROM and SRAM, as well as refresh control. The register configurations are listed in table 8.2. All registers are 16 bits. All BSC registers are all initialized by a power-on reset and in hardware standby mode. Values are retained in a manual reset and in software standby mode. 117 Table 8.2 Register Configuration Name Abbr. R/W Initial Value Address Access Size Bus control register 1 BCR1 R/W H'000F H'FFFFEC20 8, 16, 32 Bus control register 2 BCR2 R/W H'FFFF H'FFFFEC22 8, 16, 32 Wait state control register WCR R/W H'FFFF H'FFFFEC24 8, 16, 32 RAM emulation register RAMER R/W H'0000 H'FFFFEC26 8, 16, 32 Note: In register access, three cycles are required for byte access and word access, and six cycles for longword access. 8.1.5 Address Map Figure 8.2 shows the address format used by the SH7052F/SH7053F/SH7054F. A31 to A24 A23, A22 A0 A21 Output address: Output from the address pins CS space selection: Decoded, outputs CS0 to CS3 when A31 to A24 = 00000000 Space selection: Not output externally; used to select the type of space On-chip ROM space or CS0 to CS3 space when 00000000 (H'00) Reserved (do not access) when 00000001 to 11111110 (H'01 to H'FE) On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF) Figure 8.2 Address Format This chip uses 32-bit addresses: • Bits A31 to A24 are used to select the type of space and are not output externally. • Bits A23 and A22 are decoded and output as chip select signals (CS0 to CS3) for the corresponding areas when bits A31 to A24 are 00000000. • A21 to A0 are output externally. 118 Tables 8.3, 8.4 and 8.5 show the address map. Table 8.3 Address Map • On-chip ROM enabled mode (SH7052F) Address Space Memory Size Bus Width H'0000 0000 to H'0003 FFFF On-chip ROM On-chip ROM 256 kB 32 bits H'0004 0000 to H'001F FFFF Reserved Reserved H'0020 0000 to H'003F FFFF CS0 space External space 2 MB 8, 16 bits * 1 H'0040 0000 to H'007F FFFF CS1 space External space 4 MB 8, 16 bits * 1 H'0080 0000 to H'00BF FFFF CS2 space External space 4 MB 8, 16 bits * 1 H'00C0 0000 to H'00FF FFFF CS3 space External space 4 MB 8, 16 bits * 1 H'0100 0000 to H'FFFF 7FFF Reserved Reserved H'FFFF 8000 to H'FFFF AFFF On-chip RAM On-chip RAM 12 kB 32 bits H'FFFF B000 to H'FFFF DFFF Reserved Reserved H'FFFF E000 to H'FFFF FFFF On-chip peripheral module 8 kB 8, 16 bits On-chip peripheral module • On-chip ROM disabled mode (SH7052F) Address Space Memory Size Bus Width H'0000 0000 to H'003F FFFF CS0 space External space 4 MB 8, 16 bits * 2 H'0040 0000 to H'007F FFFF CS1 space External space 4 MB 8, 16 bits * 1 H'0080 0000 to H'00BF FFFF CS2 space External space 4 MB 8, 16 bits * 1 H'00C0 0000 to H'00FF FFFF CS3 space External space 4 MB 8, 16 bits * 1 H'0100 0000 to H'FFFF 7FFF Reserved Reserved H'FFFF 8000 to H'FFFF AFFF On-chip RAM On-chip RAM 12 kB 32 bits 8 kB 8, 16 bits H'FFFF B000 to H'FFFF DFFF Reserved Reserved H'FFFF E000 to H'FFFF FFFF On-chip peripheral module On-chip peripheral module Notes: Do not access reserved spaces. Operation cannot be guaranteed if they are accessed. 1. Selected by on-chip register (BCR1) settings. 2. Selected by the mode pin. 119 Table 8.4 Address Map • On-chip ROM enabled mode (SH7053F) Address Space Memory Size Bus Width H'0000 0000 to H'0003 FFFF On-chip ROM On-chip ROM 256 kB 32 bits H'0004 0000 to H'001F FFFF Reserved Reserved H'0020 0000 to H'003F FFFF CS0 space External space 2 MB 8, 16 bits * 1 H'0040 0000 to H'007F FFFF CS1 space External space 4 MB 8, 16 bits * 1 H'0080 0000 to H'00BF FFFF CS2 space External space 4 MB 8, 16 bits * 1 H'00C0 0000 to H'00FF FFFF CS3 space External space 4 MB 8, 16 bits * 1 H'0100 0000 to H'FFFF 7FFF Reserved Reserved H'FFFF 8000 to H'FFFF BFFF On-chip RAM On-chip RAM 12 kB 32 bits H'FFFF C000 to H'FFFF DFFF Reserved Reserved H'FFFF E000 to H'FFFF FFFF On-chip peripheral module 8 kB 8, 16 bits On-chip peripheral module • On-chip ROM disabled mode (SH7053F) Address Space Memory Size Bus Width H'0000 0000 to H'003F FFFF CS0 space External space 4 MB 8, 16 bits * 2 H'0040 0000 to H'007F FFFF CS1 space External space 4 MB 8, 16 bits * 1 H'0080 0000 to H'00BF FFFF CS2 space External space 4 MB 8, 16 bits * 1 H'00C0 0000 to H'00FF FFFF CS3 space External space 4 MB 8, 16 bits * 1 H'0100 0000 to H'FFFF 7FFF Reserved Reserved H'FFFF 8000 to H'FFFF BFFF On-chip RAM On-chip RAM 16 kB 32 bits 8 kB 8, 16 bits H'FFFF B000 to H'FFFF DFFF Reserved Reserved H'FFFF E000 to H'FFFF FFFF On-chip peripheral module On-chip peripheral module Notes: Do not access reserved spaces. Operation cannot be guaranteed if they are accessed. 1. Selected by on-chip register (BCR1) settings. 2. Selected by the mode pin. 120 Table 8.5 Address Map • On-chip ROM enabled mode (SH7054F) Address Space Memory Size Bus Width H'0000 0000 to H'0005 FFFF On-chip ROM On-chip ROM 384 kB 32 bits H'0006 0000 to H'001F FFFF Reserved Reserved H'0020 0000 to H'003F FFFF CS0 space External space 2 MB 8, 16 bits * 1 H'0040 0000 to H'007F FFFF CS1 space External space 4 MB 8, 16 bits * 1 H'0080 0000 to H'00BF FFFF CS2 space External space 4 MB 8, 16 bits * 1 H'00C0 0000 to H'00FF FFFF CS3 space External space 4 MB 8, 16 bits * 1 H'0100 0000 to H'FFFF 7FFF Reserved Reserved H'FFFF 8000 to H'FFFF BFFF On-chip RAM On-chip RAM 16 kB 32 bits H'FFFF C000 to H'FFFF DFFF Reserved Reserved H'FFFF E000 to H'FFFF FFFF On-chip peripheral module 8 kB 8, 16 bits On-chip peripheral module • On-chip ROM disabled mode (SH7054F) Address Space Memory Size Bus Width H'0000 0000 to H'003F FFFF CS0 space External space 4 MB 8, 16 bits * 2 H'0040 0000 to H'007F FFFF CS1 space External space 4 MB 8, 16 bits * 1 H'0080 0000 to H'00BF FFFF CS2 space External space 4 MB 8, 16 bits * 1 H'00C0 0000 to H'00FF FFFF CS3 space External space 4 MB 8, 16 bits * 1 H'0100 0000 to H'FFFF 7FFF Reserved Reserved H'FFFF 8000 to H'FFFF BFFF On-chip RAM On-chip RAM 16 kB 32 bits 8 kB 8, 16 bits H'FFFF C000 to H'FFFF DFFF Reserved Reserved H'FFFF E000 to H'FFFF FFFF On-chip peripheral module On-chip peripheral module Notes: Do not access reserved spaces. Operation cannot be guaranteed if they are accessed. 1. Selected by on-chip register (BCR1) settings. 2. Selected by the mode pin. 121 8.2 Description of Registers 8.2.1 Bus Control Register 1 (BCR1) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — A3SZ A2SZ A1SZ A0SZ Initial value: 0 0 0 0 1 1 1 1 R/W: R R R R R/W R/W R/W R/W BCR1 is a 16-bit readable/writable register that specifies the bus size of the CS spaces. Write bits 15 to 0 of BCR1 during the initialization stage after a power-on reset, and do not change the values thereafter. In on-chip ROM enabled mode, do not access any of the CS spaces until after completion of register initialization. In on-chip ROM disabled mode, do not access any CS space other than CS0 until after completion of register initialization. BCR1 is initialized to H'000F by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. • Bits 15 to 4—Reserved: These bits always read 0. Operation cannot be guaranteed if 1 is written to these bits. • Bit 3—CS3 Space Size Specification (A3SZ): Specifies the CS3 space bus size. A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 3: A3SZ Description 0 Byte (8-bit) size 1 Word (16-bit) size (Initial value) • Bit 2—CS2 Space Size Specification (A2SZ): Specifies the CS2 space bus size. A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 2: A2SZ Description 0 Byte (8-bit) size 1 Word (16-bit) size 122 (Initial value) • Bit 1—CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size. A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 1: A1SZ Description 0 Byte (8-bit) size 1 Word (16-bit) size (Initial value) • Bit 0—CS0 Space Size Specification (A0SZ): Specifies the CS0 space bus size A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 0: A0SZ Description 0 Byte (8-bit) size 1 Word (16-bit) size (Initial value) Note: A0SZ is valid only in on-chip ROM enabled mode. In on-chip ROM disabled mode, the CS0 space bus size is specified by the mode pin. 8.2.2 Bus Control Register 2 (BCR2) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 IW31 IW30 IW21 IW20 IW11 IW10 IW01 IW00 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 CW3 CW2 CW1 CW0 SW3 SW2 SW1 SW0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS signal assert extension of each CS space. BCR2 is initialized to H'FFFF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. • Bits 15 to 8—Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00): These bits specify idle cycles inserted between consecutive accesses when the second one is to a different CS area after a read. Idles are used to prevent data conflict between ROM (and other memories, which are slow to turn the read data buffer off), fast memories, and I/O interfaces. Even when access is to the same area, idle cycles must be inserted when a read access is followed immediately by a write access. The idle cycles to be inserted comply with 123 the area specification of the previous access. Refer to section 8.4, Waits between Access Cycles, for details. IW31 and IW30 specify the idle between cycles for CS3 space; IW21 and IW20 specify the idle between cycles for CS2 space; IW11 and IW10 specify the idle between cycles for CS1 space and IW01 and IW00 specify the idle between cycles for CS0 space. Bit 15: IW31 Bit 14: IW30 Description 0 0 No CS3 space idle cycle 1 Inserts one idle cycle 0 Inserts two idle cycles 1 Inserts three idle cycles Bit 13: IW21 Bit 12: IW20 Description 0 0 No CS2 space idle cycle 1 Inserts one idle cycle 0 Inserts two idle cycles 1 Inserts three idle cycles Bit 11: IW11 Bit 10: IW10 Description 0 0 No CS1 space idle cycle 1 Inserts one idle cycle 0 Inserts two idle cycles 1 Inserts three idle cycles Bit 9: IW01 Bit 8: IW00 Description 0 0 No CS0 space idle cycle 1 Inserts one idle cycle 0 Inserts two idle cycles 1 Inserts three idle cycles 1 1 1 1 (Initial value) (Initial value) (Initial value) (Initial value) • Bits 7 to 4—Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The continuous access idle specification makes insertions to clearly delineate the bus intervals by once negating the CSn signal when performing consecutive accesses to the same CS space. When a write immediately follows a read, the number of idle cycles inserted is the larger of the two values specified by IW and CW. Refer to section 8.4, Waits between Access Cycles, for details. 124 CW3 specifies the continuous access idles for CS3 space; CW2 specifies the continuous access idles for CS2 space; CW1 specifies the continuous access idles for CS1 space and CW0 specifies the continuous access idles for CS0 space. Bit 7: CW3 Description 0 No CS3 space continuous access idle cycles 1 One CS3 space continuous access idle cycle Bit 6: CW2 Description 0 No CS2 space continuous access idle cycles 1 One CS2 space continuous access idle cycle Bit 5: CW1 Description 0 No CS1 space continuous access idle cycles 1 One CS1 space continuous access idle cycle Bit 4: CW0 Description 0 No CS0 space continuous access idle cycles 1 One CS0 space continuous access idle cycle (Initial value) (Initial value) (Initial value) (Initial value) • Bits 3 to 0—CS Assert Extension Specification (SW3, SW2, SW1, SW0): The CS assert cycle extension specification is for making insertions to prevent extension of the RD signal, WRH signal, or WRL signal assert period beyond the length of the CSn signal assert period. Extended cycles insert one cycle before and after each bus cycle, which simplifies interfaces with external devices and also has the effect of extending the write data hold time. Refer to section 8.3.3, CS Assert Period Extension, for details. SW3 specifies the CS assert extension for CS3 space access; SW2 specifies the CS assert extension for CS2 space access; SW1 specifies the CS assert extension for CS1 space access and SW0 specifies the CS assert extension for CS0 space access. Bit 3: SW3 Description 0 No CS3 space CS assert extension 1 CS3 space CS assert extension Bit 2: SW2 Description 0 No CS2 space CS assert extension 1 CS2 space CS assert extension (Initial value) (Initial value) 125 Bit 1: SW1 Description 0 No CS1 space CS assert extension 1 CS1 space CS assert extension Bit 0: SW0 Description 0 No CS0 space CS assert extension 1 CS0 space CS assert extension 8.2.3 (Initial value) (Initial value) Wait Control Register (WCR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 W33 W32 W31 W30 W23 W22 W21 W20 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 W13 W12 W11 W10 W03 W02 W01 W00 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W WCR is a 16-bit readable/writable register that specifies the number of wait cycles for each CS space. WCR1 is initialized to H'FFFF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. • Bits 15 to 12—CS3 Space Wait Specification (W33, W32, W31, W30): These bits specify the number of waits for CS3 space access. Bit 15: W33 Bit 14: W32 Bit 13: W31 Bit 12: W30 Description 0 0 0 0 No wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled 1 1 15 wait external wait input enabled ⋅⋅⋅ 1 126 1 (Initial value) • Bits 11 to 8—CS2 Space Wait Specification (W23, W22, W21, W20): These bits specify the number of waits for CS2 space access. Bit 11: W23 Bit 10: W22 Bit 9: W21 Bit 8: W20 Description 0 0 0 0 No wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled 1 1 15 wait external wait input enabled ⋅⋅⋅ 1 1 (Initial value) • Bits 7 to 4—CS1 Space Wait Specification (W13, W12, W11, W10): These bits specify the number of waits for CS1 space access. Bit 7: W13 Bit 6: W12 Bit 5: W11 Bit 4: W10 Description 0 0 0 0 No wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled 1 1 15 wait external wait input enabled ⋅⋅⋅ 1 1 (Initial value) • Bits 3 to 0—CS0 Space Wait Specification (W03, W02, W01, W00): These bits specify the number of waits for CS0 space access. Bit 3: W03 Bit 2: W02 Bit 1: W01 Bit 0: W00 Description 0 0 0 0 No wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled 1 1 15 wait external wait input enabled ⋅⋅⋅ 1 1 (Initial value) 127 8.2.4 RAM Emulation Register (RAMER) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — RAMS RAM2 RAM1 RAM0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM area to be used when emulating realtime programming of flash memory. RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Note: To ensure correct operation of the RAM emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Operation cannot be guaranteed if such an access is made. • Bits 15 to 4—Reserved: Only 0 should be written to these bits. Operation cannot be guaranteed if 1 is written. • Bit 3—RAM Select (RAMS): Used together with bits 2 to 0 to select or deselect flash memory emulation by RAM (table 8.6). When 1 is written to this bit, all flash memory blocks are write/erase-protected. This bit is ignored in modes with on-chip ROM disabled. • Bits 2 to 0—RAM Area Specification (RAM2 to RAM0): These bits are used together with the RAMS bit to designate the flash memory area to be overlapped onto RAM (table 8.6). 128 Table 8.6 RAM Area Setting Method RAM Area Bit 3: RAMS Bit 2: RAM2 Bit 1: RAM1 Bit 0: RAM0 H'FFFF8000 to H'FFFF8FFF 0 * * * H'00000000 to H'00000FFF 1 0 0 0 H'00001000 to H'00001FFF 1 0 0 1 H'00002000 to H'00002FFF 1 0 1 0 H'00003000 to H'00003FFF 1 0 1 1 H'00004000 to H'00004FFF 1 1 0 0 H'00005000 to H'00005FFF 1 1 0 1 H'00006000 to H'00006FFF 1 1 1 0 H'00007000 to H'00007FFF 1 1 1 1 *: Don’t care 129 8.3 Accessing External Space A strobe signal is output in external space accesses to provide primarily for SRAM or ROM direct connections. 8.3.1 Basic Timing Figure 8.3 shows the basic timing of external space access. External access bus cycles are performed in 2 states. T1 T2 CK Address CSn RD Read Data WRH, WRL Write Data Figure 8.3 Basic Timing of External Space Access 130 8.3.2 Wait State Control The number of wait states inserted into external space access states can be controlled using the WCR settings (figure 8.4). The specified number of TW cycles are inserted as software cycles at the timing shown in figure 8.4. T1 TW T2 CK Address CSn RD Read Data WRH, WRL Write Data Figure 8.4 Wait State Timing of External Space Access (Software Wait Only) 131 When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 8.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock rise one cycle before the clock rise when the Tw state shifts to the T 2 state. When using external waits, use a WCR setting of 1 state or more when extending CS assertion, and 2 states or more otherwise. T1 TW TW TW0 T2 CK Address CSn RD Read Data WRH, WRL Write Data WAIT Figure 8.5 Wait State Timing of External Space Access (Two Software Wait States + WAIT Signal Wait State) 132 8.3.3 CS Assert Period Extension Idle cycles can be inserted to prevent extension of the RD, WRH, or WRL signal assert period beyond the length of the CSn signal assert period by setting the SW3 to SW0 bits of BCR2. This allows for flexible interfaces with external circuitry. The timing is shown in figure 8.6. Th and T f cycles are added respectively before and after the ordinary cycle. Only CSn is asserted in these cycles; RD, WRH, and WRL signals are not. Further, data is extended up to the Tf cycle, which is effective for gate arrays and the like, which have slower write operations. Th T1 T2 Tf CK Address CSn RD Read Data WRH, WRL Write Data Figure 8.6 CS Assert Period Extension Function 133 8.4 Waits between Access Cycles When a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. If there is a data conflict during memory access, the problem can be solved by inserting a wait in the access cycle. To enable detection of bus cycle starts, waits can be inserted between access cycles during continuous accesses of the same CS space by negating the CSn signal once. 8.4.1 Prevention of Data Bus Conflicts For the two cases of write cycles after read cycles, and read cycles for a different area after read cycles, waits are inserted so that the number of idle cycles specified by the IW31 to IW00 bits of BCR2 occur. When idle cycles already exist between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles are inserted. Figure 8.7 shows an example of idles between cycles. In this example, one idle between CSn space cycles has been specified, so when a CSm space write immediately follows a CSn space read cycle, one idle cycle is inserted. T1 T2 Tidle T1 T2 CK Address CSn CSm RD WRH, WRL Data CSn space read Idle cycle CSm space write Figure 8.7 Idle Cycle Insertion Example 134 IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces, or for this chip, to perform write accesses. In the same manner, IW21 and IW20 specify the number of idle cycles after a CS2 space read, IW11 and IW10, the number after a CS1 space read, and IW01 and IW00, the number after a CS0 space read. 0 to 3 idle cycles can be specified. 8.4.2 Simplification of Bus Cycle Start Detection For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles designated by the CW3 to CW0 bits of BCR2 occur. However, for write cycles after reads, the number of idle cycles inserted will be the larger of the two values defined by the IW and CW bits. When idle cycles already exist between access cycles, waits are not inserted. Figure 8.8 shows an example. A continuous access idle is specified for CSn space, and CSn space is consecutively write-accessed. T1 T2 Tidle T1 T2 CK Address CSn RD WRH, WRL Data CSn space access Idle cycle CSn space access Figure 8.8 Same Space Consecutive Access Idle Cycle Insertion Example 135 8.5 Bus Arbitration The SH7052F/SH7053F/SH7054F has a bus arbitration function that, when a bus release request is received from an external device, releases the bus to that device. The SH7052F/SH7053F/SH7054F also has three internal bus masters, the CPU, DMAC, and AUD. The priority ranking for determining bus right transfer between these bus masters is: Bus right request from external device > AUD > DMAC > CPU Therefore, an external device that generates a bus request is given priority even if the request is made during a DMAC burst transfer. The AUD does not acquire the bus during DMAC burst transfer, but at the end of the transfer. When the CPU has possession of the bus, the AUD has higher priority than the DMAC for bus acquisition. A bus request by an external device should be input at the BREQ pin. The signal indicating that the bus has been released is output from the BACK pin. Figure 8.9 shows the bus right release procedure. SH7052F, SH7053F, SH7054F BREQ accepted External device BREQ = Low Bus right request Strobe pin: high-level output Address, data, strobe pin: high impedance Bus right release response Bus right release status BACK confirmation BACK = Low Bus right acquisition Figure 8.9 Bus Right Release Procedure 136 8.6 Memory Connection Examples Figures 8.10 to 8.13 show examples of the memory connections. SH7052F, SH7053F, SH7054F 32 k × 8-bit ROM CSn CE RD OE A0 to A14 D0 to D7 A0 to A14 I/O0 to I/O7 Figure 8.10 Example of 8-Bit Data Bus Width ROM Connection SH7052F, SH7053F, SH7054F 256 k × 16-bit ROM CSn CE RD OE A0 A1 to A18 A0 to A17 D0 to D15 I/O0 to I/O15 Figure 8.11 Example of 16-Bit Data Bus Width ROM Connection SH7052F, SH7053F, SH7054F 128 k × 8-bit SRAM CSn CE RD OE A0 to A16 WRL D0 to D7 A0 to A16 WE I/O0 to I/O7 Figure 8.12 Example of 8-Bit Data Bus Width SRAM Connection 137 SH7052F, SH7053F, SH7054F CSn RD A0 A1 to A17 WRH D8 to D15 128 k × 8-bit SRAM CS OE A0 to A16 WE I/O0 to I/O7 WRL D0 to D7 CS OE A0 to A16 WE I/O0 to I/O7 Figure 8.13 Example of 16-Bit Data Bus Width SRAM Connection 138 Section 9 Direct Memory Access Controller (DMAC) 9.1 Overview The SH7052F/SH7053F/SH7054F includes an on-chip four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external memories, memory-mapped external devices, and on-chip peripheral modules (except for the DMAC, BSC, and UBC). Using the DMAC reduces the burden on the CPU and increases the operating efficiency of the chip as a whole. 9.1.1 Features The DMAC has the following features: • • • • • Four channels 4-Gbyte address space in the architecture 8-, 16-, or 32-bit selectable data transfer length Maximum of 16 M (6,777,216) transfers Address modes Both the transfer source and transfer destination are accessed by address. There are two transfer modes: direct address and indirect address. Direct address transfer mode: Values set in a DMAC internal register indicate the accessed address for both the transfer source and transfer destination. Two bus cycles are required for one data transfer. Indirect address transfer mode: The value stored at the location pointed to by the address set in the DMAC internal transfer source register is used as the address. Operation is otherwise the same as for direct access. This function can only be set for channel 3. Four bus cycles are required for one data transfer. • Channel function: Dual address mode is supported on all channels. Channel 2 has a source address reload function that reloads the source address every fourth transfer. Direct address transfer mode or indirect address transfer mode can be specified for channel 3. • Reload function Enables automatic reloading of the value set in the first source address register every fourth DMA transfer. This function can be executed on channel 2 only. • Transfer requests There are two DMAC transfer activation requests, as indicated below. Requests from on-chip peripheral modules: Transfer requests from on-chip modules such as the SCI or A/D. These can be received by all channels. Auto-request: The transfer request is generated automatically within the DMAC. 139 • Selectable bus modes: Cycle-steal mode or burst mode • Fixed DMAC channel priority ranking • CPU can be interrupted when the specified number of data transfers are complete. 9.1.2 Block Diagram Figure 9.1 is a block diagram of the DMAC. DMAC module Circuit control SARn On-chip RAM Register control DARn Peripheral bus On-chip peripheral module Internal bus On-chip ROM DMATCRn Activation control CHCRn DMAOR HCAN ATU-II SCI0 to SCI4 A/D converter 0, 1 DEIn Request priority control External ROM External I/O (memory mapped) External bus External RAM Bus interface Bus state controller SARn: DARn: DMATCRn: CHCRn: DMAOR: n: DMAC source address register DMAC destination address register DMAC transfer count register DMAC channel control register DMAC operation register 0, 1, 2, 3 Figure 9.1 DMAC Block Diagram 140 9.1.3 Register Configuration Table 9.1 summarizes the DMAC registers. The DMAC has a total of 17 registers. Each channel has four registers, and one overall DMAC control register is shared by all channels. Table 9.1 DMAC Registers Channel Name Abbr. R/W Initial Value Address 0 DMA source address register 0 SAR0 R/W Undefined H'FFFFECC0 32 bits 16, 32* 2 DMA destination address register 0 DAR0 R/W Undefined H'FFFFECC4 32 bits 16, 32* 2 DMA transfer count register 0 DMATCR0 R/W Undefined H'FFFFECC8 32 bits 16, 32* 2 DMA channel control register 0 CHCR0 R/W*1 H'00000000 H'FFFFECCC 32 bits 16, 32* 2 DMA source address register 1 SAR1 R/W Undefined H'FFFFECD0 32 bits 16, 32* 2 DMA destination address register 1 DAR1 R/W Undefined H'FFFFECD4 32 bits 16, 32* 2 DMA transfer count register 1 DMATCR1 R/W Undefined H'FFFFECD8 32 bits 16, 32* 3 DMA channel control register 1 CHCR1 R/W*1 H'00000000 H'FFFFECDC 32 bits 16, 32* 2 DMA source address register 2 SAR2 R/W Undefined H'FFFFECE0 32 bits 16, 32* 2 DMA destination address register 2 DAR2 R/W Undefined H'FFFFECE4 32 bits 16, 32* 2 DMA transfer count register 2 DMATCR2 R/W Undefined H'FFFFECE8 32 bits 16, 32* 3 DMA channel control register 2 CHCR2 R/W*1 H'00000000 H'FFFFECEC 32 bits 16, 32* 2 1 2 Register Access Size Size 141 Table 9.1 DMAC Registers (cont) Channel Name Abbr. R/W Initial Value Address 3 DMA source address register 3 SAR3 R/W Undefined H'FFFFECF0 32 bits 16, 32* 2 DMA destination address register 3 DAR3 R/W Undefined H'FFFFECF4 32 bits 16, 32* 2 DMA transfer count register 3 DMATCR3 R/W Undefined H'FFFFECF8 32 bits 16, 32* 3 DMA channel control register 3 CHCR3 R/W*1 H'00000000 H'FFFFECFC 32 bits 16, 32* 2 DMA operation register DMAOR R/W*1 H'0000 16* 4 Shared Register Access Size Size H'FFFFECB0 16 bits Notes: Word access to a register takes 3 cycles, and longword access 6 cycles. 1. Write 0 after reading 1 in bit 1 of CHCR0 to CHCR3 and in bits 1 and 2 of DMAOR to clear flags. No other writes are allowed. 2. For 16-bit access of SAR0 to SAR3, DAR0 to DAR3, and CHCR0 to CHCR3, the 16-bit value on the side not accessed is held. 3. DMATCR has a 24-bit configuration: bits 0 to 23. Writing to the upper 8 bits (bits 24 to 31) is invalid, and these bits always read 0. 4. Do not use 32-bit access on DMAOR. 5. Do not attempt to access an empty address, as operation canot be guaranteed if this is done. 9.2 Register Descriptions 9.2.1 DMA Source Address Registers 0 to 3 (SAR0 to SAR3) DMA source address registers 0 to 3 (SAR0 to SAR3) are 32-bit readable/writable registers that specify the source address of a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next source address. Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set. The initial value after a power-on reset and in standby mode is undefined. 142 Bit: 31 30 29 28 27 26 25 24 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 … … 2 1 0 … … R/W: Bit: Initial value: R/W: 9.2.2 — — — … … — — — R/W R/W R/W … … R/W R/W R/W DMA Destination Address Registers 0 to 3 (DAR0 to DAR3) DMA destination address registers 0 to 3 (DAR0 to DAR3) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next destination address. Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set. The value after a power-on reset and in standby mode is undefined. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 … … 2 1 0 … … — — — … … — — — R/W R/W R/W … … R/W R/W R/W 143 9.2.3 DMA Transfer Count Registers 0 to 3 (DMATCR0 to DMATCR3) DMA transfer count registers 0 to 3 (DMATCR0 to DMATCR3) are 24-bit read/write registers that specify the transfer count for the channel (byte count, word count, or longword count) in bits 23 to 0. Specifying H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 16,777,216 transfers. During DMAC operation, these registers indicate the remaining number of transfers. The upper 8 bits of DMATCR always read 0. The write value, also, should always be 0. The value after a power-on reset and in standby mode is undefined. Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R/W: R/W: Bit: Initial value: R/W: 144 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 9.2.4 DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3) DMA channel control registers 0 to 3 (CHCR0 to CHCR3) are 32-bit readable/writable registers that designate the operation and transmission of each channel. CHCR register bits are initialized to 0 by a power-on reset and in standby mode. Bit: Initial value: 31 30 29 28 27 26 25 24 — — — DI — — — RO 0 0 0 0 0 0 0 0 R R R R/W*2 2 R/W: R R R R/W* Bit: 23 22 21 20 19 18 17 16 — — — RS4 RS3 RS2 RS1 RS0 0 0 0 0 0 0 0 Initial value: 0 1 R/W: R R R R/W R/W R/W R/W* R/W Bit: 15 14 13 12 11 10 9 8 — — SM1 SM0 — — DM1 DM0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R R R/W R/W Bit: 7 6 5 4 3 2 1 0 — — TS1 TS0 TM IE TE DE Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/(W)*1 R/W Notes: 1. TE bit: Allows only a 0 write after reading 1. 2. The DI and RO bits may be absent, depending on the channel. 145 • Bits 31 to 29, 27 to 25, 23 to 21, 15, 14, 11, 10, 7, 6—Reserved: These bits are always read as 0, and should only be written with 0. • Bit 28—Direct/Indirect Select (DI): Specifies either direct address mode operation or indirect address mode operation for the channel 3 source address. This bit is valid only in CHCR3. It always reads 0 in CHCR0 to CHCR2, and should always be written with 0. Bit 28: DI Description 0 Direct access mode operation for channel 3 1 Indirect access mode operation for channel 3 (Initial value) • Bit 24—Source Address Reload (RO): Selects whether to reload the source address initial value during channel 2 transfer. This bit is valid only for channel 2. It always reads 0 in CHCR0, CHCR1, and CHCR3, and should always be written with 0. Bit 24: RO Description 0 Does not reload source address 1 Reloads source address 146 (Initial value) • Bits 20 to 16—Resource Select 4 to 0 (RS4 to RS0): These bits specify the transfer request source. Bit 20: RS4 Bit 19: RS3 Bit 18: RS2 Bit 17: RS1 Bit 16: RS0 Description 0 0 0 0 0 No request (Initial value) 1 SCI0 transmission 0 SCI0 reception 1 SCI1 transmission 0 SCI1 reception 1 SCI2 transmission 0 SCI2 reception 1 SCI3 transmission 0 SCI3 reception 1 SCI4 transmission 0 SCI4 reception 1 On-chip A/D0 0 On-chip A/D1 1 No request 0 No request 1 HCAN (RM) 0 No request 1 ATU-II (ICI0A) 0 ATU-II (ICI0B) 1 ATU-II (ICI0C) 0 ATU-II (ICI0D) 1 ATU-II (CMI6A) 0 ATU-II (CMI6B) 1 ATU-II (CMI6C) 0 ATU-II (CMI6D) 1 ATU-II (CMI7A) 0 ATU-II (CMI7B) 1 ATU-II (CMI7C) 0 ATU-II (CMI7D) 1 No request 0 No request 1 Auto-request 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 147 • Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify increment/decrement of the DMA transfer source address. Bit 13: SM1 Bit 12: SM0 Description 0 0 Source address fixed 0 1 Source address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) 1 0 Source address decremented (–1 during 8-bit transfer, –2 during 16-bit transfer, –4 during 32-bit transfer) 1 1 Setting prohibited (Initial value) When the transfer source is specified at an indirect address, specify in source address register 3 (SAR3) the actual storage address of the data to be transferred as the data storage address (indirect address). During indirect address mode, SAR3 obeys the SM1/SM0 setting for increment/decrement. In this case, SAR3’s increment/decrement is fixed at +4/–4 or 0, irrespective of the transfer data size specified by TS1 and TS0. • Bits 9 and 8—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify increment/decrement of the DMA transfer source address. Bit 9: DM1 Bit 8: DM0 Description 0 0 Destination address fixed 0 1 Destination address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) 1 0 Destination address decremented (–1 during 8-bit transfer, –2 during 16-bit transfer, –4 during 32-bit transfer) 1 1 Setting prohibited (Initial value) • Bits 5 and 4—Transfer Size 1 and 0 (TS1, TS0): These bits specify the size of the data for transfer. Bit 5: TS1 Bit 4: TS0 Description 0 0 Specifies byte size (8 bits) 0 1 Specifies word size (16 bits) 1 0 Specifies longword size (32 bits) 1 1 Setting prohibited 148 (Initial value) • Bit 3—Transfer Mode (TM): Specifies the bus mode for data transfer. Bit 3: TM Description 0 Cycle-steal mode 1 Burst mode (Initial value) • Bit 2—Interrupt Enable (IE): When this bit is set to 1, interrupt requests are generated after the number of data transfers specified in DMATCR (when TE = 1). Bit 2: IE Description 0 Interrupt request not generated on completion of DMATCR-specified number of transfers (Initial value) 1 Interrupt request enabled on completion of DMATCR-specified number of transfers • Bit 1—Transfer End (TE): This bit is set to 1 after the number of data transfers specified by DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI or address error, or clearing of the DE bit or DME bit of DMAOR) TE is not set to 1. With this bit set to 1, data transfer is disabled even if the DE bit is set to 1. Bit 1: TE Description 0 DMATCR-specified number of transfers not completed (Initial value) [Clearing condition] 0 write after TE = 1 read, power-on reset, standby mode 1 DMATCR-specified number of transfers completed • Bit 0—DMAC Enable (DE): DE enables operation in the corresponding channel. Bit 0: DE Description 0 Operation of the corresponding channel disabled 1 Operation of the corresponding channel enabled (Initial value) Transfer is initiated if this bit is set to 1 when auto-request is specified (RS4 to RS0 settings). With an on-chip module request, when a transfer request occurs after this bit is set to 1, transfer is initiated. If this bit is cleared during a data transfer, transfer is suspended. If the DE bit has been set, but TE = 1, then if the DME bit of DMAOR is 0, and the NMIF or AE bit of DMAOR is 1, the transfer enable state is not entered. 149 9.2.5 DMAC Operation Register (DMAOR) DMAOR is a 16-bit readable/writable register that controls the overall operation of the DMAC. Register values are initialized to 0 by a power-on reset and in standby mode. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — AE NMIF DME Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/(W)* R/(W)* R/W Note: * A 0 write only is valid after 1 is read at the AE and NMIF bits. • Bits 15 to 3—Reserved: These bits are always read 0 and should always be written with 0. • Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU cannot write a 1 to the AE bit. Clearing is effected by a 0 write after a 1 read. Bit 2: AE Description 0 No address error, DMA transfer enabled [Clearing condition] Write AE = 0 after reading AE = 1 1 Address error, DMA transfer disabled [Setting condition] Address error due to DMAC 150 (Initial value) • Bit 1—NMI Flag (NMIF): Indicates input of an NMI. This bit is set irrespective of whether the DMAC is operating or suspended. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU is unable to write a 1 to the NMIF. Clearing is effected by a 0 write after a 1 read. Bit 1: NMIF Description 0 No NMI interrupt, DMA transfer enabled (Initial value) [Clearing condition] Write NMIF = 0 after reading NMIF = 1 1 NMI has occurred, DMC transfer disabled [Setting condition] NMI interrupt occurrence • Bit 0—DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When the DME bit and DE bit of the CHCR register for the corresponding channel are set to 1, that channel is transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels are suspended. Even when the DME bit is set, when the TE bit of CHCR is 1, or its DE bit is 0, transfer is disabled if the NMIF or AE bit in DMAOR is set to 1. Bit 0: DME Description 0 Operation disabled on all channels 1 Operation enabled on all channels (Initial value) 151 9.3 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in two modes: auto-request and on-chip peripheral module request. Transfer is performed only in dual address mode, and either direct or indirect address transfer mode can be used. The bus mode can be either burst or cycle-steal. 9.3.1 DMA Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count register (DMATCR), DMA channel control registers (CHCR), and DMA operation register (DMAOR) are set to the desired transfer conditions, the DMAC transfers data according to the following procedure: 1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). 2. When a transfer request comes and transfer has been enabled, the DMAC transfers 1 transfer unit of data (determined by the TS0 and TS1 setting). For an auto-request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented by 1 upon each transfer. The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfers have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit of CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is aborted. Transfer is also aborted when the DE bit of CHCR or the DME bit of DMAOR is cleared to 0. 152 Figure 9.2 is a flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and NMIF, AE, TE = 0? No Yes Transfer request occurs?*1 No *2 *3 Yes Bus mode Transfer (1 transfer unit); DMATCR – 1 → DMATCR, SAR and DAR updated DMATCR = 0? No Yes DEI interrupt request (when IE = 1) Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes Transfer ends Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes No Transfer aborted No Normal end Notes: 1. In auto-request mode, transfer begins when NMIF, AE, and TE are all 0, and the DE and DME bits are set to 1. 2. Cycle-steal mode 3. Burst mode Figure 9.2 DMAC Transfer Flowchart 153 9.3.2 DMA Transfer Requests DMA transfer requests are generated in either the data transfer source or destination. Transfers can be requested in two modes: auto-request and on-chip peripheral module request. The request mode is selected in the RS4 to RS0 bits of DMA channel control registers 0 to 3 (CHCR0 to CHCR3). Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits of CHCR0 to CHCR3 and the DME bit of DMAOR are set to 1, the transfer begins (so long as the TE bits of CHCR0 to CHCR3 and the NMIF and AE bits of DMAOR are all 0). On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 9.2, there are 26 transfer request signals: 12 from the advanced timer unit (ATU-II), which are compare match or input capture interrupts; the receive data full interrupts (RXI) and transmit data empty interrupts (TXI) of the five serial communication interfaces (SCI); the receive interrupt of HCAN; and the A/D conversion end interrupts (ADI) of the three A/D converters. When DMA transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. When the transfer request is set to RXI (transfer request because the SCI’s receive data register is full), the transfer source must be the SCI’s receive data register (RDR). When the transfer request is set to TXI (transfer request because the SCI’s transmit data register is empty), the transfer destination must be the SCI’s transmit data register (TDR). If the transfer request is set to the A/D converter, the data transfer source must be the A/D converter register; if set to HCAN, the transfer source must be HCAN message data. 154 Table 9.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits DMAC Transfer Request Source DMAC Transfer Request Signal Transfer Source Transfer Destination RS4 RS3 RS2 RS1 RS0 0 0 0 0 1 SCI0 transmit block TXI0 (SCI0 transmitdata-empty transfer request) Don’t care* TDR0 Burst/cyclesteal 1 0 SCI0 receive block RXI0 (SCI0 receivedata-full transfer request) RDR0 Don’t care* Burst/cyclesteal 1 SCI1 transmit block TXI1 (SCI1 transmitdata-empty transfer request) Don’t care* TDR1 Burst/cyclesteal 0 SCI1 receive block RXI1 (SCI1 receivedata-full transfer request) RDR1 Don’t care* Burst/cyclesteal 1 SCI2 transmit block TXI2 (SCI2 transmitdata-empty transfer request) Don’t care* TDR2 Burst/cyclesteal 0 SCI2 receive block RXI2 (SCI2 receivedata-full transfer request) RDR2 Don’t care* Burst/cyclesteal 1 SCI3 transmit block TXI3 (SCI3 transmitdata-empty transfer request) Don’t care* TDR3 Burst/cyclesteal 0 SCI3 receive block RXI3 (SCI3 receivedata-full transfer request) RDR3 Don’t care* Burst/cyclesteal 1 SCI4 transmit block TXI4 (SCI4 transmitdata-empty transfer request) Don’t care* TDR4 Burst/cyclesteal 0 SCI4 receive block RXI4 (SCI4 receivedata-full transfer request) RDR4 Don’t care* Burst/cyclesteal 1 A/D0 ADI0 (A/D0 conversion end interrupt) ADDR0 to ADDR11 Don’t care* Burst/cyclesteal 0 A/D1 ADI1 (A/D1 conversion end interrupt) ADDR12 to ADDR23 Don’t care* Burst/cyclesteal 1 Reserved 1 HCAN RM0 (HCAN receive interrupt) MD0 to MD15 Don’t care* Burst/cyclesteal 1 0 1 1 0 0 1 1 0 1 Bus Mode 155 Table 9.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits (cont) RS4 RS3 RS2 RS1 RS0 DMAC Transfer Request Source 1 0 0 0 1 1 1 0 1 1 0 0 1 1 0 DMAC Transfer Request Signal Transfer Source Transfer Destination ATU-II ICI0A (ICR0A input capture generation) Don’t care* Don’t care* Burst/cyclesteal 0 ATU-II ICI0B (ICR0B input capture generation) Don’t care* Don’t care* Burst/cyclesteal 1 ATU-II ICI0C (ICR0C input capture generation) Don’t care* Don’t care* Burst/cyclesteal 0 ATU-II ICI0D (ICR0D input capture generation) Don’t care* Don’t care* Burst/cyclesteal 1 ATU-II CMI6A (CYLR6A compare-match generation) Don’t care* Don’t care* Burst/cyclesteal 0 ATU-II CMI6B (CYLR6B compare-match generation) Don’t care* Don’t care* Burst/cyclesteal 1 ATU-II CMI6C (CYLR6C compare-match generation) Don’t care* Don’t care* Burst/cyclesteal 0 ATU-II CMI6D (CYLR6D compare-match generation) Don’t care* Don’t care* Burst/cyclesteal 1 ATU-II CMI7A (CYLR7A compare-match generation) Don’t care* Don’t care* Burst/cyclesteal 0 ATU-II CMI7B (CYLR7B compare-match generation) Don’t care* Don’t care* Burst/cyclesteal 1 ATU-II CMI7C (CYLR7C compare-match generation) Don’t care* Don’t care* Burst/cyclesteal 0 ATU-II CMI7D (CYLR7D compare-match generation) Don’t care* Don’t care* Burst/cyclesteal Legend: SCI0, SCI1, SCI2, SCI3, SCI4: A/D0, A/D1: HCAN: ATU-II: TDR0, TDR1, TDR2, TDR3, TDR4: RDR0, RDR1, RDR2, RDR3, RDR4: ADDR0 to ADDR11: 156 Serial communication interface channels 0 to 4 A/D converter channels 0, 1 Hitachi controller area network channel 0 Advanced timer unit SCI0 to SCI4 transmit data registers SCI0 to SCI4 receive data registers A/D0 data registers Bus Mode ADDR12 to ADDR23: MD0 to MD15: A/D1 data registers HCAN message data Note: * External memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding DMAC, BSC, and UBC) 9.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to the following priority order: • CH0 > CH1 > CH2 > CH3 9.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 9.3. It operates in dual address mode, in which both the transfer source and destination addresses are output. The dual address mode consists of a direct address mode, in which the output address value is the object of a direct data transfer, and an indirect address mode, in which the output address value is not the object of the data transfer, but the value stored at the output address becomes the transfer object address. The actual transfer operation timing varies with the bus mode. The DMAC has two bus modes: cycle-steal mode and burst mode. Table 9.3 Supported DMA Transfers Transfer Destination Transfer Source External Memory Memory-Mapped External Device On-Chip Memory On-Chip Peripheral Module External memory Supported Supported Supported Supported Memory-mapped external device Supported Supported Supported Supported On-chip memory Supported Supported Supported Supported On-chip peripheral module Supported Supported Supported Supported 9.3.5 Dual Address Mode Dual address mode is used for access of both the transfer source and destination by address. Transfer source and destination can be accessed either internally or externally. Dual address mode is subdivided into two other modes: direct address transfer mode and indirect address transfer mode. 157 Direct Address Transfer Mode: Data is read from the transfer source during the data read cycle, and written to the transfer destination during the write cycle, so transfer is conducted in two bus cycles. At this time, the transfer data is temporarily stored in the DMAC. With the kind of external memory transfer shown in figure 9.3, data is read from one of the memories by the DMAC during a read cycle, then written to the other external memory during the subsequent write cycle. Figure 9.4 shows the timing for this operation. 1st bus cycle DMAC SAR Data bus Address bus DAR Memory Transfer source module Transfer destination module Data buffer The SAR value is taken as the address, and data is read from the transfer source module and stored temporarily in the DMAC. 2nd bus cycle DMAC SAR Data buffer Data bus Address bus DAR Memory Transfer source module Transfer destination module The DAR value is taken as the address, and data stored in the DMAC's data buffer is written to the transfer destination module. Figure 9.3 Direct Address Operation in Dual Address Mode 158 CK A21 to A0 Transfer source address Transfer destination address CSn D15 to D0 RD WRH, WRL Figure 9.4 Direct Address Transfer Timing in Dual Address Mode Indirect Address Transfer Mode: In this mode the memory address storing the data actually to be transferred is specified in the DMAC internal transfer source address register (SAR3). Therefore, in indirect address transfer mode, the DMAC internal transfer source address register value is read first. This value is first stored in the DMAC. Next, the read value is output as the address, and the value stored at that address is again stored in the DMAC. Finally, the subsequent read value is written to the address specified by the transfer destination address register, ending one cycle of DMAC transfer. In indirect address mode (figure 9.5), the transfer destination, transfer source, and indirect address storage destination are all 16-bit external memory locations, and transfer in this example is conducted in 16-bit or 8-bit units. Timing for this transfer example is shown in figure 9.6. In indirect address mode, one NOP cycle (figure 9.6) is required until the data read as the indirect address is output to the address bus. When transfer data is 32-bit, the third and fourth bus cycles each need to be doubled, giving a required total of six bus cycles and one NOP cycle for the whole operation. 159 1st and 2nd bus cycles DMAC SAR3 Data bus Temporary buffer Address bus DAR3 Memory Transfer source module Transfer destination module Data buffer The SAR3 value is taken as the address, memory data is read, and the value is stored in the temporary buffer. Since the value read at this time is used as the address, it must be 32 bits. If the data bus is 16 bits wide when the external memory space is accessed, two bus cycles are necessary. 3rd bus cycle DMAC SAR3 Data bus Temporary buffer Address bus DAR3 Memory Data buffer Transfer source module Transfer destination module The value in the temporary buffer is taken as the address, and data is read from the transfer source module to the data buffer. 4th bus cycle DMAC SAR3 Data buffer Data bus Temporary buffer Address bus DAR3 Memory Transfer source module Transfer destination module The DAR3 value is taken as the address, and the value in the data buffer is written to the transfer destination module. Note: Memory, transfer source, and transfer destination modules are shown here. In practice, connection can be made as long as it is within the address space. Figure 9.5 Dual Address Mode and Indirect Address Operation (16-Bit-Width External Memory Space) 160 External memory space → External memory space (External memory space has 16-bit width) CK A21 to A0 Transfer source address (H) Transfer source address (L) NOP Transfer destination address Indirect address CSn D15 to D0 Internal address bus Indirect address (H) Transfer source address*1 Internal data bus Transfer data Indirect address (L) Transfer data Indirect address NOP Indirect address Transfer data Transfer data *2 DMAC indirect address buffer Indirect address DMAC data buffer Transfer data RD WRH, WRL Address read cycle (1st) (2nd) NOP cycle Data read cycle (3rd) Data write cycle (4th) Notes: 1. The internal address bus is controlled by the port and does not change. 2. The DMAC does not latch the value until 32-bit data is read from the internal data bus. Figure 9.6 Dual Address Mode and Indirect Address Transfer Timing Example 1 161 Figure 9.7 shows an example of timing in indirect address mode when transfer source and indirect address storage locations are in internal memory, the transfer destination is an on-chip peripheral module with 2-cycle access space, and transfer data is 8-bit. Since the indirect address storage destination and the transfer source are in internal memory, these can be accessed in one cycle. The transfer destination is 2-cycle access space, so two data write cycles are required. One NOP cycle is required until the data read as the indirect address is output to the address bus. Internal memory space → Internal memory space CK Internal address bus Internal data bus Transfer source address NOP Indirect address Transfer destination address Indirect address NOP Transfer data DMAC indirect address buffer Transfer data Indirect address DMAC data buffer Transfer data Address read cycle (1st) NOP cycle (2nd) Data read cycle (3rd) Data write cycle (4th) Figure 9.7 Dual Address Mode and Indirect Address Transfer Timing Example 2 162 9.3.6 Bus Modes Select the appropriate bus mode in the TM bits of CHCR0 to CHCR3. There are two bus modes: cycle-steal and burst. Cycle-Steal Mode: In cycle-steal mode, the bus right is given to another bus master after each one-transfer-unit (8-bit, 16-bit, or 32-bit) DMAC transfer. When the next transfer request occurs, the bus right is obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. Cycle-steal mode can be used with all categories of transfer destination, transfer source and transfer request. Figure 9.8 shows an example of DMA transfer timing in cycle-steal mode. Bus control returned to CPU Bus cycle CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU Read/Write Read/Write CPU Figure 9.8 DMA Transfer Timing Example in Cycle-Steal Mode Burst Mode: Once the bus right is obtained, transfer is performed continuously until the transfer end condition is satisfied. Figure 9.9 shows an example of DMA transfer timing in burst mode. Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC Read/Write Read/Write CPU Read/Write Figure 9.9 DMA Transfer Timing Example in Burst Mode 163 9.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 9.4 shows the relationship between request modes and bus modes by DMA transfer category. Table 9.4 Relationship between Request Modes and Bus Modes by DMA Transfer Category Bus*5 Mode Transfer Usable Size (Bits) Channels External memory and external memory Any*1 B/C 8/16/32 0 to 3 1 B/C 8/16/32 0 to 3 Memory-mapped external device and memory-mapped external device Any*1 B/C 8/16/32 0 to 3 External memory and on-chip memory Any*1 B/C Address Mode Transfer Category Dual Request Mode External memory and memory-mapped Any* external device 2 Any* Memory-mapped external device and on-chip memory Any*1 B/C 8/16/32 0 to 3 Memory-mapped external device and on-chip peripheral module Any*2 B/C* 3 8/16/32* 4 0 to 3 On-chip memory and on-chip memory Any*1 B/C 8/16/32 0 to 3 On-chip memory and on-chip peripheral module Any* On-chip peripheral module and onchip peripheral module Any*2 B/C* 3 B/C* 3 8/16/32* 0 to 3 4 External memory and on-chip peripheral module 2 B/C* 8/16/32 3 0 to 3 4 0 to 3 8/16/32* 4 0 to 3 8/16/32* B: Burst, C: Cycle-steal Notes: 1. Auto-request or on-chip peripheral module request enabled. However, in the case of an on-chip peripheral module request, it is not possible to specify the ATU, SCI, HCAN, or A/D converter for the transfer request source. 2. Auto-request or on-chip peripheral module request possible. However, if the transfer request source is the SCI, HCAN, or A/D converter, the transfer source or transfer destination must be same as the transfer request source. 3. When the transfer request source is the SCI, only cycle-steal mode is possible. 4. Access size permitted by the on-chip peripheral module register that is the transfer source or transfer destination. 164 9.3.8 Bus Mode and Channel Priorities If, for example, a transfer request is issued for channel 0 while transfer is in progress on lowerpriority channel 1 in burst mode, transfer is started immediately on channel 0. In this case, if channel 0 is set to burst mode, channel 1 transfer is continued after completion of all transfers on channel 0. If channel 0 is set to cycle-steal mode, channel 1 transfer is continued only if a channel 0 transfer request has not been issued; if a transfer request is issued, channel 0 transfer is started immediately. 9.3.9 Source Address Reload Function Channel 2 has a source address reload function. This returns to the first value set in the source address register (SAR2) every four transfers by setting the RO bit of CHCR2 to 1. Figure 9.10 illustrates this operation. Figure 9.11 is a timing chart for reload ON mode, with burst mode, autorequest, 16-bit transfer data size, SAR2 increment, and DAR2 fixed. DMAC DMAC control block RO bit = 1 Reload control Reload signal DMATCR2 SAR2 (initial value) Reload signal 4th count Address bus Count signal Transfer request CHCR2 SAR2 Figure 9.10 Source Address Reload Function 165 CK Internal address bus Internal data bus SAR2 DAR2 SAR2+2 SAR2 data DAR2 SAR2+4 SAR2+2 data DAR2 SAR2+6 DAR2 SAR2+4 data SAR2 SAR2+6 data DAR2 SAR2 data 1st channel 2 transfer 2nd channel 2 transfer 3rd channel 2 transfer 4th channel 2 transfer 5th channel 2 transfer SAR2 output DAR2 output SAR2+2 output DAR2 output SAR2+4 output DAR2 output SAR2+6 output DAR2 output SAR2 output DAR2 output After SAR2+6 output, SAR2 is reloaded Bus right is returned one time in four Figure 9.11 Source Address Reload Function Timing Chart The reload function can be executed whether the transfer data size is 8, 16, or 32 bits. DMATCR2, which specifies the number of transfers, is decremented by 1 at the end of every single-transfer-unit transfer, regardless of whether the reload function is on or off. Therefore, when using the reload function in the on state, a multiple of 4 must be specified in DMATCR2. Operation will not be guaranteed if any other value is set. Also, the counter which counts the occurrence of four transfers for address reloading is reset by clearing of the DME bit in DMAOR or the DE bit in CHCR2, setting of the transfer end flag (the TE bit in CHCR2), NMI input, and setting of the AE flag (address error generation in DMAC transfer), as well as by a reset and in software standby mode, but SAR2, DAR2, DMATCR2, and other registers are not reset. Consequently, when one of these sources occurs, there is a mixture of initialized counters and uninitialized registers in the DMAC, and incorrect operation may result if a restart is executed in this state. Therefore, when one of the above sources, other than TE setting, occurs during use of the address reload function, SAR, DAR2, and DMATCR2 settings must be carried out before reexecution. 9.3.10 DMA Transfer Ending Conditions The DMA transfer ending conditions vary for individual channels ending and for all channels ending together. Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel’s DMA transfer count register (DMATCR) is 0, or when the DE bit of the channel’s CHCR is cleared to 0. 166 • When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's DMA transfer ends, the transfer end flag bit (TE) is set in CHCR. If the IE (interrupt enable) bit has been set, a DMAC interrupt (DEI) request is sent to the CPU. • When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the channel’s CHCR. The TE bit is not set when this happens. Conditions for Ending on All Channels Simultaneously: Transfers on all channels end when the NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in DMAOR, or when the DME bit in DMAOR is cleared to 0. • When the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address error occurs, the NMIF or AE bit is set to 1 in DMAOR and all channels stop their transfers. The DMAC obtains the bus right, and if these flags are set to 1 during execution of a transfer, DMAC halts operation when the transfer processing currently being executed ends, and transfers the bus right to the other bus master. Consequently, even if the NMIF or AE bit is set to 1 during a transfer, the DMA source address register (SAR), designation address register (DAR), and transfer count register (DMATCR) are all updated. The TE bit is not set. To resume the transfers after NMI interrupt or address error processing, the NMIF or AE flag must be cleared. To avoid restarting a transfer on a particular channel, clear its DE bit to 0 in CHCR. When the processing of a one-unit transfer is complete: In a dual address mode direct address transfer, even if an address error occurs or the NMI flag is set during read processing, the transfer will not be halted until after completion of the following write processing. In such a case, SAR, DAR, and DMATCR values are updated. In the same manner, the transfer is not halted in indirect address transfers until after the final write processing has ended. • When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in DMAOR aborts the transfers on all channels. The TE bit is not set. 9.3.11 DMAC Access from CPU The space addressed by the DMAC is 3-cycle space. Therefore, when the CPU becomes the bus master and accesses the DMAC, a minimum of three basic clock cycles are required for one bus cycle. Also, since the DMAC is located in word space, while a word-size access to the DMAC is completed in one bus cycle, a longword-size access is automatically divided into two word accesses, requiring two bus cycles (six basic clock cycles). These two bus cycles are executed consecutively; a different bus cycle is never inserted between the two word accesses. This applies to both write accesses and read accesses. 167 9.4 Examples of Use 9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory In this example, on-chip serial communication interface channel 0 (SCI0) receive data is transferred to external memory using DMAC channel 0. Table 9.5 indicates the transfer conditions and the set values of each of the registers. Table 9.5 Transfer Conditions and Register Set Values for Transfer between On-chip SCI and External Memory Transfer Conditions Register Value Transfer source: RDR0 of on-chip SCI0 SAR0 H'FFFFF005 Transfer destination: external memory DAR0 H'00400000 Transfer count: 64 times DMATCR0 H'00000040 Transfer source address: fixed CHCR0 H'00020105 DMAOR H'0001 Transfer destination address: incremented Transfer request source: SCI0 (RDR0) Bus mode: cycle-steal Transfer unit: byte Interrupt request generation at end of transfer DMAC master enable on 9.4.2 Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On) In this example, on-chip A/D converter channel 0 is the transfer source and on-chip memory is the transfer destination, and the address reload function is on. Table 9.6 indicates the transfer conditions and the set values of each of the registers. 168 Table 9.6 Transfer Conditions and Register Set Values for Transfer between A/D Converter and On-Chip Memory Transfer Conditions Register Value Transfer source: on-chip A/D converter ch1 (A/D1) SAR2 H'FFFFF820 Transfer destination: on-chip memory DAR2 H'FFFF6000 Transfer count: 128 times (reload count 32 times) DMATCR2 H'00000080 Transfer source address: incremented CHCR2 H'010C110D DMAOR H'0001 Transfer destination address: incremented Transfer request source: A/D converter ch1 (A/D1) Bus mode: burst Transfer unit: byte Interrupt request generation at end of transfer DMAC master enable on When address reload is on, the SAR2 value returns to its initially set value every four transfers. In the above example, when a transfer request is input from the A/D1, the byte-size data is first read in from the H'FFFFF820 register of on-chip A/D1 and that data is written to internal address H'FFFF6000. Because a byte-size transfer was performed, the SAR2 and DAR2 values at this point are H'FFFFF821 and H'FFFF6001, respectively. Also, because this is a burst transfer, the bus right remains secured, so continuous data transfer is possible. When four transfers are completed, if address reload is off, execution continues with the fifth and sixth transfers and the SAR2 value continues to increment from H'FFFFF824 to H'FFFFF825 to H'FFFFF826 and so on. However, when address reload is on, DMAC transfer is halted upon completion of the fourth transfer and the bus right request signal to the CPU is cleared. At this time, the value stored in SAR2 is not H'FFFFF823 → H'FFFFF824, but H'FFFFF823 → H'FFFFF820, a return to the initially set address. The DAR2 value always continues to be decremented regardless of whether address reload is on or off. The DMAC internal status, due to the above operation after completion of the fourth transfer, is indicated in table 9.7 for both address reload on and off. 169 Table 9.7 DMAC Internal Status Item Address Reload On Address Reload Off SAR2 H'FFFFF820 H'FFFFF824 DAR2 H'FFFF6004 H'FFFF6004 DMATCR2 H'0000007C H'0000007C Bus right Released Retained DMAC operation Halted Processing continues Interrupts Not issued Not issued Transfer request source flag clear Executed Not executed Notes: 1. Interrupts are executed until the DMATCR2 value becomes 0, and if the IE bit of CHCR2 is set to 1, are issued regardless of whether address reload is on or off. 2. If transfer request source flag clears are executed until the DMATCR2 value becomes 0, they are executed regardless of whether address reload is on or off. 3. Designate burst mode when using the address reload function. There are cases where abnormal operation will result if it is used in cycle-steal mode. 4. Designate a multiple of four for the DMATCR2 value when using the address reload function. There are cases where abnormal operation will result if anything else is designated. To execute transfers after the fifth transfer when address reload is on, have the transfer request source issue another transfer request signal. 9.4.3 Example of DMA Transfer between External Memory and SCI1 Transmitting Side (Indirect Address On) In this example, DMAC channel 3 is used, indirect address designated external memory is the transfer source, and the SCI1 transmitting side is the transfer destination. Table 9.8 indicates the transfer conditions and the set values of each of the registers. 170 Table 9.8 Transfer Conditions and Register Set Values for Transfer between External Memory and SCI1 Transmitting Side Transfer Conditions Register Value Transfer source: external memory SAR3 H'00400000 Value stored in address H'00400000 — H'00450000 Value stored in address H'00450000 — H'55 Transfer destination: on-chip SCI TDR1 DAR3 H'FFFFF00B Transfer count: 10 times DMATCR3 H'0000000A Transfer source address: incremented CHCR3 H'10031001 DMAOR H'0001 Transfer destination address: fixed Transfer request source: SCI1 (TDR1) Bus mode: cycle-steal Transfer unit: byte Interrupt request not generated at end of transfer DMAC master enable on When indirect address mode is on, the data stored in the address set in SAR is not used as the transfer source data. In the case of indirect addressing, the value stored in the SAR address is read, then that value is used as the address and the data read from that address is used as the transfer source data, then that data is stored in the address designated by DAR. In the table 9.8 example, when a transfer request from TDR1 of SCI1 is generated, a read of the address located at H'00400000, which is the value set in SAR3, is performed first. The data H'00450000 is stored at this H'00400000 address, and the DMAC first reads this H'00450000 value. It then uses this read value of H'00450000 as an address and reads the value of H'55 that is stored in the H'00450000 address. It then writes the value H'55 to address H'FFFFF00B designated by DAR3 to complete one indirect address transfer. With indirect addressing, the first executed data read from the address set in SAR3 always results in a longword size transfer regardless of the TS0 and TS1 bit designations for transfer data size. However, the transfer source address fixed and increment or decrement designations are according to the SM0 and SM1 bits. Consequently, despite the fact that the transfer data size designation is byte in this example, the SAR3 value at the end of one transfer is H'00400004. The write operation is exactly the same as an ordinary dual address transfer write operation. 171 9.5 Usage Notes 1. Only word (16-bit) access can be used on the DMA operation register (DMAOR). All other registers can be accessed in word (16-bit) or longword (32-bit) units. 2. When rewriting the RS0 to RS4 bits of CHCR0 to CHCR3, first clear the DE bit to 0 (clear the DE bit to 0 before modifying CHCR). 3. When an NMI interrupt is input, the NMIF bit of DMAOR is set even when the DMAC is not operating. 4. Clear the DME bit of DMAOR to 0 and make certain that any transfer request processing accepted by the DMAC has been completed before entering standby mode. 5. Do not access the DMAC, BSC, or UBC on-chip peripheral modules from the DMAC. 6. When activating the DMAC, make the CHCR settings as the final step. Abnormal operation may result if any other registers are set last. 7. After the DMATCR count becomes 0 and the DMA transfer ends normally, always write 0 to DMATCR, even when executing the maximum number of transfers on the same channel. Abnormal operation may result if this is not done. 8. Designate burst mode as the transfer mode when using the address reload function. Abnormal operation may result in cycle-steal mode. 9. Designate a multiple of four for the DMATCR value when using the address reload function, otherwise abnormal operation may result. 10. Do not access empty DMAC register addresses. Operation cannot be guaranteed when empty addresses are accessed. 11. If DMAC transfer is aborted by NMIF or AE setting, or DME or DE clearing, during DMAC execution with address reload on, the SAR2, DAR2, and DMATCR2 settings should be made before re-executing the transfer. The DMAC may not operate correctly if this is not done. 12. Do not set the DE bit to 1 while bits RS0 to RS4 in CHCR0 to CHCR3 are still set to “no request.” 172 Section 10 Advanced Timer Unit-II (ATU-II) 10.1 Overview The SH7052F/SH7053F/SH7054F has an on-chip advanced timer unit-II (ATU-II) with one 32-bit timer channel and eleven 16-bit timer channels. 10.1.1 Features ATU-II features are summarized below. • Capability to process up to 63 pulse inputs and outputs • Prescaler Input clock to channels 0 and 10 scaled in 1 stage, input clock to channels 1 to 8 and 11 scaled in 2 stages 1/1 to 1/32 clock scaling possible in initial stage for all channels 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 scaling possible in second stage for channels 1 to 8 and 11 External clock TCLKA, TCLKB selection also possible for channels 1 to 5 and 11 • Channel 0 has four 32-bit input capture lines, allowing the following operations: Rising-edge, falling-edge, or both-edge detection selectable DMAC can be activated at capture timing Channel 10 compare-match signal can be captured as a trigger Interval interrupt generation function generates three interval interrupts as selected. CPU interruption or A/D converter (AD0, 1) activation possible Capture interrupt and counter overflow interrupt can be generated • Channel 1 has one 16-bit output compare register, eight general registers, and one dedicated input capture register. The output compare register can also be selected for one-shot pulse offset in combination with the channel 8 down-counter. General registers (GR1A to H) can be used as input capture or output compare registers Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output Input capture function: Rising-edge, falling-edge, or both-edge detection Channel 0 input signal (TI0A) can be captured as trigger Provision for forcible cutoff of channel 8 down-counters (DCNT8A to H) Compare-match interrupts/capture interrupts and counter overflow interrupts can be generated 173 • Channel 2 has eight 16-bit output compare registers, eight general registers, and one dedicated input capture register. The output compare registers can also be selected for one-shot pulse offset in combination with the channel 8 down-counter. General registers (GR2A to H) can be used as input capture or output compare registers Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output Input capture function: Rising-edge, falling-edge, or both-edge detection Channel 0 input signal (TI0A) can be captured as trigger Provision for forcible cutoff of channel 8 down-counters (DCNT8A to H) Compare-match interrupts/capture interrupts and counter overflow interrupts can be generated • Channels 3 to 5 each have four general registers, allowing the following operations: Selection of input capture, output compare, PWM mode Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output Input capture function: Rising-edge, falling-edge, or both-edge detection Channel 9 compare-match signal can be captured as trigger (channel 3 only) Compare-match interrupts/capture interrupts can be generated • Channels 6 and 7 have four 16-bit duty registers, four cycle registers, and four buffer registers, allowing the following operations: Any cycle and duty from 0 to 100% can be set Duty buffer register value transferred to duty register every cycle Interrupts can be generated every cycle Complementary PWM output can be set (channel 6 only) • Channel 8 has sixteen 16-bit down-counters for one-shot pulse output, allowing the following operations: One-shot pulse generation by down-counter Down-counter can be rewritten during count Interrupt can be generated at end of down-count Offset one-shot pulse function available Can be linked to channel 1 and 2 output compare functions • Channel 9 has six event counters and six output compare registers, allowing the following operations: Event counters can be cleared by compare-match Rising-edge, falling-edge, or both-edge detection available for external input Compare-match signal can be input to channel 3 174 • Channel 10 has a 32-bit output compare and input capture register, free-running counter, 16-bit free-running counter, output compare/input capture register, reload register, 8-bit event counter, and output compare register, and four 16-bit reload counters, allowing the following operations: Capture on external input pin edge input Reload count possible with 32, 64, 128, or 256 times the captured value Internal clock generated by reload counter underflow can be used as 16-bit free-running counter input Channel 1 and 2 free-running counter clearing capability • Channel 11 has one 16-bit free-running counter and two 16-bit general registers, allowing the following operations: Two general registers can be used for compare-match Compare-match signal can be output to APC • High-speed access to internal 16-bit bus High-speed access to 16-bit bus for 16-bit registers: timer counters, compare registers, and capture registers • 75 interrupt sources Four input capture interrupt requests, one overflow interrupt request, and one interval interrupt request for channel 0 Sixteen dual input capture/compare-match interrupt requests and two counter overflow interrupt requests for channels 1 and 2 Twelve dual input capture/compare-match interrupt requests and three overflow interrupt requests for channels 3 to 5 Eight compare-match interrupts for channels 6 and 7 Sixteen one-shot end interrupt requests for channel 8 Six compare-match interrupts for channel 9 Two compare-match interrupts and one dual-function input capture/compare-match interrupt for channel 10 Two dual input capture/compare-match interrupt requests and one overflow interrupt request for channel 11 • Direct memory access controller (DMAC) activation The DMAC can be activated by a channel 0 input capture interrupt (ICI0A to D) The DMAC can be activated by a channel 6 cycle register 6 compare-match interrupt (CMI6A to D) The DMAC can be activated by a channel 7 cycle register 7 compare-match interrupt (CMI7A to D) • A/D converter activation The A/D converter can be activated by detection of 1 in bits ITVA6 to 13 of the channel 0 interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B) 175 Table 10.1 lists the functions of the ATU-II. Table 10.1 ATU-II Functions Item Counter configuration Clock sources Channel 0 Channel 1 Channel 2 Channels 3 to 5 φ to φ/32 (φ to φ/32) × (1/2n) (φ to φ/32) × (1/2n) (φ to φ/32) × (1/2n) (n = 0 to 5) (n = 0 to 5) (n = 0 to 5) TCLKA, TCLKB TCLKA, TCLKB TCLKA, TCLKB Counters TCNT0H, TCNT0L TCNT1A, TCNT1B TCNT2A, TCNT2B TCNT3 to 5 General registers — GR1A to H GR2A to H GR3A to D, GR4A to D, GR5A to D Dedicated input capture ICR0AH, ICR0AL, ICR0BH, ICR0BL, ICR0CH, ICR0CL, ICR0DH, ICR0DL OSBR1 OSBR2 — Dedicated output compare — OCR1 OCR2A to 2H — PWM output — — — Duty: GR3A to C, GR4A to C, GR5A to C Cycle: GR3D, GR4D, GR5D Input pins TI0A to D — — — I/O pins — TIO1A to H TIO2A to H TIO3A to D, TIO4A to D, TIO5A to D Output pins — — — — Counter clearing function — — — O 6 sources 9 sources 9 sources 15 sources Interval × 1, input capture × 4, overflow × 1 Dual input capture/ Dual input capture/ Dual input capture/ compare-match × 8, compare-match × 8, compare-match × 12, overflow × 1 overflow × 1* overflow × 3 Interrupt sources (* Same vector) Inter-channel and inter-module connection signals 176 A/D converter activation by interval interrupt request, DMAC activation by input capture interrupt, channel 10 compare-match signal capture trigger input Compare-match signal trigger output to channel 8 one-shot pulse output down-counter Compare-match signal trigger output to channel 8 one-shot pulse output down-counter Channel 10 compare- Channel 10 comparematch signal counter match signal counter clear input clear input Channel 9 comparematch signal input to capture trigger (Channel 3 only) Table 10.1 ATU-II Functions (cont) Item Counter configuration Clock sources Channels 6, 7 Channel 8 Channel 9 Channel 10 Channel 11 (φ to φ/32) × (1/2n) (φ to φ/32) × (1/2n) (φ to φ/32) (n = 0 to 5) (n = 0 to 5) (φ to φ/32) × (1/2n) (n = 0 to 5) TCLKA, TCLKB Counters TCNT6A to D, TCNT7A to D DCNT8A to P ECNT9A to F TCNT10AH, TCNT10AL, TCNT10B to H TCNT11 General registers — — — — GR11A, GR11B Dedicated input capture — — — ICR10AH, ICR10AL — Dedicated output compare — — GR9A to F GR10G — PWM output CYLR6A to D, CYLR7A to D, DTR6A to D, DTR7A to D, BFR6A to D, BFR7A to D — — — — Input pins — — TI9A to F TI10 — I/O pins — — — — — Output pins TO6A to D, TO7A to D TO8A to P — — — Counter clearing function O — O O — Interrupt sources 8 sources 16 sources 6 sources 3 sources 3 sources Inter-channel and inter-module connection signals Compare-match Underflow × 16 ×8 Compare-match Compare-match Compare-match ×6 × 2, dual input × 2, overflow × 1 capture/comparematch × 1 DMAC activation Channel 1 and 2 compare-match compare-match signal output signal trigger input to one-shot pulse output down-counter Compare-match signal channel 3 capture trigger output Compare-match Compare-match signal channel 0 signal output to capture trigger APC output Channel 1 and 2 counter clear output O: Available —: Not available 177 10.1.2 Pin Configuration Table 10.2 shows the pin configuration of the ATU-II. When these external pin functions are used, the pin function controller (PFC) should also be set in accordance with the ATU-II settings. If there are a number of pins with the same function, make settings so that only one of the pins is used. For details, see section 18, Pin Function Controller. Table 10.2 ATU-II Pins Channel Name Abbreviation I/O Function Common Clock input A TCLKA Input External clock A input pin Clock input B TCLKB Input External clock B input pin Input capture 0A TI0A Input ICR0AH, ICR0AL input capture input pin Input capture 0B TI0B Input ICR0BH, ICR0BL input capture input pin Input capture 0C TI0C Input ICR0CH, ICR0CL input capture input pin Input capture 0D TI0D Input ICR0DH, ICR0DL input capture input pin Input capture/output compare 1A TIO1A Input/ output GR1A output compare output/input capture input Input capture/output compare 1B TIO1B Input/ output GR1B output compare output/input capture input Input capture/output compare 1C TIO1C Input/ output GR1C output compare output/input capture input Input capture/output compare 1D TIO1D Input/ output GR1D output compare output/input capture input Input capture/output compare 1E TIO1E Input/ output GR1E output compare output/input capture input Input capture/output compare 1F TIO1F Input/ output GR1F output compare output/input capture input Input capture/output compare 1G TIO1G Input/ output GR1G output compare output/input capture input Input capture/output compare 1H TIO1H Input/ output GR1H output compare output/input capture input 0 1 178 Table 10.2 ATU-II Pins (cont) Channel Name Abbreviation I/O Function 2 Input capture/output compare 2A TIO2A Input/ output GR2A output compare output/input capture input Input capture/output compare 2B TIO2B Input/ output GR2B output compare output/input capture input Input capture/output compare 2C TIO2C Input/ output GR2C output compare output/input capture input Input capture/output compare 2D TIO2D Input/ output GR2D output compare output/input capture input Input capture/output compare 2E TIO2E Input/ output GR2E output compare output/input capture input Input capture/output compare 2F TIO2F Input/ output GR2F output compare output/input capture input Input capture/output compare 2G TIO2G Input/ output GR2G output compare output/input capture input Input capture/output compare 2H TIO2H Input/ output GR2H output compare output/input capture input Input capture/output compare 3A TIO3A Input/ output GR3A output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 3B TIO3B Input/ output GR3B output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 3C TIO3C Input/ output GR3C output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 3D TIO3D Input/ output GR3D output compare output/input capture input Input capture/output compare 4A TIO4A Input/ output GR4A output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 4B TIO4B Input/ output GR4B output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 4C TIO4C Input/ output GR4C output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 4D TIO4D Input/ output GR4D output compare output/input capture input 3 4 179 Table 10.2 ATU-II Pins (cont) Channel Name Abbreviation I/O Function 5 Input capture/output compare 5A TIO5A Input/ output GR5A output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 5B TIO5B Input/ output GR5B output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 5C TIO5C Input/ output GR5C output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 5D TIO5D Input/ output GR5D output compare output/input capture input Output compare 6A TO6A Output PWM output pin Output compare 6B TO6B Output PWM output pin Output compare 6C TO6C Output PWM output pin Output compare 6D TO6D Output PWM output pin Output compare 7A TO7A Output PWM output pin Output compare 7B TO7B Output PWM output pin Output compare 7C TO7C Output PWM output pin Output compare 7D TO7D Output PWM output pin One-shot pulse 8A TO8A Output One-shot pulse output pin One-shot pulse 8B TO8B Output One-shot pulse output pin One-shot pulse 8C TO8C Output One-shot pulse output pin One-shot pulse 8D TO8D Output One-shot pulse output pin One-shot pulse 8E TO8E Output One-shot pulse output pin One-shot pulse 8F TO8F Output One-shot pulse output pin One-shot pulse 8G TO8G Output One-shot pulse output pin One-shot pulse 8H TO8H Output One-shot pulse output pin One-shot pulse 8I TO8I Output One-shot pulse output pin One-shot pulse 8J TO8J Output One-shot pulse output pin One-shot pulse 8K TO8K Output One-shot pulse output pin One-shot pulse 8L TO8L Output One-shot pulse output pin One-shot pulse 8M TO8M Output One-shot pulse output pin One-shot pulse 8N TO8N Output One-shot pulse output pin 6 7 8 180 Table 10.2 ATU-II Pins (cont) Channel Name Abbreviation I/O Function 8 One-shot pulse 8O TO8O Output One-shot pulse output pin One-shot pulse 8P TO8P Output One-shot pulse output pin Event input 9A TI9A Input GR9A event input Event input 9B TI9B Input GR9B event input Event input 9C TI9C Input GR9C event input Event input 9D TI9D Input GR9D event input Event input 9E TI9E Input GR9E event input Event input 9F TI9F Input GR9F event input Input capture TI10 Input ICR10AH, ICR10AL input capture input 9 10 181 10.1.3 Register Configuration Table 10.3 summarizes the ATU-II registers. Table 10.3 ATU-II Registers Channel Name Abbreviation R/W Initial Value Address Access Size (Bits) Common Timer start register 1 TSTR1 R/W H'00 H'FFFFF401 8, 16, 32 Timer start register 2 TSTR2 R/W H'00 H'FFFFF400 Timer start register 3 TSTR3 R/W H'00 H'FFFFF402 Prescaler register 1 PSCR1 W H'00 H'FFFFF404 Prescaler register 2 PSCR2 W H'00 H'FFFFF406 Prescaler register 3 PSCR3 W H'00 H'FFFFF408 Prescaler register 4 PSCR4 W H'00 H'FFFFF40A Free-running counter 0H TCNT0H R/W H'0000 H'FFFFF430 Free-running counter 0L TCNT0L R/W H'0000 Input capture register 0AH ICR0AH R H'0000 H'FFFFF434 Input capture register 0AL ICR0AL R H'0000 Input capture register 0BH ICR0BH R H'0000 H'FFFFF438 Input capture register 0BL ICR0BL R H'0000 Input capture register 0CH ICR0CH R H'0000 H'FFFFF43C Input capture register 0CL ICR0CL R H'0000 Input capture register 0DH ICR0DH R H'0000 H'FFFFF420 Input capture register 0DL ICR0DL R H'0000 Timer interval interrupt ITVRR1 request register 1 R/W H'00 H'FFFFF424 Timer interval interrupt ITVRR2A request register 2A R/W H'00 H'FFFFF426 0 182 8 32 8 Table 10.3 ATU-II Registers (cont) Channel Name 0 1 Abbreviation R/W Initial Value Address Access Size (Bits) 8 Timer interval interrupt ITVRR2B request register 2B R/W H'00 H'FFFFF428 Timer I/O control register R/W H'00 H'FFFFF42A TIOR0 Timer status register 0 TSR0 R/(W)* H'0000 H'FFFFF42C 16 Timer interrupt enable register 0 TIER0 R/W H'0000 H'FFFFF42E Free-running counter 1A TCNT1A R/W H'0000 H'FFFFF440 Free-running counter 1B TCNT1B R/W H'0000 H'FFFFF442 General register 1A GR1A R/W H'FFFF H'FFFFF444 General register 1B GR1B R/W H'FFFF H'FFFFF446 General register 1C GR1C R/W H'FFFF H'FFFFF448 General register 1D GR1D R/W H'FFFF H'FFFFF44A General register 1E GR1E R/W H'FFFF H'FFFFF44C General register 1F GR1F R/W H'FFFF H'FFFFF44E General register 1G GR1G R/W H'FFFF H'FFFFF450 General register 1H GR1H R/W H'FFFF H'FFFFF452 Output compare register 1 OCR1 R/W H'FFFF H'FFFFF454 Offset base register 1 OSBR1 R H'0000 H'FFFFF456 Timer I/O control register 1A TIOR1A R/W H'00 H'FFFFF459 Timer I/O control register 1B TIOR1B R/W H'00 H'FFFFF458 Timer I/O control register 1C TIOR1C R/W H'00 H'FFFFF45B Timer I/O control register 1D TIOR1D R/W H'00 H'FFFFF45A Timer control register 1A TCR1A R/W H'00 H'FFFFF45D Timer control register 1B TCR1B R/W H'00 H'FFFFF45C 16 8, 16 183 Table 10.3 ATU-II Registers (cont) Channel Name Abbreviation R/W 1 Timer status register 1A TSR1A R/(W)* H'0000 H'FFFFF45E 16 Timer status register 1B TSR1B R/(W)* H'0000 H'FFFFF460 Timer interrupt enable register 1A TIER1A R/W H'0000 H'FFFFF462 Timer interrupt enable register 1B TIER1B R/W H'0000 H'FFFFF464 Trigger mode register TRGMDR R/W H'00 Free-running counter 2A TCNT2A R/W H'0000 H'FFFFF600 Free-running counter 2B TCNT2B R/W H'0000 H'FFFFF602 General register 2A GR2A R/W H'FFFF H'FFFFF604 General register 2B GR2B R/W H'FFFF H'FFFFF606 General register 2C GR2C R/W H'FFFF H'FFFFF608 General register 2D GR2D R/W H'FFFF H'FFFFF60A General register 2E GR2E R/W H'FFFF H'FFFFF60C General register 2F GR2F R/W H'FFFF H'FFFFF60E General register 2G GR2G R/W H'FFFF H'FFFFF610 General register 2H GR2H R/W H'FFFF H'FFFFF612 Output compare register 2A OCR2A R/W H'FFFF H'FFFFF614 Output compare register 2B OCR2B R/W H'FFFF H'FFFFF616 Output compare register 2C OCR2C R/W H'FFFF H'FFFFF618 Output compare register 2D OCR2D R/W H'FFFF H'FFFFF61A Output compare register 2E OCR2E R/W H'FFFF H'FFFFF61C Output compare register 2F OCR2F R/W H'FFFF H'FFFFF61E 2 184 Initial Value Address H'FFFFF466 Access Size (Bits) 8 16 Table 10.3 ATU-II Registers (cont) Channel Name Abbreviation R/W Initial Value 2 Output compare register 2G OCR2G R/W H'FFFF H'FFFFF620 Output compare register 2H OCR2H R/W H'FFFF H'FFFFF622 Offset base register 2 OSBR2 R H'0000 H'FFFFF624 Timer I/O control register 2A TIOR2A R/W H'00 H'FFFFF627 Timer I/O control register 2B TIOR2B R/W H'00 H'FFFFF626 Timer I/O control register 2C TIOR2C R/W H'00 H'FFFFF629 Timer I/O control register 2D TIOR2D R/W H'00 H'FFFFF628 Timer control register 2A TCR2A R/W H'00 H'FFFFF62B Timer control register 2B TCR2B R/W H'00 H'FFFFF62A Timer status register 2A TSR2A R/(W)* H'0000 H'FFFFF62C 16 Timer status register 2B TSR2B R/(W)* H'0000 H'FFFFF62E Timer interrupt enable register 2A TIER2A R/W H'0000 H'FFFFF630 Timer interrupt enable register 2B TIER2B R/W H'0000 H'FFFFF632 3 to 5 3 Address Access Size (Bits) 16 8, 16 Timer status register 3 TSR3 R/(W)* H'0000 H'FFFFF480 Timer interrupt enable register 3 TIER3 R/W H'0000 H'FFFFF482 Timer mode register TMDR R/W H'00 Free-running counter 3 TCNT3 R/W H'0000 H'FFFFF4A0 16 General register 3A GR3A R/W H'FFFF H'FFFFF4A2 General register 3B GR3B R/W H'FFFF H'FFFFF4A4 General register 3C GR3C R/W H'FFFF H'FFFFF4A6 General register 3D GR3D R/W H'FFFF H'FFFFF4A8 H'FFFFF484 16 8 185 Table 10.3 ATU-II Registers (cont) Channel Name Abbreviation R/W Initial Value Address 3 Timer I/O control register 3A TIOR3A R/W H'00 H'FFFFF4AB 8, 16 Timer I/O control register 3B TIOR3B R/W H'00 H'FFFFF4AA Timer control register 3 TCR3 R/W H'00 H'FFFFF4AC 8 Free-running counter 4 TCNT4 R/W H'0000 H'FFFFF4C0 16 General register 4A GR4A R/W H'FFFF H'FFFFF4C2 General register 4B GR4B R/W H'FFFF H'FFFFF4C4 General register 4C GR4C R/W H'FFFF H'FFFFF4C6 General register 4D GR4D R/W H'FFFF H'FFFFF4C8 Timer I/O control register 4A TIOR4A R/W H'00 H'FFFFF4CB 8, 16 Timer I/O control register 4B TIOR4B R/W H'00 H'FFFFF4CA Timer control register 4 TCR4 R/W H'00 H'FFFFF4CC 8 Free-running counter 5 TCNT5 R/W H'0000 H'FFFFF4E0 16 General register 5A GR5A R/W H'FFFF H'FFFFF4E2 General register 5B GR5B R/W H'FFFF H'FFFFF4E4 General register 5C GR5C R/W H'FFFF H'FFFFF4E6 General register 5D GR5D R/W H'FFFF H'FFFFF4E8 Timer I/O control register 5A TIOR5A R/W H'00 H'FFFFF4EB 8, 16 Timer I/O control register 5B TIOR5B R/W H'00 H'FFFFF4EA Timer control register 5 TCR5 R/W H'00 H'FFFFF4EC 8 Free-running counter 6A TCNT6A R/W H'0001 H'FFFFF500 Free-running counter 6B TCNT6B R/W H'0001 H'FFFFF502 Free-running counter 6C TCNT6C R/W H'0001 H'FFFFF504 Free-running counter 6D TCNT6D R/W H'0001 H'FFFFF506 4 5 6 186 Access Size (Bits) 16 Table 10.3 ATU-II Registers (cont) Channel Name Abbreviation R/W Initial Value 6 Cycle register 6A CYLR6A R/W H'FFFF H'FFFFF508 Cycle register 6B CYLR6B R/W H'FFFF H'FFFFF50A Cycle register 6C CYLR6C R/W H'FFFF H'FFFFF50C Cycle register 6D CYLR6D R/W H'FFFF H'FFFFF50E Buffer register 6A BFR6A R/W H'FFFF H'FFFFF510 Buffer register 6B BFR6B R/W H'FFFF H'FFFFF512 Buffer register 6C BFR6C R/W H'FFFF H'FFFFF514 Buffer register 6D BFR6D R/W H'FFFF H'FFFFF516 Duty register 6A DTR6A R/W H'FFFF H'FFFFF518 Duty register 6B DTR6B R/W H'FFFF H'FFFFF51A Duty register 6C DTR6C R/W H'FFFF H'FFFFF51C Duty register 6D DTR6D R/W H'FFFF H'FFFFF51E Timer control register 6A TCR6A R/W H'00 H'FFFFF521 Timer control register 6B TCR6B R/W H'00 H'FFFFF520 7 Address Timer status register 6 TSR6 R/(W)* H'0000 H'FFFFF522 Timer interrupt enable register 6 TIER6 R/W H'0000 H'FFFFF524 PWM mode register PMDR R/W H'00 Free-running counter 7A TCNT7A R/W H'0001 H'FFFFF580 Free-running counter 7B TCNT7B R/W H'0001 H'FFFFF582 Free-running counter 7C TCNT7C R/W H'0001 H'FFFFF584 Free-running counter 7D TCNT7D R/W H'0001 H'FFFFF586 Cycle register 7A CYLR7A R/W H'FFFF H'FFFFF588 Cycle register 7B CYLR7B R/W H'FFFF H'FFFFF58A Cycle register 7C CYLR7C R/W H'FFFF H'FFFFF58C Cycle register 7D CYLR7D R/W H'FFFF H'FFFFF58E H'FFFFF526 Access Size (Bits) 16 8, 16 16 8 16 187 Table 10.3 ATU-II Registers (cont) Channel Name Abbreviation R/W Initial Value 7 Buffer register 7A BFR7A R/W H'FFFF H'FFFFF590 Buffer register 7B BFR7B R/W H'FFFF H'FFFFF592 Buffer register 7C BFR7C R/W H'FFFF H'FFFFF594 Buffer register 7D BFR7D R/W H'FFFF H'FFFFF596 Duty register 7A DTR7A R/W H'FFFF H'FFFFF598 Duty register 7B DTR7B R/W H'FFFF H'FFFFF59A Duty register 7C DTR7C R/W H'FFFF H'FFFFF59C Duty register 7D DTR7D R/W H'FFFF H'FFFFF59E Timer control register 7A TCR7A R/W H'00 H'FFFFF5A1 8, 16 Timer control register 7B TCR7B R/W H'00 H'FFFFF5A0 Timer status register 7 TSR7 R/(W)* H'0000 H'FFFFF5A2 16 Timer interrupt enable register 7 TIER7 R/W H'0000 H'FFFFF5A4 Down-counter 8A DCNT8A R/W H'0000 H'FFFFF640 Down-counter 8B DCNT8B R/W H'0000 H'FFFFF642 Down-counter 8C DCNT8C R/W H'0000 H'FFFFF644 Down-counter 8D DCNT8D R/W H'0000 H'FFFFF646 Down-counter 8E DCNT8E R/W H'0000 H'FFFFF648 Down-counter 8F DCNT8F R/W H'0000 H'FFFFF64A Down-counter 8G DCNT8G R/W H'0000 H'FFFFF64C Down-counter 8H DCNT8H R/W H'0000 H'FFFFF64E Down-counter 8I DCNT8I R/W H'0000 H'FFFFF650 Down-counter 8J DCNT8J R/W H'0000 H'FFFFF652 Down-counter 8K DCNT8K R/W H'0000 H'FFFFF654 Down-counter 8L DCNT8L R/W H'0000 H'FFFFF656 Down-counter 8M DCNT8M R/W H'0000 H'FFFFF658 Down-counter 8N DCNT8N R/W H'0000 H'FFFFF65A Down-counter 8O DCNT8O R/W H'0000 H'FFFFF65C Down-counter 8P DCNT8P R/W H'0000 H'FFFFF65E 8 188 Address Access Size (Bits) 16 16 Table 10.3 ATU-II Registers (cont) Channel Name Abbreviation R/W Initial Value 8 Reload register 8 RLDR8 R/W H'0000 H'FFFFF660 Timer connection register TCNR R/W H'0000 H'FFFFF662 One-shot pulse terminate register OTR R/W H'0000 H'FFFFF664 Down-count start register DSTR R/W H'0000 H'FFFFF666 Timer control register 8 TCR8 R/W H'00 Timer status register 8 TSR8 R/(W)* H'0000 H'FFFFF66A 16 Timer interrupt enable register 8 R/W H'0000 H'FFFFF66C Reload enable register RLDENR R/W H'00 H'FFFFF66E 8 Event counter 9A ECNT9A R/W H'00 H'FFFFF680 Event counter 9B ECNT9B R/W H'00 H'FFFFF682 Event counter 9C ECNT9C R/W H'00 H'FFFFF684 Event counter 9D ECNT9D R/W H'00 H'FFFFF686 Event counter 9E ECNT9E R/W H'00 H'FFFFF688 Event counter 9F ECNT9F R/W H'00 H'FFFFF68A General register 9A GR9A R/W H'FF H'FFFFF68C General register 9B GR9B R/W H'FF H'FFFFF68E General register 9C GR9C R/W H'FF H'FFFFF690 General register 9D GR9D R/W H'FF H'FFFFF692 General register 9E GR9E R/W H'FF H'FFFFF694 General register 9F GR9F R/W H'FF H'FFFFF696 Timer control register 9A TCR9A R/W H'00 H'FFFFF698 Timer control register 9B TCR9B R/W H'00 H'FFFFF69A Timer control register 9C TCR9C R/W H'00 H'FFFFF69C 9 TIER8 Address H'FFFFF668 Access Size (Bits) 16 8 8 Timer status register 9 TSR9 R/(W)* H'0000 H'FFFFF69E 16 Timer interrupt enable register 9 R/W TIER9 H'0000 H'FFFFF6A0 189 Table 10.3 ATU-II Registers (cont) Channel Name Abbreviation R/W Initial Value 10 Free-running counter 10AH TCNT10AH R/W H'0000 H'FFFFF6C0 32 Free-running counter 10AL TCNT10AL R/W H'0001 Event counter 10B TCNT10B R/W H'00 Reload counter 10C TCNT10C R/W H'0001 H'FFFFF6C6 16 Correction counter 10D TCNT10D R/W H'00 Correction angle counter 10E TCNT10E R/W H'0000 H'FFFFF6CA 16 Correction angle counter 10F TCNT10F R/W H'0001 H'FFFFF6CC Free-running counter 10G TCNT10G R/W H'0000 H'FFFFF6CE Input capture register 10AH ICR10AH R H'0000 H'FFFFF6D0 32 Input capture register 10AL ICR10AL R H'0000 Output compare register 10AH OCR10AH R/W H'FFFF H'FFFFF6D4 Output compare register 10AL OCR10AL R/W H'FFFF Output compare register 10B OCR10B R/W H'FF Reload register 10C RLD10C R/W H'0000 H'FFFFF6DA 16 General register 10G GR10G R/W H'FFFF H'FFFFF6DC Noise canceler counter 10H TCNT10H R/W H'00 H'FFFFF6DE 8 Noise canceler register 10 NCR10 R/W H'FF H'FFFFF6E0 Timer I/O control register 10 TIOR10 R/W H'00 H'FFFFF6E2 Timer control register 10 TCR10 R/W H'00 H'FFFFF6E4 190 Address Access Size (Bits) H'FFFFF6C4 8 H'FFFFF6C8 8 H'FFFFF6D8 8 Table 10.3 ATU-II Registers (cont) Channel Name Abbreviation R/W Initial Value 10 Correction counter clear register 10 TCCLR10 R/W H'0000 H'FFFFF6E6 16 Timer status register 10 TSR10 R/(W)* H'FFFF H'FFFFF6E8 Timer interrupt enable register 10 TIER10 R/W H'FFFF H'FFFFF6EA Free-running counter 11 TCNT11 R/W H'0000 H'FFFFF5C0 16 General register 11A GR11A R/W H'FFFF H'FFFFF5C2 General register 11B GR11B R/W H'FFFF H'FFFFF5C4 Timer I/O control register 11 TIOR11 R/W H'00 H'FFFFF5C6 8 Timer control register 11 TCR11 R/W H'00 H'FFFFF5C8 Timer status register 11 TSR11 R/(W)* H'0000 H'FFFFF5CA 16 Timer interrupt enable register 11 TIER11 R/W 11 Address Access Size (Bits) H'0000 H'FFFFF5CC Note: * 0 write after a read 191 10.1.4 Block Diagrams Overall Block Diagram of ATU-II: Figure 10.1 shows an overall block diagram of the ATU-II. Clock selection Interrupts Inter-module connection signals External pins Bus interface Inter-module address bus TSTR3 TSTR2 TSTR1 16-bit timer channel 11 ........ Channel 10 Counter and register control, and comparator 16-bit timer channel 1 Pø I/O interrupt control IC/OC control 32-bit timer channel 0 Prescaler TCLKA TCLKB Module data bus Inter-module data bus Legend: TSTR1, 2, 3: Timer start registers (8 bits) Interrupts: ITV0 to ITV2, OVI0, OVI1A, OVI1B, OVI2A, OVI2B, OVI3 to OVI5, OVI11, ICI0A to ICI0D, IMI1A to IMI1H, CMI1, IMI2A to IMI2H, CMI2A to CMI2H, IMI3A to IMI3D, IMI4A to IMI4D, IMI5A to IMI5D, CMI6A to CMI6D, CMI7A to CMI7D, OSI8A to OSI8P, CMI9A to CMI9F, CMI10A, CMI10B, ICI10A, CMI10G, IMI11A, IMI11B External pins: TI0A to TI0D, TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D, TO6A to TO6D, TO7A to TO7D, TO8A to TO8P, TI9A to TI9F, TI10 Inter-module connection signals: Signals to A/D converter, signals to direct memory access controller (DMAC), signals to advanced pulse controller (APC) Figure 10.1 Overall Block Diagram of ATU-II 192 Block Diagram of Channel 0: Figure 10.2 shows a block diagram of ATU-II channel 0. STR0 Prescaler 1 ICR0AH ICR0BH ICR0CH ICR0DH TCNT0H ICR0AL ICR0BL ICR0CL ICR0DL TCNT0L TIOR0 TIER0 ITVRR1 ITVRR2A ITVRR2B TSR0 TI0A TI0B TI0C TI0D TRGOD (OCR10B compare-match signal) Control logic I/O control A/D converter trigger Overflow interrupt signal Interval interrupt OSBR (ch1, ch2) Internal data bus and address bus Figure 10.2 Block Diagram of Channel 0 193 Block Diagram of Channel 1: Figure 10.3 shows a block diagram of ATU-II channel 1. STR1A/2B Prescaler 1 TCLKA TCLKB TI10 (AGCK) TI10 multiplication (AGCKM) Comparator Clock selection logic (2 systems: A, B) TI0A(capture signal from CH0) GR1A GR1B GR1C GR1D GR1E GR1F GR1G GR1H OSBR1 TCNT1A TRG1A (counter clear trigger from CH10) TRG1B (counter clear trigger from CH10) Control logic OCR1 TCNT1B TIOR1A TIOR1B TIOR1C TIOR1D TCR1A TCR1B TSR1A TSR1B TIER1A TIER1B TRGMDR TIO1A TIO1B TIO1C TIO1D TIO1E TIO1F TIO1G TIO1H One-shot start trigger (CH8) One-shot terminate trigger (CH8) I/O control Overflow interrupt × 1 Input capture/output compare interrupts × 8 Internal data bus and address bus Figure 10.3 Block Diagram of Channel 1 194 Block Diagram of Channel 2: Figure 10.4 shows a block diagram of ATU-II channel 2. STR2A/2B Prescaler 1 TCLKA TCLKB TI10 (AGCKM) TI10 multiplication (AGCK) Comparator Clock selection logic TI0A (couter clear trigger from CH0) GR2A GR2B GR2C GR2D GR2E GR2F GR2G GR2H OSBR2 TCNT2A Control logic TRG2A (counter clear trigger from CH10) TRG2B (counter clear trigger from CH10) OCR2A OCR2B OCR2C OCR2D OCR2E OCR2F OCR2G OCR2H TCNT2B TIOR2A TIOR2B TIOR2C TIOR2D TCR2A TCR2B TSR2A TSR2B TIER2A TIER2B TIO2A TIO2B TIO2C TIO2D TIO2E TIO2F TIO2G TIO2H One-shot start trigger (CH8) I/O control One-shot terminate trigger (CH8) Overflow interrupt × 1 Input capture/output compare interrupts × 8 Internal data bus and address bus Figure 10.4 Block Diagram of Channel 2 195 Block Diagram of Channels 3 to 5: Figure 10.5 shows a block diagram of ATU-II channels 3, 4, and 5. STR3 to 5 Prescaler 1 TCLKA TCLKB TI10 (AGCK) Clock selection logic (3 systems: CH3, 4, 5) Comparator TI10 multiplication (AGCKM) Channel 9 comparematch trigger GR3A •• • GR3D TCNT3 TIOR3A TIOR3B TCR3 GR4A • •• GR4D TCNT4 Control logic TIOR4A TIOR4B TCR4 GR5A •• • GR5D TCNT5 TIOR5A TIOR5B TCR5 TMDR TIER3 TSR3 TIO3A TIO3B TIO3C TIO3D TIO4A TIO4B TIO4C TIO4D TIO5A TIO5B TIO5C TIO5D I/O control Overflow interrupts × 3 Input capture/output compare interrupts × 12 Internal data bus and address bus Figure 10.5 Block Diagram of Channels 3 to 5 196 Block Diagram of Channels 6 and 7: Figure 10.6 shows a block diagram of ATU-II channels 6 and 7. TSR6×, 7× Prescaler 2 Comparator Clock selection logic (A–D independent) BFR6A CYLR6A DTR6A TCNT6A BFR6B CYLR6B DTR6B TCNT6B BFR6C CYLR6C DTR6C TCNT6C Control logic BFR6D CYLR6D DTR6D TCNT6D TCR6A TCR6B TSR6 TIER6 PMDR TO6A TO6B TO6C TO6D I/O control Compare-match interrupts × 4 Internal data bus and address bus Note: Channel 7 has no PMDR7. Figure 10.6 Block Diagram of Channel 6 (Same Configuration for Channel 7) 197 Block Diagram of Channel 8: Figure 10.7 shows a block diagram of ATU-II channel 8. Prescaler 1 Clock selection (2 systems: A–H, I–P) Comparator DCNT8A DCNT8B DCNT8C DCNT8D One-shot start trigger (CH1, 2) One-shot terminate trigger (CH1, 2) • • • • DCNT8M DCNT8N DCNT8O DCNT8P Control logic RLDR8 TCNR OTR DSTR TCR8 TSR8 TIER8 RLDENR TO8A TO8B • • • • TO8O TO8P I/O control Down-count end interrupts × 16 (OSI) Internal data bus and address bus Figure 10.7 Block Diagram of Channel 8 198 Block Diagram of Channel 9: Figure 10.8 shows a block diagram of ATU-II channel 9. GR9A ECNT9A Comparator GR9B ECNT9B GR9C ECNT9C GR9D ECNT9D GR9E ECNT9E Control logic GR9F ECNT9F TCR9A TCR9B TCR9C TSR9 TIER9 TI9A TI9B TI9C TI9D TI9E TI9F Channel 3 capture trigger × 4 I/O control Compare-match interrupts × 6 Internal data bus and address bus Figure 10.8 Block Diagram of Channel 9 199 Block Diagram of Channel 10: Figure 10.9 shows a block diagram of ATU-II channel 10. STR10 Prescaler 4 ICR10AH OCR10AH TCNT10AH ICR10AL OCR10AL TCNT10AL OCR10B TCNT10B RLD10C TCNT10C TCNT10D TCNT10E TCNT10F Control logic GR10G TCNT10G NCR10 TCNT10H TCCLR10 TIOR10 TCR10 TIER10 TSR10 TI10 I/O control Internal data bus and address bus Figure 10.9 Block Diagram of Channel 10 200 TRG1A, 1B, 2A, 2B (Counter clear trigger) TRG0D (OCR10B comparematch signal) Frequency multiplication clock Frequency multiplication correction clock Output compare interrupts × 2 Input capture / output compare interrupt × 1 Block Diagram of Channel 11: Figure 10.10 shows a block diagram of ATU-II channel 11. STR11 Prescaler 4 TCLKA TCLKB Comparator Clock selection logic GR11A GR11B TCNT11 TIOR11 TCR11 TSR11 TIER11 Control logic APC output compare-match timing signals × 2 Overflow interrupt × 1 Output compare interrupts × 2 Internal data bus and address bus Figure 10.10 Block Diagram of Channel 11 201 10.1.5 Inter-Channel and Inter-Module Signal Communication Diagram Figure 10.11 shows the connections between channels and between modules in the ATU-II. Channel 0 TI0A ICR0A ICR0B ICR0C ICR0D ITVRR1 ITVRR2A ITVRR2B A/D converter activation DMAC activation Channel 10 Capture trigger OCR10B Channel 1 TCNT1A TCNT1B Capture trigger OSBR1 GR1A GR1B OCR1 GR1H OSBR2 TCNT2A TCNT2B OCR2A OCR2B GR2A GR2B TCNT10F •• • Channel 2 •• • •• • OCR2H GR2H TI10(AGCK) TI10 multiplication (AGCKM) Counter clear trigger TI10(AGCK) TI10 multiplication (AGCKM) Channel 8 One-shot start One-shot terminate DCNT8A DCNT8B DCNT8C DCNT8D DCNT8E DCNT8F DCNT8G DCNT8H DCNT8I DCNT8J DCNT8K DCNT8L DCNT8M DCNT8N DCNT8O DCNT8P TI10(AGCK) TI10 multiplication (AGCKM) Channel 3 GR3A GR3B GR3C GR3D Channel 4 TI10(AGCK) TI10 multiplication (AGCKM) Channel 5 TI10(AKCK) TI10 multiplication (AGCKM) Capture trigger Channel 9 Channel 6, 7 GR9A GR9B GR9C GR9D GR9E GR9F TCNT6x, 7x CYLR6x, 7x DTR6x, 7x BFR6x, 7x X: A, B, C, D Channel 11 TCNT11 GR11A GR11B Compare-match signal transmission to advanced pulse controller (APC) Figure 10.11 Inter-Module Communication Signals 202 DMAC activation (compare-match) 10.1.6 Prescaler Diagram Figure 10.12 shows a diagram of the ATU-II prescalers. Input clock φ/2 Channel 0 Prescaler 1 Channel 1 Channel 2 TCLKA TCLKB Channel 3 Edge detection Channel 4 Channel 5 Channel 8 Channel 10 TI10 TI9A TI9B TI9C TI9D TI9E TI9F Prescaler 2 Channel 6 Prescaler 3 Channel 7 Prescaler 4 Channel 11 Channel 9 Timer control register Figure 10.12 Prescaler Diagram 203 10.2 Register Descriptions 10.2.1 Timer Start Registers (TSTR) The timer start registers (TSTR) are 8-bit registers. The ATU-II has three TSTR registers. Channel Abbreviation Function 0, 1, 2, 3, 4, 5, 10 TSTR1 Free-running counter operation/stop setting 6, 7 TSTR2 11 TSTR3 Timer Start Register 1 (TSTR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 STR10 STR5 STR4 STR3 STR1B, 2B STR2A STR1A STR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TSTR1 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT) in channels 0 to 5 and 10. TSTR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Counter Start 10 (STR10): Starts and stops channel 10 counters (TCNT10A, 10C, 10D, 10E, 10F, and 10G). TCNT10B and 10H are not stopped. Bit 7: STR10 Description 0 TCNT10 is halted 1 TCNT10 counts (Initial value) • Bit 6—Counter Start 5 (STR5): Starts and stops free-running counter 5 (TCNT5). Bit 6: STR5 Description 0 TCNT5 is halted 1 TCNT5 counts 204 (Initial value) • Bit 5—Counter Start 4 (STR4): Starts and stops free-running counter 4 (TCNT4). Bit 5: STR4 Description 0 TCNT4 is halted 1 TCNT4 counts (Initial value) • Bit 4—Counter Start 3 (STR3): Starts and stops free-running counter 3 (TCNT3). Bit 4: STR3 Description 0 TCNT3 is halted 1 TCNT3 counts (Initial value) • Bit 3—Counter Start 1B, 2B (STR1B, STR2B): Starts and stops free-running counters 1B and 2B (TCNT1B, TCNT2B). Bit 3: STR1B, STR2B Description 0 TCNT1B and TCNT2B are halted 1 TCNT1B and TCNT2B count (Initial value) • Bit 2—Counter Start 2A (STR2A): Starts and stops free-running counter 2A (TCNT2A). Bit 2: STR2A Description 0 TCNT2A is halted 1 TCNT2A counts (Initial value) • Bit 1—Counter Start 1A (STR1A): Starts and stops free-running counter 1A (TCNT1A). Bit 1: STR1A Description 0 TCNT1A is halted 1 TCNT1A counts (Initial value) • Bit 0—Counter Start 0 (STR0): Starts and stops free-running counter 0 (TCNT0). Bit 0: STR0 Description 0 TCNT0 is halted 1 TCNT0 counts (Initial value) 205 Timer Start Register 2 (TSTR2) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 STR7D STR7C STR7B STR7A STR6D STR6C STR6B STR6A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TSTR2 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT) in channels 6 and 7. TSTR2 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Counter Start 7D (STR7D): Starts and stops free-running counter 7D (TCNT7D). Bit 7: STR7D Description 0 TCNT7D is halted 1 TCNT7D counts (Initial value) • Bit 6—Counter Start 7C (STR7C): Starts and stops free-running counter 7C (TCNT7C). Bit 6: STR7C Description 0 TCNT7C is halted 1 TCNT7C counts (Initial value) • Bit 5—Counter Start 7B (STR7B): Starts and stops free-running counter 7B (TCNT7B). Bit 5: STR7B Description 0 TCNT7B is halted 1 TCNT7B counts (Initial value) • Bit 4—Counter Start 7A (STR7A): Starts and stops free-running counter 7A (TCNT7A). Bit 4: STR7A Description 0 TCNT7A is halted 1 TCNT7A counts 206 (Initial value) • Bit 3—Counter Start 6D (STR6D): Starts and stops free-running counter 6D (TCNT6D). Bit 3: STR6D Description 0 TCNT6D is halted 1 TCNT6D counts (Initial value) • Bit 2—Counter Start 6C (STR6C): Starts and stops free-running counter 6C (TCNT6C). Bit 2: STR6C Description 0 TCNT6C is halted 1 TCNT6C counts (Initial value) • Bit 1—Counter Start 6B (STR6B): Starts and stops free-running counter 6B (TCNT6B). Bit 1: STR6B Description 0 TCNT6B is halted 1 TCNT6B counts (Initial value) • Bit 0—Counter Start 6A (STR6A): Starts and stops free-running counter 6A (TCNT6A). Bit 0: STR6A Description 0 TCNT6A is halted 1 TCNT6A counts (Initial value) Timer Start Register 3 (TSTR3) Bit: 7 6 5 4 3 2 1 0 — — — — — — — STR11 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W TSTR3 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT11) in channel 11. TSTR3 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bits 7 to 1—Reserved: These bits always read 0. The write value should always be 0. 207 • Bit 0—Counter Start 11 (STR11): Starts and stops free-running counter 11 (TCNT11). Bit 0: STR11 Description 0 TCNT11 is halted 1 TCNT11 counts 10.2.2 (Initial value) Prescaler Registers (PSCR) The prescaler registers (PSCR) are 8-bit registers. The ATU-II has four PSCR registers. Channel Abbreviation Function 0, 1, 2, 3, 4, 5, 8, 11 PSCR1 Prescaler setting for respective channels 6 PSCR2 7 PSCR3 10 PSCR4 PSCRx is an 8-bit writable register that enables the first-stage counter clock φ' input to each channel to be set to any value from Pφ/1 to Pφ/32. Bit: 7 6 5 4 3 2 1 0 — — — PSCxE PSCxD PSCxC PSCxB PSCxA Initial value: — — — 0 0 0 0 0 R/W: — — — W W W W W x = 1 to 4 Input counter clock φ' is determined by setting PSCxA to PSCxE: φ' is Pφ/1 when the set value is H'00, and Pφ/32 when H'1F. PSCRx is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. The internal clock φ' set with this register can undergo further second-stage scaling to create clock φ" for channels 1 to 8 and 11, the setting being made in the timer control register (TCR). • Bits 7 to 5—Reserved. These bits cannot be modified. • Bits 4 to 0—Prescaler (PSCxE, PSCxD, PSCxC, PSCxB, PSCxA): These bits specify frequency division of first-stage counter clock φ' input to the corresponding channel. 208 10.2.3 Timer Control Registers (TCR) The timer control registers (TCR) are 8-bit registers. The ATU-II has 16 TCR registers: two each for channels 1 and 2, one each for channels 3, 4, 5, 8, and 11, two each for channels 6 and 7, and three for channel 9. For details of channel 10, see section 10.2.26, Channel 10 Registers. Channel Abbreviation Function 1 TCR1A, TCR1B Internal clock/external clock/TI10 input clock selection 2 TCR2A, TCR2B 3 TCR3 4 TCR4 5 TCR5 6 TCR6A, TCR6B 7 TCR7A, TCR7B 8 TCR8 9 TCR9A, TCR9B, TCR9C External clock selection/setting of channel 3 trigger in event of compare-match 11 TCR11 Internal clock/external clock selection Internal clock selection Each TCR is an 8-bit readable/writable register that selects whether an internal clock or external clock is used for channels 1 to 5 and 11. For channels 6 to 8, TCR selects an internal clock, and for channel 9, an external clock. When an internal clock is selected, TCR selects the value of φ" further scaled from clock φ' scaled with prescaler register 1 (PSCR1). Scaled clock φ" can be selected, for channels 1 to 8 and 11 only, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32 (only φ' is available for channel 0). Edge detection is performed on the rising edge. When an external clock is selected, TCR selects whether TCLKA, TCLKB (channels 1 to 5 and 11 only), TI10 pin input (channels 1 to 5 only), or a TI10 pin input multiplied clock (channels 1 to 5 only) is used, and also performs edge selection. Each TCR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. 209 Timer Control Registers 1A, 1B, 2A, 2B (TCR1A, TCR1B, TCR2A, TCR2B) TCR1A, TCR2A Bit: 7 6 5 4 3 2 1 0 — — CKEGA1 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 — — CKEGB1 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W CKEGA0 CKSELA3 CKSELA2 CKSELA1 CKSELA0 TCR1B, TCR2B Bit: CKEGB0 CKSELB3 CKSELB2 CKSELB1 CKSELB0 • Bits 7 and 6—Reserved: These bits always read 0. The write value should always be 0. • Bits 5 and 4—Clock Edge 1 and 0 (CKEGx1, CKEGx0): These bits select the count edge(s) for external clock TCLKA and TCLKB input. Bit 5: CKEGx1 Bit 4: CKEGx0 Description 0 0 Rising edges counted 1 Falling edges counted 0 Both rising and falling edges counted 1 Count disabled 1 (Initial value) x = A or B • Bits 3 to 0—Clock Select A3 to A0, B3 to B0 (CKSELA3 to CKSELA0, CKSELB3 to CKSELB0): These bits select whether an internal clock or external clock is used. When an internal clock is selected, scaled clock φ" is selected from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. When an external clock is selected, TCLKA, TCLKB, TI10 pin input, or a TI10 pin input multiplied clock is selected. When TI10 pin input and TI10 pin input clock multiplication are selected, set CKEG1 and CKEG0 in TCR10 so that TI10 input is possible. 210 Bit 3: CKSELx3 Bit 2: CKSELx2 Bit 1: CKSELx1 Bit 0: CKSELx0 Description 0 0 0 0 Internal clock φ": counting on φ' 1 Internal clock φ": counting on φ'/2 0 Internal clock φ": counting on φ'/4 1 Internal clock φ": counting on φ'/8 0 Internal clock φ": counting on φ'/16 1 Internal clock φ": counting on φ'/32 0 External clock: counting on TCLKA pin input 1 External clock: counting on TCLKB pin input 0 Counting on TI10 pin input (AGCK) 1 Counting on multiplied (corrected)(AGCKM) TI10 pin input clock 1 * Setting prohibited * * Setting prohibited 1 1 0 1 1 0 0 1 (Initial value) x = A or B *: Don’t care Timer Control Registers 3 to 5 (TCR3, TCR4, TCR5) Bit: 7 6 5 — — CKEG1 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W CKEG0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 • Bits 7 and 6—Reserved: These bits always read 0. The write value should always be 0. • Bits 5 and 4—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the count edge(s) for external clock TCLKA and TCLKB input. Bit 5: CKEG1 Bit 4: CKEG0 Description 0 0 Rising edges counted 1 Falling edges counted 0 Both rising and falling edges counted 1 Count disabled 1 (Initial value) 211 • Bits 3 to 0—Clock Select 3 to 0 (CKSEL3 to CKSEL0): These bits select whether an internal clock or external clock is used. When an internal clock is selected, scaled clock φ" is selected from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. When an external clock is selected, TCLKA, TCLKB, TI10 pin input, or a TI10 pin input multiplied clock is selected. When TI10 pin input and TI10 pin input clock multiplication are selected, set CKEG1 and CKEG0 in TCR10 so that TI10 input is possible. Bit 3: CKSEL3 Bit 2: CKSEL2 Bit 1: CKSEL1 Bit 0: CKSEL0 Description 0 0 0 0 Internal clock φ": counting on φ' 1 Internal clock φ": counting on φ'/2 0 Internal clock φ": counting on φ'/4 1 Internal clock φ": counting on φ'/8 0 Internal clock φ": counting on φ'/16 1 Internal clock φ": counting on φ'/32 0 External clock: counting on TCLKA pin input 1 External clock: counting on TCLKB pin input 0 Counting on TI10 pin input (AGCK) 1 Counting on multiplied (corrected)(AGCKM) TI10 pin input clock 1 * Setting prohibited * * Setting prohibited 1 1 0 1 1 0 1 *: Don’t care 212 0 (Initial value) Timer Control Registers 6A, 6B, 7A, 7B (TCR6A, TCR6B, TCR7A, TCR7B) TCR6A, TCR7A Bit: 7 — 6 5 4 CKSELB2 CKSELB1 CKSELB0 3 — 2 1 0 CKSELA2 CKSELA1 CKSELA0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W 7 6 5 4 3 2 1 0 TCR6B, TCR7B Bit: — CKSELD2 CKSELD1 CKSELD0 — CKSELC2 CKSELC1 CKSELC0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bits 6 to 4—Clock Select B2 to B0, D2 to D0 (CKSELB2 to CKSELB0, CKSELD2 to CKSELD0): These bits select clock φ", scaled from the internal clock source, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. Bit 6: CKSELx2 Bit 5: CKSELx1 Bit 4: CKSELx0 Description 0 0 0 Internal clock φ": counting on φ' 1 Internal clock φ": counting on φ'/2 0 Internal clock φ": counting on φ'/4 1 Internal clock φ": counting on φ'/8 0 Internal clock φ": counting on φ'/16 1 Internal clock φ": counting on φ'/32 0 Setting prohibited 1 Setting prohibited 1 1 0 1 (Initial value) x = B or D • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. 213 • Bits 2 to 0—Clock Select A2 to A0, C2 to C0 (CKSELA2 to CKSELA0, CKSELC2 to CKSELC0): These bits select clock φ", scaled from the internal clock source, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. Bit 2: CKSELx2 Bit 1 CKSELx1 Bit 0 CKSELx0 Description 0 0 0 Internal clock φ": counting on φ' 1 Internal clock φ": counting on φ'/2 0 Internal clock φ": counting on φ'/4 1 Internal clock φ": counting on φ'/8 0 Internal clock φ": counting on φ'/16 1 Internal clock φ": counting on φ'/32 0 Setting prohibited 1 Setting prohibited 1 1 0 1 (Initial value) x = A or C Timer Control Register 8 (TCR8) Bit: 7 — 6 5 4 CKSELB2 CKSELB1 CKSELB0 3 — 2 1 0 CKSELA2 CKSELA1 CKSELA0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W The CKSELAx bits relate to DCNT8A to DCNT8H, and the CKSELBx bits relate to DCNT8I to DCNT8P. • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. 214 • Bits 6 to 4—Clock Select B2 to B0 (CKSELB2 to CKSELB0): These bits, relating to counters DCNT8I to DCNT8P, select clock φ", scaled from the internal clock source, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. Bit 6: CKSELB2 Bit 5: CKSELB1 Bit 4: CKSELB0 Description 0 0 0 Internal clock φ": counting on φ' 1 Internal clock φ": counting on φ'/2 0 Internal clock φ": counting on φ'/4 1 Internal clock φ": counting on φ'/8 0 Internal clock φ": counting on φ'/16 1 Internal clock φ": counting on φ'/32 0 Setting prohibited 1 Setting prohibited 1 1 0 1 (Initial value) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bits 2 to 0—Clock Select A2 to A0 (CKSELA2 to CKSELA0): These bits, relating to counters DCNT8A to DCNT8H, select clock φ", scaled from the internal clock source, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. Bit 2: CKSELA2 Bit 1: CKSELA1 Bit 0: CKSELA0 Description 0 0 0 Internal clock φ": counting on φ' 1 Internal clock φ": counting on φ'/2 0 Internal clock φ": counting on φ'/4 1 Internal clock φ": counting on φ'/8 0 Internal clock φ": counting on φ'/16 1 Internal clock φ": counting on φ'/32 0 Setting prohibited 1 Setting prohibited 1 1 0 1 (Initial value) 215 Timer Control Registers 9A, 9B, 9C (TCR9A, TCR9B, TCR9C) TCR9A Bit: 7 — 6 5 4 TRG3BEN EGSELB1 EGSELB0 3 — 2 1 0 TRG3AEN EGSELA1 EGSELA0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W 7 6 5 4 3 2 1 0 TCR9B Bit: — TRG3DEN EGSELD1 EGSELD0 — TRG3CEN EGSELC1 EGSELC0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W 7 6 5 4 3 2 1 0 — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R R R/W R/W TCR9C Bit: EGSELF1 EGSELF0 EGSELE1 EGSELE0 • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—Trigger Channel 3BEN, 3DEN (TRG3BEN, TRG3DEN): These bits select the channel 9 event counter compare-match signal channel 3 input capture trigger. Bit 6: TRG3xEN Description 0 Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is disabled (Initial value) 1 Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is enabled x = B or D 216 • Bits 5 and 4—Edge Select B1, B0, D1, D0, F1, F0 (EGSELB1, EGSELB0, EGSELD1, EGSELD0, EGSELF1, EGSELF0): These bits select the event counter counted edge(s). Bit 5: EGSELx1 Bit 4: EGSELx0 Description 0 0 Count disabled 1 Rising edges counted 0 Falling edges counted 1 Both rising and falling edges counted 1 (Initial value) x = B, D, or F • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—Trigger Channel 3AEN, 3CEN (TRG3AEN, TRG3CEN): These bits select the channel 9 event counter compare-match signal channel 3 input capture trigger. Bit 2: TRG3xEN Description 0 Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is disabled (Initial value) 1 Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is enabled x = A or C • Bits 1 and 0—Edge Select A1, A0, C1, C0, E1, E0 (EGSELA1, EGSELA0, EGSELC1, EGSELC0, EGSELE1, EGSELE0): These bits select the event counter counted edge(s). Bit 1: EGSELx1 Bit 0: EGSELx0 Description 0 0 Count disabled 1 Rising edges counted 0 Falling edges counted 1 Both rising and falling edges counted 1 (Initial value) x = A, C, or E 217 Timer Control Register 11 (TCR11) Bit: 7 6 5 4 3 2 1 0 — — CKEG1 CKEG0 — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R R/W R/W R/W CKSELA2 CKSELA1 CKSELA0 • Bits 7, 6, and 3—Reserved: These bits always read 0. The write value should always be 0. • Bits 5 and 4—Edge Select: These bits select the event counter counted edge(s). Bit 5: CKEG1 Bit 4: CKEG0 Description 0 0 Rising edges counted 1 Falling edges counted 0 Both rising and falling edges counted 1 Count disabled 1 (Initial value) • Bits 2 to 0—Clock Select A2 to A0 (CKSELA2 to CKSELA0): These bits select clock φ", scaled from the internal clock source, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. Bit 2: CKSELA2 Bit 1: CKSELA1 Bit 0: CKSELA0 Description 0 0 0 Internal clock φ": counting on φ' 1 Internal clock φ": counting on φ'/2 0 Internal clock φ": counting on φ'/4 1 Internal clock φ": counting on φ'/8 0 Internal clock φ": counting on φ'/16 1 Internal clock φ": counting on φ'/32 0 External clock: counting on TCLKA pin input 1 External clock: counting on TCLKB pin input 1 1 0 1 218 (Initial value) 10.2.4 Timer I/O Control Registers (TIOR) The timer I/O control registers (TIOR) are 8-bit registers. The ATU-II has 16 TIOR registers: one for channel 0, four each for channels 1 and 2, two each for channels 3 to 5, and one for channel 11. For details of channel 10, see section 10.2.26, Channel 10 Registers. Channel Abbreviation Function 0 TIOR0 ICR0 edge detection setting 1 TIOR1A to 1D 2 TIOR2A to 2D GR input capture/compare-match switching, edge detection/ output value setting 3 TIOR3A, TIOR3B 4 TIOR4A, TIOR4B 5 TIOR5A, TIOR5B 11 TIOR11 GR input capture/compare-match switching, edge detection/ output value setting, TCNT3 to TCNT5 clear enable/disable setting GR input capture/compare-match switching, edge detection/output value setting Each TIOR is an 8-bit readable/writable register used to select the functions of dedicated input capture registers and general registers. For dedicated input capture registers (ICR), TIOR performs edge detection setting. For general registers (GR), TIOR selects use as an input capture register or output compare register, and performs edge detection setting. For channels 3 to 5, TIOR also selects enabling or disabling of free-running counter (TCNT) clearing in the event of a compare-match. Timer I/O Control Register 0 (TIOR0) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 IO0D1 IO0D0 IO0C1 IO0C0 IO0B1 IO0B0 IO0A1 IO0A0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TIOR0 specifies edge detection for input capture registers ICR0A to ICR0D. TIOR0 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. 219 • Bits 7 and 6—I/O Control 0D1 and 0D0 (IO0D1, IO0D0): These bits select TIOD pin input capture signal edge detection. Bit 7: IO0D1 Bit 6: IO0D0 Description 0 0 Input capture disabled (input capture possible in TCNT10B compare-match) (Initial value) 1 Input capture in ICR0D on rising edge 0 Input capture in ICR0D on falling edge 1 Input capture in ICR0D on both rising and falling edges 1 • Bits 5 and 4—I/O Control 0C1 and 0C0 (IO0C1, IO0C0): These bits select TIOC pin input capture signal edge detection. Bit 5: IO0C1 Bit 4: IO0C0 Description 0 0 Input capture disabled 1 Input capture in ICR0C on rising edge 0 Input capture in ICR0C on falling edge 1 Input capture in ICR0C on both rising and falling edges 1 (Initial value) • Bits 3 and 2—I/O Control 0B1 and 0B0 (IO0B1, IO0B0): These bits select TIOB pin input capture signal edge detection. Bit 3: IO0B1 Bit 2: IO0B0 Description 0 0 Input capture disabled 1 Input capture in ICR0B on rising edge 0 Input capture in ICR0B on falling edge 1 Input capture in ICR0B on both rising and falling edges 1 (Initial value) • Bits 1 and 0—I/O Control 0A1 and 0A0 (IO0A1, IO0A0): These bits select TIOA pin input capture signal edge detection. Bit 1: IO0A1 Bit 0: IO0A0 Description 0 0 Input capture disabled 1 Input capture in ICR0A on rising edge 0 Input capture in ICR0A on falling edge 1 Input capture in ICR0A on both rising and falling edges 1 220 (Initial value) Timer I/O Control Registers 1A to 1D (TIOR1A to TIOR1D) TIOR1A Bit: 7 6 5 4 3 2 1 0 — IO1B2 IO1B1 IO1B0 — IO1A2 IO1A1 IO1A0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 — IO1D2 IO1D1 IO1D0 — IO1C2 IO1C1 IO1C0 TIOR1B Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 — IO1F2 IO1F1 IO1F0 — IO1E2 IO1E1 IO1E0 TIOR1C Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 — IO1H2 IO1H1 IO1H0 — IO1G2 IO1G1 IO1G0 TIOR1D Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Registers TIOR1A to TIOR1D specify whether general registers GR1A to GR1H are used as input capture or compare-match registers, and also perform edge detection and output value setting. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. 221 • Bits 6 to 4—I/O Control 1B2 to 1B0, 1D2 to 1D0, 1F2 to 1F0, 1H2 to 1H0 (IO1B2 to IO1B0, IO1D2 to IO1D0, IOF12 to IO1F0, IO1H2 to IO1H0): These bits select the general register (GR) function. Bit 6: IO1x2 Bit 5: IO1x1 Bit 4: IO1x0 0 0 0 1 1 0 1 Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 GR is an input capture register Input capture disabled (GR cannot be written to) 1 Input capture in GR on rising edge at TIO1x pin (GR cannot be written to) 0 Input capture in GR on falling edge at TIO1x pin (GR cannot be written to) 1 Input capture in GR on both rising and falling edges at TIO1x pin (GR cannot be written to) x = B, D, F, or H • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. 222 • Bits 2 to 0—I/O Control 1A2 to 1A0, 1C2 to 1C0, 1E2 to 1E0, 1G2 to 1G0 (IO1A2 to IO1A0, IO1C2 to IO1C0, IO1E2 to IO1E0, IO1G2 to IO1G0): These bits select the general register (GR) function. Bit 2: IO1x2 Bit 1: IO1x1 Bit 0: IO1x0 0 0 0 1 1 0 1 Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 GR is an input capture register Input capture disabled (GR cannot be written to) 1 Input capture in GR on rising edge at TIO1x pin (GR cannot be written to) 0 Input capture in GR on falling edge at TIO1x pin (GR cannot be written to) 1 Input capture in GR on both rising and falling edges at TIO1x pin (GR cannot be written to) 223 Timer I/O Control Registers 2A to 2D (TIOR2A to TIOR2D) TIOR2A Bit: 7 6 5 4 3 2 1 0 — IO2B2 IO2B1 IO2B0 — IO2A2 IO2A1 IO2A0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 — IO2D2 IO2D1 IO2D0 — IO2C2 IO2C1 IO2C0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 — IO2F2 IO2F1 IO2F0 — IO2E2 IO2E1 IO2E0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 — IO2H2 IO2H1 IO2H0 — IO2G2 IO2G1 IO2G0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W TIOR2B TIOR2C TIOR2D Registers TIOR2A to TIOR2D specify whether general registers GR2A to GR2H are used as input capture or compare-match registers, and also perform edge detection and output value setting. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. 224 • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bits 6 to 4—I/O Control 2B2 to 2B0, 2D2 to 2D0, 2F2 to 2F0, 2H2 to 2H0 (IO2B2 to IO2B0, IO2D2 to IO2D0, IO2F2 to IO2F0, IO2H2 to IO2H0): These bits select the general register (GR) function. Bit 6: IO2x2 Bit 5: IO2x1 Bit 4: IO2x0 0 0 0 1 1 0 1 Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 GR is an input capture register Input capture disabled 1 Input capture in GR on rising edge at TIO2x pin (GR cannot be written to) 0 Input capture in GR on falling edge at TIO2x pin (GR cannot be written to) 1 Input capture in GR on both rising and falling edges at TIO2x pin (GR cannot be written to) x = B, D, F, or H • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. 225 • Bits 2 to 0—I/O Control 2A2 to 2A0, 2C2 to 2C0, 2E2 to 2E0, 2G2 to 2G0 (IO2A2 to IO2A0, IO2C2 to IO2C0, IO2E2 to IO2E0, IO2G2 to IO2G0): These bits select the general register (GR) function. Bit 2: IO2x2 Bit 1: IO2x1 Bit 0: IO2x0 0 0 0 1 1 0 Description GR is an output compare register 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 1 Compare-match disabled; pin output undefined (Initial value) GR is an input capture register Input capture disabled 1 Input capture in GR on rising edge at TIO2x pin (GR cannot be written to) 0 Input capture in GR on falling edge at TIO2x pin (GR cannot be written to) 1 Input capture in GR on both rising and falling edges at TIO2x pin (GR cannot be written to) x = A, C, E, or G Timer I/O Control Registers 3A, 3B, 4A, 4B, 5A, 5B (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B) TIOR3A, TIOR4A, TIOR5A Bit: Initial value: R/W: x = 3 to 5 226 7 6 5 4 3 2 1 0 CCIxB IOxB2 IOxB1 IOxB0 CCIxA IOxA2 IOxA1 IOxA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TIOR3B, TIOR4B, TIOR5B Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 CCIxD IOxD2 IOxD1 IOxD0 CCIxC IOxC2 IOxC1 IOxC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W x = 3 to 5 TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, and TIOR5B specify whether general registers GR3A to GR3D, GR4A to GR4D, and GR5A to GR5D are used as input capture or comparematch registers, and also perform edge detection and output value setting. They also select enabling or disabling of free-running counter (TCNT3 to TCNT5) clearing. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Clear Counter Enable Flag 3B, 4B, 5B, 3D, 4D, 5D (CCI3B, CCI4B, CCI5B, CCI3D, CCI4D, CCI5D): These bits select enabling or disabling of free-running counter (TCNT) clearing. Bit 7: CCIxx Description 0 TCNT clearing disabled 1 TCNT cleared on GR compare-match (Initial value) xx = 3B, 4B, 5B, 3D, 4D, or 5D TCNT is cleared on compare-match only when GR is functioning as an output compare register. 227 • Bits 6 to 4—I/O Control 3B2 to 3B0, 4B2 to 4B0, 5B2 to 5B0, 3D2 to 3D0, 4D2 to 4D0, 5D2 to 5D0 (IO3B2 to IO3B0, IO4B2 to IO4B0, IO5B2 to IO5B0, IO3D2 to IO3D0, IO4D2 to IO4D0, IO5D2 to IO5D0): These bits select the general register (GR) function. Bit 6: IOxx2 Bit 5: IOxx1 Bit 4: IOxx0 0 0 0 1 1 0 1 Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 GR is an input capture register Input capture disabled (input capture by channel 3 and 9 compare-match enabled) (In channel 3 only, GR cannot be written to) 1 Input capture in GR on rising edge at TIOxx pin (GR cannot be written to) 0 Input capture in GR on falling edge at TIOxx pin (GR cannot be written to) 1 Input capture in GR on both rising and falling edges at TIOxx pin (GR cannot be written to) xx = 3B, 4B, 5B, 3D, 4D, or 5D • Bit 3—Clear Counter Enable Flag 3A, 4A, 5A, 3C, 4C, 5C (CCI3A, CCI4A, CCI5A, CCI3C, CCI4C, CCI5C): These bits select enabling or disabling of free-running counter (TCNT) clearing. Bit 3: CCIxx Description 0 TCNT clearing disabled 1 TCNT cleared on GR compare-match (Initial value) xx = 3A, 4A, 5A, 3C, 4C, or 5C TCNT is cleared on compare-match only when GR is functioning as an output compare register. 228 • Bits 2 to 0—I/O Control 3A2 to 3A0, 4A2 to 4A0, 5A2 to 5A0, 3C2 to 3C0, 4C2 to 4C0, 5C2 to 5C0 (IO3A2 to IO3A0, IO4A2 to IO4A0, IO5A2 to IO5A0, IO3C2 to IO3C0, IO4C2 to IO4C0, IO5C2 to IO5C0): These bits select the general register (GR) function. Bit 2: IOxx2 Bit 1: IOxx1 Bit 0: IOxx0 0 0 0 1 1 0 1 Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 GR is an input capture register Input capture disabled (input capture by channel 3 and 9 compare-match enabled) (In channel 3 only, GR cannot be written to) 1 Input capture in GR on rising edge at TIOxx pin (GR connot be written to) 0 Input capture in GR on falling edge at TIOxx pin (GR connot be written to) 1 Input capture in GR on both rising and falling edges at TIOxx pin (GR connot be written to) xx = 3A, 4A, 5A, 3C, 4C, or 5C 229 Timer I/O Control Register 11 (TIOR11) TIOR11 Bit: 7 6 5 4 3 2 1 0 — — — IO11B0 — — — IO11A0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R/W R/W R/W TIOR11 specifies whether general registers GR11A and GR11B are used as input capture or compare-match registers, and also performs edge detection and output value setting. TIOR11 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bits 7 to 5—Reserved: These bits always reads 0. The write value should always be 0. • Bit 4—I/O Control 11B0 (IO11B0): These bits select the general register (GR) function. Bit 4: IO11B0 Description 0 Compare-match is disabled 1 Ccompare-match is enabled (Initial value) • Bits 3 to 1—Reserved: These bits always reads 0. The write value should always be 0. • Bit 0—I/O Control 11A0 (IO11A0): This bit select the general register (GR) function. Bit 0: IO11A0 Description 0 Compare-match is disabled 1 Ccompare-match is enabled 230 (Initial value) 10.2.5 Timer Status Registers (TSR) The timer status registers (TSR) are 16-bit registers. The ATU-II has 11 TSR registers: one each for channels 0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5. For details of channel 10, see section 10.2.26, Channel 10 Registers. Channel Abbreviation Function 0 TSR0 Indicates input capture, interval interrupt, and overflow status 1 TSR1A, TSR1B Indicate input capture, compare-match, and overflow status 2 TSR2A, TSR2B 3 TSR3 Indicates input capture, compare-match, and overflow status 6 TSR6 Indicate cycle register compare-match status 7 TSR7 8 TSR8 Indicates down-counter output end (low) status 9 TSR9 Indicates event counter compare-match status 11 TSR11 Indicates compare-match and overflow status 4 5 The TSR registers are 16-bit readable/writable registers containing flags that indicate free-running counter (TCNT) overflow, channel 0 input capture or interval interrupt generation, channel 3, 4, 5, and 11 general register input capture or compare-match, channel 6 and 7 compare-matches, channel 8 down-counter output end, and channel 9 event counter compare-matches. Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is enabled by the corresponding bit in the timer interrupt enable register (TIER). Each TSR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. 231 Timer Status Register 0 (TSR0) TSR0 indicates the status of channel 0 interval interrupts, input capture, and overflow. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 IIF2B IIF2A IIF1 OVF0 ICF0D ICF0C ICF0B ICF0A 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial value: R/W: Note: * Only 0 can be written, to clear the flag. • Bits 15 to 8—Reserved: These bits always read 0. The write value should always be 0. • Bit 7—Interval Interrupt Flag 2B (IIF2B): Status flag that indicates the generation of an interval interrupt. Bit 7: IIF2B Description 0 [Clearing condition] When IIF2B is read while set to 1, then 0 is written to IIF2B 1 [Setting condition] When interval interrupt selected by ITVRR2B is generated (Initial value) • Bit 6—Interval Interrupt Flag 2A (IIF2A): Status flag that indicates the generation of an interval interrupt. Bit 6: IIF2A Description 0 [Clearing condition] When IIF2A is read while set to 1, then 0 is written to IIF2A 1 [Setting condition] When interval interrupt selected by ITVRR2A is generated 232 (Initial value) • Bit 5—Interval Interrupt Flag 1 (IIF1): Status flag that indicates the generation of an interval interrupt. Bit 5: IIF1 Description 0 [Clearing condition] When IIF1 is read while set to 1, then 0 is written to IIF1 1 [Setting condition] When interval interrupt selected by ITVRR1 is generated (Initial value) • Bit 4—Overflow Flag 0 (OVF0): Status flag that indicates TCNT0 overflow. Bit 4: OVF0 Description 0 [Clearing condition] When OVF0 is read while set to 1, then 0 is written to OVF0 1 [Setting condition] When the TCNT0 value overflows (from H'FFFFFFFF to H'00000000) (Initial value) • Bit 3—Input Capture Flag 0D (ICF0D): Status flag that indicates ICR0D input capture. Bit 3: ICF0D Description 0 [Clearing condition] When ICF0D is read while set to 1, then 0 is written to ICF0D 1 [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal. Also set by input capture with a channel 10 compare match as the trigger (Initial value) • Bit 2—Input Capture Flag 0C (ICF0C): Status flag that indicates ICR0C input capture. Bit 2: ICF0C Description 0 [Clearing condition] When ICF0C is read while set to 1, then 0 is written to ICF0C 1 [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal (Initial value) 233 • Bit 1—Input Capture Flag 0B (ICF0B): Status flag that indicates ICR0B input capture. Bit 1: ICF0B Description 0 [Clearing condition] When ICF0B is read while set to 1, then 0 is written to ICF0B 1 [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal (Initial value) • Bit 0—Input Capture Flag 0A (ICF0A): Status flag that indicates ICR0A input capture. Bit 0: ICF0A Description 0 [Clearing condition] When ICF0A is read while set to 1, then 0 is written to ICF0A 1 [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal (Initial value) Timer Status Registers 1A and 1B (TSR1A, TSR1B) TSR1A: TSR1A indicates the status of channel 1 input capture, compare-match, and overflow. Bit: 15 14 13 12 11 10 9 8 — — — — — — — OVF1A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/(W)* Bit: 7 6 5 4 3 2 1 0 IMF1H IMF1G IMF1F IMF1E IMF1D IMF1C IMF1B IMF1A 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial value: R/W: Note: * Only 0 can be written, to clear the flag. • Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0. 234 • Bit 8—Overflow Flag 1A (OVF1A): Status flag that indicates TCNT1A overflow. Bit 8: OVF1A Description 0 [Clearing condition] (Initial value) When OVF1A is read while set to 1, then 0 is written to OVF1A 1 [Setting condition] When the TCNT1A value overflows (from H'FFFF to H'0000) • Bit 7—Input Capture/Compare-Match Flag 1H (IMF1H): Status flag that indicates GR1H input capture or compare-match. Bit 7: IMF1H Description 0 [Clearing condition] When IMF1H is read while set to 1, then 0 is written to IMF1H 1 [Setting conditions] • When the TCNT1A value is transferred to GR1H by an input capture signal while GR1H is functioning as an input capture register • When TCNT1A = GR1H while GR1H is functioning as an output compare register (Initial value) • Bit 6—Input Capture/Compare-Match Flag 1G (IMF1G): Status flag that indicates GR1G input capture or compare-match. Bit 6: IMF1G Description 0 [Clearing condition] (Initial value) When IMF1G is read while set to 1, then 0 is written to IMF1G 1 [Setting conditions] • When the TCNT1A value is transferred to GR1G by an input capture signal while GR1G is functioning as an input capture register • When TCNT1A = GR1G while GR1G is functioning as an output compare register 235 • Bit 5—Input Capture/Compare-Match Flag 1F (IMF1F): Status flag that indicates GR1F input capture or compare-match. Bit 5: IMF1F Description 0 [Clearing condition] When IMF1F is read while set to 1, then 0 is written to IMF1F 1 [Setting conditions] • When the TCNT1A value is transferred to GR1F by an input capture signal while GR1F is functioning as an input capture register • When TCNT1A = GR1F while GR1F is functioning as an output compare register (Initial value) • Bit 4—Input Capture/Compare-Match Flag 1E (IMF1E): Status flag that indicates GR1E input capture or compare-match. Bit 4: IMF1E Description 0 [Clearing condition] When IMF1E is read while set to 1, then 0 is written to IMF1E 1 [Setting conditions] • When the TCNT1A value is transferred to GR1E by an input capture signal while GR1E is functioning as an input capture register • When TCNT1A = GR1E while GR1E is functioning as an output compare register (Initial value) • Bit 3—Input Capture/Compare-Match Flag 1D (IMF1D): Status flag that indicates GR1D input capture or compare-match. Bit 3: IMF1D Description 0 [Clearing condition] When IMF1D is read while set to 1, then 0 is written to IMF1D 1 [Setting conditions] • When the TCNT1A value is transferred to GR1D by an input capture signal while GR1D is functioning as an input capture register • When TCNT1A = GR1D while GR1D is functioning as an output compare register 236 (Initial value) • Bit 2—Input Capture/Compare-Match Flag 1C (IMF1C): Status flag that indicates GR1C input capture or compare-match. Bit 2: IMF1C Description 0 [Clearing condition] When IMF1C is read while set to 1, then 0 is written to IMF1C 1 [Setting conditions] • When the TCNT1A value is transferred to GR1C by an input capture signal while GR1C is functioning as an input capture register • When TCNT1A = GR1C while GR1C is functioning as an output compare register (Initial value) • Bit 1—Input Capture/Compare-Match Flag 1B (IMF1B): Status flag that indicates GR1B input capture or compare-match. Bit 1: IMF1B Description 0 [Clearing condition] When IMF1B is read while set to 1, then 0 is written to IMF1B 1 [Setting conditions] • When the TCNT1A value is transferred to GR1B by an input capture signal while GR1B is functioning as an input capture register • When TCNT1A = GR1B while GR1B is functioning as an output compare register (Initial value) • Bit 0—Input Capture/Compare-Match Flag 1A (IMF1A): Status flag that indicates GR1A input capture or compare-match. Bit 0: IMF1A Description 0 [Clearing condition] When IMF1A is read while set to 1, then 0 is written to IMF1A 1 [Setting conditions] • When the TCNT1A value is transferred to GR1A by an input capture signal while GR1A is functioning as an input capture register • When TCNT1A = GR1A while GR1A is functioning as an output compare register (Initial value) 237 TSR1B: TSR1B indicates the status of channel 1 compare-match and overflow. Bit: 15 14 13 12 11 10 9 8 — — — — — — — OVF1B Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/(W)* Bit: 7 6 5 4 3 2 1 0 — — — — — — — CMF1 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/(W)* Note: * Only 0 can be written, to clear the flag. • Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0. • Bit 8—Overflow Flag 1B (OVF1B): Status flag that indicates TCNT1B overflow. Bit 8: OVF1B Description 0 [Clearing condition] (Initial value) When OVF1B is read while set to 1, then 0 is written to OVF1B 1 [Setting condition] When the TCNT1B value overflows (from H'FFFF to H'0000) • Bits 7 to 1—Reserved: These bits always read 0. The write value should always be 0. • Bit 0—Compare-Match Flag 1 (CMF1): Status flag that indicates OCR1 compare-match. Bit 0: CMF1 Description 0 [Clearing condition] When CMF1 is read while set to 1, then 0 is written to CMF1 1 [Setting condition] When TCNT1B = OCR1 238 (Initial value) Timer Status Registers 2A and 2B (TSR2A, TSR2B) TSR2A: TSR2A indicates the status of channel 2 input capture, compare-match, and overflow. Bit: 15 14 13 12 11 10 9 8 — — — — — — — OVF2A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/(W)* Bit: 7 6 5 4 3 2 1 0 IMF2H IMF2G IMF2F IMF2E IMF2D IMF2C IMF2B IMF2A 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial value: R/W: Note: * Only 0 can be written, to clear the flag. • Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0. • Bit 8—Overflow Flag 2A (OVF2A): Status flag that indicates TCNT2A overflow. Bit 8: OVF2A Description 0 [Clearing condition] (Initial value) When OVF2A is read while set to 1, then 0 is written to OVF2A 1 [Setting condition] When the TCNT2A value overflows (from H'FFFF to H'0000) • Bit 7—Input Capture/Compare-Match Flag 2H (IMF2H): Status flag that indicates GR2H input capture or compare-match. Bit 7: IMF2H Description 0 [Clearing condition] When IMF2H is read while set to 1, then 0 is written to IMF2H 1 [Setting conditions] • When the TCNT2A value is transferred to GR2H by an input capture signal while GR2H is functioning as an input capture register • When TCNT2A = GR2H while GR2H is functioning as an output compare register (Initial value) 239 • Bit 6—Input Capture/Compare-Match Flag 2G (IMF2G): Status flag that indicates GR2G input capture or compare-match. Bit 6: IMF2G Description 0 [Clearing condition] (Initial value) When IMF2G is read while set to 1, then 0 is written to IMF2G 1 [Setting conditions] • When the TCNT2A value is transferred to GR2G by an input capture signal while GR2G is functioning as an input capture register • When TCNT2A = GR2G while GR2G is functioning as an output compare register • Bit 5—Input Capture/Compare-Match Flag 2F (IMF2F): Status flag that indicates GR2F input capture or compare-match. Bit 5: IMF2F Description 0 [Clearing condition] When IMF2F is read while set to 1, then 0 is written to IMF2F 1 [Setting conditions] • When the TCNT2A value is transferred to GR2F by an input capture signal while GR2F is functioning as an input capture register • When TCNT2A = GR2F while GR2F is functioning as an output compare register (Initial value) • Bit 4—Input Capture/Compare-Match Flag 2E (IMF2E): Status flag that indicates GR2E input capture or compare-match. Bit 4: IMF2E Description 0 [Clearing condition] When IMF2E is read while set to 1, then 0 is written to IMF2E 1 [Setting conditions] • When the TCNT2A value is transferred to GR2E by an input capture signal while GR2E is functioning as an input capture register • When TCNT2A = GR2E while GR2E is functioning as an output compare register 240 (Initial value) • Bit 3—Input Capture/Compare-Match Flag 2D (IMF2D): Status flag that indicates GR2D input capture or compare-match. Bit 3: IMF2D Description 0 [Clearing condition] When IMF2D is read while set to 1, then 0 is written to IMF2D 1 [Setting conditions] • When the TCNT2A value is transferred to GR2D by an input capture signal while GR2D is functioning as an input capture register • When TCNT2A = GR2D while GR2D is functioning as an output compare register (Initial value) • Bit 2—Input Capture/Compare-Match Flag 2C (IMF2C): Status flag that indicates GR2C input capture or compare-match. Bit 2: IMF2C Description 0 [Clearing condition] When IMF2C is read while set to 1, then 0 is written to IMF2C 1 [Setting conditions] • When the TCNT2A value is transferred to GR2C by an input capture signal while GR2C is functioning as an input capture register • When TCNT2A = GR2C while GR2C is functioning as an output compare register (Initial value) • Bit 1—Input Capture/Compare-Match Flag 2B (IMF2B): Status flag that indicates GR2B input capture or compare-match. Bit 1: IMF2B Description 0 [Clearing condition] When IMF2B is read while set to 1, then 0 is written to IMF2B 1 [Setting conditions] • • (Initial value) When the TCNT2A value is transferred to GR2B by an input capture signal while GR2B is functioning as an input capture register When TCNT2A = GR2B while GR2B is functioning as an output compare register 241 • Bit 0—Input Capture/Compare-Match Flag 2A (IMF2A): Status flag that indicates GR2A input capture or compare-match. Bit 0: IMF2A Description 0 [Clearing condition] When IMF2A is read while set to 1, then 0 is written to IMF2A 1 [Setting conditions] • When the TCNT2A value is transferred to GR2A by an input capture signal while GR2A is functioning as an input capture register • When TCNT2A = GR2A while GR2A is functioning as an output compare register (Initial value) TSR2B: TSR2B indicates the status of channel 2 compare-match and overflow. Bit: 15 14 13 12 11 10 9 8 — — — — — — — OVF2B Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/(W)* Bit: 7 6 5 4 3 2 1 0 CMF2H Initial value: R/W: CMF2G CMF2F CMF2E CMF2D CMF2C CMF2B CMF2A 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. • Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0. • Bit 8—Overflow Flag 2B (OVF2B): Status flag that indicates TCNT2B overflow. Bit 8: OVF2B Description 0 [Clearing condition] (Initial value) When OVF2B is read while set to 1, then 0 is written to OVF2B 1 [Setting condition] When the TCNT2B value overflows (from H'FFFF to H'0000) 242 • Bit 7—Compare-Match Flag 2H (CMF2H): Status flag that indicates OCR2H compare-match. Bit 7: CMF2H Description 0 [Clearing condition] (Initial value) When CMF2H is read while set to 1, then 0 is written to CMF2H 1 [Setting condition] When TCNT2B = OCR2H • Bit 6—Compare-Match Flag 2G (CMF2G): Status flag that indicates OCR2G compare-match. Bit 6: CMF2G Description 0 [Clearing condition] (Initial value) When CMF2G is read while set to 1, then 0 is written to CMF2G 1 [Setting condition] When TCNT2B = OCR2G • Bit 5—Compare-Match Flag 2F (CMF2F): Status flag that indicates OCR2F compare-match. Bit 5: CMF2F Description 0 [Clearing condition] (Initial value) When CMF2F is read while set to 1, then 0 is written to CMF2F 1 [Setting condition] When TCNT2B = OCR2F • Bit 4—Compare-Match Flag 2E (CMF2E): Status flag that indicates OCR2E compare-match. Bit 4: CMF2E Description 0 [Clearing condition] (Initial value) When CMF2E is read while set to 1, then 0 is written to CMF2E 1 [Setting condition] When TCNT2B = OCR2E • Bit 3—Compare-Match Flag 2D (CMF2D): Status flag that indicates OCR2D compare-match. Bit 3: CMF2D Description 0 [Clearing condition] (Initial value) When CMF2D is read while set to 1, then 0 is written to CMF2D 1 [Setting condition] When TCNT2B = OCR2D 243 • Bit 2—Compare-Match Flag 2C (CMF2C): Status flag that indicates OCR2C compare-match. Bit 2: CMF2C Description 0 [Clearing condition] (Initial value) When CMF2C is read while set to 1, then 0 is written to CMF2C 1 [Setting condition] When TCNT2B = OCR2C • Bit 1—Compare-Match Flag 2B (CMF2B): Status flag that indicates OCR2B compare-match. Bit 1: CMF2B Description 0 [Clearing condition] (Initial value) When CMF2B is read while set to 1, then 0 is written to CMF2B 1 [Setting condition] When TCNT2B = OCR2B • Bit 0—Compare-Match Flag 2A (CMF2A): Status flag that indicates OCR2A compare-match. Bit 0: CMF2A Description 0 [Clearing condition] (Initial value) When CMF2A is read while set to 1, then 0 is written to CMF2A 1 [Setting condition] When TCNT2B = OCR2A Timer Status Register 3 (TSR3) TSR3 indicates the status of channel 3 to 5 input capture, compare-match, and overflow. Bit: 15 14 13 12 11 10 9 8 — OVF5 IMF5D IMF5C IMF5B IMF5A OVF4 IMF4D Initial value: 0 0 0 0 0 0 0 0 R/W: R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Bit: 7 6 5 4 3 2 1 0 IMF4C IMF4B IMF4A OVF3 IMF3D IMF3C IMF3B IMF3A 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial value: R/W: Note: * Only 0 can be written, to clear the flag. 244 • Bit 15—Reserved: This bit always reads 0. The write value should always be 0. • Bit 14—Overflow Flag 5 (OVF5): Status flag that indicates TCNT5 overflow. Bit 14: OVF5 Description 0 [Clearing condition] When OVF5 is read while set to 1, then 0 is written to OVF5 1 [Setting condition] When the TCNT5 value overflows (from H'FFFF to H'0000) (Initial value) • Bit 13—Input Capture/Compare-Match Flag 5D (IMF5D): Status flag that indicates GR5D input capture or compare-match. Bit 13: IMF5D Description 0 [Clearing condition] When IMF5D is read while set to 1, then 0 is written to IMF5D 1 [Setting conditions] • When the TCNT5 value is transferred to GR5D by an input capture signal while GR5D is functioning as an input capture register • When TCNT5 = GR5D while GR5D is functioning as an output compare register • When TCNT5 = GR5D while GR5D is functioning as a synchronous register in PWM mode (Initial value) • Bit 12—Input Capture/Compare-Match Flag 5C (IMF5C): Status flag that indicates GR5C input capture or compare-match. The flag is not set in PWM mode. Bit 12: IMF5C Description 0 [Clearing condition] When IMF5C is read while set to 1, then 0 is written to IMF5C 1 [Setting conditions] • When the TCNT5 value is transferred to GR5C by an input capture signal while GR5C is functioning as an input capture register • When TCNT5 = GR5C while GR5C is functioning as an output compare register (Initial value) 245 • Bit 11—Input Capture/Compare-Match Flag 5B (IMF5B): Status flag that indicates GR5B input capture or compare-match. The flag is not set in PWM mode. Bit 11: IMF5B Description 0 [Clearing condition] When IMF5B is read while set to 1, then 0 is written to IMF5B 1 [Setting conditions] • When the TCNT5 value is transferred to GR5B by an input capture signal while GR5B is functioning as an input capture register • When TCNT5 = GR5B while GR5B is functioning as an output compare register (Initial value) • Bit 10—Input Capture/Compare-Match Flag 5A (IMF5A): Status flag that indicates GR5A input capture or compare-match. The flag is not set in PWM mode. Bit 10: IMF5A Description 0 [Clearing condition] When IMF5A is read while set to 1, then 0 is written to IMF5A 1 [Setting conditions] • When the TCNT5 value is transferred to GR5A by an input capture signal while GR5A is functioning as an input capture register • When TCNT5 = GR5A while GR5A is functioning as an output compare register (Initial value) • Bit 9—Overflow Flag 4 (OVF4): Status flag that indicates TCNT4 overflow. Bit 9: OVF4 Description 0 [Clearing condition] When OVF4 is read while set to 1, then 0 is written to OVF4 1 [Setting condition] When the TCNT4 value overflows (from H'FFFF to H'0000) 246 (Initial value) • Bit 8—Input Capture/Compare-Match Flag 4D (IMF4D): Status flag that indicates GR4D input capture or compare-match. Bit 8: IMF4D Description 0 [Clearing condition] When IMF4D is read while set to 1, then 0 is written to IMF4D 1 [Setting conditions] • When the TCNT4 value is transferred to GR4D by an input capture signal while GR4D is functioning as an input capture register • When TCNT4 = GR4D while GR4D is functioning as an output compare register • When TCNT4 = GR4D while GR4D is functioning as a PWM mode synchronous register (Initial value) • Bit 7—Input Capture/Compare-Match Flag 4C (IMF4C): Status flag that indicates GR4C input capture or compare-match. The flag is not set in PWM mode. Bit 7: IMF4C Description 0 [Clearing condition] When IMF4C is read while set to 1, then 0 is written to IMF4C 1 [Setting conditions] • When the TCNT4 value is transferred to GR4C by an input capture signal while GR4C is functioning as an input capture register • When TCNT4 = GR4C while GR4C is functioning as an output compare register (Initial value) • Bit 6—Input Capture/Compare-Match Flag 4B (IMF4B): Status flag that indicates GR4B input capture or compare-match. The flag is not set in PWM mode. Bit 6: IMF4B Description 0 [Clearing condition] When IMF4B is read while set to 1, then 0 is written to IMF4B 1 [Setting conditions] • When the TCNT4 value is transferred to GR4B by an input capture signal while GR4B is functioning as an input capture register • When TCNT4 = GR4B while GR4B is functioning as an output compare register (Initial value) 247 • Bit 5—Input Capture/Compare-Match Flag 4A (IMF4A): Status flag that indicates GR4A input capture or compare-match. The flag is not set in PWM mode. Bit 5: IMF4A Description 0 [Clearing condition] When IMF4A is read while set to 1, then 0 is written to IMF4A 1 [Setting conditions] • When the TCNT4 value is transferred to GR4A by an input capture signal while GR4A is functioning as an input capture register • When TCNT4 = GR4A while GR4A is functioning as an output compare register (Initial value) • Bit 4—Overflow Flag 3 (OVF3): Status flag that indicates TCNT3 input capture or comparematch. Bit 4: OVF3 Description 0 [Clearing condition] When OVF3 is read while set to 1, then 0 is written to OVF3 1 [Setting condition] When the TCNT3 value overflows (from H'FFFF to H'0000) (Initial value) • Bit 3—Input Capture/Compare-Match Flag 3D (IMF3D): Status flag that indicates GR5D input capture or compare-match. Bit 3: IMF3D Description 0 [Clearing condition] When IMF3D is read while set to 1, then 0 is written to IMF3D 1 [Setting conditions] • When the TCNT3 value is transferred to GR3D by an input capture signal while GR3D is functioning as an input capture register. However, IMF3D is not set by input capture with a channel 9 compare match as the trigger • When TCNT3 = GR3D while GR3D is functioning as an output compare register • When TCNT3 = GR3D while GR3D is functioning as a synchronous register in PWM mode 248 (Initial value) • Bit 2—Input Capture/Compare-Match Flag 3C (IMF3C): Status flag that indicates GR3C input capture or compare-match. The flag is not set in PWM mode. Bit 2: IMF3C Description 0 [Clearing condition] When IMF3C is read while set to 1, then 0 is written to IMF3C 1 [Setting conditions] • When the TCNT3 value is transferred to GR3C by an input capture signal while GR3C is functioning as an input capture register. However, IMF3C is not set by input capture with a channel 9 compare match as the trigger • When TCNT3 = GR3C while GR3C is functioning as an output compare register (Initial value) • Bit 1—Input Capture/Compare-Match Flag 3B (IMF3B): Status flag that indicates GR3B input capture or compare-match. The flag is not set in PWM mode. Bit 1: IMF3B Description 0 [Clearing condition] When IMF3B is read while set to 1, then 0 is written to IMF3B 1 [Setting conditions] • When the TCNT3 value is transferred to GR3B by an input capture signal while GR3B is functioning as an input capture register. However, IMF3B is not set by input capture with a channel 9 compare match as the trigger • When TCNT3 = GR3B while GR3B is functioning as an output compare register (Initial value) • Bit 0—Input Capture/Compare-Match Flag 3A (IMF3A): Status flag that indicates GR3A input capture or compare-match. The flag is not set in PWM mode. Bit 0: IMF3A Description 0 [Clearing condition] When IMF3A is read while set to 1, then 0 is written to IMF3A 1 [Setting conditions] • When the TCNT3 value is transferred to GR3A by an input capture signal while GR3A is functioning as an input capture register. However, IMF3A is not set by input capture with a channel 9 compare match as the trigger • When TCNT3 = GR3A while GR3A is functioning as an output compare register (Initial value) 249 Timer Status Registers 6 and 7 (TSR6, TSR7) TSR6 and TRS7 indicate the channel 6 and 7 free-running counter up-count and down-count status, and cycle register compare status. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 UDxD UDxC UDxB UDxA CMFxD CMFxC CMFxB CMFxA Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. x = 6 or 7 UDxA to UDxD relate to TSR6 only. Bits relating to TSR7 always read 0. • Bits 15 to 8—Reserved: These bits always read 0. The write value should always be 0. • Bit 7—Count-Up/Count-Down Flag 6D (UD6D): Status flag that indicates the TCNT6D count operation. Bit 7: UD6D Description 0 Free-running counter TCNT6D operates as an up-counter 1 Free-running counter TCNT6D operates as a down-counter • Bit 6—Count-Up/Count-Down Flag 6C (UD6C): Status flag that indicates the TCNT6C count operation. Bit 6: UD6C Description 0 Free-running counter TCNT6C operates as an up-counter 1 Free-running counter TCNT6C operates as a down-counter 250 • Bit 5—Count-Up/Count-Down Flag 6B (UD6B): Status flag that indicates the TCNT6B count operation. Bit 5: UD6B Description 0 Free-running counter TCNT6B operates as an up-counter 1 Free-running counter TCNT6B operates as a down-counter • Bit 4—Count-Up/Count-Down Flag 6A (UD6A): Status flag that indicates the TCNT6A count operation. Bit 4: UD6A Description 0 Free-running counter TCNT6A operates as an up-counter 1 Free-running counter TCNT6A operates as a down-counter • Bit 3—Cycle Register Compare-Match Flag 6D/7D (CMF6D/CMF7D): Status flag that indicates CYLRxD compare-match. Bit 3: CMFxD Description 0 [Clearing condition] (Initial value) When CMFxD is read while set to 1, then 0 is written to CMFxD 1 [Setting conditions] • When TCNTxD = CYLRxD (in non-complementary PWM mode) • When TCNT6D = H'0000 in a down-count (in complementary PWM mode) x = 6 or 7 • Bit 2—Cycle Register Compare-Match Flag 6C/7C (CMF6C/CMF7C): Status flag that indicates CYLRxC compare-match. Bit 2: CMFxC Description 0 [Clearing condition] (Initial value) When CMFxC is read while set to 1, then 0 is written to CMFxC 1 [Setting conditions] • When TCNTxC = CYLRxC (in non-complementary PWM mode) • When TCNT6C = H'0000 in a down-count (in complementary PWM mode) x = 6 or 7 251 • Bit 1—Cycle Register Compare-Match Flag 6B/7B (CMF6B/CMF7B): Status flag that indicates CYLRxB compare-match. Bit 1: CMFxB Description 0 [Clearing condition] (Initial value) When CMFxB is read while set to 1, then 0 is written to CMFxB 1 [Setting conditions] • When TCNTxB = CYLRxB (in non-complementary PWM mode) • When TCNT6B = H'0000 in a down-count (in complementary PWM mode) x = 6 or 7 • Bit 0—Cycle Register Compare-Match Flag 6A/7A (CMF6A/CMF7A): Status flag that indicates CYLRxA compare-match. Bit 0: CMFxA Description 0 [Clearing condition] (Initial value) When CMFxA is read while set to 1, then 0 is written to CMFxA 1 [Setting conditions] • When TCNTxA = CYLRxA (in non-complementary PWM mode) • When TCNT6A = H'0000 in a down-count (in complementary PWM mode) x = 6 or 7 Timer Status Register 8 (TSR8) TSR8 indicates the channel 8 one-shot pulse status. Bit: Initial value: R/W: Bit: 15 14 OSF8P OSF8O 0 0 0 0 R/(W)* R/(W)* R/(W)* 7 6 OSF8H OSF8G Initial value: R/W: 13 10 9 8 11 OSF8K OSF8J OSF8I 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 5 4 3 2 1 0 OSF8F OSF8E OSF8D OSF8C OSF8B OSF8A OSF8N OSF8M OSF8L 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. 252 12 • Bit 15—One-Shot Pulse Flag 8P (OSF8P): Status flag that indicates a DCNT8P one-shot pulse. Bit 15: OSF8P Description 0 [Clearing condition] (Initial value) When OSF8P is read while set to 1, then 0 is written to OSF8P 1 [Setting condition] When DCNT8P underflows • Bit 14—One-Shot Pulse Flag 8O (OSF8O): Status flag that indicates a DCNT8O one-shot pulse. Bit 14: OSF8O Description 0 [Clearing condition] (Initial value) When OSF8O is read while set to 1, then 0 is written to OSF8O 1 [Setting condition] When DCNT8O underflows • Bit 13—One-Shot Pulse Flag 8N (OSF8N): Status flag that indicates a DCNT8N one-shot pulse. Bit 13: OSF8N Description 0 [Clearing condition] (Initial value) When OSF8N is read while set to 1, then 0 is written to OSF8N 1 [Setting condition] When DCNT8N underflows • Bit 12—One-Shot Pulse Flag 8M (OSF8M): Status flag that indicates a DCNT8M one-shot pulse. Bit 12: OSF8M Description 0 [Clearing condition] (Initial value) When OSF8M is read while set to 1, then 0 is written to OSF8M 1 [Setting condition] When DCNT8M underflows 253 • Bit 11—One-Shot Pulse Flag 8L (OSF8L): Status flag that indicates a DCNT8L one-shot pulse. Bit 11: OSF8L Description 0 [Clearing condition] (Initial value) When OSF8L is read while set to 1, then 0 is written to OSF8L 1 [Setting condition] When DCNT8L underflows • Bit 10—One-Shot Pulse Flag 8K (OSF8K): Status flag that indicates a DCNT8K one-shot pulse. Bit 10: OSF8K Description 0 [Clearing condition] (Initial value) When OSF8K is read while set to 1, then 0 is written to OSF8K 1 [Setting condition] When DCNT8K underflows • Bit 9—One-Shot Pulse Flag 8J (OSF8J): Status flag that indicates a DCNT8J one-shot pulse. Bit 9: OSF8J Description 0 [Clearing condition] (Initial value) When OSF8J is read while set to 1, then 0 is written to OSF8J 1 [Setting condition] When DCNT8J underflows • Bit 8—One-Shot Pulse Flag 8I (OSF8I): Status flag that indicates a DCNT8I one-shot pulse. Bit 8: OSF8I Description 0 [Clearing condition] When OSF8I is read while set to 1, then 0 is written to OSF8I 1 [Setting condition] When DCNT8I underflows 254 (Initial value) • Bit 7—One-Shot Pulse Flag 8H (OSF8H): Status flag that indicates a DCNT8H one-shot pulse. Bit 7: OSF8H Description 0 [Clearing condition] (Initial value) When OSF8H is read while set to 1, then 0 is written to OSF8H 1 [Setting condition] When DCNT8H underflows • Bit 6—One-Shot Pulse Flag 8G (OSF8G): Status flag that indicates a DCNT8G one-shot pulse. Bit 6: OSF8G Description 0 [Clearing condition] (Initial value) When OSF8G is read while set to 1, then 0 is written to OSF8G 1 [Setting condition] When DCNT8G underflows • Bit 5—One-Shot Pulse Flag 8F (OSF8F): Status flag that indicates a DCNT8F one-shot pulse. Bit 5: OSF8F Description 0 [Clearing condition] (Initial value) When OSF8F is read while set to 1, then 0 is written to OSF8F 1 [Setting condition] When DCNT8F underflows • Bit 4—One-Shot Pulse Flag 8E (OSF8E): Status flag that indicates a DCNT8E one-shot pulse. Bit 4: OSF8E Description 0 [Clearing condition] (Initial value) When OSF8E is read while set to 1, then 0 is written to OSF8E 1 [Setting condition] When DCNT8E underflows 255 • Bit 3—One-Shot Pulse Flag 8D (OSF8D): Status flag that indicates a DCNT8D one-shot pulse. Bit 3: OSF8D Description 0 [Clearing condition] (Initial value) When OSF8D is read while set to 1, then 0 is written to OSF8D 1 [Setting condition] When DCNT8D underflows • Bit 2—One-Shot Pulse Flag 8C (OSF8C): Status flag that indicates a DCNT8C one-shot pulse. Bit 2: OSF8C Description 0 [Clearing condition] (Initial value) When OSF8C is read while set to 1, then 0 is written to OSF8C 1 [Setting condition] When DCNT8C underflows • Bit 1—One-Shot Pulse Flag 8B (OSF8B): Status flag that indicates a DCNT8B one-shot pulse. Bit 1: OSF8B Description 0 [Clearing condition] (Initial value) When OSF8B is read while set to 1, then 0 is written to OSF8B 1 [Setting condition] When DCNT8B underflows • Bit 0—One-Shot Pulse Flag 8A (OSF8A): Status flag that indicates a DCNT8A one-shot pulse. Bit 0: OSF8A Description 0 [Clearing condition] (Initial value) When OSF8A is read while set to 1, then 0 is written to OSF8A 1 [Setting condition] When DCNT8A underflows 256 Timer Status Register 9 (TSR9) TSR9 indicates the channel 9 event counter compare-match status. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — CMF9F Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* CMF9E CMF9D CMF9C CMF9B CMF9A Note: * Only 0 can be written, to clear the flag. • Bits 15 to 6—Reserved: These bits always read 0. The write value should always be 0. • Bit 5—Compare-Match Flag 9F (CMF9F): Status flag that indicates GR9F compare-match. Bit 5: CMF9F Description 0 [Clearing condition] (Initial value) When CMF9F is read while set to 1, then 0 is written to CMF9F 1 [Setting condition] When the next edge is input while ECNT9F = GR9F • Bit 4—Compare-Match Flag 9E (CMF9E): Status flag that indicates GR9E compare-match. Bit 4: CMF9E Description 0 [Clearing condition] (Initial value) When CMF9E is read while set to 1, then 0 is written to CMF9E 1 [Setting condition] When the next edge is input while ECNT9E = GR9E 257 • Bit 3—Compare-Match Flag 9D (CMF9D): Status flag that indicates GR9D compare-match. Bit 3: CMF9D Description 0 [Clearing condition] (Initial value) When CMF9D is read while set to 1, then 0 is written to CMF9D 1 [Setting condition] When the next edge is input while ECNT9D = GR9D • Bit 2—Compare-Match Flag 9C (CMF9C): Status flag that indicates GR9C compare-match. Bit 2: CMF9C Description 0 [Clearing condition] (Initial value) When CMF9C is read while set to 1, then 0 is written to CMF9C 1 [Setting condition] When the next edge is input while ECNT9C = GR9C • Bit 1—Compare-Match Flag 9B (CMF9B): Status flag that indicates GR9B compare-match. Bit 1: CMF9B Description 0 [Clearing condition] (Initial value) When CMF9B is read while set to 1, then 0 is written to CMF9B 1 [Setting condition] When the next edge is input while ECNT9B = GR9B • Bit 0—Compare-Match Flag 9A (CMF9A): Status flag that indicates GR9A compare-match. Bit 0: CMF9A Description 0 [Clearing condition] (Initial value) When CMF9A is read while set to 1, then 0 is written to CMF9A 1 [Setting condition] When the next edge is input while ECNT9A = GR9A 258 Timer Status Register 11 (TSR11) TSR11 indicates the status of channel 11 compare-match and overflow. Bit: 15 14 13 12 11 10 9 8 — — — — — — — OVF11 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/(W)* Bit: 7 6 5 4 3 2 1 0 — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/(W)* R/(W)* IMF11B IMF11A Note: * Only 0 can be written, to clear the flag. • Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0. • Bit 8—Overflow Flag 11 (OVF11): Status flag that indicates TCNT11 overflow. Bit 8: OVF11 Description 0 [Clearing condition] (Initial value) When OVF11 is read while set to 1, then 0 is written to OVF11 1 [Setting condition] When the TCNT11 value overflows (from H'FFFF to H'0000) • Bits 7 to 2—Reserved: These bits always read 0. The write value should always be 0. • Bit 1—Compare-Match Flag 11B (IMF11B): Status flag that indicates GR11B compare-match. Bit 1: IMF11B Description 0 [Clearing condition] (Initial value) When IMF11B is read while set to 1, then 0 is written to IMF11B 1 [Setting condition] When TCNT11 = GR11B while GR11B is functioning as an output compare register 259 • Bit 0—Compare-Match Flag 11A (IMF11A): Status flag that indicates GR11A comparematch. Bit 0: IMF11A Description 0 [Clearing condition] (Initial value) When IMF11A is read while set to 1, then 0 is written to IMF11A 1 [Setting condition] When TCNT11 = GR11A while GR11A is functioning as an output compare register 10.2.6 Timer Interrupt Enable Registers (TIER) The timer interrupt enable registers (TIER) are 16-bit registers. The ATU-II has 11 TIER registers: one each for channels 0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5. For details of channel 10, see section 10.2.26, Channel 10 Registers. Channel Abbreviation Function 0 TIER0 Controls input capture, and overflow interrupt request enabling/disabling. 1 TIER1A, TIER1B 2 TIER2A, TIER2B Control input capture, compare-match, and overflow interrupt request enabling/disabling. 3 TIER3 Controls input capture, compare-match, and overflow interrupt request enabling/disabling. 6 TIER6 7 TIER7 Control cycle register compare-match interrupt request enabling/disabling. 8 TIER8 Controls down-counter output end (low) interrupt request enabling/disabling. 9 TIER9 Controls event counter compare-match interrupt request enabling/disabling. 11 TIER11 Controls input capture, compare-match, and overflow interrupt request enabling/disabling. 4 5 The TIER registers are 16-bit readable/writable registers that control enabling and disabling of timer interrupt requests. These cover free-running counter (TCNT) overflow interrupts, channel 0 input capture interrupts, channel 1 to 5 general register input capture/compare-match interrupts, channel 6 and 7 compare-match interrupts, channel 8 down-counter output pin interrupts, channel 9 event counter compare-match interrupts, and channel 11 general register compare-match interrupts. 260 Each TIER is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Timer Interrupt Enable Register 0 (TIER0) TIER0 controls enabling/disabling of channel 0 input capture and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — OVE0 ICE0D ICE0C ICE0B ICE0A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W • Bits 15 to 5—Reserved: These bits always read 0. The write value should always be 0. • Bit 4—Overflow Interrupt Enable 0 (OVE0): Enables or disables interrupt requests by the overflow flag (OVF0) in TSR0 when OVF0 is set to 1. Bit 4: OVE0 Description 0 OVI0 interrupt requested by OVF0 is disabled 1 OVI0 interrupt requested by OVF0 is enabled (Initial value) • Bit 3—Input Capture Interrupt Enable 0D (ICE0D): Enables or disables interrupt requests by the input capture flag (ICF0D) in TSR0 when ICF0D is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 3: ICE0D Description 0 ICI0D interrupt requested by ICF0D is disabled 1 ICI0D interrupt requested by ICF0D is enabled (Initial value) 261 • Bit 2—Input Capture Interrupt Enable 0C (ICE0C): Enables or disables interrupt requests by the input capture flag (ICF0C) in TSR0 when ICF0C is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 2: ICE0C Description 0 ICI0C interrupt requested by ICF0C is disabled 1 ICI0C interrupt requested by ICF0C is enabled (Initial value) • Bit 1—Input Capture Interrupt Enable 0B (ICE0B): Enables or disables interrupt requests by the input capture flag (ICF0B) in TSR0 when ICF0B is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 1: ICE0B Description 0 ICI0B interrupt requested by ICF0B is disabled 1 ICI0B interrupt requested by ICF0B is enabled (Initial value) • Bit 0—Input Capture Interrupt Enable 0A (ICE0A): Enables or disables interrupt requests by the input capture flag (ICF0A) in TSR0 when ICF0A is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 0: ICE0A Description 0 ICI0A interrupt requested by ICF0A is disabled 1 ICI0A interrupt requested by ICF0A is enabled (Initial value) Timer Interrupt Enable Registers 1A and 1B (TIER1A, TIER1B) TIER1A: TIER1A controls enabling/disabling of channel 1 input capture, compare-match, and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 — — — — — — — OVE1A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 IME1H IME1G IME1F IME1E IME1D IME1C IME1B IME1A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: 262 • Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0. • Bit 8—Overflow Interrupt Enable 1A (OVE1A): Enables or disables interrupt requests by OVF1A in TSR1A when OVF1A is set to 1. Bit 8: OVE1A Description 0 OVI1A interrupt requested by OVF1A is disabled 1 OVI1A interrupt requested by OVF1A is enabled (Initial value) • Bit 7—Input Capture/Compare-Match Interrupt Enable 1H (IME1H): Enables or disables interrupt requests by IMF1H in TSR1A when IMF1H is set to 1. Bit 7: IME1H Description 0 IMI1H interrupt requested by IMF1H is disabled 1 IMI1H interrupt requested by IMF1H is enabled (Initial value) • Bit 6—Input Capture/Compare-Match Interrupt Enable 1G (IME1G): Enables or disables interrupt requests by IMF1G in TSR1A when IMF1G is set to 1. Bit 6: IME1G Description 0 IMI1G interrupt requested by IMF1G is disabled 1 IMI1G interrupt requested by IMF1G is enabled (Initial value) • Bit 5—Input Capture/Compare-Match Interrupt Enable 1F (IME1F): Enables or disables interrupt requests by IMF1F in TSR1A when IMF1F is set to 1. Bit 5: IME1F Description 0 IMI1F interrupt requested by IMF1F is disabled 1 IMI1F interrupt requested by IMF1F is enabled (Initial value) • Bit 4—Input Capture/Compare-Match Interrupt Enable 1E (IME1E): Enables or disables interrupt requests by IMF1E in TSR1A when IMF1E is set to 1. Bit 4: IME1E Description 0 IMI1E interrupt requested by IMF1E is disabled 1 IMI1E interrupt requested by IMF1E is enabled (Initial value) 263 • Bit 3—Input Capture/Compare-Match Interrupt Enable 1D (IME1D): Enables or disables interrupt requests by IMF1D in TSR1A when IMF1D is set to 1. Bit 3: IME1D Description 0 IMI1D interrupt requested by IMF1D is disabled 1 IMI1D interrupt requested by IMF1D is enabled (Initial value) • Bit 2—Input Capture/Compare-Match Interrupt Enable 1C (IME1C): Enables or disables interrupt requests by IMF1C in TSR1A when IMF1C is set to 1. Bit 2: IME1C Description 0 IMI1C interrupt requested by IMF1C is disabled 1 IMI1C interrupt requested by IMF1C is enabled (Initial value) • Bit 1—Input Capture/Compare-Match Interrupt Enable 1B (IME1B): Enables or disables interrupt requests by IMF1B in TSR1A when IMF1B is set to 1. Bit 1: IME1B Description 0 IMI1B interrupt requested by IMF1B is disabled 1 IMI1B interrupt requested by IMF1B is enabled (Initial value) • Bit 0—Input Capture/Compare-Match Interrupt Enable 1A (IME1A): Enables or disables interrupt requests by IMF1A in TSR1A when IMF1A is set to 1. Bit 0: IME1A Description 0 IMI1A interrupt requested by IMF1A is disabled 1 IMI1A interrupt requested by IMF1A is enabled 264 (Initial value) TIER1B: TIER1B controls enabling/disabling of channel 1 compare-match and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 — — — — — — — OVE1B Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 — — — — — — — CME1 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W • Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0. • Bit 8—Overflow Interrupt Enable 1B (OVE1B): Enables or disables interrupt requests by OVF1B in TSR1B when OVF1B is set to 1. Bit 8: OVE1B Description 0 OVI1B interrupt requested by OVF1B is disabled 1 OVI1B interrupt requested by OVF1B is enabled (Initial value) • Bits 7 to 1—Reserved: These bits always read 0. The write value should always be 0. • Bit 0—Compare-Match Interrupt Enable 1 (CME1): Enables or disables interrupt requests by CMF1 in TSR1B when CMF1 is set to 1. Bit 0: CME1 Description 0 CMI1 interrupt requested by CMF1 is disabled 1 CMI1 interrupt requested by CMF1 is enabled (Initial value) 265 Timer Interrupt Enable Registers 2A and 2B (TIER2A, TIER2B) TIER2A: TIER2A controls enabling/disabling of channel 2 input capture, compare-match, and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 — — — — — — — OVE2A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 IME2H IME2G IME2F IME2E IME2D IME2C IME2B IME2A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: • Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0. • Bit 8—Overflow Interrupt Enable 2A (OVE2A): Enables or disables interrupt requests by OVF2A in TSR2A when OVF2A is set to 1. Bit 8: OVE2A Description 0 OVI2A interrupt requested by OVF2A is disabled 1 OVI2A interrupt requested by OVF2A is enabled (Initial value) • Bit 7—Input Capture/Compare-Match Interrupt Enable 2H (IME2H): Enables or disables interrupt requests by IMF2H in TSR2A when IMF2H is set to 1. Bit 7: IME2H Description 0 IMI2H interrupt requested by IMF2H is disabled 1 IMI2H interrupt requested by IMF2H is enabled (Initial value) • Bit 6—Input Capture/Compare-Match Interrupt Enable 2G (IME2G): Enables or disables interrupt requests by IMF2G in TSR2A when IMF2G is set to 1. Bit 6: IME2G Description 0 IMI2G interrupt requested by IMF2G is disabled 1 IMI2G interrupt requested by IMF2G is enabled 266 (Initial value) • Bit 5—Input Capture/Compare-Match Interrupt Enable 2F (IME2F): Enables or disables interrupt requests by IMF2F in TSR2A when IMF2F is set to 1. Bit 5: IME2F Description 0 IMI2F interrupt requested by IMF2F is disabled 1 IMI2F interrupt requested by IMF2F is enabled (Initial value) • Bit 4—Input Capture/Compare-Match Interrupt Enable 2E (IME2E): Enables or disables interrupt requests by IMF2E in TSR2A when IMF2E is set to 1. Bit 4: IME2E Description 0 IMI2E interrupt requested by IMF2E is disabled 1 IMI2E interrupt requested by IMF2E is enabled (Initial value) • Bit 3—Input Capture/Compare-Match Interrupt Enable 2D (IME2D): Enables or disables interrupt requests by IMF2D in TSR2A when IMF2D is set to 1. Bit 3: IME2D Description 0 IMI2D interrupt requested by IMF2D is disabled 1 IMI2D interrupt requested by IMF2D is enabled (Initial value) • Bit 2—Input Capture/Compare-Match Interrupt Enable 2C (IME2C): Enables or disables interrupt requests by IMF2C in TSR2A when IMF2C is set to 1. Bit 2: IME2C Description 0 IMI2C interrupt requested by IMF2C is disabled 1 IMI2C interrupt requested by IMF2C is enabled (Initial value) • Bit 1—Input Capture/Compare-Match Interrupt Enable 2B (IME2B): Enables or disables interrupt requests by IMF2B in TSR2A when IMF2B is set to 1. Bit 1: IME2B Description 0 IMI2B interrupt requested by IMF2B is disabled 1 IMI2B interrupt requested by IMF2B is enabled (Initial value) 267 • Bit 0—Input Capture/Compare-Match Interrupt Enable 2A (IME2A): Enables or disables interrupt requests by IMF2A in TSR2A when IMF2A is set to 1. Bit 0: IME2A Description 0 IMI2A interrupt requested by IMF2A is disabled 1 IMI2A interrupt requested by IMF2A is enabled (Initial value) TIER2B: TIER2B controls enabling/disabling of channel 2 compare-match and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 — — — — — — — OVE2B Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 CME2H CME2G CME2F CME2E CME2D CME2C CME2B CME2A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: • Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0. • Bit 8—Overflow Interrupt Enable 2B (OVE2B): Enables or disables interrupt requests by OVF2B in TSR2B when OVF2B is set to 1. Bit 8: OVE2B Description 0 OVI2B interrupt requested by OVF2B is disabled 1 OVI2B interrupt requested by OVF2B is enabled (Initial value) • Bit 7—Compare-Match Interrupt Enable 2H (CME2H): Enables or disables interrupt requests by CMF2F in TSR2B when CMF2H is set to 1. Bit 7: CME2H Description 0 CMI2H interrupt requested by CMF2H is disabled 1 CMI2H interrupt requested by CMF2H is enabled 268 (Initial value) • Bit 6—Compare-Match Interrupt Enable 2G (CME2G): Enables or disables interrupt requests by CMF2G in TSR2B when CMF2G is set to 1. Bit 6: CME2G Description 0 CMI2G interrupt requested by CMF2G is disabled 1 CMI2G interrupt requested by CMF2G is enabled (Initial value) • Bit 5—Compare-Match Interrupt Enable 2F (CME2F): Enables or disables interrupt requests by CMF2F in TSR2B when CMF2F is set to 1. Bit 5: CME2F Description 0 CMI2F interrupt requested by CMF2F is disabled 1 CMI2F interrupt requested by CMF2F is enabled (Initial value) • Bit 4—Compare-Match Interrupt Enable 2E (CME2E): Enables or disables interrupt requests by CMF2E in TSR2B when CMF2E is set to 1. Bit 4: CME2E Description 0 CMI2E interrupt requested by CMF2E is disabled 1 CMI2E interrupt requested by CMF2E is enabled (Initial value) • Bit 3—Compare-Match Interrupt Enable 2D (CME2D): Enables or disables interrupt requests by CMF2D in TSR2B when CMF2D is set to 1. Bit 3: CME2D Description 0 CMI2D interrupt requested by CMF2D is disabled 1 CMI2D interrupt requested by CMF2D is enabled (Initial value) • Bit 2—Compare-Match Interrupt Enable 2C (CME2C): Enables or disables interrupt requests by CMF2C in TSR2B when CMF2C is set to 1. Bit 2: CME2C Description 0 CMI2C interrupt requested by CMF2C is disabled 1 CMI2C interrupt requested by CMF2C is enabled (Initial value) 269 • Bit 1—Compare-Match Interrupt Enable 2B (CME2BB): Enables or disables interrupt requests by CMF2B in TSR2B when CMF2B is set to 1. Bit 1: CME2B Description 0 CMI2B interrupt requested by CMF2B is disabled 1 CMI2B interrupt requested by CMF2B is enabled (Initial value) • Bit 0—Compare-Match Interrupt Enable 2A (CME2A): Enables or disables interrupt requests by CMF2A in TSR2B when CMF2A is set to 1. Bit 0: CME2A Description 0 CMI2A interrupt requested by CMF2A is disabled 1 CMI2A interrupt requested by CMF2A is enabled (Initial value) Timer Interrupt Enable Register 3 (TIER3) TIER3 controls enabling/disabling of channel 3 to 5 input capture, compare-match, and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 — OVE5 IME5D IME5C IME5B IME5A OVE4 IME4D Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 IME4C IME4B IME4A OVE3 IME3D IME3C IME3B IME3A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: • Bit 15—Reserved: This bit always reads 0. The write value should always be 0. • Bit 14—Overflow Interrupt Enable 5 (OVE5): Enables or disables interrupt requests by OVF5 in TSR3 when OVF5 is set to 1. Bit 14: OVE5 Description 0 OVI5 interrupt requested by OVF5 is disabled 1 OVI5 interrupt requested by OVF5 is enabled 270 (Initial value) • Bit 13—Input Capture/Compare-Match Interrupt Enable 5D (IME5D): Enables or disables interrupt requests by IMF5D in TSR3 when IMF5D is set to 1. Bit 13: IME5D Description 0 IMI5D interrupt requested by IMF5D is disabled 1 IMI5D interrupt requested by IMF5D is enabled (Initial value) • Bit 12—Input Capture/Compare-Match Interrupt Enable 5C (IME5C): Enables or disables interrupt requests by IMF5C in TSR3 when IMF5C is set to 1. Bit 12: IME5C Description 0 IMI5C interrupt requested by IMF5C is disabled 1 IMI5C interrupt requested by IMF5C is enabled (Initial value) • Bit 11—Input Capture/Compare-Match Interrupt Enable 5B (IME5B): Enables or disables interrupt requests by IMF5B in TSR3 when IMF5B is set to 1. Bit 11: IME5B Description 0 IMI5B interrupt requested by IMF5B is disabled 1 IMI5B interrupt requested by IMF5B is enabled (Initial value) • Bit 10—Input Capture/Compare-Match Interrupt Enable 5A (IME5A): Enables or disables interrupt requests by IMF5A in TSR3 when IMF5A is set to 1. Bit 10: IME5A Description 0 IMI5A interrupt requested by IMF5A is disabled 1 IMI5A interrupt requested by IMF5A is enabled (Initial value) • Bit 9—Overflow Interrupt Enable 4 (OVE4): Enables or disables interrupt requests by OVF4 in TSR3 when OVF4 is set to 1. Bit 9: OVE4 Description 0 OVI4 interrupt requested by OVF4 is disabled 1 OVI4 interrupt requested by OVF4 is enabled (Initial value) 271 • Bit 8—Input Capture/Compare-Match Interrupt Enable 4D (IME4D): Enables or disables interrupt requests by IMF4D in TSR3 when IMF4D is set to 1. Bit 8: IME4D Description 0 IMI4D interrupt requested by IMF4D is disabled 1 IMI4D interrupt requested by IMF4D is enabled (Initial value) • Bit 7—Input Capture/Compare-Match Interrupt Enable 4C (IME4C): Enables or disables interrupt requests by IMF4C in TSR3 when IMF4C is set to 1. Bit 7: IME4C Description 0 IMI4C interrupt requested by IMF4C is disabled 1 IMI4C interrupt requested by IMF4C is enabled (Initial value) • Bit 6—Input Capture/Compare-Match Interrupt Enable 4B (IME4B): Enables or disables interrupt requests by IMF4B in TSR3 when IMF4B is set to 1. Bit 6: IME4B Description 0 IMI4B interrupt requested by IMF4B is disabled 1 IMI4B interrupt requested by IMF4B is enabled (Initial value) • Bit 5—Input Capture/Compare-Match Interrupt Enable 4A (IME4A): Enables or disables interrupt requests by IMF4A in TSR3 when IMF4A is set to 1. Bit 5: IME4A Description 0 IMI4A interrupt requested by IMF4A is disabled 1 IMI4A interrupt requested by IMF4A is enabled (Initial value) • Bit 4—Overflow Interrupt Enable 3 (OVE3): Enables or disables interrupt requests by OVF3 in TSR3 when OVF3 is set to 1. Bit 4: OVE3 Description 0 OVI3 interrupt requested by OVF3 is disabled 1 OVI3 interrupt requested by OVF3 is enabled 272 (Initial value) • Bit 3—Input Capture/Compare-Match Interrupt Enable 3D (IME3D): Enables or disables interrupt requests by IMF3D in TSR3 when IMF3D is set to 1. Bit 3: IME3D Description 0 IMI3D interrupt requested by IMF3D is disabled 1 IMI3D interrupt requested by IMF3D is enabled (Initial value) • Bit 2—Input Capture/Compare-Match Interrupt Enable 3C (IME3C): Enables or disables interrupt requests by IMF3C in TSR3 when IMF3C is set to 1. Bit 2: IME3C Description 0 IMI3C interrupt requested by IMF3C is disabled 1 IMI3C interrupt requested by IMF3C is enabled (Initial value) • Bit 1—Input Capture/Compare-Match Interrupt Enable 3B (IME3B): Enables or disables interrupt requests by IMF3B in TSR3 when IMF3B is set to 1. Bit 1: IME3B Description 0 IMI3B interrupt requested by IMF3B is disabled 1 IMI3B interrupt requested by IMF3B is enabled (Initial value) • Bit 0—Input Capture/Compare-Match Interrupt Enable 3A (IME3A): Enables or disables interrupt requests by IMF3A in TSR3 when IMF3A is set to 1. Bit 0: IME3A Description 0 IMI3A interrupt requested by IMF3A is disabled 1 IMI3A interrupt requested by IMF3A is enabled (Initial value) 273 Timer Interrupt Enable Registers 6 and 7 (TIER6, TIER7) TIER6 and TIER7 control enabling/disabling of channel 6 and 7 cycle register compare interrupt requests. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — CMExD CMExC Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W CMExB CMExA x = 6 or 7 • Bits 15 to 4—Reserved: These bits always read 0. The write value should always be 0. • Bit 3—Cycle Register Compare-Match Interrupt Enable 6D/7D (CME6D/CME7D): Enables or disables interrupt requests by CMFxD in TSR6 or TSR7 when CMFxD is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 3: CMExD Description 0 CMIxD interrupt requested by CMFxD is disabled 1 CMIxD interrupt requested by CMFxD is enabled (Initial value) x = 6 or 7 • Bit 2—Cycle Register Compare-Match Interrupt Enable 6C/7C (CME6C/CME7C): Enables or disables interrupt requests by CMFxC in TSR6 or TSR7 when CMFxC is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 2: CMExC Description 0 CMIxC interrupt requested by CMFxC is disabled 1 CMIxC interrupt requested by CMFxC is enabled x = 6 or 7 274 (Initial value) • Bit 1—Cycle Register Compare-Match Interrupt Enable 6B/7B (CME6B/CME7B): Enables or disables interrupt requests by CMFxB in TSR6 or TSR7 when CMFxB is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 1: CMExB Description 0 CMIxB interrupt requested by CMFxB is disabled 1 CMIxB interrupt requested by CMFxB is enabled (Initial value) x = 6 or 7 • Bit 0—Cycle Register Compare-Match Interrupt Enable 6A/7A (CME6A/CME7A): Enables or disables interrupt requests by CMFxA in TSR6 or TSR7 when CMFxA is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 0: CMExA Description 0 CMIxA interrupt requested by CMFxA is disabled 1 CMIxA interrupt requested by CMFxA is enabled (Initial value) x = 6 or 7 Timer Interrupt Enable Register 8 (TIER8) TIER8 controls enabling/disabling of channel 8 one-shot pulse interrupt requests. Bit: 15 14 13 OSE8P OSE8O OSE8N Initial value: R/W: Bit: R/W: 11 10 9 8 OSE8K OSE8J OSE8I 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 OSE8H Initial value: 12 OSE8M OSE8L OSE8G OSE8F OSE8E OSE8D OSE8C OSE8B OSE8A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 275 • Bit 15—One-Shot Pulse Interrupt Enable 8P (OSE8P): Enables or disables interrupt requests by OSF8P in TSR8 when OSF8P is set to 1. Bit 15: OSE8P Description 0 OSI8P interrupt requested by OSF8P is disabled 1 OSI8P interrupt requested by OSF8P is enabled (Initial value) • Bit 14—One-Shot Pulse Interrupt Enable 8O (OSE8O): Enables or disables interrupt requests by OSF8O in TSR8 when OSF8O is set to 1. Bit 14: OSE8O Description 0 OSI8O interrupt requested by OSF8O is disabled 1 OSI8O interrupt requested by OSF8O is enabled (Initial value) • Bit 13—One-Shot Pulse Interrupt Enable 8N (OSE8N): Enables or disables interrupt requests by OSF8N in TSR8 when OSF8N is set to 1. Bit 13: OSE8N Description 0 OSI8N interrupt requested by OSF8N is disabled 1 OSI8N interrupt requested by OSF8N is enabled (Initial value) • Bit 12—One-Shot Pulse Interrupt Enable 8M (OSE8M): Enables or disables interrupt requests by OSF8M in TSR8 when OSF8M is set to 1. Bit 12: OSE8M Description 0 OSI8M interrupt requested by OSF8M is disabled 1 OSI8M interrupt requested by OSF8M is enabled (Initial value) • Bit 11—One-Shot Pulse Interrupt Enable 8L (OSE8L): Enables or disables interrupt requests by OSF8L in TSR8 when OSF8L is set to 1. Bit 11: OSE8L Description 0 OSI8L interrupt requested by OSF8L is disabled 1 OSI8L interrupt requested by OSF8L is enabled 276 (Initial value) • Bit 10—One-Shot Pulse Interrupt Enable 8K (OSE8K): Enables or disables interrupt requests by OSF8K in TSR8 when OSF8K is set to 1. Bit 10: OSE8K Description 0 OSI8K interrupt requested by OSF8K is disabled 1 OSI8K interrupt requested by OSF8K is enabled (Initial value) • Bit 9—One-Shot Pulse Interrupt Enable 8J (OSE8J): Enables or disables interrupt requests by OSF8J in TSR8 when OSF8J is set to 1. Bit 9: OSE8J Description 0 OSI8J interrupt requested by OSF8J is disabled 1 OSI8J interrupt requested by OSF8J is enabled (Initial value) • Bit 8—One-Shot Pulse Interrupt Enable 8I (OSE8I): Enables or disables interrupt requests by OSF8I in TSR8 when OSF8I is set to 1. Bit 8: OSE8I Description 0 OSI8I interrupt requested by OSF8I is disabled 1 OSI8I interrupt requested by OSF8I is enabled (Initial value) • Bit 7—One-Shot Pulse Interrupt Enable 8H (OSE8H): Enables or disables interrupt requests by OSF8H in TSR8 when OSF8H is set to 1. Bit 7: OSE8H Description 0 OSI8H interrupt requested by OSF8H is disabled 1 OSI8H interrupt requested by OSF8H is enabled (Initial value) • Bit 6—One-Shot Pulse Interrupt Enable 8G (OSE8G): Enables or disables interrupt requests by OSF8G in TSR8 when OSF8G is set to 1. Bit 6: OSE8G Description 0 OSI8G interrupt requested by OSF8G is disabled 1 OSI8G interrupt requested by OSF8G is enabled (Initial value) 277 • Bit 5—One-Shot Pulse Interrupt Enable 8F (OSE8F): Enables or disables interrupt requests by OSF8F in TSR8 when OSF8F is set to 1. Bit 5: OSE8F Description 0 OSI8F interrupt requested by OSF8F is disabled 1 OSI8F interrupt requested by OSF8F is enabled (Initial value) • Bit 4—One-Shot Pulse Interrupt Enable 8E (OSE8E): Enables or disables interrupt requests by OSF8E in TSR8 when OSF8E is set to 1. Bit 4: OSE8E Description 0 OSI8E interrupt requested by OSF8E is disabled 1 OSI8E interrupt requested by OSF8E is enabled (Initial value) • Bit 3—One-Shot Pulse Interrupt Enable 8D (OSE8D): Enables or disables interrupt requests by OSF8D in TSR8 when OSF8D is set to 1. Bit 3: OSE8D Description 0 OSI8D interrupt requested by OSF8D is disabled 1 OSI8D interrupt requested by OSF8D is enabled (Initial value) • Bit 2—One-Shot Pulse Interrupt Enable 8C (OSE8C): Enables or disables interrupt requests by OSF8C in TSR8 when OSF8C is set to 1. Bit 2: OSE8C Description 0 OSI8C interrupt requested by OSF8C is disabled 1 OSI8C interrupt requested by OSF8C is enabled (Initial value) • Bit 1—One-Shot Pulse Interrupt Enable 8B (OSE8B): Enables or disables interrupt requests by OSF8B in TSR8 when OSF8B is set to 1. Bit 1: OSE8B Description 0 OSI8B interrupt requested by OSF8B is disabled 1 OSI8B interrupt requested by OSF8B is enabled 278 (Initial value) • Bit 0—One-Shot Pulse Interrupt Enable 8A (OSE8A): Enables or disables interrupt requests by OSF8A in TSR8 when OSF8A is set to 1. Bit 0: OSE8A Description 0 OSI8A interrupt requested by OSF8A is disabled 1 OSI8A interrupt requested by OSF8A is enabled (Initial value) Timer Interrupt Enable Register 9 (TIER9) TIER9 controls enabling/disabling of channel 9 event counter compare-match interrupt requests. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W CME9F CME9E CME9D CME9C CME9B CME9A • Bits 15 to 6—Reserved: These bits always read 0. The write value should always be 0. • Bit 5—Compare-Match Interrupt Enable 9F (CME9F): Enables or disables interrupt requests by CMF9F in TSR9 when CMF9F is set to 1. Bit 5: CME9F Description 0 CMI9F interrupt requested by CMF9F is disabled 1 CMI9F interrupt requested by CMF9F is enabled (Initial value) • Bit 4—Compare-Match Interrupt Enable 9E (CME9E): Enables or disables interrupt requests by CMF9E in TSR9 when CMF9E is set to 1. Bit 4: CME9E Description 0 CMI9E interrupt requested by CMF9E is disabled 1 CMI9E interrupt requested by CMF9E is enabled (Initial value) 279 • Bit 3—Compare-Match Interrupt Enable 9D (CME9D): Enables or disables interrupt requests by CMF9D in TSR9 when CMF9D is set to 1. Bit 3: CME9D Description 0 CMI9D interrupt requested by CMF9D is disabled 1 CMI9D interrupt requested by CMF9D is enabled (Initial value) • Bit 2—Compare-Match Interrupt Enable 9C (CME9C): Enables or disables interrupt requests by CMF9C in TSR9 when CMF9C is set to 1. Bit 2: CME9C Description 0 CMI9C interrupt requested by CMF9C is disabled 1 CMI9C interrupt requested by CMF9C is enabled (Initial value) • Bit 1—Compare-Match Interrupt Enable 9B (CME9B): Enables or disables interrupt requests by CMF9B in TSR9 when CMF9B is set to 1. Bit 1: CME9B Description 0 CMI9B interrupt requested by CMF9B is disabled 1 CMI9B interrupt requested by CMF9B is enabled (Initial value) • Bit 0—Compare-Match Interrupt Enable 9A (CME9A): Enables or disables interrupt requests by CMF9A in TSR9 when CMF9A is set to 1. Bit 0: CME9A Description 0 CMI9A interrupt requested by CMF9A is disabled 1 CMI9A interrupt requested by CMF9A is enabled 280 (Initial value) Timer Interrupt Enable Register 11 (TIER11) TIER11 controls enabling/disabling of channel 11 compare-match and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 — — — — — — — OVE11 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W IME11B IME11A • Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0. • Bit 8—Overflow Interrupt Enable 11 (OVE11): Enables or disables interrupt requests by OVF11 in TSR11 when OVF11 is set to 1. Bit 8: OVE11 Description 0 OVI11 interrupt requested by OVF11 is disabled 1 OVI11 interrupt requested by OVF11 is enabled (Initial value) • Bits 7 to 2—Reserved: These bits always read 0. The write value should always be 0. • Bit 1—Compare-Match Interrupt Enable 11B (IME11B): Enables or disables interrupt requests by IMF11B in TSR11 when IMF11B is set to 1. Bit 1: IME11B Description 0 IMI11B interrupt requested by IMF11B is disabled 1 IMI11B interrupt requested by IMF11B is enabled (Initial value) • Bit 0—Compare-Match Interrupt Enable 11A (IME11A): Enables or disables interrupt requests by IMF11A in TSR11 when IMF11A is set to 1. Bit 0: IME11A Description 0 IMI11A interrupt requested by IMF11A is disabled 1 IMI11A interrupt requested by IMF11A is enabled (Initial value) 281 10.2.7 Interval Interrupt Request Registers (ITVRR) The interval interrupt request registers (ITVRR) are 8-bit registers. The ATU-II has three ITVRR registers in channel 0. Channel Abbreviation Function 0 ITVRR1 TCNT0 bit 6 to 9 interval interrupt generation ITVRR2A TCNT0 bit 10 to 13 interval interrupt generation and A/D0 converter activation ITVRR2B TCNT0 bit 10 to 13 interval interrupt generation and A/D1 converter activation Interval Interrupt Request Register 1 (ITVRR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ITVE9 ITVE8 ITVE7 ITVE6 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W ITVRR1 is an 8-bit readable/writable register that detects the rise of bits corresponding to the channel 0 free-running counter (TCNT0) and requests cyclic interrupt. ITVRR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7 to 4—Reserved: These bits always read 0. The write value should always be 0. • Bit 3—Interval Interrupt Bit 9 (ITVE9): INTC interval interrupt setting bit corresponding to bit 9 in TCNT0. The rise of bit 9 in TCNT0 is ANDed with ITVE9, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 3: ITVE9 Description 0 Interrupt request (ITV1) by rise of TCNT0 bit 9 is disabled 1 Interrupt request (ITV1) by rise of TCNT0 bit 9 is enabled (Initial value) • Bit 2—Interval Interrupt Bit 8 (ITVE8): INTC interval interrupt setting bit corresponding to bit 8 in TCNT0. The rise of bit 8 in TCNT0 is ANDed with ITVE8, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. 282 Bit 2: ITVE8 Description 0 Interrupt request (ITV1) by rise of TCNT0 bit 8 is disabled 1 Interrupt request (ITV1) by rise of TCNT0 bit 8 is enabled (Initial value) • Bit 1—Interval Interrupt Bit 7 (ITVE7): INTC interval interrupt setting bit corresponding to bit 7 in TCNT0. The rise of bit 7 in TCNT0 is ANDed with ITVE7, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 1: ITVE7 Description 0 Interrupt request (ITV1) by rise of TCNT0 bit 7 is disabled 1 Interrupt request (ITV1) by rise of TCNT0 bit 7 is enabled (Initial value) • Bit 0—Interval Interrupt Bit 6 (ITVE6): INTC interval interrupt setting bit corresponding to bit 6 in TCNT0. The rise of bit 6 in TCNT0 is ANDed with ITVE6, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 0: ITVE6 Description 0 Interrupt request (ITV1) by rise of TCNT0 bit 6 is disabled 1 Interrupt request (ITV1) by rise of TCNT0 bit 6 is enabled (Initial value) Interval Interrupt Request Registers 2A and 2B (ITVRR2A, ITVRR2B) Bit: 7 6 5 4 3 2 1 0 ITVA13x ITVA12x ITVA11x ITVA10x ITVE13x ITVE12x ITVE11x ITVE10x Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W x = A or B • Bit 7—A/D0 / A/D1 Converter Interval Activation Bit 13A/13B (ITVA13A/ITVA13B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 13 in TCNT0. The rise of bit 13 in TCNT0 is ANDed with ITVA13x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 7: ITVA13x Description 0 A/D0 or A/D1 converter activation by rise of TCNT0 bit 13 is disabled (Initial value) 1 A/D0 or A/D1 converter activation by rise of TCNT0 bit 13 is enabled x = A or B 283 • Bit 6—A/D0 / A/D1 Converter Interval Activation Bit 12A/12B (ITVA12A/ITVA12B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 12 in TCNT0. The rise of bit 12 in TCNT0 is ANDed with ITVA12x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 6: ITVA12x Description 0 A/D0 or A/D1 converter activation by rise of TCNT0 bit 12 is disabled (Initial value) 1 A/D0 or A/D1 converter activation by rise of TCNT0 bit 12 is enabled x = A or B • Bit 5—A/D0 / A/D1 Converter Interval Activation Bit 11A/11B (ITVA11A/ITVA11B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 11 in TCNT0. The rise of bit 11 in TCNT0 is ANDed with ITVA11x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 5: ITVA11x Description 0 A/D0 or A/D1 converter activation by rise of TCNT0 bit 11 is disabled (Initial value) 1 A/D0 or A/D1 converter activation by rise of TCNT0 bit 11 is enabled x = A or B • Bit 4—A/D0 / A/D1 Converter Interval Activation Bit 10A/10B (ITVA10A/ITVA10B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 10 in TCNT0. The rise of bit 10 in TCNT0 is ANDed with ITVA10x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 4: ITVA10x Description 0 A/D0 or A/D1 converter activation by rise of TCNT0 bit 10 is disabled (Initial value) 1 A/D0 or A/D1 converter activation by rise of TCNT0 bit 10 is enabled x = A or B 284 • Bit 3—Interval Interrupt Bit 13A/13B (ITVE13A/ITVE13B): INTC interval interrupt setting bit corresponding to bit 13 in TCNT0. The rise of bit 13 in TCNT0 is ANDed with ITVE13x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 3: ITVE13x Description 0 Interrupt request (ITV2x) by rise of TCNT0 bit 13 is disabled 1 Interrupt request (ITV2x) by rise of TCNT0 bit 13 is enabled (Initial value) x = A or B • Bit 2—Interval Interrupt Bit 12A/12B (ITVE12A/ITVE12B): INTC interval interrupt setting bit corresponding to bit 12 in TCNT0. The rise of bit 12 in TCNT0 is ANDed with ITVE12x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 2: ITVE12x Description 0 Interrupt request (ITV2x) by rise of TCNT0 bit 12 is disabled 1 Interrupt request (ITV2x) by rise of TCNT0 bit 12 is enabled (Initial value) x = A or B • Bit 1—Interval Interrupt Bit 11A/11B (ITVE11A/ITVE11B): INTC interval interrupt setting bit corresponding to bit 11 in TCNT0. The rise of bit 11 in TCNT0 is ANDed with ITVE11x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 1: ITVE11x Description 0 Interrupt request (ITV2x) by rise of TCNT0 bit 11 is disabled 1 Interrupt request (ITV2x) by rise of TCNT0 bit 11 is enabled (Initial value) x = A or B • Bit 0—Interval Interrupt Bit 10 (ITVE10): INTC interval interrupt setting bit corresponding to bit 10 in TCNT0. The rise of bit 10 in TCNT0 is ANDed with ITVE10x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 0: ITVE10x Description 0 Interrupt request (ITV2x) by rise of TCNT0 bit 10 is disabled 1 Interrupt request (ITV2x) by rise of TCNT0 bit 10 is enabled (Initial value) x = A or B For details, see section 10.3.7, Interval Timer Functions. 285 10.2.8 Trigger Mode Register (TRGMDR) The trigger mode register (TRGMDR) is an 8-bit register. The ATU-II has one TRGMDR register. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TRGMD — — — — — — — 0 0 0 0 0 0 0 0 R/W R R R R R R R TRGMDR is an 8-bit readable/writable register that selects whether a channel 1 compare-match is used as a channel 8 one-shot pulse start trigger or as a one-shot pulse terminate trigger when channel 1 and channel 8 are used in combination. TRGMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Trigger Mode Selection Register (TRGMD): Selects the channel 8 one-shot pulse start trigger/one-shot pulse terminate trigger setting. Bit 7: TRGMD Description 0 One-shot pulse start trigger (TCNT1B = OCR1) (Initial value) One-shot pulse terminate trigger (TCNT1A = GR1A to GR1H) 1 One-shot pulse start trigger (TCNT1A = GR1A to GR1H) One-shot pulse terminate trigger (TCNT1B = OCR1) • Bits 6 to 0—Reserved: These bits always read 0. The write value should always be 0. 10.2.9 Timer Mode Register (TMDR) The timer mode register (TMDR) is an 8-bit register. The ATU-II has one TDR register. Bit: 7 6 5 4 3 2 1 0 — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W T5PWM T4PWM T3PWM TMDR is an 8-bit readable/writable register that specifies whether channels 3 to 5 are used in input capture/output compare mode or PWM mode. TMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. 286 • Bits 7 to 3—Reserved: These bits always read 0. The write value should always be 0. • Bit 2—PWM Mode 5 (T5PWM): Selects whether channel 5 operates in input capture/output compare mode or PWM mode. Bit 2: T5PWM Description 0 Channel 5 operates in input capture/output compare mode 1 Channel 5 operates in PWM mode (Initial value) When bit T5PWM is set to 1 to select PWM mode, pins TIO5A to TIO5C become PWM output pins, general register 5D (GR5D) functions as a cycle register, and general registers 5A to 5C (GR5A to GR5C) function as duty registers. Settings in the timer I/O control registers (TIOR5A, TIOR5B) are invalid, and general registers 5A to 5D (GR5A to GR5D) can be written to. Do not use the TIO5D pin as a timer output. • Bit 1—PWM Mode 4 (T4PWM): Selects whether channel 4 operates in input capture/output compare mode or PWM mode. Bit 1: T4PWM Description 0 Channel 4 operates in input capture/output compare mode 1 Channel 4 operates in PWM mode (Initial value) When bit T4PWM is set to 1 to select PWM mode, pins TIO4A to TIO4C become PWM output pins, general register 4D (GR4D) functions as a cycle register, and general registers 4A to 4C (GR4A to GR4C) function as duty registers. Settings in the timer I/O control registers (TIOR4A, TIOR4B) are invalid, and general registers 4A to 4D (GR4A to GR4D) can be written to. Do not use the TIO4D pin as a timer output. • Bit 0—PWM Mode 3 (T3PWM): Selects whether channel 3 operates in input capture/output compare mode or PWM mode. Bit 0: T3PWM Description 0 Channel 3 operates in input capture/output compare mode 1 Channel 3 operates in PWM mode (Initial value) When bit T3PWM is set to 1 to select PWM mode, pins TIO3A to TIO3C become PWM output pins, general register 3D (GR3D) functions as a cycle register, and general registers 3A to 3C (GR3A to GR3C) function as duty registers. Settings in the timer I/O control registers (TIOR3A, TIOR3B) are invalid, and general registers 3A to 3D (GR3A to GR3D) can be written to. Do not use the TIO3D pin as a timer output. 287 10.2.10 PWM Mode Register (PMDR) The PWM mode register (PMDR) is an 8-bit register. The ATU-II has one PMDR register. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 DTSELD DTSELC DTSELB 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W DTSELA CNTSELD CNTSELC CNTSELB CNTSELA PMDR is an 8-bit readable/writable register that selects whether channel 6 PWM output is set to on-duty/off-duty, or to non-complementary PWM mode/complementary PWM mode. PMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Duty Selection Register D (DTSELD): Selects whether channel 6D TO6D output PWM is set to on-duty or to off-duty. Bit 7: DTSELD Description 0 TO6D PWM output is on-duty 1 TO6D PWM output is off-duty (Initial value) • Bit 6—Duty Selection Register C (DTSELC): Selects whether channel 6C TO6C output PWM is set to on-duty or to off-duty. Bit 6: DTSELC Description 0 TO6C PWM output is on-duty 1 TO6C PWM output is off-duty (Initial value) • Bit 5—Duty Selection Register B (DTSELB): Selects whether channel 6B TO6B output PWM is set to on-duty or to off-duty. Bit 5: DTSELB Description 0 TO6B PWM output is on-duty 1 TO6B PWM output is off-duty 288 (Initial value) • Bit 4—Duty Selection Register A (DTSELA): Selects whether channel 6A TO6A output PWM is set to on-duty or to off-duty. Bit 4: DTSELA Description 0 TO6A PWM output is on-duty 1 TO6A PWM output is off-duty (Initial value) • Bit 3—Counter Selection Register D (CNTSELD): Selects whether channel 6D PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 3: CNTSELD Description 0 TCNT6D is set to non-complementary PWM mode 1 TCNT6D is set to complementary PWM mode (Initial value) • Bit 2—Counter Selection Register C (CNTSELC): Selects whether channel 6C PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 2: CNTSELC Description 0 TCNT6C is set to non-complementary PWM mode 1 TCNT6C is set to complementary PWM mode (Initial value) • Bit 1—Counter Selection Register B (CNTSELB): Selects whether channel 6B PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 1: CNTSELB Description 0 TCNT6B is set to non-complementary PWM mode 1 TCNT6B is set to complementary PWM mode (Initial value) • Bit 0—Counter Selection Register A (CNTSELA): Selects whether channel 6A PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 0: CNTSELA Description 0 TCNT6A is set to non-complementary PWM mode 1 TCNT6A is set to complementary PWM mode (Initial value) 289 10.2.11 Down-Count Start Register (DSTR) The down-count start register (DSTR) is a 16-bit register. The ATU-II has one DSTR register in channel 8. Bit: 15 DST8P Initial value: R/W: Bit: Initial value: R/W: 14 13 DST8O DST8N 12 11 10 9 8 DST8M DST8L DST8K DST8J DST8I 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* 7 6 5 4 3 2 1 0 DST8H DST8G DST8F DST8E DST8D DST8C DST8B DST8A 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * Only 1 can be written. DSTR is a 16-bit readable/writable register that starts the channel 8 down-counter (DCNT). When the one-shot pulse function is used, a value of 1 can be set in a DST8x bit at any time by the user program, except when the corresponding DCNT8x value is H'0000. The DST8x bits are cleared to 0 automatically when the DCNT value overflows. When the offset one-shot pulse function is used, DST8x is automatically set to 1 (except when the DCNT8x value is H'0000) when a compare-match occurs between the channel 1 or 2 free-running counter (TCNT) and a general register (GR) or the output compare register (OCR1) while the corresponding timer connection register (TCNR) bit is set to 1. As regards DST8I to DST8P, if the RLDEN bit in the reload enable register (RLDENR) is set to 1 and the reload register (RLDR8) value is not H'0000, a reload is performed into the corresponding DCNT8x, and the DST8x bit is set to 1. DST8x is automatically cleared to 0 when the DCNT8x value underflows, or by input of a channel 1 or 2 one-shot terminate trigger signal set in the trigger mode register (TRGMDR) while the corresponding one-shot pulse terminate register (OTR) bit is set to 1, whichever occurs first. DCNT8x is cleared to H'0000 when underflow occurs. DSTR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 10.3.5, One-Shot Pulse Function, and 10.3.6, Offset One-Shot Pulse Function and Output Cutoff Function. 290 • Bit 15—Down-Count Start 8P (DST8P): Starts down-counter 8P (DCNT8P). Bit 15: DST8P Description 0 DCNT8P is halted (Initial value) [Clearing conditions] When the DCNT8P value underflows, or on channel 2 (GR2H) comparematch 1 DCNT8P counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8P ≠ H'0000) • Offset one-shot pulse function: Set on OCR2H compare-match (DCNT8P ≠ H'0000 or reload possible) or by user program (DCNT8P ≠ H'0000) • Bit 14—Down-Count Start 8O (DST8O): Starts down-counter 8O (DCNT8O). Bit 14: DST8O Description 0 DCNT8O is halted (Initial value) [Clearing conditions] When the DCNT8O value underflows, or on channel 2 (GR2G) comparematch 1 DCNT8O counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8O ≠ H'0000) • Offset one-shot pulse function: Set on OCR2G compare-match (DCNT8O ≠ H'0000 or reload possible) or by user program (DCNT8O ≠ H'0000) • Bit 13—Down-Count Start 8N (DST8N): Starts down-counter 8N (DCNT8N). Bit 13: DST8N Description 0 DCNT8N is halted (Initial value) [Clearing conditions] When the DCNT8N value underflows, or on channel 2 (GR2F) comparematch 1 DCNT8N counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8N ≠ H'0000) • Offset one-shot pulse function: Set on OCR2F compare-match (DCNT8N ≠ H'0000 or reload possible) or by user program (DCNT8N ≠ H'0000) 291 • Bit 12—Down-Count Start 8M (DST8M): Starts down-counter 8M (DCNT8M). Bit 12: DST8M Description 0 DCNT8M is halted (Initial value) [Clearing conditions] When the DCNT8M value underflows, or on channel 2 (GR2E) comparematch 1 DCNT8M counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8M ≠ H'0000) • Offset one-shot pulse function: Set on OCR2E compare-match (DCNT8M ≠ H'0000 or reload possible) or by user program (DCNT8M ≠ H'0000) • Bit 11—Down-Count Start 8L (DST8L): Starts down-counter 8L (DCNT8L). Bit 11: DST8L Description 0 DCNT8L is halted (Initial value) [Clearing conditions] When the DCNT8L value underflows, or on channel 2 (GR2D) comparematch 1 DCNT8L counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8L ≠ H'0000) • Offset one-shot pulse function: Set on OCR2D compare-match (DCNT8L ≠ H'0000 or reload possible) or by user program (DCNT8L ≠ H'0000) • Bit 10—Down-Count Start 8K (DST8K): Starts down-counter 8K (DCNT8K). Bit 10: DST8K Description 0 DCNT8K is halted (Initial value) [Clearing conditions] When the DCNT8K value underflows, or on channel 2 (GR2C) comparematch 1 DCNT8K counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8K ≠ H'0000) • Offset one-shot pulse function: Set on OCR2C compare-match (DCNT8K ≠ H'0000 or reload possible) or by user program (DCNT8K ≠ H'0000) 292 • Bit 9—Down-Count Start 8J (DST8J): Starts down-counter 8J (DCNT8J). Bit 9: DST8J Description 0 DCNT8J is halted (Initial value) [Clearing conditions] When the DCNT8J value underflows, or on channel 2 (GR2B) comparematch 1 DCNT8J counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8J ≠ H'0000) • Offset one-shot pulse function: Set on OCR2B compare-match (DCNT8J ≠ H'0000 or reload possible) or by user program (DCNT8J ≠ H'0000) • Bit 8—Down-Count Start 8I (DST8I): Starts down-counter 8I (DCNT8I). Bit 8: DST8I Description 0 DCNT8I is halted (Initial value) [Clearing conditions] When the DCNT8I value underflows, or on channel 2 (GR2A) compare-match 1 DCNT8I counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8I ≠ H'0000) • Offset one-shot pulse function: Set on OCR2A compare-match (DCNT8I ≠ H'0000 or reload possible) or by user program (DCNT8I ≠ H'0000) • Bit 7—Down-Count Start 8H (DST8H): Starts down-counter 8H (DCNT8H). Bit 7: DST8H Description 0 DCNT8H is halted (Initial value) [Clearing conditions] When the DCNT8H value underflows, or on channel 1 (GR1H or OCR1) compare-match 1 DCNT8H counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8H ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1H compare-match, or by user program (DCNT8H ≠ H'0000) 293 • Bit 6—Down-Count Start 8G (DST8G): Starts down-counter 8G (DCNT8G). Bit 6: DST8G Description 0 DCNT8G is halted (Initial value) [Clearing conditions] When the DCNT8G value underflows, or on channel 1 (GR1G or OCR1) compare-match 1 DCNT8G counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8G ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1G compare-match, or by user program (DCNT8G ≠ H'0000) • Bit 5—Down-Count Start 8F (DST8F): Starts down-counter 8F (DCNT8F). Bit 5: DST8F Description 0 DCNT8F is halted (Initial value) [Clearing conditions] When the DCNT8F value underflows, or on channel 1 (GR1F or OCR1) compare-match 1 DCNT8F counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8F ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1F compare-match, or by user program (DCNT8F ≠ H'0000) • Bit 4—Down-Count Start 8E (DST8E): Starts down-counter 8E (DCNT8E). Bit 4: DST8E Description 0 DCNT8E is halted (Initial value) [Clearing conditions] When the DCNT8E value underflows, or on channel 1 (GR1E or OCR1) compare-match 1 DCNT8E counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8E ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1E compare-match, or by user program (DCNT8E ≠ H'0000) 294 • Bit 3—Down-Count Start 8D (DST8D): Starts down-counter 8D (DCNT8D). Bit 3: DST8D Description 0 DCNT8D is halted (Initial value) [Clearing conditions] When the DCNT8D value underflows, or on channel 1 (GR1D or OCR1) compare-match 1 DCNT8D counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8D ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1D compare-match, or by user program (DCNT8D ≠ H'0000) • Bit 2—Down-Count Start 8C (DST8C): Starts down-counter 8C (DCNT8C). Bit 2: DST8C Description 0 DCNT8C is halted (Initial value) [Clearing conditions] When the DCNT8C value underflows, or on channel 1 (GR1C or OCR1) compare-match 1 DCNT8C counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8C ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1C compare-match, or by user program (DCNT8C ≠ H'0000) • Bit 1—Down-Count Start 8B (DST8B): Starts down-counter 8B (DCNT8B). Bit 1: DST8B Description 0 DCNT8B is halted (Initial value) [Clearing conditions] When the DCNT8B value underflows, or on channel 1 (GR1B or OCR1) compare-match 1 DCNT8B counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8B ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1B compare-match, or by user program (DCNT8B ≠ H'0000) 295 • Bit 0—Down-Count Start 8A (DST8A): Starts down-counter 8A (DCNT8A). Bit 0: DST8A Description 0 DCNT8A is halted (Initial value) [Clearing conditions] When the DCNT8A value underflows, or on channel 1 (GR1A or OCR1) compare-match 1 DCNT8A counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8A ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1A compare-match, or by user program (DCNT8A ≠ H'0000) 10.2.12 Timer Connection Register (TCNR) The timer connection register (TCNR) is a 16-bit register. The ATU-II has one TCNR register in channel 8. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 CN8P CN8O CN8N CN8M CN8L CN8K CN8J CN8I 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 CN8H CN8G CN8F CN8E CN8D CN8C CN8B CN8A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TCNR is a 16-bit readable/writable register that enables or disables connection between the channel 8 down-count start register (DSTR) and channel 1 and 2 compare-match signals (downcount start triggers). Channel 1 down-count start triggers A to H are channel 1 OCR1 comparematch signals or GR1x compare-match signals (set in TRGMDR). Channel 2 down-count start triggers A to H are channel 2 OCR2x compare-match signals. When GR1x compare-matches are used, set TIOR1A to TIOR1D to allow compare-matches. TCNR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 10.3.5, One-Shot Pulse Function, and 10.3.6, Offset One-Shot Pulse Function and Output Cutoff Operation. 296 • Bit 15—Connection Flag 8P (CN8P): Enables or disables connection between DST8P and the channel 2 down-count start trigger. Bit 15: CN8P Description 0 Connection between DST8P and channel 2 down-count start trigger H is disabled (Initial value) 1 Connection between DST8P and channel 2 down-count start trigger H is enabled • Bit 14—Connection Flag 8O (CN8O): Enables or disables connection between DST8O and the channel 2 down-count start trigger. Bit 14: CN8O Description 0 Connection between DST8O and channel 2 down-count start trigger G is disabled (Initial value) 1 Connection between DST8O and channel 2 down-count start trigger G is enabled • Bit 13—Connection Flag 8N (CN8N): Enables or disables connection between DST8N and the channel 2 down-count start trigger. Bit 13: CN8N Description 0 Connection between DST8N and channel 2 down-count start trigger F is disabled (Initial value) 1 Connection between DST8N and channel 2 down-count start trigger F is enabled • Bit 12—Connection Flag 8M (CN8M): Enables or disables connection between DST8M and the channel 2 down-count start trigger. Bit 12: CN8M Description 0 Connection between DST8M and channel 2 down-count start trigger E is disabled (Initial value) 1 Connection between DST8M and channel 2 down-count start trigger E is enabled 297 • Bit 11—Connection Flag 8L (CN8L): Enables or disables connection between DST8L and the channel 2 down-count start trigger. Bit 11: CN8L Description 0 Connection between DST8L and channel 2 down-count start trigger D is disabled (Initial value) 1 Connection between DST8L and channel 2 down-count start trigger D is enabled • Bit 10—Connection Flag 8K (CN8K): Enables or disables connection between DST8K and the channel 2 down-count start trigger. Bit 10: CN8K Description 0 Connection between DST8K and channel 2 down-count start trigger C is disabled (Initial value) 1 Connection between DST8K and channel 2 down-count start trigger C is enabled • Bit 9—Connection Flag 8J (CN8J): Enables or disables connection between DST8J and the channel 2 down-count start trigger. Bit 9: CN8J Description 0 Connection between DST8J and channel 2 down-count start trigger B is disabled (Initial value) 1 Connection between DST8J and channel 2 down-count start trigger B is enabled • Bit 8—Connection Flag 8I (CN8I): Enables or disables connection between DST8I and the channel 2 down-count start trigger. Bit 8: CN8I Description 0 Connection between DST8I and channel 2 down-count start trigger A is disabled (Initial value) 1 Connection between DST8I and channel 2 down-count start trigger A is enabled 298 • Bit 7—Connection Flag 8H (CN8H): Enables or disables connection between DST8H and the channel 1 down-count start trigger. Bit 7: CN8H Description 0 Connection between DST8H and channel 1 down-count start trigger H is disabled (Initial value) 1 Connection between DST8H and channel 1 down-count start trigger H is enabled • Bit 6—Connection Flag 8G (CN8G): Enables or disables connection between DST8G and the channel 1 down-count start trigger. Bit 6: CN8G Description 0 Connection between DST8G and channel 1 down-count start trigger G is disabled (Initial value) 1 Connection between DST8G and channel 1 down-count start trigger G is enabled • Bit 5—Connection Flag 8F (CN8F): Enables or disables connection between DST8F and the channel 1 down-count start trigger. Bit 5: CN8F Description 0 Connection between DST8F and channel 1 down-count start trigger F is disabled (Initial value) 1 Connection between DST8F and channel 1 down-count start trigger F is enabled • Bit 4—Connection Flag 8E (CN8E): Enables or disables connection between DST8E and the channel 1 down-count start trigger. Bit 4: CN8E Description 0 Connection between DST8E and channel 1 down-count start trigger E is disabled (Initial value) 1 Connection between DST8E and channel 1 down-count start trigger E is enabled 299 • Bit 3—Connection Flag 8D (CN8D): Enables or disables connection between DST8D and the channel 1 down-count start trigger. Bit 3: CN8D Description 0 Connection between DST8D and channel 1 down-count start trigger D is disabled (Initial value) 1 Connection between DST8D and channel 1 down-count start trigger D is enabled • Bit 2—Connection Flag 8C (CN8C): Enables or disables connection between DST8C and the channel 1 down-count start trigger. Bit 2: CN8C Description 0 Connection between DST8C and channel 1 down-count start trigger C is disabled (Initial value) 1 Connection between DST8C and channel 1 down-count start trigger C is enabled • Bit 1—Connection Flag 8B (CN8B): Enables or disables connection between DST8B and the channel 1 down-count start trigger. Bit 1: CN8B Description 0 Connection between DST8B and channel 1 down-count start trigger B is disabled (Initial value) 1 Connection between DST8B and channel 1 down-count start trigger B is enabled • Bit 0—Connection Flag 8A (CN8A): Enables or disables connection between DST8A and the channel 1 down-count start trigger. Bit 0: CN8A Description 0 Connection between DST8A and channel 1 down-count start trigger A is disabled (Initial value) 1 Connection between DST8A and channel 1 down-count start trigger A is enabled 300 10.2.13 One-Shot Pulse Terminate Register (OTR) The one-shot pulse terminate register (OTR) is a 16-bit register. The ATU-II has one OTR register in channel 8. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 OTEP OTEO OTEN OTEM OTEL OTEK OTEJ OTEI 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 OTEH OTEG OTEF OTEE OTED OTEC OTEB OTEA 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W OTR is a 16-bit readable/writable register that enables or disables forced termination of channel 8 one-shot pulse output by channel 1 and 2 compare-match signals. When one-shot pulse output is forcibly terminated, the corresponding DSTR bit and down-counter are cleared, and the corresponding TSR8 bit is set. The channel 1 one-shot pulse terminate signal is generated by GR1A to GR1H compare-matches and OCR1 compare-match (see TRGMDR). The channel 2 one-shot pulse terminate signal is generated by GR2A to GR2H compare-matches. To generate the terminate signal with GR1A to GR1H and GR2A to GR2H, select the respective compare-matches in TIOR1A to TIOR1D. OTR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 15—One-Shot Pulse Terminate Enable P (OTEP): Enables or disables forced termination of output by channel 2 down-counter terminate trigger H. Bit 15: OTEP Description 0 Forced termination of TO8P by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8P by down-counter terminate trigger is enabled 301 • Bit 14—One-Shot Pulse Terminate Enable O (OTEO): Enables or disables forced termination of output by channel 2 down-counter terminate trigger G. Bit 14: OTEO Description 0 Forced termination of TO8O by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8O by down-counter terminate trigger is enabled • Bit 13—One-Shot Pulse Terminate Enable N (OTEN): Enables or disables forced termination of output by channel 2 down-counter terminate trigger F. Bit 13: OTEN Description 0 Forced termination of TO8N by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8N by down-counter terminate trigger is enabled • Bit 12—One-Shot Pulse Terminate Enable M (OTEM): Enables or disables forced termination of output by channel 2 down-counter terminate trigger E. Bit 12: OTEM Description 0 Forced termination of TO8M by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8M by down-counter terminate trigger is enabled • Bit 11—One-Shot Pulse Terminate Enable L (OTEL): Enables or disables forced termination of output by channel 2 down-counter terminate trigger D. Bit 11: OTEL Description 0 Forced termination of TO8L by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8L by down-counter terminate trigger is enabled • Bit 10—One-Shot Pulse Terminate Enable K (OTEK): Enables or disables forced termination of output by channel 2 down-counter terminate trigger C. Bit 10: OTEK Description 0 Forced termination of TO8K by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8K by down-counter terminate trigger is enabled 302 • Bit 9—One-Shot Pulse Terminate Enable J (OTEJ): Enables or disables forced termination of output by channel 2 down-counter terminate trigger B. Bit 9: OTEJ Description 0 Forced termination of TO8J by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8J by down-counter terminate trigger is enabled • Bit 8—One-Shot Pulse Terminate Enable I (OTEI): Enables or disables forced termination of output by channel 2 down-counter terminate trigger A. Bit 8: OTEI Description 0 Forced termination of TO8I by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8I by down-counter terminate trigger is enabled • Bit 7—One-Shot Pulse Terminate Enable H (OTEH): Enables or disables forced termination of output by channel 1 down-counter terminate trigger H. Bit 7: OTEH Description 0 Forced termination of TO8H by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8H by down-counter terminate trigger is enabled • Bit 6—One-Shot Pulse Terminate Enable G (OTEG): Enables or disables forced termination of output by channel 1 down-counter terminate trigger G. Bit 6: OTEG Description 0 Forced termination of TO8G by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8G by down-counter terminate trigger is enabled • Bit 5—One-Shot Pulse Terminate Enable F (OTEF): Enables or disables forced termination of output by channel 1 down-counter terminate trigger F. Bit 5: OTEF Description 0 Forced termination of TO8F by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8F by down-counter terminate trigger is enabled 303 • Bit 4—One-Shot Pulse Terminate Enable E (OTEE): Enables or disables forced termination of output by channel 1 down-counter terminate trigger E. Bit 4: OTEE Description 0 Forced termination of TO8E by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8E by down-counter terminate trigger is enabled • Bit 3—One-Shot Pulse Terminate Enable D (OTED): Enables or disables forced termination of output by channel 1 down-counter terminate trigger D. Bit 3: OTED Description 0 Forced termination of TO8D by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8D by down-counter terminate trigger is enabled • Bit 2—One-Shot Pulse Terminate Enable C (OTEC): Enables or disables forced termination of output by channel 1 down-counter terminate trigger C. Bit 2: OTEC Description 0 Forced termination of TO8C by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8C by down-counter terminate trigger is enabled • Bit 1—One-Shot Pulse Terminate Enable B (OTEB): Enables or disables forced termination of output by channel 1 down-counter terminate trigger B. Bit 1: OTEB Description 0 Forced termination of TO8B by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8B by down-counter terminate trigger is enabled • Bit 0—One-Shot Pulse Terminate Enable A (OTEA): Enables or disables forced termination of output by channel 1 down-counter terminate trigger A. Bit 0: OTEA Description 0 Forced termination of TO8A by down-counter terminate trigger is disabled (Initial value) 1 Forced termination of TO8A by down-counter terminate trigger is enabled 304 10.2.14 Reload Enable Register (RLDENR) The reload enable register (RLDENR) is an 8-bit register. The ATU-II has one RLDENR register in channel 8. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 RLDEN — — — — — — — 0 0 0 0 0 0 0 0 R/W R R R R R R R RLDENR is an 8-bit readable/writable register that enables or disables loading of the reload register8 (RLDR8) value into the down-counters (DCNT8I to DCNT8P). Loading is performed on generation of a channel 2 compare-match signal one-shot pulse start trigger. Reloading is not performed if there is no linkage with channel 2 (one-shot pulse function), or while the downcounter (DCNT8I to DCNT8P) is running. RLDENR is initialized to H'00 by a power-on reset and in hardware standby mode and software standby mode. • Bit 7—Reload Enable (RLDEN): Enables or disables loading of the RLDR value into DCNT8I to DCNT8P. Bit 7: RLDEN Description 0 Loading of reload register value into down-counters is disabled (Initial value) 1 Loading of reload register value into down-counters is enabled • Bits 6 to 0—Reserved: These bits always read 0. The write value should always be 0. 305 10.2.15 Free-Running Counters (TCNT) The free-running counters (TCNT) are 32- or 16-bit up- or up/down-counters. The ATU-II has 17 TCNT counters: one 32-bit TCNT in channel 0, and sixteen 16-bit TCNTs in each of channels 1 to 7 and 11. Channel Abbreviation Function 0 TCNT0H, TCNT0L 32-bit up-counter (initial value H’00000000) 1 TCNT1A, TCNT1B 16-bit up-counters (initial value H'0000) 2 TCNT2A, TCNT2B 3 TCNT3 4 TCNT4 5 TCNT5 6 TCNT6A to TCNT6D 16-bit up/down-counters (initial value H'0001) 7 TCNT7A to TCNT7D 16-bit up-counters (initial value H'0001) 11 TCNT11 16-bit up-counter (initial value H'0000) Free-Running Counter 0 (TCNT0H, TCNT0L): Free-running counter 0 (comprising TCNT0H and TCNT0L) is a 32-bit readable/writable register that counts on an input clock. When the bits corresponding to the timer start register 1 (TSTR1) are set to 1, this counter starts to count. The input clock is selected with prescaler register 1 (PSCR1). Bit: Initial value: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When TCNT0 overflows (from H'FFFFFFFF to H'00000000), the OVF0 overflow flag in the timer status register (TSR0) is set to 1. TCNT0 can only be accessed by a longword read or write. Word reads or writes cannot be used. TCNT0 is initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. 306 Free-Running Counters 1A, 1B, 2A, 2B, 3, 4, 5, 11 (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, TCNT11): Free-running counters 1A, 1B, 2A, 2B, 3, 4, 5, and 11 (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, TCNT11) are 16-bit readable/writable registers that count on an input clock. When the bits corresponding to the timer start register 1, 3 (TSTR1, TSTR3) are set to 1, these counters start to count. The input clock is selected with prescaler register 1 (PSCR1) and the timer control register (TCR). Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit name: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TCNT1A, TCNT1B, TCNT2A, and TCNT2B counters are cleared if incremented during counter clear trigger input from channel 10. TCNT3 to TCNT5 counter clearing is performed by a compare-match with the corresponding general register, according to the setting in TIOR. When one of counters TCNT1A/1B/2A/2B/3/4/5/11 overflows (from H'FFFF to H'0000), the overflow flag (OVF) for the corresponding channel in the timer status register (TSR) is set to 1. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, and TCNT11 can only be accessed by a word read or write. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, and TCNT11 are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, and TCNT5 can count on external clock (TCLKA or TCLKB) input. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, and TCNT5 can count on an external interrupt clock (TI10) (AGCK) generated in channel 10 and on a channel 10 multiplied clock (AGCKM). 307 Free-Running Counters 6A to 6D and 7A to 7D (TCNT6A to TCNT6D, TCNT7A to TCNT7D): Free-running counters 6A to 6D and 7A to 7D (TCNT6A to TCNT6D, TCNT7A to TCNT7D) are 16-bit readable/writable registers. Channel 6 and 7 counts are started by the timer start register (TSTR2). The clock input to channels 6 and 7 is selected with prescaler registers 2 and 3 (PSCR2, PSCR3) and timer control registers 6 and 7 (TCR6, TCR7). Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT6A to TCNT6D (in non-complementary PWM mode) and TCNT7A to TCNT7D are cleared by a compare-match with the cycle register (CYLR). TCNT6A to TCNT6D (in complementary PWM mode) count up and down between zero and the cycle register value. TCNT6A to TCNT6D and TCNT7A to TCNT7D are connected to the CPU by an internal 16-bit bus, and can only be accessed by a word read or write. TCNT6A to TCNT6D and TCNT7A to TCNT7D are initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. 10.2.16 Down-Counters (DCNT) The DCNT registers are 16-bit down-counters. The ATU-II has 16 DCNT counters in channel 8. Channel Abbreviation Function 8 DCNT8A, DCNT8B, DCNT8C, DCNT8D, DCNT8E, DCNT8F, DCNT8G, DCNT8H, DCNT8I, DCNT8J, DCNT8K, DCNT8L, DCNT8M, DCNT8N, DCNT8O, DCNT8P 16-bit down-counters 308 Down-Counters 8A to 8P (DCNT8A to DCNT8P): Down-counters 8A to 8P (DCNT8A to DCNT8P) are 16-bit readable/writable registers that count on an input clock. The input clock is selected with prescaler register 1 (PSCR1) and the timer control register (TCR). Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit name: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When the one-shot pulse function is used, DCNT8x starts counting down when the corresponding DSTR bit is set to 1 by the user program after the DCNT8x value has been set. When the DCNT8x value underflows, DSTR and DCNT8x are automatically cleared to 0, and the count is stopped. At the same time, the corresponding channel 8 timer status register 8 (TSR8) status flag is set to 1. When the offset one-shot pulse function is used, on compare-match with a channel 1 or 2 general register (GR) or output compare register (OCR) (the compare-match setting being made in the trigger mode register (TRGMDR) (for channel 1 only) ) when the corresponding timer connection register (TCNR) bit is 1, the corresponding down-count start register (DSTR) bit is automatically set to 1 and the down-count is started. When the DCNT8x value underflows, the corresponding DSTR bit and DCNT8x are automatically cleared to 0, the count is stopped, and the output is inverted, or, if a one-shot terminate register (OTR) setting has been made to forcibly terminate output by means of a trigger, DSTR is cleared to 0 by a channel 1 or 2 compare-match between GR and OCR, the count is forcibly terminated, and the output is inverted. The output is inverted for whichever is first. At the same time, the corresponding channel 8 TSR8 status flag is set to 1. The DCNT8x counters can only be accessed by a word read or write. The DCNT8x counters are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 10.3.5, One-Shot Pulse Function, and 10.3.6, Offset One-Shot Pulse Function and Output Cutoff Function. 10.2.17 Event Counters (ECNT) The event counters (ECNT) are 8-bit up-counters. The ATU-II has six ECNT counters in channel 9. Channel Abbreviation Function 9 ECNT9A, ECNT9B, ECNT9C, ECNT9D, ECNT9E, ECNT9F 8-bit event counters 309 The ECNT counters are 8-bit readable/writable registers that count on detection of an input signal from input pins TI9A to TI9F. Rising edge, falling edge, or both rising and falling edges can be selected for edge detection. Bit: 7 Initial value: R/W: 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W When a compare-match with GR9 corresponding to an ECNT9x counter occurs, the comparematch flag (CMF9) in the timer status register (TSR9) is set to 1. When a compare-match with GR occurs, the ECNT9x counter is cleared automatically. The ECNT9x counters can only be accessed by a byte read or write. The ECNT9x counters are initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. 10.2.18 Output Compare Registers (OCR) The output compare registers (OCR) are 16-bit registers. The ATU-II has nine OCR registers: one in channel 1 and eight in channel 2. Channel Abbreviation Function 1 OCR1 Output compare registers 2 OCR2A, OCR2B, OCR2C, OCR2D, OCR2E, OCR2F, OCR2G, OCR2H Output Compare Registers 1 and 2A to 2H (OCR1, OCR2A to OCR2H) Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The OCR registers are 16-bit readable/writable registers that have an output compare register function. The OCR and free-running counter (TCNT1B, TCNT2B) values are constantly compared, and if the two values match, the CMF bit in the timer status register (TSR) is set to 1. If channels 1 and 2 310 and channel 8 are linked by the timer connection register (TCNR), the corresponding channel 8 down-counter (DCNT) is started at the same time. The OCR registers can only be accessed by a word read. The OCR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. 10.2.19 Input Capture Registers (ICR) The input capture registers (ICR) are 32-bit registers. The ATU-II has four 32-bit ICR registers in channel 0. Channel Abbreviation Function 0 ICR0AH, ICR0AL, ICR0BH, ICR0BL, ICR0CH, ICR0CL, ICR0DH, ICR0DL Dedicated input capture registers Input Capture Registers 0AH, 0AL to 0DH, 0DL (ICR0AH, ICR0AL to ICR0DH, ICR0DL) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R The ICR registers are 32-bit read-only registers used exclusively for input capture. These dedicated input capture registers store the TCNT0 value on detection of an input capture signal from an external source. The corresponding TSR0 bit is set to 1 at this time. The input capture signal edge to be detected is specified by timer I/O control register TIOR0. By setting the TRG0DEN bit in TCR10, ICR0DH and ICR0DL can also be used for input capture in a compare match between TCNT10B and OCR10B. The ICR registers can only be accessed by a longword read. Word reads cannot be used. 311 The ICR registers are initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. 10.2.20 General Registers (GR) The general registers (GR) are 16-bit registers. The ATU-II has 36 general registers: eight each in channels 1 and 2, four each in channels 3 to 5, six in channel 9, and two in channel 11. Channel Abbreviation Function 1 GR1A to GR1H Dual-purpose input capture and output compare registers 2 GR2A to GR2H 3 GR3A to GR3D 4 GR4A to GR4D 5 GR5A to GR5D 9 GR9A to GR9F Dedicated output compare registers 11 GR11A, GR11B Compare match registers General Registers 1A to 1H and 2A to 2H (GR1A to GR1H, GR2A to GR2H) Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W These GR registers are 16-bit readable/writable registers with both input capture and output compare functions. Function switching is performed by means of the timer I/O control registers (TIOR). When a general register is used for input capture, it stores the TCNT1A or TCNT2A value on detection of an input capture signal from an external source. The corresponding IMF bit in TSR is set to 1 at this time. The input capture signal edge to be detected is specified by the corresponding TIOR. When a general register is used for output compare, the GR value and free-running counter (TCNT1A, TCNT2A) value are constantly compared, and when both values match, the IMF bit in the timer status register (TSR) is set to 1. If connection of channels 1 and 2 and channel 8 is specified in the timer connection register (TCNR), the corresponding channel 8 down-counter (DCNT) is started. Compare-match output is specified by the corresponding TIOR. The GR registers can only be accessed by a word read or write. 312 The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. General Registers 3A to 3D, 4A to 4D, and 5A to 5D (GR3A to GR3D, GR4A to GR4D, and GR5A to GR5D) Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W These GR registers are 16-bit readable/writable registers with both input capture and output compare functions. Function switching is performed by means of the timer I/O control registers (TIOR). When a general register is used for input capture, it stores the corresponding TCNT value on detection of an input capture signal from an external source. The corresponding IMF bit in TSR is set to 1 at this time. The input capture signal edge to be detected is specified by the corresponding TIOR. GR3A to GR3D can also be used for input capture with a channel 9 compare-match as the trigger. In this case, the corresponding IMF bit in TSR is not set. When a general register is used for output compare, the GR value and free-running counter (TCNT) value are constantly compared, and when both values match, the IMF bit in the timer status register (TSR) is set to 1. Compare-match output is specified by the corresponding TIOR. The GR registers can only be accessed by a word read or write. The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. General Registers 9A to 9F (GR9A to GR9F) Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: These GR registers are 8-bit readable/writable registers with a compare-match function. The GR value and event counter (ECNT) value are constantly compared, and when both values match a compare-match signal is generated and the next edge is input, the corresponding CMF bit in TSR is set to 1. 313 In addition, channel 3 (GR3A to GR3D) input capture can be generated by GR9A to GR9D compare-matches. This function is set by TRG3xEN in the timer control register (TCR). The GR registers can be accessed by a byte read or write. The GR registers are initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. General Registers 11A, B (GR11A, B) Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W These GR registers are 16-bit readable/writable registers with compare-match function. When a general register is used as a compare-match register, the GR value and free-running counter (TCNT) value are constantly compared, and when both values match, the IMF bit in the timer status register (TSR) is set to 1. Compare-match output is specified by the corresponding TIOR. GR11A and GR11B compare-mach signals are transmitted to the advanced pulse controller (APC). For details, see section 11, Advanced Pulse Controller (APC). The GR registers can only be accessed by a word read or write. The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. 10.2.21 Offset Base Registers (OSBR) The offset base registers (OSBR) are 16-bit registers. The ATU-II has two OSBR registers, one each in channels 1 and 2. Channel Abbreviation Function 1 OSBR1 2 OSBR2 Dedicated input capture registers with signal from channel 0 ICR0A as input trigger 314 Offset Base Registers 1 and 2 (OSBR1, OSBR2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R OSBR1 and OSBR2 are 16-bit read-only registers used exclusively for input capture. OSBR1 and OSBR2 use the channel 0 ICR0A input capture register input as their trigger signal, and store the TCNT1A or TCNT2A value on detection of an edge. The OSBR registers can only be accessed by a word read. The OSBR registers are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 10.3.8, Twin-Capture Function. 10.2.22 Cycle Registers (CYLR) The cycle registers (CYLR) are 16-bit registers. The ATU-II has eight cycle registers, four each in channels 6 and 7. Channel Abbreviation Function 6 CYLR6A to CYLR6D 16-bit PWM cycle registers 7 CYLR7A to CYLR7D Cycle Registers (CYLR6A to CYLR6D, CYLR7A to CYLR7D) Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The CYLR registers are 16-bit readable/writable registers used for PWM cycle storage. The CYLR value is constantly compared with the corresponding free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) value, and when the two values match, the corresponding timer start register (TSR) bit (CMF6A to CMF6D, CMF7A to CMF7D) is set to 1, and the freerunning counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) is cleared. At the same time, the buffer register (BFR) value is transferred to the duty register (DTR). 315 The CYLR registers can only be accessed by a word read or write. The CYLR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. For details of the CYLR, BFR, and DTR registers, see section 10.3.9, PWM Timer Function. 10.2.23 Buffer Registers (BFR) The buffer registers (BFR) are 16-bit registers. The ATU-II has eight buffer registers, four each in channels 6 and 7. Channel Abbreviation Function 6 BFR6A to BFR6D 16-bit PWM buffer registers 7 BFR7A to BFR7D Buffer register (BFR) value is transferred to duty register (DTR) on compare-match of corresponding cycle register (CYLR) Buffer Registers (BFR6A to BFR6D, BFR7A to BFR7D) Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The BFR registers are 16-bit readable/writable registers that store the value to be transferred to the duty register (DTR) in the event of a cycle register (CYLR) compare-match. The BFR registers can only be accessed by a word read or write. The BFR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. 316 10.2.24 Duty Registers (DTR) The duty registers (DTR) are 16-bit registers. The ATU-II has eight duty registers, four each in channels 6 and 7. Channel Abbreviation Function 6 DTR6A to DTR6D 16-bit PWM duty registers 7 DTR7A to DTR7D Duty Registers (DTR6A to DTR6D, DTR7A to DTR7D) Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The DTR registers are 16-bit readable/writable registers used for PWM duty storage. The DTR value is constantly compared with the corresponding free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) value, and when the two values match, the corresponding channel output pin (TO6A to TO6D, TO7A to TO7D) goes to 0 output. Also, when CYLR and the corresponding the free-running counter match, the corresponding BFR value is loaded. Set a value in the range 0 to CYLR for DTR; do not set a value greater than CYLR. The DTR registers can only be accessed by a word read or write. The DTR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. 317 10.2.25 Reload Register (RLDR) The reload register is a 16-bit register. The ATU-II has one RLDR register in channel 8. Reload Register 8 (RLDR8) Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RLDR8 is a 16-bit readable/writable register. When reload is enabled (by a setting in RLDENR) and DSTR8I to DSTR8P are set to 1 by the channel 2 compare-match signal one-shot pulse start trigger, the reload register value is transferred to DCNT8I to DCNT8P before the down-count is started. The reload register value is not transferred when the one-shot pulse function is used independently, without linkage to channel 2, or when down-counters DCNT8I to DCNT8P are running. RLDR8 can only be accessed by a word read or write. RLDR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. 10.2.26 Channel 10 Registers Counters (TCNT) Channel 10 has seven TCNT counters: one 32-bit TCNT, four 16-bit TCNTs, and two 8-bit TCNTs. The input clock is selected with prescaler register 4 (PSCR4). Count operations are performed by setting STR10 to 1 in timer start register 1 (TSTR1). Channel Abbreviation Function 10 TCNT10AH, AL 32-bit free-running counter (initial value H'00000001) TCNT10B 8-bit event counter (initial value H'00) TCNT10C 16-bit reload counter (initial value H'0001) TCNT10D 8-bit correction counter (initial value H'00) TCNT10E 16-bit correction counter (initial value H'0000) TCNT10F 16-bit correction counter (initial value H'0001) TCNT10G 16-bit free-running counter (initial value H'0000) 318 Free-Running Counter 10AH, AL (TCNT10AH, TCNT10AL): Free-running counter 10AH, AL (comprising TCNT10AH and TCNT10AL) is a 32-bit readable/writable register that counts on an input clock and is cleared by input capture input (TI10) (AGCK). Bit: Initial value: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10A can only be accessed by a longword read or write. Word reads or writes cannot be used. TCNT10A is initialized to H'00000001 by a power-on reset, and in hardware standby mode and software standby mode. Event Counter 10B (TCNT10B): Event counter 10B (TCNT10B) is an 8-bit readable/writable register that counts on external clock input (TI10) (AGCK). For this operation, TI10 input must be set with bits CKEG1 and CKEG0 in TCR10. TI10 input will be counted even if halting of the count operation is specified by bit STR10 in TSTR1. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TCNT10B can only be accessed by a byte read or write. TCNT10B is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. 319 Reload Counter 10C (TCNT10C): Reload counter 10C (TCNT10C) is a 16-bit readable/writable register. Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When TCNT10C = H'0001 in the down-count operation, the value in the reload register (RLD10C) is transferred to TCNT10C, and a multiplied clock (AGCK1) is generated. TCNT10C is connected to the CPU via an internal 16-bit bus, and can only be accessed by a word read or write. TCNT10C is initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. Correction Counter 10D (TCNT10D): Correction counter 10D (TCNT10D) is an 8-bit readable/writable register that counts on external clock input (TI10) after transfer of the counter value to correction counter E (TCNT10E). Set TI10 input with bits CKEG1 and CKEG0 in TCR10. Counting will not be performed on TI10 input unless the count operation is enabled by bit STR10 in TSTR1. Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: At the external clock input (TI10) (AGCK) timing, the value in this counter is shifted according to the multiplication factor set by bits PIM1 and PIM0 in timer I/O control register 10 (TIOR10) and transferred to correction counter E (TCNT10E). TCNT10D can only be accessed by a byte read or write. TCNT10D is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. 320 Correction Counter 10E (TCNT10E): Correction counter 10E (TCNT10E) is a 16-bit readable/writable register that loads the TCNT10D shift value at the external input (TI10) timing, and counts on the multiplied clock (AGCK1) output by reload counter 10C (TCNT10C). However, if CCS in timer I/O control register 10 (TIOR10) is set to 1, when the TCNT10D shifted value is reached the count is halted. Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10E can only be accessed by a word read or write. TCNT10E is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Correction Counter 10F (TCNT10F): Correction counter 10F (TCNT10F) is a 16-bit readable/writable register that counts up if the counter value is smaller than the correction counter 10E (TCNT10E) value when the STR10 bit in TSTR1 has been set for counter operation. The count is halted by a match with the correction counter clear register (TCCLR10). If TI10 is input when TCNT10D = H'0000, TCNT10F is initialized and correction is carried out. When TCNT10F = TCCLR10, TCNT10F is cleared to H'0001. While TCNT10F ≠ TCCLR10, TCNT10F is incremented automatically until it reaches the TCCLR10 value, and is then cleared to H'0001. A corrected clock (AGCKM) is output following correction each time this counter is incremented. Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10F is can only be accessed by a word read or write. TCNT10F is initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. 321 Free-Running Counter 10G (TCNT10G): Free-running counter 10G (TCNT10G) is a 16-bit readable/writable register that counts up on the multiplied clock (AGCK1). TCNT10G is initialized to H'0000 by input from external input (TI10) (AGCK). Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10G can only be accessed by a word read or write. TCNT10G is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Registers There are six registers in channel 10: a 32-bit ICR, 32-bit OCR, 16-bit GR, 16-bit RLD, 16-bit TCCLR, and 8-bit OCR. Channel Abbreviation Function 10 ICR10AH, AL 32-bit input capture register (initial value H'00000000) OCR10AH, AL 32-bit output compare register (initial value H'FFFFFFFF) OCR10B 8-bit output compare register (initial value H'FF) RLD10C 16-bit reload register (initial value H'0000) GR10G 16-bit general register (initial value H'FFFF) TCCLR10 16-bit correction counter clear register (initial value H'0000) 322 Input Capture Register 10AH, AL (ICR10AH, ICR10AL): Input capture register 10AH, AL (comprising ICR10AH and ICR10AL) is a 32-bit read-only register to which the TCNT10AH, AL value is transferred on external input (TI10) (AGCK). At the same time, ICF10A in timer status register 10 (TCR10) is set to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R ICR10A is initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. Output Compare Register 10AH, AL (OCR10AH, OCR10AL): Output compare register 10AH, AL (comprising OCR10AH and OCR10AL) is a 32-bit readable/writable register that is constantly compared with free-running counter 10AH, AL (TCNT10AH, TCNT10AL). When both values match, CMF10A in timer status register 10 (TSR10) is set to 1. Bit: Initial value: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCR10A is initialized to H'FFFFFFFF by a power-on reset, and in hardware standby mode and software standby mode. 323 Output Compare Register 10B (OCR10B): Output compare register 10B (OCR10B) is an 8-bit readable/writable register that is constantly compared with free-running counter 10B (TCNT10B). When AGCK is input with both values matching, CMF10B in timer status register 10 (TSR10) is set to 1. Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: OCR10B is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. Reload Register 10C (RLD10C): Reload register 10C (RLD10C) is a 16-bit readable/writable register. When STR10 in timer start register 1 (TSTR1) is 1 and RLDEN in the timer I/O control register (TIOR10) is 0, and the value of TCNT10A is captured into input capture register 10A (ICR10A), the ICR10A capture value is shifted according to the multiplication factor set by bits PIM1 and PIM0 in TIOR10 before being transferred to RLD10C. The contents of reload register 10C (RLD10C) are loaded when reload counter 10C (TCNT10C) reaches H'0001. Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RLD10C is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. General Register 10G (GR10G): General register 10G (GR10G) is a 16-bit readable/writable register with an output compare function. Function switching is performed by means of timer I/O control register 10 (TIOR10). The GR10G value and free-running counter 10G (TCNT10G) value are constantly compared, and when AGCK is input with both values matching, CMF10G in timer status register 10 (TSR10) is set to 1. Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W GR10G is initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. 324 Correction Counter Clear Register 10 (TCCLR10): Correction counter clear register 10 (TCCLR10) is a 16-bit readable/writable register. TCCLR10 is constantly compared with TCNT10F, and when the two values match, TCNT10F halts. TCNTxx can be cleared at this time by setting TRGxxEN (xx = 1A, 1B, 2A, 2B) in TCR10. Then, when TCNT10D is H'0000 and TI10 is input, TCNT10F is cleared to H'0001. Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCCLR10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Noise Canceler Registers There are two 8-bit noise canceler registers in channel 10: TCNT10H and NCR10. Channel Abbreviation Function 10 TCNT10H Noise canceler counter (Initial value H'00) NCR10 Noise canceler compare-match register (Initial value H'FF) Noise Canceler Counter 10H (TCNT10H): Noise canceler counter 10H (TCNT10H) is an 8-bit readable/writable register. When the noise canceler function is enabled, TCNT10H starts counting up on Pφ × 10, with the signal from external input (TI10) (AGCK) as a trigger. The counter operates even if STR10 is cleared to 0 in the timer start register (TSTR1). TI10 input is masked while the counter is running. When the count matches the noise canceler register (NCR10) value, the counter is cleared and TI10 input masking is released. Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: TCNT10H is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. 325 Noise Canceler Register 10 (NCR10): Noise canceler register 10 (NCR10) is an 8-bit readable/writable register used to set the upper count limit of noise canceler counter 10H (TCNT10H). TCNT10H is constantly compared with NCR10 during the count, and when a compare-match occurs the TCNT10H counter is halted and input signal masking is released. Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: NCR10 is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. Channel 10 Control Registers There are four control registers in channel 10. Channel Abbreviation Function 10 TIOR10 Reload setting, counter correction setting, external input (TI10) edge interval multiplier setting GR compare-match setting TCR10 (Initial value H'00) TCCLR10 counter clear source Noise canceler function enabling/disabling selection 326 External input (TI10) edge selection (Initial value H'00) TSR10 Input capture/compare-match status (Initial value H'0000) TIER10 Input capture/compare-match interrupt request enabling/disabling selection (Initial value H'0000) Timer I/O Control Register 10 (TIOR10): TIOR10 is an 8-bit readable/writable register that selects the value for multiplication of the external input (TI10) edge interval. It also makes a setting for using the general register (GR10G) for output compare, and makes the edge detection setting. TIOR10 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 6 5 4 3 RLDEN CCS PIM1 PIM0 — 0 0 0 0 0 0 0 0 R/W R/W R/W R/W — R/W R/W R/W Initial value: R/W: 2 1 0 IO10G2 IO10G1 IO10G0 • Bit 7—Reload Enable (RLDEN): Enables or disables transfer of the input capture register 10A (ICR10A) value to reload register 10C (RLD10C). Bit 7: RLDEN Description 0 Transfer of ICR10A value to RLD10C on input capture is enabled (Initial value) 1 Transfer of ICR10A value to RLD10C on input capture is disabled • Bit 6—Counter Clock Select (CCS): Selects the operation of correction counter 10E (TCNT10E). Set the multiplication factor with bits PIM1 and PIM0. Bit 6: CCS Description 0 TCNT10E count is not halted when TCNT10D x multiplication factor = TCNT10E* (Initial value) 1 TCNT10E count is halted when TCNT10D x multiplication factor = TCNT10E* Note: * When [TCNT10D × multiplication factor] matches the value of TCNT10E with bits 8 to 0 masked. • Bits 5 and 4—Pulse Interval Multiplier (PIM1, PIM0): These bits select the external input (TI10) cycle multiplier. Bit 5: PIM1 Bit 4: PIM0 Description 0 0 Counting on external input cycle × 32 1 Counting on external input cycle × 64 0 Counting on external input cycle × 128 1 Counting on external input cycle × 256 1 (Initial value) 327 • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bits 2 to 0—I/O Control 10G2 to 10G0 (IO10G2 to IO10G0): These bits select the function of general register 10G (GR10G). Bit 2: IO10G2 Bit 1: IO10G1 Bit 0: IO10G0 0 0 0 1 Description GR is an output compare register Compare-match disabled (Initial value) 1 GR10G = TCNT10G compare-match 1 * Cannot be used * * Cannot be used Timer Control Register 10 (TCR10): TCR10 is an 8-bit readable/writable register that selects the correction counter clear register (TCCLR10) compare-match counter clear source, enables or disables the noise canceler function, and selects the external input (TI10) edge. TCR10 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 6 5 4 3 TRG2BEN TRG1BEN TRG2AEN TRG1AEN TRG0DEN Initial value: R/W: 2 1 0 NCE CKEG1 CKEG0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bit 7—Trigger 2B Enable (TRG2BEN): Enables or disables counter clearing for channel 2 TCNT2B. If TCNT2B counts while clearing is enabled, TCNT2B will be cleared. Bit 7: TRG2BEN Description 0 Channel 2 counter B (TCNT2B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) 1 Channel 2 counter B (TCNT2B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled 328 • Bit 6—Trigger 1B Enable (TRG1BEN): Enables or disables counter clearing for channel 1 TCNT1B. If TCNT1B counts while clearing is enabled, TCNT1B will be cleared. Bit 6: TRG1BEN Description 0 Channel 1 counter B (TCNT1B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) 1 Channel 1 counter B (TCNT1B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled • Bit 5—Trigger 2A Enable (TRG2AEN): Enables or disables counter clearing for channel 2 TCNT2A. If TCNT2A counts while clearing is enabled, TCNT2A will be cleared. Bit 5: TRG2AEN Description 0 Channel 2 counter 2A (TCNT2A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) 1 Channel 2 counter 2A (TCNT2A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled • Bit 4—Trigger 1A Enable (TRG1AEN): Enables or disables counter clearing for channel 1 TCNT1A. If TCNT1A counts while clearing is enabled, TCNT1A will be cleared. Bit 4: TRG1AEN Description 0 Channel 1 counter 1A (TCNT1A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) 1 Channel 1 counter 1A (TCNT1A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled • Bit 3—Trigger 0D Enable (TRG0DEN): Enables or disables channel 0 ICR0D input capture signal requests. Bit 3: TRG0DEN Description 0 Capture requests for channel 0 input capture register (ICR0D) on event counter (TCNT10B) compare-match are disabled (Initial value) 1 Capture requests for channel 0 input capture register (ICR0D) on event counter (TCNT10B) compare-match are enabled 329 • Bit 2—Noise Canceler Enable (NCE): Enables or disables the noise canceler function. Bit 2: NCE Description 0 Noise canceler function is disabled 1 Noise canceler function is enabled (Initial value) • Bits 1 and 0—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the channel 10 external input (TI10) edge(s). The clock (AGCK) is generated by the detected edge(s). Bit 1: CKEG1 Bit 0: CKEG0 Description 0 0 TI10 input disabled 1 TI10 input rising edges detected 0 TI10 input falling edges detected 1 TI10 input rising and falling edges both detected 1 (Initial value) Timer Status Register 10 (TSR10): TSR10 is a 16-bit readable/writable register that indicates the occurrence of channel 10 input capture or compare-match. Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is enabled by the corresponding bit in timer interrupt enable register 10 (TIER10). TSR10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/(W)* R/(W)* R/(W)* R/(W)* CMF10G CMF10B ICF10A CMF10A Note: * Only 0 can be written, to clear the flag. • Bits 15 to 4—Reserved: These bits always read 0. The write value should always be 0. 330 • Bit 3—Compare-Match Flag 10G (CMF10G): Status flag that indicates GR10G comparematch. Bit 3: CMF10G Description 0 [Clearing condition] (Initial value) When CMF10G is read while set to 1, then 0 is written to IMF10G 1 [Setting condition] When TCNT10G = GR10G • Bit 2—Compare-Match Flag 10B (CMF10B): Status flag that indicates OCR10B comparematch. Bit 2: CMF10B Description 0 [Clearing condition] (Initial value) When CMF10B is read while set to 1, then 0 is written to CMF10B 1 [Setting condition] When TCNT10B is incremented while TCNT10B = OCR10B • Bit 1—Input Capture Flag 10A (ICF10A): Status flag that indicates ICR10A input capture. Bit 1: ICF10A Description 0 [Clearing condition] (Initial value) When ICR10A is read while set to 1, then 0 is written to ICR10A 1 [Setting condition] When the TCNT10A value is transferred to ICR10A by an input capture signal • Bit 0—Compare-Match Flag 10A (CMF10A): Status flag that indicates OCR10A comparematch. Bit 0: CMF10A Description 0 [Clearing condition] (Initial value) When CMF10A is read while set to 1, then 0 is written to CMF10A 1 [Setting condition] When TCNT10A = OCR10A 331 Timer Interrupt Enable Register 10 (TIER10): TIER10 is a 16-bit readable/writable register that controls enabling/disabling of channel 10 input capture and compare-match interrupt requests. TIER10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W IREG CME10G CME10B ICE10A CME10A • Bits 15 to 5—Reserved: These bits always read 0. The write value should always be 0. • Bit 4—Interrupt Enable Edge G (IREG): Specifies TSR10 CMF10G interrupt request timing. Bit 4: IREG Description 0 Interrupt is requested when CMF10G becomes 1 1 Interrupt is requested by next external input (TI10) (AGCK) after CMF10G becomes 1 (Initial value) • Bit 3—Compare-Match Interrupt Enable 10G (CME10G): Enables or disables interrupt requests by CMF10G in TSR10 when CMF10G is set to 1. Bit 3: CME10G Description 0 CMI10G interrupt requested by CMF10G is disabled 1 CMI10G interrupt requested by CMF10G is enabled (Initial value) • Bit 2—Compare-Match Interrupt Enable 10B (CME10B): Enables or disables interrupt requests by CMF10B in TSR10 when CMF10B is set to 1. Bit 2: CME10B Description 0 CMI10B interrupt requested by CMF10B is disabled 1 CMI10B interrupt requested by CMF10B is enabled 332 (Initial value) • Bit 1—Input Capture Interrupt Enable 10A (ICE10A): Enables or disables interrupt requests by ICF10A in TSR10 when ICF10A is set to 1. Bit 1: ICE10A Description 0 ICI10A interrupt requested by ICF10A is disabled 1 ICI10A interrupt requested by ICF10A is enabled (Initial value) • Bit 0—Compare-Match Interrupt Enable 10A (CME10A): Enables or disables interrupt requests by CMF10A in TSR10 when CMF10A is set to 1. Bit 0: CME10A Description 0 CMI10A interrupt requested by CMF10A is disabled 1 CMI10A interrupt requested by CMF10A is enabled 10.3 Operation 10.3.1 Overview (Initial value) The ATU-II has twelve timers of eight kinds in channels 0 to 11. It also has a built-in prescaler that generates input clocks, and it is possible to generate or select internal clocks of the required frequency independently of circuitry outside the ATU-II. The operation of each channel and the prescaler is outlined below. Channel 0: Channel 0 has a 32-bit free-running counter (TCNT0) and four 32-bit input capture registers (ICR0A to ICR0D). TCNT0 is an up-counter that performs free-running operation. An interrupt request can be generated on counter overflow. The four input capture registers (ICR0A to ICR0D) capture the free-running counter (TCNT0) value by means of input from the corresponding external signal input pin (TI0A to TI0D). For capture by means of input from an external signal input pin, rising edge, falling edge, or both edges can be selected in the timer I/O control register (TIOR0). In the case of input capture register 0D (ICR0D) only, capture can be performed by means of a compare-match between free-running counter 10B (TCNT10B) and compare-match register 10B (OCR10B), by making a setting in timer control register 10 (TCR10). In this case, capture is performed even if an input capture disable setting has been made for TIOR0. In each case, the DMAC can be activated or an interrupt requested when capture occurs. Channel 0 also has three interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B). A/D converter (AD0 to AD2) activation can be selected by setting 1 in ITVA6 to ITVA13 in ITVRR, and an interrupt request to the CPU by setting 1 in ITVE6 to ITVE13. These operations are performed when the corresponding bit of bits 6 to 13 in TCNT0 changes to 1, enabling use as an interval timer function. 333 Channel 1: Channel 1 has two 16-bit free-running counters (TCNT1A, TCNT1B), eight 16-bit general registers (GR1A to GR1H), and a 16-bit output compare register (OCR1). TCNT1A and TCNT1B are up-counters that perform free-running operation. When the clock generated in channel 10 (described below) is selected, these counters can be cleared at the count specified in channel 10. Each counter can generate an interrupt request when it overflows. The eight general registers (GR1A to GR1H) can be used as input capture or output compare registers using the corresponding external signal I/O pin (TIO1A to TIO1H). When used for input capture, the free-running counter (TCNT1A) value is captured by means of input from the corresponding external signal I/O pin (TIO1A to TIO1H). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR1A to TIOR1D). When used for output compare, compare-match with the free-running counter (TCNT1A) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR1A to TIOR1D). When used as output compare registers, a compare-match can be used as a one-shot pulse start/terminate trigger by setting the channel 8 timer connection register (TCNR) and oneshot pulse terminate register (OTR), and using these in combination with the down-counters (DCNT8A to DCNT8H). Start/terminate trigger selection is performed by means of the trigger mode register (TRGMDR). The output compare register (OCR1) can be used as a one-shot pulse offset function, in the same way as the general registers, in combination with channel 8 down-counters DCNT8A to DCNT8H. An interrupt can be requested on the occurrence of the respective input capture or compare-match. In addition, channel 1 has a 16-bit dedicated input capture register (OSBR1). The channel 0 TI0A input pin can also be used as the OSBR1 trigger input, enabling use of a twin-capture function. Channel 2: Channel 2 has two 16-bit free-running counters (TCNT2A, TCNT2B), eight 16-bit general registers (GR2A to GR2H), and eight 16-bit output compare registers (OCR2A to OCR2H). TCNT2A and TCNT2B are up-counters that perform free-running operation. When the clock generated in channel 10 (described below) is selected, these counters can be cleared at the count specified in channel 10. Each counter can generate an interrupt request when it overflows. The eight general registers (GR2A to GR2H) can be used as input capture or output compare registers using the corresponding external signal I/O pin (TIO2A to TIO2H). When used for input capture, the free-running counter (TCNT2A) value is captured by means of input from the corresponding external signal I/O pin (TIO2A to TIO2H). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR2A to TIOR2D). When used for output compare, compare-match with the free-running counter (TCNT2A) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR2A to 334 TIOR2D). When used as output compare registers, a compare-match can be used as a one-shot pulse terminate trigger by setting the channel 8 one-shot pulse terminate register (OTR), and using this in combination with the down-counters (DCNT8A to DCNT8H). In the case of the output compare registers (OCR2A to OCR2H), a TCNT2B compare-match can be used as a one-shot pulse start trigger by setting the channel 8 timer connection register (TCNR), and using this in combination with the down-counters (DCNT8I to DCNT8P). An interrupt can be requested on the occurrence of the respective input capture or compare-match. In addition, channel 2 has a 16-bit dedicated input capture register (OSBR2). The channel 0 TI0A input pin can also be used as the OSBR2 trigger input, enabling use of a twin-capture function. Channels 3 to 5: Channels 3 to 5 each have a 16-bit free-running counter (TCNT3 to TCNT5) and four 16-bit general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D). TCNT3 to TCNT5 are up-counters that perform free-running operation. Channels 3 to 5 each have a 16-bit free-running counter (TCNT3 to TCNT5) and four 16-bit general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D). TCNT3 to TCNT5 are up-counters that perform free-running operation. In addition, counter clearing can be performed by compare-match by making a setting in the timer I/O control register (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). Each counter can generate an interrupt request when it overflows. The four general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D) each have corresponding external signal I/O pins (TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D), and can be used as input capture or output compare registers. When used for input capture, the free-running counter (TCNT3 to TCNT5) value is captured by means of input from the corresponding external signal I/O pin (TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). Also, in use for input capture, input capture can be performed using a compare-match between a channel 9 event counter (ECNT9A to ECNT9D), described later, and a general register (GR9A to GR9D) as the trigger. In this case, capture is performed even if an input capture disable setting has been made for TIOR3A to TIOR3D. When used for output compare, compare-match with the free-running counter (TCNT3 to TCNT5) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). An interrupt can be requested on the occurrence of the respective input capture or compare-match. However, in the case of input capture using channel 9 as a trigger, an interrupt request from channel 3 cannot be used. By selecting PWM mode in the timer mode register (TMDR), PWM output can be obtained, with three outputs for each. In this case, GR3D, GR4D, and GR5D are automatically used as cycle registers, and GR3A to GR3C, GR4A to GR4C, GR5A to GR5C, as duty registers. TCNT3 to TCNT5 are cleared by the corresponding GR3D, GR4D, or GR5D compare-match. 335 Channels 6 and 7: Channels 6 and 7 each have 16-bit free-running counters (TCNT6A to TCNT6D, TCNT7A to TCNT7D), 16-bit cycle registers (CYLR6A to CYLR6D, CYLR7A to CYLR7D), 16-bit duty registers (DTR6A to DTR6D, DTR7A to DTR7D), and buffer registers (BFR6A to BFR6D, BFR7A to BFR7D). Channels 6 and 7 also each have external output pins (TO6A to TO6D, TO7A to TO7D), and can be used as buffered PWM timers. The TCNT registers are up-counters, and 0 is output to the corresponding external output pin when the TCNT value matches the DTR value (when DTR ≠ CYLR). When the TCNT value matches the CYLR value (when DTR ≠ H'0000), 1 is output to the external output pin, TCNT is initialized to H'0001, and the BFR value is transferred to DTR. Thus, the configuration of channels 6 and 7 enables them to perform waveform output with the CYLR value as the cycle and the DTR value as the duty, and to use BFR to absorb the time lag between setting of data in DTR and compare-match occurrence. When DTR = CYLR, 1 is output continuously to the external output pin, giving a duty of 100%. When DTR = H'0000, 0 is output continuously to the external output pin, giving a duty of 0%. Do not set a value in DTR that will result in the condition DTR > CYLR. In channel 6, TCNT can also be designated for complementary PWM output by means of the PWM mode register (PMDR). When the corresponding TSTR is set to 1, TCNT starts counting up, then switches to a down-count when the count matches the CYLR value. When TCNT reaches H'0000, it starts counting up again. When TCNT = DTR, the corresponding TO6A to TO6D output changes. Whether TCNT is counting up or down can be ascertained from the timer status register (TSR6). DMAC activation and interrupt request generation, respectively, are possible when TCNT = CYLR in asynchronous PWM mode, and when TCNT = H'0000 in complementary PWM mode. Channel 8: Channel 8 has sixteen 16-bit down-counters (DCNT8A to DCNT8P). The downcounters have corresponding external signal output pins, and can generate one-shot pulses. Setting a value in DCNT and setting the corresponding bit to 1 in the down-count start register (DSTR) starts DCNT operation and simultaneously outputs 1 to the external output pin. When DCNT counts down to H'0000, it stops and outputs 0 to the external output pin. An interrupt can be requested when DCNT underflows. Down-counter operation can be coupled with the channel 1 or channel 2 output compare function by means of settings in the timer connection register (TCNR) and one-shot pulse terminate register (OTR), respectively, so that DCNT8I to DCNT8H count operations are started and stopped from channel 1, and DCNT8I to DCNT8P count operations from channel 2. DCNT8I to DCNT8P have a reload register (RLDR), and a setting in the reload enable register (RLDEN) enables count operations to be started after reading the value from this register. Channel 9: Channel 9 has six 8-bit event counters (ECNT9A to ECNT9F) and six 8-bit general registers (GR9A to GR9F). The event counters are up-counters, each with a corresponding external input pin (ECNT9A to ECNT9F). The event counter value is incremented by input from 336 the corresponding external input pin. Incrementing on the rising edge, falling edge, or both edges can be selected by means of settings in the timer control registers (TCR9A to TCR9C). An event counter is cleared by edge input after a match with the corresponding general register. An interrupt can requested when an event counter is cleared. Timer control register (TCR9A, TCR9B) settings can be made to enable event counters ECNT9A to ECNT9D to send a compare-match signal to channel 3 when the count matches the corresponding general register (GR9A to GR9D), allowing input capture to be performed on channel 3. This enables the pulse input interval to be measured. Channel 10: Channel 10 generates a multiplied clock based on external input, and supplies this to channels 1 to 5. Channel 10 is divided into three blocks: (1) an inter-edge measurement block, (2) a multiplied clock generation block, and (3) a multiplied clock correction block. (1) Inter-edge measurement block This block has a 32-bit free-running counter (TCNT10A), 32-bit input capture register (ICR10A), 32-bit output compare register (OCR10A), 8-bit event counter (TCNT10B), 8-bit output compare register (OCR10B), 8-bit noise canceler counter (TCNT10H), and 8-bit noise canceler compare-match register (NCR10). The 32-bit free-running counter (TCNT10A) is an up-counter that performs free-running operations. When input capture is performed by means of TI10 input, this counter is cleared to H'00000001. When free-running counter (TCNT10A) reaches the value set in the output compare register (OCR10A), a compare-match interrupt can be requested. The input capture register (ICR10A) has an external signal input pin (TI10), and the freerunning counter (TCNT10A) value can be captured by means of input from TI10. Rising edge, falling edge, or both edges can be selected by making a setting in bits CKEG1 and CKEG0 in the timer control register (TCR10). The TI10 input has a noise canceler function, which can be enabled by setting the NCE bit in the timer control register (TCR10). When the counter value is captured, TCNT10A is cleared to 0 and an interrupt can be requested. The captured value can be transferred to the multiplied clock generation block reload register (RLD10C). The 8-bit event counter (TCNT10B) is an up-counter that is incremented by TI10 input. When the event counter (TCNT10B) value reaches the value set in the output compare register (OCR10B), a compare-match interrupt can be requested. By setting the TRG0DEN bit in the timer control register (TCR10), a capture request can also be issued for the channel 0 input capture register 0D (ICR0D) when compare-match occurs. The 8-bit noise canceler counter (TCNT10H) and 8-bit noise canceler compare-match register (NCR10) are used to set the period for which the noise canceler functions. By setting a value in the noise canceler compare-match register (TCNT10H) and setting the NCE bit in the timer control register (TCR10), TI10 input is masked when it occurs. At the same time as TI10 input is masked, the noise canceler counter (TCNT10H) starts counting up on the Pφx10 clock. 337 When the noise canceler counter (TCNT10H) value matches the noise canceler compare-match register (NCR10) value, the noise canceler counter (TCNT10H) is cleared to H'0000 and TI10 input masking is cleared. (2) Multiplied clock generation block This block has 16-bit reload counters (TCNT10C, RLD10C), a 16-bit register free-running counter (TCNT10G), and a 16-bit general register (GR10G). 16-bit reload counter 10C (RLD10C) is captured by 32-bit input capture register 10A (ICR10A), and when RLDEN in the timer I/O control register (TIOR10) is 0, the value captured in input capture register 10A is transferred to the multiplied clock generation block reload register (RLD10C). The value transferred can be selected from 1/32, 1/64, 1/128, or 1/256 the original value, according to the setting of bits PIM1 and PIM0 in TIOR10. 16-bit reload counter 10C (TCNT10C) performs down-count operations. When TCNT10C reaches H'0001, the value is read automatically from the reload buffer (RLD10C), internal clock AGCK1 is generated, and the down-count operation is repeated. Internally generated AGCK1 is input as a clock to the multiplied clock correction block 16-bit correction counter (TCNT10E) and 16-bit free-running counter 10G (TCNT10G). 16-bit register free-running counter 10G (TCNT10G) counts on AGCK1 generated by TCNT10C. It is initialized to H'0000 by external input from TI10. The 16-bit general register (GR10G) can be used in a compare-match with free-running counter 10G (TCNT10G) by setting bits IO10G2 to IO10G0 in the timer I/O control register (TIOR10). An interrupt can be requested when a compare-match occurs. Also, by setting timer interrupt enable register 10 (TIER10), an interrupt can be request in the event of TI10 input after a compare-match. (3) Multiplied clock correction block This block has three 16-bit correction counters (TCNT10D, TCNT10E, TCNT10F) and a 16bit correction counter clear register (TCCLR10). When 32-bit input capture register 10A (ICR10A) performs a capture operation due to input from external input pin TI10, the value in correction counter 10D (TCNT10D) is transferred to TCNT10E and TCNT10D is incremented. The value transferred to TCNT10E is 32, 64, 128, or 256 times the TCNT10D value, according to the setting of bits PIM1 and PIM0 in the timer I/O control register (TIOR10). 16-bit correction counter 10E (TCNT10E) counts up on AGCK1 generated by reload counter 10C (TCNT10C, RLD10C) in the multiplied clock generation block. However, by setting the CCS bit in the timer I/O control register (TIOR10), it is possible to stop free-running counter 10E (TCNT10E) when the free-running counter 10D (TCNT10D) multiplication value specified by PIM1 and PIM0 and the free-running counter 10E (TCNT10E) value match. The multiplied TCNT10D value is transferred when input capture register 10A (ICR10A) performs a capture operation due to TI10 input. 338 16-bit correction counter 10F (TCNT10F) has Pφ as its input and is constantly compared with 16-bit correction counter 10E (TCNT10E). When the 16-bit correction counter 10F (TCNT10F) value is smaller than that in 16-bit correction counter 10E (TCNT10E), it is incremented and generates count-up AGCKM. When the 16-bit correction counter 10F (TCNT10F) value exceeds that in 16-bit correction counter 10E (TCNT10E) (for example, when TCNT10F reloads TCNT10D), no count-up operation is performed. The TI10 multiplied signal (AGCKM) generated when TCNT10F is incremented is output to the channel 1 to 5 free-running counters (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5), and an up-count can be performed on AGCKM by setting this as the counter clock on each channel. TCNT10F is constantly compared with the 16-bit correction counter clear register (TCCLR10), and when the free-running counter 10F (TCNT10F) and correction counter clear register (TCCLR10) values match, the TCNT10F up-count stops. Setting TRG1AEN, TRG1BEN, TRG2AEN, and TRG2BEN in the timer control register (TCR10) enables the channel 1 and 2 free-running counters (TCNT1A, TCNT1B, TCNT2A, TCNT2B) to be cleared at this time. If TI10 is input when TCNT10D = H'0000, initialization and correction operations are performed. When TCNT10F = TCCLR10, TCNT10F is cleared to H'0001. When TCNT10F ≠ TCCLR10, TCNT10F automatically counts up to the TCCLR10 value, and is cleared to H'0001. Channel 11: Channel 11 has a 16-bit free-running counter (TCNT11) and two 16-bit general registers (GR11A, GR11B). TCNT11 is an up-counter that performs free-running operation. The counter can generate an interrupt request when it overflows. When the two general registers (GR11A, GR11B) are designated for compare-match use, a compare-match signal can be output to the APC. Prescaler: The ATU-II has a dedicated prescaler with a 2-stage configuration. The first stage comprises 5-bit prescalers (PSCR1 to PSCR4) that generate a 1/m clock (where m = 1 to 32) with respect to clock Pφ. The second prescaler stage allows selection of a clock obtained by further scaling the clock from the first stage by 2n (where n = 0 to 5) according to the timer control registers for the respective channels (TCR1A, TCR1B, TCR2A, TCR2B, TCR3 to TCR5, TCR6A, TCR6B, TCR7A, TCR7B, TCR8, TCR11). The prescalers of channels 1 to 8 and 11 have a 2-stage configuration, while the channel 0 and 10 prescalers only have a first stage. The first-stage prescaler is common to channels 0 to 5, 8, and 11, and it is not possible to set different first-stage division ratios for each. Channels 6, 7, and 10 each have a first-stage prescaler, and different first-stage division ratios can be set for each. 10.3.2 Free-Running Counter Operation and Cyclic Counter Operation The free-running counters (TCNT) in ATU-II channels 0 to 5 and 11 start counting up as freerunning counters when the corresponding timer start register (TSTR) bit is set to 1. When TCNT overflows (channel 0: from H'FFFFFFFF to H'00000000; channels 1 to 5 and 11: from H'FFFF to H'0000), the OVF bit in the timer status register (TSR) is set to 1. If the OVE bit in the 339 corresponding timer interrupt enable register (TIER) is set to 1 at this time, an interrupt request is sent to the CPU. After overflowing, TCNT starts counting up again from H'00000000 or H'0000. If the TSTR value is cleared to 0 during TCNT operation, the corresponding TCNT halts. In this case, TCNT is not reset. If external output is being performed from the GR for the corresponding TCNT, the output value does not change. Channel 0 free-running counter operation is shown in figure 10.13. Pø TSTR TST0 TCNT0 Clock TCNT0 00000001 00000001 00000002 00000003 00000004 00000005 FFFFFFFD FFFFFFFE FFFFFFFF 00000000 00000001 00000002 Cleared by software TSR0 OVF0 Figure 10.13 Free-Running Counter Operation and Overflow Timing The free-running counters (TCNT) in ATU-II channels 6 and 7 perform cyclic count operations unconditionally. With channel 3 to 5 free-running counters (TCNT), when the corresponding T3PWM to T5PWM bit in the timer mode register (TMDR) is set to 1, or the corresponding CCI bit in the timer I/O control register (TIOR) is set to 1 when bits T3PWM to T5PWM are 0, the counter for the relevant channel performs a cyclic count. The relevant TCNT counter is cleared by a compare-match of TCNT with GR3D, GR4D, or GR5D in channel 3 to 5, or CYLR in channels 6 and 7 (counter clear function). TCNT starts counting up as a cyclic counter when the corresponding STR bit in TSTR is set to 1 after the TMDR setting is made. When the count value matches the GR3D, GR4D, GR5D, or CYLR value, the corresponding IMF3D, IMF4D, or IMF5D bit in the timer status register (TSR) (or the CMF bit in TSR6 or TSR7 for channels 6 and 7) is set to 1, and TCNT is cleared to H'0000 (H'0001 in channels 6 and 7). If the corresponding TIER bit is set to 1 at this time, an interrupt request is sent to the CPU. After the compare-match, TCNT starts counting up again from H'0000 (H'0001 in channels 6 and 7). Figure 10.14 shows the operation when channel 3 is used as a cyclic counter (with a cycle setting of H'0008). 340 Pø TCNT3 Clock TCNT3 GR3D (period) 0008 0000 0001 0002 0003 0008 0007 0008 0000 0001 0002 0003 0004 0005 0008 Cleared by software Cleared by software TSR3 IMF3D Figure 10.14 Example of Cyclic Counter Operation 10.3.3 Compare-Match Function Designating general registers in channels 1 to 5 (GR1A to GR1H, GR2A to GR2H, GR3A to GR3D, GR4A to GR4D, GR5A to GR5D) for compare-match operation in the timer I/O control registers (TIOR1 to TIOR5) enables compare-match output to be performed at the corresponding external pins (TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D). A free-running counter (TCNT) starts counting up when 1 is set in the timer status register (TSTR). When the desired number is set beforehand in GR, and the TCNT value matches the GR value, the timer status register (TSR) bit corresponding to GR is set and a waveform is output from the corresponding external pin. 1 output, 0 output, or toggle output can be selected by means of a setting in TIOR. If the appropriate interrupt enable register (TIER) setting is made, an interrupt request will be sent to the CPU when a compare-match occurs. Channel 1 and 2 compare-match registers (OCR1, OCR2A to OCR2H) perform compare-match operations unconditionally. However, there are no corresponding output pins. If the appropriate TIER setting is made, an interrupt request will be sent to the CPU when a compare-match occurs. Channel 1 and 2 GR and OCR registers can send a trigger/terminate signal to channel 8 when a compare-match occurs. In this case, settings should be made in the trigger mode register (TRGMDR), timer connection register (TCNR), and one-shot pulse terminate register (OTR). An example of compare-match operation is shown in figure 10.15. In the example in figure 10.15, channel 1 is activated, and external output is performed with toggle output specified for GR1A, 1 output for GR1B, and 0 output for GR1C. 341 Pø TCNT1 Clock TCNT1 GR1A–1C 003C 003D 003E 003F 0040 003E 007E 007F 0080 0081 0082 0083 0084 0085 0081 TIO1A TIO1B TIO1C TSR1 IMF1A–1D Cleared by software Cleared by software Channel 8 start/terminate trigger signal Figure 10.15 Compare-Match Operation 10.3.4 Input Capture Function If input capture registers (ICR0A to ICR0D) and general registers (GR1A to GR1H, GR2A to GR2H, GR3A to GR3D, GR4A to GR4D, GR5A to GR5D) in channels 0 to 5 and 11 are designated for input capture operation in the timer I/O control registers (TIOR0 to TIOR5), input capture is performed when an edge is input at the corresponding external pins (TI0A to TI0D, TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D). A free-running counter (TCNT) starts counting up when a setting is made in the timer start register (TSTR). When an edge is input at an external pin corresponding to ICR or GR, the corresponding timer status register (TSR) bit is set and the TCNT value is transferred to ICR or GR. Rising-edge, falling-edge, or both-edge detection can be selected. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. 342 An example of input capture operation is shown in figure 10.16. In the example in figure 10.16, channel 1 is activated, and input capture operation is performed with both-edge detection specified for TIO1A, rising-edge detection for TIO1B, and falling-edge detection for TIO1C. Pø TCNT1 Clock TCNT1 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E TIO1A–1C GR1A 0003 567A GR1B 0003 0003 GR1C 567A Cleared by software Cleared by software TSR1 IMF1A TSR1 IMF1B TSR1 IMF1C Figure 10.16 Input Capture Operation 10.3.5 One-Shot Pulse Function Channel 8 has sixteen down-counters (DCNT8A to DCNT8P) and corresponding external pins (TO8A to TO8P) which can be used as one-shot pulse output pins. When a value is set beforehand in DCNT and the corresponding bit in the down-counter start register (DSTR) is set, DCNT starts counting down, and at the same time 1 is output from the corresponding external pin. When DCNT reaches H'0000 the down-count stops, the corresponding bit in the timer status register (TSR) is set, and 0 is output from the external pin. The corresponding bit in DSTR is cleared automatically. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. An example of one-shot pulse operation is shown in figure 10.17. In the example in figure 10.17, H'0005 is set in DCNT and a down-count is started. 343 Pø DSTR DST8A DCNT Clock Synchronized with down-counter clock TO8A DCNT8A 0005 0004 0003 0002 0001 0000 Cleared by software TSR8 Figure 10.17 One-Shot Pulse Output Operation 10.3.6 Offset One-Shot Pulse Function and Output Cutoff Function By making an appropriate setting in the timer connection register (TCNR), down-counting by channel 8 down-counters (DCNT8A to DCNT8P) can be started using compare-match signals from channel 1 general registers (GR1A to GR1H) or channel 1 and 2 compare-match registers (OCR1, OCR2A to OCR2H). DCNT8A to DCNT8H are connected to channel 1 OCR1 or GR1A to GR1H, and DCNT8I to DCNT8P are connected to channel 2 OCR2A to OCR2H or GR2A to GR2H. This enables one-shot pulse output from the external pin (TO8A to TO8P) corresponding to DCNT. The down-count can be forcibly stopped by making a setting in the one-shot pulse terminate register (OTR). On channel 1, down-count start or termination by a GR or OCR compare-match can be selected with the trigger mode register (TRGMDR). Making a setting in the timer start register (TSTR) starts an up-count by a free-running counter (TCNT) in channel 1 or 2. When TCNT matches GR or OCR while connection is enabled by TCNR, the corresponding DSTR is automatically set and DCNT starts counting down. At the same time, 1 is output from the corresponding external pin (TO8A to TO8P). By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. When TCNT1 matches GR or OCR, or TCNT2 matches GR, while channel 8 one-shot pulse termination by a channel 1 or 2 compare-match signal is enabled by OTR, the corresponding DSTR is automatically cleared and DCNT stops counting down. DCNT is cleared to H'0000 at this time, and must be rewritten before the down-count is restarted. DCNT8I to DCNT8P are connected to the reload register (RLDR8), and when the DSTR corresponding to DCNT8I to DCNT8P is set, the DCNT8I to DCNT8P counter loads RLDR8 before starting the down-count. 344 An example of the offset one-shot pulse output function and output cutoff function is shown in figure 10.18. In the example shown in this figure, DCNT8I is started by OCR2A of channel 2, and DCNT8I output is cut off by GR2A. Pφ First prescaler 1 Second prescaler 1 Start trigger (OSTRG1A-P) Terminate trigger (OSTRG0A-P) Down-count start trigger (corresponding bit) Down-counter 10A-10P clock One-shot pulse (TOA10-TOP10) Down-counter 10A-10P Synchronized with down-counter clock 0009 0008 0007 0006 0005 0004 0003 0000 One-shot end detection signal One-shot end interrupt (flag) Figure 10.18 Offset One-Shot Pulse Output Function and Output Cutoff Function Operation 10.3.7 Interval Timer Operation The interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B) are connected to bits 6 to 9 and 10 to 13 of the channel 0 free-running counter (TCNT0). The ITVRR registers are 8-bit registers; the upper 4 bits (ITVA) are used for A/D converter activation, and the lower 4 bits (ITVE) are used for interrupt requests. ITVRR1 is connected to A/D converter 2 (AD2), ITVRR2A to A/D converter 0 (AD0), and ITVRR2B to A/D converter 1 (AD1). When the ITVA bit for the desired timing is set, the A/D converter is activated when the corresponding bit of TCNT0 changes to 1. When the ITVE bit for the desired timing is set, an interrupt can be requested when the corresponding bit of TCNT0 changes to 1. At this time, the corresponding bit of the timer status 345 register (TSR0) is set. There are four interrupt sources for the respective ITVRR registers, but there is only one interrupt vector. To suppress interrupts and A/D converter activation, ITVRR bits should be cleared to 0. An example of interval timer function operation is shown in figure 10.19. In the example in figure 10.19, TCNT0 is started by setting ITVE to 1 in ITVRR1. Pø TCNT0 Clock TCNT0 0000003C 0000003D 0000003E 0000003F 00000040 0000007E 0000007F 00000080 Internal detection signal In case of bit 6 detection 00000081 00000082 00000083 00000084 00000085 In case of bit 7 detection AD activation trigger Figure 10.19 Interval Timer Function 10.3.8 Twin-Capture Function Channel 0 input capture register ICR0A, channel 1 offset base register 1 (OSBR1), and channel 2 offset base register 2 (OSBR2) can be made to perform input capture in response to the same trigger by means of a setting in timer I/O control register 0 (TIOR0). When TCNT0, TCNT1A, and TCNT2A in channel 0, channel 1, and channel 2 are started by a setting in the timer status register (TSR), and an edge is input to ICR0A, the TCNT1A value is transferred to OSBR1, and the TCNT2A value to OSBR2. Edge detection is as described in section 10.3.4, Input Capture Function. An example of twin-capture operation is shown in figure 10.20. 346 Pø TCNT1A Clock TCNT1A 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E Edge detection signal (from channel 0) 0003 OSBR1 567A Figure 10.20 Twin-Capture Operation 10.3.9 PWM Timer Function Channels 6 and 7 can be used unconditionally as PWM timers using external pins (TO6A to TO6D, TO7A to TO7D). In channels 6 and 7, when the corresponding bit is set in the timer start register (TSTR) and the free-running counter (TCNT) is started, the counter counts up until its value matches the corresponding cycle register (CYLR). When TCNT matches CYLR, it is cleared to H'0001 and starts counting up again from that value. At this time, 1 is output from the corresponding external pin. An interrupt request can be sent to the CPU by setting the corresponding bit in the timer interrupt enable register (TIER). If a value has been set in the duty register (DTR), when TCNT matches DTR, 0 is output to the corresponding external pin. If the DTR value is H'0000, the output does not change (0% duty). A duty of 100% is specified by setting DTR = CYLR. Do not set a value in DTR that will result in the condition DTR > CYLR. Channels 6 and 7 have buffers (BFR); the BFR value is transferred to DTR when TCNT matches CYLR. The duty value written into BFR is reflected in the output value in the cycle following that in which BFR is written to. An example of PWM timer operation is shown in figure 10.21. In the example in figure 10.21, H'0004 is set in channel 6 CYLR6A, and H'0002, H'0000 (0%), H'0004 (100%), and H'0001 in BFR6A. 347 Pø TST6A TCNT6A Clock TCNT6A 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 CYLR6A Data = 0000 Data = 0004 Data = 0001 Write to BFR6A BFR6A 0002 0002 DTR6A TO6A No PWM output for 1 cycle after activation 0004 0000 Cleared by software 0001 0000 0004 Cleared by software 0001 Cleared by software TSR6 Cycle Cycle Cycle Duty = 0% Cycle Duty = 100% Cycle Figure 10.21 PWM Timer Operation Channel 6 can be used in complementary PWM mode by making a setting in the PWM mode control register (PMDR). On-duty or off-duty can also be selected with a setting in PMDR. When TCNT6 is started by a setting in TSTR, it starts counting up. When TCNT6 reaches the CYLR6 value, it starts counting down, and on reaching H'000, starts counting up again. The counter status is shown by TSR6. When TCNT6 underflows, an interrupt request can be sent to the CPU by setting the corresponding bit in TIER. When TCNT6 matches the duty register (DTR6) value, the output is inverted. The output prior to the match depends on the PMDR setting. When a value including dead time is set in DTR6, a maximum of 4-phase PWM output is possible. Data transfer from BFR6 to DTR6 is performed when TCNT6 underflows. An example of channel 6 complementary PWM mode operation is shown in figure 10.22. In the example in figure 10.22, H'0004 is set in channel 6 CYLR6A, and H'0002, H'0003, H'0004 (100%), and H'0000 (0%) in BFR6A. 348 Pø TST6A TCNT6A Clock TCNT6A 00 01 TCNT6A up-/downcount 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 Up Up Up Down Up Down CYLR6A Up Down Down Down 0004 Data = 0003 Data = 0004 Data = 0000 Write to BFR6A BFR6A 0002 0003 DTR6A TO6A 0002 0004 0003 0000 0004 0000 No PWM output for 1 cycle after activation Cleared by software Cleared by software Cleared by software TSR6 Cycle Cycle Cycle Cycle Duty = 100% Cycle Duty = 0% Figure 10.22 Complementary PWM Mode Operation 10.3.10 Channel 3 to 5 PWM Function PWM mode is selected for channels 3 to 5 by setting the corresponding bits to 1 in the timer mode register (TMDR), enabling the channels to operate as PWM timers with the same cycle. In PWM mode, general registers D (GR3D, GR4D, GR5D) are used as cycle registers, and general registers A to C (GR3A to GR3C, GR4A to GR4C, GR5A to GR5C) as duty registers. The external pins (TIO3A to TIO3C, TIO4A to TIO4C, TIO5A to TIO5C) corresponding to the GRs used as duty registers are used as PWM outputs. External pins TIO3D, TIO4D, and TIO5D should not be used as timer outputs. The free-running counter (TCNT) is started by making a setting in the timer start register (TSTR), and when TCNT reaches the cycle register (GR3D, GR4D, GR5D) value, a compare-match is generated and TCNT starts counting up again from H'0000. At the same time, the corresponding bit is set in the timer status register (TSR) and 1 is output from the corresponding external pin. When TCNT reaches the duty register (GR3A to GR3C, GR4A to GR4C, GR5A to GR5C) value, 0 is output to the external pin. The corresponding status flag is not set. When PWM operation is performed by starting the free-running counter from its initial value of H'0000, PWM output is not performed for one cycle. To perform immediate PWM output, the value in the cycle register must be set in the free-running counter before the counter is started. If PWM operation is performed 349 after setting H'FFFF in the cycle register, the cycle register’s compare-match flag and overflow flag will be set simultaneously. Note that 0% or 100% duty output is not possible in channel 3 to 5 PWM mode. An example of channel 3 to 5 PWM mode operation is shown in figure 10.23. In the example in figure 10.23, H'F0008 is set in GR3D, H'0002 is set in GR3A, GR3B, and GR3C, and channel 3 is activated; then, during operation, H'0000 is set in GR3A, GR3B, and GR3C, and output is performed to external pins TIOA3 to TIOC3. Note that 0% duty output is not possible even though H'0000 is set. Pø TCNT3 Clock TCNT3 GR3D 0008 0000 0001 0002 0003 0007 0008 0008 0000 0001 0002 0003 0004 0005 0008 Rewritten by software GR3A–3C (pulse width) 0002 0000 TIO3A– TIO3C Cleared by software Cleared by software TSR3 Figure 10.23 Channel 3 to 5 PWM Mode Operation 10.3.11 Event Count Function and Event Cycle Measurement Channel 9 has six 8-bit event counters (ECNT9A to ECNT9F) and corresponding general registers (GR9A to GR9F). Each event counter has an external pin (TI9A to TI9F). Each ECNT9 operates unconditionally as an event counter. When an edge is input from the external pin, ECNT9 is incremented. When ECNT9 matches the value set in GR9, it is cleared, and then counts up when an edge is again input at the external pin. By making the appropriate setting in the interrupt enable register (TIER) beforehand, an interrupt request can be sent to the CPU on compare-match. For ECNT9A to ECNT9D, a trigger can be transmitted to channel 3 when a compare-match occurs. In channel 3, if the channel 9 trigger input is set in the timer I/O control register (TIOR) and the corresponding bit is set to 1 in the timer start register (TSTR), the TCNT3 value is captured in the corresponding general register (GR3A to GR3D) when an ECNT9A to ECNT9D compare-match occurs. This enables the event cycle to be measured. 350 An example of event count operation is shown in figure 10.24. In this example, ECNT9A counts up on both-edge, falling-edge, and rising-edge detection, H'10 is set in GR9A, and a comparematch is generated. An example of event cycle measurement operation is shown in figure 10.24. In this example, GR3A in channel 3 captures TCNT3 in response to a trigger from channel 9. Pø TI9A Edge detection signal ECNT9A Clock ECNT9A 00 01 02 03 10 GR9A 00 05 06 10 Cleared by software TSR9 CMF9A Capture trigger To channel 3 Falling edge Rising and falling edges Rising edge Figure 10.24 Event Count Operation Pø TCNT3 Clock TCNT3 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E Compare-match trigger (from channel 9) GR3A TSR3 IMF3A 0003 567A Cleared by software Figure 10.25 Event Cycle Measurement Operation 351 10.3.12 Channel 10 Functions Inter-Edge Measurement Function and Edge Input Cessation Detection Function:32-bit input capture register 10A (ICR10A) and 32-bit output compare register 10A (OCR10A) in channel 10 unconditionally perform input capture and compare-match operations, respectively. These registers are connected to 32-bit free-running counter TCNT10A. When the corresponding bit is set in the timer start register (TSTR), the entire channel 10 starts operating. ICR10A has an external input pin (TI10), and when an edge is input at this input pin, ICR10A captures the TCNT10A value. At this time, TCNT10A is cleared to H'00000001. The captured value is transferred to the read register (RLD10C) in the multiplied clock generation block. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. This allows inter-edge measurement to be carried out. When TCNT10A reaches the value set in OCR10A, a compare-match interrupt can be requested. In this way it is possible to detect the cessation of edge input beyond the time set in OCR10A. The input edge from TI10 is synchronized internally; the internal signal is AGCK. Noise cancellation is possible for edges input at TI10 using the timer 10H (TCNT10H) input cancellation function by setting the NCE bit in timer control register TCR10. When an edge is input at TI10, TCNT10H starts and input is disabled until it reaches compare-match register NCR10. Edge input operation without noise cancellation is shown in figure 10.26, edge input operation with noise cancellation in figure 10.27, and TCNT10A capture operation and compare-match operation in figure 10.28. Pø TI10 After internal synchronization 1 After internal synchronization 2 AGCK AGCK operation TCNT clock When rising edge is set When falling edge is set When rising and falling edges are set Figure 10.26 Edge Input Operation (Without Noise Cancellation) 352 Pø TI10 AGCK Noise cancellation period External edge mask period External edge mask period Pφ × 10 (clock) 0 TCNT10H 1 NCR10 0 1 AGCK operation TCNT clock Note: When rising and falling edges are set Figure 10.27 Edge Input Operation (With Noise Cancellation) Pø TSTR TST10 TCNT10A Clock 00000001 00000002 00000003 12345677 1234 5678 00000000 55555555 55555556 55555557 AGCK Capture transfer signal TCNT reset signal ICR10A TSR10 IMF10A OCR10A TSR10 CMF10A 00000000 12345678 Cleared by software 55555556 Cleared by software Figure 10.28 TCNT10A Capture Operation and Compare-Match Operation Internally synchronized AGCK is counted by event count 10B (TCNT10B), and when TCNT10B reaches the value set beforehand in compare-match register 10B (OCR10B), a compare-match occurs, and the compare-match trigger signal is transmitted to channel 0. By setting the corresponding bit in TIER, an interrupt request can be sent to the CPU. 353 Figure 10.29 shows TCNT10B compare-match operation. Pø AGCK TCNT10B Clock TCNT10B 00 01 55 56 OCR10B 55 TSR10 CMF10B Cleared by software Channel 0 trigger Figure 10.29 TCNT10B Compare-Match Operation Multiplied Clock Generation Function: The channel 10 16-bit reload counter (TCNT10C, RLD10C) and 16-bit free-running counter 10G (TCNT10G) can be used to multiply the interval between edges input from external pin TI10 by 32, 64, 128, or 256. The value captured in ICR10A above is multiplied by 1/32, 1/64, 1/128, or 1/256 according to the value set in the timer I/O control register (TIOR10), and transferred to the reload buffer (RLD10C). At the same time, the same value is transferred to 16-bit reload counter 10C (TCNT10C) and a down-count operation is started. When this counter reaches H'0001, the value is read automatically from RLD10C and the down-count operation is repeated. When this reload occurs, a multiplied clock signal (AGCK1) is generated. AGCK1 is converted to a corrected clock (AGCKM) by the multiplied clock correction function described in the following section. Channel 10 can also perform compare-match operation by means of the multiplied clock (AGCK1) using general register 10G (GR10G) and 16-bit free-running counter 10G (TCNT10G). TCNT10G is incremented unconditionally by AGCK1. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU when TCNT10G and GR10G match. The timing of this interrupt can be selected with the IREG bit in TIER as either on occurrence of the compare-match or on input of the first TI10 edge after the compare-match. TCNT10C operation is shown in figure 10.30, and TCNT10G compare-match operation in figure 10.31. 354 Pø TST10 AGCK ICR10A 00000000 00000020 1ck 1ck Shifter output 0000 0001 Initial value set by software 0002 RLD10C RLD10C write enable signal TCNT10C 0001 Not loaded when RLDEN = 1 0002 0001 0001 0002 0001 0002 0001 0001 0001 0001 RLD10C load signal AGCK1 RLDEN RLDEN set to 0 by software RLDEN set to 1 by software Note: In case of multiplication factor of 32 Figure 10.30 TCNT10C Operation Pø AGCK AGCK1 Cleared by AGCK Write by software TCNT10G GR10G 0000 0001 0002 0034 0036 0000 0001 0034 When IREG = 1 TSR10 CMF10G TSR10 CMF10G 0035 When IREG = 0 Figure 10.31 TCNT10G Compare-Match Operation 355 Multiplied Clock Correction Function: Channel 10’s three 16-bit correction counters (TCNT10D, TCNT10E, TCNT10F) and correction counter clear register (TCCLR10) have a correction function that makes the interval between edges input from TI10 the frequency multiplication value set in TIOR10. When AGCK is input, the value in TCNT10D multiplied by the multiplication factor set in TIOR10 is transferred to TCNT10E. At the same time, TCNT10D is incremented. TCNT10E counts up on AGCK1. TCNT10E loads TCNT10D on AGCK, and counts up again on AGCK1. Using the counter correction select bit (CCS) in TIOR10, it is possible to select whether or not TCNT10E is halted when TCNT10D = TCNT10E. TCNT10F has the peripheral clock (Pφ) as its input and is constantly compared with TCNT10E. When the TCNT10F value is smaller than that in TCNT10E, TCNT10F is incremented and outputs a corrected multiplied clock signal (AGCKM). When the TCNT10E value exceeds the TCNT10F value (when TCNT10E loads TCNT10D), no count-up operation is performed. AGCKM is output to the channel 1 to 5 free-running counters (TCNT1 to TCNT5). Channel 10 also has a correction counter clear register (TCCLR10). The correction counters (TCNT10D, TCNT10E, TCNT10F) and channel 1 and 2 free-running counters (TCNT1 and TCNT2) can be cleared when TCNT10F reaches the value set in TCCLR10. TCNT10D operation is shown in figure 10.32, TCNT10E operation in figure 10.33, TCNT10F operation (at startup) in figure 10.34, TCNT10F operation (end of cycle, with correction) in figure 10.35, and TCNT10F operation (end of cycle, without correction) in figure 10.36. Pø TST10 AGCK TCNT10D Clock TCNT10D Shifter output 00 01 02 03 0000 0020 0040 0060 Note: In case of multiplication factor of 32 Figure 10.32 TCNT10D Operation 356 Pø TST10 AGCK AGCK1 Initial value load TCNT10E valid Corrected value load 0024 00 00 TCNT10E TCNT10D (shift amount) Corrected value load 0001 0002 0003 0000 0004 0022 0023 0020 0021 0038 0022 0020 0039 00 41 0040 0040 00 42 00 43 00 44 0060 Note: In case of multiplication factor of 32 Figure 10.33 TCNT10E Operation Pø TST10 AGCK TCNT10E Clock 0024 0000 TCNT10E TCNT10F 0001 0080 0002 0001 0003 0002 0004 0003 0004 0022 0023 0022 0020 0023 0021 0022 0023 0024 0024 0025 0027 0026 0025 0026 0027 Same value as cycle register set by software AGCKM TCNT clock operating on AGCKM TCNT1, TCNT2 0000 0001 0002 0003 0022 0023 0024 0025 0026 TCNT1, TCNT2 reset trigger TCNT10D 00 01 02 Note: Multiplication factor of 32, TCCLR10 = H'0080 Figure 10.34 TCNT10F Operation (At Startup) 357 Pø TST10 AGCK TCNT10E Clock TCNT10E 005A 0061 0062 0063 0064 0065 0066 0077 0076 0079 0078 007A 00 00 TCNT10F 005A 0001 0002 0003 0080 0060 0063 0064 0065 0066 0076 0077 0078 0079 007A 00 01 0002 0003 AGCKM TCNT clock operating on AGCKM TCNT1, TCNT2 0063 0064 0065 00 66 0076 0077 0078 0079 007A 00 0002 01 0000 0003 TCNT1, TCNT2 reset trigger Cleared to H'00 by software TCNT10D 02 03 00 01 Note: Multiplication factor of 32, TCCLR10 = H'0080 Figure 10.35 TCNT10F Operation (End of Cycle, Acceleration, Deceleration) 358 Pø TST10 AGCK TCNT10E Clock TCNT10E 005A 0061 0062 0063 0064 0065 0066 007F 007E 0080 0081 0082 00 00 0001 0002 0003 0060 TCNT10F 005A 0063 0064 0065 0066 007E 007F 0080 0001 0002 0003 AGCKM TCNT clock operating on AGCKM TCNT1, TCNT2 005A 0063 0064 0065 00 66 007E 007F 0000 0001 0002 TCNT1, TCNT2 reset trigger Set to H'00 by software TCNT10D 02 03 00 01 Note: Multiplication factor of 32, TCCLR10 = H'0080 Figure 10.36 TCNT10F Operation (End of Cycle, Steady-State) 359 10.4 Interrupts The ATU has 75 interrupt sources of five kinds: input capture interrupts, compare-match interrupts, overflow interrupts, underflow interrupts, and interval interrupts. 10.4.1 Status Flag Setting Timing IMF (ICF) Setting Timing in Input Capture: When an input capture signal is generated, the IMF bit and ICF bit are set to 1 in the timer status register (TSR), and the TCNT value is simultaneously transferred to the corresponding GR, ICR and OSBR. The timing in this case is shown in figure 10.37. In the example in figure 10.37, a signal is input from an external pin, and input capture is performed on detection of a rising edge. CK tTICS (input capture input setup time) Input capture input Internal input capture signal TCNT N GR (ICR) Interrupt status flag IMF (ICF) Interrupt request signal IMI (ICI) Figure 10.37 IMF (ICF) Setting Timing in Input Capture 360 N IMF (ICF) Setting Timing in Compare-Match: The IMF bit and CMF bit are set to 1 in the timer status register (TSR) by the compare-match signal generated when the general register (GR) output compare register (OCR), or cycle register (CYLR) value matches the timer counter (TCNT) value. The compare-match signal is generated in the last state of the match (when the matched TCNT count value is updated). The timing in this case is shown in figure 10.38. CK TCNT input clock TCNT GR(CYLR) N N+1 N Compare-match signal Interrupt status flag IMF (CMF) Interrupt request signal IMI (CMI) Figure 10.38 IMF (CMF) Setting Timing in Compare-Match 361 OVF Setting Timing in Overflow: When TCNT overflows (from H'FFFF to H'0000, or from H'FFFFFFFF to H'00000000), the OVF bit is set to 1 in the timer status register (TSR). The timing in this case is shown in figure 10.39. CK TCNT input clock TCNT H'FFFF H'0000 Overflow signal Interrupt status flag OVF Interrupt request signal OVI Figure 10.39 OVF Setting Timing in Overflow 362 OSF Setting Timing in Underflow: When a down-counter (DCNT) counts down from H'0001 to H'0000 on DCNT input clock input, the OSF bit is set to 1 in the timer status register (TSR) when the next DCNT input clock pulse is input (when underflow occurs). However, when DCNT is H'0000, it remains unchanged at H'0000 no matter how many DCNT input clock pulses are input. When DCNT is cleared by means of the one-shot pulse function, the OSF bit is cleared when the next DCNT input clock is input. The timing in this case is shown in figure 10.40. CK DCNT input clock DCNT H'0001 H'0000 H'0000 Underflow signal Interrupt status flag OSF Interrupt request signal OSI Figure 10.40 OSF Setting Timing in Underflow 363 Timing of IIF Setting by Interval Timer: When 1 is generated by ANDing the rise of bit 10 to 13 in free-running counter TCNT0L with bit ITVE0 to ITVE3 in the interval interrupt request register (ITVRR), the IIF bit is set to 1 in the timer status register (TSR). The timing in this case is shown in figure 10.41. TCNT0 value N in the figure is the counter value when TCNT0L bit 6 to 13 changes to 1. (For example, N = H'00000400 in the case of bit 10, H'00000800 in the case of bit 11, etc.) CK TCNT input clock TCNT0 N–1 N Internal interval signal Interrupt status flag IIF Interrupt request signal Figure 10.41 Timing of IIF Setting Timing by Interval Timer 364 10.4.2 Status Flag Clearing Clearing by CPU Program: The interrupt status flag is cleared when the CPU writes 0 to the flag after reading it while set to 1. The procedure and timing in this case are shown in figure 10.42. TSR write cycle T1 T2 Start CK Read 1 from TSR Address Write 0 to TSR Interrupt status flag cleared TSR address Internal write signal Interrupt status flag IMF, ICF, CMF, OVF, OSF, IIF Interrupt request signal Figure 10.42 Procedure and Timing for Clearing by CPU Program 365 Clearing by DMAC: The interrupt status flag (ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D) is cleared automatically during data transfer when the DMAC is activated by input capture or compare-match. The procedure and timing in this case are shown in figure 10.43. CK Start Clear request signal from DMAC Activate DMAC Interrupt status flag cleared during data transfer Interrupt status flag clear signal Interrupt status flag ICF0B, CMF6 Interrupt request signal Figure 10.43 Procedure and Timing for Clearing by DMAC 366 10.5 CPU Interface 10.5.1 Registers Requiring 32-Bit Access Free-running counters 0 and 10A (TCNT0, TCNT10A), input capture registers 0A to 0D and 10A (ICR0A to ICR0D, ICR10A), and output compare register 10A (OCR10A) are 32-bit registers. As these registers are connected to the CPU via an internal 16-bit data bus, a read or write (read only, in the case of ICR0A to ICR0D and ICR10A) is automatically divided into two 16-bit accesses. Figure 10.44 shows a read from TCNT0, and figure 10.45 a write to TCNT0. When reading TCNT0, in the first read the TCNT0H (upper 16-bit) value is output to the internal data bus, and at the same time, the TCNT0L (lower 16-bit) value is output to an internal buffer register. Then, in the second read, the TCNT0L (lower 16-bit) value held in the internal buffer register is output to the internal data bus. When writing to TCNT0, in the first write the upper 16 bits are output to an internal buffer register. Then, in the second write, the lower 16 bits are output to TCNT0L, and at the same time, the upper 16 bits held in the internal buffer register are output to TCNT0H to complete the write. The above method performs simultaneous reading and simultaneous writing of 32-bit data, preventing contention with an up-count. Internal data bus H CPU 1st read operation Module data bus H Bus interface TCNT0H Internal buffer register L TCNT0L Module data bus Internal data bus L CPU 2nd read operation Bus interface Module data bus L Internal buffer register TCNT0H TCNT0L Figure 10.44 Read from TCNT0 367 1st write operation Internal data bus H CPU Bus interface H Internal buffer register Module data bus Internal data bus L CPU TCNT0H TCNT0L Module data bus Internal buffer H register 2nd write operation Bus interface L TCNT0H TCNT0L Module data bus Figure 10.45 Write to TCNT0 368 10.5.2 Registers Permitting 8-Bit, 16-Bit, or 32-Bit Access Timer registers 1, 2, and 3 (TSTR1, TSTR2, TSTR3) are 8-bit registers. As these registers are connected to the CPU via an internal 16-bit data bus, a simultaneous 32-bit read or write access to TSTR1, TSTR2, and TSTR3 is automatically divided into two 16-bit accesses. Figure 10.46 shows a read from TSTR, and figure 10.47 a write to TSTR. When reading TSTR, in the first read the TSTR1 and TSTR2 (upper 16-bit) value is output to the internal data bus. Then, in the second read, the TSTR3 (lower 16-bit) value is output to the internal data bus. When writing to TSTR, in the first write the upper 16 bits are written to TSTR1 and TSTR2. Then, in the second write, the lower 16 bits are written to TSTR3. Note that, with the above method, in a 32-bit write the write timing is not the same for TSTR1/TSTR2 and TSTR3. For information on 8-bit and 16-bit access, see section 10.5.4, 8-Bit or 16-Bit Accessible Registers. Internal data bus H CPU Internal data bus L CPU 1st read operation Module data bus H Bus interface TSTR2 TSTR1 TSTR3 2nd read operation Bus interface Module data bus L TSTR2 TSTR1 TSTR3 Figure 10.46 Read from TSTR1, TSTR2, and TSTR3 369 1st write operation Internal data bus H CPU Bus interface H TSTR2 TSTR1 TSTR3 Module data bus Internal data bus L CPU 2nd write operation Bus interface L TSTR2 TSTR1 TSTR3 Module data bus Figure 10.47 Write to TSTR1, TSTR2 and TSTR3 10.5.3 Registers Requiring 16-Bit Access The free-running counters (TCNT; but excluding TCNT0, TCNT10A, TCNT10B, TCNT10D, and TCNT10H), the general registers (GR; but excluding GR9A to GR9D), down-counters (DCNT), offset base register (OSBR), cycle registers (CYLR), buffer registers (BFR), duty registers (DTR), timer connection register (TCNR), one-shot pulse terminate register (OTR), down-count start register (DSTR), output compare registers (OCR: but excluding OCR10B), reload registers (RLDR8, RLD10C), correction counter clear register (TCCLR10), timer interrupt enable register (TIER), and timer status register (TSR) are 16-bit registers. These registers are connected to the CPU via an internal 16-bit data bus, and can be read or written (read only, in the case of OSBR) a word at a time. Figure 10.48 shows the operation when performing a word read or write access to TCNT1A. Internal data bus CPU Bus interface Module data bus Figure 10.48 TCNT1A Read/Write Operation 370 TCNT1A 10.5.4 8-Bit or 16-Bit Accessible Registers The timer control registers (TCR1A, TCR1B, TCR2A, TCR2B, TCR6A, TCR6B, TCR7A, TCR7B), timer I/O control registers (TIOR1A to TIOR1D, TIOR2A to TIOR2D, TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B), and the timer start register (TSTR1, TSTR2, TSTR3) are 8-bit registers. These registers are connected to the upper 8 bits or lower 8 bits of the internal 16-bit data bus, and can be read or written a byte at a time. In addition, a pair of 8-bit registers for which only the least significant bit of the address is different, such as timer I/O control register 1A (TIOR1A) and timer I/O control register 1B (TIOR1B), can be read or written in combination a word at a time. Figures 10.49 and 10.50 show the operation when performing individual byte read or write accesses to TIOR1A and TIOR1B. Figure 10.51 shows the operation when performing a word read or write access to TIOR1A and TIOR1B simultaneously. Internal data bus CPU Bus interface Only upper 8 bits used Module data bus TIOR1B TIOR1A Only upper 8 bits used Figure 10.49 Byte Read/Write Access to TIOR1B Internal data bus CPU Bus interface Only lower 8 bits used Module data bus TIOR1B TIOR1A Only lower 8 bits used Figure 10.50 Byte Read/Write Access to TIOR1A Internal data bus CPU Bus interface Module data bus TIOR1B TIOR1A Figure 10.51 Word Read/Write Access to TIOR1A and TIOR1B 371 10.5.5 Registers Requiring 8-Bit Access The timer mode register (TMDR), prescaler register (PSCR), timer I/O control registers (TIOR0, TIOR10, TIOR11), trigger mode register (TRGMDR), interval interrupt request register (ITVRR), timer control registers (TCR3, TCR4, TCR5, TCR8, TCR9A to TCR9C, TCR10, TCR11), PWM mode register (PMDR), reload enable register (RLDENR), free-running counters (TCNT10B, TCNT10D, TCNT10H), event counter (ECNT), general registers (GR9A to GR9F), output compare register (OCR10B), and noise canceler register (NCR) are 8-bit registers. These registers are connected to the upper 8 bits of the internal 16-bit data bus, and can be read or written a byte at a time. Figure 10.52 shows the operation when performing individual byte read or write accesses to ITVRR1. Internal data bus CPU Bus interface Only upper 8 bits used Module data bus ITVRR1 Only upper 8 bits used Figure 10.52 Byte Read/Write Access to ITVRR1 10.6 Sample Setup Procedures Sample setup procedures for activating the various ATU-II functions are shown below. Sample Setup Procedure for Input Capture: An example of the setup procedure for input capture is shown in figure 10.53. 1. Select the first-stage counter clock ø' in prescaler register (PSCR) and the second-stage counter clock ø" with the CKSEL bit in the timer control register (TCR). When selecting an external clock, also select the external clock edge type with the CKEG bit in TCR. 2. Set the port control register, corresponding to the port for signal input as the input capture trigger, to ATU input capture input. 3. Select rising edge, falling edge, or both edges as the input capture signal input edge(s) with the timer I/O control register (TIOR). If necessary, a timer interrupt request can be sent to the CPU on input capture by making the appropriate setting in the interrupt enable register (TIER). In channel 0, setting the DMAC allows DMAC activation to be performed. 4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running counter (TCNT) for the relevant channel. Note: When input capture occurs, the counter value is always captured, irrespective of freerunning counter (TCNT) activation. 372 Start Select counter clock 1 Set port-ATU-II connection 2 Set input waveform edge detection 3 Start counter 4 Input capture operation Figure 10.53 Sample Setup Procedure for Input Capture Sample Setup Procedure for Waveform Output by Output Compare-Match: An example of the setup procedure for waveform output by output compare-match is shown in figure 10.54. 1. Select the first-stage counter clock ø' in prescaler register (PSCR), and the second-stage counter clock ø" with the CKSEL bit in the timer control register (TCR). When selecting an external clock, also select the external clock edge type with the CKEG bit in TCR. 2. Set the port control register corresponding to the waveform output port to ATU output compare-match output. Also set the corresponding bit to 1 in the port IO register to specify the output attribute for the port. 3. Select 0, 1, or toggle output for output compare-match output with the timer I/O control register (TIOR). If necessary, a timer interrupt request can be sent to the CPU on output compare-match by making the appropriate setting in the interrupt enable register (TIER). 4. Set the timing for compare-match generation in the ATU general register (GR) corresponding to the port set in 2. 5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running counter (TCNT). Waveform output is performed from the relevant port when the TCNT value and GR value match. 373 Start Select counter clock 1 Set port-ATU-II connection 2 Select waveform output mode 3 Set output timing 4 Start counter 5 Waveform output Figure 10.54 Sample Setup Procedure for Waveform Output by Output Compare-Match 374 Sample Setup Procedure for Channel 0 Input Capture Triggered by Channel 10 CompareMatch: An example of the setup procedure for compare-match transmission is shown in figure 10.55. 1. Set the timing for compare-match generation in the channel 10 output compare register (OCR10B). 2. Set the TRG0DEN bit to 1 in the channel 10 timer control register (TCR10). 3. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 10 freerunning counter (TCNT10B). On compare-match between TCNT10B and OCR10B, the compare-match signal is transmitted to channel 0 as the channel 0 ICR0D input capture signal. Start Set compare-match 1 Set TCR10 2 Start counter 3 Signal transmission Figure 10.55 Sample Setup Procedure for Compare-Match Signal Transmission 375 Sample Setup Procedure for One-Shot pulse Output: An example of the setup procedure for one-shot pulse output is shown in figure 10.56. 1. Set the first-stage counter clock ø' in prescaler register 1 (PSCR1), and select the second-stage counter clock ø" with the CKSEL bit in timer control register8 TCR8. 2. Set port K control registers H and L (PKCRH, PKCRL) corresponding to the waveform output port to ATU one-shot pulse output. Also set the corresponding bit to 1 in the port K IO register (PKIOR) to specify the output attribute. 3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2). If necessary, a timer interrupt request can be sent to the CPU when the down-counter underflows by making the appropriate setting in the interrupt enable register (TIER8). 4. Set the corresponding bit (DST8A to DST8P) to 1 in the down-count start register (DSTR) to start the down-counter (DCNT). Start Select counter clock 1 Set port-ATU-II connection 2 Set pulse width 3 Start down-count 4 One-shot pulse output Figure 10.56 Sample Setup Procedure for One-Shot Pulse Output 376 Sample Setup Procedure for Offset One-Shot Pulse Output/Cutoff Operation: An example of the setup procedure for offset one-shot pulse output is shown in figure 10.57. 1. Set the first-stage counter clock ø' in prescaler register 1 (PSCR1), and select the second-stage counter clock ø" with the CKSEL bit in the timer control register (TCR1, TCR2, TCR8). 2. Set port K control registers H and L (PKCRH, PKCRL) corresponding to the waveform output port to ATU one-shot pulse output. Also set the corresponding bit to 1 in the port K IO register (PKIOR) to specify the output attribute 3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2). If necessary, a timer interrupt request can be sent to the CPU when the down-counter underflows by making the appropriate setting in the interrupt enable register (TIER8). 4. Set the offset width in the channel 1 or 2 general register (GR1A to GR1H, GR2A to GR2H) connected to the down-counter (DCNT) corresponding to the port set in 2, and in the output compare register (OCR1, OCR2A to OCR2H). Set the timer I/O control register (TIOR1A to TIOR1D, TIOR2A to TIOR2D) to the compare-match enabled state. 5. Set the start/terminate trigger by means of the trigger mode register (TRGMDR), timer connection register (TCNR), and one-shot pulse terminate register (OTR), so that it corresponds to the port set in step 2 above. 6. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 1 or 2 freerunning counter (TCNT1, TCNT2). When the TCNT value and GR value or OCR value match, the corresponding DCNT starts counting down or is forcibly cleared, and one-shot pulse output is performed. 377 Start Select counter clock 1 Set port-ATU connection 2 Set pulse width 3 Set offset width 4 Set offset operation 5 Start count 6 Offset one-shot pulse output Figure 10.57 Sample Setup Procedure for Offset One-Shot Pulse Output 378 Sample Setup Procedure for Interval Timer Operation: An example of the setup procedure for interval timer operation is shown in figure 10.58. 1. Set the first-stage counter clock ø' in prescaler register 1 (PSCR1). 2. Set the ITVE bit to be used in the interval interrupt request register (ITVRR) to 1. An interrupt request can be sent to the CPU when the corresponding bit changes to 1 in the channel 0 freerunning counter (TCNT0). To start A/D converter sampling, set the ITVA bit to be used in ITVRR to 1. 3. Set bit 0 to 1 in the timer start register (TSTR) to start TCNT0. Start Select counter clock 1 Set interval 2 Start counter 3 Interrupt request to CPU or start of A/D0 sampling Figure 10.58 Sample Setup Procedure for Interval Timer Operation 379 Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5 ): An example of the setup procedure for PWM timer operation (channels 3 to 5 ) is shown in figure 10.59. 1. Set the first-stage counter clock ø' in prescaler register 1 (PSCR1), and select the second-stage counter clock ø" with the CKSEL bit in the timer control register (TCR). When selecting an external clock, at the same time select the external clock edge type with the CKEG bit in TCR. 2. Set the port control registers (PxCRH, PxCRL) corresponding to the waveform output port to ATU output compare-match output. Also set the corresponding bit to 1 in the port IO register (PxIOR) to specify the output attribute. 3. Set bit T3PWM to T5PWM in the timer mode register (TMDR) to PWM mode. When PWM mode is set, the timer operates in PWM mode irrespective of the timer I/O control register (TIOR) contents, and general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D) can be written to. 4. The GR3A to GR3C, GR4A to GR4C, and GR5A to GR5C ATU general registers are used as duty registers (DTR), and the GR3D, GR4D, and GR5D ATU general registers as cycle registers (CYLR). Set the PWM waveform output 0 output timing in DTR, and the PWM waveform output 1 output timing in CYLR. Also, if necessary, interrupt requests can be sent to the CPU at the 0/1 output timing by making a setting in the timer interrupt enable register (TIER). 5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running counter (TCNT) for the relevant channel. 380 Start Select counter clock 1 Set port-ATU connection 2 Set PWM timer 3 Set GR 4 Start count 5 PWM waveform output Figure 10.59 Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5) 381 Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7): An example of the setup procedure for PWM timer operation (channels 6 and 7) is shown in figure 10.60. 1. Set the first-stage counter clock ø' in prescaler register 2 and 3 (PSCR2, PSCR3), and select the second-stage counter clock ø" with the CKSEL bit in the timer control register (TCR6A, TCR6B, TCR7A, TCR7B). 2. Set the port B control register L (PBCRL) corresponding to the waveform output port to ATU PWM output. Also set the corresponding bit to 1 in the port B IO register (PBIOR) to specify the output attribute. 3. Set PWM waveform output 1 output timing in the cycle register (CYLR6A to CYLR6D, CYLR7A to CYLR7D), and set the PWM waveform output 0 output timing in the buffer register (BFR6A to BFR6D, BFR7A to BFR7D) and duty register (DTR6A to DTR6D, DTR7A to DTR7D). If necessary, an interrupt request can be sent to the CPU on a comparematch between the CYLR value and the free-running counter (TCNT) value by making the appropriate setting in the timer interrupt enable register (TIER). In addition, setting the DMAC allows DMAC activation to be performed. 4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the TCNT counter for the relevant channel. Notes: 1. Do not make a setting in DTR after the counter is started. Use BFR to make a DTR setting. 2. 0% duty is specified by setting H'0000 in the duty register (DTR), and 100% duty is specified by setting buffer register (BFR) = cycle register (CYLR). Do not set BFR > CYLR. 382 Start Select counter clock 1 Set port-ATU connection 2 Set CYLR, BFR, DTR 3 Start count 4 PWM waveform output Figure 10.60 Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7) 383 Sample Setup Procedure for Event Counter Operation: An example of the setup procedure for event counter operation is shown in figure 10.61. 1. Set the number of events to be counted in a general register (GR9A to GR9D). Also, if necessary, an interrupt request can be sent to the CPU upon compare-match by making a setting in the timer interrupt enable register (TIER). 2. Set the port control register, corresponding to the port for signal input to the event counter, to ATU event counter input. 3. Select the event counter count edge with the EGSEL bits in the channel 9 timer control register (TCR9A to TCR9C). 4. Input a signal to the event counter input pin. Start Set number of events 1 Set port-ATU-II connection 2 Select counter clock 3 Start event input 4 Event counter operation Figure 10.61 Sample Setup Procedure for Event Counter Operation 384 Sample Setup Procedure for Channel 3 Input Capture Triggered by Channel 9 CompareMatch: An example of the setup procedure for compare-match signal transmission is shown in figure 10.62. 1. Set the port control register, corresponding to the port for signal input to the event counter, to ATU event counter input. 2. Set the channel 3 timer I/O control register (TIOR3A, TIOR3B), and select the input capture disable setting for the general registers (GR3A to GR3D). Input from pins TIO3A to TIO3D is masked. 3. Select the event counter count edge with the EGSEL bits in the channel 9 timer control register (TCR9A, TCR9B), and set the TRG3xEN bit to 1. Set the timing for capture in the general register (GR9A to GR9D). 4. Set bit STR3 to 1 in the timer start register (TSTR) to start the channel 3 free-running counter (TCNT3). 5. Input a signal to the event counter input pin. Note: An interrupt request can be sent to the CPU upon channel 9 compare-match by making a setting in the timer interrupt enable register (TIER), but an interrupt request cannot be sent to the CPU upon channel 3 input capture. Start Set port-ATU-II connection 1 Set input capture 2 Select compare-match 3 Start counter 4 Start event input 5 Input capture operation Figure 10.62 Sample Setup Procedure for Compare-Match Signal Transmission 385 Sample Setup Procedure for Channel 10 Missing-Teeth Detection: An example of the setup procedure for missing-teeth detection is shown in figure 10.63. 1. Set port B control register H (PBCRH) or port L control register L (PLCRL), corresponding to the port for input of the external signal (missing-teeth signal), to ATU edge input (TI10). 2. Set 1st-stage counter clock ø' in prescaler register 4 (PSCR4). Set the external input (TI10) cycle multiplication factor with the PIM bits in timer I/O control register 10 (TIOR10), and enable reload register 10C (RLD10C) updating with the RLDEN bit. Select the external input edge type with the CKEG bits in timer control register 10 (TCR10). 3. Set general register 10G (GR10G) to the compare-match function with bit IO10G in TIOR10. Also, an interrupt request can be sent to the CPU upon compare-match by making a setting in interrupt enable register 10 (TIER10). 4. Set the timing for compare-match generation in GR10G according to the multiplication factor and number of missing-teeths in the missing-teeth interval set in step 1. 5. Set the corresponding bit to 1 in timer start register 1 (TSTR1) to start the channel 10 count. A compare-match occurs when the values in free-running counter 10G (TCNT10G) and GR10G match. Note: The TCNT10G counter clock is generated according to the external input edge interval and multiplication factor selected in step 1, and the counter is cleared to H'0000 by an external input edge. Start Set port-ATU-II connection 1 Select counter clock 2 Set compare-match 3 Set missing-teeth timing 4 Start counter 5 Interrupt requests to CPU Figure 10.63 Sample Setup Procedure for Missing-Teeth Detection 386 10.7 Usage Notes Note that the kinds of operation and contention described below occur during ATU operation. Contention between TCNT Write and Clearing by Compare-Match: With channel 3 to 7 freerunning counters (TCNT3 to TCNT5, TCNT6A to TCNT6D, TCNT7A to TCNT7D), if a compare-match occurs in the T2 state of a CPU write cycle when counter clearing by comparematch has been set, or when PWM mode is used, the write to TCNT has priority and TCNT clearing is not performed. The compare-match remains valid, and writing of 1 to the interrupt status flag and waveform output to an external destination are performed in the same way as for a normal compare-match. The timing in this case is shown in figure 10.64. T1 T2 Pø Address TCNT address Internal write signal Compare-match signal Counter clear signal TCNT CPU write value Interrupt status flag External output signal (1 output) Figure 10.64 Contention between TCNT Write and Clear 387 Contention between TCNT Write and Increment: If a write to a channel 0 to 11 free-running counter (TCNT0, TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3 to TCNT5, TCNT6A to TCNT6D, TCNT7A to TCNT7D, TCNT10A to TCNT10H, TCNT11), down-counter (DCNT8A to DCNT8P), or event counter 9 (ECNT9A to ECNT9F) is performed while that counter is counting up or down, the write to the counter has priority and the counter is not incremented or decremented. The timing in this case is shown in figure 10.65 In this example, the CPU writes H'5555 at the point at which TCNT is to be incremented from H'1001 to H'1002. T1 T2 Pø TCNT input clock Address TCNT address Internal write signal TCNT 1001 5555 (CPU write value) 5556 Figure 10.65 Contention between TCNT Write and Increment 388 Contention between TCNT Write and Counter Clearing by Overflow: With channel 0 to 5 and 11 free-running counters (TCNT0, TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3 to TCNT5, TCNT11), if overflow occurs in the T2 state of a CPU write cycle, the write to TCNT has priority and TCNT is not cleared. Writing of 1 to the interrupt status flag (OVF) due to the overflow is performed in the same way as for normal overflow. The timing in this case is shown in figure 10.66. In this example, H'5555 is written at the point at which TCNT overflows. T2 T1 Pø TCNT input clock Address TCNT address Internal write signal Overflow signal TCNT FFFF 5555 (CPU write value) 5556 Interrupt status flag (OVF) Figure 10.66 Contention between TCNT Write and Overflow 389 Contention between Interrupt Status Flag Setting by Interrupt Generation and Clearing: If an event such as input capture/compare-match or overflow/underflow occurs in the T2 state of an interrupt status flag 0 write cycle by the CPU, zeroizing by the 0 write has priority and the interrupt status flag is cleared. The timing in this case is shown in figure 10.67. TSR write cycle T2 T1 Pø Address TSR address 0 written to TSR Internal write signal TCNT GR N N+1 N Compare-match signal Interrupt status flag IMF Figure 10.67 Contention between Interrupt Status Flag Setting by Compare-Match and Clearing 390 Contention between DTR Write and BFR Value transfer by Buffer Function: In channels 6 and 7, if there is contention between transfer of the buffer register (BFR) value to the corresponding duty register (DTR) due to a cycle register (CYLR) compare-match, and a write to DTR by the CPU, the CPU write value is written to DTR. Figure 10.68 shows an example in which contention arises when the BFR value is H'AAAA and the value to be written to DTR is H'5555. Pø Address Internal write signal DTR address H'5555 written to DTR Compare-match signal BFR DTR H'AAAA H'5555 Figure 10.68 Contention between DTR Write and BFR Value Transfer by Buffer Function 391 Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input Capture/Compare-Match: If a clear request signal is generated by the DMAC when the interrupt status flag (ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D) is set by input capture (ICR0A to ICR0D) or compare-match (CYLR6A to CYLR6D, CYLR7A to CYLR7D), clearing by the DMAC has priority and the interrupt status flag is not set. The timing in this case is shown in figure 10.69. Pø DMAC clear request signal Interrupt status flag clear signal Input capture/ compare-match signal Interrupt status flag ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D Figure 10.69 Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input Capture/Compare-Match 392 Halting of a Down-Counter by the CPU: A down-counter (DCNT) can be halted by writing H'0000 to it. The CPU cannot write 0 directly to the down-count start register (DSTR); instead, by setting DCNT to H'0000, the corresponding DSTR bit is cleared to 0 and the count is stopped. However, the OSF bit in the timer status register (TSR) is set when DCNT underflows. Note that when H'0000 is written to DCNT, the corresponding DSTR bit is not cleared to 0 immediately; it is cleared to 0, and the down-counter is stopped, when underflow occurs following the H'0000 write. The timing in this case is shown in figure 10.70. Pø DCNT input clock DCNT Internal write signal N H'0000 H'0000 H'0000 written to DCNT DSTR TSR Port output (one-shot pulse) Figure 10.70 Halting of a Down-Counter by the CPU 393 Input Capture Operation when Free-Running Counter is Halted: In channels 0 to 5, channel 10, or channel 11, if input capture setting is performed and a trigger signal is input from the input pin, the TCNT value will be transferred to the corresponding general register (GR) or input capture register (ICR) irrespective of whether the free-running counter (TCNT) is running or halted, and the IMF or ICF bit will be set in the timer status register (TSR). The timing in this case is shown in figure 10.71. Pø Timer status register TSR Internal input capture signal TCNT GR (ICR) N N Interrupt status flag IMF (ICF) Figure 10.71 Input Capture Operation before Free-Running Counter is Started 394 Contention between DCNT Write and Counter Clearing by Underflow: With the channel 8 down-counters (DCNT8A to DCNT8P), if the count is halted due to underflow occurring in the T2 state of a down-counter write cycle by the CPU, retention of the H'0000 value has priority and the write to DCNT by the CPU is not performed. Writing of 1 to the interrupt status flag (OSF) when the underflow occurs is performed in the same way as for normal underflow. The timing in this case is shown in figure 10.72. In this example, a write of H'5555 to DCNT is attempted at the same time as DCNT underflows. T1 T2 Pø DCNT input clock Address DCNT address Write data 5555 Internal write signal Underflow signal H'0000 retained when DCNT halts DCNT 0001 0000 0000 Interrupt status flag (OSF) Figure 10.72 Contention between DCNT Write and Underflow 395 Contention between DSTR Bit Setting by CPU and Clearing by Underflow: If underflow occurs in the T2 state of a down-counter start register (DSTR) “1” write cycle by the CPU, clearing to 0 by the underflow has priority, and the corresponding bit of DSTR is not set to 1. The timing in this case is shown in figure 10.73. STR write cycle T1 T2 Pø Address DSTR address 1 written to DSTR Internal write signal DCNT 0001 0000 0000 Underflow signal Down-count start register Figure 10.73 Contention between DSTR Bit Setting by CPU and Clearing by Underflow 396 Timing of Prescaler Register (PSCR), Timer Control Register (TCR), and Timer Mode Register (TMDR) Setting: Settings in the prescaler register (PSCR), timer control register (TCR), and timer mode register (TMDR) should be made before the counter is started. Operation is not guaranteed if these registers are modified while the counter is running. Also, the counter must not be started until Pø has been input 32 times after setting PSCR1 to PSCR4. Interrupt Status Flag Clearing Procedure: When an interrupt status flag is cleared to 0 by the CPU, it must first be read before 0 is written to it. Correct operation cannot be guaranteed if 0 is written without first reading the flag. Setting H'0000 in Free-Running Counters 6A to 6D, 7A to 7D (TCNT6A to TCNT6D, TCNT7A to TCNT7D): If H'0000 is written to a channel 6 and 7 free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D), and the counter is started, the interval up to the first compare-match with the cycle register (CYLR) and duty register (DTR) will be a maximum of one TCNT input clock cycle longer than the set value. With subsequent compare-matches, the correct waveform will be output for the CYLR and DTR values. Register Values when a Free-Running Counter (TCNT) Halts: If the timer start register (TSTR) value is set to 0 during counter operation, only incrementing of the corresponding freerunning counter (TCNT) is stopped, and neither the free-running counter (TCNT) nor any other ATU registers are initialized. The external output value at the time TSTR is cleared to 0 will continue to be output. TCNT0 Writing and Interval Timer Operation: If the CPU program writes 1 to a bit in freerunning counter 0 (TCNT0) corresponding to a bit set to 1 in the interval interrupt request register (ITVRR) when that TCNT0 bit is 0, TCNT0 bit 6, 7, 8, 9, 10, 11, 12, or 13 will be detected as having changed from 0 to 1, and an interrupt request will be sent to INTC and A/D sampling will be started. While the count is halted with the STR0 bit cleared to 0 in timer start register 1 (TSTR1), the bit transition from 0 to 1 will still be detected. Automatic TSR Clearing by DMAC Activation by the ATU: Automatic clearing of TSR is performed after completion of the transfer when the DMAC is in burst mode, and each time the DMAC returns the bus in cycle steal mode. Interrupt Status Flag Setting/Resetting: With TSR, a 0 write to a bit is possible even if overlapping events occur for the same bit before writing 0 after reading 1 to clear that bit. (The duplicate events are not accepted.) 397 External Output Value in Software Standby Mode: In software standby mode, the ATU register and external output values are cleared to 0. However, while the channel 1, 2, and 11 TIO1A to TIO1H, TIO2A to TIO2H external output values are cleared to 0 immediately after software standby mode is exited, other external output values and all registers are cleared to 0 immediately after a transition to software standby mode. Also, when pin output is inverted by the pin function controller's port B invert register (PBIR) or port K invert register (PKIR), the corresponding pins are cleared to 1. Software standby mode CK TIO1A to 1H, TIO2A to 2H, TIO11A, 11B Other external outputs Figure 10.74 External Output Value Transition Points in Relation to Software Standby Mode Contention between TCNT Clearing from Channel 10 and TCNT Overflow: When a channel 1 or 2 free-running counter (TCNT1A, TCNT1B, TCNT2A, TCNT2B) overflows, it is cleared to H'0000. If a clear signal from the channel 10 correction counter clear register (TCCLR) is input at the same time, a 1 write to the interrupt status flag (OVF) due to the overflow is still performed in the same way as for a normal overflow. Contention between Channel 10 Reload Register Transfer Timing and Write: If there is contention between a multiplied-output transfer from the input capture register (ICR10A) to the channel 10 reload register (RLDR10C), and the timing of a CPU write to that register, the CPU write has priority and the multiplied output is ignored. Contention between Channel 10 Reload Timing and Write to TCNT10C: If there is contention between a multiplied-output transfer from the input capture register (ICR10A) to the channel 10 reload register (RLDR10C), and a CPU write to the reload counter (TCNT10C), the CPU write has priority and the multiplied output is ignored. 398 ATU Pin Setting: When a port is set to the ATU pin function, the following points must be noted. When using a port for input capture input, the corresponding TIOR register must be in the input capture disabled state when the port is set. Regarding channel 10 TI10 input, TCR10 must be in the TI10 input disabled state when the port is set. When using a port for external clock input, the STR bit for the corresponding channel must be in the count operation disabled state when the port is set. When using a port for event input, the corresponding TCR register must be in the count operation disabled state when the port is set. Regarding TCLKB and TI10 input, although input is assigned to a number of pins, when using TCLKB and TI10 input, only one pin should be enabled. Writing to ROM Area Immediately after ATU Register Write: If a write cycle for a ROM address for which address bit 11 = 0 and address bit 12 = 1 (H'00001000 to H'000017FF, H'00003000 to H'000037FF, H'00005000 to H'000057FF, ..., H'0007F000 to H'0007F7FF, ..., H'000FF000 to H'000FF7FF) occurs immediately after an ATU register write cycle, the value, or part of the value, written to ROM will be written to the ATU register. The following measures should be taken to prevent this. • Do not perform a CPU write to a ROM address immediately after an ATU register write cycle. For example, an instruction arrangement in which an MOV instruction that writes to the ATU is located at an even-word address (4n address), and is immediately followed by an MOV instruction that writes to a ROM area, will meet the bug conditions. • Do not perform an AUD write to any of the above ROM addresses immediately after an ATU register write cycle. For example, in the case of a write to overlap RAM when using the RAM emulation function, the write should be performed to the on-chip RAM area address, not the overlapping ROM area address. • Do not perform a DMAC write to an ATU register when a ROM address write operation occurs. 399 10.8 ATU-II Registers And Pins Table 10.4 ATU-II Registers and Pins Channel Register Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Name 0 1 2 3 4 5 6 7 8 9 10 Channel 11 TSTR (3) TSTR1 TSTR1 TSTR1 TSTR3 TSTR1 PSCR (4) PSCR1 PSCR1 PSCR1 PSCR1 PSCR1 PSCR1 PSCR2 PSCR3 PSCR1 — PSCR4 PSCR1 TSTR1 TSTR1 TSTR1 TSTR2 TSTR2 — — TCNT (25) TCNT0H, TCNT1A, TCNT2A, TCNT3 TCNT4 TCNT0L TCNT1B TCNT2B TCNT5 TCNT6A TCNT7A — to to TCNT6D TCNT7D — DCNT (16) — — — — — — — — DCNT8A — to DCNT8P ECNT (6) — — — — — — — — — TCR (17) — TCR1A, TCR1B TCR2A, TCR3 TCR2B TCR4 TCR5 TCR6A, TCR7A, TCR8 TCR6B TCR7B TIOR (17) TIOR0 TIOR1A TIOR2A TIOR3A, TIOR4A, TIOR5A, — to to TIOR3B TIOR4B TIOR5B TIOR1D TIOR2D — TSR (12) TSR0 TSR1A, TSR1B TSR2A, TSR3 TSR2B TSR6 TIER (12) TIER0 TIER1A, TIER2A, TIER3 TIER1B TIER2B TCNT10AH, TCNT11 TCNT10AL, TCNT10B to TCNT10B — — ECNT9A — to ECNT9F — TCR9A TCR10 to TCR9C TCR11 — — TIOR10 TIOR11 TSR7 TSR8 TSR9 TSR10 TSR11 TIER6 TIER7 TIER8 TIER9 TIER10 TIER11 — — — — — — GR1A to GR2A to GR3A to GR4A to GR5A to — GR1H GR2H GR3D GR4D GR5D — — GR9A to GR10G GR9F GR11A, GR11B — ITVRR (3) ITVRR1, — ITVRR2A, ITVRR2B GR (37) — ICR (5) ICR0AH, — ICR0AL to ICR0DH, ICR0DL — — — — — — — — — — — — ICR10AH, ICR10AL OCR (11) — OCR1 OCR2A — to OCR2H — — — — — — OCR10AH, — OCR10AL, OCR10B OSBR (2) — OSBR1 OSBR2 — — — — — — — — — TRGMDR — (1) TRGMDR — — — — — — — — — — TMDR (1) — — TMDR TMDR TMDR — — — — — — 400 — Table 10.4 ATU-II Registers and Pins (cont) Channel Register Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Name 0 1 2 3 4 5 6 7 8 9 10 Channel 11 CYLR (8) — — — — — — CYLR6A CYLR7A — to to CYLR6D CYLR7D — — — BFR (8) — — — — — — BFR6A to BFR6D BFR7A — to BFR7D — — — DTR (8) — — — — — — DTR6A to DTR7A DTR7A — to DTR7D — — — PMDR (1) — — — — — — PMDR — — — — — PLDR (1) — — — — — — — — RLDR8 — — — TCNR (1) — — — — — — — — TCNR — — — OTR (1) — — — — — — — — OTR — — — DSTR (1) — — — — — — — — DSTR — — — RLDENR — (1) — — — — — — — RLDENR — — — RLD (1) — — — — — — — — — — RLD10C — NCR (1) — — — — — — — — — — NCR10 — TCCLR (1) — — — — — — — — — — TCCLR10 — Pins * TIO1A to D, TCLKA, TCLKB TIO2A to H, TCLKA, TCLKB TIO3A to D, TCLKA, TCLKB TIO4A to D, TCLKA, TCLKB TIO5A TO6A to D, to D TCLKA, TCLKB TO7A to D TO8A to P TI9A to F T10 TCLKA, TCLKB TI0A to D Note: * Pin functions should be set as described in section 20, Pin Function Controller (PFC). 401 402 Section 11 Advanced Pulse Controller (APC) 11.1 Overview The SH7052F/SH7053F/SH7054F has an on-chip advanced pulse controller (APC) that can generate a maximum of eight pulse outputs, using the advanced timer unit II (ATU-II) as the time base. 11.1.1 Features The features of the APC are summarized below. • Maximum eight pulse outputs The pulse output pins can be selected from among eight pins. Multiple settings are possible. • Output trigger provided by advanced timer unit II (ATU-II) channel 2 Pulse 0 output and 1 output is performed using the compare-match signal generated by the ATU-II channel II compare-match register as the trigger. 403 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the advanced pulse controller. ATU-II Internal/external clock TCNT11 GR11A Compare GR11B Comparematch signal Comparematch signal Set Bit 7 Reset Bit 15 PULS7 Set POPCR (pulse output port setting register) Bit 6 Reset Bit 14 PULS6 Set Bit 5 Reset Bit 13 PULS5 Set Bit 4 Reset Bit 12 PULS4 Set Bit 3 Reset Bit 11 PULS3 Set Bit 2 Reset Bit 10 PULS2 Set Bit 1 Reset Bit 9 PULS1 Set Bit 0 Reset Bit 8 APC POPCR: Pulse output port control register Figure 11.1 Advanced Pulse Controller Block Diagram 404 PULS0 11.1.3 Pin Configuration Table 11.1 summarizes the advanced pulse controller’s output pins. Table 11.1 Advanced Pulse Controller Pins Pin Name I/O Function PULS0 Output APC pulse output 0 PULS1 Output APC pulse output 1 PULS2 Output APC pulse output 2 PULS3 Output APC pulse output 3 PULS4 Output APC pulse output 4 PULS5 Output APC pulse output 5 PULS6 Output APC pulse output 6 PULS7 Output APC pulse output 7 11.1.4 Register Configuration Table 11.2 summarizes the advanced pulse controller’s register. Table 11.2 Advanced Pulse Controller Register Name Abbreviation R/W Initial Value Address Access Size Pulse output port control register POPCR R/W H'0000 H'FFFFF700 8, 16 Note: Register access requires 4 or 5 cycles. 405 11.2 Register Descriptions 11.2.1 Pulse Output Port Control Register (POPCR) The pulse output port control register (POPCR) is a 16-bit readable/writable register. POPCR is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PULS7 ROE PULS6 ROE PULS5 ROE PULS4 ROE PULS3 ROE PULS2 ROE PULS1 ROE PULS0 ROE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PULS7 SOE PULS6 SOE PULS5 SOE PULS4 SOE PULS3 SOE PULS2 SOE PULS1 SOE PULS0 SOE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 to 8—PULS7 to PULS0 Reset Output Enable (PULS7ROE to PULS0ROE): These bits enable or disable 0 output to the APC pulse output pins (PULS7 to PULS0) bit by bit. Bits 15 to 8: PULS7ROE to PULS0ROE Description 0 0 output to APC pulse output pin (PULS7 to PULS0) is disabled (Initial value) 1 0 output to APC pulse output pin (PULS7 to PULS0) is enabled When one of these bits is set to 1, 0 is output from the corresponding pin on a compare-match between the GR11B and TCNT11 values. 406 • Bits 7 to 0—PULS7 to PULS0 Set Output Enable (PULS7SOE to PULS0SOE): These bits enable or disable 1 output to the APC pulse output pins (PULS7 to PULS0) bit by bit. Bits 7 to 0: PULS7SOE to PULS0SOE Description 0 1 output to APC pulse output pin (PULS7 to PULS0) is disabled (Initial value) 1 1 output to APC pulse output pin (PULS7 to PULS0) is enabled When one of these bits is set to 1, 1 is output from the corresponding pin on a compare-match between the GR11A and TCNT11 values. 11.3 Operation 11.3.1 Overview APC pulse output is enabled by designating multiplex pins for APC pulse output with the pin function controller (PFC), and setting the corresponding bits to 1 in the pulse output port control register (POPCR). When general register 11A (GR11A) in the advanced timer unit II (ATU-II) subsequently generates a compare-match signal, 1 is output from the pins set to 1 by bits 7 to 0 in POPCR. When general register 11B (GR11B) generates a compare-match signal, 0 is output from the pins set to 1 by bits 15 to 8 in POPCR. 0 is output from the output-enabled state until the first compare-match occurs. The advanced pulse controller output operation is shown in figure 11.2. 407 CR Upper 8 bits of POPCR Compare-match signal GR11B Reset signal Port function selection APC output pins (PULS0 to PULS7) Set signal Compare-match signal GRIIA Lower 8 bits of POPCR Figure 11.2 Advanced Pulse Controller Output Operation 11.3.2 Advanced Pulse Controller Output Operation Example of Setting Procedure for Advanced Pulse Controller Output Operation: Figure 11.3 shows an example of the setting procedure for advanced pulse controller output operation. 1. Set general registers GR11A and GR11B as output compare registers with the timer I/O control register (TIOR). 2. Set the pulse rise point with GR11A and the pulse fall point with GR11B. 3. Select the timer counter 11 (TCNT11) counter clock with the timer prescale register (PSCR). TCNT11 can only be cleared by an overflow. 4. Enable the respective interrupts with the timer interrupt enable register (TIER). 5. Set the pins for 1 output and 0 output with POPCR. 6. Set the control register for the port to be used by the APC to the APC output pin function. 7. Set the STR bit to 1 in the timer start register (TSTR) to start timer counter 11 (TCNT11). 8. Each time a compare-match interrupt is generated, update the GR value and set the next pulse output time. 9. Each time a compare-match interrupt is generated, update the POPCR value and set the next pin for pulse output. 408 APC output operation GR function selection 1 GR setting 2 Count operation setting 3 Interrupt request setting 4 APC setting Rise/fall port setting 5 Port setting Port output setting 6 Start count 7 ATU-II settings ATU-II setting Compare-match? No Yes ATU-II setting APC setting GR setting 8 Rise/fall port setting 9 Figure 11.3 Example of Setting Procedure for Advanced Pulse Controller Output Operation 409 Example of Advanced Pulse Controller Output Operation: Figure 11.4 shows an example of advanced pulse controller output operation. 1. Set ATU-11 registers GR11A and GR11B (to be used for output trigger generation) as output compare registers. Set the rise point in GR11A and the fall point in GR11B, and enable the respective compare-match interrupts. 2. Write H'0101 to POPCR. 3. Start the ATU timer 2 count. When a GR11A compare-match occurs, 1 is output from the PULS0 pin. When a GR11B compare-match occurs, 0 is output from the PULS0 pin. 4. Pulse output widths and output pins can be continually changed by successively rewriting GR11A, GR11B, and POPCR in response to compare-match interrupts. 5. By setting POPCR to a value such as H'E0E0, pulses can be output from up to 8 pins in response to a single compare-match. Cleared on overflow TCNT value Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten GR11B GR11A H'0000 POPCR 0101 0202 0404 0808 1010 E0E0 PULS0 PULS1 PULS2 PULS3 PULS4 PULS5 PULS6 PULS7 Figure 11.4 Example of Advanced Pulse Controller Output Operation 410 11.4 Usage Notes Contention between Compare-Match Signals: If the same value is set for both GR11A and GR11B, and 0 output and 1 output are both enabled for the same pin by the POPCR settings, 0 output has priority on pins PULS0 to PULS7 when compare-matches occur. TCNT value H'FFFF H'8000 GR11A H'8000 GR11B H'8000 POPCR H'0101 PULS0 pin Pin output is 0 Figure 11.5 Example of Compare-Match Contention 411 412 Section 12 Watchdog Timer (WDT) 12.1 Overview The watchdog timer (WDT) is a 1-channel timer for monitoring system operations. If a system encounters a problem (crashes, for example) and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT can simultaneously generate an internal reset signal for the entire chip. When the watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow. The WDT is also used in recovering from standby mode. 12.1.1 Features The WDT has the following features: • Works in watchdog timer mode or interval timer mode • Outputs WDTOVF in watchdog timer mode When the counter overflows in watchdog timer mode, overflow signal WDTOVF is output externally. It is possible to select whether to reset the chip internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset signal. • Generates interrupts in interval timer mode When the counter overflows, it generates an interval timer interrupt. • Clears software standby mode • Works with eight counter input clocks 413 12.1.2 Block Diagram Figure 12.1 is the block diagram of the WDT. Overflow Interrupt control Clock WDTOVF Clock select Reset control Internal reset signal* RSTCSR TCNT φ/2 φ/64 φ/128 φ/256 φ/512 φ/1024 φ/4096 φ/8192 Internal clock sources TCSR Bus interface Module bus Internal data bus ITI (interrupt signal) WDT TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Note: * The internal reset signal can be generated by making a register setting. Figure 12.1 WDT Block Diagram 12.1.3 Pin Configuration Table 12.1 shows the pin configuration. Table 12.1 Pin Configuration Pin Abbreviation I/O Function Watchdog timer overflow WDTOVF O Outputs the counter overflow signal in watchdog timer mode 414 12.1.4 Register Configuration Table 12.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 12.2 WDT Registers Address Initial Value Write* Read* 2 R/(W)*3 H'18 H'FFFFEC10 H'FFFFEC10 R/W H'00 Name Abbreviation R/W Timer control/status register TCSR Timer counter TCNT Reset control/status register Notes: 1. 2. 3. 4. RSTCSR R/(W)* 3 1 H'FFFFEC11 H'1F H'FFFFEC12 H'FFFFEC13 Write by word transfer. These registers cannot be written in byte or longword. Read by byte transfer. These registers cannot be read in word or longword. Only 0 can be written to bit 7 to clear the flag. In register access, three cycles are required for both byte access and word access. 12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable upcounter. (TCNT differs from other registers in that it is more difficult to write to. See section 12.2.4, Register Access, for details.) When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows (changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of TCSR. TCNT is initialized to H'00 by a power-on reset, in hardware and software standby modes, and when the TME bit is cleared to 0. Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: 415 12.2.2 Timer Control/Status Register (TCSR) The timer control/status register (TCSR) is an 8-bit readable/writable register. (TCSR differs from other registers in that it is more difficult to write to. See section 12.2.4, Register Access, for details.) TCSR performs selection of the timer counter (TCNT) input clock and mode. Bits 7 to 5 are initialized to 000 by a power-on reset, and in hardware standby mode and software standby mode. Bits 2 to 0 are initialized to 000 by a power-on reset and in hardware standby mode, but retain their values in software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 OVF WT/IT TME — — CKS2 CKS1 CKS0 0 0 0 1 1 0 0 0 R/(W)* R/W R/W R R R/W R/W R/W Note: * The only operation permitted on the OVF bit is a write of 0 after reading 1. • Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00 in interval timer mode. This flag is not set in the watchdog timer mode. Bit 7: OVF Description 0 No overflow of TCNT in interval timer mode (Initial value) [Clearing condition] When 0 is written to OVF after reading OVF 1 TCNT overflow in interval timer mode • Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer. When TCNT overflows, the WDT either generates an interval timer interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected. Bit 6: WT/IT Description 0 Interval timer mode: interval timer interrupt (ITI) request to the CPU when TCNT overflows (Initial value) 1 Watchdog timer mode: WDTOVF signal output externally when TCNT overflows. (Section 12.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in watchdog timer mode.) 416 • Bit 5—Timer Enable (TME): Enables or disables the timer. Bit 5: TME Description 0 Timer disabled: TCNT is initialized to H'00 and count-up stops (Initial value) 1 Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. • Bits 4 and 3—Reserved: These bits always read 1. The write value should always be 1. • Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources for input to TCNT. The clock signals are obtained by dividing the frequency of the system clock (φ). Description Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source Overflow Interval* φ = 40 MHz) (φ 0 0 0 φ/2 12.8 µs 0 0 1 φ/64 409.6 µs 0 1 0 φ/128 0.8 ms 0 1 1 φ/256 1.6 ms 1 0 0 φ/512 3.3 ms 1 0 1 φ/1024 6.6 ms 1 1 0 φ/4096 26.2 ms 1 1 1 φ/8192 52.4 ms (Initial value) Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. 417 12.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable/writable register. (RSTCSR differs from other registers in that it is more difficult to write. See section 12.2.4, Register Access, for details.) It controls output of the internal reset signal generated by timer counter (TCNT) overflow. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by overflow of the WDT. It is initialized to H'1F in hardware standby mode and software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 WOVF RSTE RSTS — — — — — 0 0 0 1 1 1 1 1 R/(W)* R/W R/W R R R R R Note: Only 0 can be written to bit 7 to clear the flag. • Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed (H'FF to H'00) in watchdog timer mode. This flag is not set in interval timer mode. Bit 7: WOVF Description 0 No TCNT overflow in watchdog timer mode (Initial value) [Clearing condition] When 0 is written to WOVF after reading WOVF 1 Set by TCNT overflow in watchdog timer mode • Bit 6—Reset Enable (RSTE): Selects whether to reset the chip internally if TCNT overflows in watchdog timer mode. Bit 6: RSTE Description 0 Not reset when TCNT overflows (Initial value) LSI not reset internally, but TCNT and TCSR reset within WDT. 1 Reset when TCNT overflows • Bit 5—Reset Select (RSTS): Selects the kind of internal reset to be generated when TCNT overflows in watchdog timer mode. Bit 5: RSTS Description 0 Power-on reset 1 Manual reset (Initial value) • Bits 4 to 0—Reserved: These bits always read 1. The write value should always be 1. 418 12.2.4 Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in that they are more difficult to write to. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure 12.2). This transfers the write data from the lower byte to TCNT or TCSR. Writing to TCNT 15 Address: H'FFFFEC10 8 7 H'5A 0 Write data Writing to TCSR 15 Address: H'FFFFEC10 8 H'A5 7 0 Write data Figure 12.2 Writing to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFFEC12. It cannot be written by byte transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 12.3. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. 419 Writing 0 to the WOVF bit 15 Address: H'FFFFEC12 8 7 H'A5 0 H'00 Writing to the RSTE and RSTS bits 15 Address: H'FFFFEC12 8 H'5A 7 0 Write data Figure 12.3 Writing to RSTCSR Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFFEC10 for TCSR, H'FFFFEC11 for TCNT, and H'FFFFEC13 for RSTCSR. 12.3 Operation 12.3.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits of TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. No TCNT overflows will occur while the system is operating normally, but if TCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output externally (figure 12.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 128 φ clock cycles. If the RSTE bit in the reset control/status register (RSTCSR) is set to 1, a signal that resets the chip internally will be generated at the same time as the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512 φ clock cycles. When a WDT overflow reset is generated simultaneously with a reset input at the RES pin, the RES reset takes priority, and the WOVF bit in RSTCSR is cleared to 0. The following are not initialized by a WDT reset signal: • PFC (pin function controller) registers • I/O port registers These registers are initialized only by an external power-on reset. 420 TCNT value Overflow H'FF H'00 Time WT/IT = 1 TME = 1 H'00 written in TCNT WOVF = 1 WT/IT = 1 H'00 written in TCNT TME = 1 WDTOVF and internal reset generated WDTOVF signal 128 φ clocks Internal reset signal* 512 φ clocks WT/IT: Timer mode select bit TME: Timer enable bit Note: * Internal reset signal occurs only when the RSTE bit is set to 1. Figure 12.4 Operation in Watchdog Timer Mode 421 12.3.2 Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1 in TCSR. An interval timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 12.5). TCNT value Overflow H'FF Overflow Overflow Overflow H'00 Time WT/IT = 0 TME = 1 ITI ITI ITI ITI ITI: Interval timer interrupt request generation Figure 12.5 Operation in Interval Timer Mode 12.3.3 Clearing Software Standby Mode The watchdog timer has a special function to clear software standby mode with an NMI interrupt. When using software standby mode, set the WDT as described below. Before Transition to Software Standby Mode: The TME bit in TCSR must be cleared to 0 to stop the watchdog timer counter before entering software standby mode. The chip cannot enter software standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 in TCSR so that the counter overflow interval is equal to or longer than the oscillation settling time. See section 24.3, AC Characteristics, for the oscillation settling time. Recovery from Software Standby Mode: When an NMI request signal is received in software standby mode, the clock oscillator starts running and the watchdog timer starts incrementing at the rate selected by bits CKS2 to CKS0 before software standby mode was entered. When TCNT overflows (changes from H'FF to H'00), the clock is presumed to be stable and usable; clock signals are supplied to the entire chip and software standby mode ends. For details on software standby mode, see section 23, Power-Down State. 422 12.3.4 Timing of Setting the Overflow Flag (OVF) In interval timer mode, when TCNT overflows, the OVF flag of TCSR is set to 1 and an interval timer interrupt (ITI) is simultaneously requested (figure 12.6). CK TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 12.6 Timing of Setting OVF 12.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF) When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an internal reset signal to be generated for the entire chip (figure 12.7). CK TCNT H'FF H'00 Overflow signal (internal signal) WOVF Figure 12.7 Timing of Setting WOVF 423 12.4 Usage Notes 12.4.1 TCNT Write and Increment Contention If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer counter is not incremented (figure 12.8). TCNT write cycle T1 T2 T3 CK Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.8 Contention between TCNT Write and Increment 12.4.2 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 12.4.3 Changing between Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. 424 12.4.4 System Reset by WDTOVF Signal If a WDTOVF signal is input to the RES pin, the chip cannot initialize correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 12.9. SH7052F, SH7053F, SH7054F Reset input Reset signal to entire system RES WDTOVF Figure 12.9 Example of System Reset Circuit Using WDTOVF Signal 12.4.5 Internal Reset in Watchdog Timer Mode If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset. 12.4.6 Manual Reset in Watchdog Timer When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits until the end of the bus cycle at the time of manual reset generation before making the transition to manual reset exception processing. Therefore, the bus cycle is retained in a manual reset, but if a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception processing will be deferred until the CPU acquires the bus. However, if the interval from generation of the manual reset until the end of the bus cycle is equal to or longer than the internal manual reset interval of 512 cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception processing is not executed. 425 426 Section 13 Compare Match Timer (CMT) 13.1 Overview The SH7052F/SH7053F/SH7054F has an on-chip compare match timer (CMT) comprising two 16-bit timer channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 13.1.1 Features The CMT has the following features: • Four types of counter input clock can be selected One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) can be selected independently for each channel. • Interrupt sources A compare match interrupt can be requested independently for each channel. 427 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the CMT. CMI1 Pφ/8 Control circuit Module bus Clock selection Bus interface CMT Internal bus CMSTR: CMCSR: CMCOR: CMCNT: CMI: Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match timer counter Compare match interrupt Figure 13.1 CMT Block Diagram 428 Pφ/512 Pφ/128 CMCNT1 Clock selection CMCNT0 Comparator CMCOR0 CMCSR0 CMSTR Control circuit Pφ/128 Comparator Pφ/8 Pφ/32 CMCSR1 CM10 Pφ/512 CMCOR1 Pφ/32 13.1.3 Register Configuration Table 13.1 summarizes the CMT register configuration. Table 13.1 Register Configuration Channel Name Abbreviation R/W Initial Value Address Access Size (Bits) Shared Compare match timer CMSTR start register R/W H'0000 H'FFFFF710 8, 16, 32 0 Compare match timer CMCSR0 control/status register 0 R/(W)*1 H'0000 H'FFFFF712 8, 16, 32 Compare match timer CMCNT0 counter 0 R/W H'0000 H'FFFFF714 8, 16, 32 Compare match timer CMCOR0 constant register 0 R/W H'FFFF H'FFFFF716 8, 16, 32 Compare match timer CMCSR1 control/status register 1 R/(W)*1 H'0000 H'FFFFF718 8, 16, 32 Compare match timer CMCNT1 counter 1 R/W H'0000 H'FFFFF71A 8, 16, 32 Compare match timer CMCOR1 constant register 1 R/W H'FFFF H'FFFFF71C 8, 16, 32 1 Notes: 1. The only value that can be written to the CMCSR0 and CMCSR1 CMF bits is a 0 to clear the flags. 2. With regard to access size, four or five cycles are required for byte access and word access, and eight or nine cycles for longword access. 429 13.2 Register Descriptions 13.2.1 Compare Match Timer Start Register (CMSTR) The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). It is initialized to H'0000 by a power-on reset and in the standby modes. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — STR1 STR0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W • Bits 15 to 2—Reserved: These bits always read 0. The write value should always be 0. • Bit 1—Count Start 1 (STR1): Selects whether to operate or halt compare match timer counter 1. Bit 1: STR1 Description 0 CMCNT1 count operation halted 1 CMCNT1 count operation (Initial value) • Bit 0—Count Start 0 (STR0): Selects whether to operate or halt compare match timer counter 0. Bit 0: STR0 Description 0 CMCNT0 count operation halted 1 CMCNT0 count operation 430 (Initial value) 13.2.2 Compare Match Timer Control/Status Register (CMCSR) The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the clock used for incrementation. It is initialized to H'0000 by a power-on reset and in the standby modes. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 CMF CMIE — — — — CKS1 CKS0 0 0 0 0 0 0 0 0 R/(W)* R/W R R R R R/W R/W Initial value: R/W: Note: * The only value that can be written is a 0 to clear the flag. • Bits 15 to 8 and 5 to 2—Reserved: These bits always read 0. The write value should always be 0. • Bit 7—Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and CMCOR values have matched. Bit 7: CMF Description 0 CMCNT and CMCOR values have not matched (Initial value) [Clearing condition] Write 0 to CMF after reading 1 from it 1 CMCNT and CMCOR values have matched • Bit 6—Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1). Bit 6: CMIE Description 0 Compare match interrupt (CMI) disabled 1 Compare match interrupt (CMI) enabled (Initial value) 431 • Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock input to CMCNT from among the four internal clocks obtained by dividing the peripheral clock (Pφ). When the STR bit of CMSTR is set to 1, CMCNT begins incrementing with the clock selected by CKS1 and CKS0. Bit 1: CKS1 Bit 0: CKS0 Description 0 0 Pφ/8 1 Pφ/32 0 Pφ/128 1 Pφ/512 1 13.2.3 (Initial value) Compare Match Timer Counter (CMCNT) The compare match timer counter (CMCNT) is a 16-bit register used as an up-counter for generating interrupt requests. When an internal clock is selected with the CKS1 and CKS0 bits of the CMCSR register and the STR bit of CMSTR is set to 1, CMCNT begins incrementing with that clock. When the CMCNT value matches that of the compare match timer constant register (CMCOR), CMCNT is cleared to H'0000 and the CMF flag of CMCSR is set to 1. If the CMIE bit of CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. CMCNT is initialized to H'0000 by a power-on reset and in the standby modes. It is not initialized by a manual reset. Bit: 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: R/W: 432 13.2.4 Compare Match Timer Constant Register (CMCOR) The compare match timer constant register (CMCOR) is a 16-bit register that sets the period for compare match with CMCNT. CMCOR is initialized to H'FFFF by a power-on reset and in the standby modes. It is not initialized by a manual reset. Bit: 15 Initial value: 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: 13.3 Operation 13.3.1 Cyclic Count Operation When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR bit of CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the CMCNT counter value matches that of the compare match constant register (CMCOR), the CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT counter begins counting up again from H'0000. Figure 13.2 shows the compare match counter operation. CMCNT value Counter cleared by CMCOR compare match CMCOR H'0000 Time Figure 13.2 Counter Operation 433 13.3.2 CMCNT Count Timing One of four clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral clock (Pφ) can be selected by the CKS1 and CKS0 bits of CMCSR. Figure 13.3 shows the timing. Pφ Internal clock CMCNT input clock CMCNT N–1 N N+1 Figure 13.3 Count Timing 13.4 Interrupts 13.4.1 Interrupt Sources and DTC Activation The CMT has a compare match interrupt for each channel, with independent vector addresses allocated to each of them. The corresponding interrupt request is output when interrupt request flag CMF is set to 1 and interrupt enable bit CMIE has also been set to 1. When activating CPU interrupts by interrupt request, the priority between the channels can be changed by means of interrupt controller settings. See section 6, Interrupt Controller, for details. 13.4.2 Compare Match Flag Set Timing The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the CMCOR register and the CMCNT counter match. The compare match signal is generated upon the final state of the match (timing at which the CMCNT counter matching count value is updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal will not be generated until a CMCNT counter input clock occurs. Figure 13.4 shows the CMF bit set timing. 434 Pφ CMCNT input clock CMCNT CMCOR N 0 N Compare match signal CMF CMI Figure 13.4 CMF Set Timing 13.4.3 Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared by writing a 0 to it after reading a 1. Figure 13.5 shows the timing when the CMF bit is cleared by the CPU. CMCSR write cycle T1 T2 Pφ CMF Figure 13.5 Timing of CMF Clear by the CPU 435 13.5 Usage Notes Take care that the contentions described in sections 13.5.1 to 13.5.3 do not arise during CMT operation. 13.5.1 Contention between CMCNT Write and Compare Match If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure 13.6 shows the timing. CMCNT write cycle T1 T2 Pφ Address CMCNT Internal write signal Compare match signal CMCNT N H'0000 Figure 13.6 CMCNT Write and Compare Match Contention 436 13.5.2 Contention between CMCNT Word Write and Incrementation If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter write has priority, so no increment occurs. Figure 13.7 shows the timing. CMCNT write cycle T1 T2 Pφ Address CMCNT Internal write signal CMCNT input clock CMCNT N M CMCNT write data Figure 13.7 CMCNT Word Write and Increment Contention 437 13.5.3 Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the side on which the write was performed. The byte data on the side on which writing was not performed is also not incremented, so the contents are those before the write. Figure 13.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle. CMCNT write cycle T1 T2 Pφ Address CMCNTH Internal write signal CMCNT input clock CMCNTH N M CMCNTH write data CMCNTL X X Figure 13.8 CMCNT Byte Write and Increment Contention 438 Section 14 Serial Communication Interface (SCI) 14.1 Overview The SH7052F/SH7053F/SH7054F has a serial communication interface (SCI) with five independent channels. The SCI supports both asynchronous and synchronous serial communication. It also has a multiprocessor communication function for serial communication between two or more processors, and a clock inverted input/output function. 14.1.1 Features The SCI has the following features: • Selection of asynchronous or synchronous as the serial communication mode Asynchronous mode Serial data communication is synchronized in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other chip that employs standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. • Data length: seven or eight bits • Stop bit length: one or two bits • Parity: even, odd, or none • Multiprocessor bit: one or none • Receive error detection: parity, overrun, and framing errors • Break detection: by reading the RxD level directly when a framing error occurs Synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is one serial data communication format. • Data length: eight bits • Receive error detection: overrun errors • Serial clock inverted input/output • Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. • On-chip baud rate generator with selectable bit rates 439 • Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin (external) • Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can start the direct memory access controller (DMAC) to transfer data. • Selection of LSB-first or MSB-first transfer (8-bit length) This selection is available regardless of the communication mode. (The descriptions in this section are based on LSB-first transfer.) 14.1.2 Block Diagram Bus interface Figure 14.1 shows a block diagram of the SCI. Module data bus RDR TDR Internal data bus BRR SSR SCR SMR RxD RSR TSR Baud rate generator SDCR Transmit/ receive control TxD Parity generation Pφ Pφ/4 Pφ/16 Pφ/64 Clock Parity check External clock SCK TEI TXI RXI ERI SCI RSR: RDR: TSR: TDR: Receive shift register Receive data register Transmit shift register Transmit data register SMR: SCR: SSR: BRR: SDCR: Serial mode register Serial control register Serial status register Bit rate register Serial direction control register Figure 14.1 SCI Block Diagram 440 14.1.3 Pin Configuration Table 14.1 summarizes the SCI pins by channel. Table 14.1 SCI Pins Channel Pin Name Abbreviation Input/Output Function 0 Serial clock pin SCK0 Input/output SCI0 clock input/output Receive data pin RxD0 Input SCI0 receive data input Transmit data pin TxD0 Output SCI0 transmit data output Serial clock pin SCK1 Input/output SCI1 clock input/output Receive data pin RxD1 Input SCI1 receive data input Transmit data pin TxD1 Output SCI1 transmit data output Serial clock pin SCK2 Input/output SCI2 clock input/output Receive data pin RxD2 Input SCI2 receive data input Transmit data pin TxD2 Output SCI2 transmit data output Serial clock pin SCK3 Input/output SCI3 clock input/output Receive data pin RxD3 Input SCI3 receive data input Transmit data pin TxD3 Output SCI3 transmit data output Serial clock pin SCK4 Input/output SCI4 clock input/output Receive data pin RxD4 Input SCI4 receive data input Transmit data pin TxD4 Output SCI4 transmit data output 1 2 3 4 Note: In the text the pins are referred to as SCK, RxD, and TxD, omitting the channel number. 441 14.1.4 Register Configuration Table 14.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 14.2 Registers Channel Name Abbreviation R/W Initial Value Address* 2 Access Size 0 Serial mode register 0 SMR0 R/W H'00 H'FFFFF000 8, 16 Bit rate register 0 BRR0 R/W H'FF H'FFFFF001 Serial control register 0 SCR0 R/W H'00 H'FFFFF002 Transmit data register 0 TDR0 R/W H'FF H'FFFFF003 H'84 H'FFFFF004 1 2 442 1 Serial status register 0 SSR0 R/(W)* Receive data register 0 RDR0 R H'00 H'FFFFF005 Serial direction control register 0 SDCR0 R/W H'F2 H'FFFFF006 8 Serial mode register 1 SMR1 R/W H'00 H'FFFFF008 8, 16 Bit rate register 1 BRR1 R/W H'FF H'FFFFF009 Serial control register 1 SCR1 R/W H'00 H'FFFFF00A Transmit data register 1 TDR1 R/W H'FF H'FFFFF00B H'84 H'FFFFF00C 1 Serial status register 1 SSR1 R/(W)* Receive data register 1 RDR1 R H'00 H'FFFFF00D Serial direction control register 1 SDCR1 R/W H'F2 H'FFFFF00E 8 Serial mode register 2 SMR2 R/W H'00 H'FFFFF010 8, 16 Bit rate register 2 BRR2 R/W H'FF H'FFFFF011 Serial control register 2 SCR2 R/W H'00 H'FFFFF012 Transmit data register 2 TDR2 R/W H'FF H'FFFFF013 H'84 H'FFFFF014 1 Serial status register 2 SSR2 R/(W)* Receive data register 2 RDR2 R H'00 H'FFFFF015 Serial direction control register 2 SDCR2 R/W H'F2 H'FFFFF016 8 Table 14.2 Registers (cont) Channel Name Abbreviation R/W Initial Value Address* 2 Access Size 3 Serial mode register 3 SMR3 R/W H'00 H'FFFFF018 8, 16 Bit rate register 3 BRR3 R/W H'FF H'FFFFF019 Serial control register 3 SCR3 R/W H'00 H'FFFFF01A Transmit data register 3 TDR3 R/W H'FF H'FFFFF01B H'84 H'FFFFF01C 4 1 Serial status register 3 SSR3 R/(W)* Receive data register 3 RDR3 R H'00 H'FFFFF01D Serial direction control register 3 SDCR3 R/W H'F2 H'FFFFF01E 8 Serial mode register 4 SMR4 R/W H'00 H'FFFFF020 8, 16 Bit rate register 4 BRR4 R/W H'FF H'FFFFF021 Serial control register 4 SCR4 R/W H'00 H'FFFFF022 Transmit data register 4 TDR4 R/W H'FF H'FFFFF023 H'84 H'FFFFF024 1 Serial status register 4 SSR4 R/(W)* Receive data register 4 RDR4 R H'00 H'FFFFF025 Serial direction control register 4 SDCR4 R/W H'F2 H'FFFFF026 8 Notes: 1. The only value that can be written is a 0 to clear the flags. 2. Do not access empty addresses. 3. In register access, four or five cycles are required for byte access, and eight or nine cycles for word access. 14.2 Register Descriptions 14.2.1 Receive Shift Register (RSR) The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to RDR. The CPU cannot read or write to RSR directly. Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — 443 14.2.2 Receive Data Register (RDR) The receive data register (RDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (RSR) into RDR for storage. RSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write to RDR. RDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. 14.2.3 Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Transmit Shift Register (TSR) The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the transmit data register (TDR) into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting again. If the TDRE bit of SSR is 1, however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write to TSR directly. 444 Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — 14.2.4 Transmit Data Register (TDR) The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in TDR into TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in TDR during serial transmission from TSR. The CPU can always read and write to TDR. TDR is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: 14.2.5 Serial Mode Register (SMR) The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SMR. SMR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset, and in software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or synchronous mode. Bit 7: C/A Description 0 Asynchronous mode 1 Synchronous mode (Initial value) 445 • Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6: CHR Description 0 Eight-bit data 1 Seven-bit data (Initial value) When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. LSB-first/MSB-first selection is not available. • Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In synchronous mode and when using a multiprocessor format, a parity bit is neither added nor checked, regardless of the PE bit setting. Bit 5: PE Description 0 Parity bit not added or checked 1 Parity bit added and checked (Initial value) When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E bit) setting. Receive data parity is checked according to the even/odd (O/E bit) setting. • Bit 4—Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is invalid in synchronous mode, in asynchronous mode when parity bit addition and checking is disabled, and when using a multiprocessor format. Bit 4: O/E Description 0 Even parity (Initial value) If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1 Odd parity If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. 446 • Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 3: STOP Description 0 One stop bit (Initial value) In transmitting, a single bit of 1 is added at the end of each transmitted character. 1 Two stop bits In transmitting, two 1-bits are added at the end of each transmitted character. • Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit setting is used only in asynchronous mode; it is ignored in synchronous mode. For the multiprocessor communication function, see section 14.3.3, Multiprocessor Communication. Bit 2: MP Description 0 Multiprocessor function disabled 1 Multiprocessor format selected (Initial value) • Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available: Pφ, Pφ/4, Pφ/16, or Pφ/64 (Pφ is the peripheral clock). For further information on the clock source, bit rate register settings, and baud rate, see section 14.2.8, Bit Rate Register. Bit 1: CKS1 Bit 0: CKS0 Description 0 0 Pφ 1 Pφ/4 0 Pφ/16 1 Pφ/64 1 (Initial value) 447 14.2.6 Serial Control Register (SCR) The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCR. SCR is initialized to H'00 by a poweron reset, and in hardware standby mode. It is not initialized by a manual reset, and in software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1 by transfer of serial transmit data from TDR to TSR. Bit 7: TIE Description 0 Transmit-data-empty interrupt request (TXI) is disabled (Initial value) The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. 1 Transmit-data-empty interrupt request (TXI) is enabled • Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1 by transfer of serial receive data from RSR to RDR. It also enables or disables receive-error interrupt (ERI) requests. Bit 6: RIE Description 0 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled (Initial value) RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. 1 448 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled • Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter. Bit 5: TE Description 0 Transmitter disabled (Initial value) The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1. 1 Transmitter enabled Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR) is cleared to 0 after writing of transmit data into TDR. Select the transmit format in SMR before setting TE to 1. • Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver. Bit 4: RE Description 0 Receiver disabled (Initial value) Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. 1 Receiver enabled Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in synchronous mode. Select the receive format in SMR before setting RE to 1. 449 • Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE Description 0 Multiprocessor interrupts are disabled (normal receive operation) (Initial value) [Clearing conditions] 1 • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received Multiprocessor interrupts are enabled. Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SSR) are disabled until data with the multiprocessor bit set to 1 is received. The SCI does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SSR). When it receives data that includes MPB = 1, MPB is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1), and allows the FER and ORER bits to be set. • Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted. Bit 2: TEIE Description 0 Transmit-end interrupt (TEI) requests are disabled* 1 Transmit-end interrupt (TEI) requests are enabled* (Initial value) Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0; or by clearing the TEIE bit to 0. 450 • Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output, or serial clock input. Select the SCK pin function by using the pin function controller (PFC). The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). For further details on selection of the SCI clock source, see table 14.9 in section 14.3, Operation. Bit 1: Bit 0: CKE1 CKE0 Description*1 0 0 1 1 0 1 0 1 Asynchronous mode Internal clock, SCK pin used for input pin (input signal is ignored) or output pin (output level is undefined)* 2 Synchronous mode Internal clock, SCK pin used for synchronous clock output*2 Asynchronous mode Internal clock, SCK pin used for clock output*3 Synchronous mode Internal clock, SCK pin used for synchronous clock output Asynchronous mode External clock, SCK pin used for clock input* 4 Synchronous mode External clock, SCK pin used for synchronous clock input Asynchronous mode External clock, SCK pin used for clock input* 4 Synchronous mode External clock, SCK pin used for synchronous clock input Notes: 1. The SCK pin is multiplexed with other functions. Use the pin function controller (PFC) to select the SCK function for this pin, as well as the I/O direction. 2. Initial value. 3. The output clock frequency is the same as the bit rate. 4. The input clock frequency is 16 times the bit rate. 451 14.2.7 Serial Status Register (SSR) The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating status. The CPU can always read and write to SSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SSR is initialized to H'84 by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * The only value that can be written is a 0 to clear the flag. • Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and new serial transmit data can be written in TDR. Bit 7: TDRE Description 0 TDR contains valid transmit data [Clearing conditions] 1 • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC writes data in TDR TDR does not contain valid transmit data (Initial value) [Setting conditions] 452 • Power-on reset, hardware standby mode, or software standby mode • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR, enabling new data to be written in TDR • Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains received data. Bit 6: RDRF Description 0 RDR does not contain valid receive data (Initial value) [Clearing conditions] 1 • Power-on reset, hardware standby mode, or software standby mode • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC reads data from RDR RDR contains valid received data [Setting condition] RDRF is set to 1 when serial data is received normally and transferred from RSR to RDR Note: RDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the receive data is lost. • Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5: ORER Description 0 Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which retains its previous value. [Clearing conditions] 1 • Power-on reset, hardware standby mode, or software standby mode • When 0 is written to ORER after reading ORER = 1 A receive overrun error occurred RDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In synchronous mode, serial transmitting is disabled. [Setting condition] ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1 453 • Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing error in asynchronous mode. Bit 4: FER Description 0 Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value. [Clearing conditions] 1 • Power-on reset, hardware standby mode, or software standby mode • When 0 is written to FER after reading FER = 1 A receive framing error occurred When the stop bit length is two bits, only the first bit is checked to see if it is a 1. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In synchronous mode, serial transmitting is also disabled. [Setting condition] FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0 • Bit 3—Parity Error (PER): Indicates that data reception (with parity) ended abnormally due to a parity error in asynchronous mode. Bit 3: PER Description 0 Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which retains its previous value. [Clearing conditions] 1 • Power-on reset, hardware standby mode, or software standby mode • When 0 is written to PER after reading PER = 1 A receive parity error occurred When a parity error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. [Setting condition] PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR) 454 • Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, TDR did not contain valid data, so transmission has ended. TEND is a read-only bit and cannot be written. Bit 2: TEND Description 0 Transmission is in progress [Clearing conditions] 1 • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC writes data in TDR End of transmission (Initial value) [Setting conditions] • Power-on reset, hardware standby mode, or software standby mode • When the TE bit in SCR is 0 • If TDRE = 1 when the last bit of a one-byte serial transmit character is transmitted • Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in asynchronous mode. MPB is a readonly bit and cannot be written. Bit 1: MPB Description 0 Multiprocessor bit value in receive data is 0 (Initial value) If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previous value. 1 Multiprocessor bit value in receive data is 1 • Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. Bit 0: MPBT Description 0 Multiprocessor bit value in transmit data is 0 1 Multiprocessor bit value in transmit data is 1 (Initial value) 455 14.2.8 Bit Rate Register (BRR) The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the serial transmit/receive bit rate. The CPU can always read and write to BRR. BRR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset, and in software standby mode. Each channel has independent baud rate generator control, so different values can be set for each channel. Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: Table 14.3 lists examples of BRR settings in the asynchronous mode; table 14.4 lists examples of BBR settings in the clock synchronous mode. The BRR setting is calculated as follows: Asynchronous mode: N= Pφ 64 × 22n–1 × B × 106 – 1 Synchronous mode: N= B: N: Pφ 8 × 22n–1 × B × 106 – 1 Bit rate (bits/s) Baud rate generator BRR setting (0 ≤ N ≤ 255) Pφ : Peripheral module operating frequency (MHz) (1/2 of system clock) n: Baud rate generator input clock (n = 0 to 3) (See the following table for the clock sources and value of n.) 456 SMR Settings CKS2 n Clock Source CKS1 0 Pφ 0 0 1 Pφ /4 0 1 2 Pφ /16 1 0 3 Pφ /64 1 1 The bit rate error in asynchronous mode is calculated as follows: Pφ × 106 Error (%) = – 1 × 100 2n–1 (N + 1) × B × 64 × 2 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode φ (MHz) Pφ 10 11.0592 12 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 177 –0.25 2 195 0.19 2 212 0.03 150 2 129 0.16 2 143 0.00 2 155 0.16 300 2 64 0.16 2 71 0.00 2 77 0.16 600 1 129 0.16 1 143 0.00 1 155 0.16 1200 1 64 0.16 1 71 0.00 1 77 0.16 2400 0 129 0.16 0 143 0.00 0 155 0.16 4800 0 64 0.16 0 71 0.00 0 77 0.16 9600 0 32 –1.36 0 35 0.00 0 28 0.16 14400 0 21 –1.36 0 23 0.00 0 25 0.16 19200 0 15 1.73 0 19 0.00 0 19 –2.34 28800 0 10 –1.36 0 11 0.00 0 12 0.16 31250 0 9 0.00 0 10 0.54 0 11 0.00 38400 0 7 1.73 0 8 0.00 0 9 –2.34 457 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) Pφ 12.288 14 14.7456 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.70 150 2 159 0.00 2 181 0.16 2 191 0.00 300 2 79 0.00 2 90 0.16 2 95 0.00 600 1 159 0.00 1 181 0.16 1 191 0.00 1200 1 79 0.00 1 90 0.16 1 95 0.00 2400 0 159 0.00 0 181 0.16 0 191 0.00 4800 0 79 0.00 0 90 0.16 0 95 0.00 9600 0 39 0.00 0 45 –0.93 0 47 0.00 14400 0 26 –1.23 0 29 1.27 0 31 0.00 19200 0 19 0.00 0 22 –0.93 0 23 0.00 28800 0 12 2.56 0 14 1.27 0 15 0.00 31250 0 11 2.40 0 13 0.00 0 14 –1.70 38400 0 9 0.00 0 10 3.57 0 11 0.00 458 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) Pφ 16 17.2032 18 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 3 70 0.03 3 75 0.48 3 79 –0.12 150 2 207 0.16 2 223 0.00 2 233 0.16 300 2 103 0.16 2 111 0.00 2 116 0.16 600 1 207 0.16 1 223 0.00 1 233 0.16 1200 1 103 0.16 1 111 0.00 1 116 0.16 2400 0 207 0.16 0 223 0.00 0 233 0.16 4800 0 103 0.16 0 111 0.00 0 116 0.16 9600 0 51 0.16 0 55 0.00 0 58 –0.69 14400 0 34 –0.79 0 36 0.90 0 38 0.16 19200 0 25 0.16 0 27 0.00 0 28 1.02 28800 0 16 2.12 0 18 –1.75 0 19 –2.34 31250 0 15 0.00 0 16 1.20 0 17 0.00 38400 0 12 0.16 0 13 0.00 0 14 –2.34 459 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 18.432 19.6608 20 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 3 81 –0.22 3 86 0.31 3 88 –0.25 150 2 239 0.00 2 255 0.00 3 64 0.16 300 2 119 0.00 2 127 0.00 2 129 0.16 600 1 239 0.00 1 255 0.00 2 64 0.16 1200 1 119 0.00 1 127 0.00 1 129 0.16 2400 0 239 0.00 0 255 0.00 1 64 0.16 4800 0 119 0.00 0 127 0.00 0 129 0.16 9600 0 59 0.00 0 63 0.00 0 64 0.16 14400 0 39 0.00 0 42 –0.78 0 42 0.94 19200 0 29 0.00 0 31 0.00 0 32 –1.36 28800 0 19 0.00 0 20 1.59 0 21 –1.36 31250 0 17 2.40 0 19 –1.70 0 19 0.00 38400 0 14 0.00 0 15 0.00 0 15 1.73 460 Table 14.4 Bit Rates and BRR Settings in Synchronous Mode φ (MHz) Pφ 10 12 16 Bit Rate (Bits/s) n N n N n N 250 — — 3 187 3 249 500 — — 3 93 3 1k — — 2 187 2.5 k 1 249 2 5k 1 124 10 k 0 25 k 20 n N 124 — — 2 249 — — 74 2 99 2 124 1 149 1 199 2 249 249 1 74 1 99 1 124 0 99 0 119 0 159 1 199 50 k 0 49 0 59 0 79 0 99 100 k 0 24 0 29 0 39 0 49 250 k 0 9 0 11 0 15 0 19 500 k 0 4 0 5 0 7 0 9 0 2 0 3 0 4 0 0* — — 0 1 0 0* 1M 2.5 M 0 0* 5M Note: Settings with an error of 1% or less are recommended. Legend Blank: No setting available —: Setting possible, but error occurs *: Continuous transmission/reception not possible Table 14.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is being used for various frequencies. Tables 14.6 and 14.7 show the maximum rates for external clock input. 461 Table 14.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings φ (MHz) Pφ Maximum Bit Rate (Bits/s) n N 10 312500 0 0 11.0592 345600 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 18.432 576000 0 0 19.6608 614400 0 0 20 625000 0 0 Table 14.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode) φ (MHz) Pφ External Input Clock (MHz) Maximum Bit Rate (Bits/s) 10 2.5000 156250 11.0592 2.7648 172800 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 18.432 4.6080 288000 19.6608 4.9152 307200 20 5.0000 312500 462 Table 14.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode) φ (MHz) Pφ External Input Clock (MHz) Maximum Bit Rate (Bits/s) 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 14.2.9 Serial Direction Control Register (SDCR) Bit: 7 6 5 4 3 2 1 0 — — — — DIR — — — Initial value: 1 1 1 1 0 0 1 0 R/W: R R R R R/W R R R The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the communication mode. With a 7-bit data length, LSB-first transfer must be selected. The description in this section assumes LSB-first transfer. SDCR is initialized to H'F2 by a power-on reset and in the hardware standby mode. It is not initialized by a manual reset, and in software standby mode. • Bits 7 to 4—Reserved: The write value must always be 1. Operation cannot be guaranteed if 0 is written. • Bit 3—Data Transfer Direction (DIR): Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive format. Bit 3: DIR Description 0 TDR contents are transmitted in LSB-first order (Initial value) Receive data is stored in RDR in LSB-first order 1 TDR contents are transmitted in MSB-first order Receive data is stored in RDR in MSB-first order • Bit 2—Reserved: This bit always reads 0. Operation cannot be guaranteed if 1 is written. • Bit 1—Reserved: This bit always reads 1, and cannot be modified. 463 • Bit 0—Reserved: This bit always reads 0. Operation cannot be guaranteed if 1 is written. 14.2.10 Inversion of SCK Pin Signal The signal input from the SCK pin and the signal output from the SCK pin can be inverted by means of a port control register setting. See the section on port function control for details. 14.3 Operation 14.3.1 Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made in the serial mode register (SMR) as shown in table 14.8. The SCI clock source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR), as shown in table 14.9. Asynchronous Mode: • Data length is selectable: seven or eight bits. • Parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits). These selections determine the transmit/receive format and character length. • In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors (ORER), and the break state. • An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator clock, and can output a clock with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode: • The communication format has a fixed 8-bit data length. • In receiving, it is possible to detect overrun errors (ORER). • An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator clock, and outputs a serial clock signal to external devices. When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. 464 Table 14.8 Serial Mode Register Settings and SCI Communication Formats SMR Settings SCI Communication Format Mode Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 2 MP Bit 3 STOP Data Length Parity Bit Multipro- Stop Bit cessor Bit Length Asynchronous 0 0 0 0 0 8-bit Absent Absent 1 1 2 bits 0 Present 1 bit 1 1 0 0 2 bits 7-bit Absent 1 bit 1 1 2 bits 0 Present 1 bit 1 Asynchronous (multiprocessor format) 0 * 1 Synchronous 1 * 1 0 * 1 * 0 * 1 * * * 1 bit 2 bits 8-bit Absent Present 1 bit 2 bits 7-bit 1 bit 2 bits 8-bit Absent None Note: Asterisks (*) in the table indicate don’t care bits. Table 14.9 SMR and SCR Settings and SCI Clock Source Selection SMR Mode Bit 7 C/A Asynchronous 0 SCR Settings SCI Transmit/Receive Clock Bit 1 CKE1 Bit 0 CKE0 Clock Source SCK Pin Function* 0 0 Internal 1 1 0 SCI does not use the SCK pin Outputs a clock with frequency matching the bit rate External Inputs a clock with frequency 16 times the bit rate Internal Outputs the serial clock or the inverted serial clock External Inputs the serial clock or the inverted serial clock 1 Synchronous 1 0 0 1 1 0 1 Note: * Select the function in combination with the pin function controller (PFC). 465 14.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 14.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the marking (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes on the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. (LSB) 1 Serial data 0 D0 Idling (marking) 1 (MSB) D1 D2 D3 D4 D5 Start bit D6 D7 0/1 1 1 Parity bit Stop bit 1 or no bit 1 or 2 bits Transmit/receive data 1 bit 7 or 8 bits One unit of communication data (character or frame) Figure 14.2 Data Format in Asynchronous Communication (Example: 8-bit Data with Parity and Two Stop Bits) 466 Transmit/Receive Formats: Table 14.10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SMR). Table 14.10 Serial Communication Formats (Asynchronous Mode) SMR Bits Serial Transmit/Receive Format and Frame Length CHR PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 START 8-bit data STOP 0 0 0 1 START 8-bit data STOP STOP 0 1 0 0 START 8-bit data P STOP 0 1 0 1 START 8-bit data P STOP STOP 1 0 0 0 START 7-bit data STOP 1 0 0 1 START 7-bit data STOP STOP 1 1 0 0 START 7-bit data P STOP 1 1 0 1 START 7-bit data P STOP STOP 0 — 1 0 START 8-bit data MPB STOP 0 — 1 1 START 8-bit data MPB STOP STOP 1 — 1 0 START 7-bit data MPB STOP 1 — 1 1 START 7-bit data MPB STOP STOP —: Don’t care bits. START: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR) (table 14.9). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. 467 When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 14.3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 14.3 Output Clock and Communication Data Phase Relationship (Asynchronous Mode) Data Transmit/Receive Operation SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the operation mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 14.4 is a sample flowchart for initializing the SCI. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in SCR. 2. Select the communication format in the serial mode register (SMR) and serial direction control register (SDCR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR) (unless an external clock is used). 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1.* Also set RIE, TIE, TEIE and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD or RxD pin. Note: * In simultaneous transmit/receive operation, the TE bit and RE bit must be cleared to 0 or set to 1 simultaneously. 468 Initialization Clear TE and RE bits to 0 in SCR Set transmit/receive format in SMR (TE and RE bits cleared to 0) 1 Select transmit/receive format in SMR and SDCR 2 Set value in BRR 3 Wait 1-bit interval elapsed? No Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE as necessary 4 End Figure 14.4 Sample Flowchart for SCI Initialization Transmitting Serial Data (Asynchronous Mode): Figure 14.5 shows a sample flowchart for transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the TxD pin using the PFC. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. 3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-empty interrupt request (TXI) in order to write data in TDR, the TDRE bit is checked and cleared automatically. 4. To output a break at the end of serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCR and use the PFC to establish the TxD pin as an output port. 469 Initialization 1 Start of transmission Read TDRE bit in SSR 2 No TDRE = 1? Yes Write transmit data to TDR and clear TDRE bit in SSR to 0 3 All data transmitted? No Yes Read TEND bit in SSR No TEND = 1? Yes No Output break signal? 4 Yes Clear port DR to 0 Clear TE bit in SCR to 0; select theTxD pin as an output port with the PFC End of transmission Figure 14.5 Sample Flowchart for Transmitting Serial Data 470 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0-bit is output. b. Transmit data: seven or eight bits of data are output, LSB first. c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: one or two 1-bits (stop bits) are output. e. Marking: output of 1-bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in SSR, outputs the stop bit, then continues output of 1-bits (marking). If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-end interrupt (TEI) is requested. Figure 14.6 shows an example of SCI transmit operation in asynchronous mode. 471 1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 Idling 1 (marking) TDRE TEND TXI TXI interrupt interrupt handler writes request data in TDR and clears TDRE to 0 TXI interrupt request TEI interrupt request 1 frame Figure 14.6 SCI Transmit Operation in Asynchronous Mode (Example: 8-Bit Data with Parity and One Stop Bit) Receiving Serial Data (Asynchronous Mode): Figures 14.7 and 14.8 show a sample flowchart for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart). 1. SCI initialization: Set the RxD pin using the PFC. 2. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER bits of SSR to identify the error. After executing the necessary error handling, clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 3. SCI status check and receive-data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. Continue receiving serial data: Read RDR and the RDRF bit and clear RDRF to 0 before the stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. 472 Initialization 1 Start of reception Read ORER, PER, and FER bits in SSR PER, FER, ORER = 1? Yes 2 Error handling No Read RDRF bit in SSR No 3 RDRF = 1? Yes Read receive data in RDR and clear RDRF bit in SSR to 0 No 4 All data received? Yes Clear RE bit in SCR to 0 End of reception Figure 14.7 Sample Flowchart for Receiving Serial Data (1) 473 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling No Clear RE bit in SCR to 0 PER = 1? Yes Parity error handling Clear ORER, PER, and FER to 0 in SSR End Figure 14.8 Sample Flowchart for Receiving Serial Data (2) 474 In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into RSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check. The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR. b. Stop bit check. The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check. RDRF must be 0 so that receive data can be loaded from RSR into RDR. If the data passes these checks, the SCI sets RDRF to 1 and stores the receive data in RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 14.11. Note: When a receive error occurs, further receiving is disabled. While receiving, the RDRF bit is not set to 1, so be sure to clear the error flags. 4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Table 14.11 Receive Error Conditions and SCI Operation Receive Error Abbreviation Condition Data Transfer Overrun error ORER Receiving of next data ends while RDRF is still set to 1 in SSR Receive data not loaded from RSR into RDR Framing error FER Stop bit is 0 Receive data loaded from RSR into RDR Parity error PER Parity of receive data differs from even/odd parity setting in SMR Receive data loaded from RSR into RDR Figure 14.9 shows an example of SCI receive operation in asynchronous mode. 475 1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Parity Stop bit bit Data D0 D1 D7 0/1 1 1 Idling (marking) RDRF RXI interrupt request FER 1 frame RXI interrupt handler reads data in RDR and clears RDRF to 0. Framing error generates ERI interrupt request. Figure 14.9 SCI Receive Operation (Example: 8-Bit Data with Parity and One Stop Bit) 14.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line for sending and receiving data. The processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 14.10 shows an example of communication among processors using the multiprocessor format. 476 Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 14.8. Clock: See the description in the asynchronous mode section. Transmitting processor Serial communication line Serial data Receiving processor A Receiving processor B Receiving processor C Receiving processor D (ID = 01) (ID = 02) (ID = 03) (ID = 04) H'01 H'AA (MPB = 1) ID-transmit cycle: receiving processor address (MPB = 0) Data-transmit cycle: data sent to receiving processor specified by ID MPB: Multiprocessor bit Figure 14.10 Communication Among Processors Using Multiprocessor Format (Example: Sending Data H'AA to Receiving Processor A) Data Transmit/Receive Operation Transmitting Multiprocessor Serial Data: Figure 14.11 shows a sample flowchart for transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the TxD pin using the PFC. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0. 3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. 4. Output a break at the end of serial transmission: Set the data register (DR) of the port to 0, then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC. 477 Initialization 1 Start of transmission Read TDRE bit in SSR TDRE = 1? 2 No Yes Write transmit data in TDR and set MPBT in SSR Clear TDRE bit to 0 All data transmitted? No 3 Yes Read TEND bit in SSR TEND = 1? No Yes Output break signal? No 4 Yes Clear port DR to 0 Clear TE bit in SCR to 0; select theTxD pin function as an output port with the PFC End of transmission Figure 14.11 Sample Flowchart for Transmitting Multiprocessor Serial Data 478 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0-bit is output. b. Transmit data: seven or eight bits are output, LSB first. c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output. d. Stop bit: one or two 1-bits (stop bits) are output. e. Marking: output of 1-bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, outputs the stop bit, then continues output of 1-bits in the marking state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. Figure 14.12 shows an example of SCI receive operation in the multiprocessor format. 1 Multiprocessor bit Stop Start Data bit bit Start bit Serial data 0 D0 D1 D7 0/1 1 0 Multiprocessor bit Stop Data bit D0 D1 D7 0/1 1 1 Idling (marking) TDRE TEND TXI interrupt request TXI interrupt handler writes data in TDR and clears TDRE to 0 TXI interrupt request TEI interrupt request 1 frame Figure 14.12 SCI Multiprocessor Transmit Operation (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) 479 Receiving Multiprocessor Serial Data: Figures 14.13 and 14.14 show sample flowcharts for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the RxD pin using the PFC. 2. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1. 3. SCI status check and compare to ID reception: Read the serial status register (SSR), check that RDRF is set to 1, then read data from the receive data register (RDR) and compare with the processor’s own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 5. SCI status check and data receiving: Read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR). 480 Initialization 1 Start of reception Set MPIE bit in SCR to 1 2 Read ORER and FER bits in SSR FER = 1? or ORER =1? Yes No Read RDRF bit in SSR No 3 RDRF = 1? Yes Read receive data from RDR No Is ID the station’s ID? Yes Read ORER and FER bits in SSR FER = 1? or ORER =1? Yes No Read RDRF bit in SSR RDRF = 1? 5 No Yes Read receive data from RDR 4 No All data received? Error handling Yes Clear RE bit in SCR to 0 End of reception Figure 14.13 Sample Flowchart for Receiving Multiprocessor Serial Data (1) 481 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling Clear RE bit in SCR to 0 Clear ORER and FER bits in SSR to 0 End Figure 14.14 Sample Flowchart for Receiving Multiprocessor Serial Data (2) 482 Figures 14.15 and 14.16 show examples of SCI receive operation using a multiprocessor format. 1 Serial data Start bit Data (ID1) 0 D0 D1 Stop Start Data MPB bit bit (data 1) D7 1 1 0 D0 D1 Stop MPB bit D7 0 1 1 Idling (marking) MPB MPIE RDRF RDR value ID1 RXI interrupt request (multiprocessor interrupt), MPIE = 0 RXI interrupt handler reads data in RDR and clears RDRF to 0 Not station’s ID, so MPIE is set to 1 again No RXI interrupt, RDR maintains state Figure 14.15 SCI Receive Operation (ID Does Not Match) (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) 483 1 Serial data Start bit 0 Data (ID2) D0 D1 Stop Start Data MPB bit bit (data 2) D7 1 1 0 D0 D1 Stop MPB bit D7 0 1 1 Idling (marking) MPB MPIE RDRF RDR value ID1 RXI interrupt request (multiprocessor interrupt), MPIE = 0 ID2 RXI interrupt handler reads data in RDR and clears RDRF to 0 Data 2 Station’s ID, so receiving MPIE continues, with data bit is again received by the RXI set to 1 interrupt processing routine Figure 14.16 Example of SCI Receive Operation (ID Matches) (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) 14.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full duplex communication is possible while sharing the same clock. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 14.17 shows the general format in synchronous serial communication. 484 Transfer direction One unit (character or frame) of communication data * * Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Note: * High except in continuous transmitting or receiving. Figure 14.17 Data Format in Synchronous Communication In synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode, the SCI transmits or receives data by synchronizing with the rise of the serial clock. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR). See table 14.9. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. An overrun error occurs only during the receive operation, and the serial clock is output until the RE bit is cleared to 0. To perform a receive operation in one-character units, select an external clock for the clock source. 485 Transmitting and Receiving Data SCI Initialization (Synchronous Mode): Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. Figure 14.18 is a sample flowchart for initializing the SCI. 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. 2. Select the communication format in the serial mode register (SMR) and serial direction control register (SDCR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR) (unless an external clock is used). 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1.* Also set RIE, TIE, TEIE, and MPIE. The TxD, RxD pins becomes usable in response to the PFC corresponding bits and the TE, RE bit settings. Note: * In simultaneous transmit/receive operation, the TE bit and RE bit must be cleared to 0 or set to 1 simultaneously. 486 Start of initialization Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (RIE, TIE, TEIE, MPIE,TE, and RE are 0) 1 Select transmit/receive format in SMR and SDCR 2 Set value in BRR 3 Wait 1-bit interval elapsed? No Yes Set TE and RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE bits 4 End of initialization Figure 14.18 Sample Flowchart for SCI Initialization Transmitting Serial Data (Synchronous Mode): Figure 14.19 shows a sample flowchart for transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the TxD pin function with the PFC. 2. SCI status check and transmit data write: Read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. 3. To continue transmitting serial data: After checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. 487 Initialization 1 Start of transmission 2 Read TDRE flag in SSR No TDRE = 1? Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR No All data transmitted? 3 Yes Read TEND flag in SSR TEND = 1? No Yes Clear TE bit to 0 in SCR End Figure 14.19 Sample Flowchart for Serial Transmitting 488 Figure 14.20 shows an example of SCI transmit operation. Transfer direction Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request TXI interrupt TXI interrupt handler writes request data in TDR and clears TDRE to 0 TEI interrupt request 1 frame Figure 14.20 Example of SCI Transmit Operation SCI serial transmission operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output mode is selected, the SCI outputs eight serial clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmitend interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK pin is held in the high state. 489 Receiving Serial Data (Synchronous Mode): Figures 14.21 and 14.22 show sample flowcharts for receiving serial data. When switching from asynchronous mode to synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. The procedure for receiving serial data is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the RxD pin using the PFC. 2. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 3. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. Continue receiving serial data: Read RDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. 490 Initialization 1 Start of reception Read ORER bit in SSR Yes ORER = 1? 2 No Read RDRF bit in SSR No Error handling 3 RDRF = 1? Yes Read receive data from RDR and clear RDRF bit in SSR to 0 4 No All data received? Yes Clear RE bit in SCR to 0 End of reception Figure 14.21 Sample Flowchart for Serial Receiving (1) 491 Error handling Overrun error handling Clear ORER bit in SSR to 0 End Figure 14.22 Sample Flowchart for Serial Receiving (2) Figure 14.23 shows an example of the SCI receive operation. Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request Read data with RXI interrupt processing routine and clear RDRF bit to 0 RXI interrupt request 1 frame Figure 14.23 Example of SCI Receive Operation 492 ERI interrupt request generated by overrun error In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into RSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the receive data in RDR. If the check does not pass (receive error), the SCI operates as indicated in table 14.11 and no further transmission or reception is possible. If the error flag is set to 1, the RDRF bit is not set to 1 during reception, even if the RDRF bit is 0 cleared. When restarting reception, be sure to clear the error flag. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receivedata-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 14.24 shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the TxD and RxD pins using the PFC. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. 3. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 4. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 5. Continue transmitting and receiving serial data: Read the RDRF bit and RDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is started by a transmitdata-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. When the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically. Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set both TE and RE to 1 simultaneously. 493 Initialization 1 Start of transmission/reception Read TDRE bit in SSR No 2 TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit in SSR to 0 Read ORER bit in SSR ORER = 1? Yes 3 Error handling No Read RDRF bit in SSR No 4 RDRF = 1? Yes Read receive data in RDR, and clear RDRF bit in SSR to 0 No 5 All data transmitted/ received? Yes Clear TE and RE bits in SCR to 0 End of transmission/reception Figure 14.24 Sample Flowchart for Serial Transmission and Reception 494 14.4 SCI Interrupt Sources and the DMAC The SCI has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 14.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in SSR is set to 1. TXI can start the direct memory access controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC writes data in the transmit data register (TDR). RXI is requested when the RDRF bit in SSR is set to 1. RXI can start the DMAC to transfer data. RDRF is automatically cleared to 0 when the DMAC reads the receive data register (RDR). ERI is requested when the ORER, PER, or FER bit in SSR is set to 1. ERI cannot start the DMAC. TEI is requested when the TEND bit in SSR is set to 1. TEI cannot start the DMAC. Where the TXI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is complete. Table 14.12 SCI Interrupt Sources Interrupt Source Description DMAC Activation Priority ERI Receive error (ORER, PER, or FER) No High RXI Receive data full (RDRF) Yes TXI Transmit data empty (TDRE) Yes TEI Transmit end (TEND) No Low 495 14.5 Usage Notes Sections 14.5.1 through 14.5.9 provide information concerning use of the SCI. 14.5.1 TDR Write and TDRE Flag The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is 0, however, the old data stored in TDR will be lost because the data has not yet been transferred to TSR. Before writing transmit data to TDR, be sure to check that TDRE is set to 1. 14.5.2 Simultaneous Multiple Receive Errors Table 14.13 indicates the state of the SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to RDR, so receive data is lost. Table 14.13 SSR Status Flags and Transfer of Receive Data Receive Error Status RDRF ORER FER PER Receive Data Transfer RSR → RDR Overrun error 1 1 0 0 X Framing error 0 0 1 0 O Parity error 0 0 0 1 O Overrun error + framing error 1 1 1 0 X Overrun error + parity error 1 1 0 1 X Framing error + parity error 0 0 1 1 O Overrun error + framing error + parity error 1 1 1 1 X SSR Status Flags Note: O: Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR. 496 14.5.3 Break Detection and Processing (Asynchronous Mode Only) Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. 14.5.4 Sending a Break Signal (Asynchronous Mode Only) The TxD pin becomes a general I/O pin with the I/O direction and level determined by the I/O port data register (DR) and pin function controller (PFC) control register (CR). These conditions allow break signals to be sent. The DR value is substituted for the marking status until the PFC is set. Consequently, the output port is set to initially output a 1. To send a break in serial transmission, first clear the DR to 0, then establish the TxD pin as an output port using the PFC. When TE is cleared to 0, the transmission section is initialized regardless of the present transmission status. 14.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only) When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. 14.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer rate. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure 14.25). 497 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks Receive data (RxD) +7.5 clocks Start bit D0 Synchronization sampling timing Data sampling timing Figure 14.25 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as: M = 0.5 – 1 D – 0.5 (1 + F) × 100% – (L – 0.5) F – 2N N M : Receive margin (%) N : Ratio of clock frequency to bit rate (N = 16) D : Clock duty cycle (D = 0 to 1.0) L : Frame length (L = 9 to 12) F : Absolute deviation of clock frequency From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%: D = 0.5, F = 0 M = (0.5 – 1/(2 × 16)) × 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%. 498 D1 14.5.7 Constraints on DMAC Use • When using an external clock source for the serial clock, update TDR with the DMAC, and then after the elapse of five peripheral clocks (Pφ) or more, input a transmit clock. If a transmit clock is input in the first four Pφ clocks after TDR is written, an error may occur (figure 14.26). • Before reading the receive data register (RDR) with the DMAC, select the receive-data-full (RXI) interrupt of the SCI as a start-up source. SCK t TDRE D0 D1 D2 D3 D4 D5 D6 D7 Note: During external clock operation, an error may occur if t is 4 Pφ clocks or less. Figure 14.26 Example of Synchronous Transmission with DMAC 14.5.8 Cautions on Synchronous External Clock Mode • Set TE = RE = 1 only when external clock SCK is 1. • Do not set TE = RE = 1 until at least four Pφ clocks after external clock SCK has changed from 0 to 1. • When receiving, RDRF is 1 when RE is cleared to zero 2.5 to 3.5 Pφ clocks after the rising edge of the RxD D7 bit SCK input, but copying to RDR is not possible. 14.5.9 Caution on Synchronous Internal Clock Mode When receiving, RDRF is 1 when RE is cleared to zero 1.5 Pφ clocks after the rising edge of the RxD D7 bit SCK output, but copying to RDR is not possible. 499 500 Section 15 Hitachi Controller Area Network (HCAN) 15.1 Overview The HCAN is a module for controlling a controller area network (CAN) for realtime communication in automotive and industrial equipment systems, etc. The SH7052F/SH7053F/ SH7054F has a 1-channel on-chip HCAN module. Reference: Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH 15.1.1 Features The HCAN has the following features: • CAN version: Bosch 2.0B active compatible Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function) Broadcast communication system Transmission path: Bidirectional 2-wire serial communication Communication speed: Max. 1 Mbps (at 40 MHz operation) Data length: 0 to 8 bytes • Number of channels: 1 • Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception) • Data transmission: Choice of two methods: Mailbox (buffer) number order (low-to-high) Message priority (identifier) high-to-low order • Data reception: Two methods: Message identifier match (transmit/receive-setting buffers) Reception with message identifier masked (receive-only) • CPU interrupts: Four independent interrupt vectors: Error interrupt Reset processing interrupt Message reception interrupt Message transmission interrupt • HCAN operating modes: Support for various modes: Hardware reset Software reset Normal status (error-active, error-passive) 501 Bus off status HCAN configuration mode HCAN sleep mode HCAN halt mode • Other features: DMAC can be activated by message reception mailbox (HCAN mailbox 0 only) 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the HCAN. Peripheral data bus Peripheral address bus HCAN MBI Message buffer Mailboxes Message control Message data MC0 to MC15, MD0 to MD15 LAFM (CDLC) CAN Data Link Controller Bosch CAN 2.0B active Tx buffer MPI Microprocessor interface Rx buffer HTxD HRxD CPU interface Control register Status register Figure 15.1 HCAN Block Diagram Message Buffer Interface (MBI): The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.). Transmit messages are written by the CPU. For receive messages, the data received by the CDLC is stored automatically. Microprocessor Interface (MPI): The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN internal data, statuses, and so forth. CAN Data Link Controller (CDLC): The CDLC performs transmission and reception of messages conforming to the Bosch CAN Ver. 2.0B active standard (data frames, remote frames, error frames, overload frames, inter-frame spacing), as well as CRC checking, bus arbitration, and other functions. 502 15.1.3 Pin Configuration Table 15.1 shows the HCAN’s pins. When using the functions of these external pins, the pin function controller (PFC) must also be set in line with the HCAN settings. When using HCAN pins, settings must be made in the HCAN configuration mode (during initialization: MCR0 = 1 and GSR3 = 1). Table 15.1 HCAN Pins Name Abbreviation Input/Output Function HCAN transmit data pin HTxD Output CAN bus transmission pin HCAN receive data pin HRxD Input CAN bus reception pin A bus driver is necessary between the pins and the CAN bus. A Philips PCA82C250 compatible model is recommended. 503 15.1.4 Register Configuration Table 15.2 lists the HCAN’s registers. Table 15.2 HCAN Registers Name Abbreviation R/W Initial Value Address Access Size Master control register MCR H'01 H'FFFF E400 8 bits 16 bits R/W General status register GSR R H'0C H'FFFF E401 8 bits Bit configuration register BCR R/W H'0000 H'FFFF E402 8/16 bits Mailbox configuration register MBCR R/W H'0100 H'FFFF E404 8/16 bits Transmit wait register TXPR R/W H'0000 H'FFFF E406 8/16 bits Transmit wait cancel register TXCR R/W H'0000 H'FFFF E408 8/16 bits Transmit acknowledge register TXACK R/W H'0000 H'FFFF E40A 8/16 bits Abort acknowledge register ABACK R/W H'0000 H'FFFF E40C 8/16 bits Receive complete register RXPR R/W H'0000 H'FFFF E40E 8/16 bits Remote request register RFPR R/W H'0000 H'FFFF E410 8/16 bits Interrupt register IRR R/W H'0100 H'FFFF E412 8/16 bits Mailbox interrupt mask register MBIMR R/W H'FFFF H'FFFF E414 8/16 bits Interrupt mask register IMR R/W H'FEFF H'FFFF E416 8/16 bits Receive error counter REC R H'00 H'FFFF E418 8 bits 16 bits Transmit error counter TEC R H'00 H'FFFF E419 8 bits Unread message status register UMSR R/W H'0000 H'FFFF E41A 8/16 bits Local acceptance filter mask L LAFML R/W H'0000 H'FFFF E41C 8/16 bits Local acceptance filter mask H LAFMH R/W H'0000 H'FFFF E41E 8/16 bits 504 Table 15.2 HCAN Registers (cont) Name Abbreviation R/W Initial Value Address Access Size Message control 0 [1:8] MC0 [1:8] R/W Undefined H'FFFF E420 8/16 bits Message control 1 [1:8] MC1 [1:8] R/W Undefined H'FFFF E428 8/16 bits Message control 2 [1:8] MC2 [1:8] R/W Undefined H'FFFF E430 8/16 bits Message control 3 [1:8] MC3 [1:8] R/W Undefined H'FFFF E438 8/16 bits Message control 4 [1:8] MC4 [1:8] R/W Undefined H'FFFF E440 8/16 bits Message control 5 [1:8] MC5 [1:8] R/W Undefined H'FFFF E448 8/16 bits Message control 6 [1:8] MC6 [1:8] R/W Undefined H'FFFF E450 8/16 bits Message control 7 [1:8] MC7 [1:8] R/W Undefined H'FFFF E458 8/16 bits Message control 8 [1:8] MC8 [1:8] R/W Undefined H'FFFF E460 8/16 bits Message control 9 [1:8] MC9 [1:8] R/W Undefined H'FFFF E468 8/16 bits Message control 10 [1:8] MC10 [1:8] R/W Undefined H'FFFF E470 8/16 bits Message control 11 [1:8] MC11 [1:8] R/W Undefined H'FFFF E478 8/16 bits Message control 12 [1:8] MC12 [1:8] R/W Undefined H'FFFF E480 8/16 bits Message control 13 [1:8] MC13 [1:8] R/W Undefined H'FFFF E488 8/16 bits Message control 14 [1:8] MC14 [1:8] R/W Undefined H'FFFF E490 8/16 bits Message control 15 [1:8] MC15 [1:8] R/W Undefined H'FFFF E498 8/16 bits Message data 0 [1:8] MD0 [1:8] R/W Undefined H'FFFF E4B0 8/16 bits Message data 1 [1:8] MD1 [1:8] R/W Undefined H'FFFF E4B8 8/16 bits Message data 2 [1:8] MD2 [1:8] R/W Undefined H'FFFF E4C0 8/16 bits Message data 3 [1:8] MD3 [1:8] R/W Undefined H'FFFF E4C8 8/16 bits Message data 4 [1:8] MD4 [1:8] R/W Undefined H'FFFF E4D0 8/16 bits Message data 5 [1:8] MD5 [1:8] R/W Undefined H'FFFF E4D8 8/16 bits Message data 6 [1:8] MD6 [1:8] R/W Undefined H'FFFF E4E0 8/16 bits Message data 7 [1:8] MD7 [1:8] R/W Undefined H'FFFF E4E8 8/16 bits Message data 8 [1:8] MD8 [1:8] R/W Undefined H'FFFF E4F0 8/16 bits Message data 9 [1:8] MD9 [1:8] R/W Undefined H'FFFF E4F8 8/16 bits Message data 10 [1:8] MD10 [1:8] R/W Undefined H'FFFF E500 8/16 bits Message data 11 [1:8] MD11 [1:8] R/W Undefined H'FFFF E508 8/16 bits Message data 12 [1:8] MD12 [1:8] R/W Undefined H'FFFF E510 8/16 bits Message data 13 [1:8] MD13 [1:8] R/W Undefined H'FFFF E518 8/16 bits Message data 14 [1:8] MD14 [1:8] R/W Undefined H'FFFF E520 8/16 bits Message data 15 [1:8] MD15 [1:8] R/W Undefined H'FFFF E528 8/16 bits 505 15.2 Register Descriptions 15.2.1 Master Control Register (MCR) The master control register (MCR) is an 8-bit readable/writable register that controls the CAN interface. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 MCR7 — MCR5 — — MCR2 MCR1 MCR0 0 0 0 0 0 0 0 1 R/W — R/W — — R/W R/W R/W • Bit 7—HCAN Sleep Mode Release (MCR7): Enables or disables HCAN sleep mode release by bus operation. Bit 7: MCR7 Description 0 HCAN sleep mode release by CAN bus operation disabled 1 HCAN sleep mode release by CAN bus operation enabled (Initial value) • Bit 6—Reserved: This bit always reads 0. The write value should always be 0. • Bit 5—HCAN Sleep Mode (MCR5): Enables or disables HCAN sleep mode transition. Bit 5: MCR5 Description 0 HCAN sleep mode released 1 Transition to HCAN sleep mode enabled (Initial value) • Bits 4 and 3—Reserved: These bits always read 0. The write value should always be 0. • Bit 2—Message Transmission Method (MCR2): Selects the transmission method for transmit messages. Bit 2: MCR2 Description 0 Transmission order determined by message identifier priority (Initial value) 1 Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15) 506 • Bit 1—Halt Request (MCR1): Controls halting of the HCAN module. Bit 1: MCR1 Description 0 Normal operating mode 1 Halt mode transition request (Initial value) • Bit 0—Reset Request (MCR0): Controls resetting of the HCAN module. Bit 0: MCR0 Description 0 Normal operating mode (MCR0 = 0 and GSR3 = 0) [Setting condition] When 0 is written after an HCAN reset 1 Reset mode transition request (Initial value) In order for GSR3 to change from 1 to 0 after 0 is written to MCR0, time is required before the HCAN is internally reset. There is consequently a delay before GSR3 is cleared to 0 after MCR0 is cleared to 0. 15.2.2 General Status Register (GSR) The general status register (GSR) is an 8-bit readable/writable register that indicates the status of the CAN bus. Bit: 7 6 5 4 3 2 1 0 — — — — GSR3 GSR2 GSR1 GSR0 Initial value: 0 0 0 0 1 1 0 0 R/W: R R R R R R R R • Bits 7 to 4—Reserved: These bits always read 0. The write value should always be 0. • Bit 3—Reset Status Bit (GSR3): Indicates whether the HCAN module is in the normal operating state or the reset state. This bit cannot be modified. Bit 3: MCR3 Description 0 Normal operating state [Setting condition] After an HCAN internal reset 1 Configuration mode (Initial value) [Reset condition] MCR0-initiated reset state or sleep mode 507 • Bit 2—Message Transmission Status Flag (GSR2): Flag that indicates whether the module is currently in the message transmission period. The “message transmission period” is the period from the start of message transmission (SOF) until the end of a 3-bit intermission interval after EOF (End of Frame). This bit cannot be modified. Bit 2: GSR2 Description 0 Transmission in progress 1 [Reset condition] Idle period (Initial value) • Bit 1—Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning. This bit cannot be modified. it 1: GSR1 Description 0 [Reset condition] When TEC < 96 and REC < 96 or TEC ≥ 256 (Initial value) When TEC ≥ 96 or REC ≥ 96 1 • Bit 0—Bus Off Flag (GSR0): Flag that indicates the bus off state. This bit cannot be modified. Bit 0: GSR0 Description 0 [Reset condition] Recovery from bus off state When TEC ≥ 256 (bus off state) 1 15.2.3 (Initial value) Bit Configuration Register (BCR) The bit configuration register (BCR) is a 16-bit readable/writable register that is used to set CAN bit timing parameters and the baud rate prescaler. Bit: Initial value: R/W: Bit: Initial value: R/W: 508 15 14 13 12 11 10 9 8 BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 and 14—Re-synchronization Jump Width (SJW): These bits set the maximum bit synchronization range. Bit 15: BCR7 Bit 14: BCR6 Description 0 0 Maximum bit synchronization width = 1 time quantum 1 Maximum bit synchronization width = 2 time quanta 0 Maximum bit synchronization width = 3 time quanta 1 Maximum bit synchronization width = 4 time quanta 1 • Bits 13 to 8—Baud Rate Prescale (BRP): These bits are used to set the CAN bus baud rate. Bit 13: BCR5 Bit 12: BCR4 Bit 11: BCR3 Bit 10: BCR2 Bit 9: BCR1 Bit 8: BCR0 Description 0 0 0 0 0 0 2 × system clock 0 0 0 0 0 1 4 × system clock 0 0 0 0 1 0 6 × system clock ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ 1 1 1 1 1 1 1-bit time (Initial value) ⋅ ⋅ ⋅ 128 × system clock 1-bit time (8–25 time quanta) SYNC_SEG 1 PRSEG PHSEG1 TSEG1 (time segment 1)* 2–16 PHSEG2 TSEG2 (time segment 2)* Quantum 2–8 SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal bit edge transitions occur in this segment.) PRSEG: Segment for compensating for physical delay between networks. PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended when synchronization (re-synchronization) is established.) PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is shortened when synchronization (re-synchronization) is established.) Note: * The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1. Figure 15.2 Detailed Description of One Bit 509 HCAN bit rate calculation: Bit rate [b/s] = fCLK 2 × (BRP + 1) × (3 + TSEG1 + TSEG2) Note: f CLK = Pφ (peripheral clock (φ/2)) The BCR values are used for BRP, TSEG1, and TSEG2. BCR Setting Constraints TSEG1 > TSEG2 ≥ SJW (SJW = 1 to 4) 3 + TSEG1 + TSEG2 = 8 to 25 time quanta TSEG2 > B'001 (BRP = B'000000) TSEG2 > B'000 (BRP > B'000000) These constraints allow the setting range shown in table 15.3 for TSEG1 and TSEG2 in BCR. Table 15.3 Setting Range for TSEG1 and TSEG2 in BCR TSEG2 (BCR [14:12]) TSEG1 (BCR [11:8]) 001 010 011 100 101 110 111 0011 No Yes No No No No No 0100 Yes* Yes Yes No No No No 0101 Yes* Yes Yes Yes No No No 0110 Yes* Yes Yes Yes Yes No No 0111 Yes* Yes Yes Yes Yes Yes No 1000 Yes* Yes Yes Yes Yes Yes Yes 1001 Yes* Yes Yes Yes Yes Yes Yes 1010 Yes* Yes Yes Yes Yes Yes Yes 1011 Yes* Yes Yes Yes Yes Yes Yes 1100 Yes* Yes Yes Yes Yes Yes Yes 1101 Yes* Yes Yes Yes Yes Yes Yes 1110 Yes* Yes Yes Yes Yes Yes Yes 1111 Yes* Yes Yes Yes Yes Yes Yes Notes: The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1. * Setting is enabled except when BRP[13:8] = B'000000. 510 • Bit 7—Bit Sample Point (BSP): Sets the point at which data is sampled. Bit 7: BCR15 Description 0 Bit sampling at one point (end of time segment 1) 1 Bit sampling at three points (end of time segment 1, and 1 time quantum before and after) (Initial value) • Bits 6 to 4—Time Segment 2 (TSEG2): These bits are used to set the segment for correcting 1bit time error. A value from 2 to 8 can be set. Bit 6: BCR14 Bit 5: BCR13 Bit 4: BCR12 Description 0 0 0 Setting prohibited 1 TSEG2 (PHSEG2) = 2 time quanta 0 TSEG2 (PHSEG2) = 3 time quanta 1 TSEG2 (PHSEG2) = 4 time quanta 0 TSEG2 (PHSEG2) = 5 time quanta 1 TSEG2 (PHSEG2) = 6 time quanta 0 TSEG2 (PHSEG2) = 7 time quanta 1 TSEG2 (PHSEG2) = 8 time quanta 1 1 0 1 (Initial value) • Bits 3 to 0—Time Segment 1 (TSEG1): These bits are used to set the segment for absorbing output buffer, CAN bus, and input buffer delay. A value from 1 to 16 can be set. Bit 3: BCR11 Bit 2: BCR10 Bit 1: BCR9 Bit 0: BCR8 Description 0 0 0 0 Setting prohibited 0 0 0 1 Setting prohibited 0 0 1 0 Setting prohibited 0 0 1 1 TSEG1 (PRSEG + PHSEG1) = 4 time quanta 0 1 0 0 TSEG1 (PRSEG + PHSEG1) = 5 time quanta ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ 1 1 1 1 (Initial value) ⋅ ⋅ ⋅ TSEG1 (PRSEG + PHSEG1) = 16 time quanta 511 15.2.4 Mailbox Configuration Register (MBCR) The mailbox configuration register (MBCR) is a 16-bit readable/writable register that is used to set mailbox (buffer) transmission/reception. Bit: Initial value: R/W: Bit: 15 14 13 12 11 10 9 8 MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 — 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 MBCR9 MBCR8 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 to 9 and 7 to 0—Mailbox Setting Register (MBCR7 to 1, MBCR15 to 8): These bits set the polarity of the corresponding mailboxes (buffers). Bit x: MBCRx Description 0 Corresponding mailbox is set for transmission 1 Corresponding mailbox is set for reception (Initial value) • Bit 8—Reserved: This bit always reads 1. The write value should always be 1. 15.2.5 Transmit Wait Register (TXPR) The transmit wait register (TXPR) is a 16-bit readable/writable register that is used to set a transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait). Bit: Initial value: R/W: Bit: 15 14 13 12 11 10 9 8 TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 — 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 Initial value: R/W: 512 TXPR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 to 9 and 7 to 0—Transmit Wait Register (TXPR7 to 1, TXPR15 to 8): These bits set a CAN bus arbitration wait for the corresponding mailboxes (buffers). Bit x: TXPRx Description 0 Transmit message idle state in corresponding mailbox (Initial value) [Clearing condition] Message transmission completion and cancellation completion 1 Transmit message transmit wait in corresponding mailbox (CAN bus arbitration) • Bit 8—Reserved: This bit always reads 0. The write value should always be 0. 15.2.6 Transmit Wait Cancel Register (TXCR) The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls cancellation of transmit wait messages in mailboxes (buffers). Bit: Initial value: R/W: Bit: 15 14 13 12 11 10 9 8 TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 — 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 Initial value: R/W: TXCR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 to 9 and 7 to 0—Transmit Wait Cancel Register (TXCR7 to 1, TXCR15 to 8): These bits control cancellation of transmit wait messages in the corresponding HCAN mailboxes (buffers). Bit x: TXCRx Description 0 Transmit message cancellation idle state in corresponding mailbox (Initial value) [Clearing condition] Completion of TXPR clearing (when transmit message is canceled normally) 1 TXPR cleared for corresponding mailbox (transmit message cancellation) • Bit 8—Reserved: This bit always reads 0. The write value should always be 0. 513 15.2.7 Transmit Acknowledge Register (TXACK) The transmit acknowledge register (TXACK) is a 16-bit readable/writable register containing status flags that indicate normal transmission of mailbox (buffer) transmit messages. Bit: 15 TXACK7 Initial value: R/W: Bit: 14 13 TXACK6 TXACK5 12 11 TXACK4 TXACK3 10 9 8 TXACK2 TXACK1 — 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 to 9 and 7 to 0—Transmit Acknowledge Register (TXACK7 to 1, TXACK15 to 8): These bits indicate that a transmit message in the corresponding HCAN mailbox (buffer) has been transmitted normally. Bit x: TXACKx Description 0 [Clearing condition] Writing 1 1 Completion of message transmission for corresponding mailbox • Bit 8—Reserved: This bit always reads 0. The write value should always be 0. 514 (Initial value) 15.2.8 Abort Acknowledge Register (ABACK) The abort acknowledge register (ABACK) is a 16-bit readable/writable register containing status flags that indicate normal cancellation (aborting) of a mailbox (buffer) transmit messages. Bit: 15 ABACK7 Initial value: R/W: Bit: 14 13 ABACK6 ABACK5 12 11 ABACK4 ABACK3 10 9 8 ABACK2 ABACK1 — 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 to 9 and 7 to 0—Abort Acknowledge Register (ABACK7 to 1, ABACK15 to 8): These bits indicate that a transmit message in the corresponding mailbox (buffer) has been canceled (aborted) normally. Bit x: ABACKx Description 0 [Clearing condition] Writing 1 1 (Initial value) Completion of transmit message cancellation for corresponding mailbox • Bit 8—Reserved: This bit always reads 0. The write value should always be 0. 515 15.2.9 Receive Complete Register (RXPR) The receive complete register (RXPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of messages (data frame or remote frame) in mailboxes (buffers). In the case of remote frame reception, the corresponding bit in the remote request register (RFPR) is also set. Bit: 15 RXPR7 Initial value: R/W: Bit: 14 13 RXPR6 RXPR5 12 11 RXPR4 RXPR3 10 RXPR2 9 8 RXPR1 RXPR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 to 0—Receive Complete Register (RXPR7 to 0, RXPR15 to 8): These bits indicate that a receive message has been received normally in the corresponding mailbox (buffer). Bit x: RXPRx Description 0 [Clearing condition] Writing 1 1 516 (Initial value) Completion of message (data frame or remote frame) reception in corresponding mailbox 15.2.10 Remote Request Register (RFPR) The remote request register (RFPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of remote frames in mailboxes (buffers). When a bit in this register is set, the corresponding bit in the receive complete register (RXPR) is also set. Bit: Initial value: R/W: Bit: 15 14 13 12 11 10 9 8 RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 Initial value: R/W: RFPR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 to 0—Remote Request Register (RFPR7 to 0, RFPR15 to 8): These bits indicate that a remote frame has been received normally in the corresponding mailbox (buffer). Bit x: RFPRx Description 0 [Clearing condition] Writing 1 1 (Initial value) Completion of remote frame reception in corresponding mailbox 15.2.11 Interrupt Register (IRR) The interrupt register (IRR) is a 16-bit readable/writable register containing status flags for the various interrupt sources. Bit: Initial value: 15 14 13 12 11 10 9 8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R R R/W 7 6 5 4 3 2 1 0 — — — IRR12 — — IRR9 IRR8 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R/W R/W R/W: Bit: 517 • Bit 15—Overload Frame/Bus Off Recovery Interrupt Flag (IRR7): Status flag indicating that the HCAN has transmitted an overload frame or recovered from the bus off state. Bit 15: IRR7 Description 0 [Clearing condition] Writing 1 1 (Initial value) Overload frame transmission or recovery from bus off state [Setting conditions] Error active/error passive state • When overload frame is transmitted Bus off state • When 11 recessive bits is received 128 times (REC ≥ 128) • Bit 14—Bus Off Interrupt Flag (IRR6): Status flag indicating the bus off state caused by the transmit error counter. Bit 14: IRR6 Description 0 [Clearing condition] Writing 1 1 (Initial value) Bus off state caused by transmit error [Setting condition] When TEC ≥ 256 • Bit 13—Error Passive Interrupt Flag (IRR5): Status flag indicating the error passive state caused by the transmit/receive error counter. Bit 13: IRR5 Description 0 [Clearing condition] Writing 1 1 Error passive state caused by transmit/receive error [Setting condition] When TEC ≥ 128 or REC ≥ 128 518 (Initial value) • Bit 12—Receive Overload Warning Interrupt Flag (IRR4): Status flag indicating the error warning state caused by the receive error counter. Bit 12: IRR4 Description 0 [Clearing condition] Writing 1 1 (Initial value) Error warning state caused by receive error [Setting condition] When REC ≥ 96 • Bit 11—Transmit Overload Warning Interrupt Flag (IRR3): Status flag indicating the error warning state caused by the transmit error counter. Bit 11: IRR3 Description 0 [Clearing condition] Writing 1 1 (Initial value) Error warning state caused by transmit error [Setting condition] When TEC ≥ 96 • Bit 10—Remote Frame Request Interrupt Flag (IRR2): Status flag indicating that a remote frame has been received in a mailbox (buffer). Bit 10: IRR2 Description 0 [Clearing condition] Clearing of all bits in RFPR (remote request wait register) 1 (Initial value) Remote frame received and stored in mailbox [Setting conditions] When remote frame reception is completed. When corresponding MBIMR = 0. • Bit 9—Receive Message Interrupt Flag (IRR1): Status flag indicating that a mailbox (buffer) receive message has been received normally. Bit 9: IRR1 Description 0 [Clearing condition] Clearing of all bits in RXPR (receive complete register) when MBIMR is 0 (Initial value) 1 Data frame or remote frame received and stored in mailbox [Setting conditions] When data frame or remote frame reception is completed. When corresponding MBIMR = 0. 519 • Bit 8—Reset Interrupt Flag (IRR0): Status flag indicating that the HCAN module has been reset. This bit cannot be masked in the interrupt mask register (IMR). If this bit is not cleared after a power-on reset or a transition to software standby mode, the program will jump to the interrupt vector as soon as interrupts are enabled by the interrupt controller. Bit 8: IRR0 Description 0 [Clearing condition] Writing 1 1 Interrupt request by power-on reset or transition to software standby mode (OVR) (Initial value) [Setting condition] When reset processing is completed after power-on reset or software standby mode transition • Bits 7 to 5, 3, and 2—Reserved: These bits always read 0. The write value should always be 0. • Bit 4—Bus Operation Interrupt Flag (IRR12): Status flag indicating detection of a dominant bit due to bus operation when the HCAN module is in HCAN sleep mode. Bit 4: IRR12 Description 0 CAN bus idle state (Initial value) [Clearing condition] Writing 1 1 CAN bus operation in HCAN sleep mode [Setting condition] Bus operation (dominant bit detection) in HCAN sleep mode • Bit 1—Unread Interrupt Flag (IRR9): Status flag indicating that a receive message has been overwritten while still unread. Bit 1: IRR9 Description 0 [Clearing condition] Clearing of all bits in UMSR (unread message status register) (Initial value) 1 Unread message overwrite [Setting condition] When UMSR (unread message status register) is set 520 • Bit 0—Mailbox Empty Interrupt Flag (IRR8): Status flag indicating that the next transmit message can be stored in the mailbox. Bit 0: IRR8 Description 0 [Clearing condition] Writing 1 1 (Initial value) Transmit message has been transmitted or aborted, and new message can be stored [Setting condition] When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort 15.2.12 Mailbox Interrupt Mask Register (MBIMR) The mailbox interrupt mask register (MBIMR) is a 16-bit readable/writable register containing flags that enable or disable individual mailbox (buffer) interrupt requests. Bit: 15 MBIMR7 Initial value: R/W: Bit: 14 13 MBIMR6 MBIMR5 12 11 MBIMR4 MBIMR3 10 MBIMR2 9 8 MBIMR1 MBIMR0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 Initial value: R/W: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 to 0—Mailbox Interrupt Mask (MBIMR7 to 0, MBIMR15 to 8): Flags that enable or disable individual mailbox interrupt requests. Bit x: MBIMRx Description 0 [Transmitting] Interrupt request to CPU due to TXPR clearing [Receiving] Interrupt request to CPU due to RXPR setting 1 Interrupt requests to CPU disabled (Initial value) 521 15.2.13 Interrupt Mask Register (IMR) The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that enable or disable requests by individual interrupt sources. Bit: Initial value: 15 14 13 12 11 10 9 8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 — 1 1 1 1 1 1 1 0 R/W R/W R/W R/W R/W R/W R/W — 7 6 5 4 3 2 1 0 — — — IMR12 — — IMR9 IMR8 Initial value: 1 1 1 1 1 1 1 1 R/W: R R R R/W R R R/W R/W R/W: Bit: • Bit 15—Overload Frame/Bus Off Recovery Interrupt Mask (IMR7): Enables or disables overload frame/bus off recovery interrupt requests. Bit 15: IMR7 Description 0 Overload frame/bus off recovery interrupt request (OVR) by IRR7 to CPU enabled 1 Overload frame/bus off recovery interrupt request (OVR) by IRR7 to CPU disabled (Initial value) • Bit 14—Bus Off Interrupt Mask (IMR6): Enables or disables bus off interrupt requests caused by the transmit error counter. Bit 14: IMR6 Description 0 Bus off interrupt request (ERS) by IRR6 to CPU enabled 1 Bus off interrupt request (ERS) by IRR6 to CPU disabled (Initial value) • Bit 13—Error Passive Interrupt Mask (IMR5): Enables or disables error passive interrupt requests caused by the transmit/receive error counter. Bit 13: IMR5 Description 0 Error passive interrupt request (ERS) by IRR5 to CPU enabled 1 Error passive interrupt request (ERS) by IRR5 to CPU disabled (Initial value) 522 • Bit 12—Receive Overload Warning Interrupt Mask (IMR4): Enables or disables error warning interrupt requests caused by the receive error counter. Bit 12: IMR4 Description 0 REC error warning interrupt request (OVR) by IRR4 to CPU enabled 1 REC error warning interrupt request (OVR) by IRR4 to CPU disabled (Initial value) • Bit 11—Transmit Overload Warning Interrupt Mask (IMR3): Enables or disables error warning interrupt requests caused by the transmit error counter. Bit 11: IMR3 Description 0 TEC error warning interrupt request (OVR) by IRR3 to CPU enabled 1 TEC error warning interrupt request (OVR) by IRR3 to CPU disabled (Initial value) • Bit 10—Remote Frame Request Interrupt Mask (IMR2): Enables or disables remote frame reception interrupt requests. Bit 10: IMR2 Description 0 Remote frame reception interrupt request (OVR) by IRR2 to CPU enabled 1 Remote frame reception interrupt request (OVR) by IRR2 to CPU disabled (Initial value) • Bit 9—Receive Message Interrupt Mask (IMR1): Enables or disables message reception interrupt requests. Bit 9: IMR1 Description 0 Message reception interrupt request (RM) by IRR1 to CPU enabled 1 Message reception interrupt request (RM) by IRR1 to CPU disabled (Initial value) • Bit 8—Reserved: This bit always reads 0. The write value should always be 0. • Bits 7 to 5, 3, and 2—Reserved: These bits always read 1. The write value should always be 1. 523 • Bit 4—Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to bus operation in sleep mode. Bit 4: IMR12 Description 0 Bus operation interrupt request (OVR) by IRR12 to CPU enabled 1 Bus operation interrupt request (OVR) by IRR12 to CPU disabled (Initial value) • Bit 1—Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite interrupt requests. Bit 1: IMR9 Description 0 Unread message overwrite interrupt request (OVR) by IRR9 to CPU enabled 1 Unread message overwrite interrupt request (OVR) by IRR9 to CPU disabled (Initial value) • Bit 0—Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt requests. Bit 0: IMR8 Description 0 Mailbox empty interrupt request (SLE) by IRR8 to CPU enabled 1 Mailbox empty interrupt request (SLE) by IRR8 to CPU disabled (Initial value) 15.2.14 Receive Error Counter (REC) The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating the number of receive message errors on the CAN bus. The count value is stipulated in the CAN protocol. 524 Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R 15.2.15 Transmit Error Counter (TEC) The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter indicating the number of transmit message errors on the CAN bus. The count value is stipulated in the CAN protocol. Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R 15.2.16 Unread Message Status Register (UMSR) The unread message status register (UMSR) is a 16-bit readable/writable register containing status flags that indicate, for individual mailboxes (buffers), that a received message has been overwritten by a new receive message before being read. When an unread message is overwritten by a new receive message, the old data is lost. Bit: Initial value: R/W: Bit: 15 14 13 12 11 10 9 8 UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 UMSR9 UMSR8 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 to 0—Unread Message Status Flags (UMSR7 to 0, UMSR15 to 8): Status flags indicating that an unread receive message has been overwritten. Bit x: UMSRx Description 0 [Clearing condition] Writing 1 1 (Initial value) Unread receive message is overwritten by a new message [Setting condition] When a new message is received before RXPR is cleared 525 15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) The local acceptance filter masks (LAFML, LAFMH) are 16-bit readable/writable registers that filter receive messages to be stored in the receive-only mailbox (MC0, MD0) according to the identifier. In these registers, consist of LAFMH15: MSB to LAFMH5: LSB are 11 standard/extended identifier bits, and LAFMH1: MSB to LAFML0: LSB are 18 extended identifier bits. LAFML Bit: Initial value: R/W: Bit: 15 14 13 12 11 10 9 8 LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 LAFML9 LAFML8 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 — — — LAFMH Bit: LAFMH7 Initial value: R/W: Bit: LAFMH6 LAFMH5 LAFMH1 LAFMH0 0 0 0 0 0 0 0 0 R/W R/W R/W R R R R/W R/W 7 6 5 4 3 2 1 0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • LAFMH Bits 7 to 0 and 15 to 13—11-Bit Identifier Filter (LAFMH7 to 5, LAFMH15 to 8): Filter mask bits for the first 11 bits of the receive message identifier (for both standard and extended identifiers). 526 Bit x: LAFMHx Description 0 Stored in MC0 and MD0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Initial value) 1 Stored in MC0 and MD0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier • LAFMH Bits 12 to 10—Reserved: These bits always read 0. The write value should always be 0. • LAFMH Bits 9 and 8, LAFML bits 15 to 0—18-Bit Identifier Filter (LAFMH1, 0, LAFML15 to 0): Filter mask bits for the 18 bits of the receive message identifier (extended). Bit x: LAFMHx LAFMLx Description 0 Stored in MC0 and MD0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Initial value) 1 Stored in MC0 and MD0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier 15.2.18 Message Control (MC0 to MC15) The message control register sets (MC0 to MC15) consist of eight 8-bit readable/writable registers (MCx[1] to MCx[8]). The HCAN has 16 sets of these registers (MC0 to MC15). The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). MCx [1] Bit: Initial value: 7 6 5 4 3 2 1 0 DLC3 DLC2 DLC1 DLC0 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: MCx [2] R/W: 527 MCx [3] Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 RTR IDE R/W: MCx [4] R/W: MCx [5] Bit: STD_ID2 STD_ID1 STD_ID0 Initial value: R/W: EXD_ID17 EXD_ID16 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MCx [6] Bit: STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Initial value: R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MCx [7] Bit: EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value: R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MCx [8] Bit: EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value: R/W: 528 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W • MCx[1] Bits 7 to 4—Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). • MCx[1] Bits 3 to 0: Data Length Code (DLC3 to 0): These bits indicate the required length of data frames and remote frames. Bit 3: DLC3 Bit 2: DLC2 Bit 1: DLC1 Bit 0: DLC0 Description 0 0 0 0 Data length = 0 bytes 1 Data length = 1 byte 0 Data length = 2 bytes 1 Data length = 3 bytes 0 Data length = 4 bytes 1 Data length = 5 bytes 0 Data length = 6 bytes 1 Data length = 7 bytes * Data length = 8 bytes 1 1 0 1 1 * * *: Don’t care • MCx[2] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). • MCx[3] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). • MCx[4] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). • MCx[6] Bits 7 to 0: Standard Identifier (STD_ID10 to STD_ID3) MCx[5] Bits 7 to 5: Standard Identifier (STD_ID2 to STD_ID0) These bits set the identifier (standard identifier) of data frames and remote frames. Standard identifier SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE SRR STD_IDxx Figure 15.3 Standard Identifier 529 • MCx[5] Bit 4: Remote Transmission Request (RTR): Used to distinguish between data frames and remote frames. Bit 4: RTR Description 0 Data frame 1 Remote frame • MCx[5] Bit 3: Identifier Extension (IDE): Used to distinguish between the standard format and extended format of data frames and remote frames. Bit 3: IDE Description 0 Standard format 1 Extended format • MCx[5] Bit 2—Reserved: The initial value of this bit is undefined; it must be initialized (by writing 0 or 1). • MCx[5] Bits 1 and 0: Extended Identifier (EXD_ID17, EXD_ID16) MCx[8] Bits 7 to 0: Extended Identifier (EXD_ID15 to EXD_ID8) MCx[7] Bits 7 to 0: Extended Identifier (EXD_ID7 to EXD_ID0) These bits set the identifier (extended identifier) of data frames and remote frames. Extended Identifier IDE ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 EXD_IDxx ID4 ID3 ID2 ID1 ID0 RTR EXD_IDxx Figure 15.4 Extended Identifier 530 R1 ID7 ID6 ID5 15.2.19 Message Data (MD0 to MD15) The message data register sets (MD0 to MD15) consist of eight 8-bit readable/writable registers (MDx[1] to MDx[8]). The HCAN has 16 sets of these registers (MD0 to MD15). The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). MDx[1] Message Data 1 Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: MDx[2] Message Data 2 Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: MDx[3] Message Data 3 Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: MDx[4] Message Data 4 Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: MDx[5] Message Data 5 Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: 531 MDx[6] Message Data 6 Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: MDx[7] Message Data 7 Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: MDx[8] Message Data 8 Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: 532 15.3 Operation 15.3.1 Hardware Reset and Software Reset There are two ways of resetting the HCAN: Hardware reset, software reset Hardware Reset (power-on reset or hardware/software standby): The MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR within the HCAN are automatically set and initialization is performed. At the same time, all internal registers are initialized. However mailbox (RAM) contents are not initialized. A flowchart of this reset is shown in figure 15.5. Software Reset: In normal operation, HCAN is initialized by setting the MCR reset request bit (MCR0) in MCR. With this kind of reset, if the CAN controller is performing a communication operation (transmission or reception), the initialization state is not entered until the message has been completed. During initialization, the reset state bit (GSR3) in GSR is set. In this kind of initialization, the error counters (TEC and REC) are initialized but other registers and RAM are not. A flowchart of this reset is shown in figure 15.6. 533 Hardware reset MCR0 = 1 (automatic) IRR0 = 1 (automatic) GSR3 = 1 (automatic) Initialization of HCAN module Bit configuration mode Period in which BCR, MBCR, etc., are initialized Clear IRR0 HCAN port setting BCR setting MBCR setting Mailbox initialization Message transmission method initialization MCR0 = 0 GSR3 = 0? No Yes IMR setting (interrupt mask setting) MBIMR setting (interrupt mask setting) MC[x] setting (receive identifier setting) LAFM setting (receive identifier mask setting) GSR3 = 0 & 11 recessive bits received? No Yes CAN bus communication enabled Figure 15.5 Hardware Reset Flowchart 534 : Settings by user : Processing by hardware MCR0 = 1 Bus idle? No Yes GSR3 = 1 (automatic) Initialization of REC and TEC only Correction IRR clearing HCAN port setting BCR setting MBCR setting Mailbox initialization Message transmission method initialization OK? No Yes MCR0 = 0 GSR3 = 0? No Yes IMR setting MBIMR setting MC[x] setting LAFM setting OK? Correction No Yes GSR3 = 0 & 11 recessive bits received? No Yes CAN bus communication enabled : Settings by user : Processing by hardware Figure 15.6 Software Reset Flowchart 535 15.3.2 Initialization after a Hardware Reset After a hardware reset, the following initialization processing should be carried out: 1. 2. 3. 4. 5. 6. IRR0 clearing HCAN pin port settings Bit rate setting Mailbox transmit/receive settings Mailbox (RAM) initialization Message transmission method setting These initial settings must be made while the HCAN is in bit configuration mode. Configuration mode is a state in which the reset request bit (MCR0) in the master control register (MCR) is 1 and the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is exited by clearing the reset request bit in MCR to 0; when MCR0 is cleared to 0, the HCAN automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up sequence then begins, and communication with the CAN bus is possible as soon as the sequence ends. The power-up sequence consists of the detection of 11 consecutive recessive bits. IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. HCAN Pin Port Settings: HCAN pin port settings must be made during or before bit configuration. Refer to the section 18, Pin Function Controller (PFC), for details of the setting method. Bit Rate Settings: As bit rate settings, a baud rate setting and bit timing setting must be made each time a CAN node begins communication. The baud rate and bit timing settings are made in the bit configuration register (BCR). Notes: 1. BCR can be written to at all times, but should only be modified in configuration mode. 2. Settings should be made so that all CAN controllers connected to the CAN bus have the same baud rate and bit width. 3. Limits for the settable variables (TSEG1, TSEG2, BRP, sample point, and SJW) are shown in table 15.4. 536 Table 15.4 BCR Setting Limits Name Abbreviation Min. Value Max. Value Unit Time segment 1 TSEG1 4 16 TQ Time segment 2 TSEG2 2 8 TQ Baud rate prescaler BRP 2 128 System clock Sample point SAM 1 3 Point Re-synchronization jump width SJW 1 4 TQ Settable Variable Limits • The bit width consists of the total of the settable time quanta (TQ). TQ (number of system clocks) is determined by the baud rate prescaler (BRP). TQ = (2*(BRP + 1))/(fCLK) fCLK = Pφ • The minimum value of SJW is stipulated in the CAN specifications. 4 ≥ SJW ≥ 1 • The minimum value of TSEG1 is stipulated in the CAN specifications. TSEG1 ≥ TSEG2 • The minimum value of TSEG2 is stipulated in the CAN specifications. TSEG2 ≥ (1 + SJW) The following formula is used to calculate the baud rate. Bit rate [b/s] = fCLK 2 × (BRP + 1) × (3 + TSEG1 + TSEG2) Note: f CLK = Pφ (peripheral clock: φ/2] The BCR values are used for BRP, TSEG1, and TSEG2. 537 Example: With a 1 Mb/s baud rate and a 40 MHz input clock: 1 Mb/s = 20 MHz 2 × (0 + 1) × (3 + 4 + 3) Set Values Actual Values f CLK 40 MHz/2 — BRP 0 (B'000000) System clock × 2 TSEG1 4 (B'0100) 5TQ TSEG2 3 (B'011) 4TQ Mailbox Transmit/Receive Settings: HCAN0 and HCAN1 each have 16 mailboxes. Mailbox 0 is receive-only, while mailboxes 1 to 15 can be set for transmission or reception. Mailboxes that can be set for transmission or reception must be designated either for transmission use or for reception use before communication begins. The Initial status of mailboxes 1 to 15 is for transmission (while mailbox 0 is for reception only). Mailbox transmit/receive settings are not initialized by a software reset. • Setting for transmission Transmit mailbox setting (mailboxes 1 to 15) Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding mailbox for transmission use. After a reset, mailboxes are initialized for transmission use, so this setting is not necessary. • Setting for reception Transmit/receive mailbox setting (mailboxes 1 to 15) Setting a bit to 1 in the mailbox configuration register (MBCR) designates the corresponding mailbox for reception use. When setting mailboxes for reception, to improve message transmission efficiency, high-priority messages should be set in low-to-high mailbox order (priority order: mailbox 1 (MCx[1]) > mailbox 15 (MCx[15])). • Receive-only mailbox (mailbox 0) No setting is necessary, as this mailbox is always used for reception. Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings: After power is supplied, all registers and RAM (message control/data, control registers, status registers, etc.) are initialized. Message control/data (MCx[x], MDx[x]) only are in RAM, and so their values are undefined. Initial values must therefore be set in all the mailboxes (by writing 0s or 1s). Setting the Message Transmission Method: Either of the following message transmission methods can be selected with the message transmission method bit (MCR2) in the master control register (MCR): 538 1. Transmission order determined by mailbox number priority 2. Transmission order determined by message identifier priority When the mailbox number priority method is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order: mailbox 1 > 15). CAN bus arbitration is then carried out for the messages in the transmit buffer, and message transmission is performed when the bus is acquired. When the message identifier priority method is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority set in the message identifier (MCx[5] to MCx[8]) is stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. When the TXPR bit is set, internal arbitration is performed again, and the highest-priority message is found and stored in the transmit buffer. 15.3.3 Transmit Mode Message transmission is performed using mailboxes 1 to 15. The transmission procedure is described below, and a transmission flowchart is shown in figure 15.7. 1. Initialization (after hardware reset only) a. b. c. d. e. f. Clearing of IRR0 bit in interrupt register (IRR) HCAN pin port settings Bit rate settings Mailbox transmit/receive settings Mailbox initialization Message transmission method setting 2. Interrupt and transmit data settings a. Interrupt setting b. Arbitration field setting c. Control field setting d. Data field setting 3. Message transmission and interrupts a. Message transmission wait b. Message transmission completion and interrupt c. Message transmission abort d. Message retransmission 539 Initialization (after Hardware Reset Only): These settings should be made while the HCAN is in bit configuration mode. 1. IRR0 clearing The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. 2. HCAN pin port settings To prevent erroneous identification of CAN bus data, HCAN pin port settings should be made first. See section 15.3.2, HCAN Pin Port Settings, and section 18, Pin Function Controller, for details. 3. Bit rate settings Set values relating to the CAN bus communication speed and re-synchronization. See section 15.3.2, Bit Rate Settings, for details. 4. Mailbox transmit/receive settings Mailbox transmit/receive settings should be made in advance. A total of 30 mailbox can be set for transmission or reception (mailboxes 1 to 15 in HCAN0 and HCAN1). To set a mailbox for transmission, clear the corresponding bit to 0 in the mailbox configuration register (MBCR). See section 15.3.2, Mailbox Transmit/Receive Settings, for details. 5. Mailbox initialization As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to the mailboxes. See section 15.3.2, Mailbox Transmit/Receive Settings, for details. 6. Message transmission method setting Set the transmission method for mailboxes designated for transmission. The following two transmission methods can be used. See section 15.3.2, Setting the Message Transmission Method, for details. a. Transmission order determined by message identifier priority b. Transmission order determined by mailbox number priority 540 Initialization (after hardware reset only) • IRR0 clearing • HCAN port setting • BCR setting • MBCR setting • Mailbox initialization • Message transmission method setting Interrupt settings Transmit data setting • Arbitration field setting • Control field setting • Data field setting Message transmission wait • TXPR setting No Bus idle? Yes Message transmission GSR2 = 0 (during transmission only) Transmission completed? No Yes Yes IMR8 = 1? No TXACK = 1? No Interrupt to CPU Yes Clear TXACK Clear IRR8 : Settings by user End of transmission : Processing by hardware Figure 15.7 Transmission Flowchart 541 Interrupt and Transmit Data Settings: When mailbox initialization is finished, CPU interrupt source settings and data settings must be made. Interrupt source settings are made in the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR), while transmit data settings are made by writing the following three kinds of necessary data in the message control registers (MCx[1] to MCx[8]) and message data registers (MDx[1] to MDx[8]). 1. CPU interrupt source settings Transmission acknowledge and transmission abort acknowledge interrupts can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR). Interrupt register (IRR) interrupts can be masked in the interrupt mask register (IMR). 2. Arbitration field In the arbitration field, the 11-bit identifier (STD_ID0 to STD_ID10) and RTR bit (standard format) or 29-bit identifier (STD_ID0 to STD_ID10, EXT_ID0 to EXT_ID17) and IDE.RTR bit (extended format) are set. The registers to be set are MCx[5] to MCx[8]. 3. Control field In the control field, the byte length of the data to be transmitted is set in DLC0 to DLC3. The register to be set is MCx[1]. 4. Data field In the data field, the data to be transmitted is set in byte units in the range of 0 to 8 bytes. The registers to be set are MDx[1] to MDx[8]. The number of bytes in the data actually transmitted depends on the data length code (DLC) in the control field. If a value exceeding the value set in DLC is set in the data field, only the number of bytes set in DLC will actually be transmitted. 542 Message Transmission and Interrupts: 1. Message transmission wait If message transmission is to be performed after completion of the message control (MCx[1] to MCx[8]) and message data (MDx[1] to MDx[8]) settings, transmission is started by setting the corresponding mailbox transmit wait bit (TXPR1 to TXPR15) to 1 in the transmit wait register (TXPR). The following two transmission methods can be used: a. Transmission order determined by mailbox number priority b. Transmission order determined by message identifier priority When the message identifier priority method is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order: mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit buffer, and message transmission is performed when the bus is acquired. When the mailbox number priority method is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority set in the message identifier (MCx[5] to MCx[8]) is stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. When the TXPR bit is set, internal arbitration is performed again, the highest-priority message is found and stored in the transmit buffer, CAN bus arbitration is carried out in the same way, and message transmission is performed when the transmission right is acquired. 2. Message transmission completion and interrupt When a message is transmitted error-free using the above procedure, The corresponding acknowledge bit (TXACK1 to TXACK15) in the transmit acknowledge register (TXACK) and transmit wait bit (TXPR1 to TXPR15) in the transmit wait register (TXPR) are automatically initialized. If the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. 3. Message transmission cancellation Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the bit for the corresponding mailbox (TXCR1 to TXCR15) to 1 in the transmit cancel register (TXCR). When cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (ABACK). An interrupt can be requested. If the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. 543 However, a transmit wait message cannot be canceled at the following times: a. During internal arbitration or CAN bus arbitration b. During data frame or remote frame transmission Also, transmission cannot be canceled by clearing the transmit wait register (TXPR). Figure 15.8 shows a flowchart of transmit message cancellation. 4. Message retransmission If transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically: a. CAN bus arbitration failure (failure to acquire the bus) b. Error during transmission (bit error, stuff error, CRC error, frame error, ACK error) 544 Message transmit wait TXPR setting Set TXCR bit corresponding to message to be canceled Cancellation possible? No Yes Message not sent Clear TXCR, TXPR ABACK = 1 IRR8 = 1 IMR8 = 1? Completion of message transmission TXACK = 1 Clear TXCR, TXPR IRR8 = 1 Yes No Interrupt to CPU Clear TXACK Clear ABACK Clear IRR8 : Settings by user End of transmission/transmission cancellation : Processing by hardware Figure 15.8 Transmit Message Cancellation Flowchart 545 15.3.4 Receive Mode Message reception is performed using mailboxes 0 and 1 to 15. The reception procedure is described below, and a reception flowchart is shown in figure 15.9. 1. Initialization (after hardware reset only) a. Clearing of IRR0 bit in interrupt register (IRR) b. HCAN pin port settings c. Bit rate settings d. Mailbox transmit/receive settings e. Mailbox initialization 2. Interrupt and receive message settings a. Interrupt setting b. Arbitration field setting c. Local acceptance filter mask (LAFM) settings 3. Message reception and interrupts a. Message reception CRC check b. Data frame reception c. Remote frame reception d. Unread message reception 546 Initialization (after Hardware Reset Only): These settings should be made while the HCAN is in bit configuration mode. 1. IRR0 clearing The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. 2. HCAN pin port settings To prevent erroneous identification of CAN bus data, HCAN pin port settings should be made first. See section 15.3.2, HCAN Pin Port Settings, and section 18, Pin Function Controller, for details. 3. Bit rate settings Set values relating to the CAN bus communication speed and re-synchronization. See section 15.3.2, Bit Rate Settings, for details. 4. Mailbox transmit/receive settings Each channel has one receive-only mailbox (mailbox 0) and 15 mailboxes that can be set for reception. Thus a total of 32 mailboxes can be used for reception. To set a mailbox for reception, set the corresponding bit to 1 in the mailbox configuration register (MBCR). The initial setting for mailboxes is 0, designating transmission use. See section 15.3.2, Mailbox Transmit/Receive Settings, for details. 5. Mailbox (RAM) initialization As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to the mailboxes. See section 15.3.2, Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings, for details. 547 Initialization • IRR0 clearing • HCAN port setting : Settings by user • BCR setting • MBCR setting : Processing by hardware • Mailbox (RAM) initialization Interrupt settings Receive data setting • Arbitration field setting • Local acceptance filter settings Message reception (Match of identifier in mailbox?) No Yes Same RXPR = 1? Yes Unread message No Data frame? No Yes RXPR IRR1 = 1 IMR1 = 1? No RXPR, RFPR = 1 IRR2 = 1, IRR1 = 1 Yes IMR2 = 1? RXPR = 1? Interrupt to CPU No No RXPR = 1? Interrupt to CPU Yes Yes Message control read Message data read Message control read Message data read Clear PXPR Clear RXPR, RFPR Transmission of data frame corresponding to remote frame End of reception Figure 15.9 Reception Flowchart 548 Yes No Interrupt and Receive Message Settings: When mailbox initialization is finished, CPU interrupt source settings and receive message specifications must be made. Interrupt source settings are made in the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). To receive a message, the identifier must be set in advance in the message control (MCx[1] to MCx[8]) for the receiving mailbox. When a message is received, all the bits in the receive message identifier are compared, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox 0 (MC0[x], MD0[x]) has a local acceptance filter mask (LAFM) that allows Don’t Care settings to be made. 1. CPU interrupt source settings When transmitting, transmission acknowledge and transmission abort acknowledge interrupts can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR). When receiving, data frame and remote frame receive wait interrupts can be masked. Interrupt register (IRR) interrupts can be masked in the interrupt mask register (IMR). 2. Arbitration field setting In the arbitration field, the identifier (STD_ID0 to STD_ID10, EXT_ID0 to EXT_ID17) of the message to be received is set. If all the bits in the set identifier do not match, the message is not stored in a mailbox. Example: Mailbox 1 010_1010_1010 (standard identifier) Only one kind of message identifier can be received by MB1 Identifier 1: 010_1010_1010 3. Local acceptance filter mask (LAFM) setting The local acceptance filter mask is provided for mailbox 0 (MC0[x], MD0[x]) only, enabling a Don’t Care specification to be made for all bits in the received identifier. This allows various kinds of messages to be received. Example: Mailbox 0 LAFM 010_1010_1010 (standard identifier) 000_0000_0011 (0: Care, 1: Don’t Care) A total of four kinds of message identifiers can be received by MB0 Identifier 1: 010_1010_1000 Identifier 2: 010_1010_1001 Identifier 3: 010_1010_1010 Identifier 4: 010_1010_1011 549 Message Reception and Interrupts: 1. Message reception CRC check When a message is received, a CRC check is performed automatically (by hardware). If the result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether or not the message can be received. 2. Data frame reception If the received message is confirmed to be error-free by the CRC check, etc., the identifier in the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive message are compared, and if a complete match is found, the message is stored in the mailbox. The message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (RXPR0 to RXPR15) is set in the receive complete register (RXPR). However, when a mailbox 0 LAFM comparison is carried out, even if the identifier matches, the mailbox comparison sequence does not end at that point, but continues with mailbox 1 and then the remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received by another mailbox (however, the same message cannot be stored in more than one of mailboxes 1 to 15). If the corresponding bit (MBIMR0 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the receive message interrupt mask (IMR1) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. 3. Remote frame reception Two kinds of messages—data frames and remote frames—can be stored in mailboxes. A remote frame differs from a data frame in that the remote reception request bit (RTR) in the message control register (MC[x]5) and the data field are 0 bytes. The data length to be returned in a data frame must be stored in the data length code (DLC) in the control field. When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote request wait register (RFPR). If the corresponding bit (MBIMR0 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. 550 4. Unread message reception When the identifier in a mailbox matches a receive message, the message is stored in the mailbox. If a message overwrite occurs before the CPU reads the message, the corresponding bit (UMSR0 to UMSR15) is set in the unread message register (UMSR). In overwriting of an unread message, when a new message is received before the corresponding bit in the receive complete register (RXPR) has been cleared, the unread message register (UMSR) is set. If the unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Figure 15.10 shows a flowchart of unread message overwriting. Unread message overwrite UMSR = 1 IRR9 = 1 IMR9 = 1? Yes No Interrupt to CPU Clear IRR9 Message control/message data read : Settings by user End : Processing by hardware Figure 15.10 Unread Message Overwrite Flowchart 551 15.3.5 HCAN Sleep Mode The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state to reduce current dissipation. Figure 15.11 shows a flowchart of the HCAN sleep mode. MCR5 = 1 Bus idle? No Yes Initialize TEC and REC Bus operation? No Yes IRR12 = 1 IMR12 = 1? No CPU interrupt Yes Sleep mode clearing method MCR7 = 0? No (automatic) Yes (manual) MCR5 = 0 Clear sleep mode? No Yes MCR5 = 0 11 recessive bits? Yes CAN bus communication possible No : Settings by user : Processing by hardware Figure 15.11 HCAN Sleep Mode Flowchart 552 HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle. Either of the following methods of clearing HCAN sleep mode can be selected by making a setting in the MCR7 bit. 1. Clearing by software 2. Clearing by CAN bus operation Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus communication is enabled again. Clearing by Software: Clearing by software is performed by having the CPU write 0 to MCR5. Clearing by CAN Bus Operation: Clearing by CAN bus operation occurs automatically when the CAN bus performs an operation and this change is detected. In this case, the first message is not received in the message box; normal reception starts with the second message. When a change is detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. 553 15.3.6 HCAN Halt Mode The HCAN halt mode is provided to enable mailbox settings to be changed without performing an HCAN hardware or software reset. Figure 15.12 shows a flowchart of the HCAN halt mode. MCR1 = 1 GSR2 = 1? (Wait until transmission is completed if in progress) Bus idle? No Yes MBCR setting MCR1 = 0 : Settings by user CAN bus communication possible : Processing by hardware Figure 15.12 HCAN Halt Mode Flowchart HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until the bus becomes idle. HCAN halt mode is cleared by clearing MCR1 to 0. 554 15.3.7 Interrupt Interface There are 12 interrupt sources for each HCAN channel. Four independent interrupt vectors are assigned to each channel. Table 15.5 lists the HCAN interrupt sources. With the exception of the power-on reset processing vector (IRR0), these sources can be masked. Masking is implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). Table 15.5 HCAN Interrupt Sources Channel IPR Bits Vector Vector Number IRR Bit HCAN IPRL (11 to 8) ERS 220 (initial value) OVR RM0 SLE0 221 222 223 Description IRR5 Error passive interrupt (TEC ≥ 128 or REC ≥ 128) IRR6 Bus off interrupt (TEC ≥ 256) IRR0 Power-on reset processing interrupt IRR2 Remote frame reception interrupt IRR3 Error warning interrupt (TEC ≥ 96) IRR4 Error warning interrupt (REC ≥ 96) IRR7 Overload frame transmission interrupt/bus off recovery interrupt (11 recessive bits × 128 times) IRR9 Unread message overwrite interrupt IRR12 HCAN sleep mode CAN bus operation interrupt IRR1 Mailbox 0 message reception interrupt IRR1 Mailbox 1 to 15 message reception interrupt IRR8 Message transmission/cancellation interrupt 555 15.3.8 DMAC Interface The DMAC can be activated by reception of a message in HCAN’s mailbox 0. When DMAC transfer ends after DMAC activation has been set, the RXPR0 and RFPR0 flags are acknowledge signal automatically. An interrupt request due to a receive interrupt from the HCAN cannot be sent to the CPU in this case. Figure 15.13 shows a DMAC transfer flowchart. DMAC initialization • Activation source setting • Source/destination address settings • Transfer count setting • Interrupt setting Message reception in HCAN’s mailbox 0 DMAC activation End of DMAC transfer? No Yes DMAC transfer end bit setting RXPR and RFPR clearing DMAC interrupt enabled? No Yes Interrupt to CPU Clear DMAC interrupt flag : Settings by user End : Processing by hardware Figure 15.13 DMAC Transfer Flowchart 556 15.4 CAN Bus Interface A bus transceiver IC is necessary to connect the SH7052F/SH7053F/SH7054F chip to a CAN bus. A Philips PCA82C250 transceiver IC, or compatible device, is recommended. Figure 15.14 shows a sample connection diagram. 124 Ω SH7052F/SH7053F/SH7054F Vcc PCA82C250 RS Vcc HRxD RxD CANH HTxD TxD CANL N.C. Vref CAN bus GND 124 Ω Figure 15.14 Example of High-Speed Interface Using PCA82C250 557 15.5 Usage Notes 1. Reset The HCAN is reset by a power-on reset, and in hardware standby mode and software standby mode. All the registers are initialized in a reset, but mailboxes (message control (MCx[x])/message data (MDx[x]) are not. However, after powering on, mailboxes (message control (MCx[x])/message data (MDx[x]) are initialized, and their values are undefined. Therefore, mailbox initialization must always be carried out after a power-on reset or a transition to hardware standby mode or software standby mode. The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. As this bit cannot be masked in the interrupt mask register (IMR), if HCAN interrupt enabling is set in the interrupt controller without clearing the flag, an HCAN interrupt will be initiated immediately. IRR0 should therefore be cleared during initialization. 2. HCAN sleep mode The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by bus operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode release. Also note that the reset status bit (GSR3) in the general status register (GSR) is set in sleep mode. 3. Port settings 4. 5. 6. 7. Port settings must be made with the PFC before the HCAN begins CAN bus communication. When using the two HCAN pins in a 2-channel/32-buffer configuration (wired-AND), set the other two HCAN pin locations as non-HCAN. DMAC activation When the DMAC is activated automatically by reception of a message in HCAN0’s mailbox 0 (receive-only mailbox), a signal is not sent to the INTC. Interrupts When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8.2.1) is not set by reception completion, transmission completion, or transmission cancellation for the set mailboxes. Error counters In the case of error active and error passive, REC and TEC normally count up and down. In the bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96 during the count, IRR4 and GSR1 are set, and if REC reaches 128, IRR7 is set. Register access Byte or word access can be used on all HCAN registers. Longword access cannot be used. 8. Register initialization in standby modes All HCAN registers are initialized in hardware standby mode and software standby mode. 558 Section 16 A/D Converter 16.1 Overview The SH7052F/SH7053F/SH7054F includes a 10-bit successive-approximation A/D converter, with software selection of up to 32 analog input channels. The A/D converter is composed of two independent modules, A/D0 and A/D1. A/D0 comprises three groups and A/D1 comprises one group. Module Analog Groups Channels A/D0 Analog group 0 AN0 to AN3 Analog group 1 AN4 to AN7 Analog group 2 AN8 to AN11 Analog group 3 AN12 to AN15 A/D1 16.1.1 Features The features of the A/D converter are summarized below. • 10-bit resolution 16 input channels (A/D0: 12 channels, A/D1: 4 channels) • High-speed conversion Conversion time: minimum 13.4 µs per channel (when φ = 40 MHz) • Two conversion modes Single mode: A/D conversion on one channel Scan mode: cotinuous scan mode, single-cycle scan mode (AN0 to AN3, AN4 to AN7, AN8 to AN11, AN12 to AN15) Continuous conversion on 1 to 12 channels (A/D0) Continuous conversion on 1 to 4 channels (A/D1) • Sixteen 10-bit A/D data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. • Two sample-and-hold circuits A sample-and-hold circuit is built into each A/D converter module (A/D0 and A/D1), simplifying the configuration of external analog input circuitry. • A/D conversion interrupts and DMA function supported 559 An A/D conversion interrupt request (ADI) can be sent to the CPU at the end of A/D conversion (ADI0: A/D0 interrupt request; ADI1: A/D1 interrupt request). Also, the DMAC can be activated by an ADI interrupt request. • Two kinds of conversion activation Software or external trigger (ADTER0, ATU-II (ITVRR2A)) can be selected (A/D0) Software or external trigger (ADTGR0, ATU-II (ITVRR2B)) can be selected (A/D1) 560 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the A/D converter. Analog multiplexer AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Sample-andhold circuit + – Comparator ADCR0 ADDR0 to ADDR1 ADTRGR0 10-bit D/A AVss ADCSR0 AVcc AVref Successiveapproximation register Module data bus Bus interface A/D0 Internal data bus A/D conversion control circuit ADI0 interrupt signal ATU0 ADTRG0 AN12 AN13 AN14 AN15 Analog multiplexer Sample-andhold circuit + – Comparator ADCR1 ADTRGR1 ADDR12 to ADDR15 ADCSR1 10-bit D/A Successiveapproximation register Module data bus Bus interface A/D1 Internal data bus A/D conversion control circuit ADI1 interrupt signal ATU0 ADCR0, ADCR1: A/D control registers 0 and 1 ADCSR0, ADCSR1: A/D control/status registers 0 and 1 ADDR0 to ADDR15: A/D data registers 0 to 15 ADTRGR0: A/D trigger register0 Figure 16.1 A/D Converter Block Diagram 561 16.1.3 Pin Configuration Table 16.1 summarizes the A/D converter’s input pins. There are 16 analog input pins, AN0 to AN15. The 12 pins AN0 to AN11 are A/D0 analog inputs, divided into three groups: AN0 to AN3 (group 0), AN4 to AN7 (group 1), and AN8 to AN11 (group 2). The 4 pins AN12 to AN15 are A/D1 analog inputs, which is one group: AN12 to AN15 (group 3). The ADTRG0 pin is used to provide A/D conversion start timing from off-chip. When a low level is applied to one of these pins, A/D0 or A/D1 starts conversion. The AVCC and AVSS pins are power supply voltage pins for the analog section in A/D converter modules A/D0 and A/D1. The AVref pin is the A/D converter module A/D0 and A/D1 reference voltage pin. To maintain chip reliability, ensure that AVCC = 5 V ±0.5 V and AVSS = VSS during normal operation, and never leave the AVCC and AVSS pins open, even when the A/D converter is not being used. The voltage applied to the analog input pins should be in the range AV SS ≤ ANn ≤ AVref . 562 Table 16.1 A/D Converter Pins Pin Name Abbreviation I/O Function Analog power supply pin AVCC Input A/D0, A/D1 analog section power supply Analog ground pin AVSS Input A/D0, A/D1 analog section ground and reference voltage Analog reference power supply pin AVref Input A/D0, A/D1 analog section reference voltage Analog input pin 0 AN0 Input A/D0 analog inputs 0 to 3 (analog group 0) Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input Analog input pin 8 AN8 Input Analog input pin 9 AN9 Input Analog input pin 10 AN10 Input Analog input pin 11 AN11 Input Analog input pin 12 AN12 Input Analog input pin 13 AN13 Input Analog input pin 14 AN14 Input Analog input pin 15 AN15 Input A/D conversion trigger input pin 0 ADTRG0 Input A/D0 analog inputs 4 to 7 (analog group 1) A/D0 analog inputs 8 to 11 (analog group 2) A/D1 analog inputs 12 to 15 (analog group 3) A/D0 and A/D1 A/D conversion trigger input 563 16.1.4 Register Configuration Table 16.2 summarizes the A/D converter’s registers. Table 16.2 A/D Converter Registers Name Abbreviation R/W Initial Value Address Access Size* 1 A/D data register 0 (H/L) ADDR0 (H/L) R H'0000 H'FFFFF800 8, 16 A/D data register 1 (H/L) ADDR1 (H/L) R H'0000 H'FFFFF802 8, 16 A/D data register 2 (H/L) ADDR2 (H/L) R H'0000 H'FFFFF804 8, 16 A/D data register 3 (H/L) ADDR3 (H/L) R H'0000 H'FFFFF806 8, 16 A/D data register 4 (H/L) ADDR4 (H/L) R H'0000 H'FFFFF808 8, 16 A/D data register 5 (H/L) ADDR5 (H/L) R H'0000 H'FFFFF80A 8, 16 A/D data register 6 (H/L) ADDR6 (H/L) R H'0000 H'FFFFF80C 8, 16 A/D data register 7 (H/L) ADDR7 (H/L) R H'0000 H'FFFFF80E 8, 16 A/D data register 8 (H/L) ADDR8 (H/L) R H'0000 H'FFFFF810 8, 16 A/D data register 9 (H/L) ADDR9 (H/L) R H'0000 H'FFFFF812 8, 16 A/D data register 10 (H/L) ADDR10 (H/L) R H'0000 H'FFFFF814 8, 16 A/D data register 11 (H/L) ADDR11 (H/L) R H'0000 H'FFFFF816 8, 16 A/D data register 12 (H/L) ADDR12 (H/L) R H'0000 H'FFFFF820 8, 16 A/D data register 13 (H/L) ADDR13 (H/L) R H'0000 H'FFFFF822 8, 16 A/D data register 14 (H/L) ADDR14 (H/L) R H'0000 H'FFFFF824 8, 16 A/D data register 15 (H/L) ADDR15 (H/L) R H'0000 H'FFFFF826 8, 16 H'00 H'FFFFF818 8, 16 H'0F H'FFFFF819 8, 16 H'FF H'FFFFF76E 8 H'00 H'FFFFF838 8, 16 A/D control/status register 0 ADCSR0 R/(W)* A/D control register 0 ADCR0 R/W A/D trigger register 0 ADTRGR0 R/W 2 2 A/D control/status register 1 ADCSR1 R/(W)* A/D control register 1 ADCR1 R/W H'0F H'FFFFF839 8, 16 A/D trigger register 1 ADTRGR1 R/W H'FF H'FFFFF72E 8 Notes: Register accesses consist of 6 or 7 cycles for byte access and 12 or 13 cycles for word access. 1. A 16-bit access must be made on a word boundary. 2. Only 0 can be written to bit 7, to clear the flag. 564 16.2 Register Descriptions 16.2.1 A/D Data Registers 0 to 15 (ADDR0 to ADDR15) A/D data registers 0 to 15 (ADDR0 to ADDR15) are 16-bit read-only registers that store the results of A/D conversion. There are 31 registers, corresponding to analog inputs 0 to 15 (AN0 to AN15). The ADDR registers are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 6 5 4 3 2 1 0 ADDRnH (upper byte) AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 ADDRnL (lower byte) AD1 AD0 — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R (n = 0 to 15) The A/D converter converts analog input to a 10-bit digital value. The upper 8 bits of this data are stored in the upper byte of the ADDR corresponding to the selected channel, and the lower 2 bits in the lower byte of that ADDR. Only the most significant 2 bits of the ADDR lower byte data are valid. Table 16.3 shows correspondence between the analog input channels and A/D data registers. 565 Table 16.3 Analog Input Channels and A/D Data Registers Analog Input Channel A/D Data Register Analog Input Channel A/D Data Register AN0 ADDR0 AN8 ADDR8 AN1 ADDR1 AN9 ADDR9 AN2 ADDR2 AN10 ADDR10 AN3 ADDR3 AN11 ADDR11 AN4 ADDR4 AN12 ADDR12 AN5 ADDR5 AN13 ADDR13 AN6 ADDR6 AN14 ADDR14 AN7 ADDR7 AN15 ADDR15 16.2.2 A/D Control/Status Register 0 (ADCSR0) A/D control/status register 0 (ADCSR0) is 8-bit readable/writable register whose function includes selection of the A/D conversion mode for A/D0. ADCSR0 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ADF ADIE ADM1 ADM0 CH3 CH2 CH1 CH0 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written, to clear the flag. • Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7: ADF Description 0 Indicates that A/D0 is performing A/D conversion, or is in the idle state (Initial value) [Clearing conditions] 1 • When ADF is read while set to 1, then 0 is written to ADF • When the DMAC is activated by ADI0 Indicates that A/D0 has finished A/D conversion, and the digital value has been transferred to ADDR [Setting conditions] • • 566 Single mode: When A/D conversion ends Scan mode: When all set A/D conversions end The operation of the A/D converter after ADF is set to 1 differs between single mode and scan mode. In single mode, after the A/D converter transfers the digital value to ADDR, ADF is set to 1 and the A/D converter enters the idle state. In scan mode (continuous scanning), after all the set conversions end ADF is set to 1 and conversion is continued. For example, in the case of 12-channel scanning, ADF is set to 1 immediately after the end of conversion for AN8 to AN11 (group 2). In scan mode (single-cycle scanning), after all the set analog conversions end ADF is set to 1 and conversion is terminated. For example, in the case of 12-channel scanning, ADF is set to 1 immediately after the end of conversion for AN0 to AN11. • Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the A/D interrupt (ADI). To prevent incorrect operation, ensure that the ADST bit in A/D control registers 0 and 1 (ADCR0) is cleared to 0 before switching the operating mode. Bit 6: ADIE Description 0 A/D interrupt (ADI0) is disabled 1 A/D interrupt (ADI0) is enabled (Initial value) When A/D conversion ends and the ADF bit is set to 1, an A/D0 or A/D1 A/D interrupt (ADI0, ADI1) will be generated If the ADIE bit is 1. ADI0 and ADI1 are cleared by clearing ADF or ADIE to 0. • Bits 5 and 4: A/D Mode 1 and 0 (ADM1, ADM0): These bits select the A/D conversion mode from single mode, 4-channel scan mode, 8-channel scan mode, and 12-channel scan mode. To prevent incorrect operation, ensure that the ADST bit in A/D control registers 1 and 0 (ADCR1, ADCR0) is cleared to 0 before switching the operating mode. Bit 5: ADM1 Bit 4: ADM0 Description 0 0 Single mode 1 4-channel scan mode (analog groups 0, 1, 2) 0 8-channel scan mode (analog groups 0, 1) 1 12-channel scan mode (analog groups 0, 1, 2) 1 (Initial value) When ADM1 and ADM0 are set to 00, single mode is set. In single mode, operation ends after A/D conversion has been performed once on the analog channels selected with bits CH3 to CH0 in ADCSR. 567 When ADM1 and ADM0 are set to 01, 4-channel scan mode is set. In scan mode, A/D conversion is performed continuously on a number of channels. The channels on which A/D conversion is to be performed in scan mode are set with bits CH3 to CH0 in ADCSR0. In 4channel scan mode, conversion is performed continuously on the channels in one of analog groups 0 (AN0 to AN3), 1 (AN4 to AN7), 2 (AN8 to AN11). When the ADCS bit is cleared to 0, selecting scanning of all channels within the group (AN0 to AN3, AN4 to AN7, AN8 to AN11), conversion is performed continuously, once only for each channel within the group, and operation stops on completion of conversion for the last (highest-numbered) channel. When ADM1 and ADM0 are set to 10, 8-channel scan mode is set. In 8-channel scan mode, conversion is performed continuously on the 8 channels in analog groups 0 (AN0 to AN3) and 1 (AN4 to AN7). When the ADCS bit is cleared to 0, selecting scanning of all channels within the groups (AN0 to AN7), conversion is performed continuously, once only for each channel within the groups, and operation stops on completion of conversion for the last (highestnumbered) channel. When ADM1 and ADM0 are set to 11, 12-channel scan mode is set. In 12-channel scan mode, conversion is performed continuously on the 12 channels in analog groups 0 (AN0 to AN3), 1 (AN4 to AN7), and 2 (AN8 to AN11). When the ADCS bit is cleared to 0, selecting scanning of all channels within the groups (AN0 to AN11), conversion is performed continuously, once only for each channel within the groups, and operation stops on completion of conversion for the last (highest-numbered) channel. For details of the operation in single mode and scan mode, see section 16.4, Operation. • Bits 3 to 0—Channel Select 3 to 0 (CH3 to CH0): These bits, together with the ADM1 and ADM0 bits, select the analog input channels. To prevent incorrect operation, ensure that the ADST bit in A/D control registers 1 and 0 (ADCR1, ADCR0) is cleared to 0 before changing the analog input channel selection. 568 Analog Input Channels Bit 3: CH3 Bit 2: CH2 Bit 1: CH1 Bit 0: CH0 0 0 0 1 1 0 1 1 0* 0 1 Single Mode 4-Channel Scan Mode A/D0 A/D0 0 AN0 (Initial value) AN0 1 AN1 AN0, AN1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 0 AN4 AN4 1 AN5 AN4, AN5 0 AN6 AN4 to AN6 1 AN7 AN4 to AN7 0 AN8 AN8 1 AN9 AN8, AN9 0 AN10 AN8 to AN10 1 AN11 AN8 to AN11 Note: * Must be cleared to 0. Analog Input Channels 8-Channel Scan Mode Bit 3: Bit 2: Bit 1: Bit 0: CH3 CH2 CH1 CH0 A/D0 A/D0 0 0 0 1 1 0 1 1 0* 1 0 1 12-Channel Scan Mode 0 AN0, AN4 AN0, AN4, AN8 1 AN0, AN1, AN4, AN5 AN0, AN1, AN4, AN5, AN8, AN9 0 AN0 to AN2, AN4 to AN6 AN0 to AN2, AN4 to AN6, AN8 to AN10 1 AN0 to AN7 AN0 to AN11 0 AN0, AN4 AN0, AN4, AN8 1 AN0, AN1, AN4, AN5 AN0, AN1, AN4, AN5, AN8, AN9 0 AN0 to AN2, AN4 to AN6 AN0 to AN2, AN4 to AN6, AN8 to AN10 1 AN0 to AN7 AN0 to AN11 0 Reserved* 2 AN0, AN4, AN8 1 AN0, AN1, AN4, AN5, AN8, AN9 0 AN0 to AN2, AN4 to AN6, AN8 to AN10 1 AN0 to AN11 Notes: 1. Must be cleared to 0. 2. These modes are provided for future expansion, and cannot be used at present. 569 16.2.3 A/D Control Registers 0 and 1 (ADCR0, ADCR1) A/D control registers 0 and 1 (ADCR0 and ADCR1) are 8-bit readable/writable registers that control the start of A/D conversion and selects the operating clock for A/D0 and A/D1. ADCR0 and ADCR1 are initialized to H'0F by a power-on reset, and in hardware standby mode and software standby mode. Bits 3 to 0 of ADCR0 and ADCR1 are reserved. These bits cannot be written to, and always return 1 if read. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TRGE CKS ADST ADCS — — — — 0 0 0 0 1 1 1 1 R/W R/W R/W R/W R R R R • Bit 7—Trigger Enable (TRGE): Enables or disables triggering of A/D conversion by external input or the ATU-II. Bit 7: TRGE Description 0 A/D conversion triggering by external input or ATU-II is disabled 1 A/D conversion triggering by external input or ATU-II is enabled (Initial value) For details of external or ATU-II trigger selection, see section 16.2.5, A/D Trigger Register 0 and 1. When ATU triggering is selected, clear bit 7 of registers ADTRGR0 and ADTRGR1 to 0. When external triggering is selected, upon input of a low level to the ADTRG0 pin after TRGE has been set to 1, the A/D converter detects the low level, and sets the ADST bit to 1 in ADCR. The same operation is subsequently performed when 1 is written in the ADST bit by software. External triggering of A/D conversion is only enabled when the ADST bit is cleared to 0. When external triggering is used, the low level input to the ADTRG0 pin must be at least 1.5 Pφ clock cycles in width. For details, see section 16.4.4, External Triggering of A/D Converter. 570 • Bit 6—Clock Select (CKS): Selects the A/D conversion time. A/D conversion is executed in a maximum of 532 states when CKS is 0, and a maximum of 268 states when 1. To prevent incorrect operation, ensure that the ADST bit A/D control registers 0 and 1 (ADCR0 and ADCR1) is cleared to 0 before changing the A/D conversion time. For details, see section 16.4.3, Analog Input Sampling and A/D Conversion Time. Bit 6: CKS Description 0 Conversion time = 532 states (maximum) 1 Conversion time = 268 states (maximum) (Initial value) • Bit 5—A/D Start (ADST): Starts or stops A/D conversion. A/D conversion is started when ADST is set to 1, and stopped when ADST is cleared to 0. Bit 5: ADST Description 0 A/D conversion is stopped 1 A/D conversion is being executed (Initial value) [Clearing conditions] • • Single mode: Automatically cleared to 0 when A/D conversion ends Scan mode: Automatically cleared to 0 on completion of one round of conversion on all set channels (single-cycle scan) Note that the operation of the ADST bit differs between single mode and scan mode. In single mode, ADST is automatically cleared to 0 when A/D conversion ends on one channel. In scan mode (continuous scan), when all conversions have ended for the selected analog inputs, ADST remains set to 1 in order to start A/D conversion again for all the channels. Therefore, in scan mode (continuous scan), the ADST bit must be cleared to 0, stopping A/D conversion, before changing the conversion time or the analog input channel selection. However, in scan mode (single-cycle scan), the ADST bit is automatically cleared to 0, stopping A/D conversion, when one round of conversion ends on all the set channels. Ensure that the ADST bit in ADCR0 and ADCR1 is cleared to 0 before switching the operating mode. Also, make sure that A/D conversion is stopped (ADST is cleared to 0) before changing A/D interrupt enabling (bit ADIE in ADCSR0 and ADCSR1), the A/D conversion time (bit CKS in ADCR0 and ADCR1), the operating mode (bits ADM1 and ADM0 in ADSCR0 and ADCSR1), or the analog input channel selection (bits CH3 to CH0 in ADCSR0 and ADCSR1). The A/D data register contents will not be guaranteed if these changes are made while the A/D converter is operating (ADST is set to 1). 571 • Bit 4—A/D Continuous Scan (ADCS): Selects either single-cycle scan or continuous scan in scan mode. This bit is valid only when scan mode is selected. See section 16.4.2, Scan Mode, for details. Bit 4: ADCS Description 0 Single-cycle scan 1 Continuous scan (Initial value) • Bits 3 to 0—Reserved: These bits are always read as 1, and should only be written with 1. 16.2.4 A/D Control/Status Register 1 (ADCSR1) A/D control/status register 1 (ADCSR1) is an 8-bit readable/writable register whose functions include selection of the A/D conversion mode for A/D1. ADCSR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ADF ADIE ADM1 ADM0 CH3 CH2 CH1 CH0 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written, to clear the flag. • Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7: ADF Description 0 Indicates that A/D1 is performing A/D conversion, or is in the idle state (Initial value) [Clearing conditions] 1 • When ADF is read while set to 1, then 0 is written to ADF • When the DMAC is activated by ADI2 Indicates that A/D1 has finished A/D conversion, and the digital value has been transferred to ADDR [Setting conditions] • • Single mode: When A/D conversion ends Scan mode: When all set A/D conversions end The operation of the A/D converter after ADF is set to 1 differs between single mode and scan mode. 572 In single mode, after the A/D converter transfers the digital value to ADDR, ADF is set to 1 and the A/D converter enters the idle state. In scan mode (continuous scanning), after all the set conversions end ADF is set to 1 and conversion is continued. For example, in the case of 4channel scanning, ADF is set to 1 immediately after the end of conversion for AN12 to AN15 (group 3). In scan mode (single-cycle scanning), after all the set analog conversions end ADF is set to 1 and conversion is terminated. For example, in the case of 4-channel scanning, ADF is set to 1 immediately after the end of conversion for AN12 to AN15. • Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the A/D interrupt (ADI). To prevent incorrect operation, ensure that the ADST bit in A/D control register 2 (ADCR2) is cleared to 0 before switching the operating mode. Bit 6: ADIE Description 0 A/D interrupt (ADI1) is disabled 1 A/D interrupt (ADI1) is enabled (Initial value) When A/D conversion ends and the ADF bit in ADCSR2 is set to 1, an A/D1 A/D interrupt (ADI1) will be generated If the ADIE bit is 1. ADI1 is cleared by clearing ADF or ADIE to 0. • Bits 5 and 4: A/D Mode 1 and 0 (ADM1, ADM0): These bits select the A/D conversion mode from single mode, 4-channel scan mode, 8-channel scan mode, 12-channel scan mode. To prevent incorrect operation, ensure that the ADST bit in A/D control register 1, 0 (ADCR1, 0) is cleared to 0 before switching the operating mode. Bit 5: ADM1 Bit 4: ADM0 Description 0 0 Single mode 1 4-channel scan mode (analog groups 3) 0 Reserved 1 Reserved 1 (Initial value) When ADM1 and ADM0 are set to 00, single mode is set. In single mode, operation ends after A/D conversion has been performed once on the analog channels selected with bits CH3 to CH0 in ADCSR. When ADM1 and ADM0 are set to 01, 4-channel scan mode is set. In scan mode, A/D conversion is performed continuously on a number of channels. The channels on which A/D conversion is to be performed in scan mode are set with bits CH3 to CH0 in ADCSR1. In 4channel scan mode, conversion is performed continuously on the channels in one of analog groups 3 (AN12 to AN15). 573 When the ADCS bit is cleared to 0, selecting scanning of all channels within the group (AN12 to AN15), conversion is performed continuously, once only for each channel within the group, and operation stops on completion of conversion for the last (highest-numbered) channel. For details of the operation in single mode and scan mode, see section 16.4, Operation. • Bits 3 to 0—Channel Select 3 to 0 (CH3 to CH0): These bits, together with the ADM1 and ADM0 bits, select the analog input channels. To prevent incorrect operation, ensure that the ADST bit in A/D control register 1 (ADCR1) is cleared to 0 before changing the analog input channel selection. Analog Input Channels Bit: Bit: Bit: Bit: Single Mode 4-Channel Scan Mode CH3 CH2 CH1 CH0 A/D1 A/D1 1 1 0 0 AN12 (Initial value) AN12 1 AN13 AN12, AN13 0 AN14 AN12 to AN14 1 AN15 AN12 to AN15 0* 0* 1 Notes 1. These bits must be set to 0. 2. Other modes, which are not described in this table are, for future use. Be sure not to use the modes. 574 16.2.5 A/D Trigger Registers 0 and 1 (ADTRGR0, ADTRGR1) The A/D trigger registers (ADTRGR0 and ADTRGR1) are 8-bit readable/writable registers that select the A/D0 and A/D1 triggers. Either external pin (ADTRG0) or ATU-II (ATU-II interval timer A/D conversion request) triggering can be selected. ADTRG0 and ADTRG1 are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized in software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 EXTRG — — — — — — — 1 1 1 1 1 1 1 1 R/W R R R R R R R • Bit 7—Trigger Enable (EXTRG): Selects external pin input (ADTRG0) or the ATU-II interval timer A/D conversion request. Bit 7: EXTRG Description 0 A/D conversion is triggered by the ATU-II channel 0 interval timer A/D conversion request 1 A/D conversion is triggered by external pin input (ADTRG) (Initial value) In order to select external triggering or ATU-II triggering, the TGRE bit in ADCR0 and ADCR1 must be set to 1. For details, see section 16.2.3, A/D Control Registers 0 and 1. • Bits 6 to 0—Reserved: These bits are always read as 1, and should only be written with 1. 575 16.3 CPU Interface A/D data registers 0 to 15 (ADDR0 to ADDR15) are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, the upper and lower bytes must be read separately. To prevent the data being changed between the reads of the upper and lower bytes of an A/D data register, the lower byte is read via a temporary register (TEMP). The upper byte can be read directly. Data is read from an A/D data register as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When performing byte-size reads on an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. If a word-size read is performed on an A/D data register, reading is performed in upper byte, lower byte order automatically. Figure 16.2 shows the data flow for access to an A/D data register. Upper-byte read CPU (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) Lower-byte read CPU (H'40) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) Figure 16.2 A/D Data Register Access Operation (Reading H'AA40) 576 16.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. There are two kinds of scan mode: continuous and single-cycle. In single mode, conversion is performed once on one specified channel, then ends. In continuous scan mode, A/D conversion continues on one or more specified channels until the ADST bit is cleared to 0. In single-cycle scan mode, A/D conversion ends after being performed once on one or more channels. 16.4.1 Single Mode Single mode, should be selected when only one A/D conversion on one channel is required. Single mode is selected by setting the ADM1 and ADM0 bits in the A/D control/status register (ADSCR) to 00. When the ADST bit in the A/D control register (ADCR) is set to 1, A/D conversion is started in single mode. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. When conversion ends, the ADF flag in ADCSR is set to 1. If the ADIE bit in ADCSR is also 1, an ADI interrupt is requested. To clear the ADF flag, first read ADF when set to 1, then write 0 to ADF. If the DMAC is activated by the ADI interrupt, ADF is cleared automatically. An example of the operation when analog input channel 1 (AN1) is selected and A/D conversion is performed in single mode is described next. Figure 16.3 shows a timing diagram for this example. 1. Single mode is selected (ADM1 = ADM0 = 0), input channel AN1 is selected (CH3 = CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred to ADDR1. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine is started. 5. The routine reads ADF set to 1, then writes 0 to ADF. 6. The routine reads and processes the conversion result (ADDR1). 7. Execution of the A/D interrupt handling routine ends. After this, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated. 577 Set* ADIE A/D conver- Set* sion starts Set* ADST Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion (1) Idle A/D conversion (2) Idle ADDR0 Read conversion result ADDR1 A/D conversion result (1) Read conversion result A/D conversion result (2) ADDR2 ADDR3 Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 16.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 578 16.4.2 Scan Mode Scan mode is useful for monitoring analog inputs in a group of one or more channels. Scan mode is selected for A/D0 by setting the ADM1 and ADM0 bits in A/D control/status register 0 or 1 (ADSCR0) to 01 (4-channel scan mode), or 11 (12-channel scan mode). For A/D1, scan mode is selected by setting the ADM1 and ADM0 bits in A/D control/status register 1 (ADCSR1) to 01 (4-channel scan mode). When the ADCS bit is cleared to 0 and the ADST bit is set to 1 in the A/D control register (ADCR), single-cycle scanning is performed. When the ADCS bit is set to 1 and the ADST bit is set to 1, continuous scanning is performed. In scan mode, A/D conversion is performed in low-to-high analog input channel number order (AN0, AN1 ... AN11, AN12, AN13 ... AN15). In single-cycle scanning, the ADF bit in ADCSR is set to 1 when conversion has been performed once on all the set channels, and the ADST bit is automatically cleared to 0. In continuous scanning, the ADF bit in ADCSR is set to 1 when conversion ends on all the set channels. To stop A/D conversion, write 0 to the ADST bit. If the ADIE bit in ADCSR is set to 1 when ADF is set to 1, an ADI interrupt (ADI0, ADI1, or ADI2) is requested. To clear the ADF flag, first read ADF when set to 1, then write 0 to ADF. If the DMAC is activated by the ADI interrupt, ADF is cleared to 0 automatically. An example of the operation when analog inputs 0 to 11 (AN0 to AN11) are selected and A/D conversion is performed in single-cycle scan mode is described below. Figure 16.4 shows the operation timing for this example. 1. 12-channel scan mode is selected (ADM1 = 1, ADM0 = 1), single-cycle scan mode is selected (ADCS = 0), analog input channels AN0 to AN11 are selected (CH3 = 0, CH2 = 0, CH1 = 1, CH0 = 1), and A/D conversion is started. 2. When conversion of the first channel (AN0) is completed, the result is transferred to ADDR0. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the 12th channel (AN11). 4. When conversion is completed for all the selected channels (AN0 to AN11), the ADF flag is set to 1, the ADST bit is cleared to 0 automatically, and A/D conversion stops. If the ADIE bit is 1, an ADI interrupt is requested after A/D conversion ends. 579 An example of the operation when analog inputs 0 to 2 and 4 to 6 (AN0 to AN2 and AN4 to AN6) are selected and A/D conversion is performed in 8-channel scan mode is described below. Figure 16.5 shows the operation timing. 1. 8-channel scan mode is selected (ADM1 = 1, ADM0 = 0) continuous scan mode is selected (ADCS = 1), analog input channels AN0 to AN2 and AN4 to AN6 are selected (CH3 = 0, CH2 = 0, CH1 = 1, CH0 = 0), and A/D conversion is started. 2. When conversion of the first channel (AN0) is completed, the result is transferred to ADDR0. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. Conversion of the fourth channel (AN4) starts automatically. 5. Conversion proceeds in the same way through the sixth channel (AN6) 6. When conversion is completed for all the selected channels (AN0 to AN2 and AN4 to AN6), the ADF flag is set to 1. If the ADIE bit is also 1, an ADI interrupt is requested. 7. Steps 2 to 6 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After this, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). 580 Continuous A/D conversion Set* Clear* ADST Clear* ADF State of channel 0 (AN0) State of channel 1 (AN1) Idle Idle A/D conversion (1) Idle A/D conversion (2) State of channel 2 (AN2) Idle State of channel 9 (AN9) Idle State of channel 10 (AN10) Idle State of channel 11 (AN11) Idle Idle Idle A/D conversion (3) Idle A/D conversion (9) Idle A/D conversion (10) Idle A/D conversion (11) ADDR0 A/D conversion result (0) ADDO1 A/D conversion result (1) ADDR2 A/D conversion result (2) ADDR9 A/D conversion result (9) ADDR10 A/D conversion result (10) ADDR11 A/D conversion result (11) Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 16.4 Example of A/D Converter Operation (Scan Mode (Single-Cycle Scan), Channels AN0 to AN11 Selected) 581 Continuous A/D conversion Set*1 Clear*1 ADST Clear*1 ADF State of channel 0 (AN0) State of channel 1 (AN1) Idle A/D conversion (1) Idle Idle State of channel 3 (AN3) Idle State of channel 4 (AN4) Idle State of channel 5 (AN5) Idle State of channel 6 (AN6) Idle State of channel 7 (AN7) Idle ADDR1 ADDR2 Idle A/D conversion (7) Idle A/D conversion (2) State of channel 2 (AN2) ADDR0 Idle Idle A/D conversion (3) Idle A/D conversion (8) Idle A/D conversion (9) Idle A/D conversion (4) A/D conversion (10) Idle A/D conversion (5) *2 Idle A/D conversion (11) Idle A/D conversion (6) A/D conversion result (1) Idle A/D conversion result (7) A/D conversion result (2) A/D conversion result (8) A/D conversion result (3) A/D conversion result (9) ADDR3 ADDR4 ADDR5 ADDR6 A/D conversion result (4) A/D conversion result (10) A/D conversion result (5) A/D conversion result (6) ADDR7 Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. Figure 16.5 Example of A/D Converter Operation (Scan Mode (Continuous Scan), Channels AN0 to AN2 and AN4 to AN6 Selected) 582 16.4.3 Analog Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit in A/D0, A/D1, and A/D2. The A/D converter samples the analog input at time t D (A/D conversion start delay time) after the ADST bit is set to 1, then starts conversion. Figure 16.6 shows the A/D conversion timing. The A/D conversion time (t CONV) includes tD and the analog input sampling time (tSPL). The length of t D is not fixed, since it includes the time required for synchronization of the A/D conversion operation. The total conversion time therefore varies within the ranges shown in table 16.4. In scan mode, the tCONV values given in table 16.4 apply to the first conversion. In the second and subsequent conversions, tCONV is fixed at 512 states when CKS = 0 or 256 states when CKS = 1. Table 16.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max Unit A/D conversion start delay time tD 20 — 34 12 — 18 States (φ base) Input sampling time t SPL — 128 — — 64 — A/D conversion time t CONV 518 — 532 262 — 268 583 A/D conversion time (tCONV) A/D conversion start delay time (tD) Analog input sampling time (tSPL) Write cycle A/D synchronization time (6 states) (up to 28 states) Pφ Address Internal write signal ADST write timing Analog input sampling signal A/D converter Idle Sample-and-hold A/D conversion ADF End of A/D conversion Figure 16.6 A/D Conversion Timing 584 16.4.4 External Triggering of A/D Converter A/D conversion can be externally triggered. To activate the A/D converter with an external trigger, first set the pin functions with the PFC (pin function controller) and input a high level to the ADTRG pin, then set the TRGE bit to 1 and clear the ADST bit to 0 in the A/D control register (ADCR), and set the EXTRG bit to 1 in the A/D trigger register (ADTRGR). When a low level is input to the ADTRG pin after these settings have been made, the A/D converter detects the low level and sets the ADST bit to 1. If a low level is being input to the ADTRG pin when A/D conversion ends, the ADST bit is set to 1 again, and A/D conversion is started. Figure 16.7 shows the timing for external trigger input. The ADST bit is set to 1 two states after the A/D converter samples the low level on the ADTRG pin. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written into the ADST bit by software. ADTRG pin sampled Pφ ADTRG input ADST bit ADST = 1 Figure 16.7 External Trigger Input Timing 585 16.4.5 A/D Converter Activation by ATU-II The A/D0 and A/D1 converter modules can be activated by an A/D conversion request from the ATU-II’s channel 0 interval timer. To activate the A/D converter by means of the ATU-II, set the TRGE bit to 1 in the A/D control register (ADCR) and clear the EXTRG bit to 0 in the A/D trigger register (ADTRGR). When an ATU-II channel 0 interval timer A/D conversion request is generated after these settings have been made, the ADST bit set to 1. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written into the ADST bit by software. 16.5 Interrupt Sources and DMA Transfer Requests The A/D converter can generate an A/D conversion end interrupt request (ADI0 or ADI1) upon completion of A/D conversions. The ADI interrupt can be enabled by setting the ADIE bit in the A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0. The DMAC can be activated by an ADI interrupt. In this case an interrupt request is not sent to the CPU. When the DMAC is activated by an ADI interrupt, the ADF bit in ADCSR is automatically cleared when data is transferred by the DMAC. See section 9.4.2, Example of DMA Transfer between A/D Converter and On-Chip Memory, for an example of this operation. 16.6 Usage Notes The following points should be noted when using the A/D converter. 1. Analog input voltage range The voltage applied to analog input pins during A/D conversion should be in the range AV SS ≤ ANn ≤ AVref . 2. Relation between AV SS , AVCC and VSS , VCC When using the A/D converter, set AVCC = 5.0 V ±0.5 V, and AVSS = VSS . When the A/D converter is not used, set AVSS = VSS , and do not leave the AVCC pin open. 3. AVref input range Set AVref = 4.5 V to AVCC when the A/D converter is used, and AVref ≤ AVCC when not used. If conditions above are not met, the reliability of the device may be adversely affected. 586 4. Notes on board design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (ANn), analog reference voltage (AVref ), and analog power supply (AVCC) by the analog ground (AVSS ). AVSS should be connected at one point to a stable digital ground (VSS) on the board. 5. Notes on noise countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (ANn) and analog reference voltage (AVref ) should be connected between AVCC and AVSS as shown in figure 16.8. Also, the bypass capacitors connected to AVCC and AVref and the filter capacitor connected to ANn must be connected to AV SS . If a filter capacitor is connected as shown in figure 16.8, the input currents at the analog input pins (ANn) are averaged, and so an error may arise. Careful consideration is therefore required when deciding the circuit constants. AVCC AVref Rin*2 *1 100 Ω AN0–AN31 *1 0.1 µF SH7052 SH7053 SH7054 AVSS Notes: 1. 10 µF 0.01 µF 2. Rin: Input impedance Figure 16.8 Example of Analog Input Pin Protection Circuit 587 Table 16.5 Analog Pin Specifications Item Min Max Unit Analog input capacitance — 20 pF Permissible signal source impedance — 3 kΩ 16.6.1 A/D conversion accuracy definitions A/D conversion accuracy definitions are given below. 1. Resolution The number of A/D converter digital conversion output codes 2. Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (does not include quantization error) (see figure 16.9). 3. Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 111111111 (does not include quantization error) (see figure 16.9). 4. Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.9). 5. Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. 6. Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. 588 Digital output Digital output 111 110 Ideal A/D conversion characteristic Full-scale error Ideal A/D conversion characteristic 101 100 011 001 ;;;;; ; 010 Nonlinearity error Quantization error Actual A/D conversion characteristic 000 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage Offset error FS Analog input voltage Figure 16.9 A/D Conversion Accuracy Definitions 589 590 Section 17 Advanced User Debugger (AUD) 17.1 Overview The SH7052F/SH7053F/SH7054F has an on-chip advanced user debugger (AUD). Use of the AUD simplifies the construction of a simple emulator, with functions such as acquisition of branch trace data and monitoring/tuning of on-chip RAM data. 17.1.1 Features The AUD has the following features: • Eight input/output pins Data bus (AUDATA3 to AUDATA0) AUD reset (AUDRST) AUD sync signal (AUDSYNC) AUD clock (AUDCK) AUD mode (AUDMD) • Two modes Branch trace mode or RAM monitor mode can be selected by switching AUDMD. Branch trace mode When the PC branches on execution of a branch instruction or generation of an interrupt in the user program , the branch is detected by the AUD and the branch destination address is output from AUDATA. The address is compared with the previously output address, and 4-, 8-, 16-, or 32-bit output is selected automatically according to the upper address matching status. RAM monitor mode When an address is written to AUDATA from off-chip, the data corresponding to that address is output. If an address and data are written to AUDATA, the data is transferred to that address. 591 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the AUD. Internal bus AUDATA0 Peripheral module bus PC output circuit On-chip memory AUDATA1 AUDATA2 Address buffer AUDATA3 AUDRST Bus controller Data buffer AUDMD AUDCK On-chip peripheral module Mode control AUDSYNC CPU Figure 17.1 AUD Block Diagram 17.2 Pin Configuration Table 17.1 shows the AUD’s input/output pins. Table 17.1 AUD Pins Function Name Abbreviation Branch Trace Mode RAM Monitor Mode AUD data AUDATA3 to AUDATA0 Branch destination address output Monitor address/data input/output AUD reset AUDRST AUD reset input AUD reset input AUD mode AUDMD Mode select input (L) Mode select input (H) AUD clock AUDCK Serial clock (φ/2) output Serial clock input AUD sync signal AUDSYNC Data start position identification signal output Data start position identification signal input 592 17.2.1 Pin Descriptions Pins Used in Both Modes Pin Description AUDMD The mode is selected by changing the input level at this pin. Low: Branch trace mode High: RAM monitor mode The input at this pin should be changed when AUDRST is low. When no connection is made, this pin is pulled up internally. AUDRST The AUD’s internal buffers and logic are initialized by inputting a low level to this pin. When this signal goes low, the AUD enters the reset state and the AUD’s internal buffers and logic are reset. When AUDRST goes high again after the AUDMD level settles, the AUD starts operating in the selected mode. When no connection is made, this pin is pulled down internally. 593 Pin Functions in Branch Trace Mode Pin Description AUDCK This pin outputs 1/2 the operating frequency (φ/2). This is the clock for AUDATA synchronization. AUDSYNC This pin indicates whether output from AUDATA is valid. High: Valid data is not being output Low: An address is being output AUDATA3 to AUDATA0 1. When AUDSYNC is low When a program branch or interrupt branch occurs, the AUD asserts AUDSYNC and outputs the branch destination address. The output order is A3 to A0, A7 to A4, A11 to A8, A15 to A12, A19 to A16, A23 to A20, A27 to A24, A31 to A28. 2. When AUDSYNC is high When waiting for branch destination address output, these pins constantly output 0011. When an branch occurs, AUDATA3 to AUDATA2 output 10, and AUDATA1 to AUDATA0 indicate whether a 4-, 8-, 16-, or 32-bit address is to be output by comparing the previous fully output address with the address output this time (see table below). AUDATA1, AUDATA0 594 00 Address bits A31 to A4 match; 4 address bits A3 to A0 are to be output (i.e. output is performed once). 01 Address bits A31 to A8 match; 8 address bits A3 to A0 and A7 to A4 are to be output (i.e. output is performed twice). 10 Address bits A31 to A16 match; 16 address bits A3 to A0, A7 to A4, A11 to A8, and A15 to A12 are to be output (i.e. output is performed four times). 11 None of the above cases applies; 31 address bits A3 to A0, A7 to A4, A11 to A8, and A15 to A12, A19 to A16, A23 to A20, A27 to A24, and A31 to A28 are to be output (i.e. output is performed eight times). Pin Functions in RAM Monitor Mode Pin Description AUDCK The external clock input pin. Input the clock to be used for debugging to this pin. The input frequency must not exceed 1/4 the operating frequency. When no connection is made, this pin is pulled up internally. AUDSYNC Do not assert this pin until a command is input to AUDATA from off-chip and the necessary data can be prepared. See the protocol description for details. When no connection is made, this pin is pulled up internally. AUDATA3 to AUDATA0 When a command is input from off-chip, data is output after Ready reception. Output starts when AUDSYNC is negated. See the protocol description for details. When no connections are made, these pins are pulled up internally. 17.3 Branch Trace Mode 17.3.1 Overview In this mode, the branch destination address is output when a branch occurs in the user program. Branches may be caused by branch instruction execution or interrupt/exception processing, but no distinction is made between the two in this mode. 17.3.2 Operation Operation starts in branch trace mode when AUDRST is asserted, AUDMD is driven low, then AUDRST is negated. Figure 17.2 shows an example of data output. While the user program is being executed without branches, the AUDATA pins constantly output 0011 in synchronization with AUDCK. When a branch occurs, after execution starts at the branch destination address in the PC, the previous fully output address (i.e. for which output was not interrupted by the occurrence of another branch) is compared with the current branch address, and depending on the result, AUDSYNC is asserted and the branch destination address output after 1-clock output of 1000 (in the case of 4-bit output), 1001 (8-bit output), 1010 (16-bit output), or 1011 (32-bit output). The initial value of the compared address is H'00000000. On completion of the cycle in which the address is output, AUDSYNC is negated and 0011 is output from the AUDATA pins. 595 If another branch occurs during branch destination address output, the later branch has priority for output. In this case, AUDSYNC is negated and the AUDATA pins output the address after outputting 10xx again (figure 17.3 shows an example of the output when consecutive branches occur). Note that the compared address is the previous fully output address, and not an interrupted address (since the upper address of an interrupted address will be unknown). The interval from the start of execution at the branch destination address in the PC until the AUDATA pins output 10xx is 1.5 or 2 AUDCK cycles. Start of execution at branch destination address in PC AUDCK AUDSYNC AUDATA [3:0] 0011 0011 1011 A3–A0 A7–A4 A11–A8 A15–A12 A19–A16 A23–A20 A27–A24 A31–A28 0011 Figure 17.2 Example of Data Output (32-Bit Output) Start of execution at branch destination address in PC (1) Start of execution at branch destination address in PC (2) AUDCK AUDSYNC AUDATA [3:0] 0011 0011 1011 A3–A0 A7–A4 1010 A3–A0 A7–A4 A11–A8 A15–A12 Figure 17.3 Example of Output in Case of Successive Branches 596 0011 0011 17.4 RAM Monitor Mode 17.4.1 Overview In this mode, all the modules connected to the SH7052F/SH7053F/SH7054F’s internal or external bus can be read and written to, allowing RAM monitoring and tuning to be carried out. 17.4.2 Communication Protocol The AUD latches the AUDATA input when AUDSYNC is asserted. The following AUDATA input format should be used. Input format 0000 DIR A3 to A0 Command . . . . . . A31 to A28 D3 to D0 Address Bit 3 Bit 2 Fixed at 1 0: Read 1: Write . . . . . . Dn to Dn-3 Data (in case of write only) B write: n = 7 W write: n = 15 L write: n = 31 Bit 1 Bit 0 00: Byte 01: Word 10: Longword Spare bits (4 bits): b'0000 Figure 17.4 AUDATA Input Format 597 17.4.3 Operation Operation starts in RAM monitor mode AUDMD is driven high after AUDRST has been asserted, then AUDRST is negated. Figure 17.5 shows an example of a read operation, and figure 17.6 an example of a write operation. When AUDSYNC is asserted, input from the AUDATA pins begins. When a command, address, or data (writing only) is input in the format shown in figure 17.4 AUDATA Input Format, execution of read/write access to the specified address is started. During internal execution, the AUD returns Not Ready (0000). When execution is completed, the Ready flag (0001) is returned (figures 17.5 and 17.6). In a read, data of the specified size is output when AUDSYNC is negated following detection of this flag (figure 17.5). If a command other than the above is input in DIR, the AUD treats this as a command error, disables processing, and sets bit 1 in the Ready flag to 1. If a read/write operation initiated by the command specified in DIR causes a bus error, the AUD disables processing and sets bit 2 in the Ready flag to 1 (figure 17.7). Table 17.2 Ready Flag Format Bit 3 Fixed at 0 Bit 2 Bit 1 Bit 0 0: Normal status 0: Normal status 0: Not ready 1: Bus error 1: Bus error 1: Ready Bus error conditions 1. 2. 3. 4. Word access to address 4n+1 or 4n+3 Longword access to address 4n+1, 4n+2, or 4n+3 Longword access to on-chip I/O 8-bit space Access to external space in single-chip mode AUDCK AUDSYNC Input/output switchover AUDATAn 0000 1000 A3–A0 DIR Input A31–A28 0000 0001 Not ready Ready 0001 0001 D3–D0 D7–D4 Ready Ready Output Figure 17.5 Example of Read Operation (Byte Read) 598 AUDCK AUDSYNC Input/output switchover AUDATAn 0000 1110 A3–A0 A31–A28 D3–D0 0000 D31–D28 DIR 0001 Not ready Input Ready 0001 0001 Ready Ready Output Figure 17.6 Example of Write Operation (Longword Read) AUDCK AUDSYNC Input/output switchover AUDATAn 0000 1010 A3–A0 DIR A31–A28 0000 0101 Not ready Ready (Bus error) Input 0101 Ready 0101 Ready (Bus error) (Bus error) Output Figure 17.7 Example of Error Occurrence (Longword Read) 17.5 Usage Notes 17.5.1 Initialization The debugger’s internal buffers and processing states are initialized in the following cases: 1. 2. 3. 4. 5. In a power-on reset In hardware standby mode When AUDRST is driven low When the AUDSRST bit is set to 1 in the SYSCR register (see section 23.2.2) When the MSTOP3 bit is set to 1 in the MSTCR register (see section 23.2.3) 17.5.2 Operation in Software Standby Mode The debugger is not initialized in software standby mode. However, since the SH7052F/SH7053F/SH7054F’s internal operation halts in software standby mode: 1. When AUDMD is high (RAM monitor mode): Ready is not returned (Not Ready continues to be returned) However, when operating on an external clock, the protocol continues. 2. When AUDMD is low (PC trace): Operation stops. However, operation continues when STBY is released. 599 17.5.3 ROM Area Writes Do not perform an AUD write to a ROM address immediately after an ATU register write cycle. For details, see “Writing to ROM Area Immediately after ATU Register Write” in section 10.7, Usage Notes. 600 Section 18 Pin Function Controller (PFC) 18.1 Overview The pin function controller (PFC) consists of registers for selecting multiplex pin functions and their input/output direction. Table 18.1 shows the SH7052F/SH7053F/SH7054F’s multiplex pins. Table 18.1 SH7052F/SH7053F/SH7054F Multiplex Pins Port Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) A PA0 input/output (port) TI0A input (ATU) A PA1 input/output (port) TI0B input (ATU) A PA2 input/output (port) TI0C input (ATU) A PA3 input/output (port) TI0D input (ATU) A PA4 input/output (port) TIO3A input/output (ATU) A PA5 input/output (port) TIO3B input/output (ATU) A PA6 input/output (port) TIO3C input/output (ATU) A PA7 input/output (port) TIO3D input/output (ATU) A PA8 input/output (port) TIO4A input/output (ATU) A PA9 input/output (port) TIO4B input/output (ATU) A PA10 input/output (port) TIO4C input/output (ATU) A PA11 input/output (port) TIO4D input/output (ATU) A PA12 input/output (port) TIO5A input/output (ATU) A PA13 input/output (port) TIO5B input/output (ATU) A PA14 input/output (port) TxD0 output (SCI) A PA15 input/output (port) RxD0 input (SCI) B PB0 input/output (port) TO6A output (ATU) B PB1 input/output (port) TO6B output (ATU) B PB2 input/output (port) TO6C output (ATU) B PB3 input/output (port) TO6D output (ATU) B PB4 input/output (port) TO7A output (ATU) TO8A output (ATU) B PB5 input/output (port) TO7B output (ATU) TO8B output (ATU) B PB6 input/output (port) TO7C output (ATU) TO8C output (ATU) B PB7 input/output (port) TO7D output (ATU) TO8D output (ATU) B PB8 input/output (port) TxD3 output (SCI) TO8E output (ATU) B PB9 input/output (port) RxD3 input (SCI) TO8F output (ATU) Function 4 (Related Module) 601 Table 18.1 SH7052F/SH7053F/SH7054F Multiplex Pins (cont) Port Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) Function 4 (Related Module) B PB10 input/output (port) TxD4 output (SCI) HTxD output (HCAN) TO8G output (ATU) B PB11 input/output (port) RxD4 input (SCI) HRxD input (HCAN) TO8H output (ATU) B PB12 input/output (port) TCLKA input (ATU) UBCTRG output (UBC) B PB13 input/output (port) SCK0 input/output (SCI) B PB14 input/output (port) SCK1 input/output (SCI) TCLKB input (ATU) B PB15 input/output (port) PULS5 output (APC) SCK2 input/output (SCI) C PC0 input/output (port) TxD1 output (SCI) C PC1 input/output (port) RxD1 input (SCI) C PC2 input/output (port) TxD2 output (SCI) C PC3 input/output (port) RxD2 input (SCI) C PC4 input/output (port) IRQ0 input (INTC) D PD0 input/output (port) TIO1A input/output (ATU) D PD1 input/output (port) TIO1B input/output (ATU) D PD2 input/output (port) TIO1C input/output (ATU) D PD3 input/output (port) TIO1D input/output (ATU) D PD4 input/output (port) TIO1E input/output (ATU) D PD5 input/output (port) TIO1F input/output (ATU) D PD6 input/output (port) TIO1G input/output (ATU) D PD7 input/output (port) TIO1H input/output (ATU) D PD8 input/output (port) PULS0 output (APC) D PD9 input/output (port) PULS1 output (APC) D PD10 input/output (port) PULS2 output (APC) D PD11 input/output (port) PULS3 output (APC) D PD12 input/output (port) PULS4 output (APC) D PD13 input/output (port) PULS6 output (APC) E PE0 input/output (port) A0 output (BSC) E PE1 input/output (port) A1 output (BSC) E PE2 input/output (port) A2 output (BSC) E PE3 input/output (port) A3 output (BSC) E PE4 input/output (port) A4 output (BSC) E PE5 input/output (port) A5 output (BSC) E PE6 input/output (port) A6 output (BSC) E PE7 input/output (port) A7 output (BSC) 602 HTxD output (HCAN) TI10 input (ATU) Table 18.1 SH7052F/SH7053F/SH7054F Multiplex Pins (cont) Port Function 1 (Related Module) Function 2 (Related Module) E PE8 input/output (port) A8 output (BSC) E PE9 input/output (port) A9 output (BSC) E PE10 input/output (port) A10 output (BSC) E PE11 input/output (port) A11 output (BSC) E PE12 input/output (port) A12 output (BSC) E PE13 input/output (port) A13 output (BSC) E PE14 input/output (port) A14 output (BSC) E PE15 input/output (port) A15 output (BSC) F PF0 input/output (port) A16 output (BSC) F PF1 input/output (port) A17 output (BSC) F PF2 input/output (port) A18 output (BSC) F PF3 input/output (port) A19 output (BSC) F PF4 input/output (port) A20 output (BSC) F PF5 input/output (port) A21 output (BSC) F PF6 input/output (port) WRL output (BSC) F PF7 input/output (port) WRH output (BSC) F PF8 input/output (port) WAIT input (BSC) F PF9 input/output (port) RD output (BSC) F PF10 input/output (port) CS0 output (BSC) F PF11 input/output (port) CS1 output (BSC) F PF12 input/output (port) CS2 output (BSC) F PF13 input/output (port) CS3 output (BSC) F PF14 input/output (port) BACK output (BSC) F PF15 input/output (port) BREQ input (BSC) G PG0 input/output (port) PULS7 output (APC) G PG1 input/output (port) IRQ1 input (INTC) G PG2 input/output (port) IRQ2 input (INTC) G PG3 input/output (port) IRQ3 input (INTC) H PH0 input/output (port) D0 input/output (BSC) H PH1 input/output (port) D1 input/output (BSC) H PH2 input/output (port) D2 input/output (BSC) H PH3 input/output (port) D3 input/output (BSC) H PH4 input/output (port) D4 input/output (BSC) Function 3 (Related Module) Function 4 (Related Module) POD input (port) HRxD input (HCAN) ADTRG0 input (A/D) 603 Table 18.1 SH7052F/SH7053F/SH7054F Multiplex Pins (cont) Port Function 1 (Related Module) Function 2 (Related Module) H PH5 input/output (port) D5 input/output (BSC) H PH6 input/output (port) D6 input/output (BSC) H PH7 input/output (port) D7 input/output (BSC) H PH8 input/output (port) D8 input/output (BSC) H PH9 input/output (port) D9 input/output (BSC) H PH10 input/output (port) D10 input/output (BSC) H PH11 input/output (port) D11 input/output (BSC) H PH12 input/output (port) D12 input/output (BSC) H PH13 input/output (port) D13 input/output (BSC) H PH14 input/output (port) D14 input/output (BSC) H PH15 input/output (port) D15 input/output (BSC) J PJ0 input/output (port) TIO2A input/output (ATU) J PJ1 input/output (port) TIO2B input/output (ATU) J PJ2 input/output (port) TIO2C input/output (ATU) J PJ3 input/output (port) TIO2D input/output (ATU) J PJ4 input/output (port) TIO2E input/output (ATU) J PJ5 input/output (port) TIO2F input/output (ATU) J PJ6 input/output (port) TIO2G input/output (ATU) J PJ7 input/output (port) TIO2H input/output (ATU) J PJ8 input/output (port) TIO5C input/output (ATU) J PJ9 input/output (port) TIO5D input/output (ATU) J PJ10 input/output (port) TI9A input (ATU) J PJ11 input/output (port) TI9B input (ATU) J PJ12 input/output (port) TI9C input (ATU) J PJ13 input/output (port) TI9D input (ATU) J PJ14 input/output (port) TI9E input (ATU) J PJ15 input/output (port) TI9F input (ATU) K PK0 input/output (port) TO8A output (ATU) K PK1 input/output (port) TO8B output (ATU) K PK2 input/output (port) TO8C output (ATU) K PK3 input/output (port) TO8D output (ATU) K PK4 input/output (port) TO8E output (ATU) K PK5 input/output (port) TO8F output (ATU) 604 Function 3 (Related Module) Function 4 (Related Module) Table 18.1 SH7052F/SH7053F/SH7054F Multiplex Pins (cont) Port Function 1 (Related Module) Function 2 (Related Module) K PK6 input/output (port) TO8G output (ATU) K PK7 input/output (port) TO8H output (ATU) K PK8 input/output (port) TO8I output (ATU) K PK9 input/output (port) TO8J output (ATU) K PK10 input/output (port) TO8K output (ATU) K PK11 input/output (port) TO8L output (ATU) K PK12 input/output (port) TO8M output (ATU) K PK13 input/output (port) TO8N output (ATU) K PK14 input/output (port) TO8O output (ATU) K PK15 input/output (port) TO8P output (ATU) Function 3 (Related Module) Function 4 (Related Module) 605 18.2 Register Configuration PFC registers are listed in table 18.2. Table 18.2 PFC Registers Name Abbreviation R/W Initial Value Address Access Size Port A IO register PAIOR R/W H'0000 H'FFFFF720 8, 16 Port A control register H PACRH R/W H'0000 H'FFFFF722 8, 16 Port A control register L PACRL R/W H'0000 H'FFFFF724 8, 16 Port B IO register PBIOR R/W H'0000 H'FFFFF730 8, 16 Port B control register H PBCRH R/W H'0000 H'FFFFF732 8, 16 Port B control register L PBCRL R/W H'0000 H'FFFFF734 8, 16 Port B invert register PBIR R/W H'0000 H'FFFFF736 8, 16 Port C IO register PCIOR R/W H'0000 H'FFFFF73A 8, 16 Port C control register PCCR R/W H'0000 H'FFFFF73C 8, 16 Port D IO register PDIOR R/W H'0000 H'FFFFF740 8, 16 Port D control register H PDCRH R/W H'0000 H'FFFFF742 8, 16 Port D control register L PDCRL R/W H'0000 H'FFFFF744 8, 16 Port E IO register PEIOR R/W H'0000 H'FFFFF750 8, 16 Port E control register PECR R/W H'0000 H'FFFFF752 8, 16 Port F IO register PFIOR R/W H'0000 H'FFFFF748 8, 16 Port F control register H PFCRH R/W H'0015 H'FFFFF74A 8, 16 Port F control register L PFCRL R/W H'5000 H'FFFFF74C 8, 16 Port G IO register PGIOR R/W H'0000 H'FFFFF760 8, 16 Port G control register PGCR R/W H'0000 H'FFFFF762 8, 16 Port H IO register PHIOR R/W H'0000 H'FFFFF728 8, 16 Port H control register PHCR R/W H'0000 H'FFFFF72A 8, 16 Port J IO register PJIOR R/W H'0000 H'FFFFF766 8, 16 Port J control register H PJCRH R/W H'0000 H'FFFFF768 8, 16 Port J control register L PJCRL R/W H'0000 H'FFFFF76A 8, 16 Port K IO register PKIOR R/W H'0000 H'FFFFF770 8, 16 Port K control register H PKCRH R/W H'0000 H'FFFFF772 8, 16 Port K control register L PKCRL R/W H'0000 H'FFFFF774 8, 16 Port K invert register PKIR R/W H'0000 H'FFFFF776 8, 16 606 18.3 Register Descriptions 18.3.1 Port A IO Register (PAIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PA15 IOR PA14 IOR PA13 IOR PA12 IOR PA11 IOR PA10 IOR PA9 IOR PA8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PA7 IOR PA6 IOR PA5 IOR PA4 IOR PA3 IOR PA2 IOR PA1 IOR PA0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port A IO register (PAIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port A. Bits PA15IOR to PA0IOR correspond to pins PA15/RxD0 to PA0/TI0A. PAIOR is enabled when port A pins function as general input/output pins (PA15 to PA0) or ATU input/output pins, and disabled otherwise. For bits 3 to 0, when ATU input capture input is selected, the PAIOR bits should be cleared to 0. When port A pins function as PA15 to PA0 or ATU input/output pins, a pin becomes an output when the corresponding bit in PAIOR is set to 1, and an input when the bit is cleared to 0. PAIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 18.3.2 Port A Control Registers H and L (PACRH, PACRL) Port A control registers H and L (PACRH, PACRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port A. PACRH selects the functions of the pins for the upper 8 bits of port A, and PACRL selects the functions of the pins for the lower 8 bits. PACRH and PACRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. 607 Port A Control Register H (PACRH) Bit: 15 14 13 12 11 10 9 8 — PA15MD — PA14MD — PA13MD — PA12MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Bit: 7 6 5 4 3 2 1 0 — PA11MD — PA10MD — PA9MD — PA8MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W • Bit 15—Reserved: This bit always reads 0. The write value should always be 0. • Bit 14—PA15 Mode Bit (PA15MD): Selects the function of pin PA15/RxD0. Bit 14: PA15MD Description 0 General input/output (PA15) 1 Receive data input (RxD0) (Initial value) • Bit 13—Reserved: This bit always reads 0. The write value should always be 0. • Bit 12—PA14 Mode Bit (PA14MD): Selects the function of pin PA14/TxD0. Bit 12: PA14MD Description 0 General input/output (PA14) 1 Transmit data output (TxD0) (Initial value) • Bit 11—Reserved: This bit always reads 0. The write value should always be 0. • Bit 10—PA13 Mode Bit (PA13MD): Selects the function of pin PA13/TIO5B. Bit 10: PA13MD Description 0 General input/output (PA13) 1 ATU input capture input/output compare output (TIO5B) • Bit 9—Reserved: This bit always reads 0. The write value should always be 0. 608 (Initial value) • Bit 8—PA12 Mode Bit (PA12MD): Selects the function of pin PA12/TIO5A. Bit 8: PA12MD Description 0 General input/output (PA12) 1 ATU input capture input/output compare output (TIO5A) (Initial value) • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—PA11 Mode Bit (PA11MD): Selects the function of pin PA11/TIO4D. Bit 6: PA11MD Description 0 General input/output (PA11) 1 ATU input capture input/output compare output (TIO4D) (Initial value) • Bit 5—Reserved: This bit always reads 0. The write value should always be 0. • Bit 4—PA10 Mode Bit (PA10MD): Selects the function of pin PA10/TIO4C. Bit 4: PA10MD Description 0 General input/output (PA10) 1 ATU input capture input/output compare output (TIO4C) (Initial value) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PA9 Mode Bit (PA9MD): Selects the function of pin PA9/TIO4B. Bit 2: PA9MD Description 0 General input/output (PA9) 1 ATU input capture input/output compare output (TIO4B) (Initial value) • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. • Bit 0—PA8 Mode Bit (PA8MD): Selects the function of pin PA8/TIO4A. Bit 0: PA8MD Description 0 General input/output (PA8) 1 ATU input capture input/output compare output (TIO4A) (Initial value) 609 Port A Control Register L (PACRL) Bit: 15 14 13 12 11 10 9 8 — PA7MD — PA6MD — PA5MD — PA4MD Initial value: 0 0 0 0 0 0 0 0 R/W: — R/W — R/W — R/W — R/W Bit: 7 6 5 4 3 2 1 0 — PA3MD — PA2MD — PA1MD — PA0MD Initial value: 0 0 0 0 0 0 0 0 R/W: — R/W — R/W — R/W — R/W • Bit 15—Reserved: This bit always reads 0. The write value should always be 0. • Bit 14—PA7 Mode Bit (PA7MD): Selects the function of pin PA7/TIO3D. Bit 14: PA7MD Description 0 General input/output (PA7) 1 ATU input capture input/output compare output (TIO3D) (Initial value) • Bit 13—Reserved: This bit always reads 0. The write value should always be 0. • Bit 12—PA6 Mode Bit (PA6MD): Selects the function of pin PA6/TIO3C. Bit 12: PA6MD Description 0 General input/output (PA6) 1 ATU input capture input/output compare output (TIO3C) (Initial value) • Bit 11—Reserved: This bit always reads 0. The write value should always be 0. • Bit 10—PA5 Mode Bit (PA5MD): Selects the function of pin PA5/TIO3B. Bit 10: PA5MD Description 0 General input/output (PA5) 1 ATU input capture input/output compare output (TIO3B) • Bit 9—Reserved: This bit always reads 0. The write value should always be 0. 610 (Initial value) • Bit 8—PA4 Mode Bit (PA4MD): Selects the function of pin PA4/TIO3A. Bit 8: PA4MD Description 0 General input/output (PA4) 1 ATU input capture input/output compare output (TIO3A) (Initial value) • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—PA3 Mode Bit (PA3MD): Selects the function of pin PA3/TI0D. Bit 6: PA3MD Description 0 General input/output (PA3) 1 ATU input capture input (TI0D) (Initial value) • Bit 5—Reserved: This bit always reads 0. The write value should always be 0. • Bit 4—PA2 Mode Bit (PA2MD): Selects the function of pin PA2/TI0C. Bit 4: PA2MD Description 0 General input/output (PA2) 1 ATU input capture input (TI0C) (Initial value) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PA1 Mode Bit (PA1MD): Selects the function of pin PA1/TI0B. Bit 2: PA1MD Description 0 General input/output (PA1) 1 ATU input capture input (TI0B) (Initial value) • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. • Bit 0—PA0 Mode Bit (PA0MD): Selects the function of pin PA0/TI0A. Bit 0: PA1MD Description 0 General input/output (PA0) 1 ATU input capture input (TI0A) (Initial value) 611 18.3.3 Port B IO Register (PBIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PB15 IOR PB14 IOR PB13 IOR PB12 IOR PB11 IOR PB10 IOR PB9 IOR PB8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7 IOR PB6 IOR PB5 IOR PB4 IOR PB3 IOR PB2 IOR PB1 IOR PB0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port B IO register (PBIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port B. Bits PB15IOR to PB0IOR correspond to pins PB15/PULS5/SCK2 to PB0/TO6A. PBIOR is enabled when port B pins function as general input/output pins (PB15 to PB0) or serial clock pins (SCK0, SCK1, SCK2), and disabled otherwise. When port B pins function as PB15 to PB0 or SCK0, SCK1, and SCK2, a pin becomes an output when the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0. PBIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 18.3.4 Port B Control Registers H and L (PBCRH, PBCRL) Port B control registers H and L (PBCRH, PBCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port B. PBCRH selects the functions of the pins for the upper 8 bits of port B, and PBCRL selects the functions of the pins for the lower 8 bits. PBCRH and PBCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. 612 Port B Control Register H (PBCRH) Bit: 15 14 13 12 11 10 9 8 PB15 MD1 PB15 MD0 PB14 MD1 PB14 MD0 — PB13 MD PB12 MD1 PB12 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R R/W R/W R/W 7 6 5 4 3 2 1 0 PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bit: Initial value: R/W: • Bits 15 and 14—PB15 Mode Bits 1 and 0 (PB15MD1, PB15MD0): These bits select the function of pin PB15/PULS5/SCK2. Bit 15: PB15MD1 Bit 14: PB15MD0 Description 0 0 General input/output (PB15) 1 APC pulse output (PULS5) 0 Serial clock input/output (SCK2) 1 Reserved (Do not set) 1 (Initial value) • Bits 13 and 12—PB14 Mode Bits 1 and 0 (PB14MD1, PB14MD0): These bits select the function of pin PB14/SCK1/TCLKB/T110. Bit 13: PB14MD1 Bit 12: PB14MD0 Description 0 0 General input/output (PB14) 1 Serial clock input/output (SCK1) 0 ATU clock input (TCLKB) 1 ATU edge input (TI10) 1 (Initial value) • Bit 11—Reserved: This bit always reads 0. The write value should always be 0. 613 • Bit 10—PB13 Mode Bit (PB13MD): Selects the function of pin PB13/SCK0. Bit 10: PB13MD Description 0 General input/output (PB13) 1 Serial clock input/output (SCK0) (Initial value) • Bits 9 and 8—PB12 Mode Bits 1 and 0 (PB12MD1, PB12MD0): These bits select the function of pin PB12/TCLKA/UBCTRG. Bit 9: PB12MD1 Bit 8: PB12MD0 Description 0 0 General input/output (PB12) 1 ATU clock input (TCLKA) 0 Trigger pulse output (UBCTRG) 1 Reserved (Do not set) 1 (Initial value) • Bits 7 and 6—PB11 Mode Bits 1 and 0 (PB11MD1, PB11MD0): These bits select the function of pin PB11/RxD4/HRxD0/TO8H. Bit 7: PB11MD1 Bit 6: PB11MD0 Description 0 0 General input/output (PB11) 1 Receive data input (RxD4) 0 HCAN receive data input (HRxD) 1 ATU one-shot pulse output (TO8H) 1 (Initial value) • Bits 5 and 4—PB10 Mode Bits 1 and 0 (PB10MD1, PB10MD0): These bits select the function of pin PB10/TxD4/HTxD0/TO8G. Bit 5: PB10MD1 Bit 4: PB10MD0 Description 0 0 General input/output (PB10) 1 Transmit data output (TxD4) 0 HCAN transmit data output (HTxD) 1 ATU one-shot pulse output (TO8G) 1 614 (Initial value) • Bits 3 and 2—PB9 Mode Bits 1 and 0 (PB9MD1, PB9MD0): These bits select the function of pin PB9/RxD3/TO8F. Bit 3: PB9MD1 Bit 2: PB9MD0 Description 0 0 General input/output (PB9) 1 Receive data input (RxD3) 0 ATU one-shot pulse output (TO8F) 1 Reserved (Do not set) 1 (Initial value) • Bits 1 and 0—PB8 Mode Bits 1 and 0 (PB8MD1, PB8MD0): These bits select the function of pin PB8/TxD3/TO8E. Bit 1: PB8MD1 Bit 0: PB8MD0 Description 0 0 General input/output (PB8) 1 Transmit data output (TxD3) 0 ATU one-shot pulse output (TO8E) 1 Reserved (Do not set) 1 (Initial value) Port B Control Register L (PBCRL) Bit: 15 14 13 12 11 10 9 8 PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 — PB3MD — PB2MD — PB1MD — PB0MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W R/W: Bit: 615 • Bits 15 and 14—PB7 Mode Bits 1 and 0 (PB7MD1, PB7MD0): These bits select the function of pin PB7/TO7D/TO8D. Bit 15: PB7MD1 Bit 14: PB7MD0 Description 0 0 General input/output (PB7) 1 ATU PWM output (TO7D) 0 ATU one-shot pulse output (TO8D) 1 Reserved (Do not set) 1 (Initial value) • Bits 13 and 12—PB6 Mode Bits 1 and 0 (PB6MD1, PB6MD0): These bits select the function of pin PB6/TO7C/TO8C. Bit 13: PB6MD1 Bit 12: PB6MD0 Description 0 0 General input/output (PB6) 1 ATU PWM output (TO7C) 0 ATU one-shot pulse output (TO8C) 1 Reserved (Do not set) 1 (Initial value) • Bits 11 and 10—PB5 Mode Bits 1 and 0 (PB5MD1, PB5MD0): These bits select the function of pin PB5/TO7B/TO8B. Bit 11: PB5MD1 Bit 10: PB5MD0 Description 0 0 General input/output (PB5) 1 ATU PWM output (TO7B) 0 ATU one-shot pulse output (TO8B) 1 Reserved (Do not set) 1 (Initial value) • Bits 9 and 8—PB4 Mode Bits 1 and 0 (PB4MD1, PB4MD0): These bits select the function of pin PB4/TO7A/TO8A. Bit 9: PB4MD1 Bit 8: PB4MD0 Description 0 0 General input/output (PB4) 1 ATU PWM output (TO7A) 0 ATU one-shot pulse output (TO8A) 1 Reserved (Do not set) 1 • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. 616 (Initial value) • Bit 6—PB3 Mode Bit (PB3MD): Selects the function of pin PB3/TO6D. Bit 6: PB3MD Description 0 General input/output (PB3) 1 ATU PWM output (TO6D) (Initial value) • Bit 5—Reserved: This bit always reads 0. The write value should always be 0. • Bit 4—PB2 Mode Bit (PB2MD): Selects the function of pin PB2/TO6C. Bit 4: PB2MD Description 0 General input/output (PB2) 1 ATU PWM output (TO6C) (Initial value) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PB1 Mode Bit (PB1MD): Selects the function of pin PB1/TO6B. Bit 2: PB1MD Description 0 General input/output (PB1) 1 ATU PWM output (TO6B) (Initial value) • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. • Bit 0—PB0 Mode Bit (PB0MD): Selects the function of pin PB0/TO6A. Bit 0: PB0MD Description 0 General input/output (PB0) 1 ATU PWM output (TO6A) (Initial value) 617 18.3.5 Port B Invert Register (PBIR) Bit: 15 14 13 PB15IR PB14IR PB13IR Initial value: R/W: Bit: Initial value: R/W: 12 — 11 10 PB11IR PB10IR 9 8 PB9IR PB8IR 0 0 0 0 0 0 0 0 R/W R/W R/W R R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7IR PB6IR PB5IR PB4IR PB3IR PB2IR PB1IR PB0IR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port B invert register (PBIR) is a 16-bit readable/writable register that sets the port B inversion function. Bits PB15IR to PB13IR and PB11IR to PB0IR correspond to pins PB15/PULS5/SCK2 to PB13/SCK0 and PB11/RxD4/HRxD0/TO8H to PB0/TO6A. PBIR is enabled when port B pins function as ATU outputs or serial clock pins, and disabled otherwise. When port B pins function as ATU outputs or serial clock pins, the value of a pin is inverted when the corresponding bit in PBIR is set to 1. PBIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PBnIR Description 0 Value is not inverted 1 Value is inverted n = 15 to 0 618 (Initial value) 18.3.6 Port C IO Register (PCIOR) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W PC4IOR PC3IOR PC2IOR PC1IOR PC0IOR The port C IO register (PCIOR) is a 16-bit readable/writable register that selects the input/output direction of the 5 pins in port C. Bits PC4IOR to PC0IOR correspond to pins PC4/IRQ0 to PC0/TxD1. PCIOR is enabled when port C pins function as general input/output pins (PC4 to PC0), and disabled otherwise. When port C pins function as PC4 to PC0, a pin becomes an output when the corresponding bit in PCIOR is set to 1, and an input when the bit is cleared to 0. PCIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 619 18.3.7 Port C Control Register (PCCR) The port C control register (PCCR) is a 16-bit readable/writable register that selects the functions of the 5 multiplex pins in port C. PCCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Bit: 15 14 13 12 11 10 9 8 — — — — — — — PC4MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 — PC3MD — PC2MD — PC1MD — PC0MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W • Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0. • Bit 8—PC4 Mode Bit (PC4MD): Selects the function of pin PC4/IRQ0. Bit 8: PC4MD Description 0 General input/output (PC4) 1 Interrupt request input (IRQ0) (Initial value) • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—PC3 Mode Bit (PC3MD): Selects the function of pin PC3/RxD2. Bit 6: PC3MD Description 0 General input/output (PC3) 1 Receive data input (RxD2) 620 (Initial value) • Bit 5—Reserved: This bit always reads 0. The write value should always be 0. • Bit 4—PC2 Mode Bit (PC2MD): Selects the function of pin PC2/TxD2. Bit 4: PC2MD Description 0 General input/output (PC2) 1 Transmit data output (TxD2) (Initial value) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PC1 Mode Bit (PC1MD): Selects the function of pin PC1/RxD1. Bit 2: PC1MD Description 0 General input/output (PC1) 1 Receive data input (RxD1) (Initial value) • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. • Bit 0—PC0 Mode Bit (PC0MD): Selects the function of pin PC0/TxD1. Bit 0: PC0MD Description 0 General input/output (PC0) 1 Transmit data output (TxD1) (Initial value) 621 18.3.8 Port D IO Register (PDIOR) Bit: 15 14 13 12 11 10 9 8 — — PD13 IOR PD12 IOR PD11 IOR PD10 IOR PD9 IOR PC8 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PD7 IOR PD6 IOR PD5 IOR PD4 IOR PD3 IOR PD2 IOR PD1 IOR PD0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: The port D IO register (PDIOR) is a 16-bit readable/writable register that selects the input/output direction of the 14 pins in port D. Bits PD13IOR to PD0IOR correspond to pins PD13/PULS6/HTxD0/HTxD1 to PD0/TIO1A. PDIOR is enabled when port D pins function as general input/output pins (PD13 to PD0) or timer input/output pins, and disabled otherwise. When port D pins function as PD13 to PD0 or timer input/output pins, a pin becomes an output when the corresponding bit in PDIOR is set to 1, and an input when the bit is cleared to 0. PDIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 622 18.3.9 Port D Control Registers H and L (PDCRH, PDCRL) Port D control registers H and L (PDCRH, PDCRL) are 16-bit readable/writable registers that select the functions of the 14 multiplex pins in port D. PDCRH selects the functions of the pins for the upper 6 bits of port D, and PDCRL selects the functions of the pins for the lower 8 bits. PDCRH and PDCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. Port D Control Register H (PDCRH) Bit: 15 14 13 12 11 10 9 8 — — — — PD13 MD1 PD13 MD0 — PD12 MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R R/W Bit: 7 6 5 4 3 2 1 0 — PD11 MD — PD10 MD — PD9 MD — PD8 MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W • Bits 15 to 12—Reserved: These bits always read 0. The write value should always be 0. • Bits 11 and 10—PD13 Mode Bits 1 and 0 (PD13MD1, PD13MD0): These bits select the function of pin PD13/PULS6/HTxD. Bit 11: PD13MD1 Bit 10: PD13MD0 Description 0 0 General input/output (PD13) 1 APC pulse output (PULS6) 0 HCAN transmit data output (HTxD) 1 Reserved (Do not set) 1 (Initial value) • Bit 9—Reserved: This bit always reads 0. The write value should always be 0. 623 • Bit 8—PD12 Mode Bit (PD12MD): Selects the function of pin PD12/PULS4. Bit 8: PD12MD Description 0 General input/output (PD12) 1 APC pulse output (PULS4) (Initial value) • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—PD11 Mode Bit (PD11MD): Selects the function of pin PD11/PULS3. Bit 6: PD12MD Description 0 General input/output (PD11) 1 APC pulse output (PULS3) (Initial value) • Bit 5—Reserved: This bit always reads 0. The write value should always be 0. • Bit 4—PD10 Mode Bit (PD10MD): Selects the function of pin PD10/PULS2. Bit 4: PD10MD Description 0 General input/output (PD10) 1 APC pulse output (PULS2) (Initial value) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PD9 Mode Bit (PD9MD): Selects the function of pin PD9/PULS1. Bit 2: PD9MD Description 0 General input/output (PD9) 1 APC pulse output (PULS1) (Initial value) • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. • Bit 0—PD8 Mode Bit (PD8MD): Selects the function of pin PD8/PULS0. Bit 0: PD8MD Description 0 General input/output (PD8) 1 APC pulse output (PULS0) 624 (Initial value) Port D Control Register L (PDCRL) Bit: 15 14 13 12 11 10 9 8 — PD7MD — PD6MD — PD5MD — PD4MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Bit: 7 6 5 4 3 2 1 0 — PD3MD — PD2MD — PD1MD — PD0MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W • Bit 15—Reserved: This bit always reads 0. The write value should always be 0. • Bit 14—PD7 Mode Bit (PD7MD): Selects the function of pin PD7/TIO1H. Bit 14: PD7MD Description 0 General input/output (PD7) 1 ATU input capture input/output compare output (TIO1H) (Initial value) • Bit 13—Reserved: This bit always reads 0. The write value should always be 0. • Bit 12—PD6 Mode Bit (PD6MD): Selects the function of pin PD6/TIO1G. Bit 12: PD6MD Description 0 General input/output (PD6) 1 ATU input capture input/output compare output (TIO1G) (Initial value) • Bit 11—Reserved: This bit always reads 0. The write value should always be 0. • Bit 10—PD5 Mode Bit (PD5MD): Selects the function of pin PD5/TIO1F. Bit 10: PD5MD Description 0 General input/output (PD5) 1 ATU input capture input/output compare output (TIO1F) (Initial value) • Bit 9—Reserved: This bit always reads 0. The write value should always be 0. 625 • Bit 8—PD4 Mode Bit (PD4MD): Selects the function of pin PD4/TIO1E. Bit 8: PD4MD Description 0 General input/output (PD4) 1 ATU input capture input/output compare output (TIO1E) (Initial value) • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—PD3 Mode Bit (PD3MD): Selects the function of pin PD3/TIO1D. Bit 6: PD3MD Description 0 General input/output (PD3) 1 ATU input capture input/output compare output (TIO1D) (Initial value) • Bit 5—Reserved: This bit always reads 0. The write value should always be 0. • Bit 4—PD2 Mode Bit (PD2MD): Selects the function of pin PD2/TIO1C. Bit 4: PD2MD Description 0 General input/output (PD2) 1 ATU input capture input/output compare output (TIO1C) (Initial value) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PD1 Mode Bit (PD1MD): Selects the function of pin PD1/TIO1B. Bit 2: PD1MD Description 0 General input/output (PD1) 1 ATU input capture input/output compare output (TIO1B) (Initial value) • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. • Bit 0—PD0 Mode Bit (PD0MD): Selects the function of pin PD0/TIO1A. Bit 0: PD0MD Description 0 General input/output (PD0) 1 ATU input capture input/output compare output (TIO1A) 626 (Initial value) 18.3.10 Port E IO Register (PEIOR) Bit: 15 14 13 12 11 10 9 8 PE15 IOR PE14 IOR PE13 IOR PE12 IOR PE11 IOR PE10 IOR PE9 IOR PE8 IOR Initial value: 0 R/W: R/W Bit: Initial value: R/W: 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PE7 IOR PE6 IOR PE5 IOR PE4 IOR PE3 IOR PE2 IOR PE1 IOR PE0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port E IO register (PEIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port E. Bits PE15IOR to PE0IOR correspond to pins PE15/A15 to PE0/A0. PEIOR is enabled when port E pins function as general input/output pins (PE15 to PE0), and disabled otherwise. When port E pins function as PE15 to PE0, a pin becomes an output when the corresponding bit in PEIOR is set to 1, and an input when the bit is cleared to 0. PEIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 627 18.3.11 Port E Control Register (PECR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PE15 MD PE14 MD PE13 MD PE12 MD PE11 MD PE10 MD PE9 MD PE8 MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PE7 MD PE6 MD PE5 MD PE4 MD PE3 MD PE2 MD PE1 MD PE0 MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port E control register (PECR) is a 16-bit readable/writable register that selects the functions of the 16 multiplex pins in port E. PECR settings are not valid in all operating modes. 1. Expanded mode with on-chip ROM disabled Port E pins function as address output pins, and PECR settings are invalid. 2. Expanded mode with on-chip ROM enabled Port E pins are multiplexed as address output pins and general input/output pins. PECR settings are valid. 3. Single-chip mode Port E pins function as general input/output pins, and PECR settings are invalid. PECR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. • Bit 15—PE15 Mode Bit (PE15MD): Selects the function of pin PE15/A15. Description Bit 15: PE15MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A15) (Initial value) General input/output (PE15) (Initial value) General input/output (PE15) (Initial value) 1 Address output (A15) Address output (A15) General input/output (PE15) 628 • Bit 14—PE14 Mode Bit (PE14MD): Selects the function of pin PE14/A14. Description Bit 14: PE14MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A14) (Initial value) General input/output (PE14) (Initial value) General input/output (PE14) (Initial value) 1 Address output (A14) Address output (A14) General input/output (PE14) • Bit 13—PE13 Mode Bit (PE13MD): Selects the function of pin PE13/A13. Description Bit 13: PE13MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A13) (Initial value) General input/output (PE13) (Initial value) General input/output (PE13) (Initial value) 1 Address output (A13) Address output (A13) General input/output (PE13) • Bit 12—PE12 Mode Bit (PE12MD): Selects the function of pin PE12/A12. Description Bit 12: PE12MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A12) (Initial value) General input/output (PE12) (Initial value) General input/output (PE12) (Initial value) 1 Address output (A12) Address output (A12) General input/output (PE12) • Bit 11—PE11 Mode Bit (PE11MD): Selects the function of pin PE11/A11. Description Bit 11: PE11MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A11) (Initial value) General input/output (PE11) (Initial value) General input/output (PE11) (Initial value) 1 Address output (A11) Address output (A11) General input/output (PE11) 629 • Bit 10—PE10 Mode Bit (PE10MD): Selects the function of pin PE10/A10. Description Bit 10: PE10MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A10) (Initial value) General input/output (PE10) (Initial value) General input/output (PE10) (Initial value) 1 Address output (A10) Address output (A10) General input/output (PE10) • Bit 9—PE9 Mode Bit (PE9MD): Selects the function of pin PE9/A9. Description Bit 9: PE9MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A9) (Initial value) General input/output (PE9) (Initial value) General input/output (PE9) (Initial value) 1 Address output (A9) Address output (A9) General input/output (PE9) • Bit 8—PE8 Mode Bit (PE8MD): Selects the function of pin PE8/A8. Description Bit 8: PE8MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A8) (Initial value) General input/output (PE8) (Initial value) General input/output (PE8) (Initial value) 1 Address output (A8) Address output (A8) General input/output (PE8) • Bit 7—PE7 Mode Bit (PE7MD): Selects the function of pin PE7/A7. Description Bit 7: PE7MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A7) (Initial value) General input/output (PE7) (Initial value) General input/output (PE7) (Initial value) 1 Address output (A7) Address output (A7) General input/output (PE7) 630 • Bit 6—PE6 Mode Bit (PE6MD): Selects the function of pin PE6/A6. Description Bit 6: PE6MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A6) (Initial value) General input/output (PE6) (Initial value) General input/output (PE6) (Initial value) 1 Address output (A6) Address output (A6) General input/output (PE6) • Bit 5—PE5 Mode Bit (PE5MD): Selects the function of pin PE5/A5. Description Bit 5: PE5MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A5) (Initial value) General input/output (PE5) (Initial value) General input/output (PE5) (Initial value) 1 Address output (A5) Address output (A5) General input/output (PE5) • Bit 4—PE4 Mode Bit (PE4MD): Selects the function of pin PE4/A4. Description Bit 4: PE4MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A4) (Initial value) General input/output (PE4) (Initial value) General input/output (PE4) (Initial value) 1 Address output (A4) Address output (A4) General input/output (PE4) • Bit 3—PE3 Mode Bit (PE3MD): Selects the function of pin PE3/A3. Description Bit 3: PE3MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A3) (Initial value) General input/output (PE3) (Initial value) General input/output (PE3) (Initial value) 1 Address output (A3) Address output (A3) General input/output (PE3) 631 • Bit 2—PE2 Mode Bit (PE2MD): Selects the function of pin PE2/A2. Description Bit 2: PE2MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A2) (Initial value) General input/output (PE2) (Initial value) General input/output (PE2) (Initial value) 1 Address output (A2) Address output (A2) General input/output (PE2) • Bit 1—PE1 Mode Bit (PE1MD): Selects the function of pin PE1/A1. Description Bit 1: PE1MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A1) (Initial value) General input/output (PE1) (Initial value) General input/output (PE1) (Initial value) 1 Address output (A1) Address output (A1) General input/output (PE1) • Bit 0—PE0 Mode Bit (PE0MD): Selects the function of pin PE0/A0. Description Bit 0: PE0MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A0) (Initial value) General input/output (PE0) (Initial value) General input/output (PE0) (Initial value) 1 Address output (A0) Address output (A0) General input/output (PE0) 632 18.3.12 Port F IO Register (PFIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PF15 IOR PF14 IOR PF13 IOR PF12 IOR PF11 IOR PF10 IOR PF9 IOR PF8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PF7 IOR PF6 IOR PF5 IOR PF4 IOR PF3 IOR PF2 IOR PF1 IOR PF0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port F IO register (PFIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port F. Bits PF15IOR to PF0IOR correspond to pins PF15/BREQ to PF0/A16. PFIOR is enabled when port F pins function as general input/output pins (PF15 to PF0), and disabled otherwise. When port F pins function as PF15 to PF0, a pin becomes an output when the corresponding bit in PFIOR is set to 1, and an input when the bit is cleared to 0. PFIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 633 18.3.13 Port F Control Registers H and L (PFCRH, PFCRL) Port F control registers H and L (PFCRH, PFCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port F and the function of the CK pin. PFCRH selects the functions of the pins for the upper 8 bits of port F, and PFCRL selects the functions of the pins for the lower 8 bits. PFCRH and PFCRL are initialized to H'0015 and H'5000, respectively, by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. Port F Control Register H (PFCRH) Bit: 15 14 13 12 11 10 9 8 CKHIZ PF15MD — PF14MD — PF13MD — PF12MD 0 0 0 0 0 0 0 0 R/W R/W R R/W R R/W R R/W 7 6 5 4 3 2 1 0 — PF11MD — PF10MD — PF9MD — PF8MD Initial value: 0 0 0 1 0 1 0 1 R/W: R R/W R R/W R R/W R R/W Initial value: R/W: Bit: • Bit 15—CKHIZ Bit: Selects the function of pin CK. Bit: CKHIZ Description 0 CK pin output 1 CK pin Hi-Z (Initial value) • Bit 14—PF15 Mode Bit (PF15MD): Selects the function of pin PF15/BREQ. Description Bit 14: PF15MD Expanded Mode Single-Chip Mode 0 General input/output (PF15) (Initial value) General input/output (PF15) (Initial value) 1 Bus request input (BREQ) General input/output (PF15) 634 • Bit 13—Reserved: This bit always reads 0. The write value should always be 0. • Bit 12—PF14 Mode Bit (PF14MD): Selects the function of pin PF14/BACK. Description Bit 12: PF14MD Expanded Mode Single-Chip Mode 0 General input/output (PF14) (Initial value) General input/output (PF14) (Initial value) 1 Bus acknowledge output (BACK) General input/output (PF14) • Bit 11—Reserved: This bit always reads 0. The write value should always be 0. • Bit 10—PF13 Mode Bit (PF13MD): Selects the function of pin PF13/CS3. Description Bit 10: PF13MD Expanded Mode Single-Chip Mode 0 General input/output (PF13) (Initial value) General input/output (PF13) (Initial value) 1 Chip select output (CS3) General input/output (PF13) • Bit 9—Reserved: This bit always reads 0. The write value should always be 0. • Bit 8—PF12 Mode Bit (PF12MD): Selects the function of pin PF12/CS2. Description Bit 8: PF12MD Expanded Mode Single-Chip Mode 0 General input/output (PF12) (Initial value) General input/output (PF12) (Initial value) 1 Chip select output (CS2) General input/output (PF12) • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—PF11 Mode Bit (PF11MD): Selects the function of pin PF11/CS1. Description Bit 6: PF11MD Expanded Mode Single-Chip Mode 0 General input/output (PF11) (Initial value) General input/output (PF11) (Initial value) 1 Chip select output (CS1) General input/output (PF11) 635 • Bit 5—Reserved: This bit always reads 0. The write value should always be 0. • Bit 4—PF10 Mode Bit (PF10MD): Selects the function of pin PF10/CS0. Description Bit 4: PF10MD Expanded Mode Single-Chip Mode 0 General input/output (PF10) General input/output (PF10) 1 Chip select output (CS0) (Initial value) General input/output (PF10) (Initial value) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PF9 Mode Bit (PF9MD): Selects the function of pin PF9/RD. Description Bit 2: PF9MD Expanded Mode Single-Chip Mode 0 General input/output (PF9) General input/output (PF9) 1 Read output (RD) (Initial value) General input/output (PF9) (Initial value) • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. • Bit 0—PF8 Mode Bit (PF8MD): Selects the function of pin PF8/WAIT. Description Bit 0: PF8MD Expanded Mode Single-Chip Mode 0 General input/output (PF8) General input/output (PF8) 1 Wait state input (WAIT) (Initial value) General input/output (PF8) (Initial value) 636 Port F Control Register L (PFCRL) Bit: 15 14 13 12 11 — PF7MD — Initial value: 0 1 0 1 0 R/W: R R/W R R/W Bit: 7 6 5 — PF3MD Initial value: 0 R/W: R 10 9 8 — PF4MD 0 0 0 R/W R/W R R/W 4 3 2 1 0 — PF2MD — PF1MD — PF0MD 0 0 0 0 0 0 0 R/W R R/W R R/W R R/W PF6MD PF5MD1 PF5MD0 • Bit 15—Reserved: This bit always reads 0. The write value should always be 0. • Bit 14—PF7 Mode Bit (PF7MD): Selects the function of pin PF7/WRH. Description Bit 14: PF7MD Expanded Mode Single-Chip Mode 0 General input/output (PF7) General input/output (PF7) 1 Upper write output (WRH) (Initial value) General input/output (PF7) (Initial value) • Bit 13—Reserved: This bit always reads 0. The write value should always be 0. • Bit 12—PF6 Mode Bit (PF6MD): Selects the function of pin PF6/WRL. Description Bit 12: PF6MD Expanded Mode Single-Chip Mode 0 General input/output (PF6) General input/output (PF6) 1 Lower write output (WRL) (Initial value) General input/output (PF6) (Initial value) 637 • Bits 11 and 10—PF5 Mode Bits 1 and 0 (PF5MD1, PF5MD0): These bits select the function of pin PF5/A21/POD. Description Bit 11: PF5MD1 Bit 10: PF5MD0 Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 0 Address output (A21) (Initial value) General input/output (PF5) (Initial value) General input/output (PF5) (Initial value) 1 Address output (A21) Address output (A21) General input/output (PF5) 0 Address output (A21) Port output disable input (POD) Port output disable input (POD) 1 Reserved (Do not set) Reserved (Do not set) Reserved (Do not set) 1 • Bit 9—Reserved: This bit always reads 0. The write value should always be 0. • Bit 8—PF4 Mode Bit (PF4MD): Selects the function of pin PF4/A20. Description Bit 8: PF4MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A20) (Initial value) General input/output (PF4) (Initial value) General input/output (PF4) (Initial value) 1 Address output (A20) Address output (A20) General input/output (PF4) • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—PF3 Mode Bit (PF3MD): Selects the function of pin PF3/A19. Description Bit 6: PF3MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A19) (Initial value) General input/output (PF3) (Initial value) General input/output (PF3) (Initial value) 1 Address output (A19) Address output (A19) General input/output (PF3) 638 • Bit 5—Reserved: This bit always reads 0. The write value should always be 0. • Bit 4—PF2 Mode Bit (PF2MD): Selects the function of pin PF2/A18. Description Bit 4: PF2MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A18) (Initial value) General input/output (PF2) (Initial value) General input/output (PF2) (Initial value) 1 Address output (A18) Address output (A18) General input/output (PF2) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PF1 Mode Bit (PF1MD): Selects the function of pin PF1/A17. Description Bit 2: PF1MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A17) (Initial value) General input/output (PF1) (Initial value) General input/output (PF1) (Initial value) 1 Address output (A17) Address output (A17) General input/output (PF1) • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. • Bit 0—PF0 Mode Bit (PF0MD): Selects the function of pin PF0/A16. Description Bit 0: PF0MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A16) (Initial value) General input/output (PF0) (Initial value) General input/output (PF0) (Initial value) 1 Address output (A16) Address output (A16) General input/output (PF0) 639 18.3.14 Port G IO Register (PGIOR) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W PG3IOR PG2IOR PG1IOR PG0IOR The port G IO register (PGIOR) is a 16-bit readable/writable register that selects the input/output direction of the 4 pins in port G. Bits PG3IOR to PG0IOR correspond to pins PG3/IRQ3/ADTRG0 to PG0/PULS7/HRxD0/HRxD1. When port G pins function as PG3 to PG0, a pin becomes an output when the corresponding bit in PGIOR is set to 1, and an input when the bit is cleared to 0. PGIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 640 18.3.15 Port G Control Register (PGCR) The port G control register (PGCR) is a 16-bit readable/writable register that selects the functions of the 4 multiplex pins in port G. PGCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 PG3MD1 PG3MD0 PG2MD1 PG2MD0 Initial value: R/W: — PG1MD PG0MD1 PG0MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R R/W R/W R/W • Bits 15 to 8—Reserved: These bits always read 0. The write value should always be 0. • Bits 7 and 6—PG3 Mode Bits 1 and 0 (PG3MD1, PG3MD0): These bits select the function of pin PG3/IRQ3/ADTRG0. Bit 7: PG3MD1 Bit 6: PG3MD0 Description 0 0 General input/output (PG3) 1 Interrupt request input (IRQ3) 0 A/D conversion trigger input (ADTRG0) 1 Reserved (Do not set) 1 (Initial value) • Bits 5 and 4—PG2 Mode Bits 1 and 0 (PG2MD1, PG2MD0): These bits select the function of pin PG2/IRQ2. Bit 5: PG2MD1 Bit 4: PG2MD0 Description 0 0 General input/output (PG2) 1 Interrupt request input (IRQ2) 0 Reserved (Do not set) 1 Reserved (Do not set) 1 (Initial value) 641 • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PG1 Mode Bit (PG1MD): Selects the function of pin PG1/IRQ1. Bit 2: PG1MD Description 0 General input/output (PG1) 1 Interrupt request input (IRQ1) (Initial value) • Bits 1 and 0—PG0 Mode Bits 1 and 0 (PG0MD1, PG2MD0): These bits select the function of pin PG0/PULS7/HRxD0. Bit 1: PG0MD1 Bit 0: PG0MD0 Description 0 0 General input/output (PG0) 1 APC pulse output (PULS7) 0 HCAN receive data input (HRxD) 1 Reserved (Do not set) 1 642 (Initial value) 18.3.16 Port H IO Register (PHIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PH15 IOR PH14 IOR PH13 IOR PH12 IOR PH11 IOR PH10 IOR PH9 IOR PH8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PH7 IOR PH6 IOR PH5 IOR PH4 IOR PH3 IOR PH2 IOR PH1 IOR PH0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port H IO register (PHIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port H. Bits PH15IOR to PH0IOR correspond to pins PH15/D15 to PH0/D0. PHIOR is enabled when port H pins function as general input/output pins (PH15 to PH0), and disabled otherwise. When port H pins function as PH15 to PH0, a pin becomes an output when the corresponding bit in PHIOR is set to 1, and an input when the bit is cleared to 0. PHIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 643 18.3.17 Port H Control Register (PHCR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PH15 MD PH14 MD PH13 MD PH12 MD PH11 MD PH10 MD PH9 MD PH8 MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PH7 MD PH6 MD PH5 MD PH4 MD PH3 MD PH2 MD PH1 MD PH0 MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port H control register (PHCR) is a 16-bit readable/writable register that selects the functions of the 16 multiplex pins in port H. PHCR settings are not valid in all operating modes. 1. Expanded mode with on-chip ROM disabled (area 0: 8-bit bus) Port H pins D0 to D7 function as data input/output pins, and PHCR settings are invalid. 2. Expanded mode with on-chip ROM disabled (area 0: 16-bit bus) Port H pins function as data input/output pins, and PHCR settings are invalid. 3. Expanded mode with on-chip ROM enabled Port H pins are multiplexed as data input/output pins and general input/output pins. PHCR settings are valid. 4. Single-chip mode Port H pins function as general input/output pins, and PHCR settings are invalid. PHCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 644 • Bit 15—PH15 Mode Bit (PH15MD): Selects the function of pin PH15/D15. Description Bit 15: PH15MD Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode 0 General input/output Data input/output (PH15) (D15) (Initial value) (Initial value) General input/output General input/output (PH15) (PH15) (Initial value) (Initial value) 1 Data input/output (D15) Data input/output (D15) Data input/output (D15) General input/output (PH15) • Bit 14—PH14 Mode Bit (PH14MD): Selects the function of pin PH14/D14. Description Bit 14: PH14MD Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode 0 General input/output Data input/output (PH14) (D14) (Initial value) (Initial value) General input/output General input/output (PH14) (PH14) (Initial value) (Initial value) 1 Data input/output (D14) Data input/output (D14) Data input/output (D14) General input/output (PH14) • Bit 13—PH13 Mode Bit (PH13MD): Selects the function of pin PH13/D13. Description Bit 13: PH13MD Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode 0 General input/output Data input/output (PH13) (D13) (Initial value) (Initial value) General input/output General input/output (PH13) (PH13) (Initial value) (Initial value) 1 Data input/output (D13) Data input/output (D13) Data input/output (D13) General input/output (PH13) 645 • Bit 12—PH12 Mode Bit (PH12MD): Selects the function of pin PH12/D12. Description Bit 12: PH12MD Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode 0 General input/output Data input/output (PH12) (D12) (Initial value) (Initial value) General input/output General input/output (PH12) (PH12) (Initial value) (Initial value) 1 Data input/output (D12) Data input/output (D12) Data input/output (D12) General input/output (PH12) • Bit 11—PH11 Mode Bit (PH11MD): Selects the function of pin PH11/D11. Description Bit 11: PH11MD Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode 0 General input/output Data input/output (PH11) (D11) (Initial value) (Initial value) General input/output General input/output (PH11) (PH11) (Initial value) (Initial value) 1 Data input/output (D11) Data input/output (D11) Data input/output (D11) General input/output (PH11) • Bit 10—PH10 Mode Bit (PH10MD): Selects the function of pin PH10/D10. Description Bit 10: PH10MD Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode 0 General input/output Data input/output (PH10) (D10) (Initial value) (Initial value) General input/output General input/output (PH10) (PH10) (Initial value) (Initial value) 1 Data input/output (D10) Data input/output (D10) 646 Data input/output (D10) General input/output (PH10) • Bit 9—PH9 Mode Bit (PH9MD): Selects the function of pin PH9/D9. Description Bit 9: PH9MD Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode 0 General input/output Data input/output (PH9) (D9) (Initial value) (Initial value) General input/output General input/output (PH9) (PH9) (Initial value) (Initial value) 1 Data input/output (D9) Data input/output (D9) Data input/output (D9) General input/output (PH9) • Bit 8—PH8 Mode Bit (PH8MD): Selects the function of pin PH8/D8. Description Bit 8: PH8MD Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode 0 General input/output Data input/output (PH8) (D8) (Initial value) (Initial value) General input/output General input/output (PH8) (PH8) (Initial value) (Initial value) 1 Data input/output (D8) Data input/output (D8) Data input/output (D8) General input/output (PH8) • Bit 7—PH7 Mode Bit (PH7MD): Selects the function of pin PH7/D7. Description Bit 7: PH7MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D7) (Initial value) General input/output (PH7) (Initial value) General input/output (PH7) (Initial value) 1 Data input/output (D7) Data input/output (D7) General input/output (PH7) 647 • Bit 6—PH6 Mode Bit (PH6MD): Selects the function of pin PH6/D6. Description Bit 6: PH6MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D6) (Initial value) General input/output (PH6) (Initial value) General input/output (PH6) (Initial value) 1 Data input/output (D6) Data input/output (D6) General input/output (PH6) • Bit 5—PH5 Mode Bit (PH5MD): Selects the function of pin PH5/D5. Description Bit 5: PH5MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D5) (Initial value) General input/output (PH5) (Initial value) General input/output (PH5) (Initial value) 1 Data input/output (D5) Data input/output (D5) General input/output (PH5) • Bit 4—PH4 Mode Bit (PH4MD): Selects the function of pin PH4/D4. Description Bit 4: PH4MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D4) (Initial value) General input/output (PH4) (Initial value) General input/output (PH4) (Initial value) 1 Data input/output (D4) Data input/output (D4) General input/output (PH4) • Bit 3—PH3 Mode Bit (PH3MD): Selects the function of pin PH3/D3. Description Bit 3: PH3MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D3) (Initial value) General input/output (PH3) (Initial value) General input/output (PH3) (Initial value) 1 Data input/output (D3) Data input/output (D3) General input/output (PH3) 648 • Bit 2—PH2 Mode Bit (PH2MD): Selects the function of pin PH2/D2. Description Bit 2: PH2MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D2) (Initial value) General input/output (PH2) (Initial value) General input/output (PH2) (Initial value) 1 Data input/output (D2) Data input/output (D2) General input/output (PH2) • Bit 1—PH1 Mode Bit (PH1MD): Selects the function of pin PH1/D1. Description Bit 1: PH1MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D1) (Initial value) General input/output (PH1) (Initial value) General input/output (PH1) (Initial value) 1 Data input/output (D1) Data input/output (D1) General input/output (PH1) • Bit 0—PH0 Mode Bit (PH0MD): Selects the function of pin PH0/D0. Description Bit 0: PH0MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D0) (Initial value) General input/output (PH0) (Initial value) General input/output (PH0) (Initial value) 1 Data input/output (D0) Data input/output (D0) General input/output (PH0) 649 18.3.18 Port J IO Register (PJIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PJ15 IOR PJ14 IOR PJ13 IOR PJ12 IOR PJ11 IOR PJ10 IOR PJ9 IOR PJ8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PJ7 IOR PJ6 IOR PJ5 IOR PJ4 IOR PJ3 IOR PJ2 IOR PJ1 IOR PJ0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port J IO register (PJIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port J. Bits PJ15IOR to PJ0IOR correspond to pins PJ15/TI9F to PJ0/TIO2A. PJIOR is enabled when port J pins function as general input/output pins (PJ15 to PJ0) or ATU input/output pins, and disabled otherwise. When port J pins function as PJ15 to PJ0 or ATU input/output pins, a pin becomes an output when the corresponding bit in PJIOR is set to 1, and an input when the bit is cleared to 0. PJIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 650 18.3.19 Port J Control Registers H and L (PJCRH, PJCRL) Port J control registers H and L (PJCRH, PJCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port J. PJCRH selects the functions of the pins for the upper 8 bits of port J, and PJCRL selects the functions of the pins for the lower 8 bits. PJCRH and PJCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. Port J Control Register H (PJCRH) Bit: 15 14 13 12 11 10 9 8 — PJ15MD — PJ14MD — PJ13MD — PJ12MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Bit: 7 6 5 4 3 2 1 0 — PJ11MD — PJ10MD — PJ9MD — PJ8MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W • Bit 15—Reserved: This bit always reads 0. The write value should always be 0. • Bit 14—PJ15 Mode Bit (PJ15MD): Selects the function of pin PJ15/TI9F. Bit 14: PJ15MD Description 0 General input/output (PJ15) 1 ATU event counter input (TI9F) (Initial value) • Bit 13—Reserved: This bit always reads 0. The write value should always be 0. • Bit 12—PJ14 Mode Bit (PJ14MD): Selects the function of pin PJ14/TI9E. Bit 12: PJ14MD Description 0 General input/output (PJ14) 1 ATU event counter input (TI9E) (Initial value) 651 • Bit 11—Reserved: This bit always reads 0. The write value should always be 0. • Bit 10—PJ13 Mode Bit (PJ13MD): Selects the function of pin PJ13/TI9D. Bit 10: PJ13MD Description 0 General input/output (PJ13) 1 ATU event counter input (TI9D) (Initial value) • Bit 9—Reserved: This bit always reads 0. The write value should always be 0. • Bit 8—PJ12 Mode Bit (PJ12MD): Selects the function of pin PJ12/TI9C. Bit 8: PJ12MD Description 0 General input/output (PJ12) 1 ATU event counter input (TI9C) (Initial value) • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—PJ11 Mode Bit (PJ11MD): Selects the function of pin PJ11/TI9B. Bit 6: PJ11MD Description 0 General input/output (PJ11) 1 ATU event counter input (TI9B) (Initial value) • Bit 5—Reserved: This bit always reads 0. The write value should always be 0. • Bit 4—PJ10 Mode Bit (PJ10MD): Selects the function of pin PJ10/TI9A. Bit 4: PJ10MD Description 0 General input/output (PJ10) 1 ATU event counter input (TI9A) (Initial value) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PJ9 Mode Bit (PJ9MD): Selects the function of pin PJ9/TIO5D. Bit 2: PJ9MD Description 0 General input/output (PJ9) 1 ATU input capture input/output compare output (TIO5D) 652 (Initial value) • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. • Bit 0—PJ8 Mode Bit (PJ8MD): Selects the function of pin PJ8/TIO5C. Bit 0: PJ8MD Description 0 General input/output (PJ8) 1 ATU input capture input/output compare output (TIO5C) (Initial value) Port J Control Register L (PJCRL) Bit: 15 14 13 12 11 10 9 8 — PJ7MD — PJ6MD — PJ5MD — PJ4MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Bit: 7 6 5 4 3 2 1 0 — PJ3MD — PJ2MD — PJ1MD — PJ0MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W • Bit 15—Reserved: This bit always reads 0. The write value should always be 0. • Bit 14—PJ7 Mode Bit (PJ7MD): Selects the function of pin PJ7/TIO2H. Bit 14: PJ7MD Description 0 General input/output (PJ7) 1 ATU input capture input/output compare output (TIO2H) (Initial value) • Bit 13—Reserved: This bit always reads 0. The write value should always be 0. • Bit 12—PJ6 Mode Bit (PJ6MD): Selects the function of pin PJ6/TIO2G. Bit 12: PJ6MD Description 0 General input/output (PJ6) 1 ATU input capture input/output compare output (TIO2G) (Initial value) 653 • Bit 11—Reserved: This bit always reads 0. The write value should always be 0. • Bit 10—PJ5 Mode Bit (PJ5MD): Selects the function of pin PJ5/TIO2F. Bit 10: PJ5MD Description 0 General input/output (PJ5) 1 ATU input capture input/output compare output (TIO2F) (Initial value) • Bit 9—Reserved: This bit always reads 0. The write value should always be 0. • Bit 8—PJ4 Mode Bit (PJ4MD): Selects the function of pin PJ4/TIO2E. Bit 8: PJ4MD Description 0 General input/output (PJ4) 1 ATU input capture input/output compare output (TIO2E) (Initial value) • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—PJ3 Mode Bit (PJ3MD): Selects the function of pin PJ3/TIO2D. Bit 6: PJ3MD Description 0 General input/output (PJ3) 1 ATU input capture input/output compare output (TIO2D) (Initial value) • Bit 5—Reserved: This bit always reads 0. The write value should always be 0. • Bit 4—PJ2 Mode Bit (PJ2MD): Selects the function of pin PJ2/TIO2C. Bit 4: PJ2MD Description 0 General input/output (PJ2) 1 ATU input capture input/output compare output (TIO2C) (Initial value) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PJ1 Mode Bit (PJ1MD): Selects the function of pin PJ1/TIO2B. Bit 2: PJ1MD Description 0 General input/output (PJ1) 1 ATU input capture input/output compare output (TIO2B) 654 (Initial value) • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. • Bit 0—PJ0 Mode Bit (PJ0MD): Selects the function of pin PJ0/TIO2A. Bit 0: PJ0MD Description 0 General input/output (PJ0) 1 ATU input capture input/output compare output (TIO2A) 18.3.20 (Initial value) Port K IO Register (PKIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PK15 IOR PK14 IOR PK13 IOR PK12 IOR PK11 IOR PK10 IOR PK9 IOR PK8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PK7 IOR PK6 IOR PK5 IOR PK4 IOR PK3 IOR PK2 IOR PK1 IOR PK0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port K IO register (PKIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port K. Bits PK15IOR to PK0IOR correspond to pins PK15/TO8P to PK0/TO8A. PKIOR is enabled when port K pins function as general input/output pins (PK15 to PK0), and disabled otherwise. When port K pins function as PK15 to PK0, a pin becomes an output when the corresponding bit in PKIOR is set to 1, and an input when the bit is cleared to 0. PKIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 655 18.3.21 Port K Control Registers H and L (PKCRH, PKCRL) Port K control registers H and L (PKCRH, PKCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port K. PKCRH selects the functions of the pins for the upper 8 bits of port K, and PKCRL selects the functions of the pins for the lower 8 bits. PKCRH and PKCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. Port K Control Register H (PKCRH) Bit: 15 14 13 12 11 10 9 8 — PK15 MD — PK14 MD — PK13 MD — PK12 MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Bit: 7 6 5 4 3 2 1 0 — PK11 MD — PK10 MD — PK9 MD — PK8 MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W • Bit 15—Reserved: This bit always reads 0. The write value should always be 0. • Bit 14—PK15 Mode Bit (PK15MD): Selects the function of pin PK15/TO8P. Bit 14: PK15MD Description 0 General input/output (PK15) 1 ATU one-shot pulse output (TO8P) (Initial value) • Bit 13—Reserved: This bit always reads 0. The write value should always be 0. • Bit 12—PK14 Mode Bit (PK14MD): Selects the function of pin PK14/TO8O. Bit 12: PK14MD Description 0 General input/output (PK14) 1 ATU one-shot pulse output (TO8O) • Bit 11—Reserved: This bit always reads 0. The write value should always be 0. 656 (Initial value) • Bit 10—PK13 Mode Bit (PK13MD): Selects the function of pin PK13/TO8N. Bit 10: PK13MD Description 0 General input/output (PK13) 1 ATU one-shot pulse output (TO8N) (Initial value) • Bit 9—Reserved: This bit always reads 0. The write value should always be 0. • Bit 8—PK12 Mode Bit (PK12MD): Selects the function of pin PK12/TO8M. Bit 8: PK12MD Description 0 General input/output (PK12) 1 ATU one-shot pulse output (TO8M) (Initial value) • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—PK11 Mode Bit (PK11MD): Selects the function of pin PK11/TO8L. Bit 6: PK11MD Description 0 General input/output (PK11) 1 ATU one-shot pulse output (TO8L) (Initial value) • Bit 5—Reserved: This bit always reads 0. The write value should always be 0. • Bit 4—PK10 Mode Bit (PK10MD): Selects the function of pin PK10/TO8K. Bit 4: PK10MD Description 0 General input/output (PK10) 1 ATU one-shot pulse output (TO8K) (Initial value) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PK9 Mode Bit (PK9MD): Selects the function of pin PK9/TO8J. Bit 2: PK9MD Description 0 General input/output (PK9) 1 ATU one-shot pulse output (TO8J) (Initial value) • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. 657 • Bit 0—PK8 Mode Bit (PK8MD): Selects the function of pin PK8/TO8I. Bit 0: PK8MD Description 0 General input/output (PK8) 1 ATU one-shot pulse output (TO8I) (Initial value) Port K Control Register L (PKCRL) Bit: 15 14 13 12 11 10 9 8 — PK7MD — PK6MD — PK5MD — PK4MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Bit: 7 6 5 4 3 2 1 0 — PK3MD — PK2MD — PK1MD — PK0MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W • Bit 15—Reserved: This bit always reads 0. The write value should always be 0. • Bit 14—PK7 Mode Bit (PK7MD): Selects the function of pin PK7/TO8H. Bit 14: PK7MD Description 0 General input/output (PK7) 1 ATU one-shot pulse output (TO8H) (Initial value) • Bit 13—Reserved: This bit always reads 0. The write value should always be 0. • Bit 12—PK6 Mode Bit (PK6MD): Selects the function of pin PK6/TO8G. Bit 12: PK6MD Description 0 General input/output (PK6) 1 ATU one-shot pulse output (TO8G) • Bit 11—Reserved: This bit always reads 0. The write value should always be 0. 658 (Initial value) • Bit 10—PK5 Mode Bit (PK5MD): Selects the function of pin PK5/TO8F. Bit 10: PK5MD Description 0 General input/output (PK5) 1 ATU one-shot pulse output (TO8F) (Initial value) • Bit 9—Reserved: This bit always reads 0. The write value should always be 0. • Bit 8—PK4 Mode Bit (PK4MD): Selects the function of pin PK4/TO8E. Bit 8: PK4MD Description 0 General input/output (PK4) 1 ATU one-shot pulse output (TO8E) (Initial value) • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—PK3 Mode Bit (PK3MD): Selects the function of pin PK3/TO8D. Bit 6: PK3MD Description 0 General input/output (PK3) 1 ATU one-shot pulse output (TO8D) (Initial value) • Bit 5—Reserved: This bit always reads 0. The write value should always be 0. • Bit 4—PK2 Mode Bit (PK2MD): Selects the function of pin PK2/TO8C. Bit 4: PK2MD Description 0 General input/output (PK2) 1 ATU one-shot pulse output (TO8C) (Initial value) • Bit 3—Reserved: This bit always reads 0. The write value should always be 0. • Bit 2—PK1 Mode Bit (PK1MD): Selects the function of pin PK1/TO8B. Bit 2: PK1MD Description 0 General input/output (PK1) 1 ATU one-shot pulse output (TO8B) (Initial value) • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. 659 • Bit 0—PK0 Mode Bit (PK0MD): Selects the function of pin PK0/TO8A. Bit 0: PK0MD Description 0 General input/output (PK0) 1 ATU one-shot pulse output (TO8A) 18.3.22 (Initial value) Port K Invert Register (PKIR) Bit: 15 14 13 12 11 10 PK15IR PK14IR PK13IR PK12IR PK11IR PK10IR Initial value: R/W: Bit: Initial value: R/W: 9 8 PK9IR PK8IR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PK7IR PK6IR PK5IR PK4IR PK3IR PK2IR PK1IR PK0IR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port K invert register (PKIR) is a 16-bit readable/writable register that sets the port K inversion function. Bits PK15IR to PK0IR correspond to pins PK15/TO8P to PK0/TO8A. PKIR is enabled when port K pins function as ATU outputs, and disabled otherwise. When port K pins function as ATU outputs, the value of a pin is inverted when the corresponding bit in PKIR is set to 1. PKIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PKnIR Description 0 Value is not inverted 1 Value is inverted n = 15 to 0 660 (Initial value) Section 19 I/O Ports (I/O) 19.1 Overview The SH7052F/SH7053F/SH7054F has 10 ports: A, B, C, D, E, F, G, H, J and K, all supporting both input and output. Ports A B, E, F, H, J and K are 16-bit ports, port C is a 5-bit port, ports D is a 14-bit ports, and port G is a 4-bit port. All the port pins are multiplexed as general input/output pins and special function pins. The functions of the multiplex pins are selected by means of the pin function controller (PFC). Each port is provided with a data register for storing the pin data. 661 19.2 Port A Port A is an input/output port with the 16 pins shown in figure 19.1. PA15 (I/O) /RxD0 (input) PA14 (I/O) /TxD0 (output) PA13 (I/O) /TIO5B (I/O) PA12 (I/O) /TIO5A (I/O) PA11 (I/O) /TIO4D (I/O) PA10 (I/O) /TIO4C (I/O) PA9 (I/O) /TIO4B (I/O) PA8 (I/O) /TIO4A (I/O) Port A PA7 (I/O) /TIO3D (I/O) PA6 (I/O) /TIO3C (I/O) PA5 (I/O) /TIO3B (I/O) PA4 (I/O) /TIO3A (I/O) PA3 (I/O) /TIOD (input) PA2 (I/O) /TIOC (input) PA1 (I/O) /TIOB (input) PA0 (I/O) /TIOA (input) Figure 19.1 Port A 19.2.1 Register Configuration The port A register configuration is shown in table 19.1. Table 19.1 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port A data register PADR R/W H'0000 H'FFFFF726 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 662 19.2.2 Port A Data Register (PADR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PA15 DR PA14 DR PA13 DR PA12 DR PA11 DR PA10 DR PA9 DR PA8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PA7 DR PA6 DR PA5 DR PA4 DR PA3 DR PA2 DR PA1 DR PA0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port A data register (PADR) is a 16-bit readable/writable register that stores port A data. Bits PA15DR to PA0DR correspond to pins PA15/RxD0 to PA0/TI0A. When a pin functions as a general output, if a value is written to PADR, that value is output directly from the pin, and if PADR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PADR is read the pin state, not the register value, is returned directly. If a value is written to PADR, although that value is written into PADR it does not affect the pin state. Table 19.2 summarizes port A data register read/write operations. PADR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Table 19.2 Port A Data Register (PADR) Read/Write Operations Bits 15 to 0: PAIOR Pin Function Read Write 0 General input Pin state Value is written to PADR, but does not affect pin state Other than general input Pin state Value is written to PADR, but does not affect pin state General output PADR value Write value is output from pin Other than general output PADR value Value is written to PADR, but does not affect pin state 1 663 19.3 Port B Port B is an input/output port with the 16 pins shown in figure 19.2. PB15 (I/O) /PULS5 (output) /SCK2 (I/O) PB14 (I/O) /SCK1 (I/O) /TCLKB (input) /TI10 (input) PB13 (I/O) /SCK0 (I/O) PB12 (I/O) /TCLKA (input) /UBCTRG (output) PB11 (I/O) /RxD4 (input) /HRxD (input) /TO8H (output) PB10 (I/O) /TxD4 (output) /HTxD (output) /TO8G (output) PB9 (I/O) /RxD3 (input) /TO8F (output) PB8 (I/O) /TxD3 (output) /TO8E (output) Port B PB7 (I/O) /TO7D (output) /TO8D (output) PB6 (I/O) /TO7C (output) /TO8C (output) PB5 (I/O) /TO7B (output) /TO8B (output) PB4 (I/O) /TO7A (output) /TO8A (output) PB3 (I/O) /TO6D (output) PB2 (I/O) /TO6C (output) PB1 (I/O) /TO6B (output) PB0 (I/O) /TO6A (output) Figure 19.2 Port B 19.3.1 Register Configuration The port B register configuration is shown in table 19.3. Table 19.3 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port B data register PBDR R/W H'0000 H'FFFFF738 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 664 19.3.2 Port B Data Register (PBDR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PB15 DR PB14 DR PB13 DR PB12 DR PB11 DR PB10 DR PB9 DR PB8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7 DR PB6 DR PB5 DR PB4 DR PB3 DR PB2 DR PB1 DR PB0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port B data register (PBDR) is a 16-bit readable/writable register that stores port B data. Bits PB15DR to PB0DR correspond to pins PB15/PULS5/SCK2 to PB0/TO6A. When a pin functions as a general output, if a value is written to PBDR, that value is output directly from the pin, and if PBDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PBDR is read the pin state, not the register value, is returned directly. If a value is written to PBDR, although that value is written into PBDR it does not affect the pin state. Table 19.4 summarizes port B data register read/write operations. PBDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Table 19.4 Port B Data Register (PBDR) Read/Write Operations Bits 15 to 0: PBIOR Pin Function Read Write 0 General input Pin state Value is written to PBDR, but does not affect pin state Other than general input Pin state Value is written to PBDR, but does not affect pin state General output PBDR value Write value is output from pin Other than general output PBDR value Value is written to PBDR, but does not affect pin state 1 665 19.4 Port C Port C is an input/output port with the 5 pins shown in figure 19.3. PC4 (I/O) /IRQ0 (input) PC3 (I/O) /RxD2 (input) Port C PC2 (I/O) /TxD2 (output) PC1 (I/O) /RxD1 (input) PC0 (I/O) /TxD1 (output) Figure 19.3 Port C 19.4.1 Register Configuration The port C register configuration is shown in table 19.5. Table 19.5 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port C data register PCDR R/W H'0000 H'FFFFF73E 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 19.4.2 Port C Data Register (PCDR) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — PC4 DR PC3 DR PC2 DR PC1 DR PC0 DR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W The port C data register (PCDR) is a 16-bit readable/writable register that stores port C data. Bits PC4DR to PC0DR correspond to pins PC4/IRQ0 to PC0/TxD1. 666 When a pin functions as a general output, if a value is written to PCDR, that value is output directly from the pin, and if PCDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PCDR is read the pin state, not the register value, is returned directly. If a value is written to PCDR, although that value is written into PCDR it does not affect the pin state. Table 19.6 summarizes port C data register read/write operations. PCDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. • Bits 15 to 5—Reserved: These bits always read 0. The write value should always be 0. Table 19.6 Port C Data Register (PCDR) Read/Write Operations Bits 4 to 0: PCIOR Pin Function Read Write 0 General input Pin state Value is written to PCDR, but does not affect pin state Other than general input Pin state Value is written to PCDR, but does not affect pin state General output PCDR value Write value is output from pin Other than general output PCDR value Value is written to PCDR, but does not affect pin state 1 667 19.5 Port D Port D is an input/output port with the 14 pins shown in figure 19.4. PD13 (I/O) /PULS6 (output) / HTxD (output) PD12 (I/O) /PULS4 (output) PD11 (I/O) /PULS3 (output) PD10 (I/O) /PULS2 (output) PD9 (I/O) /PULS1 (output) PD8 (I/O) /PULS0 (output) PD7 (I/O) /TIO1H (I/O) Port D PD6 (I/O) /TIO1G (I/O) PD5 (I/O) /TIO1F (I/O) PD4 (I/O) /TIO1E (I/O) PD3 (I/O) /TIO1D (I/O) PD2 (I/O) /TIO1C (I/O) PD1 (I/O) /TIO1B (I/O) PD0 (I/O) /TIO1A (I/O) Figure 19.4 Port D 19.5.1 Register Configuration The port D register configuration is shown in table 19.7. Table 19.7 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port D data register PDDR R/W H'0000 H'FFFFF746 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 668 19.5.2 Port D Data Register (PDDR) Bit: 15 14 13 12 11 10 9 8 — — PD13 DR PD12 DR PD11 DR PD10 DR PD9 DR PD8 DR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PD7 DR PD6 DR PD5 DR PD4 DR PD3 DR PD2 DR PD1 DR PD0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: The port D data register (PDDR) is a 16-bit readable/writable register that stores port D data. Bits PD13DR to PD0DR correspond to pins PD13/PULS6/HTxD0/HTxD1 to PD0/TIO1A. When a pin functions as a general output, if a value is written to PDDR, that value is output directly from the pin, and if PDDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PDDR is read the pin state, not the register value, is returned directly. If a value is written to PDDR, although that value is written into PDDR it does not affect the pin state. Table 19.8 summarizes port D data register read/write operations. PDDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. • Bits 15 and 14— Reserved: These bits always read 0. The write value should always be 0. Table 19.8 Port D Data Register (PDDR) Read/Write Operations Bits 13 to 0: PDIOR Pin Function Read Write 0 General input Pin state Value is written to PDDR, but does not affect pin state Other than general input Pin state Value is written to PDDR, but does not affect pin state General output PDDR value Write value is output from pin Other than general output PDDR value Value is written to PDDR, but does not affect pin state 1 669 19.6 Port E Port E is an input/output port with the 16 pins shown in figure 19.5. ROM disabled ROM enabled expansion mode expansion mode Port E Singlechip mode A15 (output) PE15 (I/O) /A15 (output) PE15 (I/O) A14 (output) PE14 (I/O) /A14 (output) PE14 (I/O) A13 (output) PE13 (I/O) /A13 (output) PE13 (I/O) A12 (output) PE12 (I/O) /A12 (output) PE12 (I/O) A11 (output) PE11 (I/O) /A11 (output) PE11 (I/O) A10 (output) PE10 (I/O) /A10 (output) PE10 (I/O) A9 (output) PE9 (I/O) /A9 (output) PE9 (I/O) A8 (output) PE8 (I/O) /A8 (output) PE8 (I/O) A7 (output) PE7 (I/O) /A7 (output) PE7 (I/O) A6 (output) PE6 (I/O) /A6 (output) PE6 (I/O) A5 (output) PE5 (I/O) /A5 (output) PE5 (I/O) A4 (output) PE4 (I/O) /A4 (output) PE4 (I/O) A3 (output) PE3 (I/O) /A3 (output) PE3 (I/O) A2 (output) PE2 (I/O) /A2 (output) PE2 (I/O) A1 (output) PE1 (I/O) /A1 (output) PE1 (I/O) A0 (output) PE0 (I/O) /A0 (output) PE0 (I/O) Figure 19.5 Port E 19.6.1 Register Configuration The port E register configuration is shown in table 19.9. Table 19.9 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port E data register PEDR R/W H'0000 H'FFFFF754 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 670 19.6.2 Port E Data Register (PEDR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PE15 DR PE14 DR PE13 DR PE12 DR PE11 DR PE10 DR PE9 DR PE8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PE7 DR PE6 DR PE5 DR PE4 DR PE3 DR PE2 DR PE1 DR PE0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port E data register (PEDR) is a 16-bit readable/writable register that stores port E data. Bits PE15DR to PE0DR correspond to pins PE15/A15 to PE0/A0. When a pin functions as a general output, if a value is written to PEDR, that value is output directly from the pin, and if PEDR is read, the register value is returned directly regardless of the pin state. When the POD pin is driven low, general outputs go to the high-impedance state regardless of the PEDR value. When the POD pin is driven high, the written value is output from the pin. When a pin functions as a general input, if PEDR is read the pin state, not the register value, is returned directly. If a value is written to PEDR, although that value is written into PEDR it does not affect the pin state. Table 19.10 summarizes port E data register read/write operations. PEDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 671 Table 19.10 Port E Data Register (PEDR) Read/Write Operations Bits 15 to 0: PEIOR Pin Function Read Write 0 General input Pin state Value is written to PEDR, but does not affect pin state Other than general input Pin state Value is written to PEDR, but does not affect pin state General output PEDR value Write value is output from pin (POD pin = high) 1 High impedance regardless of PEDR value (POD pin = low) Other than general output 672 PEDR value Value is written to PEDR, but does not affect pin state 19.7 Port F Port F is an input/output port with the 16 pins shown in figure 19.6. ROM disabled ROM enabled expansion mode expansion mode Port F Singlechip mode PF15 (I/O) BREQ (input) PF15 (I/O) PF14 (I/O) BACK (output) PF14 (I/O) PF13 (I/O) CS3 (output) PF13 (I/O) PF12 (I/O) CS2 (output) PF12 (I/O) PF11 (I/O) CS1 (output) PF11 (I/O) PF10 (I/O) CS0 (output) PF10 (I/O) PF9 (I/O) RD (output) PF9 (I/O) PF8 (I/O) WAIT (input) PF8 (I/O) PF7 (I/O) WRH (output) PF7 (I/O) PF6 (I/O) WRL (output) PF6 (I/O) A21 (output) A20 (output) PF5 (I/O) /A21 (output) / POD (input) PF4 (I/O) /A20 (output) PF5 (I/O) / POD (input) PF4 (I/O) A19 (output) PF3 (I/O) /A19 (output) PF3 (I/O) A18 (output) PF2 (I/O) /A18 (output) PF2 (I/O) A17 (output) PF1 (I/O) /A17 (output) PF1 (I/O) A16 (output) PF0 (I/O) /A16 (output) PF0 (I/O) Figure 19.6 Port F 19.7.1 Register Configuration The port F register configuration is shown in table 19.11. Table 19.11 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port F data register PFDR R/W H'0000 H'FFFFF74E 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 673 19.7.2 Port F Data Register (PFDR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PF15 DR PF14 DR PF13 DR PF12 DR PF11 DR PF10 DR PF9 DR PF8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PF7 DR PF6 DR PF5 DR PF4 DR PF3 DR PF2 DR PF1 DR PF0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port F data register (PFDR) is a 16-bit readable/writable register that stores port F data. Bits PF15DR to PF0DR correspond to pins PF15/BREQ to PF0/A16. When a pin functions as a general output, if a value is written to PFDR, that value is output directly from the pin, and if PFDR is read, the register value is returned directly regardless of the pin state. For pins PF0 to PF4, when the POD pin is driven low, general outputs go to the highimpedance state regardless of the PFDR value. When the POD pin is driven high, the written value is output from the pin. When a pin functions as a general input, if PFDR is read the pin state, not the register value, is returned directly. If a value is written to PFDR, although that value is written into PFDR it does not affect the pin state. Table 19.12 summarizes port F data register read/write operations. PFDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 674 Table 19.12 Port F Data Register (PFDR) Read/Write Operations Bits 15 to 5: PFIOR Pin Function Read Write 0 General input Pin state Value is written to PFDR, but does not affect pin state Other than general input Pin state Value is written to PFDR, but does not affect pin state General output PFDR value Write value is output from pin Other than general output PFDR value Value is written to PFDR, but does not affect pin state PFIOR Pin Function Read Write 0 General input Pin state Value is written to PFDR, but does not affect pin state Other than general input Pin state Value is written to PFDR, but does not affect pin state General output PFDR value Write value is output from pin (POD pin = high) 1 Bits 4 to 0: 1 High impedance regardless of PFDR value (POD pin = low) Other than general output PFDR value Value is written to PFDR, but does not affect pin state 675 19.8 Port G Port G is an input/output port with the 4 pins shown in figure 19.7. PG3 (I/O) /IRQ3 (input) /ADTRG0 (input) PG2 (I/O) /IRQ2 (input) Port G PG1 (I/O) /IRQ1 (input) PG0 (I/O) /PULS7 (output) /HRxD (input) Figure 19.7 Port G 19.8.1 Register Configuration The port G register configuration is shown in table 19.13. Table 19.13 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port G data register PGDR R/W H'0000 H'FFFFF764 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 19.8.2 Port G Data Register (PGDR) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — PG3 DR PG2 DR PG1 DR PG0 DR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W The port G data register (PGDR) is a 16-bit readable/writable register that stores port G data. Bits PG3DR to PG0DR correspond to pins PG3/IRQ3/ADTRG0 to PG0/PULS7/HRxD0. 676 When a pin functions as a general output, if a value is written to PGDR, that value is output directly from the pin, and if PGDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PGDR is read the pin state, not the register value, is returned directly. If a value is written to PGDR, although that value is written into PGDR it does not affect the pin state. Table 19.14 summarizes port G data register read/write operations. PGDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. • Bits 15 to 4—Reserved: These bits always read 0. The write value should always be 0. Table 19.14 Port G Data Register (PGDR) Read/Write Operations Bits 3 to 0: PGIOR Pin Function Read Write 0 General input Pin state Value is written to PGDR, but does not affect pin state Other than general input Pin state Value is written to PGDR, but does not affect pin state General output PGDR value Write value is output from pin Other than general output PGDR value Value is written to PGDR, but does not affect pin state 1 677 19.9 Port H Port H is an input/output port with the 16 pins shown in figure 19.8. ROM enabled expansion (Area 0: 8 bits) (Area 0: 16 bits) mode ROM disabled expansion mode Port H PH15 (I/O) / D15 (I/O) D15 (I/O) PH15 (I/O) / PH15 (I/O) D15 (I/O) PH14 (I/O) / D14 (I/O) D14 (I/O) PH14 (I/O) / PH14 (I/O) D14 (I/O) PH13 (I/O) / D13 (I/O) D13 (I/O) PH13 (I/O) / PH13 (I/O) D13 (I/O) PH12 (I/O) / D12 (I/O) D12 (I/O) PH12 (I/O) / PH12 (I/O) D12 (I/O) PH11 (I/O) / D11 (I/O) D11 (I/O) PH11 (I/O) / PH11 (I/O) D11 (I/O) PH10 (I/O) / D10 (I/O) D10 (I/O) PH10 (I/O) / PH10 (I/O) D10 (I/O) PH9 (I/O) / D9 (I/O) D9 (I/O) PH9 (I/O) / D9 (I/O) PH9 (I/O) PH8 (I/O) / D8 (I/O) D8 (I/O) PH8 (I/O) / D8 (I/O) PH8 (I/O) D7 (I/O) PH7 (I/O) / D7 (I/O) PH7 (I/O) D6 (I/O) PH6 (I/O) / D6 (I/O) PH6 (I/O) D5 (I/O) PH5 (I/O) / D5 (I/O) PH5 (I/O) D4 (I/O) PH4 (I/O) / D4 (I/O) PH4 (I/O) D3 (I/O) PH3 (I/O) / D3 (I/O) PH3 (I/O) D2 (I/O) PH2 (I/O) / D2 (I/O) PH2 (I/O) D1 (I/O) PH1 (I/O) / D1 (I/O) PH1 (I/O) D0 (I/O) PH0 (I/O) / D0 (I/O) PH0 (I/O) Figure 19.8 Port H 678 Singlechip mode 19.9.1 Register Configuration The port H register configuration is shown in table 19.15. Table 19.15 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port H data register PHDR R/W H'0000 H'FFFFF72C 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 19.9.2 Port H Data Register (PHDR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PH15 DR PH14 DR PH13 DR PH12 DR PH11 DR PH10 DR PH9 DR PH8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PH7 DR PH6 DR PH5 DR PH4 DR PH3 DR PH2 DR PH1 DR PH0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port H data register (PHDR) is a 16-bit readable/writable register that stores port H data. Bits PH15DR to PH0DR correspond to pins PH15/D15 to PH0/D0. When a pin functions as a general output, if a value is written to PHDR, that value is output directly from the pin, and if PHDR is read, the register value is returned directly regardless of the pin state. When the POD pin is driven low, general outputs go to the high-impedance state regardless of the PHDR value. When the POD pin is driven high, the written value is output from the pin. When a pin functions as a general input, if PHDR is read the pin state, not the register value, is returned directly. If a value is written to PHDR, although that value is written into PHDR it does not affect the pin state. Table 19.16 summarizes port H data register read/write operations. PHDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 679 Table 19.16 Port H Data Register (PHDR) Read/Write Operations Bits 15 to 0: PHIOR Pin Function Read Write 0 General input Pin state Value is written to PHDR, but does not affect pin state Other than general input Pin state Value is written to PHDR, but does not affect pin state General output PHDR value Write value is output from pin (POD pin = high) 1 High impedance regardless of PHDR value (POD pin = low) Other than general output 680 PHDR value Value is written to PHDR, but does not affect pin state 19.10 Port J Port J is an input/output port with the 16 pins shown in figure 19.9. PJ15 (I/O) /TI9F (input) PJ14 (I/O) /TI9E (input) PJ13 (I/O) /TI9D (input) PJ12 (I/O) /TI9C (input) PJ11 (I/O) /TI9B (input) PJ10 (I/O) /TI9A (input) PJ9 (I/O) /TIO5D (I/O) PJ8 (I/O) /TIO5C (I/O) Port J PJ7 (I/O) /TIO2H (I/O) PJ6 (I/O) /TIO2G (I/O) PJ5 (I/O) /TIO2F (I/O) PJ4 (I/O) /TIO2E (I/O) PJ3 (I/O) /TIO2D (I/O) PJ2 (I/O) /TIO2C (I/O) PJ1 (I/O) /TIO2B (I/O) PJ0 (I/O) /TIO2A (I/O) Figure 19.9 Port J 19.10.1 Register Configuration The port J register configuration is shown in table 19.17. Table 19.17 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port J data register PJDR R/W H'0000 H'FFFFF76C 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 681 19.10.2 Port J Data Register (PJDR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PJ15 DR PJ14 DR PJ13 DR PJ12 DR PJ11 DR PJ10 DR PJ9 DR PJ8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PJ7 DR PJ6 DR PJ5 DR PJ4 DR PJ3 DR PJ2 DR PJ1 DR PJ0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port J data register (PJDR) is a 16-bit readable/writable register that stores port J data. Bits PJ15DR to PJ0DR correspond to pins PJ15/TI9F to PJ0/TIO2A. When a pin functions as a general output, if a value is written to PJDR, that value is output directly from the pin, and if PJDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PJDR is read the pin state, not the register value, is returned directly. If a value is written to PJDR, although that value is written into PJDR it does not affect the pin state. Table 19.18 summarizes port J data register read/write operations. PJDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Table 19.18 Port J Data Register (PJDR) Read/Write Operations Bits 15 to 0: PJIOR Pin Function Read Write 0 General input Pin state Value is written to PJDR, but does not affect pin state Other than general input Pin state Value is written to PJDR, but does not affect pin state General output PJDR value Write value is output from pin Other than general output PJDR value Value is written to PJDR, but does not affect pin state 1 682 19.11 Port K Port K is an input/output port with the 16 pins shown in figure 19.10. PK15 (I/O) /TO8P (output) PK14 (I/O) /TO8O (output) PK13 (I/O) /TO8N (output) PK12 (I/O) /TO8M (output) PK11 (I/O) /TO8L (output) PK10 (I/O) /TO8K (output) PK9 (I/O) /TO8J (output) PK8 (I/O) /TO8I (output) Port K PK7 (I/O) /TO8H (output) PK6 (I/O) /TO8G (output) PK5 (I/O) /TO8F (output) PK4 (I/O) /TO8E (output) PK3 (I/O) /TO8D (output) PK2 (I/O) /TO8C (output) PK1 (I/O) /TO8B (output) PK0 (I/O) /TO8A (output) Figure 19.10 Port K 19.11.1 Register Configuration The port K register configuration is shown in table 19.19. Table 19.19 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port K data register PKDR R/W H'0000 H'FFFFF778 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 683 19.11.2 Port K Data Register (PKDR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PK15 DR PK14 DR PK13 DR PK12 DR PK11 DR PK10 DR PK9 DR PK8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PK7 DR PK6 DR PK5 DR PK4 DR PK3 DR PK2 DR PK1 DR PK0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port K data register (PKDR) is a 16-bit readable/writable register that stores port K data. Bits PK15DR to PK0DR correspond to pins PK15/TO8P to PK0/TO8A. When a pin functions as a general output, if a value is written to PKDR, that value is output directly from the pin, and if PKDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PKDR is read the pin state, not the register value, is returned directly. If a value is written to PKDR, although that value is written into PKDR it does not affect the pin state. Table 19.20 summarizes port K data register read/write operations. PKDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Table 19.20 Port K Data Register (PKDR) Read/Write Operations Bits 15 to 0: PKIOR Pin Function Read Write 0 General input Pin state Value is written to PKDR, but does not affect pin state Other than general input Pin state Value is written to PKDR, but does not affect pin state General output PKDR value Write value is output from pin Other than general output PKDR value Value is written to PKDR, but does not affect pin state 1 684 19.12 POD (Port Output Disable) Control The output port drive buffers for the address bus pins (A20 to A0) and data bus pins (D15 to D0) can be controlled by the POD (port output disable) pin input level. However, this function is enabled only when the address bus pins (A20 to A0) and data bus pins (D15 to D0) are designated as general output ports. Output buffer control by means of POD is performed asynchronously from bus cycles. POD Address Bus Pins (A20 to A0) and Data Bus Pins (D15 to D0) (when designated as output ports) 0 Enabled (high-impedance) 1 Disabled (general output) 685 686 Section 20 ROM (SH7052F/SH7053F) 20.1 Features The SH7052F/SH7053F has 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can be performed. To erase the entire flash memory, individual blocks must be erased in turn. Block erasing can be performed as required on 4 kB, 32 kB, and 64 kB blocks. • Programming/erase times The flash memory programming time is 7 ms (typ.) for simultaneous 128-byte programming, equivalent to 55 µs (typ.) per byte, and the erase time is 100 ms (typ.) per block. • Reprogramming capability The flash memory can be reprogrammed up to 100 times. • On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: • • • • Boot mode User program mode Automatic bit rate adjustment With data transfer in boot mode, the SH7052F/SH7053F’s bit rate can be automatically adjusted to match the transfer bit rate of the host. Flash memory emulation in RAM Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory. Protect modes There are two protect modes, hardware and software, which allow protected status to be designated for flash memory program/erase/verify operations. Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. 687 20.2 Overview 20.2.1 Block Diagram Internal address bus Module bus Internal data bus (32 bits) FLMCR1 FLMCR2 EBR1 Bus interface/controller Operating mode EBR2 RAMER Flash memory (256 kB) Legend FLMCR1: FLMCR2: EBR1: EBR2: RAMER: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Figure 20.1 Block Diagram of Flash Memory 688 FWE pin Mode pin 20.2.2 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 20.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. MD1 = 1, MD2 = 1, FWE = 0 *1 Reset state RES = 0 User mode RES = 0 MD1 = 1, MD2 = 1, FWE = 1 FWE = 1 FWE = 0 User program mode *2 RES = 0 MD1 = 0, MD2 = 1, FWE = 1 RES = 0 Programmer mode *1 Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. MD0 = 1, MD1 = 1, MD2 = 0 Figure 20.2 Flash Memory State Transitions 689 20.2.3 On-Board Programming Modes Boot Mode 2. Programming control program transfer When boot mode is entered, the boot program in the SH7052F, SH7053F (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. ; ; ;;;; 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. Host Host Programming control program New application program New application program SH7052F, SH7053F SH7052F, SH7053F SCI Boot program Flash memory SCI Boot program Flash memory RAM RAM Boot program area Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Programming control program 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host Host New application program SH7052F, SH7053F SH7052F, SH7053F SCI Boot program Flash memory RAM Flash memory Boot program area Flash memory preprogramming erase Programming control program SCI Boot program RAM Boot program area New application program Programming control program Program execution state Figure 20.3 Boot Mode 690 User Program Mode 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. ;;;; ;; 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Host Programming/ erase control program New application program New application program SH7052F, SH7053F SH7052F, SH7053F SCI Boot program Flash memory RAM SCI Boot program Flash memory RAM FWE assessment program FWE assessment program Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host Host New application program SH7052F, SH7053F SH7052F, SH7053F SCI Boot program Flash memory RAM FWE assessment program Flash memory RAM FWE assessment program Transfer program Transfer program Programming/ erase control program Flash memory erase SCI Boot program Programming/ erase control program New application program Program execution state Figure 20.4 User Program Mode 691 20.2.4 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. User Mode • User Program Mode SCI Flash memory RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Emulation block Figure 20.5 Emulation When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. 692 • User Program Mode SCI RAM Flash memory Overlap RAM (programming data) Programming control program execution state Application program Programming data Figure 20.6 Programming Flash Memory 20.2.5 Differences between Boot Mode and User Program Mode Table 20.1 Differences between Boot Mode and User Mode Boot Mode User Program Mode Total erase Yes Yes Block erase No Yes Programming control program* (2) (1) (2) (3) (1) Erase/erase-verify (2) Program/program-verify (3) Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. 693 20.2.6 Block Configuration The flash memory is divided into three 64 kB blocks, one 32 kB block, and eight 4 kB blocks. Address H'3FFFF 64 kB 64 kB 256 kB 64 kB 32 kB 4 kB × 8 Address H'00000 Figure 20.7 Block Configuration 20.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 20.2. Table 20.2 Pin Configuration Pin Name Abbreviation I/O Function Reset RES Input Reset Flash write enable FWE Input Flash program/erase protection by hardware Mode 2 MD2 Input Sets SH7052F/SH7053F operating mode Mode 1 MD1 Input Sets SH7052F/SH7053F operating mode Mode 0 MD0 Input Sets SH7052F/SH7053F operating mode Transmit data TxD1 Output Serial transmit data output Receive data RxD1 Input Serial receive data input 694 20.4 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 20.3. Table 20.3 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Flash memory control register 1 FLMCR1 R/W* H'00* H'FFFFE800 8 Flash memory control register 2 FLMCR2 R/W*1 H'00 H'FFFFE801 8 Erase block register 1 EBR1 R/W*1 H'00* 3 H'FFFFE802 8 EBR2 R/W*1 H'00* 4 Erase block register 2 H'FFFFE803 8 RAM emulation register RAMER R/W H'0000 H'FFFFEC26 8, 16, 32 1 2 Notes: 1. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are also disabled when the FWE bit is set to 1 in FLMCR1. 2. When a high level is input to the FWE pin, the initial value is H'80. 3. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in FLMCR1 is not set, these registers are initialized to H'00. 4. Will be initialized to H'00 if a low level is input to pin FWE or if bit SWE2 of FLMCR2 is not set even though a high level is input. 5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers, and RAMER is a 16-bit register. 6. Only byte accesses are valid for FLMCR1, FLMCR2, EBR1, and EBR2, the access requiring 3 cycles. Three cycles are required for a byte or word access to RAMER, and 6 cycles for a longword access. 695 20.5 Register Descriptions 20.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE1 bit to 1 when FWE = 1, then setting the EV1 or PV1 bit. Program mode is entered by setting SWE1 bit to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the P1 bit. Erase mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a power-on reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are enabled only in the following cases: Writes to bit SWE1 of FLMCR1 enabled when FWE = 1, to bits ESU1, PSU1, EV1, and PV1 when FWE = 1 and SWE1 = 1, to bit E1 when FWE = 1, SWE1 = 1 and ESU1 = 1, and to bit P1 when FWE = 1, SWE1 = 1, and PSU1 = 1. Bit: 7 6 5 4 3 2 1 0 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 Initial value: 1/0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W • Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7: FWE Description 0 When a low level is input to the FWE pin (hardware-protected state) 1 When a high level is input to the FWE pin • Bit 6—Software Write Enable Bit 1 (SWE1): Enables or disables flash memory programming and erasing. Set this bit when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 3 to 0 of EBR2. Bit 6: SWE1 Description 0 Writes disabled 1 Writes enabled [Setting condition] When FWE = 1 696 (Initial value) • Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same time. Bit 5: ESU1 Description 0 Erase setup cleared 1 Erase setup (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 • Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit at the same time. Bit 4: PSU1 Description 0 Program setup cleared 1 Program setup (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 • Bit 3—Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time. Bit 3: EV1 Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 • Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2: PV1 Description 0 Program-verify mode cleared 1 Transition to program-verify mode (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 697 • Bit 1—Erase 1 (E1): Selects erase mode transition or clearing. Do not set the SWE1, ESU1, PSU1, EV1, PV1, or P1 bit at the same time. Bit 1: E1 Description 0 Erase mode cleared 1 Transition to erase mode (Initial value) [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 • Bit 0—Program 1 (P1): Selects program mode transition or clearing. Do not set the SWE1, PSU1, ESU1, EV1, PV1, or E1 bit at the same time. Bit 0: P1 Description 0 Program mode cleared 1 Transition to program mode (Initial value) [Setting condition] When FWE = 1, SWE1 = 1, and PSU1 = 1 20.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a status register that indicates the occurrence of an error during flash memory programming or erasing. FLMCR2 is initialized to H’00 by a power-on reset and in hardware standby mode. When on-chip flash memory is disabled, a read will return H’00 and writes are invalid. Bit: 698 7 6 5 4 3 2 1 0 FLER Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R • Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. Bit 7: FLER Description 0 Flash memory is operating normally (Initial value) Flash memory program/erase protection (error protection) is disabled [Clearing condition] Power-on reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See 20.8.3 Error Protection • Bits 6 to 0—Reserved: These bits always read 0. The write value should always be 0. 20.5.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit. (Do not set more than one bit, as this will automatically clear both EBR1 and EBR2 to 0.) When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 20.4. Bit: Initial value: R/W: 20.5.4 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin. Bits 3 to 0 will be initialized to 0 if bit SWE1 is not set, even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding 699 block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit. (Do not set more than one bit, as this will automatically clear both EBR1 and EBR2 to 0.) When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 20.5. Bit: 7 6 5 4 3 2 1 0 EB11 EB10 EB9 EB8 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W Table 20.4 Flash Memory Erase Blocks Block (Size) Addresses EB0 (4 kB) H'000000 to H'000FFF EB1 (4 kB) H'001000 to H'001FFF EB2 (4 kB) H'002000 to H'002FFF EB3 (4 kB) H'003000 to H'003FFF EB4 (4 kB) H'004000 to H'004FFF EB5 (4 kB) H'005000 to H'005FFF EB6 (4 kB) H'006000 to H'006FFF EB7 (4 kB) H'007000 to H'007FFF EB8 (32 kB) H'008000 to H'00FFFF EB9 (64 kB) H'010000 to H'01FFFF EB10 (64 kB) H'020000 to H'02FFFF EB11 (64 kB) H'030000 to H'03FFFF 700 20.5.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 20.5. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — RAMS RAM2 RAM1 RAM0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W • Bits 15 to 4—Reserved: These bits always read 0. The write value should always be 0. • Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 3: RAMS Description 0 Emulation not selected (Initial value) Program/erase-protection of all flash memory blocks is disabled 1 Emulation selected Program/erase-protection of all flash memory blocks is enabled 701 • Bits 2 to 0—Flash Memory Area Selection (RAM2, RAM1, RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 22.5.) Table 20.5 Flash Memory Area Divisions Addresses RAMS RAM1 RAM1 RAM0 H'FFFF8000 to H'FFFF8FFF RAM area 4 kB 0 * * * H'00000000 to H'00000FFF EB0 (4 kB) 1 0 0 0 H'00001000 to H'00001FFF EB1 (4 kB) 1 0 0 1 H'00002000 to H'00002FFF EB2 (4 kB) 1 0 1 0 H'00003000 to H'00003FFF EB3 (4 kB) 1 0 1 1 H'00004000 to H'00004FFF EB4 (4 kB) 1 1 0 0 H'00005000 to H'00005FFF EB5 (4 kB) 1 1 0 1 H'00006000 to H'00006FFF EB6 (4 kB) 1 1 1 0 H'00007000 to H'00007FFF EB7 (4 kB) 1 1 1 1 *: Don't care 702 Block Name 20.6 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 20.6. For a diagram of the transitions to the various flash memory modes, see figure 20.2. Table 20.6 Setting On-Board Programming Modes Mode Boot mode Expanded mode PLL Multiple FWE MD2 MD1 MD0 ×4 1 1 0 0 1 0 1 1 1 0 1 1 1 Single-chip mode User program mode 20.6.1 Expanded mode Single-chip mode 1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI channel to be used is set to asynchronous mode. When a reset-start is executed after the SH7052F/SH7053F’s pins have been set to boot mode, the boot program built into the SH7052F/SH7053F is started and the programming control program prepared in the host is serially transmitted to the SH7052F/SH7053F via the SCI. In the SH7052F/SH7053F, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 20.8, and the boot mode execution procedure in figure 20.9. 703 SH7052F, SH7053F Flash memory Host Write data reception Verify data transmission RXD1 SCI1 TXD1 Figure 20.8 System Configuration in Boot Mode 704 On-chip RAM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate SH7052F and SH7053F measure low period of H'00 data transmitted by host SH7052F and SH7053F calculate bit rate and sets value in bit rate register After bit rate adjustment, SH7052F and SH7053F transmit one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, SH7052F and SH7053F transmit one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte SH7052F and SH7053F transmit received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units SH7052F and SH7053F transmit received programming control program to host as verify data (echo-back) n+1→n Transfer received programming control program to on-chip RAM No n = N? Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, SH7052F and SH7053F transmit one H'AA data byte to host Execute programming control program transferred to on-chip RAM Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 20.9 Boot Mode Execution Procedure 705 Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 Stop bit D7 Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 20.10 Automatic SCI Bit Rate Ajustment When boot mode is initiated, the SH7052F/SH7053F measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The SH7052F/SH7053F calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the SH7052F/SH7053F. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the SH7052F/SH7053F’s system clock frequency, there will be a discrepancy between the bit rates of the host and the SH7052F/SH7053F. Set the host transfer bit rate at 9,600 or 19,200 bps to operate the SCI properly. Table 20.7 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the SH7052F/SH7053F bit rate is possible. The boot program should be executed within this system clock range. Table 20.7 System Clock Frequencies for which Automatic Adjustment of SH7052F/SH7053F Bit Rate is Possible Host Bit Rate System Clock Frequency for Which Automatic Adjustment of SH7052F/SH7053F Bit Rate is Possible 9,600 bps 20 to 40 MHz (input frequency: 5 to 10 MHz) 19,200 bps 20 to 40 MHz (input frequency: 5 to 10 MHz) 706 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 20.11. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. H'FFFF8000 Boot program area ( 2 kbytes) H'FFFF8000 Boot program area ( 2 kbytes) H'FFFF87FF Programming control program area (10 kbytes) H'FFFF87FF Programming control program area (14 kbytes) H'FFFFAFFF SH7052F H'FFFFBFFF SH7053F Figure 20.11 RAM Areas in Boot Mode Note: The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note also that the boot program remains in this area of the on-chip RAM even after control branches to the programming control program. 707 20.6.2 User Program Mode After setting FWE, the user should branch to, and execute, the previously prepared programming/erase control program. Use the following procedure (figure 20.12) to execute the programming control program that writes to flash memory (when transferred to RAM). 1 Write FWE assessment program and transfer program 2 FWE = 1 (user program mode) 3 Transfer programming/erase control program to RAM 4 Execute programming/ erase control program in RAM (flash memory rewriting) 5 Execute user application program Figure 20.12 User Program Mode Execution Procedure Note: When programming and erasing, start the watchdog timer so that measures can be taken to prevent program runaway, etc. Memory cells may not operate normally if overprogrammed or overerased due to program runaway. 20.7 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1. The flash memory cannot be read while it is being written or erased. Install the program to control flash memory programming and erasing (programming control program) in the on-chip RAM, in 708 external memory, or in flash memory outside the address area, and execute the program from there. Notes: 1. Operation is not guaranteed if bits SWE1, ESU1, PSU1, EV1, PV1, E1, and P1 of FLMCR1 are set/reset by a program in flash memory in the corresponding address areas. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Programming should be performed in the erased state. Do not perform additional programming on previously programmed addresses. 20.7.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figures 20.13 and 20.14 should be followed. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. Following the elapse of 10 µs or more after the SWE1 bit is set to 1 in flash memory control register 1 (FLMCR1), 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the program data area in RAM is written consecutively to the program address (the lower 8 bits of the first address written to must be H'00 or H'80). 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU1 bit in FLMCR1, and after the elapse of tSPSU, the operating mode is switched to program mode by setting the P1 bit in FLMCR1. The time during which the Pn bit is set is the flash memory programming time. Follow the table in the programming flowchart for the write time. After the elapse of a given programming time, programming mode is exited. In exiting programming mode, the P1 bit in FLMCR1 is cleared, then after an interval of tCP or longer the PSU1 bit is cleared, and after an interval of tCPSU or longer the watchdog timer is halted. 709 20.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. A transition to program-verify mode is made by setting the PV1 bit in FLMCR1 and waiting for an interval of t SPV. Before reading in program-verify mode, perform a dummy write of H'FF data to the read addresses, and then wait for an interval of tSPVR or longer. When the flash memory is read in this state (verify data is read in longword units), the data at the latched address is read. Next, the written data is compared with the verify data, and reprogram data is computed (see figures 20.13 and 20.14) and transferred to the reprogram data area. After 128 bytes of data have been verified, exit program-verify mode. Program-verify mode is exited by clearing the PV1 bit in FLMCR1, then clearing the SWEn bit after an interval of tCPV or longer, and waiting for an interval of tCSWE or longer. If reprogramming is necessary, set program mode again, and repeat the program/programverify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than 1,000 times on the same bits. 710 Start Data writes must be performed in the memory-erased state. Do not write additional data to an address to which data is already written. Set SWE1 bit in FLMCR1 Wait: tSSWE Store 128 bytes program data in program data area and reprogram data area *4 n=1 m=0 Successively write 128-byte data from reprogram data area in RAM to flash memory *1 Subroutine call See Note 6 for pulse width Write Pulse (tSP30 or tSP200) Set PV1 bit in FLMCR1 Wait: tSPV Perform H'FF dummy-write to verify address Wait: tSPVR Increment address Read verify data n←n+1 *2 Write data = verify data? No m=1 Yes No 6 ≥ n? Yes Compute additional-programming data No Transfer additional-programming data to additional-programming data area *4 Compute reprogram data *3 Transfer reprogram data to reprogram data area *4 128 byte data verify complete? Yes Clear PV1 bit in FLMCR1 Wait: tCPV No 6 ≥ n? Yes Successively write 128-byte data from additionalprogramming data area in RAM to flash memory *1 Subroutine call Write Pulse (tSP10) m = 0? Yes No n ≥ 1000? No Yes Clear SWE1 bit in FLMCR1 Clear SWE1 bit in FLMCR1 Wait: tCSWE Wait: tCSWE Programming end Programming failure Figure 20.13 Program/Program-Verify Flowchart (1) 711 Subroutine: Write Pulse Notes: 1. Transfer data in byte units. The lower eight bits of the start address to which data is written must be H'00 or H'80. Transfer 128-byte data even when writing fewer than 128 bytes. In this case, Set H'FF in unused addresses. 2. Read verify data in longword form (32 bits). 3. Even for bits to which data has already been written in the 128byte programming loop, an additional write should be performed if the next verify write data is not the same as the verify data. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data must be provided in RAM. The reprogram and additional program data contents are modified as programming proceeds. 5. A write pulse of tSP30 or tSP200 is applied according to the progress of the programming operation. See Note 6 for the pulse widths. When writing of the additional program data is executed, a tSP10 write pulse should be applied. Reprogram data X' means reprogram data when the pulse is applied. 6. Write Pulse Width Start of subroutine Enable WDT Set PSU1 bit in FLMCR1 Wait: tSPSU Set P1 bit in FLMCR1 Wait: tSP10, tSP30, or tSP200 *5 Clear P1 bit in FLMCR1 Wait: tCP Clear PSU1 bit in FLMCR1 Wait: tCPSU Number of Writes n Disable WDT Return Write Time (z)µsec 1 tSP30 2 tSP30 3 tSP30 4 tSP30 5 tSP30 6 tSP30 7 tSP200 8 tSP200 9 tSP200 10 tSP200 Reprogram data storage area (128 bytes) 11 tSP200 12 tSP200 Additional program data storage area (128 byte) 13 . . . tSP200 . . . 998 tSP200 999 tSP200 1000 tSP200 RAM Program data storage area (128 bytes) Note: Use a tSP10 write pulse for additional programming. Reprogram Data Computation Table Original Data (D) Verify Data (V) Reprogram Data (X) 0 0 1 0 1 0 Programming is incomplete; reprogramming should be performed. 1 0 1 — 1 1 1 Left in the erased state. Comments Programming complete. Additional-Programming Data Computation Table Reprogram Data (X') Verify Data Additional-Programming (V) Data (Y) Comments 0 0 0 Additional programming executed 0 1 1 Additional programming not executed 1 0 1 Additional programming not executed 1 1 1 Additional programming not executed Figure 20.14 Program/Program-Verify Flowchart (2) 712 Table 20.8 Program/Program-Verify Parameter Flow Section Item Symbol Min Typ Max Unit t SPSU 50 50 — µs Wait time after P1 bit setting (10µs) t SP10 8 10 12 µs Additionalprogramming time wait Wait time after P1 bit setting (30µs) t SP30 28 30 32 µs Programming time wait Wait time after P1 bit setting (200µs) t SP200 198 200 202 µs Programming time wait Wait time after P1 bit clearing t CP 5 5 — µs Wait time after PSU1 bit clearing t CPSU 5 5 — µs Wait time after PV1 bit setting t SPV 4 4 — µs Wait time after dummy write t SPVR 2 2 — µs Wait time after PV1 bit clearing t CPV 2 2 — µs Wait time after SWE1 bit setting t SSWE 1 1 — µs Wait time after SWE1 bit clearing t CSWE 100 100 — µs Program/ Wait time after PSU1 bit program-verify setting All 20.7.3 Notes Erase Mode When erasing flash memory, the erase/erase-verify flowchart (single-block erase) shown in figure 20.15 should be followed for each block. To perform data or program erasure, set the SWE1 bit to 1 in flash memory control register n (FLMCR1), then, after an interval of tSSWE or longer, make a 1-bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1, EBR2). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set 19.8 ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU1 bit in FLMCR1, and after an interval of tSESU or longer, the operating mode is switched to erase mode by setting the E1 bit in FLMCR1. The time during which the E1 bit is set is the flash memory erase time. Ensure that the erase time does not exceed tSE. 713 After the elapse of the erase time, erase mode is exited. In exiting erase mode, the E1 bit in FLMCR1 is cleared, then after an interval of t CE or longer the ESU1 bit is cleared, and after a further interval of tCESU or longer the watchdog timer is halted. Note: With flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all “0”) is not necessary before starting the erase procedure. 20.7.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. A transition to erase-verify mode is made by setting the E1 bit in FLMCR1 and waiting for an interval of t SEV. Before reading in erase-verify mode, perform a dummy write of H'FF data to the read addresses, and then wait for an interval of tSEVR or longer. When the flash memory is read in this state (verify data is read in longword units), the data at the latched address is read. If the read data has been erased (all “1”), a dummy write is performed to the next address, and erase-verify is performed. If there are any unerased blocks, make a 1-bit setting for the flash memory area to be erased, and repeat the erase/erase-verify sequence as before. Ensure that the operation is not repeated more than 100 times. When verification is completed, exit erase-verify mode. Eraseverify mode is exited by clearing the EV1 bit in FLMCR1, then waiting for an interval of tCEV or longer. If erasure has been completed on all the erase blocks, clear the SWE1 bit in FLMCR1. If there are any unerased blocks, make a 1-bit setting for the flash memory area to be erased, and repeat the erase/erase-verify sequence as before. 714 Start Erasing must be performed in block units. *1 Set SWE1 bit in FLMCR1 Wait: tSSWE n=1 Set EBR1 and EBR2 *3 Enable WDT Set ESU1 bit in FLMCR1 Wait: tSESU Set E1 bit in FLMCR1 Wait: tSE Clear E1 bit in FLMCR1 Wait: tCE Clear ESU1 bit in FLMCR1 Wait: tCESU Disable WDT n←n+1 Set EV1 bit in FLMCR1 Wait: tSEV Set block start address to verify address H'FF dummy write to verify address Wait: tSEVR Read verify data Increment address Verify data = all "1"? *2 NG OK NG NG Notes: 1. 2. 3. 4. Last address of block? OK Clear EV1 bit in FLMCR1 Clear EV1 bit in FLMCR1 Wait: tCEV Wait: tCEV *4 End of erasing of all erase blocks? n ≥ 100? OK Clear SWE1 bit in FLMCR1 OK Clear SWE1 bit in FLMCR1 Wait: tCSWE Wait: tCSWE End of erasing Erase failure NG Preprogramming (setting erase block data to all "0") is not necessary. Verify data is read in 32-bit (longword) units. Set only one bit in EBR1 and EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn. Figure 20.15 Erase/Erase-Verify Flowchart 715 Table 20.9 Erase/Erase-Verify Parameter Flow Section Item Symbol Min Typ Max Unit Erase/ erase-verify Wait time after ESU1 bit setting t SESU 100 100 — µs Wait time after E1 bit setting t SE 10 10 100 ms Wait time after E1 bit clearing t CE 10 10 — µs Wait time after ESU1 bit clearing t CESU 10 10 — µs Wait time after EV1 bit setting t SEV 20 20 — µs Wait time after dummy write t SEVR 2 2 — µs Wait time after EV1 bit clearing t CEV 4 4 — µs Wait time after SWE1 bit setting t SSWE 1 1 — µs Wait time after SWE1 bit clearing t CSWE 100 100 — µs All 716 Notes Erase time wait 20.8 Protection There are two kinds of flash memory program/erase protection, hardware protection and software protection. 20.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), erase block register 1 (EBR1), and erase block register 2 (EBR2). The FLMCR1, EBR1, and EBR2 settings are retained in the error-protected state. (See table 20.10.) Table 20.10 Hardware Protection Functions Item Description Program Erase FWE pin protection • When a low level is input to the FWE pin, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/eraseprotected state is entered. Yes Yes Reset/standby protection • In a power-on reset (including a WDT power-on reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/eraseprotected state is entered. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. Do not execute a reset during programming or erasing, as the values in the flash memory are not guaranteed if this is done. In this case, execute an erase, then execute programming once again. Yes Yes • 717 20.8.2 Software Protection Software protection can be implemented by setting the SWE1 bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), does not cause a transition to program mode or erase mode. (See table 20.11.) Table 20.11 Software Protection Functions Item Description Program Erase SWE bit protection • Setting bit SWE1 in FLMCR1 to 0 sets the program/erase-protected state. (Execute the program in the on-chip RAM, external memory.) Yes Yes Block specification protection • Erase protection can be set for individual blocks by settings in erase block register 1 (EBR1) and erase block register 2 (EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. — Yes Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. Yes Yes • Emulation protection • 20.8.3 Error Protection In error protection, an error is detected when SH7052F/SH7053F runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the SH7052F/SH7053F malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1 or E1 bit. However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: 1. When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) 718 2. When a SLEEP instruction (including software standby) is executed during programming/erasing Error protection is released only by a power-on reset and in hardware standby mode. Figure 20.16 shows the flash memory state transition diagram. Program mode Erase mode Reset or standby (hardware protection) RES = 0 or HSTBY = 0 RD VF PR ER FLER = 0 RD VF PR ER FLER = 0 Error occurrence (software standby) RES = 0 or HSTBY = 0 Error occurrence RES = 0 or HSTBY = 0 Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2, EBR1, EBR2 initialization state Legend RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 20.16 Flash Memory State Transitions 719 20.9 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses cannot be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 20.17 shows an example of emulation of real-time flash memory programming. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 20.17 Flowchart for Flash Memory Emulation in RAM 720 This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFFF8000 H'FFFF8FFF Flash memory EB8 to EB11 On-chip RAM H'FFFFAFFF(SH7052F) H'FFFFBFFF(SH7053F) H'3FFFF Figure 20.18 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB0 is Overlapped 1. Set bits RAMS and RAM2 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the area (EB0) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1) will not cause a transition to program mode or erase mode. When actually programming or erasing a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 721 20.10 Note on Flash Memory Programming/Erasing In the on-board programming modes (user mode and user program mode), NMI input should be disabled to give top priority to the program/erase operations (including RAM emulation). Do not perform a write to a ROM area immediately after an ATU register write cycle. For details, see “Writing to ROM Area Immediately after ATU Register Write” in section 10.7, Usage Notes. When reading flash memory after changing the SWE1 bit from 1 to 0 on completion of a program/erase operation, wait for at least t CSWE after clearing SWE1 to 0 before executing the flash memory read. Regarding the timing of RES input after changing the SWE1 bit from 1 to 0 on completion of a program/erase operation, wait for at least tCSWE after clearing SWE1 to 0 before executing the reset operation. 20.11 Flash Memory Programmer Mode Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, flash memory read mode, auto-program mode, autoerase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. In programmer mode, set the mode pins to programmer mode (see table 20.12) and input a 6 MHz input clock, so that the SH7052F/SH7053F runs at 24 MHz. Table 20.12 shows the pin settings for programmer mode. For the pin names in programmer mode, see section 1.3.2, Pin Functions. Table 20.12 PROM Mode Pin Settings Pin Names Settings Mode pins: MD2, MD1, MD0 0, 1, 1 FWE pin High level input (in auto-program and auto-erase modes) RES pin Power-on reset circuit XTAL, EXTAL, PLLVCC, PLLCAP, PLLVSS pins Oscillator circuit 722 20.11.1 Socket Adapter Pin Correspondence Diagram Connect the socket adapter to the chip as shown in figure 20.20. This will enable conversion to a 40-pin arrangement. The on-chip ROM memory map is shown in figure 20.19, and the socket adapter pin correspondence diagram in figure 20.20. Addresses in MCU mode Addresses in programmer mode H'00000000 H'00000 On-chip ROM space 256 kB H'0003FFFF H'3FFFF Figure 20.19 On-Chip ROM Memory Map 723 SH7052F and SH7053F Socket Adapter (Conversion to 40-Pin Arrangement) HN27C4096HG (40 Pins) Pin No. Pin Name Pin No. Pin Name 188 A0 21 A0 189 A1 22 A1 190 A2 23 A2 191 A3 24 A3 192 A4 25 A4 193 A5 26 A5 195 A6 27 A6 197 A7 28 A7 198 A8 29 A8 199 A9 31 A9 200 A10 32 A10 201 A11 33 A11 202 A12 34 A12 203 A13 35 A13 204 A14 36 A14 206 A15 37 A15 208 A16 38 A16 1 A17 39 A17 2 A18 10 A18 35 D0 19 I/O0 36 D1 18 I/O1 37 D2 17 I/O2 38 D3 16 I/O3 39 D4 15 I/O4 40 D5 14 I/O5 41 D6 13 I/O6 43 D7 12 I/O7 119 CE 2 CE 121 OE 20 OE 120 WE 3 WE 28 FWE 4 FWE 1,40 VCC 11,30 VSS 10, 13, 14, 17, 19, 22, 23, 27, 29, 42, 53 54, 74, 79, 95, 115, 123, 131, 141, 158, VCC 174, 183, 194, 205 12, 15, 18, 21, 25, 31, 44, 55, 76, 81, 97, 117, 125, 133, 143, 160, 176, 185, VSS 5,6,7 NC 8 A20 9 A19 196, 207 30 RES 26 XTAL 24 EXTAL 32 PLL VCC 33 PLLCAP 34 PLL VSS Other than the above NC (OPEN) Power-on reset circuit Oscillator circuit PLL circuit Legend FWE: I/O7 to I/O0: A18 to A0: CE: OE: WE: Flash write enable Data input/output Address input Chip enable Output enable Write enable Figure 20.20 Socket Adapter Pin Correspondence Diagram 724 20.11.2 Programmer Mode Operation Table 20.13 shows how the different operating modes are set when using programmer mode, and table 20.14 lists the commands used in programmer mode. Details of each mode are given below. • Memory Read Mode Memory read mode supports byte reads. • Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. • Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-programming. • Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 20.13 Settings for Various Operating Modes In Programmer Mode Pin Names Mode FWE CE OE WE I/O7 to I/O0 A18 to A0 Read H or L L L H Data output Ain Output disable H or L L H H Hi-z X Command write H or L L H L Data input *Ain Chip disable H or L H X X Hi-z X Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. *Ain indicates that there is also address input in auto-program mode. 3. For command writes in auto-program and auto-erase modes, input a high level to the FWE pin. 725 Table 20.14 Programmer Mode Commands 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read mode 1+n Write X H'00 Read RA Dout Auto-program mode 129 Write X H'40 Write WA Din Auto-erase mode 2 Write X H'20 Write X H'20 Status read mode 2 Write X H'71 Write X H'71 Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 20.11.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. In memory read mode, command writes can be performed in the same way as in the command wait state. 3. Once memory read mode has been entered, consecutive reads can be performed. 4. After powering on, memory read mode is entered. Table 20.15 AC Characteristics in Transition to Memory Read Mode (Conditions: VCC = 3.3 V ±10%, VSS = 0 V, Ta = 25°C ±5°C) Item Symbol Min Command write cycle t nxtc 20 µs CE hold time t ceh 0 ns CE setup time t ces 0 ns Data hold time t dh 50 ns Data setup time t ds 50 ns Write pulse width t wep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns 726 Max Unit Notes Command write Memory read mode Address stable A18 to A0 tces tceh tnxtc CE OE twep tf tr WE tds tdh I/O7 to I/O0 Note: Data is latched on the rising edge of WE. Figure 20.21 Timing Waveforms for Memory Read after Memory Write Table 20.16 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Symbol Min Max Unit Command write cycle t nxtc 20 µs CE hold time t ceh 0 ns CE setup time t ces 0 ns Data hold time t dh 50 ns Data setup time t ds 50 ns Write pulse width t wep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns Notes 727 Memory read mode Other mode command write Address stable A18 to A0 tces tnxtc tceh CE OE twep tf tr WE tds tdh I/O7 to I/O0 Note: Do not enable WE and OE at the same time. Figure 20.22 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 20.17 AC Characteristics in Memory Read Mode (Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Symbol Access time Min Max Unit t acc 20 µs CE output delay time t ce 150 ns OE output delay time t oe 150 ns Output disable delay time t df 100 ns Data output hold time t oh 5 ns Address stable A18 to A0 CE VIL OE VIL WE VIH Address stable tacc tacc toh toh I/O7 to I/O0 Figure 20.23 CE and OE Enable State Read Timing Waveforms 728 Notes Address stable A18 to A0 Address stable tce tce CE toe toe OE WE VIH tacc tacc toh tdf toh tdf I/O7 to I/O0 Figure 20.24 CE and OE Clock System Read Timing Waveforms 20.11.4 Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. The lower 7 bits of the transfer address must be low. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. Memory address transfer is performed in the second cycle (figure 20.25). Do not perform transfer after the second cycle. 5. Do not perform a command write during a programming operation. 6. Perform one auto-program operation for a 128-byte block for each address. Two or more additional programming operations cannot be performed on a previously programmed address block. 7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end decision pin). 8. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. 729 Table 20.18 AC Characteristics in Auto-Program Mode (Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Symbol Min Max Unit Command write cycle t nxtc 20 µs CE hold time t ceh 0 ns CE setup time t ces 0 ns Data hold time t dh 50 ns Data setup time t ds 50 ns Write pulse width t wep 70 ns Status polling start time t wsts 1 ms Status polling access time t spa Address setup time t as 0 ns Address hold time t ah 60 ns Memory write time t write 1 Write setup time t pns 100 ns Write end setup time t pnh 100 ns WE rise time tr 30 ns WE fall time tf 30 ns 150 Notes ns 3000 ms FWE tpnh Address stable A18 to A0 tpns tces tceh tnxtc tnxtc CE OE tf twep tr tas tah twsts tspa WE tds tdh Data transfer 1 to 128 bytes twrite I/O7 Write operation end decision signal I/O6 Write normal end decision signal I/O5 to I/O0 H'40 H'00 Figure 20.25 Auto-Program Mode Timing Waveforms 730 20.11.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. Table 20.19 AC Characteristics in Auto-Erase Mode (Conditions: V CC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Symbol Min Max Unit Command write cycle t nxtc 20 µs CE hold time t ceh 0 ns CE setup time t ces 0 ns Data hold time t dh 50 ns Data setup time t ds 50 ns Write pulse width t wep 70 ns Status polling start time t ests 1 ms Status polling access time t spa Memory erase time t erase 100 Erase setup time t ens 100 ns Erase end setup time t enh 100 ns WE rise time tr 30 ns WE fall time tf 30 ns 150 ns 40000 ms Notes 731 ;;;; FWE tenh A18 to A0 tens tces tceh tnxtc tnxtc CE OE tf twep tr tests tspa WE tds terase tdh I/O7 Erase end decision signal I/O6 I/O5 to I/O0 Erase normal end decision signal H'20 H'20 H'00 Figure 20.26 Auto-Erase Mode Timing Waveforms 732 20.11.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode command write is executed. Table 20.20 AC Characteristics in Status Read Mode (Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Symbol Min Max Unit Read time after command write t nxtc 20 µs CE hold time t ceh 0 ns CE setup time t ces 0 ns Data hold time t dh 50 ns Data setup time t ds 50 ns Write pulse width t wep 70 ns OE output delay time t oe 150 ns Disable delay time t df 100 ns CE output delay time t ce 150 ns WE rise time tr 30 ns WE fall time tf 30 ns Notes ;;;; A18 to A0 tces tceh tnxtc tces tceh tnxtc tnxtc CE tce OE twep tf tr twep tf tr toe WE tds I/O7 to I/O0 tdh H'71 tds tdh tdf H'71 Note: I/O2 and I/O3 are undefined. Figure 20.27 Status Read Mode Timing Waveforms 733 Table 20.21 Status Read Mode Return Commands Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Attribute Command error Programming error Erase error — — ProgramEffective ming or address error erase count exceeded Initial value 0 0 0 0 0 0 0 Indications Normal end: 0 Command error: 1 — Count Effective exceeded: 1 address Otherwise: 0 error: 1 Normal end decision ProgramErasing — ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 Abnormal end: 1 I/O0 0 Otherwise: 0 Note: I/O2 and I/O3 are undefined. 20.11.7 Status Polling 1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. Table 20.22 Status Polling Output Truth Table Pin Name During Internal Operation Abnormal End — Normal End I/O7 0 1 0 1 I/O6 0 0 1 1 I/O0 to I/O5 0 0 0 0 20.11.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 20.23 Stipulated Transition Times to Command Wait State Item Symbol Min Standby release (oscillation stabilization time) t osc1 30 ms Programmer mode setup time t bmv 10 ms VCC hold time t dwn 0 ms 734 Max Unit Notes tosc1 tbmv Memory read mode Command Auto-program mode wait state Auto-erase mode Command wait state Normal/abnormal end decision tdwn VCC RES FWE Note: In modes other than auto-program mode and auto-erase mode, the FWE input pin should be driven low. Figure 20.28 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence 20.11.9 Notes on Memory Programming 1. When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. 2. When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be performed on previously programmed address blocks. 735 736 Section 21 ROM (SH7054F) 21.1 Features The SH7054F has 384 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can be performed. To erase the entire flash memory, individual blocks must be erased in turn. Block erasing can be performed as required on 4 kB, 32 kB, and 64 kB blocks. • Programming/erase times The flash memory programming time is 7 ms (typ.) for simultaneous 128-byte programming, equivalent to 55 µs (typ.) per byte, and the erase time is 100 ms (typ.) per block. • Reprogramming capability The flash memory can be reprogrammed up to 100 times. • On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: • • • • Boot mode User program mode Automatic bit rate adjustment With data transfer in boot mode, the SH7054F’s bit rate can be automatically adjusted to match the transfer bit rate of the host. Flash memory emulation in RAM Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory. Protect modes There are two protect modes, hardware and software, which allow protected status to be designated for flash memory program/erase/verify operations. Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. 737 21.2 Overview 21.2.1 Block Diagram Internal address bus Module bus Internal data bus (32 bits) FLMCR1 FLMCR2 EBR1 Bus interface/controller Operating mode EBR2 RAMER Flash memory (384 kB) Legend FLMCR1: FLMCR2: EBR1: EBR2: RAMER: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Figure 21.1 Block Diagram of Flash Memory 738 FWE pin Mode pin 21.2.2 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 21.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. MD1 = 1, MD2 = 1, FWE = 0 *1 Reset state RES = 0 User mode RES = 0 MD1 = 1, MD2 = 1, FWE = 1 FWE = 1 FWE = 0 User program mode *2 RES = 0 MD1 = 0, MD2 = 1, FWE = 1 RES = 0 Programmer mode *1 Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. MD0 = 1, MD1 = 1, MD2 = 0 Figure 21.2 Flash Memory State Transitions 739 21.2.3 On-Board Programming Modes Boot Mode 2. Programming control program transfer When boot mode is entered, the boot program in the SH7054F (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. ; ; ;;;; 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. Host Host Programming control program New application program New application program SH7054F SH7054F SCI Boot program Flash memory SCI Boot program Flash memory RAM RAM Boot program area Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Programming control program 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host Host New application program SH7054F SH7054F SCI Boot program Flash memory RAM Flash memory Boot program area Flash memory preprogramming erase Programming control program SCI Boot program RAM Boot program area New application program Programming control program Program execution state Figure 21.3 Boot Mode 740 User Program Mode 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. ;;;; ;; 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Host Programming/ erase control program New application program New application program SH7054F SH7054F SCI Boot program Flash memory RAM SCI Boot program RAM Flash memory FWE assessment program FWE assessment program Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host Host New application program SH7054F SH7054F SCI Boot program Flash memory RAM FWE assessment program Flash memory RAM FWE assessment program Transfer program Transfer program Programming/ erase control program Flash memory erase SCI Boot program Programming/ erase control program New application program Program execution state Figure 21.4 User Program Mode 741 21.2.4 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. User Mode • User Program Mode SCI Flash memory RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Emulation block Figure 21.5 Emulation When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. 742 • User Program Mode SCI Flash memory RAM Overlap RAM (programming data) Programming control program execution state Application program Programming data Figure 21.6 Programming Flash Memory 21.2.5 Differences between Boot Mode and User Program Mode Table 21.1 Differences between Boot Mode and User Mode Boot Mode User Program Mode Total erase Yes Yes Block erase No Yes Programming control program* (2) (1) (2) (3) (1) Erase/erase-verify (2) Program/program-verify (3) Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. 743 21.2.6 Block Configuration The flash memory is divided into five 64 kB blocks, one 32 kB block, and eight 4 kB blocks. Address H'5FFFF 64 kB 64 kB 64 kB 384 kB 64 kB 64 kB 32 kB 4 kB × 8 Address H'00000 Figure 21.7 Block Configuration 21.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 21.2. Table 21.2 Pin Configuration Pin Name Abbreviation I/O Function Reset RES Input Reset Flash write enable FWE Input Flash program/erase protection by hardware Mode 2 MD2 Input Sets SH7054F operating mode Mode 1 MD1 Input Sets SH7054F operating mode Mode 0 MD0 Input Sets SH7054F operating mode Transmit data TxD1 Output Serial transmit data output Receive data RxD1 Input Serial receive data input 744 21.4 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 21.3. Table 21.3 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Flash memory control register 1 FLMCR1 R/W* H'00* H'FFFFE800 8 Flash memory control register 2 FLMCR2 R/W*1 H'00 H'FFFFE801 8 Erase block register 1 EBR1 R/W*1 H'00* 3 H'FFFFE802 8 EBR2 R/W*1 H'00* 4 Erase block register 2 H'FFFFE803 8 RAM emulation register RAMER R/W H'0000 H'FFFFEC26 8, 16, 32 1 2 Notes: 1. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are also disabled when the FWE bit is set to 1 in FLMCR1. 2. When a high level is input to the FWE pin, the initial value is H'80. 3. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in FLMCR1 is not set, these registers are initialized to H'00. 4. Will be initialized to H'00 if a low level is input to pin FWE or if bit SWE2 of FLMCR2 is not set even though a high level is input. 5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers, and RAMER is a 16-bit register. 6. Only byte accesses are valid for FLMCR1, FLMCR2, EBR1, and EBR2, the access requiring 3 cycles. Three cycles are required for a byte or word access to RAMER, and 6 cycles for a longword access. 745 21.5 Register Descriptions 21.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE1 bit to 1 when FWE = 1, then setting the EV1 or PV1 bit. Program mode is entered by setting SWE1 bit to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the P1 bit. Erase mode is entered by setting SWE1 bit to 1 when FWE = 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a power-on reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are enabled only in the following cases: Writes to bit SWE1 of FLMCR1 enabled when FWE = 1, to bits ESU1, PSU1, EV1, and PV1 when FWE = 1 and SWE1 = 1, to bit E1 when FWE = 1, SWE1 = 1 and ESU1 = 1, and to bit P1 when FWE = 1, SWE1 = 1, and PSU1 = 1. Bit: 7 6 5 4 3 2 1 0 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 Initial value: 1/0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W • Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7: FWE Description 0 When a low level is input to the FWE pin (hardware-protected state) 1 When a high level is input to the FWE pin • Bit 6—Software Write Enable Bit 1 (SWE1): Enables or disables flash memory programming and erasing. Set this bit when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 3 to 0 of EBR2. Bit 6: SWE1 Description 0 Writes disabled 1 Writes enabled (Initial value) [Setting condition] When FWE = 1 • Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same time. 746 Bit 5: ESU1 Description 0 Erase setup cleared 1 Erase setup (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 • Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit at the same time. Bit 4: PSU1 Description 0 Program setup cleared 1 Program setup (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 • Bit 3—Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time. Bit 3: EV1 Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 • Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2: PV1 Description 0 Program-verify mode cleared 1 Transition to program-verify mode (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 747 • Bit 1—Erase 1 (E1): Selects erase mode transition or clearing. Do not set the SWE1, ESU1, PSU1, EV1, PV1, or P1 bit at the same time. Bit 1: E1 Description 0 Erase mode cleared 1 Transition to erase mode (Initial value) [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 • Bit 0—Program 1 (P1): Selects program mode transition or clearing. Do not set the SWE1, PSU1, ESU1, EV1, PV1, or E1 bit at the same time. Bit 0: P1 Description 0 Program mode cleared 1 Transition to program mode (Initial value) [Setting condition] When FWE = 1, SWE1 = 1, and PSU1 = 1 21.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a status register that indicates the occurrence of an error during flash memory programming or erasing. FLMCR2 is initialized to H'00 by a power-on reset and in hardware standby mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Bit: 748 7 6 5 4 3 2 1 0 FLER Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R • Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. Bit 7: FLER Description 0 Flash memory is operating normally (Initial value) Flash memory program/erase protection (error protection) is disabled [Clearing condition] Power-on reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See 201.8.3 Error Protection • Bits 6 to 0—Reserved: These bits always read 0. The write value should always be 0. 21.5.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit. (Do not set more than one bit, as this will automatically clear both EBR1 and EBR2 to 0.) When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 21.4. Bit: Initial value: R/W: 21.5.4 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin. Bits 3 to 0 will be initialized even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block can be erased. Other 749 blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit. (Do not set more than one bit, as this will automatically clear both EBR1 and EBR2 to 0.) When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 21.5. Bit: 7 6 5 4 3 2 1 0 EB13 EB12 EB11 EB10 EB9 EB8 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Table 21.4 Flash Memory Erase Blocks Block (Size) Addresses EB0 (4 kB) H'000000 to H'000FFF EB1 (4 kB) H'001000 to H'001FFF EB2 (4 kB) H'002000 to H'002FFF EB3 (4 kB) H'003000 to H'003FFF EB4 (4 kB) H'004000 to H'004FFF EB5 (4 kB) H'005000 to H'005FFF EB6 (4 kB) H'006000 to H'006FFF EB7 (4 kB) H'007000 to H'007FFF EB8 (32 kB) H'008000 to H'00FFFF EB9 (64 kB) H'010000 to H'01FFFF EB10 (64 kB) H'020000 to H'02FFFF EB11 (64 kB) H'030000 to H'03FFFF EB12 (64 kB) H'040000 to H'04FFFF EB13 (64 kB) H'050000 to H'05FFFF 750 21.5.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 21.5. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — RAMS RAM2 RAM1 RAM0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W • Bits 15 to 4—Reserved: These bits always read 0. • Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 3: RAMS Description 0 Emulation not selected (Initial value) Program/erase-protection of all flash memory blocks is disabled 1 Emulation selected Program/erase-protection of all flash memory blocks is enabled 751 • Bits 2, 1 and 0—Flash Memory Area Selection (RAM2, RAM1, RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 21.5.) Table 21.5 Flash Memory Area Divisions Addresses RAMS RAM1 RAM1 RAM0 H'FFFF8000 to H'FFFF8FFF RAM area 4 kB 0 * * * H'00000000 to H'00000FFF EB0 (4 kB) 1 0 0 0 H'00001000 to H'00001FFF EB1 (4 kB) 1 0 0 1 H'00002000 to H'00002FFF EB2 (4 kB) 1 0 1 0 H'00003000 to H'00003FFF EB3 (4 kB) 1 0 1 1 H'00004000 to H'00004FFF EB4 (4 kB) 1 1 0 0 H'00005000 to H'00005FFF EB5 (4 kB) 1 1 0 1 H'00006000 to H'00006FFF EB6 (4 kB) 1 1 1 0 H'00007000 to H'00007FFF EB7 (4 kB) 1 1 1 1 *: Don't care 752 Block Name 21.6 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 21.6. For a diagram of the transitions to the various flash memory modes, see figure 21.2. Table 21.6 Setting On-Board Programming Modes Mode Boot mode Expanded mode PLL Multiple FWE MD2 MD1 MD0 ×4 1 1 0 0 1 0 1 1 1 0 1 1 1 Single-chip mode User program mode 21.6.1 Expanded mode Single-chip mode 1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI channel to be used is set to asynchronous mode. When a reset-start is executed after the SH7054F’s pins have been set to boot mode, the boot program built into the SH7054F is started and the programming control program prepared in the host is serially transmitted to the SH7054F via the SCI. In the SH7054F, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 21.8, and the boot mode execution procedure in figure 21.9. 753 SH7054F Flash memory Host Write data reception Verify data transmission RXD1 SCI1 TXD1 Figure 21.8 System Configuration in Boot Mode 754 On-chip RAM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate SH7054F measures low period of H'00 data transmitted by host SH7054F calculates bit rate and sets value in bit rate register After bit rate adjustment, SH7054F transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, SH7054F transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte SH7054F transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units SH7054F transmits received programming control program to host as verify data (echo-back) n+1→n Transfer received programming control program to on-chip RAM No n = N? Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, SH7054F transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 21.9 Boot Mode Execution Procedure 755 Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) Stop bit High period (1 or more bits) Figure 21.10 Automatic SCI Bit Rate Ajustment When boot mode is initiated, the SH7054F measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The SH7054F calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the SH7054F. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the SH7054F’s system clock frequency, there will be a discrepancy between the bit rates of the host and the SH7054F. Set the host transfer bit rate at 9,600 or 19,200 bps to operate the SCI properly. Table 21.7 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the SH7054F bit rate is possible. The boot program should be executed within this system clock range. Table 21.7 System Clock Frequencies for which Automatic Adjustment of SH7054F Bit Rate is Possible Host Bit Rate System Clock Frequency for Which Automatic Adjustment of SH7054F Bit Rate is Possible 9,600 bps 20 to 40 MHz (input frequency: 5 to 10 MHz) 19,200 bps 20 to 40 MHz (input frequency: 5 to 10 MHz) 756 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 21.11. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. H'FFFF8000 Boot program area ( 2 kbytes) H'FFFF87FF Programming control program area (14 kbytes) H'FFFFBFFF Figure 21.11 RAM Areas in Boot Mode Note: The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note also that the boot program remains in this area of the on-chip RAM even after control branches to the programming control program. 757 21.6.2 User Program Mode After setting FWE, the user should branch to, and execute, the previously prepared programming/erase control program. The Flash memory cannot be read while the flash memory is being written/erased. Execute the control program for programming or erasing using the on-chip RAM, external memory, or flash memory outside the address areas. Use the following procedure (figure 21.12) to execute the programming control program that writes to flash memory (when transferred to RAM). 1 Write FWE assessment program and transfer program 2 FWE = 1 (user program mode) 3 Transfer programming/erase control program to RAM 4 Execute programming/ erase control program in RAM (flash memory rewriting) 5 Execute user application program Figure 21.12 User Program Mode Execution Procedure Note: When programming and erasing, start the watchdog timer so that measures can be taken to prevent program runaway, etc. Memory cells may not operate normally if overprogrammed or overerased due to program runaway. 758 21.7 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1. The flash memory cannot be read while it is being written or erased. Install the program to control flash memory programming and erasing (programming control program) in the on-chip RAM, in external memory, or in flash memory outside the address area, and execute the program from there. Notes: 1. Operation is not guaranteed if bits SWE1, ESU1, PSU1, EV1, PV1, E1, and P1 of FLMCR1 are set/reset by a program in flash memory in the corresponding address areas. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Programming should be performed in the erased state. Do not perform additional programming on previously programmed addresses. 21.7.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figures 21.13 and 21.14 should be followed. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. Following the elapse of 10 µs or more after the SWE1 bit is set to 1 in flash memory control register 1 (FLMCR1), 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the program data area in RAM is written consecutively to the program address (the lower 8 bits of the first address written to must be H'00 or H'80). 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU1 bit in FLMCR1, and after the elapse of tSPSU, the operating mode is switched to program mode by setting the