Renesas HD74BC540AFPEL Octal buffers/line drivers with 3 state output Datasheet

HD74BC540A
Octal Buffers/Line Drivers With 3 State Outputs
REJ03D0285–0200Z
(Previous ADE-205-031 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74BC540A provides high drivability and operation equal to or better than high speed bipolar standard logic IC
by using Bi-CMOS process. The device features low power dissipation that is about 1/5 of high speed bipolar logic IC,
when the frequency is 10 MHz. The device has eight inverter drivers with three state outputs in a 20 pin package.
When G1 and G2 is low level, this drivers set up output is enable.
Features
• Input/Output are at high impedance state when power supply is off.
• Built in input pull up circuit can make input pins be open, when not used.
• Input is TTL level.
• Wide operating temperature range
Ta = –40 to +85°C
• Ordering Information
Part Name
Package Type
HD74BC540AFPEL
Package Code
SOP-20 pin (JEITA) FP-20DAV
Package
Abbreviation
FP
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
Function Table
Inputs
G1
G2
A
Output Y
L
L
L
H
L
H
L
X
H
X
L
Z
H
X
Z
X
H
L
X
Z
:
:
:
:
High level
Low level
Immaterial
High impedance
Rev.2.00, Jul.16.2004, page 1 of 7
HD74BC540A
Pin Arrangement
G1
1
20
VCC
A1
2
19
G2
A2
3
18
Y1
A3
4
17
Y2
A4
5
16
Y3
A5
6
15
Y4
A6
7
14
Y5
A7
8
13
Y6
A8
9
12
Y7
GND
10
11
Y8
(Top view)
Absolute Maximum Ratings
Item
Symbol
Rating
Unit
Supply voltage
Input diode current
VCC
IIK
–0.5 to +7.0
±30
V
mA
Input voltage
Output voltage
VIN
VOUT
–0.5 to +7.5
–0.5 to +7.5
V
V
Off state output voltage
VOUT(off)
–0.5 to +5.5
V
Storage temperature
Tstg
–65 to +150
°C
Note: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two
of which may be realized at the same time.
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Input voltage
VCC
VIN
4.5
0
5.0
—
5.5
VCC
V
V
Ouput voltage
Operating temperature
VOUT
Topr
0
–40
—
—
VCC
85
V
°C
8
ns/V
Input rise/fall time*1
tr , tf
0
—
Note: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Rev.2.00, Jul.16.2004, page 2 of 7
HD74BC540A
Logic Diagram
G1
G2
Rev.2.00, Jul.16.2004, page 3 of 7
A1
Y1
A2
Y2
A3
Y3
A4
Y4
A5
Y5
A6
Y6
A7
Y7
A8
Y8
HD74BC540A
Electrical Characteristics (Ta = –40 to +85°C)
Item
Symbol
Input voltage
VIH
VIL
Output voltage
VOH
Input diode voltage
Input current
VCC(V)
Min
Max
Unit
Test Conditions
2.0
—
—
0.8
V
V
4.5
4.5
2.4
2.0
—
—
V
V
IOH = –3 mA
IOH = –15 mA
VOL
4.5
4.5
—
—
0.5
0.55
V
V
IOL = 48 mA
IOL = 64 mA
VIK
II
4.5
5.5
—
—
–1.2
–250
V
µA
IIN = –18 mA
VIN = 0 V
5.5
5.5
—
—
1.0
100
µA
µA
VIN = 5.5 V
VIN = 7.0 V
Short circuit output current*1
Off state output current
IOS
IOZH
5.5
5.5
–100
—
–225
50
mA
µA
VIN = 0 or 5.5 V
VO = 2.7 V
Supply current
IOZL
ICCL
5.5
5.5
—
—
–50
27.5
µA
mA
VO = 0.5 V
VIN = 0 or 5.5 V
All outputs is “L”
ICCH
5.5
—
2.5
mA
ICCZ
5.5
—
2.5
mA
VIN = 0 or 5.5 V
All outputs is “H”
VIN = 0 or 5.5 V
All outputs is “Z”
ICCT*2
5.5
—
1.5
mA
VIN = 3.4V or 0.5V
Notes: 1. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one
second.
2. When input by the TTL level, it shows ICC increase at per one input pin.
Switching Characteristics (CL = 50 pF)
Ta = 25°C
VCC = 5.0 V
Ta = –40 to +85°C
VCC = 5.0 V ±10
Item
Propagation delay time
Symbol
Min
tPLH
3.0
Max
6.0
Min
3.0
Max
7.0
Unit
Test Conditions
ns
See under figure
Output enable time
tPHL
tZH
3.0
3.0
6.0
9.0
3.0
3.0
7.0
11.0
ns
Output disable time
tZL
tHZ
3.0
3.0
9.0
8.0
3.0
3.0
11.0
10.0
ns
3.0
8.0
3.0(Typ)
3.0
—
10.0
Input capacitance
tLZ
CIN
Output capacitance
CO
15.0(Typ)
—
Rev.2.00, Jul.16.2004, page 4 of 7
pF
VIN = VCC or GND
pF
VO = VCC or GND
HD74BC540A
Test circuit
VCC
VCC
Input
Pulse
Generator
Zout = 50Ω
See Function Table
G1
Output
A1
500Ω
Y1
CL =
50 pF
G2
Notes:
1. CL includes probe and jig capacitance.
2. A2-Y2 to A8-Y8 are identical to above load circuit.
3. Open: tPLH, tPHL, tZH, tHZ
7V: tZL, tLZ
Rev.2.00, Jul.16.2004, page 5 of 7
450Ω
50Ω
Scope
*3
OPEN
7V
HD74BC540A
Waveforms-1
tf
90 %
1.5 V
Input A
tr
90 %
1.5 V
10 %
10 %
3V
0V
t PHL
t PLH
VOH
1.5 V
Output Y
1.5 V
VOL
Waveforms-2
tf
Input G
tr
90 %
1.5 V
10 %
t ZL
Waveform–A
Notes:
0V
3.5 V
1.5 V
VOL + 0.3 V
t HZ
t ZH
Waveform–B
3V
90 %
1.5 V
10 %
t LZ
1.5 V
VOH – 0.3 V
VOL
VOH
0V
1. tr = 2.5 ns, tf = 2.5 ns
2. Input waveforms: PRR = 1 MHz, duty cycle 50%
3. Waveform-A shows input conditions such that the output is “L” level when enable by the
output control.
4. Waveform-B shows input conditions such that the output is “H” level when enable by the
output control.
Rev.2.00, Jul.16.2004, page 6 of 7
HD74BC540A
Package Dimensions
As of January, 2003
Unit: mm
12.6
13 Max
11
1
10
1.27
*0.40 ± 0.06
0.10 ± 0.10
0.80 Max
*0.20 ± 0.05
2.20 Max
5.5
20
0.20
7.80 +– 0.30
1.15
0˚ – 8 ˚
0.70 ± 0.20
0.15
0.12 M
*Ni/Pd/Au plating
Rev.2.00, Jul.16.2004, page 7 of 7
Package Code
JEDEC
JEITA
Mass (reference value)
FP-20DAV
—
Conforms
0.31 g
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