To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. HD74HCT374, HD74HCT534 Octal D-type Flip-Flops (with 3-state outputs) Octal D-type Flip-Flops (with inverted 3-state outputs) REJ03D0667–0200 (Previous ADE-205-556) Rev.2.00 Mar 30, 2006 Description These device are positive edge triggered flip-flops. The difference between HD74HCT374 and HD74HCT534 is only that the former is a true outputs and the latter is a false outputs. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the clock (CK) input. When a high logic level is applied to the output control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Features • • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (Clock to Q) = 15 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name HD74HCT374P HD74HCT374FPEL HD74HCT534FPEL HD74HCT374RPEL HD74HCT534RPEL Package Type DILP-20 pin Package Code (Previous Code) PRDP0020AC-B (DP-20NEV) Package Abbreviation P — SOP-20 pin (JEITA) PRSP0020DD-B (FP-20DAV) FP EL (2,000 pcs/reel) SOP-20 pin (JEDEC) PRSP0020DC-A (FP-20DBV) RP EL (1,000 pcs/reel) PTSP0020JB-A T (TTP-20DAV) Note: Please consult the sales office for the above package availability. HD74HCT374TELL Taping Abbreviation (Quantity) TSSOP-20 pin ELL (2,000 pcs/reel) Function Table Output Control Clock D L H L L L L X H X X Notes: 1. H; High level, L; Low level, X; Irrelevant, Z; High impedance Rev.2.00 Mar 30, 2006 page 1 of 7 HD74HCT374 Q H L No change Z HD74HCT534 Q L H No change Z HD74HCT374, HD74HCT534 Pin Arrangement HD74HCT374 Output Control 1 20 VCC 1Q 2 19 8Q 1D 3 18 8D 2D 4 17 7D 2Q 5 16 7Q 3Q 6 15 6Q 3D 7 14 6D 4D 8 13 5D 4Q 9 12 5Q GND 10 11 Clock (Top view) HD74HCT534 Output Control 1 20 VCC 1Q 2 19 8Q 1D 3 18 8D 2D 4 17 7D 2Q 5 16 7Q 3Q 6 15 6Q 3D 7 14 6D 4D 8 13 5D 4Q 9 12 5Q GND 10 11 Clock (Top view) Rev.2.00 Mar 30, 2006 page 2 of 7 HD74HCT374, HD74HCT534 Logic Diagram HD74HCT374 1D 2D 3D 4D 5D 6D 7D 8D D Q D Q D Q D Q D Q D Q D Q D Q C Q C Q C Q C Q C Q C Q C Q C Q Clock Output Control 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q HD74HCT534 1D 2D 3D 4D 5D 6D 7D 8D D Q D Q D Q D Q D Q D Q D Q D Q C Q C Q C Q C Q C Q C Q C Q C Q Clock Output Control 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IOUT ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±35 ±75 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Symbol Ratings Supply voltage VCC 4.5 to 5.5 Input / Output voltage VIN, VOUT 0 to VCC Operating temperature Ta –40 to 85 Input rise / fall time*1 tr, tf 0 to 500 Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.2.00 Mar 30, 2006 page 3 of 7 Unit V V °C ns Conditions VCC = 4.5 V HD74HCT374, HD74HCT534 Electrical Characteristics Item Ta = 25°C Min Typ Max 4.5 to 5.5 2.0 — — 4.5 to 5.5 — — 0.8 4.5 4.4 — — 4.5 4.18 — — 4.5 — — 0.1 4.5 — — 0.26 5.5 — — ±0.5 Symbol VCC (V) Input voltage VIH VIL VOH Output voltage VOL Off-state output current Input current Quiescent current IOZ Iin ICC 5.5 5.5 — — — — Ta = –40 to+85°C Min Max 2.0 — — 0.8 4.4 — 4.13 — — 0.1 — 0.33 — ±5.0 ±0.1 4.0 Unit V V V Vin = VIH or VIL IOH = –20 µA IOH = –6 mA Vin = VIH or VIL IOL = 20 µA IOL = 6 mA V µA ±1.0 40 — — Test Conditions Vin = VIH or VIL, Vout = VCC or GND Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA µA µA Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Symbol VCC (V) Maximum clock frequency Propagation delay time Output enable time Output disable time Setup time Hold time Pulse width Output rise/fall time Input capacitance Ta = 25°C Ta = –40 to +85°C Typ — Max 30 Min — Max 24 Unit fmax 4.5 Min — tPLH tPHL tZL tZH tLZ tHZ tsu th tw 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 — — — — — — 20 5 16 12 15 16 15 13 16 2 0 5 28 28 30 30 30 30 — — — — — — — — — 25 6 20 35 35 38 38 38 38 — — — tTLH tTHL Cin 4.5 — 4 12 — 15 ns — — 5 10 — 10 pF Test Conditions MHz ns ns ns ns ns ns Data to clock Clock to data Clock, output control Test Circuit VCC VCC Output Pulse Generator Zout = 50 Ω Input Pulse Generator Zout = 50 Ω OC See Function Table Input 1Q to 8Q or 1Q to 8Q S1 OPEN GND CL = 50 pF VCC 1D to 8D Clock Note : 1. CL includes probe and jig capacitance. Rev.2.00 Mar 30, 2006 page 4 of 7 1 kΩ TEST tPLH / tPHL S1 OPEN tZH / tHZ tZL / tLZ GND VCC HD74HCT374, HD74HCT534 Waveforms • Waveform –1 tr tf VCC 90 % 90 % 1.3 V Input CLK 1.3 V 10 % tr 10 % tf VCC 90 % 90 % Input D 0V 10 % 10 % 0V tPHL tPLH Output Q VOH 1.3 V 1.3 V VOL Output Q • Waveform –2 tf tr VCC 90 % 90 % 1.3 V 1.3 V Input CLK 10 % tw tsu 1.3 V 10 % tw 0V th VCC Input D 1.3 V 1.3 V 0V • Waveform –3 Input OC tf tr 90 % 1.3 V 10 % VCC 90 % 1.3 V 10 % tLZ tZL 0V VOH 1.3 V Waveform - A tZH Waveform - B 10 % VOL tHZ 1.3 V 90 % VOH VOL Notes : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns 2. Waveform– A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform– B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.2.00 Mar 30, 2006 page 5 of 7 HD74HCT374, HD74HCT534 Package Dimensions JEITA Package Code P-DIP20-6.3x24.5-2.54 RENESAS Code PRDP0020AC-B Previous Code DP-20NEV MASS[Typ.] 1.26g D 11 E 20 1 10 b3 0.89 A1 A Z Reference Symbol L e1 D E A A1 bp b3 c θ e Z L θ bp e c e1 ( Ni/Pd/Au plating ) JEITA Package Code P-SOP20-7.5x12.8-1.27 RENESAS Code PRSP0020DC-A *1 Previous Code FP-20DBV Dimension in Millimeters Min Nom Max 7.62 24.50 25.40 6.30 7.00 5.08 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0° 15° 2.29 2.54 2.79 1.27 2.54 MASS[Typ.] 0.52g D F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" @ DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT @ INCLUDE TRIM OFFSET. 11 HE c *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 e *3 bp x M L1 A Z Reference Dimension in Millimeters Symbol 10 A1 θ L y Detail F Rev.2.00 Mar 30, 2006 page 6 of 7 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 12.80 13.2 7.50 0.10 0.20 0.30 2.65 0.34 0.40 0.46 0.20 0.25 0.30 0° 8° 10.00 10.40 10.65 1.27 0.12 0.15 0.935 0.40 0.70 1.27 1.45 HD74HCT374, HD74HCT534 JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B *1 Previous Code FP-20DAV MASS[Typ.] 0.31g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 20 11 *2 c E HE bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 10 e Z *3 bp x Reference Dimension in Millimeters Symbol M A L1 A1 θ y L Detail F JEITA Package Code P-TSSOP20-4.4x6.5-0.65 RENESAS Code PTSP0020JB-A *1 Previous Code TTP-20DAV D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 12.60 13.0 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 MASS[Typ.] 0.07g D F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 11 c HE *2 E bp Terminal cross section ( Ni/Pd/Au plating ) Index mark Reference Dimension in Millimeters Symbol 1 e *3 bp L1 x M A Z 10 A1 θ L y Detail F Rev.2.00 Mar 30, 2006 page 7 of 7 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 6.50 6.80 4.40 0.03 0.07 0.10 1.10 0.15 0.20 0.25 0.10 0.15 0.20 0° 8° 6.20 6.40 6.60 0.65 0.13 0.10 0.65 0.4 0.5 0.6 1.0 Sales Strategic Planning Div. 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